blob: 03d32fcab0f52f47b92b3451df99581904c2ee78 [file] [log] [blame]
Madhukar Pappireddy464f2462021-08-03 11:23:07 -05001/*
2 * Copyright 2021 The Hafnium Authors.
3 *
4 * Use of this source code is governed by a BSD-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/BSD-3-Clause.
7 */
8
9#pragma once
10
11#include <stdatomic.h>
12
13#include "hf/arch/types.h"
14
15#include "vmapi/hf/ffa.h"
16
17/**
Daniel Boulby801f8ef2022-06-27 14:21:01 +010018 * Macros for accessing the bitmap tracking interrupts.
19 */
20/* The number of bits in each element of the interrupt bitfields. */
21#define INTERRUPT_REGISTER_BITS 32
22
Daniel Boulby4ca50f02022-07-29 18:29:34 +010023struct interrupt_bitmap {
24 uint32_t bitmap[HF_NUM_INTIDS / INTERRUPT_REGISTER_BITS];
25};
Daniel Boulby801f8ef2022-06-27 14:21:01 +010026
Daniel Boulby4ca50f02022-07-29 18:29:34 +010027static inline uint32_t interrupt_bitmap_get_value(
28 struct interrupt_bitmap *bitmap, uint32_t intid)
29{
30 uint32_t index = intid / INTERRUPT_REGISTER_BITS;
31 uint32_t shift = intid % INTERRUPT_REGISTER_BITS;
32
33 return (bitmap->bitmap[index] >> shift) & 1U;
34}
35
36static inline void interrupt_bitmap_set_value(struct interrupt_bitmap *bitmap,
37 uint32_t intid)
38{
39 uint32_t index = intid / INTERRUPT_REGISTER_BITS;
40 uint32_t shift = intid % INTERRUPT_REGISTER_BITS;
41
42 bitmap->bitmap[index] |= 1U << shift;
43}
44
45static inline void interrupt_bitmap_clear_value(struct interrupt_bitmap *bitmap,
46 uint32_t intid)
47{
48 uint32_t index = intid / INTERRUPT_REGISTER_BITS;
49 uint32_t shift = intid % INTERRUPT_REGISTER_BITS;
50
51 bitmap->bitmap[index] &= ~(1U << shift);
52}
Madhukar Pappireddy3221a442023-07-24 16:10:55 -050053
54/**
Madhukar Pappireddy938faaf2023-07-31 17:56:55 -050055 * Legal values to enable or disable an interrupt through the
56 * `INT_RECONFIGURE_ENABLE` command using the `HF_INTERRUPT_RECONFIGURE`
57 * paravirtualized interface.
58 */
59#define INT_DISABLE 0
60#define INT_ENABLE 1
61
62/**
Madhukar Pappireddy464f2462021-08-03 11:23:07 -050063 * Implementation defined Encodings for various fields:
64 *
65 * Security_State:
66 * - Secure: 1
67 * - Non-secure: 0
68 *
69 * Configuration:
70 * - Edge triggered: 0
Madhukar Pappireddy1f9df612023-01-04 08:38:22 -060071 * - Level sensitive: 1
Madhukar Pappireddy464f2462021-08-03 11:23:07 -050072 * Type:
73 * - SPI: 0b10
74 * - PPI: 0b01
75 * - SGI: 0b00
76 *
77 */
Daniel Boulby18485942024-10-14 16:23:03 +010078#define INT_DESC_SEC_STATE_NS 0
79#define INT_DESC_SEC_STATE_S 1
Madhukar Pappireddy464f2462021-08-03 11:23:07 -050080
81#define INT_DESC_TYPE_SPI 2
82#define INT_DESC_TYPE_PPI 1
83#define INT_DESC_TYPE_SGI 0
84
Madhukar Pappireddy464f2462021-08-03 11:23:07 -050085struct interrupt_descriptor {
86 uint32_t interrupt_id;
87
Daniel Boulby18485942024-10-14 16:23:03 +010088 uint8_t res : 4;
89 uint8_t type : 2;
90 uint8_t config : 1;
91 uint8_t sec_state : 1;
Madhukar Pappireddy464f2462021-08-03 11:23:07 -050092 uint8_t priority;
93 bool valid;
Raghu Krishnamurthy98da1ca2022-10-04 08:59:01 -070094 bool mpidr_valid;
95 uint64_t mpidr;
Madhukar Pappireddy938faaf2023-07-31 17:56:55 -050096 bool enabled;
Madhukar Pappireddy464f2462021-08-03 11:23:07 -050097};