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Andrew Walbranb2be7c62019-08-06 14:55:29 +01001# VM interface
2
3This page provides an overview of the interface Hafnium provides to VMs. Hafnium
4makes a distinction between the 'primary VM', which controls scheduling and has
5more direct access to some hardware, and 'secondary VMs' which exist mostly to
6provide services to the primary VM, and have a more paravirtualised interface.
7The intention is that the primary VM can run a mostly unmodified operating
Andrew Walbran6e524d72019-11-12 17:36:57 +00008system (such as Linux) with the addition of a Hafnium driver which
9[fulfils certain expectations](SchedulerExpectations.md), while secondary VMs
10will run more specialised trusted OSes or bare-metal code which is designed with
11Hafnium in mind.
Andrew Walbranb2be7c62019-08-06 14:55:29 +010012
13The interface documented here is what is planned for the first release of
14Hafnium, not necessarily what is currently implemented.
15
16## CPU scheduling
17
18The primary VM will have one vCPU for each physical CPU, and control the
19scheduling.
20
21Secondary VMs will have a configurable number of vCPUs, scheduled on arbitrary
22physical CPUs at the whims of the primary VM scheduler.
23
24All VMs will start with a single active vCPU. Subsequent vCPUs can be started
25through PSCI.
26
27## PSCI
28
29The primary VM will be able to control the physical CPUs through the following
30PSCI 1.1 calls, which will be forwarded to the underlying implementation in EL3:
31
Demi Marie Obenour1a55b772023-02-15 10:38:26 -050032* `PSCI_VERSION`
33* `PSCI_FEATURES`
34* `PSCI_SYSTEM_OFF`
35* `PSCI_SYSTEM_RESET`
36* `PSCI_AFFINITY_INFO`
37* `PSCI_CPU_SUSPEND`
38* `PSCI_CPU_OFF`
39* `PSCI_CPU_ON`
Andrew Walbranb2be7c62019-08-06 14:55:29 +010040
41All other PSCI calls are unsupported.
42
43Secondary VMs will be able to control their vCPUs through the following PSCI 1.1
44calls, which will be implemented by Hafnium:
45
Demi Marie Obenour1a55b772023-02-15 10:38:26 -050046* `PSCI_VERSION`
47* `PSCI_FEATURES`
48* `PSCI_AFFINITY_INFO`
49* `PSCI_CPU_SUSPEND`
50* `PSCI_CPU_OFF`
51* `PSCI_CPU_ON`
Andrew Walbranb2be7c62019-08-06 14:55:29 +010052
53All other PSCI calls are unsupported.
54
55## Hardware timers
56
57The primary VM will have access to both the physical and virtual EL1 timers
58through the usual control registers (`CNT[PV]_TVAL_EL0` and `CNT[PV]_CTL_EL0`).
59
60Secondary VMs will have access to the virtual timer only, which will be emulated
61with help from the kernel driver in the primary VM.
62
63## Interrupts
64
65The primary VM will have direct access to control the physical GIC, and receive
66all interrupts (other than anything already trapped by TrustZone). It will be
67responsible for forwarding any necessary interrupts to secondary VMs. The
68Interrupt Translation Service (ITS) will be disabled by Hafnium so that it
69cannot be used to circumvent access controls.
70
71Secondary VMs will have access to a simple paravirtualized interrupt controller
72through two hypercalls: one to enable or disable a given virtual interrupt ID,
73and one to get and acknowledge the next pending interrupt. There is no concept
74of interrupt priorities or a distinction between edge and level triggered
75interrupts. Secondary VMs may also inject interrupts into their own vCPUs.
76
77## Performance counters
78
79VMs will be blocked from accessing performance counter registers (for the
Andrew Walbran20215742019-11-18 11:35:05 +000080performance monitor extensions described in chapter D5 of the Armv8-A reference
Andrew Walbranb2be7c62019-08-06 14:55:29 +010081manual) in production, to prevent them from being used as a side channel to leak
82data between VMs.
83
84Hafnium may allow VMs to use them in debug builds.
85
86## Debug registers
87
88VMs will be blocked from accessing debug registers in production builds, to
89prevent them from being used to circumvent access controls.
90
91Hafnium may allow VMs to use these registers in debug builds.
92
93## RAS Extension registers
94
Fuad Tabba66476b32019-10-29 10:32:04 +000095Secondary VMs will be blocked from using registers associated with the RAS
96Extension.
Andrew Walbranb2be7c62019-08-06 14:55:29 +010097
98## Asynchronous message passing
99
100VMs will be able to send messages of up to 4 KiB to each other asynchronously,
Andrew Walbranb5ab43c2020-04-30 11:32:54 +0100101with no queueing, as specified by FF-A.
Andrew Walbranb2be7c62019-08-06 14:55:29 +0100102
103## Memory
104
105VMs will statically be given access to mutually-exclusive regions of the
106physical address space at boot. This includes MMIO space for controlling
107devices, plus a fixed amount of RAM for secondaries, and all remaining address
108space to the primary. Note that this means that only one VM can control any
109given page of MMIO registers for a device.
110
111VMs may choose to donate or share their memory with other VMs at runtime. Any
112given page may be shared with at most 2 VMs at once (including the original
113owning VM). Memory which has been donated or shared may not be forcefully
114reclaimed, but the VM with which it was shared may choose to return it.
115
Fuad Tabba7a31b8d2019-10-28 15:17:27 +0000116## Cache
117
118VMs will be blocked from using cache maintenance instructions that operate by
119set/way. These operations are difficult to virtualize, and could expose the
120system to side-channel attacks.
121
Andrew Walbranb2be7c62019-08-06 14:55:29 +0100122## Logging
123
124VMs may send a character to a shared log by means of a hypercall or SMC call.
125These log messages will be buffered per VM to make complete lines, then output
126to a Hafnium-owned UART and saved in a shared ring buffer which may be extracted
127from RAM dumps. VM IDs will be prepended to these logs.
128
129This log API is intended for use in early bringup and low-level debugging. No
130sensitive data should be logged through it. Higher level logs can be sent to the
131primary VM through the asynchronous message passing mechanism described above,
132or through shared memory.
133
134## Configuration
135
136Hafnium will read configuration from a flattened device tree blob (FDT). This
137may either be the same device tree used for the other details of the system or a
138separate minimal one just for Hafnium. This will include at least:
139
140* The available RAM.
141* The number of secondary VMs, how many vCPUs each should have, how much
142 memory to assign to each of them, and where to load their initial images.
143 (Most likely the initial image will be a minimal loader supplied with
144 Hafnium which will validate and load the rest of the image from the primary
145 later on.)
146* Which devices exist on the system, their details (MMIO regions, interrupts
147 and SYSMMU details), and which VM each is assigned to.
148 * A single physical device may be split into multiple logical devices
149 from Hafniums point of view if necessary to have different VMs own
150 different parts of it.
151* A whitelist of which SMC calls each VM is allowed to make.
152
153## Failure handling
154
155If a secondary VM tries to do something it shouldn't, Hafnium will either inject
156a fault or kill it and inform the primary VM. The primary VM may choose to
157restart the system or to continue without the secondary VM.
158
159If the primary VM tries to do something it shouldn't, Hafnium will either inject
160a fault or restart the system.
161
162## TrustZone communication
163
164The primary VM will be able to communicate with a TEE running in TrustZone
Andrew Walbranb5ab43c2020-04-30 11:32:54 +0100165either through FF-A messages or through whitelisted SMC calls, and through
Andrew Walbranb2be7c62019-08-06 14:55:29 +0100166shared memory.
167
168## Other SMC calls
169
170Other than the PSCI calls described above and those used to communicate with
171Hafnium, all other SMC calls will be blocked by default. Hafnium will allow SMC
172calls to be whitelisted on a per-VM, per-function ID basis, as part of the
173static configuration described above. These whitelisted SMC calls will be
174forwarded to the EL3 handler with the client ID (as described by the SMCCC) set
175to the calling VM's ID.