| Andrew Walbran | 9545890 | 2018-11-13 18:56:06 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2018 Google LLC |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * https://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #pragma once |
| 18 | |
| 19 | #include <stdbool.h> |
| 20 | #include <stdint.h> |
| 21 | |
| 22 | #define GICD_BASE 0x08000000 |
| 23 | #define GICR_BASE 0x080A0000 |
| 24 | #define SGI_BASE (GICR_BASE + 0x10000) |
| 25 | |
| 26 | #define GICD_CTLR (*(volatile uint32_t *)(GICD_BASE + 0x0000)) |
| 27 | #define GICD_ISENABLER(n) (((volatile uint32_t *)(GICD_BASE + 0x0100))[n]) |
| 28 | #define GICD_ICENABLER(n) (((volatile uint32_t *)(GICD_BASE + 0x0180))[n]) |
| 29 | #define GICD_ISPENDR(n) (((volatile uint32_t *)(GICD_BASE + 0x0200))[n]) |
| 30 | #define GICD_ICPENDR(n) (((volatile uint32_t *)(GICD_BASE + 0x0280))[n]) |
| 31 | #define GICD_ISACTIVER(n) (((volatile uint32_t *)(GICD_BASE + 0x0300))[n]) |
| 32 | #define GICD_ICACTIVER(n) (((volatile uint32_t *)(GICD_BASE + 0x0380))[n]) |
| 33 | #define GICD_IPRIORITYR(n) (((volatile uint8_t *)(GICD_BASE + 0x0400))[n]) |
| 34 | #define GICD_ITARGETSR(n) (((volatile uint32_t *)(GICD_BASE + 0x0800))[n]) |
| 35 | #define GICD_ICFGR(n) (((volatile uint32_t *)(GICD_BASE + 0x0c00))[n]) |
| 36 | #define GICR_WAKER (*(volatile uint32_t *)(GICR_BASE + 0x0014)) |
| 37 | #define GICR_IGROUPR0 (*(volatile uint32_t *)(SGI_BASE + 0x0080)) |
| 38 | #define GICR_ISENABLER0 (*(volatile uint32_t *)(SGI_BASE + 0x0100)) |
| 39 | #define GICR_ICENABLER0 (*(volatile uint32_t *)(SGI_BASE + 0x0180)) |
| 40 | #define GICR_ISPENDR0 (*(volatile uint32_t *)(SGI_BASE + 0x0200)) |
| 41 | #define GICR_ICPENDR0 (*(volatile uint32_t *)(SGI_BASE + 0x0280)) |
| 42 | #define GICR_ISACTIVER0 (*(volatile uint32_t *)(SGI_BASE + 0x0300)) |
| 43 | #define GICR_ICFGR(n) (((volatile uint32_t *)(SGI_BASE + 0x0c00))[n]) |
| 44 | |
| 45 | void exception_setup(); |
| 46 | void interrupt_gic_setup(); |
| 47 | void interrupt_enable(uint32_t intid, bool enable); |
| 48 | void interrupt_enable_all(bool enable); |
| 49 | void interrupt_set_priority_mask(uint8_t min_priority); |
| 50 | void interrupt_set_priority(uint32_t intid, uint8_t priority); |
| 51 | void interrupt_set_edge_triggered(uint32_t intid, bool edge_triggered); |
| 52 | void interrupt_send_sgi(uint8_t intid, bool irm, uint8_t affinity3, |
| 53 | uint8_t affinity2, uint8_t affinity1, |
| 54 | uint16_t target_list); |
| 55 | uint32_t interrupt_get_and_acknowledge(); |
| 56 | void interrupt_end(uint32_t intid); |