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Jose Marinhofc0b2b62019-06-06 11:18:45 +01001/*
2 * Copyright 2019 The Hafnium Authors.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * https://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#pragma once
18
Jose Marinho75509b42019-04-09 09:34:59 +010019#include "hf/addr.h"
20#include "hf/vm.h"
21
22#include "vmapi/hf/spci.h"
23
Jose Marinhofc0b2b62019-06-06 11:18:45 +010024#define SPCI_VERSION_MAJOR 0x0
25#define SPCI_VERSION_MINOR 0x9
26
27#define SPCI_VERSION_MAJOR_OFFSET 16
Jose Marinho75509b42019-04-09 09:34:59 +010028
29struct spci_mem_transitions {
Andrew Walbran1281ed42019-10-22 17:23:40 +010030 uint32_t orig_from_mode;
31 uint32_t orig_to_mode;
32 uint32_t from_mode;
33 uint32_t to_mode;
Jose Marinho75509b42019-04-09 09:34:59 +010034};
35
Jose Marinho713f13a2019-05-21 11:54:16 +010036/* TODO: Add device attributes: GRE, cacheability, shareability. */
Andrew Walbranf5972182019-10-15 15:41:26 +010037static inline uint32_t spci_memory_attrs_to_mode(uint16_t memory_attributes)
Jose Marinho713f13a2019-05-21 11:54:16 +010038{
39 uint32_t mode = 0;
Jose Marinho713f13a2019-05-21 11:54:16 +010040
Andrew Walbranf5972182019-10-15 15:41:26 +010041 switch (spci_get_memory_access_attr(memory_attributes)) {
42 case SPCI_MEMORY_RO_NX:
43 mode = MM_MODE_R;
Jose Marinho713f13a2019-05-21 11:54:16 +010044 break;
Andrew Walbranf5972182019-10-15 15:41:26 +010045 case SPCI_MEMORY_RO_X:
46 mode = MM_MODE_R | MM_MODE_X;
Jose Marinho713f13a2019-05-21 11:54:16 +010047 break;
Andrew Walbranf5972182019-10-15 15:41:26 +010048 case SPCI_MEMORY_RW_NX:
49 mode = MM_MODE_R | MM_MODE_W;
Jose Marinho713f13a2019-05-21 11:54:16 +010050 break;
Andrew Walbranf5972182019-10-15 15:41:26 +010051 case SPCI_MEMORY_RW_X:
52 mode = MM_MODE_R | MM_MODE_W | MM_MODE_X;
Jose Marinho713f13a2019-05-21 11:54:16 +010053 break;
54 }
Andrew Walbranf5972182019-10-15 15:41:26 +010055
Jose Marinho713f13a2019-05-21 11:54:16 +010056 return mode;
57}
58
Andrew Walbrand4d2fa12019-10-01 16:47:25 +010059static inline struct spci_value spci_error(uint64_t error_code)
60{
Andrew Walbran9b19b752019-10-10 13:49:25 +010061 return (struct spci_value){.func = SPCI_ERROR_32, .arg2 = error_code};
Andrew Walbrand4d2fa12019-10-01 16:47:25 +010062}
63
Andrew Walbran70bc8622019-10-07 14:15:58 +010064struct spci_value spci_msg_handle_architected_message(
Jose Marinho75509b42019-04-09 09:34:59 +010065 struct vm_locked to_locked, struct vm_locked from_locked,
Andrew Walbran85aabe92019-12-03 12:03:03 +000066 struct spci_memory_region *memory_region, uint32_t size,
67 uint32_t attributes, struct mpool *api_page_pool);