blob: ef263a4036fbc4866d19d81c978f4e78cb1e53b5 [file] [log] [blame]
Andrew Walbran474c4392019-09-11 13:57:17 +01001// SPDX-License-Identifier: Apache-2.0
2/*
3 * Copyright 2019 The Hafnium Authors.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * https://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17
18#include "hf/call.h"
Andrew Walbran4fef63d2019-09-12 10:34:52 +010019#include "hf/spci.h"
Andrew Walbran474c4392019-09-11 13:57:17 +010020#include "hf/types.h"
21
22int64_t hf_call(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3)
23{
24 register uint64_t r0 __asm__("x0") = arg0;
25 register uint64_t r1 __asm__("x1") = arg1;
26 register uint64_t r2 __asm__("x2") = arg2;
27 register uint64_t r3 __asm__("x3") = arg3;
28
Andrew Walbran474c4392019-09-11 13:57:17 +010029 __asm__ volatile(
30 "hvc #0"
31 : /* Output registers, also used as inputs ('+' constraint). */
Andrew Walbrana9893302019-09-12 16:36:05 +010032 "+r"(r0), "+r"(r1), "+r"(r2), "+r"(r3)
33 :
34 : /* Clobber registers. */
35 "x4", "x5", "x6", "x7");
Andrew Walbran474c4392019-09-11 13:57:17 +010036
37 return r0;
38}
Andrew Walbran4fef63d2019-09-12 10:34:52 +010039
40struct spci_value spci_call(struct spci_value args)
41{
42 register uint64_t r0 __asm__("x0") = args.func;
43 register uint64_t r1 __asm__("x1") = args.arg1;
44 register uint64_t r2 __asm__("x2") = args.arg2;
45 register uint64_t r3 __asm__("x3") = args.arg3;
46 register uint64_t r4 __asm__("x4") = args.arg3;
47 register uint64_t r5 __asm__("x5") = args.arg3;
48 register uint64_t r6 __asm__("x6") = args.arg3;
49 register uint64_t r7 __asm__("x7") = args.arg3;
50
51 __asm__ volatile(
52 "hvc #0"
53 : /* Output registers, also used as inputs ('+' constraint). */
54 "+r"(r0), "+r"(r1), "+r"(r2), "+r"(r3), "+r"(r4), "+r"(r5),
55 "+r"(r6), "+r"(r7));
56
57 return (struct spci_value){.func = r0,
58 .arg1 = r1,
59 .arg2 = r2,
60 .arg3 = r3,
61 .arg4 = r4,
62 .arg5 = r5,
63 .arg6 = r6,
64 .arg7 = r7};
65}