run_config/fvp-rdn1edgex2

#!/usr/bin/env bash
#
# Copyright (c) 2020, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#

fetch_tf_resource() {
	# Fetch the pre-built SCP/MCP binaries if they haven't been built
	if [ ! -f "$archive/mcp_rom.bin" ]; then
		url="$scp_mcp_prebuilts/mcp_romfw.bin" saveas="mcp_rom.bin" fetch_file
		archive_file "mcp_rom.bin"
	fi
	if [ ! -f "$archive/scp_ram.bin" ]; then
		url="$scp_mcp_prebuilts/scp_bl2.bin" saveas="scp_ram.bin" fetch_file
		archive_file "scp_ram.bin"
	fi
	if [ ! -f "$archive/scp_rom.bin" ]; then
		url="$scp_mcp_prebuilts/scp_bl1.bin" saveas="scp_rom.bin" fetch_file
		archive_file "scp_rom.bin"
	fi

	# Hold scp terminal_uart_aon on css0
	uart="2" file="hold_uart.exp" track_expect

	# Hold scp terminal_uart_aon on css1
	uart="3" file="hold_uart.exp" track_expect
}

pre_tf_build() {
	#
	# Dual-Chip RD-N1-Edge FVP has reliability issues with stlr instruction
	# while sending events across the chip through CCIX link. Apply 'send
	# explicit event after store release instruction' patch to improve the
	# reliability of cross chip events.
	#
	apply_tf_patch "css_rd_multichip_fvp/spinlock-send-explicit-event-after-store-release.patch"
}

post_fetch_tf_resource() {
        local model="css-rdn1edgex2"

	model="$model" gen_model_params
	set_run_env "ports_script" "$ci_root/model/css-rdinfra-ports.awk"
	set_run_env "num_uarts" "4"
	uart="0" set_expect_variable "num_cpus" "16"
	model="$model" gen_fvp_yaml
}