| Gabor Ambrus | 54a1008 | 2023-08-14 21:56:06 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PL011_H |
| 8 | #define PL011_H |
| 9 | |
| 10 | /* |
| 11 | * For the documentation of the driver, please refer to: |
| 12 | * https://developer.arm.com/documentation/ddi0183/g |
| 13 | */ |
| 14 | |
| 15 | /* PL011 Registers */ |
| 16 | #define UARTDR 0x000 |
| 17 | #define UARTRSR 0x004 |
| 18 | #define UARTECR 0x004 |
| 19 | #define UARTFR 0x018 |
| 20 | #define UARTIMSC 0x038 |
| 21 | #define UARTRIS 0x03C |
| 22 | #define UARTICR 0x044 |
| 23 | |
| 24 | /* |
| 25 | * PL011 registers which are not part of SBSA specification. |
| 26 | * These registers are disabled if the underlying hardware is |
| 27 | * only a minimally compliant generic UART, which is a subset |
| 28 | * of PL011. |
| 29 | */ |
| 30 | #if !PL011_GENERIC_UART |
| 31 | #define UARTILPR 0x020 |
| 32 | #define UARTIBRD 0x024 |
| 33 | #define UARTFBRD 0x028 |
| 34 | #define UARTLCR_H 0x02C |
| 35 | #define UARTCR 0x030 |
| 36 | #define UARTIFLS 0x034 |
| 37 | #define UARTMIS 0x040 |
| 38 | #define UARTDMACR 0x048 |
| 39 | #endif /* !PL011_GENERIC_UART */ |
| 40 | |
| 41 | /* Data status bits */ |
| 42 | #define UART_DATA_ERROR_MASK 0x0F00 |
| 43 | |
| 44 | /* Status reg bits */ |
| 45 | #define UART_STATUS_ERROR_MASK 0x0F |
| 46 | |
| 47 | /* Flag reg bits */ |
| 48 | #define PL011_UARTFR_RI (1 << 8) /* Ring indicator */ |
| 49 | #define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */ |
| 50 | #define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */ |
| 51 | #define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */ |
| 52 | #define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */ |
| 53 | #define PL011_UARTFR_BUSY (1 << 3) /* UART busy */ |
| 54 | #define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */ |
| 55 | #define PL011_UARTFR_DSR (1 << 1) /* Data set ready */ |
| 56 | #define PL011_UARTFR_CTS (1 << 0) /* Clear to send */ |
| 57 | |
| 58 | #define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in UARTFR register */ |
| 59 | #define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in UARTFR register */ |
| 60 | #define PL011_UARTFR_BUSY_BIT 3 /* UART busy bit in UARTFR register */ |
| 61 | |
| 62 | /* Control reg bits */ |
| 63 | #define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */ |
| 64 | #define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */ |
| 65 | #define PL011_UARTCR_RTS (1 << 11) /* Request to send */ |
| 66 | #define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */ |
| 67 | #define PL011_UARTCR_RXE (1 << 9) /* Receive enable */ |
| 68 | #define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */ |
| 69 | #define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */ |
| 70 | #define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */ |
| 71 | |
| 72 | #if !defined(PL011_LINE_CONTROL) |
| 73 | /* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */ |
| 74 | #define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8) |
| 75 | #endif |
| 76 | |
| 77 | /* Line Control Register Bits */ |
| 78 | #define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */ |
| 79 | #define PL011_UARTLCR_H_WLEN_8 (3 << 5) |
| 80 | #define PL011_UARTLCR_H_WLEN_7 (2 << 5) |
| 81 | #define PL011_UARTLCR_H_WLEN_6 (1 << 5) |
| 82 | #define PL011_UARTLCR_H_WLEN_5 (0 << 5) |
| 83 | #define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */ |
| 84 | #define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */ |
| 85 | #define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */ |
| 86 | #define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */ |
| 87 | #define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */ |
| 88 | |
| 89 | #define ERROR_NO_PENDING_CHAR (-1) |
| 90 | |
| 91 | #endif /* PL011_H */ |