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David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]1#######################################
2Trusted Firmware-M Generic Threat Model
3#######################################
4
5************
6Introduction
7************
8
shejia0144764cb2021-05-26 16:48:06 +0800[diff] [blame]9This document introduces a generic threat model of Trusted Firmware-M (TF-M).
10This generic threat model provides an overall analysis of TF-M implementation
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]11and identifies general threats and mitigation.
12
Kevin Pengf6eb1302022-09-05 10:01:36 +0800[diff] [blame^]13There is also a dedicated document for physical attacks mitigations which can be found
14:doc:`here </technical_references/design_docs/tfm_physical_attack_mitigation>`.
15
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]16.. note::
17
18 If you think a security vulnerability is found, please follow
19 Trustedfirmware.org [Security-Incident-Process]_ to contact TF-M security
20 team.
21
22Scope
23=====
24
25TF-M supports diverse models and topologies. It also implements multiple
26isolation levels. Each case may focus on different target of evaluation (TOE)
27and identify different assets and threats.
28TF-M implementation consists of several secure services, defined as
29Root of Trust (RoT) service. Those RoT services belong to diverse RoT
30(Application RoT or PSA RoT) and access different assets and hardware. Therefore
31each RoT service may require a dedicated threat model.
32
33The analysis on specific models, topologies or RoT services may be covered in
shejia0144764cb2021-05-26 16:48:06 +0800[diff] [blame]34dedicated threat model documents. Those threat models are out of the scope of
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]35this document.
36
37Methodology
38===========
39
40The threat modeling in this document follows the process listed below to
41build up the threat model.
42
43- Target of Evaluation (TOE)
44- Assets identification
45- Data Flow Diagram (DFD)
46- Threats Prioritization
47- Threats identification
48
49TOE is the entity on which threat modeling is performed. The logic behind this
50process is to firstly investigate the TOE which could be a system, solution or
51use case. This first step helps to identify the assets to be protected in TOE.
52
53According to TOE and assets, Trust Boundaries can be determined. The Data Flow
54Diagram (DFD) across Trust Boundaries is then defined to help identify the
55threats.
56
57Those threats should be prioritized based on a specific group of principals and
58metrics. The principals and metrics should also be specified.
59
60********************
61Target of Evaluation
62********************
63
64A typical TF-M system diagram from a high-level overview is shown below. TF-M is
65running in the Secure Processing Environment (SPE) and NS software is running in
66Non-secure Processing Environment (NSPE). For more details, please refer to
Kevin Peng4cdb2082022-03-25 17:53:03 +0800[diff] [blame]67Platform Security Architecture Firmware Framework for M (FF-M) [FF-M]_ and
68FF-M 1.1 Extensions [FF-M 1.1 Extensions]_.
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]69
70.. figure:: TF-M-block-diagram.png
71
72The TOE in this general model is the SPE, including TF-M and other components
73running in SPE.
74
75The TOE can vary in different TF-M models, RoT services and usage scenarios.
shejia0144764cb2021-05-26 16:48:06 +0800[diff] [blame]76Refer to dedicated threat models for the specific TOE definitions.
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]77
78********************
79Asset identification
80********************
81
82In this threat model, assets include the general items listed below:
83
84- Hardware Root of Trust data, e.g.
85
86 - Hardware Unique Key (HUK)
87 - Root authentication key
88 - Other embedded root keys
89
90- Software RoT data, e.g.
91
92 - Secure Partition Manager (SPM) code and data
93 - Secure partition code and data
94 - NSPE data stored in SPE
95 - Data generated in SPE as requested by NSPE
96
97- Availability of entire RoT service
98
99- Secure logs, including event logs
100
101Assets may vary in different use cases and implementations. Additional assets
102can be defined in an actual usage scenario and a dedicated threat model.
103
104For example, in a network camera use case, the following data can be defined as
105assets too:
106
107- Certificate for connecting to cloud
108- Session keys for encryption/decryption in the communication with cloud
109- Keys to encrypt/decrypt the videos and photos
110
111*****************
112Data Flow Diagram
113*****************
114
115The Trust Boundary isolates SPE from NSPE, according to the TOE definition in
116`Target of Evaluation`_. The Trust Boundary mapped to block diagram is shown
117in the figure below. Other modules inside SPE stay in the same TOE as TF-M does.
118
119Valid Data flows across the Trust Boundary are also shown in the figure below.
shejia0144764cb2021-05-26 16:48:06 +0800[diff] [blame]120This threat model only focuses on the data flows related to TF-M.
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]121
122.. figure:: overall-DFD.png
123
124More details of data flows are listed below.
125
126.. _data-flow-table:
127
128.. table:: TF-M Data Flows between NSPE and SPE
129
130 +-----------+----------------------------------------------------------------+
131 | Data flow | Description |
132 +===========+================================================================+
133 | ``DF1`` | TF-M initializes NS entry and activates NSPE. |
134 | | |
135 | | - On single Armv8-M core platforms, TF-M will hand over the |
136 | | control to Non-secure state. |
137 | | - On dual-cpu platforms, Secure core starts NS core booting. |
138 +-----------+----------------------------------------------------------------+
139 | ``DF2`` | NSPE requests TF-M RoT services. |
140 | | |
141 | | - In TF-M Library model, NS invokes Secure Function calls |
142 | | - In TF-M IPC model, NS invokes PSA Client calls based on IPC |
143 | | protocol defined in [FF-M]_. |
144 | | |
145 | | In single Armv8-M core scenarios, SG instruction is executed |
146 | | in Non-secure Callable region to trigger a transition from |
147 | | Non-secure state to Secure state. |
148 | | |
149 | | On dual-cpu platforms, non-secure core sends PSA Client calls |
150 | | to secure core via mailbox. |
151 +-----------+----------------------------------------------------------------+
152 | ``DF3`` | Secure Partitions fetch input data from NS and write back |
153 | | output data to NS. |
154 | | |
155 | | In TF-M IPC model, as required in [FF-M]_, Secure Partitions |
156 | | should not directly access NSPE memory. Instead, RoT services |
157 | | relies on TF-M SPM to access NSPE memory. |
158 +-----------+----------------------------------------------------------------+
159 | ``DF4`` | TF-M returns RoT service results to NSPE after NS request to |
160 | | RoT service is completed. |
161 | | |
162 | | In single Armv8-M core scenarios, it also trigger a transition |
163 | | from Secure state back to Non-secure state. |
164 | | |
165 | | On dual-cpu platforms, secure core returns the result to |
166 | | non-secure core via mailbox. |
167 +-----------+----------------------------------------------------------------+
168 | ``DF5`` | Non-secure interrupts preempt SPE execution in single Armv8-M |
169 | | core scenarios. |
170 +-----------+----------------------------------------------------------------+
171 | ``DF6`` | Secure interrupts preempt NSPE execution in single Armv8-M |
172 | | core scenarios. |
173 +-----------+----------------------------------------------------------------+
174
175.. note::
176
177 All the other data flows across the Trusted Boundary besides the valid ones
178 mentioned above should be prohibited by default.
179 Proper isolation must be configured to prevent NSPE directly accessing SPE.
180
181 Threats irrelevant to data flows in
182 :ref:`TF-M Data Flows between NSPE and SPE <data-flow-table>` may be specified
183 in `Miscellaneous threats`_.
184
185Data flows inside SPE (informative)
186===================================
187
188Since all the SPE components stay in the TOE within the same Trust Boundary in
189this threat model, the data flows between SPE components are not covered in this
190threat model. Instead, those data flows and corresponding threats will be
191identified in the dedicated threat model documents of TF-M RoT services and
192usage scenarios.
193
194Those data flows inside SPE include following examples:
195
196- Data flows between TF-M and BL2
197- Data flows between RoT services and SPM
198- Data flows between RoT services and corresponding secure hardware and assets,
199 such as secure storage device, crypto hardware accelerator and Hardware Unique
200 Key (HUK).
201
202*********************
203Threat identification
204*********************
205
206Threat priority
207===============
208
209Threat priority is indicated by the score calculated via Common Vulnerability
210Scoring System (CVSS) Version 3.1 [CVSS]_. The higher the threat scores, the
211greater severity the threat is with and the higher the priority is.
212
213CVSS scores can be mapped to qualitative severity ratings defined in CVSS 3.1
214specification [CVSS_SPEC]_. This threat model follows the same mapping between
215CVSS scores and threat priority rating.
216
217As a generic threat model, this document focuses on *Base Score* which reflects
218the constant and general severity of a threat according to its intrinsic
219characteristics.
220
221The *Impacted Component* defined in [CVSS_SPEC]_ refers to the assets listed in
222`Asset identification`_.
223
224Threats and mitigation list
225===========================
226
227This section lists generic threats and corresponding mitigation, based on the
228the analysis of data flows in `Data Flow Diagram`_.
229
230Threats are identified following ``STRIDE`` model. Please refer to [STRIDE]_ for
231more details.
232
233The field ``CVSS Score`` reflects the threat priority defined in
234`Threat priority`_. The field ``CVSS Vector String`` contains the textual
235representation of the CVSS metric values used to score the threat. Refer to
236[CVSS_SPEC]_ for more details of CVSS vector string.
237
238.. note::
239
240 A generic threat may have different behaviors and therefore require different
241 mitigation, in diverse TF-M models and usage scenarios.
242
243 This threat model document focuses on general analysis of the following
244 threats. For the details in a specific configuration and usage scenario,
245 please refer to the dedicated threat model document.
246
247NS entry initialization
248-----------------------
249
250This section identifies threats on ``DF1`` defined in `Data Flow Diagram`_.
251
252.. table:: TFM-GENERIC-NS-INIT-T-1
253 :widths: 10 50
254
255 +---------------+------------------------------------------------------------+
256 | Index | **TFM-GENERIC-NS-INIT-T-1** |
257 +---------------+------------------------------------------------------------+
258 | Description | The NS image can be tampered by an attacker |
259 +---------------+------------------------------------------------------------+
260 | Justification | An attack may tamper the NS image to inject malicious code |
261 +---------------+------------------------------------------------------------+
262 | Category | Tampering |
263 +---------------+------------------------------------------------------------+
264 | Mitigation | By default TF-M relies on MCUBoot to validate NS image. |
265 | | The validation of NS image integrity and authenticity is |
266 | | completed in secure boot before jumping to NS entry or |
267 | | booting up NS core. |
268 | | Refer to [SECURE-BOOT]_ for more details. |
269 | | |
270 | | The validation may vary in diverse vendor platforms |
271 | | specific Chain of Trust (CoT) implementation. |
272 +---------------+------------------------------------------------------------+
273 | CVSS Score | 3.5 (Low) |
274 +---------------+------------------------------------------------------------+
275 | CVSS Vector | CVSS:3.1/AV:P/AC:L/PR:N/UI:N/S:U/C:L/I:L/A:N |
276 | String | |
277 +---------------+------------------------------------------------------------+
278
279.. table:: TFM-GENERIC-NS-INIT-T-2
280 :widths: 10 50
281
282 +---------------+------------------------------------------------------------+
283 | Index | **TFM-GENERIC-NS-INIT-T-2** |
284 +---------------+------------------------------------------------------------+
285 | Description | An attacker may replace the current NS image with an older |
286 | | version. |
287 +---------------+------------------------------------------------------------+
288 | Justification | The attacker downgrades the NS image with an older version |
289 | | which has been deprecated due to known security issues. |
290 | | |
291 | | The older version image can pass the image signature |
292 | | validation and its vulnerabilities can be exploited by |
293 | | attackers. |
294 +---------------+------------------------------------------------------------+
295 | Category | Tampering |
296 +---------------+------------------------------------------------------------+
297 | Mitigation | TF-M relies on MCUBoot to perform anti-rollback |
298 | | protection. |
299 | | |
300 | | TF-M defines a non-volatile counter API to support |
301 | | anti-rollback. Each platform must implement it using |
302 | | specific trusted hardware non-volatile counters. |
303 | | For more details, refer to [ROLLBACK-PROTECT]_. |
304 | | |
305 | | The anti-rollback protection implementation can vary on |
306 | | diverse platforms. |
307 +---------------+------------------------------------------------------------+
308 | CVSS Score | 3.5 (Low) |
309 +---------------+------------------------------------------------------------+
310 | CVSS Vector | CVSS:3.1/AV:P/AC:L/PR:N/UI:N/S:U/C:L/I:L/A:N |
311 | String | |
312 +---------------+------------------------------------------------------------+
313
314.. table:: TFM-GENERIC-NS-INIT-T-I-1
315 :widths: 10 50
316
317 +---------------+------------------------------------------------------------+
318 | Index | **TFM-GENERIC-NS-INIT-T-I-1** |
319 +---------------+------------------------------------------------------------+
320 | Description | If SPE doesn't complete isolation configuration before |
321 | | NSPE starts, NSPE can access secure regions which it is |
322 | | disallowed to. |
323 +---------------+------------------------------------------------------------+
324 | Justification | Secure data can be tampered or disclosed if NSPE is |
325 | | activated and accesses secure regions before isolation |
326 | | configuration is completed by SPE. |
327 +---------------+------------------------------------------------------------+
328 | Category | Tampering/Information disclosure |
329 +---------------+------------------------------------------------------------+
330 | Mitigation | SPE must complete and enable proper isolation to protect |
331 | | secure regions from being accessed by NSPE, before jumping |
332 | | to NS entry or booting up NS core. |
333 | | |
334 | | TF-M executes isolation configuration at early stage of |
335 | | secure initialization before NS initialization starts. |
336 | | |
337 | | On dual-cpu platform, platform specific initialization |
338 | | must halt NS core until isolation is completed, as defined |
339 | | in [DUAL-CPU-BOOT]_. |
340 | | |
341 | | TF-M defines isolation configuration HALs for platform |
342 | | implementation. The specific isolation configuration |
343 | | depends on platform specific implementation. |
344 +---------------+------------------------------------------------------------+
345 | CVSS Score | 9.0 (Critical) |
346 +---------------+------------------------------------------------------------+
347 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:N |
348 | String | |
349 +---------------+------------------------------------------------------------+
350
351.. table:: TFM-GENERIC-NS-INIT-T-I-2
352 :widths: 10 50
353
354 +---------------+------------------------------------------------------------+
355 | Index | **TFM-GENERIC-NS-INIT-T-I-2** |
356 +---------------+------------------------------------------------------------+
357 | Description | If SPE doesn't complete isolation configuration before |
358 | | NSPE starts, NSPE can control devices or peripherals which |
359 | | it is disallowed to. |
360 +---------------+------------------------------------------------------------+
361 | Justification | On some platforms, devices and peripherals can be |
362 | | configured as Secure state in runtime. If security status |
363 | | configuration of those device and peripherals are not |
364 | | properly completed before NSPE starts, NSPE can control |
365 | | those device and peripherals and may be able to tamper |
366 | | data or access secure data. |
367 +---------------+------------------------------------------------------------+
368 | Category | Tampering/Information disclosure |
369 +---------------+------------------------------------------------------------+
370 | Mitigation | SPE must complete and enable proper configuration and |
371 | | isolation to protect critical devices and peripherals from |
372 | | being accessed by NSPE, before jumping to NS entry or |
373 | | booting up NS core. |
374 | | |
375 | | TF-M executes isolation configuration of devices and |
376 | | peripherals at early stage of secure initialization before |
377 | | NS initialization starts. |
378 | | |
379 | | The specific isolation configuration depends on platform |
380 | | specific implementation. |
381 +---------------+------------------------------------------------------------+
382 | CVSS Score | 9.0 (Critical) |
383 +---------------+------------------------------------------------------------+
384 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:N |
385 | String | |
386 +---------------+------------------------------------------------------------+
387
388.. table:: TFM-GENERIC-NS-INIT-I-2
389 :widths: 10 50
390
391 +---------------+------------------------------------------------------------+
392 | Index | **TFM-GENERIC-NS-INIT-I-2** |
393 +---------------+------------------------------------------------------------+
394 | Description | If SPE leaves some SPE information in non-secure memory |
395 | | or shared registers when NSPE starts, NSPE may access |
396 | | those SPE information. |
397 +---------------+------------------------------------------------------------+
398 | Justification | If NSPE can access those SPE information from shared |
399 | | registers or non-secure memory, secure information may be |
400 | | disclosed. |
401 +---------------+------------------------------------------------------------+
402 | Category | Information disclosure |
403 +---------------+------------------------------------------------------------+
404 | Mitigation | SPE must clean up the secure information from shared |
405 | | registers before NS starts. |
406 | | |
407 | | TF-M invalidates registers not banked before handing over |
408 | | the system to NSPE on single Armv8-M platform. |
409 | | |
410 | | On dual-cpu platforms, shared registers are implementation |
411 | | defined, such as Inter-Processor Communication registers. |
412 | | Dual-cpu platforms must not store any data which may |
413 | | disclose secure information in the shared registers. |
414 | | |
415 | | SPE must avoid storing SPE information in non-secure |
416 | | memory. |
417 +---------------+------------------------------------------------------------+
418 | CVSS Score | 4.3 (Medium) |
419 +---------------+------------------------------------------------------------+
420 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N |
421 | String | |
422 +---------------+------------------------------------------------------------+
423
424.. table:: TFM-GENERIC-NS-INIT-D-1
425 :widths: 10 50
426
427 +---------------+------------------------------------------------------------+
428 | Index | **TFM-GENERIC-NS-INIT-D-1** |
429 +---------------+------------------------------------------------------------+
430 | Description | An attacker may block NS to boot up |
431 +---------------+------------------------------------------------------------+
432 | Justification | An attacker may block NS to boot up, such as by corrupting |
433 | | NS image, to stop the whole system from performing normal |
434 | | functionalities. |
435 +---------------+------------------------------------------------------------+
436 | Category | Denial of service |
437 +---------------+------------------------------------------------------------+
438 | Mitigation | No SPE information will be disclosed and TF-M won't be |
439 | | directly impacted. |
440 | | |
441 | | It relies on NSPE and platform specific implementation to |
442 | | mitigate this threat. It is out of scope of this threat |
443 | | model. |
444 +---------------+------------------------------------------------------------+
445 | CVSS Score | 4.0 (Medium) |
446 +---------------+------------------------------------------------------------+
447 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:L |
448 | String | |
449 +---------------+------------------------------------------------------------+
450
451NSPE requests TF-M secure service
452---------------------------------
453
454This section identifies threats on ``DF2`` defined in `Data Flow Diagram`_.
455
456.. table:: TFM-GENERIC-REQUEST-SERVICE-S-1
457 :widths: 10 50
458
459 +---------------+------------------------------------------------------------+
460 | Index | **TFM-GENERIC-REQUEST-SERVICE-S-1** |
461 +---------------+------------------------------------------------------------+
462 | Description | A malicious NS application may pretend as a secure client |
463 | | to access secure data which NSPE must not directly access. |
464 +---------------+------------------------------------------------------------+
465 | Justification | [FF-M]_ defines ``Client ID`` to distinguish clients which |
466 | | request RoT services. Secure clients are assigned with |
467 | | positive IDs and non-secure clients are assigned with |
468 | | negative ones. |
469 | | |
470 | | A malicious NS application may provide a positive |
471 | | ``Client ID`` to pretend as a secure client to access |
472 | | secure data. |
473 +---------------+------------------------------------------------------------+
474 | Category | Spoofing |
475 +---------------+------------------------------------------------------------+
476 | Mitigation | TF-M checks the ``Client ID`` from NSPE. If the NS |
477 | | ``Client ID`` is not a valid one, TF-M will report this as |
478 | | a security error. |
479 +---------------+------------------------------------------------------------+
480 | CVSS Score | 8.4 (High) |
481 +---------------+------------------------------------------------------------+
482 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:N |
483 | String | |
484 +---------------+------------------------------------------------------------+
485
486.. table:: TFM-GENERIC-REQUEST-SERVICE-T-1
487 :widths: 10 50
488
489 +---------------+------------------------------------------------------------+
490 | Index | **TFM-GENERIC-REQUEST-SERVICE-T-1** |
491 +---------------+------------------------------------------------------------+
492 | Description | An attacker in NSPE may tamper the service request input |
493 | | or output vectors between check and use |
494 | | (Time-Of-Check-to-Time-Of-Use (TOCTOU)). |
495 +---------------+------------------------------------------------------------+
496 | Justification | If SPE validates the content in input/output vectors |
497 | | locally in NSPE memory, an attacker in NSPE can have a |
498 | | chance to tamper the content after the validation |
499 | | successfully passes. Then SPE will provide RoT service |
500 | | according to the corrupted parameters and it may cause |
501 | | further security issues. |
502 +---------------+------------------------------------------------------------+
503 | Category | Tampering |
504 +---------------+------------------------------------------------------------+
505 | Mitigation | In TF-M implementation, the validation of NS input/output |
506 | | vectors are only executed after those vectors are copied |
507 | | from NSPE into SPE. It prevents an attack from NSPE to |
508 | | tamper those parameters after validation in TF-M. |
509 +---------------+------------------------------------------------------------+
510 | CVSS Score | 7.8 (High) |
511 +---------------+------------------------------------------------------------+
512 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:C/C:H/I:H/A:N |
513 | String | |
514 +---------------+------------------------------------------------------------+
515
516.. table:: TFM-GENERIC-REQUEST-SERVICE-T-2
517 :widths: 10 50
518
519 +---------------+------------------------------------------------------------+
520 | Index | **TFM-GENERIC-REQUEST-SERVICE-T-2** |
521 +---------------+------------------------------------------------------------+
522 | Description | A malicious NS application may request to tamper data |
523 | | belonging to SPE. |
524 +---------------+------------------------------------------------------------+
525 | Justification | A malicious NS application may request SPE RoT services to |
526 | | write malicious value to SPE data. The malicious NS |
527 | | application may try to tamper SPE assets, such as keys, or |
528 | | modify configurations in SPE. The SPE data belongs to |
529 | | components in SPE and must not be accessed by NSPE. |
530 +---------------+------------------------------------------------------------+
531 | Category | Tampering |
532 +---------------+------------------------------------------------------------+
533 | Mitigation | TF-M executes memory access check to all the RoT service |
534 | | requests. If a request doesn't have enough permission to |
535 | | access the target memory region, TF-M will refuse this |
536 | | request and assert a security error. |
537 +---------------+------------------------------------------------------------+
538 | CVSS Score | 7.1 (High) |
539 +---------------+------------------------------------------------------------+
540 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:N/I:H/A:N |
541 | String | |
542 +---------------+------------------------------------------------------------+
543
544.. table:: TFM-GENERIC-REQUEST-SERVICE-R-1
545 :widths: 10 50
546
547 +---------------+------------------------------------------------------------+
548 | Index | **TFM-GENERIC-REQUEST-SERVICE-R-1** |
549 +---------------+------------------------------------------------------------+
550 | Description | A NS application may repudiate that it has requested |
551 | | services from a RoT service. |
552 +---------------+------------------------------------------------------------+
553 | Justification | A malicious NS application may call a RoT service to |
554 | | access critical data in SPE, which it is disallowed to, |
555 | | via a non-public vulnerability. It may refuse to admit |
556 | | that it has accessed that data. |
557 +---------------+------------------------------------------------------------+
558 | Category | Repudiation |
559 +---------------+------------------------------------------------------------+
560 | Mitigation | TF-M implements an event logging secure service to record |
561 | | the critical events, such as the access to critical data. |
562 +---------------+------------------------------------------------------------+
563 | CVSS Score | 0.0 (None) |
564 +---------------+------------------------------------------------------------+
565 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:N/I:N/A:N |
566 | String | |
567 +---------------+------------------------------------------------------------+
568
569.. table:: TFM-GENERIC-REQUEST-SERVICE-I-1
570 :widths: 10 50
571
572 +---------------+------------------------------------------------------------+
573 | Index | **TFM-GENERIC-REQUEST-SERVICE-I-1** |
574 +---------------+------------------------------------------------------------+
575 | Description | A malicious NS application may request to read data |
576 | | belonging to SPE. |
577 +---------------+------------------------------------------------------------+
578 | Justification | A malicious NS application may request SPE RoT services to |
579 | | copy SPE data to NS memory. The SPE data belongs to |
580 | | components in SPE and must not be disclosed to NSPE, such |
581 | | as root keys. |
582 +---------------+------------------------------------------------------------+
583 | Category | Information disclosure |
584 +---------------+------------------------------------------------------------+
585 | Mitigation | TF-M executes memory access check to all the RoT service |
586 | | requests. If a request doesn't have enough permission to |
587 | | access the target memory region, TF-M will refuse this |
588 | | request and assert a security error. |
589 +---------------+------------------------------------------------------------+
590 | CVSS Score | 7.1 (High) |
591 +---------------+------------------------------------------------------------+
592 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:N/A:N |
593 | String | |
594 +---------------+------------------------------------------------------------+
595
596.. table:: TFM-GENERIC-REQUEST-SERVICE-T-I-1
597 :widths: 10 50
598
599 +---------------+------------------------------------------------------------+
600 | Index | **TFM-GENERIC-REQUEST-SERVICE-T-I-1** |
601 +---------------+------------------------------------------------------------+
602 | Description | A malicious NS application may request to control secure |
603 | | device and peripherals, on which it doesn't have the |
604 | | permission. |
605 +---------------+------------------------------------------------------------+
606 | Justification | A malicious NS application may request RoT services to |
607 | | control secure device and peripherals, on which it doesn't |
608 | | have the permission. |
609 +---------------+------------------------------------------------------------+
610 | Category | Tampering/Information disclose |
611 +---------------+------------------------------------------------------------+
612 | Mitigation | TF-M performs client check to validate whether the client |
613 | | has the permission to access the secure device and |
614 | | peripherals. |
615 +---------------+------------------------------------------------------------+
616 | CVSS Score | 9.0 (Critical) |
617 +---------------+------------------------------------------------------------+
618 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:N |
619 | String | |
620 +---------------+------------------------------------------------------------+
621
622.. table:: TFM-GENERIC-REQUEST-SERVICE-D-1
623 :widths: 10 50
624
625 +---------------+------------------------------------------------------------+
626 | Index | **TFM-GENERIC-REQUEST-SERVICE-D-1** |
627 +---------------+------------------------------------------------------------+
628 | Description | A Malicious NS applications may frequently call secure |
629 | | services to block secure service requests from other NS |
630 | | applications. |
631 +---------------+------------------------------------------------------------+
632 | Justification | TF-M runs on IoT devices with constrained resource. Even |
633 | | though multiple outstanding NS PSA Client calls can be |
634 | | supported in system, the number of NS PSA client calls |
635 | | served by TF-M simultaneously are still limited. |
636 | | |
637 | | Therefore, if a malicious NS application or multiple |
638 | | malicious NS applications continue calling TF-M secure |
639 | | services frequently, it may block other NS applications to |
640 | | request secure service from TF-M. |
641 +---------------+------------------------------------------------------------+
642 | Category | Denial of service |
643 +---------------+------------------------------------------------------------+
644 | Mitigation | TF-M is unable to manage behavior of NS applications. |
645 | | Assets are not disclosed and TF-M is neither directly |
646 | | impacted in this threat. |
647 | | |
648 | | It relies on NS OS to enhance scheduling policy and |
649 | | prevent a single NS application to occupy entire CPU time. |
650 | | It is beyond the scope of this threat model. |
651 +---------------+------------------------------------------------------------+
652 | CVSS Score | 4.0 (Medium) |
653 +---------------+------------------------------------------------------------+
654 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:L |
655 | String | |
656 +---------------+------------------------------------------------------------+
657
658.. table:: TFM-GENERIC-REQUEST-SERVICE-D-2
659 :widths: 10 50
660
661 +---------------+------------------------------------------------------------+
662 | Index | **TFM-GENERIC-REQUEST-SERVICE-D-2** |
663 +---------------+------------------------------------------------------------+
664 | Description | A malicious NS application may provide invalid NS memory |
665 | | addresses as the addresses of input and output data in RoT |
666 | | service requests. |
667 +---------------+------------------------------------------------------------+
668 | Justification | SPE may be unable to achieve full knowledge of NS memory |
669 | | mapping. SPE may fail to capture those invalid NS memory |
670 | | addresses during memory access check since those invalid |
671 | | addresses may not be included in isolation configuration. |
672 | | |
673 | | In that case, SPE will access those invalid NS memory |
674 | | addresses later to read or write data. It may trigger a |
675 | | system error to crash the whole system immediately. |
676 | | |
677 | | The malicious NS application may be blocked by NS MPU from |
678 | | directly accessing that invalid NS memory address. But it |
679 | | may manipulate SPE to access that address instead. |
680 +---------------+------------------------------------------------------------+
681 | Category | Denial of service |
682 +---------------+------------------------------------------------------------+
683 | Mitigation | TF-M executes memory access check to the memory addresses |
684 | | in all the NS requests. |
685 | | |
686 | | On single Armv8-M core platforms, TF-M invokes ``TT`` |
687 | | instructions to execute memory address check. If a NS |
688 | | memory area is not matched in any valid SAU or MPU region, |
689 | | it will be marked as invalid and any access permission is |
690 | | disallowed. Therefore, SPM will reject any NS request |
691 | | containing invalid NS memory addresses and reports it as |
692 | | as a security error. |
693 | | |
694 | | On dual-core platforms, TF-M implements a default memory |
695 | | access check. If a NS memory area is not found in any |
696 | | memory region configured for isolation, it will be marked |
697 | | as invalid and therefore SPM will reject the corresponding |
698 | | NS request. It will be reported as a security error. |
699 | | |
700 | | Dual-core platforms may implement platform specific memory |
701 | | check to replace the default one. It relies on platform |
702 | | specific implementation to capture invalid memory address. |
703 | | It is out of the scope of this document. |
704 +---------------+------------------------------------------------------------+
705 | CVSS Score | 3.2 (Low) |
706 +---------------+------------------------------------------------------------+
707 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:C/C:N/I:N/A:L |
708 | String | |
709 +---------------+------------------------------------------------------------+
710
711RoT services read and write NS data
712-----------------------------------
713
714This section identifies threats on ``DF3`` defined in `Data Flow Diagram`_.
715
Kevin Peng4cdb2082022-03-25 17:53:03 +0800[diff] [blame]716In Library model, RoT services directly read and write NS memory to simplify
717the implementation and decrease latency.
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]718
Kevin Peng4cdb2082022-03-25 17:53:03 +0800[diff] [blame]719In TF-M IPC model, RoT services can either directly access NS memory or rely on
720TF-M SPM to obtain NS input data and send response data back to NS memory.
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]721
722.. _TFM-GENERIC-SECURE-SERVICE-RW-T-1:
723
724.. table:: TFM-GENERIC-SECURE-SERVICE-RW-T-1
725 :widths: 10 50
726
727 +---------------+------------------------------------------------------------+
728 | Index | **TFM-GENERIC-SECURE-SERVICE-RW-T-1** |
729 +---------------+------------------------------------------------------------+
730 | Description | An attacker may tamper NS input data while the RoT service |
731 | | is processing those data. |
732 +---------------+------------------------------------------------------------+
733 | Justification | A RoT service may access NS input data multiple times |
734 | | during its data processing. For example, it may validate |
735 | | or authenticate the NS input data before it performs |
736 | | further processing. |
737 | | |
738 | | If the NS input data remains in NSPE memory during the RoT |
739 | | service execution, an attacker may tamper the NS input |
740 | | data in NSPE memory after the validation passes. |
741 +---------------+------------------------------------------------------------+
742 | Category | Tampering |
743 +---------------+------------------------------------------------------------+
Kevin Peng4cdb2082022-03-25 17:53:03 +0800[diff] [blame]744 | Mitigation | In TF-M IPC model, if RoT services request SPM to read and |
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]745 | | write NS data. TF-M SPM follows [FF-M]_ to copy the NS |
746 | | input data into SPE memory region owned by the RoT |
747 | | service, before the RoT service processes the data. |
748 | | Therefore, the NS input data is protected during the RoT |
749 | | service execution from being tampered. |
750 | | |
Kevin Peng4cdb2082022-03-25 17:53:03 +0800[diff] [blame]751 | | If RoT services can directly access NS memory and read NS |
752 | | input data multiple times during data processing, it is |
753 | | required to review and confirm the implementation of the |
754 | | RoT service copies NS input data into SPE memory area |
755 | | before it processes the data. |
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]756 +---------------+------------------------------------------------------------+
757 | CVSS Score | 3.2 (Low) |
758 +---------------+------------------------------------------------------------+
759 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:C/C:N/I:L/A:N |
760 | String | |
761 +---------------+------------------------------------------------------------+
762
763.. _TFM-GENERIC-SECURE-SERVICE-RW-T-2:
764
765.. table:: TFM-GENERIC-SECURE-SERVICE-RW-T-2
766 :widths: 10 50
767
768 +---------------+------------------------------------------------------------+
769 | Index | **TFM-GENERIC-SECURE-SERVICE-RW-T-2** |
770 +---------------+------------------------------------------------------------+
771 | Description | A malicious NS application may embed secure memory |
772 | | addresses into a structure in RoT service request input |
773 | | vectors, to tamper secure memory which the NS application |
774 | | must not access. |
775 +---------------+------------------------------------------------------------+
776 | Justification | [FF-M]_ limits the total number of input/output vectors to |
777 | | 4. If a RoT service requires more input/output vectors, it |
778 | | may define a parameter structure which embeds multiple |
779 | | input/output buffers addresses. |
780 | | |
781 | | However, as a potential security risk, a malicious NS |
782 | | application can put secure memory addresses into a valid |
783 | | parameter structure to bypass TF-M validation on those |
784 | | memory addresses. |
785 | | |
786 | | The parameter structure can pass TF-M memory access check |
787 | | since itself is valid. However, if the RoT service parses |
788 | | the structure and directly write malicious data from NSPE |
789 | | to the secure memory addresses in parameter structure, the |
790 | | secure data will be tampered. |
791 +---------------+------------------------------------------------------------+
792 | Category | Tampering |
793 +---------------+------------------------------------------------------------+
794 | Mitigation | It should be avoided to embed memory addresses into a |
795 | | single input/output vector. If more than 4 memory |
796 | | addresses are required in a RoT service request, it is |
797 | | recommended to split this request into two or multiple |
798 | | service calls and therefore each service call requires no |
799 | | more than 4 input/output vectors. |
800 | | |
Kevin Peng4cdb2082022-03-25 17:53:03 +0800[diff] [blame]801 | | In TF-M IPC model, if RoT services request SPM to read and |
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]802 | | write NS data. SPM will validate the target addresses and |
803 | | can detect the invalid addresses to mitigate this threat. |
804 | | |
Kevin Peng4cdb2082022-03-25 17:53:03 +0800[diff] [blame]805 | | If RoT services can directly access NS memory, it is |
806 | | required to review and confirm the implementation of RoT |
807 | | service request doesn't embed memory addresses. |
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]808 +---------------+------------------------------------------------------------+
David Hu4a741da2021-03-16 11:44:31 +0800[diff] [blame]809 | CVSS Score | 7.1 (High) |
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]810 +---------------+------------------------------------------------------------+
David Hu4a741da2021-03-16 11:44:31 +0800[diff] [blame]811 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:N/I:H/A:N |
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]812 | String | |
813 +---------------+------------------------------------------------------------+
814
815.. table:: TFM-GENERIC-SECURE-SERVICE-RW-I-1
816 :widths: 10 50
817
818 +---------------+------------------------------------------------------------+
819 | Index | **TFM-GENERIC-SECURE-SERVICE-RW-I-1** |
820 +---------------+------------------------------------------------------------+
821 | Description | Similar to TFM-GENERIC-SECURE-SERVICE-RW-T-2_, a malicious |
822 | | NS application can embed secure memory addresses in a |
823 | | parameter structure in RoT service request input vectors, |
824 | | to read secure data which the NS application must not |
825 | | access. |
826 +---------------+------------------------------------------------------------+
827 | Justification | Similar to the description in |
828 | | TFM-GENERIC-SECURE-SERVICE-RW-T-2_, the secure memory |
829 | | addresses hidden in the RoT service input/output vector |
830 | | structure may bypass TF-M validation. Without a proper |
831 | | check, the RoT service may copy secure data to NSPE |
832 | | according to the secure memory addresses in structure, |
833 | | secure information can be disclosed. |
834 +---------------+------------------------------------------------------------+
835 | Category | Information disclosure |
836 +---------------+------------------------------------------------------------+
837 | Mitigation | It should be avoided to embed memory addresses into a |
838 | | single input/output vector. If more than 4 memory |
839 | | addresses are required in a RoT service request, it is |
840 | | recommended to split this request into two or multiple |
841 | | service calls and therefore each service call requires no |
842 | | more than 4 input/output vectors. |
843 | | |
Kevin Peng4cdb2082022-03-25 17:53:03 +0800[diff] [blame]844 | | In TF-M IPC model, if RoT services request SPM to read and |
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]845 | | write NS data. SPM will validate the target addresses and |
846 | | can detect the invalid addresses to mitigate this threat. |
847 | | |
Kevin Peng4cdb2082022-03-25 17:53:03 +0800[diff] [blame]848 | | If RoT services can directly access NS memory, it is |
849 | | required to review and confirm the implementation of RoT |
850 | | service request doesn't embed memory addresses. |
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]851 +---------------+------------------------------------------------------------+
David Hu4a741da2021-03-16 11:44:31 +0800[diff] [blame]852 | CVSS Score | 7.1 (High) |
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]853 +---------------+------------------------------------------------------------+
David Hu4a741da2021-03-16 11:44:31 +0800[diff] [blame]854 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:N/A:N |
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]855 | String | |
856 +---------------+------------------------------------------------------------+
857
858TF-M returns secure service result
859----------------------------------
860
861This section identifies threats on ``DF4`` defined in `Data Flow Diagram`_.
862
863When RoT service completes the request from NSPE, TF-M returns the success or
864failure error code to NS application.
865
866In single Armv8-M core scenario, TF-M writes the return code value in the
867general purpose register and returns to Non-secure state.
868
869On dual-cpu platforms, TF-M writes the return code to NSPE mailbox message queue
870via mailbox.
871
872.. table:: TFM-GENERIC-RETURN-CODE-I-1
873 :widths: 10 50
874
875 +---------------+------------------------------------------------------------+
876 | Index | **TFM-GENERIC-RETURN-CODE-I-1** |
877 +---------------+------------------------------------------------------------+
878 | Description | SPE may leave secure data in the registers not banked |
879 | | after the SPE completes PSA Client calls and executes |
880 | | ``BXNS`` to switch Armv8-M back to Non-secure state. |
881 +---------------+------------------------------------------------------------+
882 | Justification | If SPE doesn't clean up the secure data in registers not |
883 | | banked before switching into NSPE in Armv8-M core, NSPE |
884 | | can read the SPE context from those registers. |
885 +---------------+------------------------------------------------------------+
886 | Category | Information disclosure |
887 +---------------+------------------------------------------------------------+
888 | Mitigation | In single Armv8-M core scenario, TF-M cleans general |
889 | | purpose registers not banked before switching into NSPE to |
890 | | prevent NSPE probing secure context from the registers. |
891 | | |
Feder Liang9b532c92021-12-09 16:03:18 +0800[diff] [blame]892 | | When FPU is enabled in TF-M, secure FP context belonging to|
893 | | a secure partition will be saved on this partition's stack |
894 | | and cleaned by hardware during context switching. Also TF-M|
895 | | cleans secure FP context in FP registers before switching |
896 | | into NSPE to prevent NSPE from probing secure FP context. |
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]897 +---------------+------------------------------------------------------------+
898 | CVSS Score | 4.3 (Medium) |
899 +---------------+------------------------------------------------------------+
900 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N |
901 | String | |
902 +---------------+------------------------------------------------------------+
903
904NS interrupts preempts SPE execution
905------------------------------------
906
907This section identifies threats on ``DF5`` defined in `Data Flow Diagram`_.
908
909.. table:: TFM-GENERIC-NS-INTERRUPT-I-1
910 :widths: 10 50
911
912 +---------------+------------------------------------------------------------+
913 | Index | **TFM-GENERIC-NS-INTERRUPT-I-1** |
914 +---------------+------------------------------------------------------------+
915 | Description | Shared registers may contain secure data when NS |
916 | | interrupts occur. |
917 +---------------+------------------------------------------------------------+
918 | Justification | The secure data in shared registers should be cleaned up |
919 | | before NSPE can access shared registers. Otherwise, secure |
920 | | data leakage may occur. |
921 +---------------+------------------------------------------------------------+
922 | Category | Information disclosure |
923 +---------------+------------------------------------------------------------+
924 | Mitigation | In single Armv8-M core scenario, Armv8-M architecture |
925 | | automatically cleans up the registers not banked before |
926 | | switching to Non-secure state while taking NS interrupts. |
927 | | |
Feder Liang9b532c92021-12-09 16:03:18 +0800[diff] [blame]928 | | When FPU is enabled in TF-M, with setting of FPCCR_S.TS = 1|
929 | | besides secure FP context in FP caller registers, FP |
930 | | context in FP callee registers will also be cleaned by |
931 | | hardware automatically when NS interrupts occur, to prevent|
932 | | NSPE from probing secure FP context in FP registers. Refer |
933 | | to Armv8-M Architecture Reference Manual[ARM arm]_ for |
934 | | details. |
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]935 | | |
936 | | On dual-cpu platforms, shared registers are implementation |
937 | | defined, such as Inter-Processor Communication registers. |
938 | | Dual-cpu platforms must not store any data which may |
939 | | disclose secure information in the shared registers. |
940 +---------------+------------------------------------------------------------+
941 | CVSS Score | 4.3 (Medium) |
942 +---------------+------------------------------------------------------------+
943 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N |
944 | String | |
945 +---------------+------------------------------------------------------------+
946
947.. table:: TFM-GENERIC-NS-INTERRUPT-D-1
948 :widths: 10 50
949
950 +---------------+------------------------------------------------------------+
951 | Index | **TFM-GENERIC-NS-INTERRUPT-D-1** |
952 +---------------+------------------------------------------------------------+
953 | Description | An attacker may trigger spurious NS interrupts frequently |
954 | | to block SPE execution. |
955 +---------------+------------------------------------------------------------+
956 | Justification | In single Armv8-M core scenario, an attacker may inject a |
957 | | malicious NS application or hijack a NS hardware to |
958 | | frequently trigger spurious NS interrupts to keep |
959 | | preempting SPE and block SPE to perform normal secure |
960 | | execution. |
961 +---------------+------------------------------------------------------------+
962 | Category | Denial of service |
963 +---------------+------------------------------------------------------------+
964 | Mitigation | It is out of scope of TF-M. |
965 | | |
966 | | Assets protected by TF-M won't be leaked. TF-M won't be |
967 | | directly impacted. |
968 +---------------+------------------------------------------------------------+
969 | CVSS Score | 4.0 (Medium) |
970 +---------------+------------------------------------------------------------+
971 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:L |
972 | String | |
973 +---------------+------------------------------------------------------------+
974
975Secure interrupts preempts NSPE execution
976-----------------------------------------
977
978This section identifies threats on ``DF6`` defined in `Data Flow Diagram`_.
979
980.. table:: TFM-GENERIC-S-INTERRUPT-I-1
981 :widths: 10 50
982
983 +---------------+------------------------------------------------------------+
984 | Index | **TFM-GENERIC-S-INTERRUPT-I-1** |
985 +---------------+------------------------------------------------------------+
986 | Description | Shared registers may contain secure data when Armv8-M core |
987 | | switches back to Non-secure state on Secure interrupt |
988 | | return. |
989 +---------------+------------------------------------------------------------+
990 | Justification | Armv8-M architecture doesn't automatically clean up shared |
991 | | registers while returning to Non-secure state during |
992 | | Secure interrupt return. |
993 | | |
994 | | If SPE leaves critical data in the Armv8-M registers not |
995 | | banked, NSPE can read secure context from those registers |
996 | | and secure data leakage may occur. |
997 +---------------+------------------------------------------------------------+
998 | Category | Information disclosure |
999 +---------------+------------------------------------------------------------+
1000 | Mitigation | TF-M saves NPSE context in general purpose register R4~R11 |
1001 | | into secure stack during secure interrupt entry. |
1002 | | After secure interrupt handling completes, TF-M unstacks |
1003 | | NSPE context from secure stack to overwrite secure context |
1004 | | in R4~R11 before secure interrupt return. |
1005 | | |
1006 | | Armv8-M architecture will automatically unstack NSPE |
1007 | | context from non-secure stack to overwrite other registers |
1008 | | not banked, such as R0~R3 and R12, during secure interrupt |
1009 | | return, before NSPE software can access those registers. |
1010 | | |
Feder Liang9b532c92021-12-09 16:03:18 +0800[diff] [blame]1011 | | When FPU is enabled in TF-M, with setting of |
1012 | | FPCCR_S.TS = 1 and FPCCR_S.CLRONRET = 1, besides secure FP |
1013 | | context in FP caller registers, FP context in callee |
1014 | | registers will also be cleaned by hardware automatically |
1015 | | during S exception return, to prevent NSPE from probing |
1016 | | secure FP context in FP registers. Refer to Armv8-M |
1017 | | Architecture Reference Manual [ARM arm]_ for details. |
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]1018 +---------------+------------------------------------------------------------+
1019 | CVSS Score | 4.3 (Medium) |
1020 +---------------+------------------------------------------------------------+
1021 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N |
1022 | String | |
1023 +---------------+------------------------------------------------------------+
1024
1025Miscellaneous threats
1026---------------------
1027
1028This section collects threats irrelevant to the valid TF-M data flows shown
1029above.
1030
1031.. table:: TFM-GENERIC-STACK-SEAL
1032 :widths: 10 50
1033
1034 +---------------+------------------------------------------------------------+
1035 | Index | **TFM-GENERIC-STACK_SEAL** |
1036 +---------------+------------------------------------------------------------+
1037 | Description | Armv8-M processor Secure software Stack Sealing |
1038 | | vulnerability. |
1039 +---------------+------------------------------------------------------------+
1040 | Justification | On Armv8-M based processors with TrustZone, if Secure |
1041 | | software does not properly manage the Secure stacks when |
1042 | | the stacks are created, or when performing non-standard |
1043 | | transitioning between states or modes, for example, |
1044 | | creating a fake exception return stack frame to |
1045 | | de-privilege an interrupt, it is possible for Non-secure |
1046 | | world software to manipulate the Secure Stacks, and |
1047 | | potentially influence Secure control flow. |
1048 | | |
1049 | | Refer to [STACK-SEAL]_ for details. |
1050 +---------------+------------------------------------------------------------+
1051 | Category | Elevation of privilege |
1052 +---------------+------------------------------------------------------------+
1053 | Mitigation | TF-M has implemented common mitigation against stack seal |
1054 | | vulnerability. |
1055 | | |
1056 | | Refer to [ADVISORY-TFMV-1]_ for details on analysis and |
1057 | | mitigation in TF-M. |
1058 +---------------+------------------------------------------------------------+
1059 | CVSS Score | 5.3 (Medium) |
1060 +---------------+------------------------------------------------------------+
1061 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:L/I:L/A:L |
1062 | String | |
1063 +---------------+------------------------------------------------------------+
1064
David Hu4a741da2021-03-16 11:44:31 +0800[diff] [blame]1065.. table:: TFM-GENERIC-SVC-CALL-SP-FETCH
1066 :widths: 10 50
1067
1068 +---------------+------------------------------------------------------------+
1069 | Index | **TFM-GENERIC-SVC-CALL-SP-FETCH** |
1070 +---------------+------------------------------------------------------------+
1071 | Description | Invoking Secure functions from handler mode may cause TF-M |
1072 | | IPC model to behave unexpectedly. |
1073 +---------------+------------------------------------------------------------+
1074 | Justification | On Armv8-M based processors with TrustZone, if NSPE calls |
1075 | | a secure function via Secure Gateway (SG) from non-secure |
1076 | | Handler mode , TF-M selects secure process stack by |
1077 | | mistake for SVC handling. |
1078 | | It will most likely trigger a crash in secure world or |
1079 | | reset the whole system, with a very low likelihood of |
1080 | | overwriting some memory contents. |
1081 +---------------+------------------------------------------------------------+
1082 | Category | Denial of service/Tampering |
1083 +---------------+------------------------------------------------------------+
1084 | Mitigation | TF-M has enhanced implementation to mitigate this |
1085 | | vulnerability. |
1086 | | |
1087 | | Refer to [ADVISORY-TFMV-2]_ for details on analysis and |
1088 | | mitigation in TF-M. |
1089 +---------------+------------------------------------------------------------+
1090 | CVSS Score | 4.5 (Medium) |
1091 +---------------+------------------------------------------------------------+
1092 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:C/C:N/I:L/A:L |
1093 | String | |
1094 +---------------+------------------------------------------------------------+
1095
Feder Liangc89075b2021-11-24 16:01:45 +0800[diff] [blame]1096.. table:: VLLDM instruction security vulnerability
1097 :widths: 10 50
1098
1099 +---------------+------------------------------------------------------------+
1100 | Index | **TFM-GENERIC-FP-VLLDM** |
1101 +---------------+------------------------------------------------------------+
1102 | Description | Secure data in FP registers may be disclosed to NSPE when |
1103 | | VLLDM instruction is abandoned due to an exception mid-way.|
1104 +---------------+------------------------------------------------------------+
1105 | Justification | Refer to [VLLDM Vulnerability]_ for details. |
1106 +---------------+------------------------------------------------------------+
1107 | Category | Tampering/Information disclosure |
1108 +---------------+------------------------------------------------------------+
1109 | Mitigation | In current TF-M implementation, when FPU is enabled in SPE,|
1110 | | TF-M configures NSACR to disable NSPE to access FPU. |
1111 | | Therefore, secure data in FP registers is protected from |
1112 | | NSPE. |
1113 | | |
1114 | | Refer to [VLLDM Vulnerability]_, for details on analysis |
1115 | | and mitigation. |
1116 +---------------+------------------------------------------------------------+
1117 | CVSS Score | 3.4 (Low) |
1118 +---------------+------------------------------------------------------------+
1119 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:U/C:L/I:L/A:N |
1120 | String | |
1121 +---------------+------------------------------------------------------------+
1122
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]1123***************
1124Version control
1125***************
1126
1127.. table:: Version control
1128
1129 +---------+--------------------------------------------------+---------------+
1130 | Version | Description | TF-M version |
1131 +=========+==================================================+===============+
1132 | v0.1 | Initial draft | TF-M v1.1 |
1133 +---------+--------------------------------------------------+---------------+
David Hu4a741da2021-03-16 11:44:31 +0800[diff] [blame]1134 | v1.0 | First version | TF-M v1.2.0 |
1135 +---------+--------------------------------------------------+---------------+
Feder Liangc89075b2021-11-24 16:01:45 +0800[diff] [blame]1136 | v1.1 | Update version | TF-M v1.5.0 |
1137 +---------+--------------------------------------------------+---------------+
Feder Liang9b532c92021-12-09 16:03:18 +0800[diff] [blame]1138 | v1.2 | Update details to align FP support in NSPE. | TF-M v1.5.0 |
1139 +---------+--------------------------------------------------+---------------+
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]1140
1141*********
1142Reference
1143*********
1144
1145.. [Security-Incident-Process] `Security Incident Process <https://developer.trustedfirmware.org/w/collaboration/security_center/reporting/>`_
1146
1147.. [FF-M] `Arm® Platform Security Architecture Firmware Framework 1.0 <https://developer.arm.com/-/media/Files/pdf/PlatformSecurityArchitecture/Architect/DEN0063-PSA_Firmware_Framework-1.0.0-2.pdf?revision=2d1429fa-4b5b-461a-a60e-4ef3d8f7f4b4>`_
1148
Kevin Peng4cdb2082022-03-25 17:53:03 +0800[diff] [blame]1149.. [FF-M 1.1 Extensions] `Arm® Firmware Framework for M 1.1 Extensions <https://documentation-service.arm.com/static/600067c09b9c2d1bb22cd1c5?token=>`_
1150
Anton Komlev3356ba32022-03-31 22:02:11 +0100[diff] [blame]1151.. [DUAL-CPU-BOOT] :doc:`Booting a dual core system </technical_references/design_docs/dual-cpu/booting_a_dual_core_system>`
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]1152
1153.. [CVSS] `Common Vulnerability Scoring System Version 3.1 Calculator <https://www.first.org/cvss/calculator/3.1>`_
1154
1155.. [CVSS_SPEC] `CVSS v3.1 Specification Document <https://www.first.org/cvss/v3-1/cvss-v31-specification_r1.pdf>`_
1156
1157.. [STRIDE] `The STRIDE Threat Model <https://docs.microsoft.com/en-us/previous-versions/commerce-server/ee823878(v=cs.20)?redirectedfrom=MSDN>`_
1158
Anton Komlev3356ba32022-03-31 22:02:11 +0100[diff] [blame]1159.. [SECURE-BOOT] :doc:`Secure boot </technical_references/design_docs/tfm_secure_boot>`
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]1160
Anton Komlev3356ba32022-03-31 22:02:11 +0100[diff] [blame]1161.. [ROLLBACK-PROTECT] :doc:`Rollback protection in TF-M secure boot </technical_references/design_docs/secure_boot_rollback_protection>`
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]1162
Feder Liang9b532c92021-12-09 16:03:18 +0800[diff] [blame]1163.. [ARM arm] `Armv8-M Architecture Reference Manual <https://developer.arm.com/documentation/ddi0553/latest>`_
1164
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]1165.. [STACK-SEAL] `Armv8-M processor Secure software Stack Sealing vulnerability <https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing>`_
1166
Anton Komlev3356ba32022-03-31 22:02:11 +0100[diff] [blame]1167.. [ADVISORY-TFMV-1] :doc:`Advisory TFMV-1 </security/security_advisories/stack_seal_vulnerability>`
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]1168
Anton Komlev3356ba32022-03-31 22:02:11 +0100[diff] [blame]1169.. [ADVISORY-TFMV-2] :doc:`Advisory TFMV-2 </security/security_advisories/svc_caller_sp_fetching_vulnerability>`
David Hu4a741da2021-03-16 11:44:31 +0800[diff] [blame]1170
Feder Liangc89075b2021-11-24 16:01:45 +0800[diff] [blame]1171.. [VLLDM Vulnerability] : `VLLDM instruction Security Vulnerability <https://developer.arm.com/support/arm-security-updates/vlldm-instruction-security-vulnerability>`_
1172
David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]1173--------------------
1174
Kevin Peng4cdb2082022-03-25 17:53:03 +0800[diff] [blame]1175*Copyright (c) 2020-2022 Arm Limited. All Rights Reserved.*