| Gyorgy Szing | db9783c | 2019-04-17 21:08:48 +0200 | [diff] [blame] | 1 | ########################### |
| 2 | Musca-B1 Platform Specifics |
| 3 | ########################### |
| 4 | |
| 5 | **************** |
| 6 | DAPLink Firmware |
| 7 | **************** |
| Gabor Abonyi | 4aa3930 | 2022-07-14 16:33:13 +0200 | [diff] [blame] | 8 | The code on Musca-B1 is running from embedded flash. Make sure that the DAPLink |
| Gyorgy Szing | db9783c | 2019-04-17 21:08:48 +0200 | [diff] [blame] | 9 | FW for eFlash is downloaded to the board. You can find on the |
| Nicola Mazzucato | 9eadf7f | 2025-06-03 11:10:19 +0100 | [diff] [blame] | 10 | `Arm Developer page <https://developer.arm.com/documentation/110409/0100/Musca-B1-firmware-update-and-boot-recovery>`__ |
| Gyorgy Szing | db9783c | 2019-04-17 21:08:48 +0200 | [diff] [blame] | 11 | A short description of how to update the DAPLink FW can be found there as well. |
| 12 | |
| Minos Galanakis | fc6804e | 2020-03-10 11:03:34 +0000 | [diff] [blame] | 13 | .. Note:: |
| 14 | Warm reset of eFlash is not supported on Musca_B1. TF-M may not boot after |
| 15 | a warm reset. Further information on the hardware limitation can be |
| Nicola Mazzucato | 9eadf7f | 2025-06-03 11:10:19 +0100 | [diff] [blame] | 16 | found on `Arm Developer page <https://developer.arm.com/documentation/110409/0100/Musca-B1-warm-reset-of-eFlash>`__. |
| Minos Galanakis | fc6804e | 2020-03-10 11:03:34 +0000 | [diff] [blame] | 17 | |
| Miklos Balint | c7b1b6c | 2019-04-24 12:38:36 +0200 | [diff] [blame] | 18 | ******************** |
| 19 | Platform pin service |
| 20 | ******************** |
| 21 | |
| 22 | This service is designed to perform secure pin services of the platform |
| 23 | (e.g alternate function setting, pin mode setting, etc). |
| 24 | The service uses the IOCTL API of TF-M's Platform Service, which allows the |
| 25 | non-secure application to make pin service requests on Musca B1 based on a |
| 26 | generic service request delivery mechanism. |
| 27 | |
| Amjad Ouled-Ameur | 704cc76 | 2025-06-20 17:05:02 +0100 | [diff] [blame] | 28 | ******************** |
| 29 | Musca B1 Default CPU |
| 30 | ******************** |
| 31 | |
| 32 | Musca B1 is a dual core platform (being based on the `SSE-200 subsystem <https://developer.arm.com/documentation/101104/0200/introduction/about-the-sse-200>`__), |
| 33 | boot ROM code uses CPU0 running on 40.96MHz, while TF-M switches to CPU1 running on 163.84MHz. |
| 34 | An additional benefit to switching the default core is that CPU1 can access SRAM3 |
| 35 | as Tightly Coupled Memory (TCM), while CPU0 can't. |
| 36 | When the core switch happens, CPU0 sleeps in a WFI loop to save power. |
| 37 | |
| 38 | More information can be found in the following `patchset <https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/39616>`__. |
| 39 | |
| Gyorgy Szing | db9783c | 2019-04-17 21:08:48 +0200 | [diff] [blame] | 40 | -------------- |
| 41 | |
| Nicola Mazzucato | 9eadf7f | 2025-06-03 11:10:19 +0100 | [diff] [blame] | 42 | *Copyright (c) 2017-2025, Arm Limited. All rights reserved.* |