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Gabor Abonyif371d272022-07-19 13:54:05 +02001###########################
2Musca-S1 Platform Specifics
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4
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6DAPLink Firmware
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Dávid Házi6cf78962023-02-03 10:23:37 +01008The code on Musca-S1 is running from on-chip eMRAM (2MB non-volatile bootable memory).
9Make sure that the DAPLink FW for QSPI/MRAM is downloaded to the board. You can find on the
Gabor Abonyif371d272022-07-19 13:54:05 +020010`Arm Community page <https://community.arm.com/oss-platforms/w/docs/463/musca-s1-firmware-update-qspi-mram-boot-recovery>`__
11A short description of how to update the DAPLink FW can be found there as well.
12
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14Platform pin service
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16
17This service is designed to perform secure pin services of the platform
18(e.g alternate function setting, pin mode setting, etc).
19The service uses the IOCTL API of TF-M's Platform Service, which allows the
20non-secure application to make pin service requests on Musca S1 based on a
21generic service request delivery mechanism.
22
Amjad Ouled-Ameurb13961e2025-05-29 09:51:33 +020023********************
24Musca S1 Default CPU
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26
27Musca S1 is a dual core platform (being based on the `SSE-200 subsystem <https://developer.arm.com/documentation/101104/0200/introduction/about-the-sse-200>`__),
28boot ROM code uses CPU0 running on 50MHz, while TF-M switches to CPU1 running on 200MHz.
29An additional benefit to switching the default core is that CPU1 can access SRAM3
30as Tightly Coupled Memory (TCM), while CPU0 can't.
31When the core switch happens, CPU0 sleeps in a WFI loop to save power.
32
33More information can be found in the following `patchset <https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/38198/3>`__.
34
Gabor Abonyif371d272022-07-19 13:54:05 +020035--------------
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Dávid Házi6cf78962023-02-03 10:23:37 +010037*Copyright (c) 2023, Arm Limited. All rights reserved.*