blob: fdadf435b1dee2dfbb9d6527ae749ef82e62b3f3 [file] [log] [blame]
Anton Komlev341668b2023-12-13 21:36:10 +00001#######
2Roadmap
3#######
4
5TF-M has been under active development since it was launched in Q1'18. It is
6being designed to include
7
81. Secure boot ensuring integrity of runtime images and responsible for firmware upgrade.
Anton Komlev28eef362024-04-22 17:58:32 +010092. Runtime firmware consisting of TF-M Core is responsible for secure isolation,
Anton Komlev341668b2023-12-13 21:36:10 +000010 execution and communication aspects. and a set of Secure Services providing
11 services to the Non-Secure and Secure Applications. The secures services
12 currently supported are Secure Storage, Cryptography, Firmware Update,
13 Attestation and Platform Services
14
15If you are interested in collaborating on any of the roadmap features or other
16features, please mail TF-M mailing list
17
18******************
19Supported Features
20******************
21- PSA Firmware Framework v1.0, 1.1 Extension including IPC and SFN modes.
22- PSA Level1, 2 and 3 Isolation.
23- Secure Boot (mcuboot upstream) including generic fault injection mitigations
24- PSA Protected Storage, Internal Trusted Storage v1.0 and Encrypted ITS
25- PSA Cryptov1.0 (uses Mbed TLS v3.4.0)
26- PSA Initial Attestation Service v1.0
27- PSA Firmware Update v1.0
28- PSA ADAC Specification Implementation
Anton Komlev28eef362024-04-22 17:58:32 +010029- Base Config, kconfig based configuration
Anton Komlev341668b2023-12-13 21:36:10 +000030- Profile Small, Medium, ARoT-less Medium, Large
31- Secure Partition Interrupt Handling, Pre-emption of SPE execution
Anton Komlev341668b2023-12-13 21:36:10 +000032- Dual CPU
33- Open Continuous Integration (CI) System
34- Boot and Runtime Crypto Hardware Integration
35- Fault Injection Handling library to mitigate against physical attacks
36- Threat Model
37- Arm v8.1-M Privileged Execute Never (PXN) attribute and Thread reentrancy disabled (TRD)
38- FPU, MVE Support
39- CC-312 PSA Cryptoprocessor Driver Interface
Anton Komlevc594e262024-01-15 12:07:14 +000040- Secure Storage - Key Diversification Enhancements
41- Build System - Separate Secure and Non-Secure builds
Anton Komlev28eef362024-04-22 17:58:32 +010042- PSA Crypto layer for mcuboot/BL2
Anton Komleve7e27a82025-02-11 19:19:37 +000043- Support LLVM Embedded Toolchain for Arm
Anton Komlev837df132025-04-11 13:03:29 +010044- MISRA testing/documentation
45- Switch to using upstream t_cose
46- Remote Test Infrastructure
Anton Komlev341668b2023-12-13 21:36:10 +000047
48******
Anton Komlev837df132025-04-11 13:03:29 +010049CQ2'25
Anton Komlev341668b2023-12-13 21:36:10 +000050******
Anton Komlevc594e262024-01-15 12:07:14 +000051- Supporting multiple clients (Hybrid Platforms) i.e. TF-M supporting multiple on
Anton Komlev341668b2023-12-13 21:36:10 +000052 core and off core clients on heterogeneous (e.g. Cortex-A + Cortex-M platforms)
Anton Komleve7e27a82025-02-11 19:19:37 +000053- TF-M v2.2.0 release
54- Update to Mbed TLS3.6.3
Anton Komlev341668b2023-12-13 21:36:10 +000055
56******
57Future
58******
Anton Komlevd0303d82024-10-01 16:03:00 +010059- Integrate TF-PSACrypto
Anton Komlev837df132025-04-11 13:03:29 +010060- TF-M v2.3.0
61- Image encryption via. PSA Crypto in mcuboot
Anton Komlev28eef362024-04-22 17:58:32 +010062- Implement support for multiple clients (Hybrid Platforms) contd.
63- Build System Enhancements - Simplify build scripts
Anton Komlev341668b2023-12-13 21:36:10 +000064- TF-M Performance - Further Benchmarking and Optimization
65- Scheduler - Multiple Secure Context Implementation
Anton Komlev341668b2023-12-13 21:36:10 +000066- PSA FWU Service Enhancements
67- PSA ADAC Spec - Enhancements and Testing
68- Arm v8.1-M Unprevileged Debug
Anton Komlevc594e262024-01-15 12:07:14 +000069- [Secure Storage] Extended PSA APIs
Anton Komlev341668b2023-12-13 21:36:10 +000070- [Audit Logs] Secure Storage, Policy Manager
71- PSA FF Lifecycle API
72- Fuzz Testing
73
74--------------
75
Anton Komlevc594e262024-01-15 12:07:14 +000076*Copyright (c) 2017-2024, Arm Limited. All rights reserved.*