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David Hudb067eb2020-09-18 09:55:11 +0800[diff] [blame]1#######################################
2Trusted Firmware-M Generic Threat Model
3#######################################
4
5************
6Introduction
7************
8
9This document introduces a generic thread model of Trusted Firmware-M (TF-M).
10This generic thread model provides an overall analysis of TF-M implementation
11and identifies general threats and mitigation.
12
13.. note::
14
15 If you think a security vulnerability is found, please follow
16 Trustedfirmware.org [Security-Incident-Process]_ to contact TF-M security
17 team.
18
19Scope
20=====
21
22TF-M supports diverse models and topologies. It also implements multiple
23isolation levels. Each case may focus on different target of evaluation (TOE)
24and identify different assets and threats.
25TF-M implementation consists of several secure services, defined as
26Root of Trust (RoT) service. Those RoT services belong to diverse RoT
27(Application RoT or PSA RoT) and access different assets and hardware. Therefore
28each RoT service may require a dedicated threat model.
29
30The analysis on specific models, topologies or RoT services may be covered in
31dedicated thread model documents. Those threat models are out of the scope of
32this document.
33
34Methodology
35===========
36
37The threat modeling in this document follows the process listed below to
38build up the threat model.
39
40- Target of Evaluation (TOE)
41- Assets identification
42- Data Flow Diagram (DFD)
43- Threats Prioritization
44- Threats identification
45
46TOE is the entity on which threat modeling is performed. The logic behind this
47process is to firstly investigate the TOE which could be a system, solution or
48use case. This first step helps to identify the assets to be protected in TOE.
49
50According to TOE and assets, Trust Boundaries can be determined. The Data Flow
51Diagram (DFD) across Trust Boundaries is then defined to help identify the
52threats.
53
54Those threats should be prioritized based on a specific group of principals and
55metrics. The principals and metrics should also be specified.
56
57********************
58Target of Evaluation
59********************
60
61A typical TF-M system diagram from a high-level overview is shown below. TF-M is
62running in the Secure Processing Environment (SPE) and NS software is running in
63Non-secure Processing Environment (NSPE). For more details, please refer to
64Platform Security Architecture Firmware Framework for M (FF-M) [FF-M]_.
65
66.. figure:: TF-M-block-diagram.png
67
68The TOE in this general model is the SPE, including TF-M and other components
69running in SPE.
70
71The TOE can vary in different TF-M models, RoT services and usage scenarios.
72Refer to dedicated thread models for the specific TOE definitions.
73
74********************
75Asset identification
76********************
77
78In this threat model, assets include the general items listed below:
79
80- Hardware Root of Trust data, e.g.
81
82 - Hardware Unique Key (HUK)
83 - Root authentication key
84 - Other embedded root keys
85
86- Software RoT data, e.g.
87
88 - Secure Partition Manager (SPM) code and data
89 - Secure partition code and data
90 - NSPE data stored in SPE
91 - Data generated in SPE as requested by NSPE
92
93- Availability of entire RoT service
94
95- Secure logs, including event logs
96
97Assets may vary in different use cases and implementations. Additional assets
98can be defined in an actual usage scenario and a dedicated threat model.
99
100For example, in a network camera use case, the following data can be defined as
101assets too:
102
103- Certificate for connecting to cloud
104- Session keys for encryption/decryption in the communication with cloud
105- Keys to encrypt/decrypt the videos and photos
106
107*****************
108Data Flow Diagram
109*****************
110
111The Trust Boundary isolates SPE from NSPE, according to the TOE definition in
112`Target of Evaluation`_. The Trust Boundary mapped to block diagram is shown
113in the figure below. Other modules inside SPE stay in the same TOE as TF-M does.
114
115Valid Data flows across the Trust Boundary are also shown in the figure below.
116This thread model only focuses on the data flows related to TF-M.
117
118.. figure:: overall-DFD.png
119
120More details of data flows are listed below.
121
122.. _data-flow-table:
123
124.. table:: TF-M Data Flows between NSPE and SPE
125
126 +-----------+----------------------------------------------------------------+
127 | Data flow | Description |
128 +===========+================================================================+
129 | ``DF1`` | TF-M initializes NS entry and activates NSPE. |
130 | | |
131 | | - On single Armv8-M core platforms, TF-M will hand over the |
132 | | control to Non-secure state. |
133 | | - On dual-cpu platforms, Secure core starts NS core booting. |
134 +-----------+----------------------------------------------------------------+
135 | ``DF2`` | NSPE requests TF-M RoT services. |
136 | | |
137 | | - In TF-M Library model, NS invokes Secure Function calls |
138 | | - In TF-M IPC model, NS invokes PSA Client calls based on IPC |
139 | | protocol defined in [FF-M]_. |
140 | | |
141 | | In single Armv8-M core scenarios, SG instruction is executed |
142 | | in Non-secure Callable region to trigger a transition from |
143 | | Non-secure state to Secure state. |
144 | | |
145 | | On dual-cpu platforms, non-secure core sends PSA Client calls |
146 | | to secure core via mailbox. |
147 +-----------+----------------------------------------------------------------+
148 | ``DF3`` | Secure Partitions fetch input data from NS and write back |
149 | | output data to NS. |
150 | | |
151 | | In TF-M IPC model, as required in [FF-M]_, Secure Partitions |
152 | | should not directly access NSPE memory. Instead, RoT services |
153 | | relies on TF-M SPM to access NSPE memory. |
154 +-----------+----------------------------------------------------------------+
155 | ``DF4`` | TF-M returns RoT service results to NSPE after NS request to |
156 | | RoT service is completed. |
157 | | |
158 | | In single Armv8-M core scenarios, it also trigger a transition |
159 | | from Secure state back to Non-secure state. |
160 | | |
161 | | On dual-cpu platforms, secure core returns the result to |
162 | | non-secure core via mailbox. |
163 +-----------+----------------------------------------------------------------+
164 | ``DF5`` | Non-secure interrupts preempt SPE execution in single Armv8-M |
165 | | core scenarios. |
166 +-----------+----------------------------------------------------------------+
167 | ``DF6`` | Secure interrupts preempt NSPE execution in single Armv8-M |
168 | | core scenarios. |
169 +-----------+----------------------------------------------------------------+
170
171.. note::
172
173 All the other data flows across the Trusted Boundary besides the valid ones
174 mentioned above should be prohibited by default.
175 Proper isolation must be configured to prevent NSPE directly accessing SPE.
176
177 Threats irrelevant to data flows in
178 :ref:`TF-M Data Flows between NSPE and SPE <data-flow-table>` may be specified
179 in `Miscellaneous threats`_.
180
181Data flows inside SPE (informative)
182===================================
183
184Since all the SPE components stay in the TOE within the same Trust Boundary in
185this threat model, the data flows between SPE components are not covered in this
186threat model. Instead, those data flows and corresponding threats will be
187identified in the dedicated threat model documents of TF-M RoT services and
188usage scenarios.
189
190Those data flows inside SPE include following examples:
191
192- Data flows between TF-M and BL2
193- Data flows between RoT services and SPM
194- Data flows between RoT services and corresponding secure hardware and assets,
195 such as secure storage device, crypto hardware accelerator and Hardware Unique
196 Key (HUK).
197
198*********************
199Threat identification
200*********************
201
202Threat priority
203===============
204
205Threat priority is indicated by the score calculated via Common Vulnerability
206Scoring System (CVSS) Version 3.1 [CVSS]_. The higher the threat scores, the
207greater severity the threat is with and the higher the priority is.
208
209CVSS scores can be mapped to qualitative severity ratings defined in CVSS 3.1
210specification [CVSS_SPEC]_. This threat model follows the same mapping between
211CVSS scores and threat priority rating.
212
213As a generic threat model, this document focuses on *Base Score* which reflects
214the constant and general severity of a threat according to its intrinsic
215characteristics.
216
217The *Impacted Component* defined in [CVSS_SPEC]_ refers to the assets listed in
218`Asset identification`_.
219
220Threats and mitigation list
221===========================
222
223This section lists generic threats and corresponding mitigation, based on the
224the analysis of data flows in `Data Flow Diagram`_.
225
226Threats are identified following ``STRIDE`` model. Please refer to [STRIDE]_ for
227more details.
228
229The field ``CVSS Score`` reflects the threat priority defined in
230`Threat priority`_. The field ``CVSS Vector String`` contains the textual
231representation of the CVSS metric values used to score the threat. Refer to
232[CVSS_SPEC]_ for more details of CVSS vector string.
233
234.. note::
235
236 A generic threat may have different behaviors and therefore require different
237 mitigation, in diverse TF-M models and usage scenarios.
238
239 This threat model document focuses on general analysis of the following
240 threats. For the details in a specific configuration and usage scenario,
241 please refer to the dedicated threat model document.
242
243NS entry initialization
244-----------------------
245
246This section identifies threats on ``DF1`` defined in `Data Flow Diagram`_.
247
248.. table:: TFM-GENERIC-NS-INIT-T-1
249 :widths: 10 50
250
251 +---------------+------------------------------------------------------------+
252 | Index | **TFM-GENERIC-NS-INIT-T-1** |
253 +---------------+------------------------------------------------------------+
254 | Description | The NS image can be tampered by an attacker |
255 +---------------+------------------------------------------------------------+
256 | Justification | An attack may tamper the NS image to inject malicious code |
257 +---------------+------------------------------------------------------------+
258 | Category | Tampering |
259 +---------------+------------------------------------------------------------+
260 | Mitigation | By default TF-M relies on MCUBoot to validate NS image. |
261 | | The validation of NS image integrity and authenticity is |
262 | | completed in secure boot before jumping to NS entry or |
263 | | booting up NS core. |
264 | | Refer to [SECURE-BOOT]_ for more details. |
265 | | |
266 | | The validation may vary in diverse vendor platforms |
267 | | specific Chain of Trust (CoT) implementation. |
268 +---------------+------------------------------------------------------------+
269 | CVSS Score | 3.5 (Low) |
270 +---------------+------------------------------------------------------------+
271 | CVSS Vector | CVSS:3.1/AV:P/AC:L/PR:N/UI:N/S:U/C:L/I:L/A:N |
272 | String | |
273 +---------------+------------------------------------------------------------+
274
275.. table:: TFM-GENERIC-NS-INIT-T-2
276 :widths: 10 50
277
278 +---------------+------------------------------------------------------------+
279 | Index | **TFM-GENERIC-NS-INIT-T-2** |
280 +---------------+------------------------------------------------------------+
281 | Description | An attacker may replace the current NS image with an older |
282 | | version. |
283 +---------------+------------------------------------------------------------+
284 | Justification | The attacker downgrades the NS image with an older version |
285 | | which has been deprecated due to known security issues. |
286 | | |
287 | | The older version image can pass the image signature |
288 | | validation and its vulnerabilities can be exploited by |
289 | | attackers. |
290 +---------------+------------------------------------------------------------+
291 | Category | Tampering |
292 +---------------+------------------------------------------------------------+
293 | Mitigation | TF-M relies on MCUBoot to perform anti-rollback |
294 | | protection. |
295 | | |
296 | | TF-M defines a non-volatile counter API to support |
297 | | anti-rollback. Each platform must implement it using |
298 | | specific trusted hardware non-volatile counters. |
299 | | For more details, refer to [ROLLBACK-PROTECT]_. |
300 | | |
301 | | The anti-rollback protection implementation can vary on |
302 | | diverse platforms. |
303 +---------------+------------------------------------------------------------+
304 | CVSS Score | 3.5 (Low) |
305 +---------------+------------------------------------------------------------+
306 | CVSS Vector | CVSS:3.1/AV:P/AC:L/PR:N/UI:N/S:U/C:L/I:L/A:N |
307 | String | |
308 +---------------+------------------------------------------------------------+
309
310.. table:: TFM-GENERIC-NS-INIT-T-I-1
311 :widths: 10 50
312
313 +---------------+------------------------------------------------------------+
314 | Index | **TFM-GENERIC-NS-INIT-T-I-1** |
315 +---------------+------------------------------------------------------------+
316 | Description | If SPE doesn't complete isolation configuration before |
317 | | NSPE starts, NSPE can access secure regions which it is |
318 | | disallowed to. |
319 +---------------+------------------------------------------------------------+
320 | Justification | Secure data can be tampered or disclosed if NSPE is |
321 | | activated and accesses secure regions before isolation |
322 | | configuration is completed by SPE. |
323 +---------------+------------------------------------------------------------+
324 | Category | Tampering/Information disclosure |
325 +---------------+------------------------------------------------------------+
326 | Mitigation | SPE must complete and enable proper isolation to protect |
327 | | secure regions from being accessed by NSPE, before jumping |
328 | | to NS entry or booting up NS core. |
329 | | |
330 | | TF-M executes isolation configuration at early stage of |
331 | | secure initialization before NS initialization starts. |
332 | | |
333 | | On dual-cpu platform, platform specific initialization |
334 | | must halt NS core until isolation is completed, as defined |
335 | | in [DUAL-CPU-BOOT]_. |
336 | | |
337 | | TF-M defines isolation configuration HALs for platform |
338 | | implementation. The specific isolation configuration |
339 | | depends on platform specific implementation. |
340 +---------------+------------------------------------------------------------+
341 | CVSS Score | 9.0 (Critical) |
342 +---------------+------------------------------------------------------------+
343 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:N |
344 | String | |
345 +---------------+------------------------------------------------------------+
346
347.. table:: TFM-GENERIC-NS-INIT-T-I-2
348 :widths: 10 50
349
350 +---------------+------------------------------------------------------------+
351 | Index | **TFM-GENERIC-NS-INIT-T-I-2** |
352 +---------------+------------------------------------------------------------+
353 | Description | If SPE doesn't complete isolation configuration before |
354 | | NSPE starts, NSPE can control devices or peripherals which |
355 | | it is disallowed to. |
356 +---------------+------------------------------------------------------------+
357 | Justification | On some platforms, devices and peripherals can be |
358 | | configured as Secure state in runtime. If security status |
359 | | configuration of those device and peripherals are not |
360 | | properly completed before NSPE starts, NSPE can control |
361 | | those device and peripherals and may be able to tamper |
362 | | data or access secure data. |
363 +---------------+------------------------------------------------------------+
364 | Category | Tampering/Information disclosure |
365 +---------------+------------------------------------------------------------+
366 | Mitigation | SPE must complete and enable proper configuration and |
367 | | isolation to protect critical devices and peripherals from |
368 | | being accessed by NSPE, before jumping to NS entry or |
369 | | booting up NS core. |
370 | | |
371 | | TF-M executes isolation configuration of devices and |
372 | | peripherals at early stage of secure initialization before |
373 | | NS initialization starts. |
374 | | |
375 | | The specific isolation configuration depends on platform |
376 | | specific implementation. |
377 +---------------+------------------------------------------------------------+
378 | CVSS Score | 9.0 (Critical) |
379 +---------------+------------------------------------------------------------+
380 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:N |
381 | String | |
382 +---------------+------------------------------------------------------------+
383
384.. table:: TFM-GENERIC-NS-INIT-I-2
385 :widths: 10 50
386
387 +---------------+------------------------------------------------------------+
388 | Index | **TFM-GENERIC-NS-INIT-I-2** |
389 +---------------+------------------------------------------------------------+
390 | Description | If SPE leaves some SPE information in non-secure memory |
391 | | or shared registers when NSPE starts, NSPE may access |
392 | | those SPE information. |
393 +---------------+------------------------------------------------------------+
394 | Justification | If NSPE can access those SPE information from shared |
395 | | registers or non-secure memory, secure information may be |
396 | | disclosed. |
397 +---------------+------------------------------------------------------------+
398 | Category | Information disclosure |
399 +---------------+------------------------------------------------------------+
400 | Mitigation | SPE must clean up the secure information from shared |
401 | | registers before NS starts. |
402 | | |
403 | | TF-M invalidates registers not banked before handing over |
404 | | the system to NSPE on single Armv8-M platform. |
405 | | |
406 | | On dual-cpu platforms, shared registers are implementation |
407 | | defined, such as Inter-Processor Communication registers. |
408 | | Dual-cpu platforms must not store any data which may |
409 | | disclose secure information in the shared registers. |
410 | | |
411 | | SPE must avoid storing SPE information in non-secure |
412 | | memory. |
413 +---------------+------------------------------------------------------------+
414 | CVSS Score | 4.3 (Medium) |
415 +---------------+------------------------------------------------------------+
416 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N |
417 | String | |
418 +---------------+------------------------------------------------------------+
419
420.. table:: TFM-GENERIC-NS-INIT-D-1
421 :widths: 10 50
422
423 +---------------+------------------------------------------------------------+
424 | Index | **TFM-GENERIC-NS-INIT-D-1** |
425 +---------------+------------------------------------------------------------+
426 | Description | An attacker may block NS to boot up |
427 +---------------+------------------------------------------------------------+
428 | Justification | An attacker may block NS to boot up, such as by corrupting |
429 | | NS image, to stop the whole system from performing normal |
430 | | functionalities. |
431 +---------------+------------------------------------------------------------+
432 | Category | Denial of service |
433 +---------------+------------------------------------------------------------+
434 | Mitigation | No SPE information will be disclosed and TF-M won't be |
435 | | directly impacted. |
436 | | |
437 | | It relies on NSPE and platform specific implementation to |
438 | | mitigate this threat. It is out of scope of this threat |
439 | | model. |
440 +---------------+------------------------------------------------------------+
441 | CVSS Score | 4.0 (Medium) |
442 +---------------+------------------------------------------------------------+
443 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:L |
444 | String | |
445 +---------------+------------------------------------------------------------+
446
447NSPE requests TF-M secure service
448---------------------------------
449
450This section identifies threats on ``DF2`` defined in `Data Flow Diagram`_.
451
452.. table:: TFM-GENERIC-REQUEST-SERVICE-S-1
453 :widths: 10 50
454
455 +---------------+------------------------------------------------------------+
456 | Index | **TFM-GENERIC-REQUEST-SERVICE-S-1** |
457 +---------------+------------------------------------------------------------+
458 | Description | A malicious NS application may pretend as a secure client |
459 | | to access secure data which NSPE must not directly access. |
460 +---------------+------------------------------------------------------------+
461 | Justification | [FF-M]_ defines ``Client ID`` to distinguish clients which |
462 | | request RoT services. Secure clients are assigned with |
463 | | positive IDs and non-secure clients are assigned with |
464 | | negative ones. |
465 | | |
466 | | A malicious NS application may provide a positive |
467 | | ``Client ID`` to pretend as a secure client to access |
468 | | secure data. |
469 +---------------+------------------------------------------------------------+
470 | Category | Spoofing |
471 +---------------+------------------------------------------------------------+
472 | Mitigation | TF-M checks the ``Client ID`` from NSPE. If the NS |
473 | | ``Client ID`` is not a valid one, TF-M will report this as |
474 | | a security error. |
475 +---------------+------------------------------------------------------------+
476 | CVSS Score | 8.4 (High) |
477 +---------------+------------------------------------------------------------+
478 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:N |
479 | String | |
480 +---------------+------------------------------------------------------------+
481
482.. table:: TFM-GENERIC-REQUEST-SERVICE-T-1
483 :widths: 10 50
484
485 +---------------+------------------------------------------------------------+
486 | Index | **TFM-GENERIC-REQUEST-SERVICE-T-1** |
487 +---------------+------------------------------------------------------------+
488 | Description | An attacker in NSPE may tamper the service request input |
489 | | or output vectors between check and use |
490 | | (Time-Of-Check-to-Time-Of-Use (TOCTOU)). |
491 +---------------+------------------------------------------------------------+
492 | Justification | If SPE validates the content in input/output vectors |
493 | | locally in NSPE memory, an attacker in NSPE can have a |
494 | | chance to tamper the content after the validation |
495 | | successfully passes. Then SPE will provide RoT service |
496 | | according to the corrupted parameters and it may cause |
497 | | further security issues. |
498 +---------------+------------------------------------------------------------+
499 | Category | Tampering |
500 +---------------+------------------------------------------------------------+
501 | Mitigation | In TF-M implementation, the validation of NS input/output |
502 | | vectors are only executed after those vectors are copied |
503 | | from NSPE into SPE. It prevents an attack from NSPE to |
504 | | tamper those parameters after validation in TF-M. |
505 +---------------+------------------------------------------------------------+
506 | CVSS Score | 7.8 (High) |
507 +---------------+------------------------------------------------------------+
508 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:C/C:H/I:H/A:N |
509 | String | |
510 +---------------+------------------------------------------------------------+
511
512.. table:: TFM-GENERIC-REQUEST-SERVICE-T-2
513 :widths: 10 50
514
515 +---------------+------------------------------------------------------------+
516 | Index | **TFM-GENERIC-REQUEST-SERVICE-T-2** |
517 +---------------+------------------------------------------------------------+
518 | Description | A malicious NS application may request to tamper data |
519 | | belonging to SPE. |
520 +---------------+------------------------------------------------------------+
521 | Justification | A malicious NS application may request SPE RoT services to |
522 | | write malicious value to SPE data. The malicious NS |
523 | | application may try to tamper SPE assets, such as keys, or |
524 | | modify configurations in SPE. The SPE data belongs to |
525 | | components in SPE and must not be accessed by NSPE. |
526 +---------------+------------------------------------------------------------+
527 | Category | Tampering |
528 +---------------+------------------------------------------------------------+
529 | Mitigation | TF-M executes memory access check to all the RoT service |
530 | | requests. If a request doesn't have enough permission to |
531 | | access the target memory region, TF-M will refuse this |
532 | | request and assert a security error. |
533 +---------------+------------------------------------------------------------+
534 | CVSS Score | 7.1 (High) |
535 +---------------+------------------------------------------------------------+
536 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:N/I:H/A:N |
537 | String | |
538 +---------------+------------------------------------------------------------+
539
540.. table:: TFM-GENERIC-REQUEST-SERVICE-R-1
541 :widths: 10 50
542
543 +---------------+------------------------------------------------------------+
544 | Index | **TFM-GENERIC-REQUEST-SERVICE-R-1** |
545 +---------------+------------------------------------------------------------+
546 | Description | A NS application may repudiate that it has requested |
547 | | services from a RoT service. |
548 +---------------+------------------------------------------------------------+
549 | Justification | A malicious NS application may call a RoT service to |
550 | | access critical data in SPE, which it is disallowed to, |
551 | | via a non-public vulnerability. It may refuse to admit |
552 | | that it has accessed that data. |
553 +---------------+------------------------------------------------------------+
554 | Category | Repudiation |
555 +---------------+------------------------------------------------------------+
556 | Mitigation | TF-M implements an event logging secure service to record |
557 | | the critical events, such as the access to critical data. |
558 +---------------+------------------------------------------------------------+
559 | CVSS Score | 0.0 (None) |
560 +---------------+------------------------------------------------------------+
561 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:N/I:N/A:N |
562 | String | |
563 +---------------+------------------------------------------------------------+
564
565.. table:: TFM-GENERIC-REQUEST-SERVICE-I-1
566 :widths: 10 50
567
568 +---------------+------------------------------------------------------------+
569 | Index | **TFM-GENERIC-REQUEST-SERVICE-I-1** |
570 +---------------+------------------------------------------------------------+
571 | Description | A malicious NS application may request to read data |
572 | | belonging to SPE. |
573 +---------------+------------------------------------------------------------+
574 | Justification | A malicious NS application may request SPE RoT services to |
575 | | copy SPE data to NS memory. The SPE data belongs to |
576 | | components in SPE and must not be disclosed to NSPE, such |
577 | | as root keys. |
578 +---------------+------------------------------------------------------------+
579 | Category | Information disclosure |
580 +---------------+------------------------------------------------------------+
581 | Mitigation | TF-M executes memory access check to all the RoT service |
582 | | requests. If a request doesn't have enough permission to |
583 | | access the target memory region, TF-M will refuse this |
584 | | request and assert a security error. |
585 +---------------+------------------------------------------------------------+
586 | CVSS Score | 7.1 (High) |
587 +---------------+------------------------------------------------------------+
588 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:N/A:N |
589 | String | |
590 +---------------+------------------------------------------------------------+
591
592.. table:: TFM-GENERIC-REQUEST-SERVICE-T-I-1
593 :widths: 10 50
594
595 +---------------+------------------------------------------------------------+
596 | Index | **TFM-GENERIC-REQUEST-SERVICE-T-I-1** |
597 +---------------+------------------------------------------------------------+
598 | Description | A malicious NS application may request to control secure |
599 | | device and peripherals, on which it doesn't have the |
600 | | permission. |
601 +---------------+------------------------------------------------------------+
602 | Justification | A malicious NS application may request RoT services to |
603 | | control secure device and peripherals, on which it doesn't |
604 | | have the permission. |
605 +---------------+------------------------------------------------------------+
606 | Category | Tampering/Information disclose |
607 +---------------+------------------------------------------------------------+
608 | Mitigation | TF-M performs client check to validate whether the client |
609 | | has the permission to access the secure device and |
610 | | peripherals. |
611 +---------------+------------------------------------------------------------+
612 | CVSS Score | 9.0 (Critical) |
613 +---------------+------------------------------------------------------------+
614 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:N |
615 | String | |
616 +---------------+------------------------------------------------------------+
617
618.. table:: TFM-GENERIC-REQUEST-SERVICE-D-1
619 :widths: 10 50
620
621 +---------------+------------------------------------------------------------+
622 | Index | **TFM-GENERIC-REQUEST-SERVICE-D-1** |
623 +---------------+------------------------------------------------------------+
624 | Description | A Malicious NS applications may frequently call secure |
625 | | services to block secure service requests from other NS |
626 | | applications. |
627 +---------------+------------------------------------------------------------+
628 | Justification | TF-M runs on IoT devices with constrained resource. Even |
629 | | though multiple outstanding NS PSA Client calls can be |
630 | | supported in system, the number of NS PSA client calls |
631 | | served by TF-M simultaneously are still limited. |
632 | | |
633 | | Therefore, if a malicious NS application or multiple |
634 | | malicious NS applications continue calling TF-M secure |
635 | | services frequently, it may block other NS applications to |
636 | | request secure service from TF-M. |
637 +---------------+------------------------------------------------------------+
638 | Category | Denial of service |
639 +---------------+------------------------------------------------------------+
640 | Mitigation | TF-M is unable to manage behavior of NS applications. |
641 | | Assets are not disclosed and TF-M is neither directly |
642 | | impacted in this threat. |
643 | | |
644 | | It relies on NS OS to enhance scheduling policy and |
645 | | prevent a single NS application to occupy entire CPU time. |
646 | | It is beyond the scope of this threat model. |
647 +---------------+------------------------------------------------------------+
648 | CVSS Score | 4.0 (Medium) |
649 +---------------+------------------------------------------------------------+
650 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:L |
651 | String | |
652 +---------------+------------------------------------------------------------+
653
654.. table:: TFM-GENERIC-REQUEST-SERVICE-D-2
655 :widths: 10 50
656
657 +---------------+------------------------------------------------------------+
658 | Index | **TFM-GENERIC-REQUEST-SERVICE-D-2** |
659 +---------------+------------------------------------------------------------+
660 | Description | A malicious NS application may provide invalid NS memory |
661 | | addresses as the addresses of input and output data in RoT |
662 | | service requests. |
663 +---------------+------------------------------------------------------------+
664 | Justification | SPE may be unable to achieve full knowledge of NS memory |
665 | | mapping. SPE may fail to capture those invalid NS memory |
666 | | addresses during memory access check since those invalid |
667 | | addresses may not be included in isolation configuration. |
668 | | |
669 | | In that case, SPE will access those invalid NS memory |
670 | | addresses later to read or write data. It may trigger a |
671 | | system error to crash the whole system immediately. |
672 | | |
673 | | The malicious NS application may be blocked by NS MPU from |
674 | | directly accessing that invalid NS memory address. But it |
675 | | may manipulate SPE to access that address instead. |
676 +---------------+------------------------------------------------------------+
677 | Category | Denial of service |
678 +---------------+------------------------------------------------------------+
679 | Mitigation | TF-M executes memory access check to the memory addresses |
680 | | in all the NS requests. |
681 | | |
682 | | On single Armv8-M core platforms, TF-M invokes ``TT`` |
683 | | instructions to execute memory address check. If a NS |
684 | | memory area is not matched in any valid SAU or MPU region, |
685 | | it will be marked as invalid and any access permission is |
686 | | disallowed. Therefore, SPM will reject any NS request |
687 | | containing invalid NS memory addresses and reports it as |
688 | | as a security error. |
689 | | |
690 | | On dual-core platforms, TF-M implements a default memory |
691 | | access check. If a NS memory area is not found in any |
692 | | memory region configured for isolation, it will be marked |
693 | | as invalid and therefore SPM will reject the corresponding |
694 | | NS request. It will be reported as a security error. |
695 | | |
696 | | Dual-core platforms may implement platform specific memory |
697 | | check to replace the default one. It relies on platform |
698 | | specific implementation to capture invalid memory address. |
699 | | It is out of the scope of this document. |
700 +---------------+------------------------------------------------------------+
701 | CVSS Score | 3.2 (Low) |
702 +---------------+------------------------------------------------------------+
703 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:C/C:N/I:N/A:L |
704 | String | |
705 +---------------+------------------------------------------------------------+
706
707RoT services read and write NS data
708-----------------------------------
709
710This section identifies threats on ``DF3`` defined in `Data Flow Diagram`_.
711
712According to [FF-M]_, in TF-M IPC model, RoT services should rely on TF-M SPM to
713obtain NS input data and send response data back to NS memory.
714
715In Library model, RoT services directly read and write NS memory to simplify the
716implementation and decrease latency.
717
718.. _TFM-GENERIC-SECURE-SERVICE-RW-T-1:
719
720.. table:: TFM-GENERIC-SECURE-SERVICE-RW-T-1
721 :widths: 10 50
722
723 +---------------+------------------------------------------------------------+
724 | Index | **TFM-GENERIC-SECURE-SERVICE-RW-T-1** |
725 +---------------+------------------------------------------------------------+
726 | Description | An attacker may tamper NS input data while the RoT service |
727 | | is processing those data. |
728 +---------------+------------------------------------------------------------+
729 | Justification | A RoT service may access NS input data multiple times |
730 | | during its data processing. For example, it may validate |
731 | | or authenticate the NS input data before it performs |
732 | | further processing. |
733 | | |
734 | | If the NS input data remains in NSPE memory during the RoT |
735 | | service execution, an attacker may tamper the NS input |
736 | | data in NSPE memory after the validation passes. |
737 +---------------+------------------------------------------------------------+
738 | Category | Tampering |
739 +---------------+------------------------------------------------------------+
740 | Mitigation | In TF-M IPC model, RoT services request SPM to read and |
741 | | write NS data. TF-M SPM follows [FF-M]_ to copy the NS |
742 | | input data into SPE memory region owned by the RoT |
743 | | service, before the RoT service processes the data. |
744 | | Therefore, the NS input data is protected during the RoT |
745 | | service execution from being tampered. |
746 | | |
747 | | In TF-M Library model, RoT services can directly access NS |
748 | | memory. If a RoT service accesses NS input data multiple |
749 | | times during data processing, it is required to review and |
750 | | confirm Library model implementation of the RoT service |
751 | | copies NS input data into SPE memory area before it |
752 | | processes the data. |
753 +---------------+------------------------------------------------------------+
754 | CVSS Score | 3.2 (Low) |
755 +---------------+------------------------------------------------------------+
756 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:C/C:N/I:L/A:N |
757 | String | |
758 +---------------+------------------------------------------------------------+
759
760.. _TFM-GENERIC-SECURE-SERVICE-RW-T-2:
761
762.. table:: TFM-GENERIC-SECURE-SERVICE-RW-T-2
763 :widths: 10 50
764
765 +---------------+------------------------------------------------------------+
766 | Index | **TFM-GENERIC-SECURE-SERVICE-RW-T-2** |
767 +---------------+------------------------------------------------------------+
768 | Description | A malicious NS application may embed secure memory |
769 | | addresses into a structure in RoT service request input |
770 | | vectors, to tamper secure memory which the NS application |
771 | | must not access. |
772 +---------------+------------------------------------------------------------+
773 | Justification | [FF-M]_ limits the total number of input/output vectors to |
774 | | 4. If a RoT service requires more input/output vectors, it |
775 | | may define a parameter structure which embeds multiple |
776 | | input/output buffers addresses. |
777 | | |
778 | | However, as a potential security risk, a malicious NS |
779 | | application can put secure memory addresses into a valid |
780 | | parameter structure to bypass TF-M validation on those |
781 | | memory addresses. |
782 | | |
783 | | The parameter structure can pass TF-M memory access check |
784 | | since itself is valid. However, if the RoT service parses |
785 | | the structure and directly write malicious data from NSPE |
786 | | to the secure memory addresses in parameter structure, the |
787 | | secure data will be tampered. |
788 +---------------+------------------------------------------------------------+
789 | Category | Tampering |
790 +---------------+------------------------------------------------------------+
791 | Mitigation | It should be avoided to embed memory addresses into a |
792 | | single input/output vector. If more than 4 memory |
793 | | addresses are required in a RoT service request, it is |
794 | | recommended to split this request into two or multiple |
795 | | service calls and therefore each service call requires no |
796 | | more than 4 input/output vectors. |
797 | | |
798 | | In TF-M IPC model, RoT services request SPM to read and |
799 | | write NS data. SPM will validate the target addresses and |
800 | | can detect the invalid addresses to mitigate this threat. |
801 | | |
802 | | In TF-M Library model, RoT services can directly access NS |
803 | | memory. It is required to review and confirm Library model |
804 | | implementation of RoT service request doesn't embed memory |
805 | | addresses. |
806 +---------------+------------------------------------------------------------+
807 | CVSS Score | 6.3 (Medium) |
808 +---------------+------------------------------------------------------------+
809 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:R/S:C/C:N/I:H/A:N |
810 | String | |
811 +---------------+------------------------------------------------------------+
812
813.. table:: TFM-GENERIC-SECURE-SERVICE-RW-I-1
814 :widths: 10 50
815
816 +---------------+------------------------------------------------------------+
817 | Index | **TFM-GENERIC-SECURE-SERVICE-RW-I-1** |
818 +---------------+------------------------------------------------------------+
819 | Description | Similar to TFM-GENERIC-SECURE-SERVICE-RW-T-2_, a malicious |
820 | | NS application can embed secure memory addresses in a |
821 | | parameter structure in RoT service request input vectors, |
822 | | to read secure data which the NS application must not |
823 | | access. |
824 +---------------+------------------------------------------------------------+
825 | Justification | Similar to the description in |
826 | | TFM-GENERIC-SECURE-SERVICE-RW-T-2_, the secure memory |
827 | | addresses hidden in the RoT service input/output vector |
828 | | structure may bypass TF-M validation. Without a proper |
829 | | check, the RoT service may copy secure data to NSPE |
830 | | according to the secure memory addresses in structure, |
831 | | secure information can be disclosed. |
832 +---------------+------------------------------------------------------------+
833 | Category | Information disclosure |
834 +---------------+------------------------------------------------------------+
835 | Mitigation | It should be avoided to embed memory addresses into a |
836 | | single input/output vector. If more than 4 memory |
837 | | addresses are required in a RoT service request, it is |
838 | | recommended to split this request into two or multiple |
839 | | service calls and therefore each service call requires no |
840 | | more than 4 input/output vectors. |
841 | | |
842 | | In TF-M IPC model, RoT services request SPM to read and |
843 | | write NS data. SPM will validate the target addresses and |
844 | | can detect the invalid addresses to mitigate this threat. |
845 | | |
846 | | In TF-M Library model, RoT services can directly access NS |
847 | | memory. It is required to review and confirm Library model |
848 | | implementation of RoT service request doesn't embed memory |
849 | | addresses. |
850 +---------------+------------------------------------------------------------+
851 | CVSS Score | 6.3 (Medium) |
852 +---------------+------------------------------------------------------------+
853 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:R/S:C/C:H/I:N/A:N |
854 | String | |
855 +---------------+------------------------------------------------------------+
856
857TF-M returns secure service result
858----------------------------------
859
860This section identifies threats on ``DF4`` defined in `Data Flow Diagram`_.
861
862When RoT service completes the request from NSPE, TF-M returns the success or
863failure error code to NS application.
864
865In single Armv8-M core scenario, TF-M writes the return code value in the
866general purpose register and returns to Non-secure state.
867
868On dual-cpu platforms, TF-M writes the return code to NSPE mailbox message queue
869via mailbox.
870
871.. table:: TFM-GENERIC-RETURN-CODE-I-1
872 :widths: 10 50
873
874 +---------------+------------------------------------------------------------+
875 | Index | **TFM-GENERIC-RETURN-CODE-I-1** |
876 +---------------+------------------------------------------------------------+
877 | Description | SPE may leave secure data in the registers not banked |
878 | | after the SPE completes PSA Client calls and executes |
879 | | ``BXNS`` to switch Armv8-M back to Non-secure state. |
880 +---------------+------------------------------------------------------------+
881 | Justification | If SPE doesn't clean up the secure data in registers not |
882 | | banked before switching into NSPE in Armv8-M core, NSPE |
883 | | can read the SPE context from those registers. |
884 +---------------+------------------------------------------------------------+
885 | Category | Information disclosure |
886 +---------------+------------------------------------------------------------+
887 | Mitigation | In single Armv8-M core scenario, TF-M cleans general |
888 | | purpose registers not banked before switching into NSPE to |
889 | | prevent NSPE probing secure context from the registers. |
890 | | |
891 | | Current TF-M implementation doesn't support FPU in SPE. |
892 | | TF-M build will stop if FPU is enabled on platform. |
893 | | Therefore, FPU registers doesn't contain data that needs |
894 | | to be protected from NSPE. |
895 +---------------+------------------------------------------------------------+
896 | CVSS Score | 4.3 (Medium) |
897 +---------------+------------------------------------------------------------+
898 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N |
899 | String | |
900 +---------------+------------------------------------------------------------+
901
902NS interrupts preempts SPE execution
903------------------------------------
904
905This section identifies threats on ``DF5`` defined in `Data Flow Diagram`_.
906
907.. table:: TFM-GENERIC-NS-INTERRUPT-I-1
908 :widths: 10 50
909
910 +---------------+------------------------------------------------------------+
911 | Index | **TFM-GENERIC-NS-INTERRUPT-I-1** |
912 +---------------+------------------------------------------------------------+
913 | Description | Shared registers may contain secure data when NS |
914 | | interrupts occur. |
915 +---------------+------------------------------------------------------------+
916 | Justification | The secure data in shared registers should be cleaned up |
917 | | before NSPE can access shared registers. Otherwise, secure |
918 | | data leakage may occur. |
919 +---------------+------------------------------------------------------------+
920 | Category | Information disclosure |
921 +---------------+------------------------------------------------------------+
922 | Mitigation | In single Armv8-M core scenario, Armv8-M architecture |
923 | | automatically cleans up the registers not banked before |
924 | | switching to Non-secure state while taking NS interrupts. |
925 | | |
926 | | Current TF-M implementation doesn't support FPU in SPE. |
927 | | TF-M build will stop if FPU is enabled on platform. |
928 | | Therefore, FPU registers doesn't contain data that needs |
929 | | to be protected from NSPE. |
930 | | |
931 | | On dual-cpu platforms, shared registers are implementation |
932 | | defined, such as Inter-Processor Communication registers. |
933 | | Dual-cpu platforms must not store any data which may |
934 | | disclose secure information in the shared registers. |
935 +---------------+------------------------------------------------------------+
936 | CVSS Score | 4.3 (Medium) |
937 +---------------+------------------------------------------------------------+
938 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N |
939 | String | |
940 +---------------+------------------------------------------------------------+
941
942.. table:: TFM-GENERIC-NS-INTERRUPT-D-1
943 :widths: 10 50
944
945 +---------------+------------------------------------------------------------+
946 | Index | **TFM-GENERIC-NS-INTERRUPT-D-1** |
947 +---------------+------------------------------------------------------------+
948 | Description | An attacker may trigger spurious NS interrupts frequently |
949 | | to block SPE execution. |
950 +---------------+------------------------------------------------------------+
951 | Justification | In single Armv8-M core scenario, an attacker may inject a |
952 | | malicious NS application or hijack a NS hardware to |
953 | | frequently trigger spurious NS interrupts to keep |
954 | | preempting SPE and block SPE to perform normal secure |
955 | | execution. |
956 +---------------+------------------------------------------------------------+
957 | Category | Denial of service |
958 +---------------+------------------------------------------------------------+
959 | Mitigation | It is out of scope of TF-M. |
960 | | |
961 | | Assets protected by TF-M won't be leaked. TF-M won't be |
962 | | directly impacted. |
963 +---------------+------------------------------------------------------------+
964 | CVSS Score | 4.0 (Medium) |
965 +---------------+------------------------------------------------------------+
966 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:L |
967 | String | |
968 +---------------+------------------------------------------------------------+
969
970Secure interrupts preempts NSPE execution
971-----------------------------------------
972
973This section identifies threats on ``DF6`` defined in `Data Flow Diagram`_.
974
975.. table:: TFM-GENERIC-S-INTERRUPT-I-1
976 :widths: 10 50
977
978 +---------------+------------------------------------------------------------+
979 | Index | **TFM-GENERIC-S-INTERRUPT-I-1** |
980 +---------------+------------------------------------------------------------+
981 | Description | Shared registers may contain secure data when Armv8-M core |
982 | | switches back to Non-secure state on Secure interrupt |
983 | | return. |
984 +---------------+------------------------------------------------------------+
985 | Justification | Armv8-M architecture doesn't automatically clean up shared |
986 | | registers while returning to Non-secure state during |
987 | | Secure interrupt return. |
988 | | |
989 | | If SPE leaves critical data in the Armv8-M registers not |
990 | | banked, NSPE can read secure context from those registers |
991 | | and secure data leakage may occur. |
992 +---------------+------------------------------------------------------------+
993 | Category | Information disclosure |
994 +---------------+------------------------------------------------------------+
995 | Mitigation | TF-M saves NPSE context in general purpose register R4~R11 |
996 | | into secure stack during secure interrupt entry. |
997 | | After secure interrupt handling completes, TF-M unstacks |
998 | | NSPE context from secure stack to overwrite secure context |
999 | | in R4~R11 before secure interrupt return. |
1000 | | |
1001 | | Armv8-M architecture will automatically unstack NSPE |
1002 | | context from non-secure stack to overwrite other registers |
1003 | | not banked, such as R0~R3 and R12, during secure interrupt |
1004 | | return, before NSPE software can access those registers. |
1005 | | |
1006 | | Current TF-M implementation doesn't support FPU in SPE. |
1007 | | TF-M build will stop if FPU is enabled on platform. |
1008 | | Therefore, FPU registers doesn't contain data that needs |
1009 | | to be protected from NSPE. |
1010 +---------------+------------------------------------------------------------+
1011 | CVSS Score | 4.3 (Medium) |
1012 +---------------+------------------------------------------------------------+
1013 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N |
1014 | String | |
1015 +---------------+------------------------------------------------------------+
1016
1017Miscellaneous threats
1018---------------------
1019
1020This section collects threats irrelevant to the valid TF-M data flows shown
1021above.
1022
1023.. table:: TFM-GENERIC-STACK-SEAL
1024 :widths: 10 50
1025
1026 +---------------+------------------------------------------------------------+
1027 | Index | **TFM-GENERIC-STACK_SEAL** |
1028 +---------------+------------------------------------------------------------+
1029 | Description | Armv8-M processor Secure software Stack Sealing |
1030 | | vulnerability. |
1031 +---------------+------------------------------------------------------------+
1032 | Justification | On Armv8-M based processors with TrustZone, if Secure |
1033 | | software does not properly manage the Secure stacks when |
1034 | | the stacks are created, or when performing non-standard |
1035 | | transitioning between states or modes, for example, |
1036 | | creating a fake exception return stack frame to |
1037 | | de-privilege an interrupt, it is possible for Non-secure |
1038 | | world software to manipulate the Secure Stacks, and |
1039 | | potentially influence Secure control flow. |
1040 | | |
1041 | | Refer to [STACK-SEAL]_ for details. |
1042 +---------------+------------------------------------------------------------+
1043 | Category | Elevation of privilege |
1044 +---------------+------------------------------------------------------------+
1045 | Mitigation | TF-M has implemented common mitigation against stack seal |
1046 | | vulnerability. |
1047 | | |
1048 | | Refer to [ADVISORY-TFMV-1]_ for details on analysis and |
1049 | | mitigation in TF-M. |
1050 +---------------+------------------------------------------------------------+
1051 | CVSS Score | 5.3 (Medium) |
1052 +---------------+------------------------------------------------------------+
1053 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:L/I:L/A:L |
1054 | String | |
1055 +---------------+------------------------------------------------------------+
1056
1057***************
1058Version control
1059***************
1060
1061.. table:: Version control
1062
1063 +---------+--------------------------------------------------+---------------+
1064 | Version | Description | TF-M version |
1065 +=========+==================================================+===============+
1066 | v0.1 | Initial draft | TF-M v1.1 |
1067 +---------+--------------------------------------------------+---------------+
1068
1069*********
1070Reference
1071*********
1072
1073.. [Security-Incident-Process] `Security Incident Process <https://developer.trustedfirmware.org/w/collaboration/security_center/reporting/>`_
1074
1075.. [FF-M] `Arm® Platform Security Architecture Firmware Framework 1.0 <https://developer.arm.com/-/media/Files/pdf/PlatformSecurityArchitecture/Architect/DEN0063-PSA_Firmware_Framework-1.0.0-2.pdf?revision=2d1429fa-4b5b-461a-a60e-4ef3d8f7f4b4>`_
1076
1077.. [DUAL-CPU-BOOT] :doc:`Booting a dual core system </docs/design_documents/dual-cpu/booting_a_dual_core_system>`
1078
1079.. [CVSS] `Common Vulnerability Scoring System Version 3.1 Calculator <https://www.first.org/cvss/calculator/3.1>`_
1080
1081.. [CVSS_SPEC] `CVSS v3.1 Specification Document <https://www.first.org/cvss/v3-1/cvss-v31-specification_r1.pdf>`_
1082
1083.. [STRIDE] `The STRIDE Threat Model <https://docs.microsoft.com/en-us/previous-versions/commerce-server/ee823878(v=cs.20)?redirectedfrom=MSDN>`_
1084
1085.. [SECURE-BOOT] :doc:`Secure boot </docs/getting_started/tfm_secure_boot>`
1086
1087.. [ROLLBACK-PROTECT] :doc:`Rollback protection in TF-M secure boot </docs/design_documents/secure_boot_rollback_protection>`
1088
1089.. [STACK-SEAL] `Armv8-M processor Secure software Stack Sealing vulnerability <https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing>`_
1090
1091.. [ADVISORY-TFMV-1] :doc:`Advisory TFMV-1 </docs/reference/security_advisories/stack_seal_vulnerability>`
1092
1093--------------------
1094
1095*Copyright (c) 2020 Arm Limited. All Rights Reserved.*