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Lucian Paul-Trifu3519afe2022-03-08 15:02:31 +00001/*
2 * Copyright (c) 2021 Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7#ifndef TPM_H
8#define TPM_H
9
10#include <lib/utils_def.h>
11
12/*
13 * TPM_ALG_ID constants.
14 * Ref. Table 9 - Definition of (UINT16) TPM_ALG_ID Constants
15 * Trusted Platform Module Library. Part 2: Structures,
16 * Family "2.0", Level 00 Revision 01.38, September 29 2016.
17 */
18enum tpm_hash_alg {
19 TPM_ALG_NONE = 0x0,
20 TPM_ALG_SHA256 = 0x000B,
21 TPM_ALG_SHA384 = 0x000C,
22 TPM_ALG_SHA512 = 0x000D,
23};
24static inline bool tpm_alg_is_valid(enum tpm_hash_alg alg)
25{
26 switch (alg) {
27 case TPM_ALG_SHA256:
28 case TPM_ALG_SHA384:
29 case TPM_ALG_SHA512:
30 return true;
31
32 default:
33 return false;
34 }
35}
36
37enum tpm_hash_alg_dsize {
38 TPM_ALG_SHA256_DSIZE = 32,
39 TPM_ALG_SHA384_DSIZE = 48,
40 TPM_ALG_SHA512_DSIZE = 64,
41
42 TPM_ALG_MAX_DSIZE = TPM_ALG_SHA512_DSIZE
43};
44static inline size_t tpm_alg_dsize(enum tpm_hash_alg alg)
45{
46 switch (alg) {
47 case TPM_ALG_SHA256:
48 return TPM_ALG_SHA256_DSIZE;
49
50 case TPM_ALG_SHA384:
51 return TPM_ALG_SHA384_DSIZE;
52
53 case TPM_ALG_SHA512:
54 return TPM_ALG_SHA512_DSIZE;
55
56 default:
57 return 0;
58 }
59}
60
61enum tpm_pcr_idx {
62 /*
63 * SRTM, BIOS, Host Platform Extensions, Embedded
64 * Option ROMs and PI Drivers
65 */
66 TPM_PCR_0 = 0,
67 /* Host Platform Configuration */
68 TPM_PCR_1,
69 /* UEFI driver and application Code */
70 TPM_PCR_2,
71 /* UEFI driver and application Configuration and Data */
72 TPM_PCR_3,
73 /* UEFI Boot Manager Code (usually the MBR) and Boot Attempts */
74 TPM_PCR_4,
75 /*
76 * Boot Manager Code Configuration and Data (for use
77 * by the Boot Manager Code) and GPT/Partition Table
78 */
79 TPM_PCR_5,
80 /* Host Platform Manufacturer Specific */
81 TPM_PCR_6,
82 /* Secure Boot Policy */
83 TPM_PCR_7,
84 /* 8-15: Defined for use by the Static OS */
85 TPM_PCR_8,
86 /* Debug */
87 TPM_PCR_16 = 16,
88
89 /* DRTM (1) */
90 TPM_PCR_17 = 17,
91 /* DRTM (2) */
92 TPM_PCR_18 = 18,
93};
94static bool inline tpm_pcr_idx_is_valid(enum tpm_pcr_idx pcr_idx)
95{
96 switch (pcr_idx) {
97 case TPM_PCR_0:
98 case TPM_PCR_1:
99 case TPM_PCR_2:
100 case TPM_PCR_3:
101 case TPM_PCR_4:
102 case TPM_PCR_5:
103 case TPM_PCR_6:
104 case TPM_PCR_7:
105 case TPM_PCR_8:
106 case TPM_PCR_16:
107 case TPM_PCR_17:
108 case TPM_PCR_18:
109 return true;
110
111 default:
112 return false;
113 }
114}
115
116#endif /* TPM_H */