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Yann Gautierc948f772019-01-17 19:16:03 +01001/*
Boyan Karatotev270d5c52025-02-11 14:41:18 +00002 * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
Alexei Fedorov0861fcd2021-04-23 16:12:11 +01003 *
4 * SPDX-License-Identifier: MIT
5 *
Yann Gautierc948f772019-01-17 19:16:03 +01006 * This header provides constants for the ARM GIC.
7 */
8
9#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
10#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
11
Yann Gautierf1b6b012021-05-25 18:14:24 +020012#include <dt-bindings/interrupt-controller/irq.h>
13
Yann Gautierc948f772019-01-17 19:16:03 +010014/* interrupt specifier cell 0 */
15
16#define GIC_SPI 0
17#define GIC_PPI 1
18
Alexei Fedorovdfa6c542021-04-12 12:49:54 +010019/*
Boyan Karatotev270d5c52025-02-11 14:41:18 +000020 * Only relevant for GIC <= v2
Alexei Fedorovdfa6c542021-04-12 12:49:54 +010021 * Interrupt specifier cell 2.
Yann Gautierf1b6b012021-05-25 18:14:24 +020022 * The flags in irq.h are valid, plus those below.
Alexei Fedorovdfa6c542021-04-12 12:49:54 +010023 */
24#define GIC_CPU_MASK_RAW(x) ((x) << 8)
Yann Gautierf1b6b012021-05-25 18:14:24 +020025#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
Alexei Fedorovdfa6c542021-04-12 12:49:54 +010026
Yann Gautierc948f772019-01-17 19:16:03 +010027#endif