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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Yatharth Kochar42019bf2016-09-12 16:10:33 +01002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley97043ac2014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley97043ac2014-04-09 13:14:54 +010033#include <assert.h>
Juan Castillo1779ba62015-05-19 11:54:12 +010034#include <auth_mod.h>
Yatharth Kochar48bfb882015-10-10 19:06:53 +010035#include <bl1.h>
Dan Handley97043ac2014-04-09 13:14:54 +010036#include <bl_common.h>
Vikram Kanigiri4112bfa2014-04-15 18:08:08 +010037#include <debug.h>
Dan Handley97043ac2014-04-09 13:14:54 +010038#include <platform.h>
Dan Handley5f0cdb02014-05-14 17:44:19 +010039#include <platform_def.h>
Yatharth Kochar48bfb882015-10-10 19:06:53 +010040#include <smcc_helpers.h>
Soby Mathewc45f6272016-07-20 14:38:36 +010041#include <utils.h>
Dan Handley5b827a82014-04-17 18:53:42 +010042#include "bl1_private.h"
Yatharth Kochar48bfb882015-10-10 19:06:53 +010043#include <uuid.h>
44
45/* BL1 Service UUID */
46DEFINE_SVC_UUID(bl1_svc_uid,
47 0xfd3967d4, 0x72cb, 0x4d9a, 0xb5, 0x75,
48 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
Achin Gupta4f6ad662013-10-25 09:08:21 +010049
Vikram Kanigiria2f8b162015-07-23 11:16:28 +010050
Yatharth Kochar7baff112015-10-09 18:06:13 +010051static void bl1_load_bl2(void);
Vikram Kanigiri29fb9052014-05-15 18:27:15 +010052
Sandrine Bailleux8f55dfb2014-06-24 14:02:34 +010053/*******************************************************************************
54 * The next function has a weak definition. Platform specific code can override
55 * it if it wishes to.
56 ******************************************************************************/
57#pragma weak bl1_init_bl2_mem_layout
58
59/*******************************************************************************
60 * Function that takes a memory layout into which BL2 has been loaded and
61 * populates a new memory layout for BL2 that ensures that BL1's data sections
62 * resident in secure RAM are not visible to BL2.
63 ******************************************************************************/
64void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
65 meminfo_t *bl2_mem_layout)
66{
Sandrine Bailleux8f55dfb2014-06-24 14:02:34 +010067
68 assert(bl1_mem_layout != NULL);
69 assert(bl2_mem_layout != NULL);
70
Yatharth Kochar42019bf2016-09-12 16:10:33 +010071#if LOAD_IMAGE_V2
72 /*
73 * Remove BL1 RW data from the scope of memory visible to BL2.
74 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
75 */
76 assert(BL1_RW_BASE > bl1_mem_layout->total_base);
77 bl2_mem_layout->total_base = bl1_mem_layout->total_base;
78 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
79#else
Sandrine Bailleux8f55dfb2014-06-24 14:02:34 +010080 /* Check that BL1's memory is lying outside of the free memory */
81 assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) ||
Yatharth Kochar7baff112015-10-09 18:06:13 +010082 (BL1_RAM_BASE >= bl1_mem_layout->free_base +
83 bl1_mem_layout->free_size));
Sandrine Bailleux8f55dfb2014-06-24 14:02:34 +010084
85 /* Remove BL1 RW data from the scope of memory visible to BL2 */
86 *bl2_mem_layout = *bl1_mem_layout;
87 reserve_mem(&bl2_mem_layout->total_base,
88 &bl2_mem_layout->total_size,
89 BL1_RAM_BASE,
Yatharth Kochar42019bf2016-09-12 16:10:33 +010090 BL1_RAM_LIMIT - BL1_RAM_BASE);
91#endif /* LOAD_IMAGE_V2 */
Sandrine Bailleux8f55dfb2014-06-24 14:02:34 +010092
93 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
94}
Vikram Kanigiri29fb9052014-05-15 18:27:15 +010095
96/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010097 * Function to perform late architectural and platform specific initialization.
Yatharth Kochar7baff112015-10-09 18:06:13 +010098 * It also queries the platform to load and run next BL image. Only called
99 * by the primary cpu after a cold boot.
100 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +0100101void bl1_main(void)
102{
Yatharth Kochar7baff112015-10-09 18:06:13 +0100103 unsigned int image_id;
104
Dan Handley6ad2e462014-07-29 17:14:00 +0100105 /* Announce our arrival */
106 NOTICE(FIRMWARE_WELCOME_STR);
107 NOTICE("BL1: %s\n", version_string);
108 NOTICE("BL1: %s\n", build_message);
109
110 INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT);
111
Achin Gupta4f6ad662013-10-25 09:08:21 +0100112
Dan Handleyce4c8202015-03-30 17:15:16 +0100113#if DEBUG
114 unsigned long val;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115 /*
116 * Ensure that MMU/Caches and coherency are turned on
117 */
Dan Handleyce4c8202015-03-30 17:15:16 +0100118 val = read_sctlr_el3();
Andrew Thoelke354ab572015-06-11 14:12:14 +0100119 assert(val & SCTLR_M_BIT);
120 assert(val & SCTLR_C_BIT);
121 assert(val & SCTLR_I_BIT);
Dan Handleyce4c8202015-03-30 17:15:16 +0100122 /*
123 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
124 * provided platform value
125 */
126 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
127 /*
128 * If CWG is zero, then no CWG information is available but we can
129 * at least check the platform value is less than the architectural
130 * maximum.
131 */
132 if (val != 0)
133 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
134 else
135 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
136#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137
138 /* Perform remaining generic architectural setup from EL3 */
139 bl1_arch_setup();
140
Yatharth Kochar7baff112015-10-09 18:06:13 +0100141#if TRUSTED_BOARD_BOOT
142 /* Initialize authentication module */
143 auth_mod_init();
144#endif /* TRUSTED_BOARD_BOOT */
145
Achin Gupta4f6ad662013-10-25 09:08:21 +0100146 /* Perform platform setup in BL1. */
147 bl1_platform_setup();
148
Yatharth Kochar7baff112015-10-09 18:06:13 +0100149 /* Get the image id of next image to load and run. */
150 image_id = bl1_plat_get_next_image_id();
151
Yatharth Kochar48bfb882015-10-10 19:06:53 +0100152 /*
153 * We currently interpret any image id other than
154 * BL2_IMAGE_ID as the start of firmware update.
155 */
Yatharth Kochar7baff112015-10-09 18:06:13 +0100156 if (image_id == BL2_IMAGE_ID)
157 bl1_load_bl2();
Yatharth Kochar48bfb882015-10-10 19:06:53 +0100158 else
159 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
Yatharth Kochar7baff112015-10-09 18:06:13 +0100160
161 bl1_prepare_next_image(image_id);
162}
163
164/*******************************************************************************
165 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
166 * Called by the primary cpu after a cold boot.
167 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
168 * loader etc.
169 ******************************************************************************/
170void bl1_load_bl2(void)
171{
172 image_desc_t *image_desc;
173 image_info_t *image_info;
174 entry_point_info_t *ep_info;
175 meminfo_t *bl1_tzram_layout;
176 meminfo_t *bl2_tzram_layout;
177 int err;
178
179 /* Get the image descriptor */
180 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
181 assert(image_desc);
182
183 /* Get the image info */
184 image_info = &image_desc->image_info;
185
186 /* Get the entry point info */
187 ep_info = &image_desc->ep_info;
Vikram Kanigiri4112bfa2014-04-15 18:08:08 +0100188
Sandrine Bailleux8f55dfb2014-06-24 14:02:34 +0100189 /* Find out how much free trusted ram remains after BL1 load */
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +0000190 bl1_tzram_layout = bl1_plat_sec_mem_layout();
Sandrine Bailleux8f55dfb2014-06-24 14:02:34 +0100191
Juan Castillo16948ae2015-04-13 17:36:19 +0100192 INFO("BL1: Loading BL2\n");
193
Yatharth Kochar42019bf2016-09-12 16:10:33 +0100194#if LOAD_IMAGE_V2
195 err = load_auth_image(BL2_IMAGE_ID, image_info);
196#else
Sandrine Bailleux8f55dfb2014-06-24 14:02:34 +0100197 /* Load the BL2 image */
Juan Castillo1779ba62015-05-19 11:54:12 +0100198 err = load_auth_image(bl1_tzram_layout,
Juan Castillo16948ae2015-04-13 17:36:19 +0100199 BL2_IMAGE_ID,
Yatharth Kochar7baff112015-10-09 18:06:13 +0100200 image_info->image_base,
201 image_info,
202 ep_info);
Juan Castillo1779ba62015-05-19 11:54:12 +0100203
Yatharth Kochar42019bf2016-09-12 16:10:33 +0100204#endif /* LOAD_IMAGE_V2 */
205
Vikram Kanigiri4112bfa2014-04-15 18:08:08 +0100206 if (err) {
Dan Handley6ad2e462014-07-29 17:14:00 +0100207 ERROR("Failed to load BL2 firmware.\n");
Juan Castillo40fc6cd2015-09-25 15:41:14 +0100208 plat_error_handler(err);
Vikram Kanigiri4112bfa2014-04-15 18:08:08 +0100209 }
Juan Castillo01df3c12015-01-07 13:49:59 +0000210
Achin Gupta4f6ad662013-10-25 09:08:21 +0100211 /*
212 * Create a new layout of memory for BL2 as seen by BL1 i.e.
213 * tell it the amount of total and free memory available.
214 * This layout is created at the first free address visible
215 * to BL2. BL2 will read the memory layout before using its
216 * memory for other purposes.
217 */
Yatharth Kochar42019bf2016-09-12 16:10:33 +0100218#if LOAD_IMAGE_V2
219 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->total_base;
220#else
Dan Handleyfb037bf2014-04-10 15:37:22 +0100221 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base;
Yatharth Kochar42019bf2016-09-12 16:10:33 +0100222#endif /* LOAD_IMAGE_V2 */
223
Sandrine Bailleux8f55dfb2014-06-24 14:02:34 +0100224 bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100225
Yatharth Kochar7baff112015-10-09 18:06:13 +0100226 ep_info->args.arg1 = (unsigned long)bl2_tzram_layout;
227 NOTICE("BL1: Booting BL2\n");
228 VERBOSE("BL1: BL2 memory layout address = 0x%llx\n",
229 (unsigned long long) bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100230}
231
232/*******************************************************************************
Sandrine Bailleuxee5c2b12015-10-27 15:52:33 +0000233 * Function called just before handing over to BL31 to inform the user about
234 * the boot progress. In debug mode, also print details about the BL31 image's
235 * execution context.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236 ******************************************************************************/
Sandrine Bailleuxee5c2b12015-10-27 15:52:33 +0000237void bl1_print_bl31_ep_info(const entry_point_info_t *bl31_ep_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100238{
Juan Castillod1786372015-12-14 09:35:25 +0000239 NOTICE("BL1: Booting BL31\n");
Sandrine Bailleux68a68c92015-09-28 17:03:06 +0100240 print_entry_point_info(bl31_ep_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100241}
Sandrine Bailleux35e8c762015-11-10 10:01:19 +0000242
243#if SPIN_ON_BL1_EXIT
244void print_debug_loop_message(void)
245{
246 NOTICE("BL1: Debug loop, spinning forever\n");
247 NOTICE("BL1: Please connect the debugger to continue\n");
248}
249#endif
Yatharth Kochar48bfb882015-10-10 19:06:53 +0100250
251/*******************************************************************************
252 * Top level handler for servicing BL1 SMCs.
253 ******************************************************************************/
254register_t bl1_smc_handler(unsigned int smc_fid,
255 register_t x1,
256 register_t x2,
257 register_t x3,
258 register_t x4,
259 void *cookie,
260 void *handle,
261 unsigned int flags)
262{
263
264#if TRUSTED_BOARD_BOOT
265 /*
266 * Dispatch FWU calls to FWU SMC handler and return its return
267 * value
268 */
269 if (is_fwu_fid(smc_fid)) {
270 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
271 handle, flags);
272 }
273#endif
274
275 switch (smc_fid) {
276 case BL1_SMC_CALL_COUNT:
277 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
278
279 case BL1_SMC_UID:
280 SMC_UUID_RET(handle, bl1_svc_uid);
281
282 case BL1_SMC_VERSION:
283 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
284
285 default:
286 break;
287 }
288
289 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid);
290 SMC_RET1(handle, SMC_UNK);
291}