Soby Mathew | 3fd5ddf | 2014-08-18 16:57:56 +0100 | [diff] [blame] | 1 | ARM CPU Errata Workarounds |
| 2 | ========================== |
| 3 | |
Sandrine Bailleux | 4480425 | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 4 | ARM Trusted Firmware exports a series of build flags which control the |
Soby Mathew | 3fd5ddf | 2014-08-18 16:57:56 +0100 | [diff] [blame] | 5 | errata workarounds that are applied to each CPU by the reset handler. The |
| 6 | errata details can be found in the CPU specifc errata documents published |
| 7 | by ARM. The errata workarounds are implemented for a particular revision |
Soby Mathew | 7395a72 | 2014-09-22 12:11:36 +0100 | [diff] [blame^] | 8 | or a set of processor revisions. This is checked by reset handler at runtime. |
Soby Mathew | 3fd5ddf | 2014-08-18 16:57:56 +0100 | [diff] [blame] | 9 | Each errata workaround is identified by its `ID` as specified in the processor's |
| 10 | errata notice document. The format of the define used to enable/disable the |
| 11 | errata is `ERRATA_<Processor name>_<ID>` where the `Processor name` |
| 12 | is either `A57` for the `Cortex_A57` CPU or `A53` for `Cortex_A53` CPU. |
| 13 | |
| 14 | All workarounds are disabled by default. The platform is reponsible for |
| 15 | enabling these workarounds according to its requirement by defining the |
Soby Mathew | 7395a72 | 2014-09-22 12:11:36 +0100 | [diff] [blame^] | 16 | errata workaround build flags in the platform specific makefile. In case |
| 17 | these workarounds are enabled for the wrong CPU revision then the errata |
| 18 | workaround is not applied. In the DEBUG build, this is indicated by |
| 19 | printing a warning to the crash console. |
Soby Mathew | 3fd5ddf | 2014-08-18 16:57:56 +0100 | [diff] [blame] | 20 | |
| 21 | In the current implementation, a platform which has more than 1 variant |
| 22 | with different revisions of a processor has no runtime mechanism available |
| 23 | for it to specify which errata workarounds should be enabled or not. |
| 24 | |
Sandrine Bailleux | 4480425 | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 25 | The value of the build flags are 0 by default, that is, disabled. Any other |
Soby Mathew | 3fd5ddf | 2014-08-18 16:57:56 +0100 | [diff] [blame] | 26 | value will enable it. |
| 27 | |
Soby Mathew | 7395a72 | 2014-09-22 12:11:36 +0100 | [diff] [blame^] | 28 | For Cortex-A57, following errata build flags are defined : |
Soby Mathew | 3fd5ddf | 2014-08-18 16:57:56 +0100 | [diff] [blame] | 29 | |
Soby Mathew | 7395a72 | 2014-09-22 12:11:36 +0100 | [diff] [blame^] | 30 | * `ERRATA_A57_806969`: This applies errata 806969 workaround to Cortex-A57 |
Soby Mathew | 3fd5ddf | 2014-08-18 16:57:56 +0100 | [diff] [blame] | 31 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 32 | |
Soby Mathew | 7395a72 | 2014-09-22 12:11:36 +0100 | [diff] [blame^] | 33 | * `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57 |
Soby Mathew | 3fd5ddf | 2014-08-18 16:57:56 +0100 | [diff] [blame] | 34 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 35 | |
| 36 | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| 37 | |
| 38 | _Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._ |