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Arunachalam Ganapathya5b17762020-04-27 14:33:00 +01001/*
Usama Arif6ddc37f2021-01-17 18:05:08 +00002 * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
Arunachalam Ganapathya5b17762020-04-27 14:33:00 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <plat_topology.h>
9#include <tftf_lib.h>
10
11static const struct {
12 unsigned int cluster_id;
13 unsigned int cpu_id;
14} tc0_cores[] = {
Usama Arif6ddc37f2021-01-17 18:05:08 +000015 /* Cluster0: 8 cores*/
Arunachalam Ganapathya5b17762020-04-27 14:33:00 +010016 { 0, 0 },
17 { 0, 1 },
18 { 0, 2 },
Usama Arif6ddc37f2021-01-17 18:05:08 +000019 { 0, 3 },
20 { 0, 4 },
21 { 0, 5 },
22 { 0, 6 },
23 { 0, 7 }
Arunachalam Ganapathya5b17762020-04-27 14:33:00 +010024};
25
26/*
27 * The power domain tree descriptor. The cluster power domains are
28 * arranged so that when the PSCI generic code creates the power domain tree,
29 * the indices of the CPU power domain nodes it allocates match the linear
30 * indices returned by plat_core_pos_by_mpidr().
31 */
32const unsigned char tc0_pd_tree_desc[] = {
33 /* Number of root nodes */
34 TC0_CLUSTER_COUNT,
35 /* Number of children for the 1st node */
36 TC0_MAX_CPUS_PER_CLUSTER,
37 /* Number of children for the 2nd node */
38 TC0_MAX_CPUS_PER_CLUSTER
39};
40
41const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
42{
43 return tc0_pd_tree_desc;
44}
45
46uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
47{
48 uint64_t mpid;
49
50 assert(core_pos < PLATFORM_CORE_COUNT);
51
52 mpid = (uint64_t)make_mpid(tc0_cores[core_pos].cluster_id,
53 tc0_cores[core_pos].cpu_id);
54
55 return mpid;
56}