Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 1 | /* |
Deepika Bhavnani | c249d5e | 2020-02-06 16:29:45 -0600 | [diff] [blame] | 2 | * Copyright (c) 2018-2020, Arm Limited. All rights reserved. |
Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * Definitions related to the Power State Coordination Interface (PSCI) |
| 9 | * as per the SMC Calling Convention. |
| 10 | * |
| 11 | * PSCI calls are a subset of the Standard Service Calls. |
| 12 | */ |
| 13 | |
| 14 | #ifndef __PSCI_H__ |
| 15 | #define __PSCI_H__ |
| 16 | |
| 17 | #ifndef __ASSEMBLY__ |
| 18 | #include <assert.h> |
| 19 | #include <platform_def.h> |
| 20 | #include <stdbool.h> |
| 21 | #include <stdint.h> |
| 22 | #endif |
| 23 | |
| 24 | /******************************************************************************* |
| 25 | * Macro to create the array entry for psci_functions[] |
| 26 | ******************************************************************************/ |
| 27 | #define DEFINE_PSCI_FUNC(_func_id, _mandatory) \ |
| 28 | { SMC_##_func_id, _mandatory, "SMC_" # _func_id } |
| 29 | |
| 30 | /******************************************************************************* |
| 31 | * Defines for runtime services function ids |
| 32 | ******************************************************************************/ |
| 33 | #define SMC_PSCI_VERSION 0x84000000 |
| 34 | #define SMC_PSCI_CPU_SUSPEND_AARCH32 0x84000001 |
| 35 | #define SMC_PSCI_CPU_SUSPEND_AARCH64 0xc4000001 |
| 36 | #define SMC_PSCI_CPU_OFF 0x84000002 |
| 37 | #define SMC_PSCI_CPU_ON_AARCH32 0x84000003 |
| 38 | #define SMC_PSCI_CPU_ON_AARCH64 0xc4000003 |
| 39 | #define SMC_PSCI_AFFINITY_INFO_AARCH32 0x84000004 |
| 40 | #define SMC_PSCI_AFFINITY_INFO_AARCH64 0xc4000004 |
| 41 | #define SMC_PSCI_MIG_AARCH32 0x84000005 |
| 42 | #define SMC_PSCI_MIG_AARCH64 0xc4000005 |
| 43 | #define SMC_PSCI_MIG_INFO_TYPE 0x84000006 |
| 44 | #define SMC_PSCI_MIG_INFO_UP_CPU_AARCH32 0x84000007 |
| 45 | #define SMC_PSCI_MIG_INFO_UP_CPU_AARCH64 0xc4000007 |
| 46 | #define SMC_PSCI_SYSTEM_OFF 0x84000008 |
| 47 | #define SMC_PSCI_SYSTEM_RESET 0x84000009 |
| 48 | #define SMC_PSCI_FEATURES 0x8400000a |
| 49 | #define SMC_PSCI_CPU_FREEZE 0x8400000b |
| 50 | #define SMC_PSCI_CPU_DEFAULT_SUSPEND32 0x8400000c |
| 51 | #define SMC_PSCI_CPU_DEFAULT_SUSPEND64 0xc400000c |
| 52 | #define SMC_PSCI_CPU_HW_STATE32 0x8400000d |
| 53 | #define SMC_PSCI_CPU_HW_STATE64 0xc400000d |
| 54 | #define SMC_PSCI_SYSTEM_SUSPEND32 0x8400000e |
| 55 | #define SMC_PSCI_SYSTEM_SUSPEND64 0xc400000e |
| 56 | #define SMC_PSCI_SET_SUSPEND_MODE 0x8400000f |
| 57 | #define SMC_PSCI_STAT_RESIDENCY32 0x84000010 |
| 58 | #define SMC_PSCI_STAT_RESIDENCY64 0xc4000010 |
| 59 | #define SMC_PSCI_STAT_COUNT32 0x84000011 |
| 60 | #define SMC_PSCI_STAT_COUNT64 0xc4000011 |
| 61 | #define SMC_PSCI_RESET2_AARCH32 0x84000012 |
| 62 | #define SMC_PSCI_RESET2_AARCH64 0xc4000012 |
| 63 | #define SMC_PSCI_MEM_PROTECT 0x84000013 |
| 64 | #define SMC_PSCI_MEM_PROTECT_CHECK_RANGE32 0x84000014 |
| 65 | #define SMC_PSCI_MEM_PROTECT_CHECK_RANGE64 0xc4000014 |
| 66 | |
| 67 | /* |
| 68 | * Architecture-specific SMC function IDs |
| 69 | */ |
Deepika Bhavnani | c249d5e | 2020-02-06 16:29:45 -0600 | [diff] [blame] | 70 | #ifdef __aarch64__ |
Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 71 | #define SMC_PSCI_CPU_SUSPEND SMC_PSCI_CPU_SUSPEND_AARCH64 |
| 72 | #define SMC_PSCI_CPU_ON SMC_PSCI_CPU_ON_AARCH64 |
| 73 | #define SMC_PSCI_AFFINITY_INFO SMC_PSCI_AFFINITY_INFO_AARCH64 |
| 74 | #define SMC_PSCI_MIG SMC_PSCI_MIG_AARCH64 |
| 75 | #define SMC_PSCI_MIG_INFO_UP_CPU SMC_PSCI_MIG_INFO_UP_CPU_AARCH64 |
| 76 | #define SMC_PSCI_CPU_DEFAULT_SUSPEND SMC_PSCI_CPU_DEFAULT_SUSPEND64 |
| 77 | #define SMC_PSCI_CPU_HW_STATE SMC_PSCI_CPU_HW_STATE64 |
| 78 | #define SMC_PSCI_SYSTEM_SUSPEND SMC_PSCI_SYSTEM_SUSPEND64 |
| 79 | #define SMC_PSCI_STAT_RESIDENCY SMC_PSCI_STAT_RESIDENCY64 |
| 80 | #define SMC_PSCI_STAT_COUNT SMC_PSCI_STAT_COUNT64 |
| 81 | #define SMC_PSCI_RESET2 SMC_PSCI_RESET2_AARCH64 |
| 82 | #define SMC_PSCI_MEM_PROTECT_CHECK SMC_PSCI_MEM_PROTECT_CHECK_RANGE64 |
| 83 | #else |
| 84 | #define SMC_PSCI_CPU_SUSPEND SMC_PSCI_CPU_SUSPEND_AARCH32 |
| 85 | #define SMC_PSCI_CPU_ON SMC_PSCI_CPU_ON_AARCH32 |
| 86 | #define SMC_PSCI_AFFINITY_INFO SMC_PSCI_AFFINITY_INFO_AARCH32 |
| 87 | #define SMC_PSCI_MIG SMC_PSCI_MIG_AARCH32 |
| 88 | #define SMC_PSCI_MIG_INFO_UP_CPU SMC_PSCI_MIG_INFO_UP_CPU_AARCH32 |
| 89 | #define SMC_PSCI_CPU_DEFAULT_SUSPEND SMC_PSCI_CPU_DEFAULT_SUSPEND32 |
| 90 | #define SMC_PSCI_CPU_HW_STATE SMC_PSCI_CPU_HW_STATE32 |
| 91 | #define SMC_PSCI_SYSTEM_SUSPEND SMC_PSCI_SYSTEM_SUSPEND32 |
| 92 | #define SMC_PSCI_STAT_RESIDENCY SMC_PSCI_STAT_RESIDENCY32 |
| 93 | #define SMC_PSCI_STAT_COUNT SMC_PSCI_STAT_COUNT32 |
| 94 | #define SMC_PSCI_RESET2 SMC_PSCI_RESET2_AARCH32 |
| 95 | #define SMC_PSCI_MEM_PROTECT_CHECK SMC_PSCI_MEM_PROTECT_CHECK_RANGE32 |
| 96 | #endif |
| 97 | |
| 98 | /* |
| 99 | * Number of PSCI calls defined in the PSCI specification. |
| 100 | */ |
| 101 | #define PSCI_NUM_CALLS 33 |
| 102 | |
| 103 | #ifndef __ASSEMBLY__ |
| 104 | typedef struct { |
| 105 | uint32_t id; |
| 106 | bool mandatory; |
| 107 | const char *str; |
| 108 | } psci_function_t; |
| 109 | |
| 110 | extern const psci_function_t psci_functions[PSCI_NUM_CALLS]; |
| 111 | #endif /* __ASSEMBLY__ */ |
| 112 | |
| 113 | /******************************************************************************* |
| 114 | * PSCI Migrate specific defines |
| 115 | ******************************************************************************/ |
| 116 | #define PSCI_TOS_UP_MIG_CAP 0 |
| 117 | #define PSCI_TOS_NOT_UP_MIG_CAP 1 |
| 118 | #define PSCI_TOS_NOT_PRESENT_MP 2 |
| 119 | |
| 120 | /******************************************************************************* |
| 121 | * PSCI CPU_SUSPEND 'power_state' parameter specific defines |
| 122 | ******************************************************************************/ |
| 123 | /* Original format */ |
| 124 | #define PSTATE_ID_SHIFT 0 |
| 125 | #define PSTATE_TYPE_SHIFT 16 |
| 126 | #define PSTATE_AFF_LVL_SHIFT 24 |
| 127 | #define PSTATE_ID_MASK 0xFFFF |
| 128 | #define PSTATE_AFF_LVL_MASK 0x3 |
| 129 | |
| 130 | #define psci_state_id_valid(state_id) \ |
| 131 | (((state_id) & ~PSTATE_ID_MASK) == 0) |
| 132 | |
| 133 | #define psci_affinity_level_valid(aff_level) \ |
| 134 | (((aff_level) & ~PSTATE_AFF_LVL_MASK) == 0) |
| 135 | |
| 136 | /* Extended format */ |
| 137 | #define PSTATE_ID_SHIFT_EXT 0 |
| 138 | #define PSTATE_TYPE_SHIFT_EXT 30 |
| 139 | #define PSTATE_ID_MASK_EXT 0xFFFFFFF |
| 140 | |
| 141 | #define psci_state_id_ext_valid(state_id) \ |
| 142 | (((state_id) & ~PSTATE_ID_MASK_EXT) == 0) |
| 143 | |
| 144 | /* Definitions common to original and extended StateID formats */ |
| 145 | #define PSTATE_TYPE_MASK 0x1 |
| 146 | |
| 147 | #define PSTATE_TYPE_STANDBY 0x0 |
| 148 | #define PSTATE_TYPE_POWERDOWN 0x1 |
| 149 | |
| 150 | #define PSTATE_AFF_LVL_0 0 |
| 151 | #define PSTATE_AFF_LVL_1 1 |
| 152 | #define PSTATE_AFF_LVL_2 2 |
| 153 | #define PSTATE_AFF_LVL_3 3 |
| 154 | |
| 155 | #define psci_state_type_valid(state_type) \ |
| 156 | (((state_type) & ~PSTATE_TYPE_MASK) == 0) |
| 157 | |
| 158 | /******************************************************************************* |
| 159 | * PSCI 'Feature Flags' defines for CPU_SUSPEND |
| 160 | ******************************************************************************/ |
| 161 | #define CPU_SUSPEND_FEAT_OS_INIT_MODE_SHIFT 0 |
| 162 | #define CPU_SUSPEND_FEAT_PSTATE_FORMAT_SHIFT 1 |
| 163 | #define CPU_SUSPEND_FEAT_PSTATE_FORMAT_ORIGINAL 0 |
| 164 | #define CPU_SUSPEND_FEAT_PSTATE_FORMAT_EXTENDED 1 |
| 165 | |
| 166 | #define CPU_SUSPEND_FEAT_VALID_MASK \ |
| 167 | ((1 << CPU_SUSPEND_FEAT_OS_INIT_MODE_SHIFT) | \ |
| 168 | (1 << CPU_SUSPEND_FEAT_PSTATE_FORMAT_SHIFT)) |
| 169 | |
| 170 | /******************************************************************************* |
| 171 | * PSCI 'Feature Flags' defines for functions other than CPU_SUSPEND |
| 172 | ******************************************************************************/ |
| 173 | #define PSCI_FEATURE_FLAGS_ZERO 0 |
| 174 | |
| 175 | #ifndef __ASSEMBLY__ |
| 176 | |
| 177 | /* |
| 178 | * Construct the local State-ID for a particular level according to |
| 179 | * the platform specific local state-ID width. |
| 180 | */ |
| 181 | #define psci_make_local_state_id(level, local_state) \ |
| 182 | (((local_state) & ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)) \ |
| 183 | << (PLAT_LOCAL_PSTATE_WIDTH * (level))) |
| 184 | #endif |
| 185 | |
| 186 | /******************************************************************************* |
| 187 | * PSCI version |
| 188 | ******************************************************************************/ |
| 189 | #define PSCI_MAJOR_VER 1 |
| 190 | #define PSCI_MINOR_VER 1 |
| 191 | #define PSCI_MAJOR_VER_SHIFT 16 |
| 192 | #define PSCI_MAJOR_VER_MASK 0xFFFF0000 |
| 193 | #define PSCI_VERSION(major, minor) ((major << PSCI_MAJOR_VER_SHIFT) \ |
| 194 | | minor) |
| 195 | |
| 196 | /******************************************************************************* |
| 197 | * PSCI error codes |
| 198 | ******************************************************************************/ |
| 199 | #define PSCI_E_SUCCESS 0 |
| 200 | #define PSCI_E_NOT_SUPPORTED -1 |
| 201 | #define PSCI_E_INVALID_PARAMS -2 |
| 202 | #define PSCI_E_DENIED -3 |
| 203 | #define PSCI_E_ALREADY_ON -4 |
| 204 | #define PSCI_E_ON_PENDING -5 |
| 205 | #define PSCI_E_INTERN_FAIL -6 |
| 206 | #define PSCI_E_NOT_PRESENT -7 |
| 207 | #define PSCI_E_DISABLED -8 |
| 208 | #define PSCI_E_INVALID_ADDRESS -9 |
| 209 | |
| 210 | /******************************************************************************* |
Wing Li | cb88add | 2022-10-29 02:32:06 +0100 | [diff] [blame^] | 211 | * PSCI suspend mode related constants. |
| 212 | ******************************************************************************/ |
| 213 | #define PSCI_PLAT_COORD 0x0 |
| 214 | #define PSCI_OS_INIT 0x1 |
| 215 | |
| 216 | /******************************************************************************* |
Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 217 | * PSCI affinity state related constants. |
| 218 | ******************************************************************************/ |
| 219 | #define PSCI_STATE_ON 0x0 |
| 220 | #define PSCI_STATE_OFF 0x1 |
| 221 | #define PSCI_STATE_ON_PENDING 0x2 |
| 222 | |
| 223 | /******************************************************************************* |
| 224 | * PSCI node hardware state related constants. |
| 225 | ******************************************************************************/ |
| 226 | #define PSCI_HW_STATE_ON 0x0 |
| 227 | #define PSCI_HW_STATE_OFF 0x1 |
| 228 | #define PSCI_HW_STATE_STANDBY 0x2 |
| 229 | |
| 230 | #endif /* __PSCI_H__ */ |