| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2017, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <assert_macros.S> |
| 9 | #include <asm_macros.S> |
| 10 | |
| 11 | .globl amu_group0_cnt_read_internal |
| 12 | .globl amu_group1_cnt_read_internal |
| 13 | |
| 14 | /* |
| 15 | * uint64_t amu_group0_cnt_read_internal(int idx); |
| 16 | * |
| 17 | * Given `idx`, read the corresponding AMU counter |
| 18 | * and return it in `x0`. |
| 19 | */ |
| 20 | func amu_group0_cnt_read_internal |
| 21 | #if ENABLE_ASSERTIONS |
| 22 | /* |
| 23 | * It can be dangerous to call this function with an |
| 24 | * out of bounds index. Ensure `idx` is valid. |
| 25 | */ |
| 26 | mov x1, x0 |
| 27 | lsr x1, x1, #2 |
| 28 | cmp x1, #0 |
| 29 | ASM_ASSERT(eq) |
| 30 | #endif |
| 31 | |
| 32 | /* |
| 33 | * Given `idx` calculate address of mrs/ret instruction pair |
| 34 | * in the table below. |
| 35 | */ |
| 36 | adr x1, 1f |
| 37 | lsl x0, x0, #3 /* each mrs/ret sequence is 8 bytes */ |
| 38 | add x1, x1, x0 |
| 39 | br x1 |
| 40 | |
| 41 | 1: |
| 42 | mrs x0, AMEVCNTR00_EL0 /* index 0 */ |
| 43 | ret |
| 44 | mrs x0, AMEVCNTR01_EL0 /* index 1 */ |
| 45 | ret |
| 46 | mrs x0, AMEVCNTR02_EL0 /* index 2 */ |
| 47 | ret |
| 48 | mrs x0, AMEVCNTR03_EL0 /* index 3 */ |
| 49 | ret |
| 50 | endfunc amu_group0_cnt_read_internal |
| 51 | |
| 52 | /* |
| 53 | * uint64_t amu_group1_cnt_read_internal(int idx); |
| 54 | * |
| 55 | * Given `idx`, read the corresponding AMU counter |
| 56 | * and return it in `x0`. |
| 57 | */ |
| 58 | func amu_group1_cnt_read_internal |
| 59 | #if ENABLE_ASSERTIONS |
| 60 | /* |
| 61 | * It can be dangerous to call this function with an |
| 62 | * out of bounds index. Ensure `idx` is valid. |
| 63 | */ |
| 64 | mov x1, x0 |
| 65 | lsr x1, x1, #4 |
| 66 | cmp x1, #0 |
| 67 | ASM_ASSERT(eq) |
| 68 | #endif |
| 69 | |
| 70 | /* |
| 71 | * Given `idx` calculate address of mrs/ret instruction pair |
| 72 | * in the table below. |
| 73 | */ |
| 74 | adr x1, 1f |
| 75 | lsl x0, x0, #3 /* each mrs/ret sequence is 8 bytes */ |
| 76 | add x1, x1, x0 |
| 77 | br x1 |
| 78 | |
| 79 | 1: |
| 80 | mrs x0, AMEVCNTR10_EL0 /* index 0 */ |
| 81 | ret |
| 82 | mrs x0, AMEVCNTR11_EL0 /* index 1 */ |
| 83 | ret |
| 84 | mrs x0, AMEVCNTR12_EL0 /* index 2 */ |
| 85 | ret |
| 86 | mrs x0, AMEVCNTR13_EL0 /* index 3 */ |
| 87 | ret |
| 88 | mrs x0, AMEVCNTR14_EL0 /* index 4 */ |
| 89 | ret |
| 90 | mrs x0, AMEVCNTR15_EL0 /* index 5 */ |
| 91 | ret |
| 92 | mrs x0, AMEVCNTR16_EL0 /* index 6 */ |
| 93 | ret |
| 94 | mrs x0, AMEVCNTR17_EL0 /* index 7 */ |
| 95 | ret |
| 96 | mrs x0, AMEVCNTR18_EL0 /* index 8 */ |
| 97 | ret |
| 98 | mrs x0, AMEVCNTR19_EL0 /* index 9 */ |
| 99 | ret |
| 100 | mrs x0, AMEVCNTR1A_EL0 /* index 10 */ |
| 101 | ret |
| 102 | mrs x0, AMEVCNTR1B_EL0 /* index 11 */ |
| 103 | ret |
| 104 | mrs x0, AMEVCNTR1C_EL0 /* index 12 */ |
| 105 | ret |
| 106 | mrs x0, AMEVCNTR1D_EL0 /* index 13 */ |
| 107 | ret |
| 108 | mrs x0, AMEVCNTR1E_EL0 /* index 14 */ |
| 109 | ret |
| 110 | mrs x0, AMEVCNTR1F_EL0 /* index 15 */ |
| 111 | ret |
| 112 | endfunc amu_group1_cnt_read_internal |