blob: 893a2c50221ea1a337ad013d2e20e8f280d04858 [file] [log] [blame]
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02001/*
2 * Copyright (c) 2015-2017, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __NORFLASH_H_
8#define __NORFLASH_H_
9
10#include <stdint.h>
11
12/* First bus cycle */
13#define NOR_CMD_READ_ARRAY 0xFF
14#define NOR_CMD_READ_ID_CODE 0x90
15#define NOR_CMD_READ_QUERY 0x98
16#define NOR_CMD_READ_STATUS_REG 0x70
17#define NOR_CMD_CLEAR_STATUS_REG 0x50
18#define NOR_CMD_WRITE_TO_BUFFER 0xE8
19#define NOR_CMD_WORD_PROGRAM 0x40
20#define NOR_CMD_BLOCK_ERASE 0x20
21#define NOR_CMD_LOCK_UNLOCK 0x60
22#define NOR_CMD_BLOCK_ERASE_ACK 0xD0
23#define NOR_CMD_BUFFERED_PROGRAM 0xE8
24
25/* Second bus cycle */
26#define NOR_LOCK_BLOCK 0x01
27#define NOR_UNLOCK_BLOCK 0xD0
28#define NOR_CMD_BUFFERED_PROGRAM_ACK 0xD0
29
30/* Status register bits */
31#define NOR_DWS (1 << 7)
32#define NOR_ESS (1 << 6)
33#define NOR_ES (1 << 5)
34#define NOR_PS (1 << 4)
35#define NOR_VPPS (1 << 3)
36#define NOR_PSS (1 << 2)
37#define NOR_BLS (1 << 1)
38#define NOR_BWS (1 << 0)
39
40#endif /* __NORFLASH_H_ */
41