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Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02001/*
Alexei Fedorov2198e9a2019-12-12 14:14:55 +00002 * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <tftf.h>
10
11 .globl tftf_entrypoint
12 .globl tftf_hotplug_entry
13
14/* ----------------------------------------------------------------------------
15 * Cold boot entry point for the primary CPU.
16 * ----------------------------------------------------------------------------
17 */
18func tftf_entrypoint
Harrison Mutai112498c2025-02-18 11:52:12 +000019#if TRANSFER_LIST
20 mov r4, r0
21 mov r5, r1
22 mov r6, r2
23 mov r7, r3
24#endif
Sandrine Bailleux39caa2c2018-12-18 10:53:34 +010025 bl arch_init
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020026
27 /* --------------------------------------------------------------------
Alexei Fedorov2198e9a2019-12-12 14:14:55 +000028 * Invalidate the RW memory used by TFTF image.
29 * This is done to safeguard against possible corruption of this
30 * memory by dirty cache lines in a system cache as a result of use
31 * by an earlier boot loader stage.
32 * --------------------------------------------------------------------
33 */
34 ldr r0, =__DATA_START__
35 ldr r1, =__DATA_END__
36 sub r1, r1, r0
37 bl inv_dcache_range
38
39 /* --------------------------------------------------------------------
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020040 * This code is expected to be executed only by the primary CPU.
41 * Save the mpid for the first core that executes and if a secondary
42 * CPU has lost its way make it spin forever.
43 * --------------------------------------------------------------------
44 */
45 bl save_primary_mpid
46
47 /* --------------------------------------------------------------------
48 * Zero out NOBITS sections. There are 2 of them:
49 * - the .bss section;
50 * - the coherent memory section.
51 * --------------------------------------------------------------------
52 */
53 ldr r0, =__BSS_START__
54 ldr r1, =__BSS_SIZE__
55 bl zeromem
56
57 ldr r0, =__COHERENT_RAM_START__
58 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
59 bl zeromem
60
61 /* --------------------------------------------------------------------
Harrison Mutai112498c2025-02-18 11:52:12 +000062 * Save transfer list and hw_config addresses passed in registers r0 to
63 * r3 from the previous bootloader.
64 * --------------------------------------------------------------------
65 */
66#if TRANSFER_LIST
67 mov r0, r4
68 mov r1, r5
69 mov r2, r6
70 mov r3, r7
71 bl save_handoff_params
72#endif
73
74 /* --------------------------------------------------------------------
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020075 * Give ourselves a small coherent stack to ease the pain of
76 * initializing the MMU
77 * --------------------------------------------------------------------
78 */
79 ldcopr r0, MPIDR
80 bl platform_set_coherent_stack
81
82 bl tftf_early_platform_setup
83 bl tftf_plat_arch_setup
84
85 /* --------------------------------------------------------------------
86 * Give ourselves a stack allocated in Normal -IS-WBWA memory
87 * --------------------------------------------------------------------
88 */
89 ldcopr r0, MPIDR
90 bl platform_set_stack
91
92 /* --------------------------------------------------------------------
93 * tftf_cold_boot_main() will perform the remaining architectural and
94 * platform setup, initialise the test framework's state, then run the
95 * tests.
96 * --------------------------------------------------------------------
97 */
98 b tftf_cold_boot_main
99endfunc tftf_entrypoint
100
101/* ----------------------------------------------------------------------------
102 * Entry point for a CPU that has just been powered up.
103 * In : r0 - context_id
104 * ----------------------------------------------------------------------------
105 */
106func tftf_hotplug_entry
107
108 /* --------------------------------------------------------------------
109 * Preserve the context_id in a callee-saved register
110 * --------------------------------------------------------------------
111 */
112 mov r4, r0
113
Sandrine Bailleux39caa2c2018-12-18 10:53:34 +0100114 bl arch_init
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200115
116 /* --------------------------------------------------------------------
117 * Give ourselves a small coherent stack to ease the pain of
118 * initializing the MMU
119 * --------------------------------------------------------------------
120 */
121 ldcopr r0, MPIDR
122 bl platform_set_coherent_stack
123
124 /* --------------------------------------------------------------------
125 * Enable the MMU
126 * --------------------------------------------------------------------
127 */
128 bl tftf_plat_enable_mmu
129
130 /* --------------------------------------------------------------------
131 * Give ourselves a stack in normal memory.
132 * --------------------------------------------------------------------
133 */
134 ldcopr r0, MPIDR
135 bl platform_set_stack
136
137 /* --------------------------------------------------------------------
138 * Save the context_id for later retrieval by tests
139 * --------------------------------------------------------------------
140 */
141 ldcopr r0, MPIDR
142 ldr r1, =MPID_MASK
143 and r0, r0, r1
144 bl platform_get_core_pos
145
146 mov r1, r4
147
148 bl tftf_set_cpu_on_ctx_id
149
150 /* --------------------------------------------------------------------
151 * Jump to warm boot main function
152 * --------------------------------------------------------------------
153 */
154 b tftf_warm_boot_main
155endfunc tftf_hotplug_entry
156
157/* ----------------------------------------------------------------------------
Sandrine Bailleux39caa2c2018-12-18 10:53:34 +0100158 * Initialize architectural state.
159 * ----------------------------------------------------------------------------
160 */
161func arch_init
162 /* Set the exception vectors. */
163 ldr r0, =tftf_vector
164 stcopr r0, HVBAR
165
166 /* Enable the instruction cache. */
167 ldr r0, =(HSCTLR_RES1 | HSCTLR_I_BIT)
168 stcopr r0, HSCTLR
169
170 isb
171 bx lr
172endfunc arch_init
173
174/* ----------------------------------------------------------------------------
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200175 * Saves the mpid of the primary core and if the primary core
176 * is already saved then it loops infinitely.
177 * ----------------------------------------------------------------------------
178 */
179func save_primary_mpid
180 ldr r1, =tftf_primary_core
181 ldr r0, [r1]
182 mov r2, #INVALID_MPID
183 cmp r0, r2
184 bne panic
185 ldr r2, =MPID_MASK
186 ldcopr r0, MPIDR
187 and r0, r0, r2
188 str r0, [r1]
189 bx lr
190panic:
191 /* Primary core MPID already saved */
192 b panic
193endfunc save_primary_mpid
Harrison Mutai112498c2025-02-18 11:52:12 +0000194
195/* ----------------------------------------------------------------------------
196 * Save transfer list and hw_config addresses passed in registers r0 to r3 from
197 * the previous bootloader.
198 * ----------------------------------------------------------------------------
199 */
200func save_handoff_params
201 ldr r4, =ns_tl
202 str r3, [r4]
203 ldr r4, =tl_signature
204 str r1, [r4]
205 ldr r4, =hw_config_base
206 str r2, [r4]
207 bx lr
208endfunc save_handoff_params