test: exercise DMA isolation for secure access to ns memory
This test helps to validate a scenario where a secure stream
belonging to Cactus SP accesses non-secure IPA space.
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I8085f2974d53b9cec9b3ae4a17fd328607b76e2b
diff --git a/plat/arm/fvp/include/platform_def.h b/plat/arm/fvp/include/platform_def.h
index e6ae4d7..60c33e9 100644
--- a/plat/arm/fvp/include/platform_def.h
+++ b/plat/arm/fvp/include/platform_def.h
@@ -259,11 +259,11 @@
#define MAX_MMAP_REGIONS 50
#else
#if IMAGE_CACTUS
-#define MAX_XLAT_TABLES 9
+#define MAX_XLAT_TABLES 12
#else
#define MAX_XLAT_TABLES 5
#endif
-#define MAX_MMAP_REGIONS 16
+#define MAX_MMAP_REGIONS 20
#endif
/*******************************************************************************
diff --git a/spm/cactus/cactus_main.c b/spm/cactus/cactus_main.c
index be6baa9..e0e2c88 100644
--- a/spm/cactus/cactus_main.c
+++ b/spm/cactus/cactus_main.c
@@ -115,6 +115,8 @@
/* scratch memory allocated to be used for running SMMU tests */
MAP_REGION_FLAT(PLAT_CACTUS_MEMCPY_BASE, PLAT_CACTUS_MEMCPY_RANGE,
MT_MEMORY | MT_RW),
+ MAP_REGION_FLAT(PLAT_CACTUS_NS_MEMCPY_BASE, PLAT_CACTUS_MEMCPY_RANGE,
+ MT_MEMORY | MT_RW | MT_NS),
{0}
};
diff --git a/spm/cactus/plat/arm/fvp/fdts/cactus.dts b/spm/cactus/plat/arm/fvp/fdts/cactus.dts
index 16c3392..3effb39 100644
--- a/spm/cactus/plat/arm/fvp/fdts/cactus.dts
+++ b/spm/cactus/plat/arm/fvp/fdts/cactus.dts
@@ -96,10 +96,13 @@
};
smmuv3-ns-region {
- description = "smmuv3-ns-region";
+ description = "smmuv3-memcpy-ns-region";
pages-count = <8>;
base-address = <0x0 0x90000000>;
attributes = <0xb>; /* ns-read-write */
+ smmu-id = <0>;
+ stream-ids = <0x0 0x1>;
+ stream-ids-access-permissions = <0xb 0xb>;
};
};
diff --git a/tftf/tests/runtime_services/secure_service/test_spm_smmu.c b/tftf/tests/runtime_services/secure_service/test_spm_smmu.c
index ae2068a..6237eb8 100644
--- a/tftf/tests/runtime_services/secure_service/test_spm_smmu.c
+++ b/tftf/tests/runtime_services/secure_service/test_spm_smmu.c
@@ -20,8 +20,20 @@
#define TEST_DMA_ENGINE_MEMCPY (2U)
#define TEST_DMA_ENGINE_RAND48 (3U)
-#define TEST_DMA_ENGINE_ATTR_DEST_ACACHE_RAWAWB_S (0xffU)
-#define TEST_DMA_ENGINE_ATTR_DEST_ACACHE_RAWAWB_NS (0x2ffU)
+/*
+ * Attribute encoding for Inner and Outer:
+ * Read-Allocate Write-Allocate Write-Back Normal Memory
+ */
+#define ATTR_ACACHE_RAWAWB_S (0xffU)
+#define ATTR_ACACHE_RAWAWB_NS (0x2ffU)
+
+/* Source attributes occupy the bottom halfword */
+#define DMA_ENGINE_ATTR_SRC_ACACHE_RAWAWB_S ATTR_ACACHE_RAWAWB_S
+#define DMA_ENGINE_ATTR_SRC_ACACHE_RAWAWB_NS ATTR_ACACHE_RAWAWB_NS
+
+/* Destination attributes occupy the top halfword */
+#define DMA_ENGINE_ATTR_DEST_ACACHE_RAWAWB_S (ATTR_ACACHE_RAWAWB_S << 16)
+#define DMA_ENGINE_ATTR_DEST_ACACHE_RAWAWB_NS (ATTR_ACACHE_RAWAWB_NS << 16)
/**************************************************************************
* test_smmu_spm
@@ -54,7 +66,7 @@
TEST_DMA_ENGINE_RAND48,
PLAT_CACTUS_MEMCPY_BASE,
PLAT_CACTUS_MEMCPY_RANGE / 2,
- TEST_DMA_ENGINE_ATTR_DEST_ACACHE_RAWAWB_S << 16);
+ DMA_ENGINE_ATTR_DEST_ACACHE_RAWAWB_S);
/* Expect the SMMU DMA operation to pass. */
if (cactus_get_response(ret) != CACTUS_SUCCESS) {
@@ -70,8 +82,27 @@
TEST_DMA_ENGINE_MEMCPY,
PLAT_CACTUS_MEMCPY_BASE,
PLAT_CACTUS_MEMCPY_RANGE,
- (TEST_DMA_ENGINE_ATTR_DEST_ACACHE_RAWAWB_S << 16) |
- TEST_DMA_ENGINE_ATTR_DEST_ACACHE_RAWAWB_S);
+ DMA_ENGINE_ATTR_DEST_ACACHE_RAWAWB_S |
+ DMA_ENGINE_ATTR_SRC_ACACHE_RAWAWB_S);
+
+ /* Expect the SMMU DMA operation to pass. */
+ if (cactus_get_response(ret) != CACTUS_SUCCESS) {
+ return TEST_RESULT_FAIL;
+ }
+
+ /*
+ * Copy first half to second half of the non-secure buffer and
+ * check both match.
+ * Source and destination memory attributes are non-secure rawaWB.
+ * This test helps to validate a scenario where a secure stream
+ * belonging to Cactus SP accesses non-secure IPA space.
+ */
+ ret = cactus_send_dma_cmd(HYP_ID, SP_ID(1),
+ TEST_DMA_ENGINE_MEMCPY,
+ PLAT_CACTUS_NS_MEMCPY_BASE,
+ PLAT_CACTUS_MEMCPY_RANGE,
+ DMA_ENGINE_ATTR_DEST_ACACHE_RAWAWB_NS |
+ DMA_ENGINE_ATTR_SRC_ACACHE_RAWAWB_NS);
/* Expect the SMMU DMA operation to pass. */
if (cactus_get_response(ret) != CACTUS_SUCCESS) {
@@ -127,7 +158,7 @@
TEST_DMA_ENGINE_RAND48,
PLAT_CACTUS_NS_MEMCPY_BASE,
PLAT_CACTUS_MEMCPY_RANGE,
- TEST_DMA_ENGINE_ATTR_DEST_ACACHE_RAWAWB_NS << 16);
+ DMA_ENGINE_ATTR_DEST_ACACHE_RAWAWB_NS);
/* Update the buffer back to NS PAS. */
retmm = host_rmi_granule_undelegate((u_register_t)PLAT_CACTUS_NS_MEMCPY_BASE);