blob: b7664d5da837a7f5aaab7f48bea8d1a9345bbf64 [file] [log] [blame]
Varun Wadekar4d0dcc82020-06-25 19:39:27 -07001/*
2 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <assert.h>
9#include <plat_topology.h>
10#include <platform_def.h>
11#include <stddef.h>
12
13#include <tftf_lib.h>
14
15static const struct {
16 unsigned int cluster_id;
17 unsigned int cpu_id;
18} tegra210_cores[PLATFORM_CORE_COUNT] = {
19 { 0, 0 },
20 { 0, 1 },
21 { 0, 2 },
22 { 0, 3 }
23};
24
25/*
26 * The Tegra210 power domain tree descriptor. Tegra186 implements a system
27 * power domain at the level 2. The first entry in the power domain descriptor
28 * specifies the number of power domains at the highest power level.
29 */
30static const unsigned char tegra210_power_domain_tree_desc[] = {
31 /* Number of root nodes */
32 PLATFORM_SYSTEM_COUNT,
33 /* Number of children of root node */
34 PLATFORM_CLUSTER_COUNT,
35 /* Number of children for the cluster */
36 PLATFORM_CORES_PER_CLUSTER
37};
38
39const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
40{
41 return tegra210_power_domain_tree_desc;
42}
43
44uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
45{
46 assert(core_pos < PLATFORM_CORE_COUNT);
47
48 return (uint64_t)make_mpid(tegra210_cores[core_pos].cluster_id,
49 tegra210_cores[core_pos].cpu_id);
50}