| Madhukar Pappireddy | 172523b | 2020-12-31 19:25:33 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /* The test engine supports numerous frames but we only use a few */ |
| 8 | #define FRAME_COUNT (2U) |
| 9 | #define FRAME_SIZE (0x80U) /* 128 bytes */ |
| 10 | #define F_IDX(n) (n * FRAME_SIZE) |
| 11 | |
| 12 | /* Commands supported by SMMUv3TestEngine built into the AEM */ |
| 13 | #define ENGINE_NO_FRAME (0U) |
| 14 | #define ENGINE_HALTED (1U) |
| 15 | |
| 16 | /* |
| 17 | * ENGINE_MEMCPY: Read and Write transactions |
| 18 | * ENGINE_RAND48: Only Write transactions: Source address not required |
| 19 | * ENGINE_SUM64: Only read transactions: Target address not required |
| 20 | */ |
| 21 | #define ENGINE_MEMCPY (2U) |
| 22 | #define ENGINE_RAND48 (3U) |
| 23 | #define ENGINE_SUM64 (4U) |
| 24 | #define ENGINE_ERROR (0xFFFFFFFFU) |
| 25 | #define ENGINE_MIS_CFG (ENGINE_ERROR - 1) |
| 26 | |
| 27 | /* |
| 28 | * Refer to: |
| 29 | * https://developer.arm.com/documentation/100964/1111-00/Trace-components/SMMUv3TestEngine---trace |
| 30 | */ |
| 31 | |
| 32 | /* Offset of various control fields belonging to User Frame */ |
| 33 | #define CMD_OFF (0x0U) |
| 34 | #define UCTRL_OFF (0x4U) |
| Olivier Deprez | e71ec9c | 2022-02-28 18:57:26 +0100 | [diff] [blame] | 35 | #define ATTR_OFF (0x20U) |
| Madhukar Pappireddy | 172523b | 2020-12-31 19:25:33 -0600 | [diff] [blame] | 36 | #define SEED_OFF (0x24U) |
| 37 | #define BEGIN_OFF (0x28U) |
| 38 | #define END_CTRL_OFF (0x30U) |
| 39 | #define STRIDE_OFF (0x38U) |
| 40 | #define UDATA_OFF (0x40U) |
| 41 | |
| 42 | /* Offset of various control fields belonging to PRIV Frame */ |
| 43 | #define PCTRL_OFF (0x0U) |
| 44 | #define DOWNSTREAM_PORT_OFF (0x4U) |
| 45 | #define STREAM_ID_OFF (0x8U) |
| 46 | #define SUBSTREAM_ID_OFF (0xCU) |