Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2018, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <assert.h> |
| 10 | #include <debug.h> |
| 11 | #include <gic_v2.h> |
| 12 | |
| 13 | void arm_gic_enable_interrupts_local(void) |
| 14 | { |
| 15 | gicv2_enable_cpuif(); |
| 16 | } |
| 17 | |
| 18 | void arm_gic_setup_local(void) |
| 19 | { |
| 20 | gicv2_probe_gic_cpu_id(); |
| 21 | gicv2_setup_cpuif(); |
| 22 | } |
| 23 | |
| 24 | void arm_gic_disable_interrupts_local(void) |
| 25 | { |
| 26 | gicv2_disable_cpuif(); |
| 27 | } |
| 28 | |
| 29 | void arm_gic_save_context_local(void) |
| 30 | { |
| 31 | gicv2_save_cpuif_context(); |
| 32 | } |
| 33 | |
| 34 | void arm_gic_restore_context_local(void) |
| 35 | { |
| 36 | gicv2_restore_cpuif_context(); |
| 37 | } |
| 38 | |
| 39 | void arm_gic_save_context_global(void) |
| 40 | { |
| 41 | gicv2_save_sgi_ppi_context(); |
| 42 | } |
| 43 | |
| 44 | void arm_gic_restore_context_global(void) |
| 45 | { |
| 46 | gicv2_setup_distif(); |
| 47 | gicv2_restore_sgi_ppi_context(); |
| 48 | } |
| 49 | |
| 50 | void arm_gic_setup_global(void) |
| 51 | { |
| 52 | gicv2_setup_distif(); |
| 53 | } |
| 54 | |
| 55 | unsigned int arm_gic_get_intr_priority(unsigned int num) |
| 56 | { |
| 57 | return gicv2_gicd_get_ipriorityr(num); |
| 58 | } |
| 59 | |
| 60 | void arm_gic_set_intr_priority(unsigned int num, |
| 61 | unsigned int priority) |
| 62 | { |
| 63 | gicv2_gicd_set_ipriorityr(num, priority); |
| 64 | } |
| 65 | |
| 66 | void arm_gic_send_sgi(unsigned int sgi_id, unsigned int core_pos) |
| 67 | { |
| 68 | gicv2_send_sgi(sgi_id, core_pos); |
| 69 | } |
| 70 | |
| 71 | void arm_gic_set_intr_target(unsigned int num, unsigned int core_pos) |
| 72 | { |
| 73 | gicv2_set_itargetsr(num, core_pos); |
| 74 | } |
| 75 | |
| 76 | unsigned int arm_gic_intr_enabled(unsigned int num) |
| 77 | { |
| 78 | return gicv2_gicd_get_isenabler(num) != 0; |
| 79 | } |
| 80 | |
| 81 | void arm_gic_intr_enable(unsigned int num) |
| 82 | { |
| 83 | gicv2_gicd_set_isenabler(num); |
| 84 | } |
| 85 | |
| 86 | void arm_gic_intr_disable(unsigned int num) |
| 87 | { |
| 88 | gicv2_gicd_set_icenabler(num); |
| 89 | } |
| 90 | |
| 91 | unsigned int arm_gic_intr_ack(unsigned int *raw_iar) |
| 92 | { |
| 93 | assert(raw_iar); |
| 94 | |
| 95 | *raw_iar = gicv2_gicc_read_iar(); |
| 96 | return get_gicc_iar_intid(*raw_iar); |
| 97 | } |
| 98 | |
| 99 | unsigned int arm_gic_is_intr_pending(unsigned int num) |
| 100 | { |
| 101 | return gicv2_gicd_get_ispendr(num); |
| 102 | } |
| 103 | |
| 104 | void arm_gic_intr_clear(unsigned int num) |
| 105 | { |
| 106 | gicv2_gicd_set_icpendr(num); |
| 107 | } |
| 108 | |
| 109 | void arm_gic_end_of_intr(unsigned int raw_iar) |
| 110 | { |
| 111 | gicv2_gicc_write_eoir(raw_iar); |
| 112 | } |
| 113 | |
| 114 | void arm_gic_init(uintptr_t gicc_base, |
| 115 | uintptr_t gicd_base, |
| 116 | uintptr_t gicr_base) |
| 117 | { |
| 118 | gicv2_init(gicc_base, gicd_base); |
| 119 | INFO("ARM GIC v2 driver initialized\n"); |
| 120 | } |
| 121 | |