blob: 1142b93b27d3d71a16f4ffecf145a5e64c650e7a [file] [log] [blame]
<?xml version="1.0" encoding="utf-8"?>
<!--
Copyright (c) 2021-2023, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
-->
<testsuites>
<testsuite name="Realm payload at EL1" description="Test Realm EL1 framework capabilities" >
<testcase name="Realm EL1 creation and execution test"
function="host_test_realm_create_enter" />
<testcase name="Realm payload multi rec single cpu"
function="host_realm_multi_rec_single_cpu" />
<testcase name="Realm payload multi rec psci denied"
function="host_realm_multi_rec_psci_denied" />
<testcase name="Realm payload multi rec force exit on NS IRQ"
function="host_realm_multi_rec_exit_irq" />
<testcase name="Realm EL1 creation and RSI version"
function="host_test_realm_rsi_version" />
<testcase name="Realm payload boot"
function="host_realm_version_single_cpu" />
<testcase name="Realm payload multi CPU request"
function="host_realm_version_multi_cpu" />
<testcase name="Realm payload Delegate and Undelegate"
function="host_realm_delegate_undelegate" />
<testcase name="Multi CPU Realm payload Delegate and Undelegate"
function="host_realm_delundel_multi_cpu" />
<testcase name="Testing delegation fails"
function="host_realm_fail_del" />
<testcase name="PMUv3 cycle counter functional in Realm"
function="host_realm_pmuv3_cycle_works" />
<testcase name="PMUv3 event counter functional in Realm"
function="host_realm_pmuv3_event_works" />
<testcase name="PMUv3 RSI SMC counter preservation"
function="host_realm_pmuv3_rmm_preserves" />
<testcase name="PMUv3 overflow interrupt"
function="host_realm_pmuv3_overflow_interrupt" />
<testcase name="Test Secure interrupt can preempt Realm EL1"
function="host_realm_sec_interrupt_can_preempt_rl" />
<testcase name="Check that FPU state registers context is preserved in RL/SE/NS"
function="host_realm_fpu_access_in_rl_ns_se" />
<!-- Test case related to SVE support and SIMD state -->
<testcase name="Check RMI reports proper SVE VL"
function="host_check_rmi_reports_proper_sve_vl" />
<testcase name="Create SVE Realm with invalid VL"
function="host_sve_realm_test_invalid_vl" />
<testcase name="Create SVE Realm and test ID registers"
function="host_sve_realm_cmd_id_registers" />
<testcase name="Create non SVE Realm and test ID registers"
function="host_non_sve_realm_cmd_id_registers" />
<testcase name="Create SVE Realm and check rdvl result"
function="host_sve_realm_cmd_rdvl" />
<testcase name="Create SVE Realm and probe all supported VLs"
function="host_sve_realm_cmd_probe_vl" />
<testcase name="Check whether RMM preserves NS ZCR_EL2 register"
function="host_sve_realm_check_config_register" />
<testcase name="Intermittently switch to Realm while doing NS SVE ops"
function="host_sve_realm_check_vectors_operations" />
<testcase name="Check if RMM does not leak Realm SVE vector registers"
function="host_sve_realm_check_vectors_leaked" />
<testcase name="Check if Realm gets undefined abort if it access SVE"
function="host_non_sve_realm_check_undef_abort" />
<testcase name="Check various SIMD state preserved across NS/RL switch"
function="host_and_realm_check_simd" />
<!-- Test Realm for SME -->
<testcase name="Create Realm and test SME ID registers"
function="host_realm_check_sme_id_registers" />
<testcase name="Check if Realm gets undefined abort when it access SME"
function="host_realm_check_sme_undef_abort" />
<testcase name="Check whether RMM preserves NS SME configurations"
function="host_realm_check_sme_configs" />
<testcase name="Intermittently switch to Realm while NS doing SSVE ops"
function="host_sve_realm_check_streaming_vectors_operations" />
<!-- Test case related to PAuth -->
<testcase name="Check if PAuth keys are preserved in RL/SE/NS"
function="host_realm_enable_pauth" />
<testcase name="Generate PAuth Fault by overwriting LR"
function="host_realm_pauth_fault" />
</testsuite>
</testsuites>