diff options
author | TudorCretu <tudor.cretu@arm.com> | 2019-08-02 14:58:10 +0100 |
---|---|---|
committer | TudorCretu <tudor.cretu@arm.com> | 2019-08-14 13:27:17 +0100 |
commit | 519ed86207edef10b67621d108321357960da421 (patch) | |
tree | abb9e8f5583355f67b43823f9d8021912bc429ed | |
parent | 326f397d8453c31a1d57e2ef4d25cada97c57ec7 (diff) | |
download | trusted-firmware-m-519ed86207edef10b67621d108321357960da421.tar.gz |
Core: Adds the missing drivers initialisations on MUSCA_B1 platform
This patch adds a fix to properly initialise the SRAM MPC, APB PPC1, and
APB PPCEXP0 drivers driver during MUSCA_B target configuration.
Change-Id: I4c9b227d488769c8cbd95eaddbf93ce45e80150c
Signed-off-by: Tudor Cretu <tudor.cretu@arm.com>
-rw-r--r-- | platform/ext/target/musca_b1/spm_hal.c | 4 | ||||
-rw-r--r-- | platform/ext/target/musca_b1/target_cfg.c | 38 |
2 files changed, 40 insertions, 2 deletions
diff --git a/platform/ext/target/musca_b1/spm_hal.c b/platform/ext/target/musca_b1/spm_hal.c index 47b9dc3dc7..4ed6c309e0 100644 --- a/platform/ext/target/musca_b1/spm_hal.c +++ b/platform/ext/target/musca_b1/spm_hal.c @@ -18,6 +18,7 @@ #include "secure_utilities.h" /* Import MPC driver */ +extern ARM_DRIVER_MPC Driver_EFLASH0_MPC; extern ARM_DRIVER_MPC Driver_CODE_SRAM_MPC; /* Get address of memory regions to configure MPU */ @@ -182,7 +183,8 @@ enum tfm_plat_err_t tfm_spm_hal_setup_isolation_hw(void) void MPC_Handler(void) { - /* Clear MPC interrupt flag and pending MPC IRQ */ + /* Clear MPC interrupt flags and pending MPC IRQ */ + Driver_EFLASH0_MPC.ClearInterrupt(); Driver_CODE_SRAM_MPC.ClearInterrupt(); NVIC_ClearPendingIRQ(S_MPC_COMBINED_IRQn); diff --git a/platform/ext/target/musca_b1/target_cfg.c b/platform/ext/target/musca_b1/target_cfg.c index 9edbb67559..a0bc2adb84 100644 --- a/platform/ext/target/musca_b1/target_cfg.c +++ b/platform/ext/target/musca_b1/target_cfg.c @@ -244,7 +244,11 @@ enum tfm_plat_err_t nvic_interrupt_enable(void) */ Driver_APB_PPC0.ClearInterrupt(); - /* Enable PPC interrupts for APB PPC */ + /* Enable PPC interrupts */ + ret = Driver_AHB_PPCEXP0.EnableInterrupt(); + if (ret != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } ret = Driver_APB_PPC0.EnableInterrupt(); if (ret != ARM_DRIVER_OK) { return TFM_PLAT_ERR_SYSTEM_ERR; @@ -345,6 +349,14 @@ int32_t mpc_init_cfg(void) } #endif /* BL2 */ + /* SRAM MPC device needs to be initialialized so that the interrupt can be + * enabled later. The default (secure only) config is used. + */ + ret = Driver_CODE_SRAM_MPC.Initialize(); + if (ret != ARM_DRIVER_OK) { + return ret; + } + ret = mpc_data_region0->Initialize(); if (ret != ARM_DRIVER_OK) { return ret; @@ -429,6 +441,14 @@ int32_t ppc_init_cfg(void) struct spctrl_def* spctrl = CMSDK_SPCTRL; int32_t ret = ARM_DRIVER_OK; + /* No peripherals are configured on AHB PPCEXP0, but device needs to be + * initialialized so that the interrupt can be enabled later. + */ + ret = Driver_AHB_PPCEXP0.Initialize(); + if (ret != ARM_DRIVER_OK) { + return ret; + } + /* Grant non-secure access to peripherals in the APB PPC0 * (timer0 and 1, dualtimer, mhu 0 and 1) */ @@ -467,6 +487,22 @@ int32_t ppc_init_cfg(void) return ret; } + /* No peripherals are configured on APB PPC1, but device needs to be + * initialialized so that the interrupt can be enabled later. + */ + ret = Driver_APB_PPC1.Initialize(); + if (ret != ARM_DRIVER_OK) { + return ret; + } + + /* No peripherals are configured on APB PPC EXP0, but device needs to be + * initialialized so that the interrupt can be enabled later. + */ + ret = Driver_APB_PPCEXP0.Initialize(); + if (ret != ARM_DRIVER_OK) { + return ret; + } + /* Grant non-secure access for APB peripherals on EXP1 */ ret = Driver_APB_PPCEXP1.Initialize(); if (ret != ARM_DRIVER_OK) { |