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authorAndrei Narkevitch <ainh@cypress.com>2019-10-25 09:25:58 -0700
committerChris Brand <chris.brand@cypress.com>2019-11-14 16:15:13 -0800
commitb8d0f8e69ea70269572b2951f110b4d18d8a0163 (patch)
treef5b9fb287468f5f2a06550bb2532a0713ed03870
parent1d8ae2d3376b068059707ce3474654ca351fb5af (diff)
downloadtrusted-firmware-m-b8d0f8e69ea70269572b2951f110b4d18d8a0163.tar.gz
plat: Clone psoc64_1m build as psoc64
This is in preparation for adding support for PSoC64 2MB board. Note: copying entire directory "as is", thus creating many duplicating files, with an intention to create a better platform tree separation with common code support later. Signed-off-by: Andrei Narkevitch <ainh@cypress.com> Change-Id: Ib10f39fa253192e8c8de89315ee306d5d9b1c947
-rw-r--r--configs/ConfigCoreIPC.cmake2
-rw-r--r--configs/ConfigCoreIPCTfmLevel2.cmake2
-rw-r--r--configs/ConfigPsaApiTestIPC.cmake2
-rw-r--r--configs/ConfigPsaApiTestIPCTfmLevel2.cmake2
-rw-r--r--configs/ConfigRegressionIPC.cmake2
-rw-r--r--configs/ConfigRegressionIPCTfmLevel2.cmake2
-rw-r--r--docs/user_guides/tfm_build_instruction.rst6
-rw-r--r--platform/ext/psoc64.cmake259
-rw-r--r--platform/ext/target/psoc64/CMSIS_Driver/Config/RTE_Device.h627
-rw-r--r--platform/ext/target/psoc64/CMSIS_Driver/Config/cmsis_driver_config.h26
-rw-r--r--platform/ext/target/psoc64/CMSIS_Driver/Driver_Flash.c318
-rw-r--r--platform/ext/target/psoc64/CMSIS_Driver/Driver_USART.c504
-rw-r--r--platform/ext/target/psoc64/Device/Config/device_cfg.h30
-rw-r--r--platform/ext/target/psoc64/Device/Include/cmsis.h28
-rw-r--r--platform/ext/target/psoc64/Device/Include/cy8c6247bzi_d54.h1255
-rw-r--r--platform/ext/target/psoc64/Device/Include/cy_device_headers.h246
-rw-r--r--platform/ext/target/psoc64/Device/Include/cyb06447bzi_d54.h1255
-rw-r--r--platform/ext/target/psoc64/Device/Include/device_definition.h53
-rw-r--r--platform/ext/target/psoc64/Device/Include/gpio_psoc6_01_124_bga.h2542
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_backup.h234
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_ble.h2255
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_canfd.h953
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_cpuss.h356
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_cpuss_v2.h447
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_crypto.h384
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_crypto_v2.h463
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_csd.h486
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_ctbm.h296
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_ctdac.h114
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_dmac_v2.h243
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_dw.h180
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_dw_v2.h225
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_efuse.h327
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_efuse_data_psoc6_01.h114
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_efuse_data_psoc6_02.h250
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_efuse_data_psoc6_03.h250
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_fault.h122
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_fault_v2.h122
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_flashc.h603
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_flashc_v2.h718
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_gpio.h477
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_gpio_v2.h478
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_headers.h44
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_hsiom.h97
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_hsiom_v2.h119
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_i2s.h289
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_ipc.h132
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_ipc_v2.h136
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_lcd.h101
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_lcd_v2.h103
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_lpcomp.h180
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_pass.h139
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_pdm.h170
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_peri.h491
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_peri_ms_v2.h785
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_peri_v2.h254
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_profile.h114
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_prot.h388
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_prot_v2.h388
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_sar.h636
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_scb.h755
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_sdhc.h858
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_sflash.h509
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_smartio.h118
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_smartio_v2.h118
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_smif.h387
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_srss.h625
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_tcpwm.h200
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_udb.h2035
-rw-r--r--platform/ext/target/psoc64/Device/Include/ip/cyip_usbfs.h1779
-rw-r--r--platform/ext/target/psoc64/Device/Include/platform_base_address.h55
-rw-r--r--platform/ext/target/psoc64/Device/Include/platform_description.h25
-rw-r--r--platform/ext/target/psoc64/Device/Include/platform_pins.h25
-rw-r--r--platform/ext/target/psoc64/Device/Include/platform_regs.h23
-rw-r--r--platform/ext/target/psoc64/Device/Include/psoc6_01_config.h3097
-rw-r--r--platform/ext/target/psoc64/Device/Include/system_psoc6.h665
-rw-r--r--platform/ext/target/psoc64/Device/Source/armclang/cy_syslib_mdk.s109
-rw-r--r--platform/ext/target/psoc64/Device/Source/armclang/psoc6_bl2.sct49
-rw-r--r--platform/ext/target/psoc64/Device/Source/armclang/psoc6_ns.sct53
-rw-r--r--platform/ext/target/psoc64/Device/Source/armclang/startup_psoc6_bl2.s169
-rw-r--r--platform/ext/target/psoc64/Device/Source/armclang/startup_psoc6_ns.s643
-rw-r--r--platform/ext/target/psoc64/Device/Source/armclang/startup_psoc6_s.s177
-rw-r--r--platform/ext/target/psoc64/Device/Source/device_definition.c63
-rw-r--r--platform/ext/target/psoc64/Device/Source/gcc/cy_syslib_gcc.S150
-rw-r--r--platform/ext/target/psoc64/Device/Source/gcc/psoc6_bl2.ld396
-rw-r--r--platform/ext/target/psoc64/Device/Source/gcc/psoc6_ns.ld421
-rw-r--r--platform/ext/target/psoc64/Device/Source/gcc/startup_psoc6_bl2.S385
-rw-r--r--platform/ext/target/psoc64/Device/Source/gcc/startup_psoc6_ns.S616
-rw-r--r--platform/ext/target/psoc64/Device/Source/gcc/startup_psoc6_s.S387
-rw-r--r--platform/ext/target/psoc64/Device/Source/system_psoc6_cm0plus.c751
-rw-r--r--platform/ext/target/psoc64/Device/Source/system_psoc6_cm4.c587
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg.c34
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg.h48
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_clocks.c53
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_clocks.h55
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_dmas.c179
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_dmas.h67
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_notices.h30
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_peripherals.c204
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_peripherals.h140
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_pins.c883
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_pins.h571
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_platform.c557
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_platform.h53
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_routing.c51
-rw-r--r--platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_routing.h89
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_csd.h863
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_device.h1262
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_dma.h2015
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_flash.h504
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_gpio.h1973
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_ipc_drv.h1002
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_ipc_pipe.h291
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_ipc_sema.h141
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_mcwdt.h1122
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_prot.h1200
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_prot.h.rej116
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_rtc.h1329
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_scb_common.h1983
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_scb_ezi2c.h555
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_scb_uart.h1526
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_smif.h1621
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_sysclk.h3239
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_sysint.h594
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_syslib.h1165
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_syspm.h2861
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_systick.h313
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_tcpwm.h712
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_tcpwm_pwm.h633
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_trigmux.h314
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_usbfs_dev_drv.h2414
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_usbfs_dev_drv_reg.h1536
-rw-r--r--platform/ext/target/psoc64/Native_Driver/include/cy_wdt.h450
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_device.c381
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_flash.c1569
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_gpio.c363
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_ipc_drv.c181
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_ipc_pipe.c608
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_ipc_sema.c445
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_prot.c2812
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_scb_common.c427
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_scb_uart.c1435
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_sysclk.c1976
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_sysint.c376
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_syslib.c567
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_syspm.c3222
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_systick.c256
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_trigmux.c381
-rw-r--r--platform/ext/target/psoc64/Native_Driver/source/cy_wdt.c215
-rw-r--r--platform/ext/target/psoc64/attest_hal.c36
-rw-r--r--platform/ext/target/psoc64/cypress_psoc_6_spec.rst332
-rw-r--r--platform/ext/target/psoc64/driver_dap.c77
-rw-r--r--platform/ext/target/psoc64/driver_dap.h47
-rw-r--r--platform/ext/target/psoc64/driver_ppu.c611
-rw-r--r--platform/ext/target/psoc64/driver_ppu.h435
-rw-r--r--platform/ext/target/psoc64/driver_smpu.c208
-rw-r--r--platform/ext/target/psoc64/driver_smpu.h90
-rw-r--r--platform/ext/target/psoc64/dummy_boot_seed.c53
-rw-r--r--platform/ext/target/psoc64/dummy_crypto_keys.c148
-rw-r--r--platform/ext/target/psoc64/dummy_device_id.c108
-rw-r--r--platform/ext/target/psoc64/dummy_nv_counters.c194
-rw-r--r--platform/ext/target/psoc64/mailbox/mailbox_ipc_intr.c47
-rw-r--r--platform/ext/target/psoc64/mailbox/ns_ipc_config.h19
-rw-r--r--platform/ext/target/psoc64/mailbox/platform_multicore.c131
-rw-r--r--platform/ext/target/psoc64/mailbox/platform_multicore.h100
-rw-r--r--platform/ext/target/psoc64/mailbox/platform_ns_mailbox.c121
-rw-r--r--platform/ext/target/psoc64/mailbox/platform_spe_mailbox.c102
-rw-r--r--platform/ext/target/psoc64/mailbox/spe_ipc_config.h24
-rw-r--r--platform/ext/target/psoc64/partition/flash_layout.h225
-rw-r--r--platform/ext/target/psoc64/partition/region_defs.h208
-rw-r--r--platform/ext/target/psoc64/pc_config.h43
-rw-r--r--platform/ext/target/psoc64/ppu_config.h389
-rw-r--r--platform/ext/target/psoc64/security/keys/readme.rst4
-rw-r--r--platform/ext/target/psoc64/security/policy_dual_stage_CM0p_CM4.json175
-rwxr-xr-xplatform/ext/target/psoc64/security/sign.py48
-rw-r--r--platform/ext/target/psoc64/smpu_config.h204
-rw-r--r--platform/ext/target/psoc64/spm_hal.c435
-rw-r--r--platform/ext/target/psoc64/target_cfg.c762
-rw-r--r--platform/ext/target/psoc64/target_cfg.h85
-rw-r--r--platform/ext/target/psoc64/tfm_peripherals_def.h20
-rw-r--r--platform/ext/target/psoc64/tfm_platform_system.c30
181 files changed, 93527 insertions, 0 deletions
diff --git a/configs/ConfigCoreIPC.cmake b/configs/ConfigCoreIPC.cmake
index 662512325d..59ec12fda5 100644
--- a/configs/ConfigCoreIPC.cmake
+++ b/configs/ConfigCoreIPC.cmake
@@ -31,6 +31,8 @@ elseif(${TARGET_PLATFORM} STREQUAL "ref_twincpu_host")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/ref_twincpu_host.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "psoc62")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc62.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "psoc64")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "psoc64_1m")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64_1m.cmake")
else()
diff --git a/configs/ConfigCoreIPCTfmLevel2.cmake b/configs/ConfigCoreIPCTfmLevel2.cmake
index 8904177f41..6be25e9623 100644
--- a/configs/ConfigCoreIPCTfmLevel2.cmake
+++ b/configs/ConfigCoreIPCTfmLevel2.cmake
@@ -27,6 +27,8 @@ elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_B1")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_b1.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "psoc62")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc62.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "psoc64")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "psoc64_1m")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64_1m.cmake")
else()
diff --git a/configs/ConfigPsaApiTestIPC.cmake b/configs/ConfigPsaApiTestIPC.cmake
index 30fc54e16f..a5f663a8ab 100644
--- a/configs/ConfigPsaApiTestIPC.cmake
+++ b/configs/ConfigPsaApiTestIPC.cmake
@@ -27,6 +27,8 @@ elseif(${TARGET_PLATFORM} STREQUAL "AN524")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps3AN524.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "psoc62")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc62.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "psoc64")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "psoc64_1m")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64_1m.cmake")
else()
diff --git a/configs/ConfigPsaApiTestIPCTfmLevel2.cmake b/configs/ConfigPsaApiTestIPCTfmLevel2.cmake
index ae08764c75..cedcd07f4c 100644
--- a/configs/ConfigPsaApiTestIPCTfmLevel2.cmake
+++ b/configs/ConfigPsaApiTestIPCTfmLevel2.cmake
@@ -23,6 +23,8 @@ elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_B1")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_b1.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "psoc62")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc62.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "psoc64")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "psoc64_1m")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64_1m.cmake")
else()
diff --git a/configs/ConfigRegressionIPC.cmake b/configs/ConfigRegressionIPC.cmake
index 16bf1c9195..dd546b0b38 100644
--- a/configs/ConfigRegressionIPC.cmake
+++ b/configs/ConfigRegressionIPC.cmake
@@ -27,6 +27,8 @@ elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_B1")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_b1.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "psoc62")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc62.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "psoc64")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "psoc64_1m")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64_1m.cmake")
else()
diff --git a/configs/ConfigRegressionIPCTfmLevel2.cmake b/configs/ConfigRegressionIPCTfmLevel2.cmake
index b1e1e07ff2..8b0533306d 100644
--- a/configs/ConfigRegressionIPCTfmLevel2.cmake
+++ b/configs/ConfigRegressionIPCTfmLevel2.cmake
@@ -27,6 +27,8 @@ elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_B1")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_b1.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "psoc62")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc62.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "psoc64")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "psoc64_1m")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64_1m.cmake")
else()
diff --git a/docs/user_guides/tfm_build_instruction.rst b/docs/user_guides/tfm_build_instruction.rst
index e6fd3c14d7..1d465b3422 100644
--- a/docs/user_guides/tfm_build_instruction.rst
+++ b/docs/user_guides/tfm_build_instruction.rst
@@ -39,6 +39,10 @@ line arguments:
refer to target platform name in
:doc:`Cypress PSoC 6 platform specifics
</platform/ext/target/psoc62/cypress_psoc_6_spec>`.
+ - Cypress PSoC 64 platforms
+ refer to target platform name in
+ :doc:`Cypress PSoC 6 platform specifics
+ </platform/ext/target/psoc64/cypress_psoc_6_spec>`.
- Cypress PSoC 64 1MB platform
refer to target platform name in
:doc:`Cypress PSoC 6 platform specifics
@@ -119,6 +123,8 @@ Build steps for Cypress PSoC 6 platform:
========================================
Please see build steps in :doc:`Cypress PSoC 62 platform specifics
</platform/ext/target/psoc62/cypress_psoc_6_spec>` or
+:doc:`Cypress PSoC 64 platform specifics
+</platform/ext/target/psoc64/cypress_psoc_6_spec>` or
:doc:`Cypress PSoC 64 1MB platform specifics
</platform/ext/target/psoc64_1m/cypress_psoc_6_spec>`.
diff --git a/platform/ext/psoc64.cmake b/platform/ext/psoc64.cmake
new file mode 100644
index 0000000000..4b28217d04
--- /dev/null
+++ b/platform/ext/psoc64.cmake
@@ -0,0 +1,259 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+# Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+#This file gathers all Cypress PSoC 6 specific files in the application.
+
+include("Common/MultiCore")
+
+# Select configuration of multi-core topology
+enable_multi_core_topology_config()
+
+set(TFM_NS_CLIENT_IDENTIFICATION OFF)
+
+add_definitions(-DCYB06447BZI_D54=1)
+
+add_definitions(-DNDEBUG=1)
+add_definitions(-DTFM_CORE_DEBUG)
+
+# Skip Core Test temporarily
+set(CORE_TEST OFF)
+# Skip peripheral access test
+set(TFM_ENABLE_PERIPH_ACCESS_TEST OFF)
+
+# Set Cortex-M0plus as secure core
+set_secure_cpu_type("CpuM0p")
+# Set Cortex-M4 as non-secure core
+set_ns_cpu_type("CpuM4")
+
+# Set PSoC62 specific secure definitions
+add_platform_secure_definitions(CY_PSOC6_CM0P=1)
+
+set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR})
+
+#Specify the location of platform specific build dependencies.
+if(COMPILER STREQUAL "ARMCLANG")
+ set (BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/psoc64/Device/Source/armclang/psoc6_bl2.sct")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/armclang/tfm_common_s.sct")
+ set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/psoc64/Device/Source/armclang/psoc6_ns.sct")
+ if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib")
+ endif()
+elseif(COMPILER STREQUAL "GNUARM")
+ set (BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/psoc64/Device/Source/gcc/psoc6_bl2.ld")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/gcc/tfm_common_s.ld")
+ set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/psoc64/Device/Source/gcc/psoc6_ns.ld")
+ if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ # [libRTX_CM3.a should be used for CM4 without FPU]
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a")
+ endif()
+else()
+ message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
+endif()
+set (FLASH_LAYOUT "${PLATFORM_DIR}/target/psoc64/partition/flash_layout.h")
+set (PLATFORM_LINK_INCLUDES "${PLATFORM_DIR}/target/psoc64/partition")
+
+if (BL2)
+ set (BL2_LINKER_CONFIG ${BL2_SCATTER_FILE_NAME})
+
+ # Turn off hardware key feature to work around the issue that booting is
+ # stuck in mbed-crypto RSA operations. Wait for further debugging.
+ set (MCUBOOT_HW_KEY OFF)
+
+ #FixMe: MCUBOOT_SIGN_RSA_LEN can be removed when ROTPK won't be hard coded in platform/ext/common/tfm_rotpk.c
+ # instead independently loaded from secure code as a blob.
+ if (${MCUBOOT_SIGNATURE_TYPE} STREQUAL "RSA-2048")
+ add_definitions(-DMCUBOOT_SIGN_RSA_LEN=2048)
+ endif()
+ if (${MCUBOOT_SIGNATURE_TYPE} STREQUAL "RSA-3072")
+ add_definitions(-DMCUBOOT_SIGN_RSA_LEN=3072)
+ endif()
+endif()
+
+embedded_include_directories(PATH "${PLATFORM_DIR}/cmsis" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/psoc64" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/psoc64/CMSIS_Driver/Config" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/psoc64/Device/Config" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/psoc64/Device/Include" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/psoc64/Native_Driver/include" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/psoc64/Native_Driver/generated_source" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/psoc64/mailbox" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/psoc64/partition" ABSOLUTE)
+embedded_include_directories(PATH "${TFM_ROOT_DIR}/interface/include" ABSOLUTE)
+embedded_include_directories(PATH "${TFM_ROOT_DIR}/platform/include" ABSOLUTE)
+embedded_include_directories(PATH "${TFM_ROOT_DIR}/secure_fw/core/arch/include" ABSOLUTE)
+embedded_include_directories(PATH "${TFM_ROOT_DIR}/secure_fw/core/ipc/include" ABSOLUTE)
+
+#Gather all source files we need.
+list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/mailbox/platform_multicore.c")
+list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/psoc64/mailbox/mailbox_ipc_intr.c")
+list(APPEND ALL_SRC_C_NS "${PLATFORM_DIR}/target/psoc64/mailbox/platform_ns_mailbox.c")
+list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/psoc64/mailbox/mailbox_ipc_intr.c")
+list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/psoc64/mailbox/platform_spe_mailbox.c")
+
+install(FILES ${PLATFORM_DIR}/target/psoc64/mailbox/ns_ipc_config.h
+ ${PLATFORM_DIR}/target/psoc64/mailbox/platform_multicore.h
+ DESTINATION export/tfm/inc)
+
+install(FILES ${PLATFORM_DIR}/target/psoc64/mailbox/platform_multicore.c
+ ${PLATFORM_DIR}/target/psoc64/mailbox/platform_ns_mailbox.c
+ DESTINATION export/tfm/src)
+
+if (NOT DEFINED BUILD_CMSIS_CORE)
+ message(FATAL_ERROR "Configuration variable BUILD_CMSIS_CORE (true|false) is undefined!")
+elseif(BUILD_CMSIS_CORE)
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/psoc64/Device/Source/system_psoc6_cm0plus.c")
+ list(APPEND ALL_SRC_C_NS "${PLATFORM_DIR}/target/psoc64/Device/Source/system_psoc6_cm4.c")
+ list(APPEND ALL_SRC_C_BL2 "${PLATFORM_DIR}/target/psoc64/Device/Source/system_psoc6_cm0plus.c")
+endif()
+
+if (NOT DEFINED BUILD_RETARGET)
+ message(FATAL_ERROR "Configuration variable BUILD_RETARGET (true|false) is undefined!")
+elseif(BUILD_RETARGET)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Device/Source/device_definition.c")
+endif()
+
+if (NOT DEFINED BUILD_UART_STDOUT)
+ message(FATAL_ERROR "Configuration variable BUILD_UART_STDOUT (true|false) is undefined!")
+elseif(BUILD_UART_STDOUT)
+ if (NOT DEFINED SECURE_UART1)
+ message(FATAL_ERROR "Configuration variable SECURE_UART1 (true|false) is undefined!")
+ elseif(SECURE_UART1)
+ message(FATAL_ERROR "Configuration SECURE_UART1 TRUE is invalid for this target!")
+ endif()
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/common/uart_stdout.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/common" ABSOLUTE)
+ set(BUILD_NATIVE_DRIVERS true)
+ set(BUILD_CMSIS_DRIVERS true)
+endif()
+
+if (NOT DEFINED BUILD_NATIVE_DRIVERS)
+ message(FATAL_ERROR "Configuration variable BUILD_NATIVE_DRIVERS (true|false) is undefined!")
+elseif(BUILD_NATIVE_DRIVERS)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_device.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_flash.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_gpio.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_prot.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_ipc_drv.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_ipc_pipe.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_ipc_sema.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_scb_common.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_scb_uart.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_sysclk.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_sysint.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_syslib.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_syspm.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_systick.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_trigmux.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/source/cy_wdt.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/generated_source/cycfg.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/generated_source/cycfg_clocks.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/generated_source/cycfg_dmas.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/generated_source/cycfg_peripherals.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/generated_source/cycfg_pins.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/generated_source/cycfg_platform.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/Native_Driver/generated_source/cycfg_routing.c")
+ if(CMAKE_C_COMPILER_ID STREQUAL "ARMCLANG")
+ list(APPEND ALL_SRC_ASM "${PLATFORM_DIR}/target/psoc64/Device/Source/armclang/cy_syslib_mdk.s")
+ elseif(CMAKE_C_COMPILER_ID STREQUAL "GNUARM")
+ list(APPEND ALL_SRC_ASM "${PLATFORM_DIR}/target/psoc64/Device/Source/gcc/cy_syslib_gcc.S")
+ else()
+ message(FATAL_ERROR "No cy_syslib is available for compiler '${CMAKE_C_COMPILER_ID}'.")
+ endif()
+endif()
+
+if (NOT DEFINED BUILD_TIME)
+ message(FATAL_ERROR "Configuration variable BUILD_TIME (true|false) is undefined!")
+elseif(BUILD_TIME)
+endif()
+
+if (NOT DEFINED BUILD_STARTUP)
+ message(FATAL_ERROR "Configuration variable BUILD_STARTUP (true|false) is undefined!")
+elseif(BUILD_STARTUP)
+ if(CMAKE_C_COMPILER_ID STREQUAL "ARMCLANG")
+ list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/psoc64/Device/Source/armclang/startup_psoc6_s.s")
+ list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/psoc64/Device/Source/armclang/startup_psoc6_ns.s")
+ list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/psoc64/Device/Source/armclang/startup_psoc6_bl2.s")
+ elseif(CMAKE_C_COMPILER_ID STREQUAL "GNUARM")
+ list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/psoc64/Device/Source/gcc/startup_psoc6_s.S")
+ list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/psoc64/Device/Source/gcc/startup_psoc6_ns.S")
+ list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/psoc64/Device/Source/gcc/startup_psoc6_bl2.S")
+ set_property(SOURCE "${ALL_SRC_ASM_S}" "${ALL_SRC_ASM_NS}" "${ALL_SRC_ASM_BL2}" APPEND
+ PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
+ else()
+ message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
+ endif()
+endif()
+
+if (NOT DEFINED BUILD_TARGET_CFG)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_CFG (true|false) is undefined!")
+elseif(BUILD_TARGET_CFG)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/target_cfg.c")
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/psoc64/spm_hal.c")
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/psoc64/attest_hal.c")
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/psoc64/tfm_platform_system.c")
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/common/tfm_platform.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/common" ABSOLUTE)
+endif()
+
+if (NOT DEFINED BUILD_TARGET_HARDWARE_KEYS)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_HARDWARE_KEYS (true|false) is undefined!")
+elseif(BUILD_TARGET_HARDWARE_KEYS)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/common/tfm_initial_attestation_key_material.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/common/tfm_rotpk.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/dummy_crypto_keys.c")
+endif()
+
+if (NOT DEFINED BUILD_TARGET_NV_COUNTERS)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_NV_COUNTERS (true|false) is undefined!")
+elseif(BUILD_TARGET_NV_COUNTERS)
+ # NOTE: This non-volatile counters implementation is a dummy
+ # implementation. Platform vendors have to implement the
+ # API ONLY if the target has non-volatile counters.
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/dummy_nv_counters.c")
+ set(TARGET_NV_COUNTERS_ENABLE ON)
+ # Sets SST_ROLLBACK_PROTECTION flag to compile in the SST services
+ # rollback protection code as the target supports nv counters.
+ set (SST_ROLLBACK_PROTECTION ON)
+endif()
+
+if (NOT DEFINED BUILD_CMSIS_DRIVERS)
+ message(FATAL_ERROR "Configuration variable BUILD_CMSIS_DRIVERS (true|false) is undefined!")
+elseif(BUILD_CMSIS_DRIVERS)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/driver_smpu.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/driver_ppu.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/driver_dap.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/CMSIS_Driver/Driver_USART.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/target/psoc64/CMSIS_Driver" ABSOLUTE)
+ embedded_include_directories(PATH "${PLATFORM_DIR}/driver" ABSOLUTE)
+endif()
+
+if (NOT DEFINED BUILD_FLASH)
+ message(FATAL_ERROR "Configuration variable BUILD_FLASH (true|false) is undefined!")
+elseif(BUILD_FLASH)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/CMSIS_Driver/Driver_Flash.c")
+ # As the SST area is going to be in RAM, it is required to set SST_CREATE_FLASH_LAYOUT
+ # to be sure the SST service knows that when it starts the SST area does not contain any
+ # valid SST flash layout and it needs to create one.
+ set(SST_CREATE_FLASH_LAYOUT ON)
+ embedded_include_directories(PATH "${PLATFORM_DIR}/target/psoc64/CMSIS_Driver" ABSOLUTE)
+ embedded_include_directories(PATH "${PLATFORM_DIR}/driver" ABSOLUTE)
+endif()
+
+if (NOT DEFINED BUILD_BOOT_SEED)
+ message(FATAL_ERROR "Configuration variable BUILD_BOOT_SEED (true|false) is undefined!")
+elseif(BUILD_BOOT_SEED)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/dummy_boot_seed.c")
+endif()
+
+if (NOT DEFINED BUILD_DEVICE_ID)
+ message(FATAL_ERROR "Configuration variable BUILD_DEVICE_ID (true|false) is undefined!")
+elseif(BUILD_DEVICE_ID)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/psoc64/dummy_device_id.c")
+endif()
diff --git a/platform/ext/target/psoc64/CMSIS_Driver/Config/RTE_Device.h b/platform/ext/target/psoc64/CMSIS_Driver/Config/RTE_Device.h
new file mode 100644
index 0000000000..0e33998389
--- /dev/null
+++ b/platform/ext/target/psoc64/CMSIS_Driver/Config/RTE_Device.h
@@ -0,0 +1,627 @@
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H__
+#define __RTE_DEVICE_H__
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU0]
+// <i> Configuration settings for Driver_SMPU0 in component ::Drivers:MPC
+#define RTE_SMPU0 1
+// </e> MPC (Memory Protection Controller) [Driver_SMPU0]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU1]
+// <i> Configuration settings for Driver_SMPU1 in component ::Drivers:MPC
+#define RTE_SMPU1 1
+// </e> MPC (Memory Protection Controller) [Driver_SMPU1]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU2]
+// <i> Configuration settings for Driver_SMPU2 in component ::Drivers:MPC
+#define RTE_SMPU2 1
+// </e> MPC (Memory Protection Controller) [Driver_SMPU2]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU3]
+// <i> Configuration settings for Driver_SMPU3 in component ::Drivers:MPC
+#define RTE_SMPU3 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU3]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU4]
+// <i> Configuration settings for Driver_SMPU4 in component ::Drivers:MPC
+#define RTE_SMPU4 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU4]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU5]
+// <i> Configuration settings for Driver_SMPU5 in component ::Drivers:MPC
+#define RTE_SMPU5 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU5]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU6]
+// <i> Configuration settings for Driver_SMPU6 in component ::Drivers:MPC
+#define RTE_SMPU6 1
+// </e> MPC (Memory Protection Controller) [Driver_SMPU6]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU7]
+// <i> Configuration settings for Driver_SMPU7 in component ::Drivers:MPC
+#define RTE_SMPU7 1
+// </e> MPC (Memory Protection Controller) [Driver_SMPU7]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU8]
+// <i> Configuration settings for Driver_SMPU8 in component ::Drivers:MPC
+#define RTE_SMPU8 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU8]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU9]
+// <i> Configuration settings for Driver_SMPU9 in component ::Drivers:MPC
+#define RTE_SMPU9 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU9]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU10]
+// <i> Configuration settings for Driver_SMPU10 in component ::Drivers:MPC
+#define RTE_SMPU10 1
+// </e> MPC (Memory Protection Controller) [Driver_SMPU10]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU11]
+// <i> Configuration settings for Driver_SMPU11 in component ::Drivers:MPC
+#define RTE_SMPU11 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU11]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU12]
+// <i> Configuration settings for Driver_SMPU12 in component ::Drivers:MPC
+#define RTE_SMPU12 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU12]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU13]
+// <i> Configuration settings for Driver_SMPU13 in component ::Drivers:MPC
+#define RTE_SMPU13 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU13]
+
+/* SMPUs 14 and 15 are used by flashboot */
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
+#define RTE_USART0 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
+#define RTE_USART1 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART2]
+// <i> Configuration settings for Driver_USART2 in component ::Drivers:USART
+#define RTE_USART2 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART2]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART3]
+// <i> Configuration settings for Driver_USART3 in component ::Drivers:USART
+#define RTE_USART3 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART3]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART4]
+// <i> Configuration settings for Driver_USART4 in component ::Drivers:USART
+#define RTE_USART4 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART4]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART5]
+// <i> Configuration settings for Driver_USART5 in component ::Drivers:USART
+#define RTE_USART5 1
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART5]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART6]
+// <i> Configuration settings for Driver_USART6 in component ::Drivers:USART
+#define RTE_USART6 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART6]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART7]
+// <i> Configuration settings for Driver_USART7 in component ::Drivers:USART
+#define RTE_USART7 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART7]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PR0]
+// <i> Configuration settings for Driver_PPU_PR0 in component ::Drivers:PPC
+#define RTE_PPU_PR0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PR0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PR1]
+// <i> Configuration settings for Driver_PPU_PR1 in component ::Drivers:PPC
+#define RTE_PPU_PR1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PR1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PR2]
+// <i> Configuration settings for Driver_PPU_PR2 in component ::Drivers:PPC
+#define RTE_PPU_PR2 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PR2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PR3]
+// <i> Configuration settings for Driver_PPU_PR3 in component ::Drivers:PPC
+#define RTE_PPU_PR3 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PR3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PR4]
+// <i> Configuration settings for Driver_PPU_PR4 in component ::Drivers:PPC
+#define RTE_PPU_PR4 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PR4]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PR5]
+// <i> Configuration settings for Driver_PPU_PR5 in component ::Drivers:PPC
+#define RTE_PPU_PR5 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PR5]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PR6]
+// <i> Configuration settings for Driver_PPU_PR6 in component ::Drivers:PPC
+#define RTE_PPU_PR6 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PR6]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PR7]
+// <i> Configuration settings for Driver_PPU_PR7 in component ::Drivers:PPC
+#define RTE_PPU_PR7 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PR7]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PR8]
+// <i> Configuration settings for Driver_PPU_PR8 in component ::Drivers:PPC
+#define RTE_PPU_PR8 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PR8]
+
+/* PROG PPUs 9-15 are used by flashboot */
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR0]
+// <i> Configuration settings for Driver_PPU_GR0 in component ::Drivers:PPC
+#define RTE_PPU_GR0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR1]
+// <i> Configuration settings for Driver_PPU_GR1 in component ::Drivers:PPC
+#define RTE_PPU_GR1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR2]
+// <i> Configuration settings for Driver_PPU_GR2 in component ::Drivers:PPC
+#define RTE_PPU_GR2 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR3]
+// <i> Configuration settings for Driver_PPU_GR3 in component ::Drivers:PPC
+#define RTE_PPU_GR3 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR4]
+// <i> Configuration settings for Driver_PPU_GR4 in component ::Drivers:PPC
+#define RTE_PPU_GR4 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR4]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR6]
+// <i> Configuration settings for Driver_PPU_GR6 in component ::Drivers:PPC
+#define RTE_PPU_GR6 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR6]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR9]
+// <i> Configuration settings for Driver_PPU_GR9 in component ::Drivers:PPC
+#define RTE_PPU_GR9 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR9]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR10]
+// <i> Configuration settings for Driver_PPU_GR10 in component ::Drivers:PPC
+#define RTE_PPU_GR10 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR10]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO0]
+// <i> Configuration settings for Driver_PPU_GR_MMIO0 in component ::Drivers:PPC
+#define RTE_PPU_GR_MMIO0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO1]
+// <i> Configuration settings for Driver_PPU_GR_MMIO1 in component ::Drivers:PPC
+#define RTE_PPU_GR_MMIO1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO2]
+// <i> Configuration settings for Driver_PPU_GR_MMIO2 in component ::Drivers:PPC
+#define RTE_PPU_GR_MMIO2 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO3]
+// <i> Configuration settings for Driver_PPU_GR_MMIO3 in component ::Drivers:PPC
+#define RTE_PPU_GR_MMIO3 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO4]
+// <i> Configuration settings for Driver_PPU_GR_MMIO4 in component ::Drivers:PPC
+#define RTE_PPU_GR_MMIO4 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO4]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO6]
+// <i> Configuration settings for Driver_PPU_GR_MMIO6 in component ::Drivers:PPC
+#define RTE_PPU_GR_MMIO6 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO6]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO9]
+// <i> Configuration settings for Driver_PPU_GR_MMIO9 in component ::Drivers:PPC
+#define RTE_PPU_GR_MMIO9 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO9]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO10]
+// <i> Configuration settings for Driver_PPU_GR_MMIO10 in component ::Drivers:PPC
+#define RTE_PPU_GR_MMIO10 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GR_MMIO10]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR1]
+// <i> Configuration settings for Driver_GR_PPU_SL_PERI_GR1 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_PERI_GR1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_CRYPTO]
+// <i> Configuration settings for Driver_GR_PPU_SL_CRYPTO in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_CRYPTO 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_CRYPTO]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR2]
+// <i> Configuration settings for Driver_GR_PPU_SL_PERI_GR2 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_PERI_GR2 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_CPUSS]
+// <i> Configuration settings for Driver_GR_PPU_SL_CPUSS in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_CPUSS 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_CPUSS]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_FAULT]
+// <i> Configuration settings for Driver_GR_PPU_SL_FAULT in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_FAULT 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_FAULT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_IPC]
+// <i> Configuration settings for Driver_GR_PPU_SL_IPC in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_IPC 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PROT]
+// <i> Configuration settings for Driver_GR_PPU_SL_PROT in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_PROT 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PROT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_FLASHC]
+// <i> Configuration settings for Driver_GR_PPU_SL_FLASHC in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_FLASHC 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_FLASHC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SRSS]
+// <i> Configuration settings for Driver_GR_PPU_SL_SRSS in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_SRSS 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SRSS]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_BACKUP]
+// <i> Configuration settings for Driver_GR_PPU_SL_BACKUP in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_BACKUP 0
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_BACKUP]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_DW0]
+// <i> Configuration settings for Driver_GR_PPU_SL_DW0 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_DW0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_DW0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_DW1]
+// <i> Configuration settings for Driver_GR_PPU_SL_DW1 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_DW1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_DW1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_EFUSE]
+// <i> Configuration settings for Driver_GR_PPU_SL_EFUSE in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_EFUSE 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_EFUSE]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PROFILE]
+// <i> Configuration settings for Driver_GR_PPU_SL_PROFILE in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_PROFILE 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PROFILE]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT0]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_STRUCT0 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_STRUCT0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT1]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_STRUCT1 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_STRUCT1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT2]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_STRUCT2 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_STRUCT2 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT3]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_STRUCT3 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_STRUCT3 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT4]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_STRUCT4 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_STRUCT4 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT4]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT5]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_STRUCT5 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_STRUCT5 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT5]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT6]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_STRUCT6 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_STRUCT6 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT6]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT7]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_STRUCT7 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_STRUCT7 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_STRUCT7]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT0]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_INTR_STRUCT0 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_INTR_STRUCT0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT1]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_INTR_STRUCT1 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_INTR_STRUCT1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT2]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_INTR_STRUCT2 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_INTR_STRUCT2 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT3]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_INTR_STRUCT3 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_INTR_STRUCT3 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT4]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_INTR_STRUCT4 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_INTR_STRUCT4 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT4]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT5]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_INTR_STRUCT5 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_INTR_STRUCT5 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT5]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT6]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_INTR_STRUCT6 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_INTR_STRUCT6 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT6]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT7]
+// <i> Configuration settings for Driver_GR_PPU_RG_IPC_INTR_STRUCT7 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_IPC_INTR_STRUCT7 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_IPC_INTR_STRUCT7]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW0_DW_CH_STRUCT0]
+// <i> Configuration settings for Driver_GR_PPU_RG_DW0_DW_CH_STRUCT0 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_DW0_DW_CH_STRUCT0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW0_DW_CH_STRUCT0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW0_DW_CH_STRUCT1]
+// <i> Configuration settings for Driver_GR_PPU_RG_DW0_DW_CH_STRUCT1 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_DW0_DW_CH_STRUCT1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW0_DW_CH_STRUCT1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW0_DW_CH_STRUCT2]
+// <i> Configuration settings for Driver_GR_PPU_RG_DW0_DW_CH_STRUCT2 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_DW0_DW_CH_STRUCT2 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW0_DW_CH_STRUCT2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW0_DW_CH_STRUCT3]
+// <i> Configuration settings for Driver_GR_PPU_RG_DW0_DW_CH_STRUCT3 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_DW0_DW_CH_STRUCT3 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW0_DW_CH_STRUCT3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW1_DW_CH_STRUCT0]
+// <i> Configuration settings for Driver_GR_PPU_RG_DW1_DW_CH_STRUCT0 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_DW1_DW_CH_STRUCT0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW1_DW_CH_STRUCT0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW1_DW_CH_STRUCT1]
+// <i> Configuration settings for Driver_GR_PPU_RG_DW1_DW_CH_STRUCT1 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_DW1_DW_CH_STRUCT1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW1_DW_CH_STRUCT1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW1_DW_CH_STRUCT2]
+// <i> Configuration settings for Driver_GR_PPU_RG_DW1_DW_CH_STRUCT2 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_DW1_DW_CH_STRUCT2 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW1_DW_CH_STRUCT2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW1_DW_CH_STRUCT3]
+// <i> Configuration settings for Driver_GR_PPU_RG_DW1_DW_CH_STRUCT3 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_DW1_DW_CH_STRUCT3 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_DW1_DW_CH_STRUCT3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_SMPU]
+// <i> Configuration settings for Driver_GR_PPU_RG_SMPU in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_SMPU 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_SMPU]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_MPU_CP0P]
+// <i> Configuration settings for Driver_GR_PPU_RG_MPU_CP0P in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_MPU_CP0P 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_MPU_CP0P]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_MPU_CRYPTO]
+// <i> Configuration settings for Driver_GR_PPU_RG_MPU_CRYPTO in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_MPU_CRYPTO 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_MPU_CRYPTO]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_MPU_CM4]
+// <i> Configuration settings for Driver_GR_PPU_RG_MPU_CM4 in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_MPU_CM4 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_MPU_CM4]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_MPU_TC]
+// <i> Configuration settings for Driver_GR_PPU_RG_MPU_TC in component ::Drivers:PPC
+#define RTE_GR_PPU_RG_MPU_TC 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_RG_MPU_TC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR3]
+// <i> Configuration settings for Driver_GR_PPU_SL_PERI_GR3 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_PERI_GR3 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_HSIOM]
+// <i> Configuration settings for Driver_GR_PPU_SL_HSIOM in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_HSIOM 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_HSIOM]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_GPIO]
+// <i> Configuration settings for Driver_GR_PPU_SL_GPIO in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_GPIO 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_GPIO]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SMARTIO]
+// <i> Configuration settings for Driver_GR_PPU_SL_SMARTIO in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_SMARTIO 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SMARTIO]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_UDB]
+// <i> Configuration settings for Driver_GR_PPU_SL_UDB in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_UDB 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_UDB]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_LPCOMP]
+// <i> Configuration settings for Driver_GR_PPU_SL_LPCOMP in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_LPCOMP 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_LPCOMP]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_CSD]
+// <i> Configuration settings for Driver_GR_PPU_SL_CSD in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_CSD 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_CSD]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_TCPWM0]
+// <i> Configuration settings for Driver_GR_PPU_SL_TCPWM0 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_TCPWM0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_TCPWM0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_TCPWM1]
+// <i> Configuration settings for Driver_GR_PPU_SL_TCPWM1 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_TCPWM1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_TCPWM1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_LCD]
+// <i> Configuration settings for Driver_GR_PPU_SL_LCD in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_LCD 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_LCD]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_BLE]
+// <i> Configuration settings for Driver_GR_PPU_SL_BLE in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_BLE 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_BLE]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_USBFS]
+// <i> Configuration settings for Driver_GR_PPU_SL_USBFS in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_USBFS 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_USBFS]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR4]
+// <i> Configuration settings for Driver_GR_PPU_SL_PERI_GR4 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_PERI_GR4 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR4]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SMIF]
+// <i> Configuration settings for Driver_GR_PPU_SL_SMIF in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_SMIF 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SMIF]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR6]
+// <i> Configuration settings for Driver_GR_PPU_SL_PERI_GR6 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_PERI_GR6 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR6]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB0]
+// <i> Configuration settings for Driver_GR_PPU_SL_SCB0 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_SCB0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB1]
+// <i> Configuration settings for Driver_GR_PPU_SL_SCB1 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_SCB1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB2]
+// <i> Configuration settings for Driver_GR_PPU_SL_SCB2 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_SCB2 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB3]
+// <i> Configuration settings for Driver_GR_PPU_SL_SCB3 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_SCB3 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB4]
+// <i> Configuration settings for Driver_GR_PPU_SL_SCB4 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_SCB4 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB4]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB5]
+// <i> Configuration settings for Driver_GR_PPU_SL_SCB5 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_SCB5 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB5]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB6]
+// <i> Configuration settings for Driver_GR_PPU_SL_SCB6 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_SCB6 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB6]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB7]
+// <i> Configuration settings for Driver_GR_PPU_SL_SCB7 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_SCB7 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB7]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB8]
+// <i> Configuration settings for Driver_GR_PPU_SL_SCB8 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_SCB8 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_SCB8]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR9]
+// <i> Configuration settings for Driver_GR_PPU_SL_PERI_GR9 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_PERI_GR9 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR9]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PASS]
+// <i> Configuration settings for Driver_GR_PPU_SL_PASS in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_PASS 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PASS]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR10]
+// <i> Configuration settings for Driver_GR_PPU_SL_PERI_GR10 in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_PERI_GR10 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PERI_GR10]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_I2S]
+// <i> Configuration settings for Driver_GR_PPU_SL_I2S in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_I2S 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_I2S]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PDM]
+// <i> Configuration settings for Driver_GR_PPU_SL_PDM in component ::Drivers:PPC
+#define RTE_GR_PPU_SL_PDM 1
+// </e> PPC (Peripheral Protection Controller) [Driver_GR_PPU_SL_PDM]
+
+// <e> FLASH (Flash Memory) [Driver_FLASH0]
+// <i> Configuration settings for Driver_FLASH0 in component ::Drivers:FLASH
+#define RTE_FLASH0 1
+// </e> FLASH (Flash Memory) [Driver_FLASH0]
+
+#endif /* __RTE_DEVICE_H__ */
diff --git a/platform/ext/target/psoc64/CMSIS_Driver/Config/cmsis_driver_config.h b/platform/ext/target/psoc64/CMSIS_Driver/Config/cmsis_driver_config.h
new file mode 100644
index 0000000000..7cb5bae886
--- /dev/null
+++ b/platform/ext/target/psoc64/CMSIS_Driver/Config/cmsis_driver_config.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_DRIVER_CONFIG_H__
+#define __CMSIS_DRIVER_CONFIG_H__
+
+#include "device_cfg.h"
+#include "device_definition.h"
+#include "platform_description.h"
+#include "RTE_Device.h"
+#include "target_cfg.h"
+
+#endif /* __CMSIS_DRIVER_CONFIG_H__ */
diff --git a/platform/ext/target/psoc64/CMSIS_Driver/Driver_Flash.c b/platform/ext/target/psoc64/CMSIS_Driver/Driver_Flash.c
new file mode 100644
index 0000000000..89dedee28f
--- /dev/null
+++ b/platform/ext/target/psoc64/CMSIS_Driver/Driver_Flash.c
@@ -0,0 +1,318 @@
+/*
+ * Copyright (c) 2013-2019 ARM Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* This is a modified copy of the ref_twincpu version at
+ * platform/ext/target/ref_twincpu/CMSIS_Driver/Driver_Flash.c
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <stdio.h>
+#include "Driver_Flash.h"
+#include "RTE_Device.h"
+#include "flash_layout.h"
+#include "region_defs.h"
+
+#include "cycfg.h"
+#include "cy_device.h"
+#include "cy_flash.h"
+
+#ifndef ARG_UNUSED
+#define ARG_UNUSED(arg) ((void)arg)
+#endif
+
+/* Driver version */
+#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 1)
+#define ARM_FLASH_DRV_ERASE_VALUE 0xFF
+
+#define FLASH0_BASE CY_FLASH_BASE // User Flash start address for both CM0+ & CM4
+#define FLASH0_SIZE CY_FLASH_SIZE // 1 MB
+#define FLASH0_SECTOR_SIZE CY_FLASH_SIZEOF_ROW // 512 B
+#define FLASH0_PAGE_SIZE CY_FLASH_SIZEOF_ROW // 512 B
+
+struct arm_flash_dev_t {
+ const uint32_t memory_base; /*!< FLASH memory base address */
+ ARM_FLASH_INFO *data; /*!< FLASH data */
+};
+
+/* Flash Status */
+static ARM_FLASH_STATUS FlashStatus = {0, 0, 0};
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_FLASH_API_VERSION,
+ ARM_FLASH_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_FLASH_CAPABILITIES DriverCapabilities = {
+ 0, /* event_ready */
+ 0, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */
+ 1 /* erase_chip */
+};
+
+
+#if (RTE_FLASH0)
+
+static ARM_FLASH_INFO ARM_FLASH0_DEV_DATA = {
+ .sector_info = NULL, /* Uniform sector layout */
+ .sector_count = FLASH0_SIZE / FLASH0_SECTOR_SIZE,
+ .sector_size = FLASH0_SECTOR_SIZE,
+ .page_size = FLASH0_PAGE_SIZE,
+ .program_unit = SST_FLASH_PROGRAM_UNIT,
+ .erased_value = ARM_FLASH_DRV_ERASE_VALUE
+};
+
+static struct arm_flash_dev_t ARM_FLASH0_DEV = {
+ .memory_base = FLASH0_BASE,
+ .data = &(ARM_FLASH0_DEV_DATA)
+};
+
+struct arm_flash_dev_t *FLASH0_DEV = &ARM_FLASH0_DEV;
+
+/*
+ * Functions
+ */
+
+static ARM_DRIVER_VERSION ARM_Flash_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void)
+{
+ return DriverCapabilities;
+}
+
+static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event)
+{
+ ARG_UNUSED(cb_event);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state)
+{
+ switch (state) {
+ case ARM_POWER_FULL:
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+ break;
+
+ case ARM_POWER_OFF:
+ case ARM_POWER_LOW:
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+}
+
+static int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt)
+{
+ if ( (data == NULL) || (cnt == 0) ) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ // Wraparound check (before adding FLASH0_DEV->memory_base + addr)
+ if (FLASH0_DEV->memory_base >= UINT32_MAX - addr) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ uint32_t start_addr = FLASH0_DEV->memory_base + addr;
+
+ if (start_addr >= FLASH0_DEV->memory_base + FLASH0_SIZE) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ // Wraparound check (before adding start_addr + cnt)
+ if (start_addr >= UINT32_MAX - cnt) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ if ( (start_addr + cnt < FLASH0_DEV->memory_base) ||
+ (start_addr + cnt > FLASH0_DEV->memory_base + FLASH0_SIZE)
+ ) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ // Using memcpy for reading
+ memcpy(data, (void *)start_addr, cnt);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data,
+ uint32_t cnt)
+{
+ static uint8_t prog_buf[CY_FLASH_SIZEOF_ROW];
+ uint8_t *data_ptr = (uint8_t *) data;
+ uint32_t address = FLASH0_DEV->memory_base + addr;
+ cy_en_flashdrv_status_t cy_status = CY_FLASH_DRV_ERR_UNC;
+
+ // Address checks can be omitted here as they are done by Cypress API
+
+ if ( (data == NULL) || (cnt == 0) ) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ // Make sure cnt argument is aligned to program_unit size
+ if (cnt % FLASH0_DEV->data->program_unit) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ // Wraparound check (before adding FLASH0_DEV->memory_base + addr)
+ if (FLASH0_DEV->memory_base >= UINT32_MAX - addr) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ while (cnt)
+ {
+ uint32_t offset = address % CY_FLASH_SIZEOF_ROW;
+ uint32_t chunk_size;
+ if (offset + cnt > CY_FLASH_SIZEOF_ROW) {
+ chunk_size = CY_FLASH_SIZEOF_ROW - offset;
+ } else {
+ chunk_size = cnt;
+ }
+ uint32_t row_address = address / CY_FLASH_SIZEOF_ROW * CY_FLASH_SIZEOF_ROW;
+ memcpy(prog_buf, (const void *)row_address, CY_FLASH_SIZEOF_ROW);
+ memcpy(prog_buf + offset, data_ptr, chunk_size);
+
+ cy_status = Cy_Flash_ProgramRow(row_address, (const uint32_t *)prog_buf);
+ if (cy_status != CY_FLASH_DRV_SUCCESS) {
+ break;
+ }
+ data_ptr += chunk_size;
+ address += chunk_size;
+ cnt -= chunk_size;
+ }
+
+ switch (cy_status)
+ {
+ case CY_FLASH_DRV_SUCCESS:
+ return ARM_DRIVER_OK;
+
+ case CY_FLASH_DRV_IPC_BUSY:
+ return ARM_DRIVER_ERROR_BUSY;
+
+ case CY_FLASH_DRV_INVALID_INPUT_PARAMETERS:
+ return ARM_DRIVER_ERROR_PARAMETER;
+
+ default:
+ return ARM_DRIVER_ERROR;
+ }
+}
+
+static int32_t ARM_Flash_EraseSector(uint32_t addr)
+{
+ // Wraparound check (before adding FLASH0_DEV->memory_base + addr)
+ if (FLASH0_DEV->memory_base >= UINT32_MAX - addr) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ uint32_t start_addr = FLASH0_DEV->memory_base + addr;
+
+ // Address checks can be omitted here as they are done by Cypress API
+
+ cy_en_flashdrv_status_t cy_status = Cy_Flash_EraseRow(start_addr);
+
+ switch (cy_status)
+ {
+ case CY_FLASH_DRV_SUCCESS:
+ return ARM_DRIVER_OK;
+
+ case CY_FLASH_DRV_IPC_BUSY:
+ return ARM_DRIVER_ERROR_BUSY;
+
+ case CY_FLASH_DRV_INVALID_INPUT_PARAMETERS:
+ return ARM_DRIVER_ERROR_PARAMETER;
+
+ default:
+ return ARM_DRIVER_ERROR;
+ }
+}
+
+static int32_t ARM_Flash_EraseChip(void)
+{
+ uint32_t addr = FLASH0_DEV->memory_base;
+
+ cy_en_flashdrv_status_t cy_status = CY_FLASH_DRV_ERR_UNC;
+
+
+ if (DriverCapabilities.erase_chip != 1) {
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ for (uint32_t i = 0; i < FLASH0_DEV->data->sector_count; i++) {
+
+ cy_status = Cy_Flash_EraseRow(addr);
+
+ if (cy_status != CY_FLASH_DRV_SUCCESS) {
+ break;
+ }
+
+ addr += FLASH0_DEV->data->sector_size;
+ }
+
+ switch (cy_status)
+ {
+ case CY_FLASH_DRV_SUCCESS:
+ return ARM_DRIVER_OK;
+
+ case CY_FLASH_DRV_IPC_BUSY:
+ return ARM_DRIVER_ERROR_BUSY;
+
+ case CY_FLASH_DRV_INVALID_INPUT_PARAMETERS:
+ return ARM_DRIVER_ERROR_PARAMETER;
+
+ default:
+ return ARM_DRIVER_ERROR;
+ }
+}
+
+static ARM_FLASH_STATUS ARM_Flash_GetStatus(void)
+{
+ return FlashStatus;
+}
+
+static ARM_FLASH_INFO * ARM_Flash_GetInfo(void)
+{
+ return FLASH0_DEV->data;
+}
+
+ARM_DRIVER_FLASH Driver_FLASH0 = {
+ ARM_Flash_GetVersion,
+ ARM_Flash_GetCapabilities,
+ ARM_Flash_Initialize,
+ ARM_Flash_Uninitialize,
+ ARM_Flash_PowerControl,
+ ARM_Flash_ReadData,
+ ARM_Flash_ProgramData,
+ ARM_Flash_EraseSector,
+ ARM_Flash_EraseChip,
+ ARM_Flash_GetStatus,
+ ARM_Flash_GetInfo
+};
+
+#endif /* RTE_FLASH0 */
diff --git a/platform/ext/target/psoc64/CMSIS_Driver/Driver_USART.c b/platform/ext/target/psoc64/CMSIS_Driver/Driver_USART.c
new file mode 100644
index 0000000000..9443f88959
--- /dev/null
+++ b/platform/ext/target/psoc64/CMSIS_Driver/Driver_USART.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* This is a modified copy of the ref_twincpu version at
+ * platform/ext/target/ref_twincpu/CMSIS_Driver/Driver_USART.c
+ */
+
+#include "Driver_USART.h"
+
+#include "cmsis.h"
+#include "cmsis_driver_config.h"
+#include "RTE_Device.h"
+
+#include "cycfg.h"
+#include "cy_device.h"
+#include "cy_scb_uart.h"
+
+#ifndef ARG_UNUSED
+#define ARG_UNUSED(arg) (void)arg
+#endif
+
+/* Driver version */
+#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_USART_API_VERSION,
+ ARM_USART_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_USART_CAPABILITIES DriverCapabilities = {
+ 1, /* supports UART (Asynchronous) mode */
+ 0, /* supports Synchronous Master mode */
+ 0, /* supports Synchronous Slave mode */
+ 0, /* supports UART Single-wire mode */
+ 0, /* supports UART IrDA mode */
+ 0, /* supports UART Smart Card mode */
+ 0, /* Smart Card Clock generator available */
+ 0, /* RTS Flow Control available */
+ 0, /* CTS Flow Control available */
+ 0, /* Transmit completed event: \ref ARM_USARTx_EVENT_TX_COMPLETE */
+ 0, /* Signal receive character timeout event: \ref ARM_USARTx_EVENT_RX_TIMEOUT */
+ 0, /* RTS Line: 0=not available, 1=available */
+ 0, /* CTS Line: 0=not available, 1=available */
+ 0, /* DTR Line: 0=not available, 1=available */
+ 0, /* DSR Line: 0=not available, 1=available */
+ 0, /* DCD Line: 0=not available, 1=available */
+ 0, /* RI Line: 0=not available, 1=available */
+ 0, /* Signal CTS change event: \ref ARM_USARTx_EVENT_CTS */
+ 0, /* Signal DSR change event: \ref ARM_USARTx_EVENT_DSR */
+ 0, /* Signal DCD change event: \ref ARM_USARTx_EVENT_DCD */
+ 0, /* Signal RI change event: \ref ARM_USARTx_EVENT_RI */
+ 0 /* Reserved */
+};
+
+static ARM_DRIVER_VERSION ARM_USART_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void)
+{
+ return DriverCapabilities;
+}
+
+typedef struct {
+ CySCB_Type* base; /* UART device structure */
+ uint32_t tx_nbr_bytes; /* Number of bytes transfered */
+ uint32_t rx_nbr_bytes; /* Number of bytes recevied */
+ ARM_USART_SignalEvent_t cb_event; /* Callback function for events */
+} UARTx_Resources;
+
+static int32_t USARTx_convert_retval(cy_en_scb_uart_status_t val)
+{
+ switch (val) {
+ case CY_SCB_UART_SUCCESS:
+ return ARM_DRIVER_OK;
+ case CY_SCB_UART_BAD_PARAM:
+ return ARM_DRIVER_ERROR_PARAMETER;
+ case CY_SCB_UART_RECEIVE_BUSY:
+ case CY_SCB_UART_TRANSMIT_BUSY:
+ return ARM_DRIVER_ERROR_BUSY;
+ }
+}
+
+static int32_t ARM_USARTx_Initialize(UARTx_Resources* uart_dev)
+{
+ cy_en_scb_uart_status_t retval;
+
+#ifdef CY_SYSTEM_CPU_CM0P
+ cy_stc_scb_uart_config_t config = KITPROG_UART_config;
+
+ /* Assign and configure pins, assign clock divider */
+ retval = Cy_SCB_UART_Init(uart_dev->base, &config, NULL);
+
+ if (retval == CY_SCB_UART_SUCCESS)
+ Cy_SCB_UART_Enable(uart_dev->base);
+#else
+ // all hw initializations is done on the cm0p side
+ retval = CY_SCB_UART_SUCCESS;
+
+#endif
+ return USARTx_convert_retval(retval);
+}
+
+static uint32_t ARM_USARTx_Uninitialize(UARTx_Resources* uart_dev)
+{
+ Cy_SCB_UART_Disable(uart_dev->base, NULL);
+
+ Cy_SCB_UART_DeInit(uart_dev->base);
+
+ return ARM_DRIVER_OK;
+}
+
+
+static int32_t ARM_USARTx_PowerControl(UARTx_Resources* uart_dev,
+ ARM_POWER_STATE state)
+{
+ ARG_UNUSED(uart_dev);
+
+ switch (state) {
+ case ARM_POWER_OFF:
+ case ARM_POWER_LOW:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ case ARM_POWER_FULL:
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all the enumeration values are
+ * covered in the switch.*/
+ }
+}
+
+static int32_t ARM_USARTx_Send(UARTx_Resources* uart_dev, const void *data,
+ uint32_t num)
+{
+ void *p_data = (void *)data;
+
+ if ((data == NULL) || (num == 0U)) {
+ /* Invalid parameters */
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ Cy_SCB_UART_PutArrayBlocking(uart_dev->base, p_data, num);
+
+ while (!Cy_SCB_UART_IsTxComplete(uart_dev->base))
+ ;
+
+ uart_dev->tx_nbr_bytes = num;
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USARTx_Receive(UARTx_Resources* uart_dev,
+ void *data, uint32_t num)
+{
+ if ((data == NULL) || (num == 0U)) {
+ // Invalid parameters
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ Cy_SCB_UART_GetArrayBlocking(uart_dev->base, data, num);
+
+ uart_dev->rx_nbr_bytes = num;
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USARTx_Transfer(UARTx_Resources* uart_dev,
+ const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(uart_dev);
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USARTx_GetTxCount(UARTx_Resources* uart_dev)
+{
+ return uart_dev->tx_nbr_bytes;
+}
+
+static uint32_t ARM_USARTx_GetRxCount(UARTx_Resources* uart_dev)
+{
+ return uart_dev->rx_nbr_bytes;
+}
+
+static uint32_t USARTx_SetDataBits(uint32_t control,
+ cy_stc_scb_uart_config_t *config)
+{
+ switch (control & ARM_USART_DATA_BITS_Msk) {
+ case ARM_USART_DATA_BITS_5:
+ config->dataWidth = 5;
+ break;
+
+ case ARM_USART_DATA_BITS_6:
+ config->dataWidth = 6;
+ break;
+
+ case ARM_USART_DATA_BITS_7:
+ config->dataWidth = 7;
+ break;
+
+ case ARM_USART_DATA_BITS_8:
+ config->dataWidth = 8;
+ break;
+
+ case ARM_USART_DATA_BITS_9:
+ config->dataWidth = 9;
+ break;
+
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t USARTx_SetParity(uint32_t control,
+ cy_stc_scb_uart_config_t *config)
+{
+ switch (control & ARM_USART_PARITY_Msk) {
+ case ARM_USART_PARITY_NONE:
+ config->parity = CY_SCB_UART_PARITY_NONE;
+ break;
+
+ case ARM_USART_PARITY_EVEN:
+ config->parity = CY_SCB_UART_PARITY_EVEN;
+ break;
+
+ case ARM_USART_PARITY_ODD:
+ config->parity = CY_SCB_UART_PARITY_ODD;
+ break;
+
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t USARTx_SetStopBits(uint32_t control,
+ cy_stc_scb_uart_config_t *config)
+{
+ switch (control & ARM_USART_STOP_BITS_Msk) {
+ case ARM_USART_STOP_BITS_1:
+ config->stopBits = CY_SCB_UART_STOP_BITS_1;
+ break;
+
+ case ARM_USART_STOP_BITS_2:
+ config->stopBits = CY_SCB_UART_STOP_BITS_2;
+ break;
+
+ case ARM_USART_STOP_BITS_1_5:
+ config->stopBits = CY_SCB_UART_STOP_BITS_1_5;
+ break;
+
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void USARTx_SetFlowControl(uint32_t control,
+ cy_stc_scb_uart_config_t *config)
+{
+ /* First, deal with CTS */
+ switch (control & ARM_USART_FLOW_CONTROL_Msk) {
+ case ARM_USART_FLOW_CONTROL_NONE:
+ case ARM_USART_FLOW_CONTROL_RTS:
+ config->enableCts = false;
+ config->ctsPolarity = CY_SCB_UART_ACTIVE_LOW;
+ break;
+
+ case ARM_USART_FLOW_CONTROL_CTS:
+ case ARM_USART_FLOW_CONTROL_RTS_CTS:
+ config->enableCts = true;
+ config->ctsPolarity = CY_SCB_UART_ACTIVE_LOW;
+ break;
+ }
+
+ /* Then RTS */
+ switch (control & ARM_USART_FLOW_CONTROL_Msk) {
+ case ARM_USART_FLOW_CONTROL_NONE:
+ case ARM_USART_FLOW_CONTROL_CTS:
+ config->rtsRxFifoLevel = 0;
+ config->rtsPolarity = CY_SCB_UART_ACTIVE_LOW;
+ break;
+
+ case ARM_USART_FLOW_CONTROL_RTS:
+ case ARM_USART_FLOW_CONTROL_RTS_CTS:
+ config->rtsRxFifoLevel = 8; /* TODO What's a sensible value ? */
+ config->rtsPolarity = CY_SCB_UART_ACTIVE_LOW;
+ break;
+ }
+}
+
+static int32_t ARM_USARTx_Control(UARTx_Resources* uart_dev, uint32_t control,
+ uint32_t arg)
+{
+ cy_stc_scb_uart_config_t config = KITPROG_UART_config;
+ cy_en_scb_uart_status_t cy_retval;
+ uint32_t retval;
+
+ Cy_SCB_UART_Disable(uart_dev->base, NULL);
+
+ Cy_SCB_UART_DeInit(uart_dev->base);
+
+ switch (control & ARM_USART_CONTROL_Msk) {
+ case ARM_USART_MODE_ASYNCHRONOUS:
+ /* TODO Default values work for 115200 baud,
+ * but we should set config.oversample to
+ * a value derived from the divider
+ */
+ break;
+ /* Unsupported command */
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ /* UART Data bits */
+ retval = USARTx_SetDataBits(control, &config);
+ if (retval != ARM_DRIVER_OK)
+ return retval;
+
+ /* UART Parity */
+ retval = USARTx_SetParity(control, &config);
+ if (retval != ARM_DRIVER_OK)
+ return retval;
+
+ /* USART Stop bits */
+ retval = USARTx_SetStopBits(control, &config);
+ if (retval != ARM_DRIVER_OK)
+ return retval;
+
+ /* USART Flow Control */
+ USARTx_SetFlowControl(control, &config);
+
+ cy_retval = Cy_SCB_UART_Init(uart_dev->base, &config, NULL);
+
+ if (retval == CY_SCB_UART_SUCCESS)
+ Cy_SCB_UART_Enable(uart_dev->base);
+
+ return USARTx_convert_retval(cy_retval);
+}
+
+static ARM_USART_STATUS ARM_USARTx_GetStatus(UARTx_Resources* uart_dev)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USARTx_SetModemControl(UARTx_Resources* uart_dev,
+ ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USARTx_GetModemStatus(UARTx_Resources* uart_dev)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+/* Per-UART macros */
+#define DEFINE_UARTX(N) static UARTx_Resources USART##N##_DEV = { \
+ .base = SCB##N, \
+ .tx_nbr_bytes = 0, \
+ .rx_nbr_bytes = 0, \
+ .cb_event = NULL, \
+}; \
+\
+static int32_t ARM_USART##N##_Initialize(ARM_USART_SignalEvent_t cb_event) \
+{ \
+ USART##N##_DEV.cb_event = cb_event; \
+ return ARM_USARTx_Initialize(&USART##N##_DEV); \
+} \
+\
+static int32_t ARM_USART##N##_Uninitialize(void) \
+{ \
+ return ARM_USARTx_Uninitialize(&USART##N##_DEV); \
+} \
+\
+static int32_t ARM_USART##N##_PowerControl(ARM_POWER_STATE state) \
+{ \
+ return ARM_USARTx_PowerControl(&USART##N##_DEV, state); \
+} \
+ \
+static int32_t ARM_USART##N##_Send(const void *data, uint32_t num) \
+{ \
+ return ARM_USARTx_Send(&USART##N##_DEV, data, num); \
+} \
+ \
+static int32_t ARM_USART##N##_Receive(void *data, uint32_t num) \
+{ \
+ return ARM_USARTx_Receive(&USART##N##_DEV, data, num); \
+} \
+ \
+static int32_t ARM_USART##N##_Transfer(const void *data_out, void *data_in, \
+ uint32_t num) \
+{ \
+ return ARM_USARTx_Transfer(&USART##N##_DEV, data_out, data_in, num); \
+} \
+ \
+static uint32_t ARM_USART##N##_GetTxCount(void) \
+{ \
+ return ARM_USARTx_GetTxCount(&USART##N##_DEV); \
+} \
+ \
+static uint32_t ARM_USART##N##_GetRxCount(void) \
+{ \
+ return ARM_USARTx_GetRxCount(&USART##N##_DEV); \
+} \
+static int32_t ARM_USART##N##_Control(uint32_t control, uint32_t arg) \
+{ \
+ return ARM_USARTx_Control(&USART##N##_DEV, control, arg); \
+} \
+ \
+static ARM_USART_STATUS ARM_USART##N##_GetStatus(void) \
+{ \
+ return ARM_USARTx_GetStatus(&USART##N##_DEV); \
+} \
+ \
+static int32_t ARM_USART##N##_SetModemControl(ARM_USART_MODEM_CONTROL control) \
+{ \
+ return ARM_USARTx_SetModemControl(&USART##N##_DEV, control); \
+} \
+ \
+static ARM_USART_MODEM_STATUS ARM_USART##N##_GetModemStatus(void) \
+{ \
+ return ARM_USARTx_GetModemStatus(&USART##N##_DEV); \
+} \
+ \
+extern ARM_DRIVER_USART Driver_USART##N; \
+ARM_DRIVER_USART Driver_USART##N = { \
+ ARM_USART_GetVersion, \
+ ARM_USART_GetCapabilities, \
+ ARM_USART##N##_Initialize, \
+ ARM_USART##N##_Uninitialize, \
+ ARM_USART##N##_PowerControl, \
+ ARM_USART##N##_Send, \
+ ARM_USART##N##_Receive, \
+ ARM_USART##N##_Transfer, \
+ ARM_USART##N##_GetTxCount, \
+ ARM_USART##N##_GetRxCount, \
+ ARM_USART##N##_Control, \
+ ARM_USART##N##_GetStatus, \
+ ARM_USART##N##_SetModemControl, \
+ ARM_USART##N##_GetModemStatus \
+};
+
+#if (RTE_USART0)
+DEFINE_UARTX(0)
+#endif
+
+#if (RTE_USART1)
+DEFINE_UARTX(1)
+#endif
+
+#if (RTE_USART2)
+DEFINE_UARTX(2)
+#endif
+
+#if (RTE_USART3)
+DEFINE_UARTX(3)
+#endif
+
+#if (RTE_USART4)
+DEFINE_UARTX(4)
+#endif
+
+#if (RTE_USART5)
+DEFINE_UARTX(5)
+#endif
+
+#if (RTE_USART6)
+DEFINE_UARTX(6)
+#endif
+
+#if (RTE_USART7)
+DEFINE_UARTX(7)
+#endif
diff --git a/platform/ext/target/psoc64/Device/Config/device_cfg.h b/platform/ext/target/psoc64/Device/Config/device_cfg.h
new file mode 100644
index 0000000000..682684af15
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Config/device_cfg.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2017-2018 Arm Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_DEVICE_CFG_H__
+#define __ARM_LTD_DEVICE_CFG_H__
+
+/**
+ * \file device_cfg.h
+ * \brief Configuration file native driver re-targeting
+ *
+ * \details This file can be used to add native driver specific macro
+ * definitions to select which peripherals are available in the build.
+ *
+ * This is a default device configuration file with all peripherals enabled.
+ */
+
+#endif /* __ARM_LTD_DEVICE_CFG_H__ */
diff --git a/platform/ext/target/psoc64/Device/Include/cmsis.h b/platform/ext/target/psoc64/Device/Include/cmsis.h
new file mode 100644
index 0000000000..5c28355d7b
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/cmsis.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_H__
+#define __CMSIS_H__
+
+/* CMSIS wrapper for PSoC 6 board */
+
+#include "cmsis_compiler.h"
+#include "system_psoc6.h"
+#include "cy_device_headers.h"
+#include "platform_regs.h" /* Platform registers */
+#include "platform_base_address.h" /* Peripherals base addresses */
+
+#endif /*__CMSIS_H__ */
diff --git a/platform/ext/target/psoc64/Device/Include/cy8c6247bzi_d54.h b/platform/ext/target/psoc64/Device/Include/cy8c6247bzi_d54.h
new file mode 100644
index 0000000000..12b1ca9d1e
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/cy8c6247bzi_d54.h
@@ -0,0 +1,1255 @@
+/***************************************************************************//**
+* \file cy8c6247bzi_d54.h
+*
+* \brief
+* CY8C6247BZI-D54 device header
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CY8C6247BZI_D54_H_
+#define _CY8C6247BZI_D54_H_
+
+/**
+* \addtogroup group_device CY8C6247BZI-D54
+* \{
+*/
+
+/**
+* \addtogroup Configuration_of_CMSIS
+* \{
+*/
+
+/*******************************************************************************
+* Interrupt Number Definition
+*******************************************************************************/
+
+typedef enum {
+#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+ (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
+ (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
+ /* ARM Cortex-M0+ Core Interrupt Numbers */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ /* ARM Cortex-M0+ NVIC Mux inputs. Allow routing of device interrupts to the CM0+ NVIC */
+ NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CM0+ NVIC Mux input 0 */
+ NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CM0+ NVIC Mux input 1 */
+ NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CM0+ NVIC Mux input 2 */
+ NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CM0+ NVIC Mux input 3 */
+ NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CM0+ NVIC Mux input 4 */
+ NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CM0+ NVIC Mux input 5 */
+ NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CM0+ NVIC Mux input 6 */
+ NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CM0+ NVIC Mux input 7 */
+ NvicMux8_IRQn = 8, /*!< 8 [Active] CM0+ NVIC Mux input 8 */
+ NvicMux9_IRQn = 9, /*!< 9 [Active] CM0+ NVIC Mux input 9 */
+ NvicMux10_IRQn = 10, /*!< 10 [Active] CM0+ NVIC Mux input 10 */
+ NvicMux11_IRQn = 11, /*!< 11 [Active] CM0+ NVIC Mux input 11 */
+ NvicMux12_IRQn = 12, /*!< 12 [Active] CM0+ NVIC Mux input 12 */
+ NvicMux13_IRQn = 13, /*!< 13 [Active] CM0+ NVIC Mux input 13 */
+ NvicMux14_IRQn = 14, /*!< 14 [Active] CM0+ NVIC Mux input 14 */
+ NvicMux15_IRQn = 15, /*!< 15 [Active] CM0+ NVIC Mux input 15 */
+ NvicMux16_IRQn = 16, /*!< 16 [Active] CM0+ NVIC Mux input 16 */
+ NvicMux17_IRQn = 17, /*!< 17 [Active] CM0+ NVIC Mux input 17 */
+ NvicMux18_IRQn = 18, /*!< 18 [Active] CM0+ NVIC Mux input 18 */
+ NvicMux19_IRQn = 19, /*!< 19 [Active] CM0+ NVIC Mux input 19 */
+ NvicMux20_IRQn = 20, /*!< 20 [Active] CM0+ NVIC Mux input 20 */
+ NvicMux21_IRQn = 21, /*!< 21 [Active] CM0+ NVIC Mux input 21 */
+ NvicMux22_IRQn = 22, /*!< 22 [Active] CM0+ NVIC Mux input 22 */
+ NvicMux23_IRQn = 23, /*!< 23 [Active] CM0+ NVIC Mux input 23 */
+ NvicMux24_IRQn = 24, /*!< 24 [Active] CM0+ NVIC Mux input 24 */
+ NvicMux25_IRQn = 25, /*!< 25 [Active] CM0+ NVIC Mux input 25 */
+ NvicMux26_IRQn = 26, /*!< 26 [Active] CM0+ NVIC Mux input 26 */
+ NvicMux27_IRQn = 27, /*!< 27 [Active] CM0+ NVIC Mux input 27 */
+ NvicMux28_IRQn = 28, /*!< 28 [Active] CM0+ NVIC Mux input 28 */
+ NvicMux29_IRQn = 29, /*!< 29 [Active] CM0+ NVIC Mux input 29 */
+ NvicMux30_IRQn = 30, /*!< 30 [Active] CM0+ NVIC Mux input 30 */
+ NvicMux31_IRQn = 31, /*!< 31 [Active] CM0+ NVIC Mux input 31 */
+ unconnected_IRQn = 240 /*!< 240 Unconnected */
+#else
+ /* ARM Cortex-M4 Core Interrupt Numbers */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ /* CY8C6247BZI-D54 Peripheral Interrupt Numbers */
+ ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
+ ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
+ ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
+ ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
+ ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
+ ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
+ ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
+ ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
+ ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
+ ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
+ ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
+ ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
+ ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
+ ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
+ ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
+ ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
+ ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
+ lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
+ scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
+ srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
+ srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
+ srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
+ srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
+ bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
+ cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
+ cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
+ cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
+ cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
+ cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
+ cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
+ cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
+ cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
+ cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
+ cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
+ cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
+ cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
+ cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
+ cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
+ cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
+ cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
+ scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
+ scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
+ scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
+ scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
+ scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
+ scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
+ scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
+ scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
+ csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
+ cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
+ cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
+ cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
+ cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
+ cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
+ cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
+ cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
+ cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
+ cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
+ cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
+ cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
+ cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
+ cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
+ cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
+ cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
+ cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
+ cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
+ cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
+ cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
+ cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
+ cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
+ cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
+ cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
+ cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
+ cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
+ cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
+ cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
+ cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
+ cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
+ cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
+ cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
+ cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
+ cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
+ cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
+ cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
+ cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
+ cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
+ cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
+ cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
+ cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
+ tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
+ tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
+ tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
+ tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
+ tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
+ tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
+ tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
+ tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
+ tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
+ tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
+ tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
+ tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
+ tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
+ tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
+ tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
+ tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
+ tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
+ tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
+ tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
+ tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
+ tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
+ tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
+ tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
+ tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
+ tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
+ tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
+ tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
+ tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
+ tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
+ tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
+ tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
+ tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
+ udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
+ udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
+ udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
+ udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
+ udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
+ udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
+ udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
+ udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
+ udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
+ udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
+ udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
+ udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
+ udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
+ udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
+ udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
+ udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
+ pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
+ audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
+ audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
+ profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
+ smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
+ usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
+ usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
+ usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
+ pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
+ unconnected_IRQn = 240 /*!< 240 Unconnected */
+#endif
+} IRQn_Type;
+
+
+#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+ (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
+ (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
+
+/* CY8C6247BZI-D54 interrupts that can be routed to the CM0+ NVIC */
+typedef enum {
+ ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
+ ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
+ ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
+ ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
+ ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
+ ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
+ ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
+ ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
+ ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
+ ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
+ ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
+ ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
+ ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
+ ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
+ ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
+ ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
+ ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
+ lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
+ scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
+ srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
+ srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
+ srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
+ srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
+ bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
+ cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
+ cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
+ cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
+ cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
+ cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
+ cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
+ cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
+ cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
+ cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
+ cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
+ cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
+ cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
+ cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
+ cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
+ cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
+ cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
+ scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
+ scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
+ scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
+ scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
+ scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
+ scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
+ scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
+ scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
+ csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
+ cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
+ cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
+ cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
+ cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
+ cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
+ cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
+ cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
+ cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
+ cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
+ cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
+ cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
+ cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
+ cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
+ cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
+ cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
+ cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
+ cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
+ cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
+ cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
+ cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
+ cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
+ cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
+ cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
+ cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
+ cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
+ cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
+ cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
+ cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
+ cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
+ cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
+ cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
+ cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
+ cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
+ cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
+ cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
+ cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
+ cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
+ cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
+ cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
+ cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
+ tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
+ tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
+ tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
+ tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
+ tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
+ tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
+ tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
+ tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
+ tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
+ tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
+ tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
+ tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
+ tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
+ tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
+ tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
+ tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
+ tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
+ tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
+ tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
+ tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
+ tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
+ tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
+ tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
+ tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
+ tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
+ tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
+ tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
+ tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
+ tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
+ tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
+ tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
+ tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
+ udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
+ udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
+ udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
+ udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
+ udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
+ udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
+ udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
+ udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
+ udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
+ udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
+ udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
+ udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
+ udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
+ udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
+ udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
+ udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
+ pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
+ audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
+ audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
+ profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
+ smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
+ usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
+ usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
+ usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
+ pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
+ disconnected_IRQn = 240 /*!< 240 Disconnected */
+} cy_en_intr_t;
+
+#endif
+
+/*******************************************************************************
+* Processor and Core Peripheral Section
+*******************************************************************************/
+
+#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+ (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
+ (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
+
+/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
+#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+
+/** \} Configuration_of_CMSIS */
+
+#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */
+
+#else
+
+/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
+#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+#define __CM0P_PRESENT 1 /*!< CM0P present or not */
+#define __DTCM_PRESENT 0 /*!< DTCM present or not */
+#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */
+#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */
+
+/** \} Configuration_of_CMSIS */
+
+#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
+
+#endif
+
+/* Memory Blocks */
+#define CY_ROM_BASE 0x00000000UL
+#define CY_ROM_SIZE 0x00020000UL
+#define CY_SRAM_BASE 0x08000000UL
+#define CY_SRAM_SIZE 0x00048000UL
+#define CY_FLASH_BASE 0x10000000UL
+#define CY_FLASH_SIZE 0x00100000UL
+#define CY_EM_EEPROM_BASE 0x14000000UL
+#define CY_EM_EEPROM_SIZE 0x00008000UL
+#define CY_XIP_BASE 0x18000000UL
+#define CY_XIP_SIZE 0x08000000UL
+#define CY_SFLASH_BASE 0x16000000UL
+#define CY_SFLASH_SIZE 0x00008000UL
+#define CY_EFUSE_BASE 0x402C0800UL
+#define CY_EFUSE_SIZE 0x00000200UL
+
+#include "system_psoc6.h" /*!< PSoC 6 System */
+
+/* IP List */
+#define CY_IP_MXTCPWM 1u
+#define CY_IP_MXTCPWM_INSTANCES 2u
+#define CY_IP_MXTCPWM_VERSION 1u
+#define CY_IP_MXCSDV2 1u
+#define CY_IP_MXCSDV2_INSTANCES 1u
+#define CY_IP_MXCSDV2_VERSION 1u
+#define CY_IP_MXLCD 1u
+#define CY_IP_MXLCD_INSTANCES 1u
+#define CY_IP_MXLCD_VERSION 1u
+#define CY_IP_MXS40SRSS 1u
+#define CY_IP_MXS40SRSS_INSTANCES 1u
+#define CY_IP_MXS40SRSS_VERSION 1u
+#define CY_IP_MXS40SRSS_RTC 1u
+#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u
+#define CY_IP_MXS40SRSS_RTC_VERSION 1u
+#define CY_IP_MXS40SRSS_MCWDT 1u
+#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
+#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
+#define CY_IP_MXSCB 1u
+#define CY_IP_MXSCB_INSTANCES 9u
+#define CY_IP_MXSCB_VERSION 1u
+#define CY_IP_MXPERI 1u
+#define CY_IP_MXPERI_INSTANCES 1u
+#define CY_IP_MXPERI_VERSION 1u
+#define CY_IP_MXPERI_TR 1u
+#define CY_IP_MXPERI_TR_INSTANCES 1u
+#define CY_IP_MXPERI_TR_VERSION 1u
+#define CY_IP_M4CPUSS 1u
+#define CY_IP_M4CPUSS_INSTANCES 1u
+#define CY_IP_M4CPUSS_VERSION 1u
+#define CY_IP_M4CPUSS_DMA 1u
+#define CY_IP_M4CPUSS_DMA_INSTANCES 2u
+#define CY_IP_M4CPUSS_DMA_VERSION 1u
+#define CY_IP_MXCRYPTO 1u
+#define CY_IP_MXCRYPTO_INSTANCES 1u
+#define CY_IP_MXCRYPTO_VERSION 1u
+#define CY_IP_MXAUDIOSS 1u
+#define CY_IP_MXAUDIOSS_INSTANCES 1u
+#define CY_IP_MXAUDIOSS_VERSION 1u
+#define CY_IP_MXLPCOMP 1u
+#define CY_IP_MXLPCOMP_INSTANCES 1u
+#define CY_IP_MXLPCOMP_VERSION 1u
+#define CY_IP_MXS40PASS 1u
+#define CY_IP_MXS40PASS_INSTANCES 1u
+#define CY_IP_MXS40PASS_VERSION 1u
+#define CY_IP_MXS40PASS_SAR 1u
+#define CY_IP_MXS40PASS_SAR_INSTANCES 1u
+#define CY_IP_MXS40PASS_SAR_VERSION 1u
+#define CY_IP_MXS40PASS_CTDAC 1u
+#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
+#define CY_IP_MXS40PASS_CTDAC_VERSION 1u
+#define CY_IP_MXS40PASS_CTB 1u
+#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
+#define CY_IP_MXS40PASS_CTB_VERSION 1u
+#define CY_IP_MXSMIF 1u
+#define CY_IP_MXSMIF_INSTANCES 1u
+#define CY_IP_MXSMIF_VERSION 1u
+#define CY_IP_MXUSBFS 1u
+#define CY_IP_MXUSBFS_INSTANCES 1u
+#define CY_IP_MXUSBFS_VERSION 1u
+#define CY_IP_MXS40IOSS 1u
+#define CY_IP_MXS40IOSS_INSTANCES 1u
+#define CY_IP_MXS40IOSS_VERSION 1u
+#define CY_IP_MXEFUSE 1u
+#define CY_IP_MXEFUSE_INSTANCES 1u
+#define CY_IP_MXEFUSE_VERSION 1u
+#define CY_IP_MXUDB 1u
+#define CY_IP_MXUDB_INSTANCES 1u
+#define CY_IP_MXUDB_VERSION 1u
+#define CY_IP_MXPROFILE 1u
+#define CY_IP_MXPROFILE_INSTANCES 1u
+#define CY_IP_MXPROFILE_VERSION 1u
+
+#include "psoc6_01_config.h"
+#include "gpio_psoc6_01_124_bga.h"
+
+#define CY_DEVICE_PSOC6ABLE2
+#define CY_SILICON_ID 0xE2062100UL
+#define CY_HF_CLK_MAX_FREQ 150000000UL
+
+#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
+
+/*******************************************************************************
+* SFLASH
+*******************************************************************************/
+
+#define SFLASH_BASE 0x16000000UL
+#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */
+
+/*******************************************************************************
+* PERI
+*******************************************************************************/
+
+#define PERI_BASE 0x40010000UL
+#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL
+#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL
+#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL
+#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL
+#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL
+#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL
+#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL
+#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL
+#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL
+#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL
+#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL
+#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL
+#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL
+#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL
+#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL
+#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL
+#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL
+#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL
+#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL
+#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL
+#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL
+#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL
+#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL
+#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL
+#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL
+#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL
+#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL
+#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL
+#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL
+#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL
+#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL
+#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL
+#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL
+#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL
+#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL
+#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL
+#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL
+#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL
+#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL
+#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL
+#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL
+#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL
+#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL
+#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL
+#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL
+#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL
+#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL
+#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL
+#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL
+#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL
+#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL
+#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL
+#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL
+#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL
+#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL
+#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL
+#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL
+#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL
+#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL
+#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL
+#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL
+#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL
+#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL
+#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL
+#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */
+#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */
+#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */
+#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */
+#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */
+#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */
+#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */
+#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */
+#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */
+#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */
+#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */
+#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */
+#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */
+#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */
+#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */
+#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */
+#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */
+#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */
+#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */
+#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */
+#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */
+#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */
+#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */
+#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */
+#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */
+#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */
+#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */
+#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */
+#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */
+#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */
+#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */
+#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */
+#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */
+#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */
+#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */
+#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */
+#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */
+#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */
+#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */
+#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */
+#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */
+#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */
+#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */
+#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */
+#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */
+#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */
+#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */
+#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */
+#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */
+#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */
+#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */
+#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */
+#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */
+#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */
+#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */
+#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */
+#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */
+#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */
+#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */
+#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */
+#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */
+#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */
+#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */
+#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */
+#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */
+#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */
+#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */
+#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */
+#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */
+#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */
+#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */
+#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */
+#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */
+#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */
+#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */
+#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */
+#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */
+#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */
+#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */
+#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */
+#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */
+#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */
+#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */
+#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */
+#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */
+#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */
+#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */
+#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */
+#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */
+#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */
+#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */
+#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */
+#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */
+#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */
+#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */
+#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */
+#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */
+#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */
+#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */
+#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */
+#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */
+#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */
+#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */
+#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */
+#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */
+#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */
+#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */
+#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */
+#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */
+#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */
+#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */
+#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */
+
+/*******************************************************************************
+* CRYPTO
+*******************************************************************************/
+
+#define CRYPTO_BASE 0x40110000UL
+#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40110000 */
+
+/*******************************************************************************
+* CPUSS
+*******************************************************************************/
+
+#define CPUSS_BASE 0x40210000UL
+#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */
+
+/*******************************************************************************
+* FAULT
+*******************************************************************************/
+
+#define FAULT_BASE 0x40220000UL
+#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */
+#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */
+#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */
+
+/*******************************************************************************
+* IPC
+*******************************************************************************/
+
+#define IPC_BASE 0x40230000UL
+#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */
+#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */
+#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */
+#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */
+#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */
+#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */
+#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */
+#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */
+#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */
+#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */
+#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */
+#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */
+#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */
+#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */
+#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */
+#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */
+#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */
+#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */
+#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */
+#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */
+#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */
+#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */
+#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */
+#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */
+#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */
+#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */
+#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */
+#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */
+#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */
+#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */
+#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */
+#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */
+#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */
+
+/*******************************************************************************
+* PROT
+*******************************************************************************/
+
+#define PROT_BASE 0x40240000UL
+#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */
+#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */
+#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */
+#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */
+#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */
+#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */
+#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */
+#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */
+#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */
+#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */
+#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */
+#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */
+#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */
+#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */
+#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */
+#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */
+#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */
+#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */
+#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */
+#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */
+#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */
+#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */
+#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */
+#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */
+#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */
+#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */
+#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */
+#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */
+#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */
+#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */
+#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */
+#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */
+#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */
+#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */
+#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */
+#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */
+#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */
+#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */
+#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */
+#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */
+#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */
+#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */
+#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */
+#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */
+#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */
+#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */
+#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */
+#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */
+#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */
+#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */
+
+/*******************************************************************************
+* FLASHC
+*******************************************************************************/
+
+#define FLASHC_BASE 0x40250000UL
+#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */
+#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */
+
+/*******************************************************************************
+* SRSS
+*******************************************************************************/
+
+#define SRSS_BASE 0x40260000UL
+#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */
+#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */
+#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */
+
+/*******************************************************************************
+* BACKUP
+*******************************************************************************/
+
+#define BACKUP_BASE 0x40270000UL
+#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */
+
+/*******************************************************************************
+* DW
+*******************************************************************************/
+
+#define DW0_BASE 0x40280000UL
+#define DW1_BASE 0x40281000UL
+#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */
+#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */
+#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */
+#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */
+#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */
+#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */
+#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */
+#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */
+#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */
+#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */
+#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */
+#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */
+#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */
+#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */
+#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */
+#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */
+#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */
+#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */
+#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */
+#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */
+#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */
+#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */
+#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */
+#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */
+#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */
+#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */
+#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */
+#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */
+#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */
+#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */
+#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */
+#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */
+#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */
+#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */
+
+/*******************************************************************************
+* EFUSE
+*******************************************************************************/
+
+#define EFUSE_BASE 0x402C0000UL
+#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */
+
+/*******************************************************************************
+* PROFILE
+*******************************************************************************/
+
+#define PROFILE_BASE 0x402D0000UL
+#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */
+#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */
+#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */
+#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */
+#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */
+#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */
+#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */
+#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */
+#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */
+
+/*******************************************************************************
+* HSIOM
+*******************************************************************************/
+
+#define HSIOM_BASE 0x40310000UL
+#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */
+#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */
+#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */
+#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */
+#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */
+#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */
+#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */
+#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */
+#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */
+#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */
+#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */
+#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */
+#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */
+#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */
+#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */
+#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */
+
+/*******************************************************************************
+* GPIO
+*******************************************************************************/
+
+#define GPIO_BASE 0x40320000UL
+#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */
+#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
+#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
+#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
+#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
+#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
+#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
+#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
+#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
+#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
+#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
+#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
+#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
+#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
+#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
+#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
+
+/*******************************************************************************
+* SMARTIO
+*******************************************************************************/
+
+#define SMARTIO_BASE 0x40330000UL
+#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */
+#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */
+#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */
+
+/*******************************************************************************
+* UDB
+*******************************************************************************/
+
+#define UDB_BASE 0x40340000UL
+#define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */
+#define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */
+#define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */
+#define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */
+#define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */
+#define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */
+#define UDB_UDBPAIR1_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[1]) /* 0x40342280 */
+#define UDB_UDBPAIR2_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[0]) /* 0x40342400 */
+#define UDB_UDBPAIR2_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[1]) /* 0x40342480 */
+#define UDB_UDBPAIR3_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[0]) /* 0x40342600 */
+#define UDB_UDBPAIR3_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[1]) /* 0x40342680 */
+#define UDB_UDBPAIR4_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[0]) /* 0x40342800 */
+#define UDB_UDBPAIR4_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[1]) /* 0x40342880 */
+#define UDB_UDBPAIR5_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[0]) /* 0x40342A00 */
+#define UDB_UDBPAIR5_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[1]) /* 0x40342A80 */
+#define UDB_UDBPAIR0_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[0].ROUTE) /* 0x40342100 */
+#define UDB_UDBPAIR1_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[1].ROUTE) /* 0x40342300 */
+#define UDB_UDBPAIR2_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[2].ROUTE) /* 0x40342500 */
+#define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */
+#define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */
+#define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */
+#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */
+#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */
+#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */
+#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */
+#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */
+#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */
+#define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */
+#define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */
+#define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */
+#define UDB_DSI3 ((UDB_DSI_Type*) &UDB->DSI[3]) /* 0x40346180 */
+#define UDB_DSI4 ((UDB_DSI_Type*) &UDB->DSI[4]) /* 0x40346200 */
+#define UDB_DSI5 ((UDB_DSI_Type*) &UDB->DSI[5]) /* 0x40346280 */
+#define UDB_DSI6 ((UDB_DSI_Type*) &UDB->DSI[6]) /* 0x40346300 */
+#define UDB_DSI7 ((UDB_DSI_Type*) &UDB->DSI[7]) /* 0x40346380 */
+#define UDB_DSI8 ((UDB_DSI_Type*) &UDB->DSI[8]) /* 0x40346400 */
+#define UDB_DSI9 ((UDB_DSI_Type*) &UDB->DSI[9]) /* 0x40346480 */
+#define UDB_DSI10 ((UDB_DSI_Type*) &UDB->DSI[10]) /* 0x40346500 */
+#define UDB_DSI11 ((UDB_DSI_Type*) &UDB->DSI[11]) /* 0x40346580 */
+#define UDB_PA0 ((UDB_PA_Type*) &UDB->PA[0]) /* 0x40347000 */
+#define UDB_PA1 ((UDB_PA_Type*) &UDB->PA[1]) /* 0x40347040 */
+#define UDB_PA2 ((UDB_PA_Type*) &UDB->PA[2]) /* 0x40347080 */
+#define UDB_PA3 ((UDB_PA_Type*) &UDB->PA[3]) /* 0x403470C0 */
+#define UDB_PA4 ((UDB_PA_Type*) &UDB->PA[4]) /* 0x40347100 */
+#define UDB_PA5 ((UDB_PA_Type*) &UDB->PA[5]) /* 0x40347140 */
+#define UDB_PA6 ((UDB_PA_Type*) &UDB->PA[6]) /* 0x40347180 */
+#define UDB_PA7 ((UDB_PA_Type*) &UDB->PA[7]) /* 0x403471C0 */
+#define UDB_PA8 ((UDB_PA_Type*) &UDB->PA[8]) /* 0x40347200 */
+#define UDB_PA9 ((UDB_PA_Type*) &UDB->PA[9]) /* 0x40347240 */
+#define UDB_PA10 ((UDB_PA_Type*) &UDB->PA[10]) /* 0x40347280 */
+#define UDB_PA11 ((UDB_PA_Type*) &UDB->PA[11]) /* 0x403472C0 */
+#define UDB_BCTL ((UDB_BCTL_Type*) &UDB->BCTL) /* 0x40347800 */
+#define UDB_UDBIF ((UDB_UDBIF_Type*) &UDB->UDBIF) /* 0x40347900 */
+
+/*******************************************************************************
+* LPCOMP
+*******************************************************************************/
+
+#define LPCOMP_BASE 0x40350000UL
+#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */
+
+/*******************************************************************************
+* CSD
+*******************************************************************************/
+
+#define CSD0_BASE 0x40360000UL
+#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */
+
+/*******************************************************************************
+* TCPWM
+*******************************************************************************/
+
+#define TCPWM0_BASE 0x40380000UL
+#define TCPWM1_BASE 0x40390000UL
+#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */
+#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */
+#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */
+#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */
+#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */
+#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */
+#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */
+#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */
+#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */
+#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */
+#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */
+#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */
+#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */
+#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */
+#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */
+#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */
+#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */
+#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */
+#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */
+#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */
+#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */
+#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */
+#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */
+#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */
+#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */
+#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */
+#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */
+#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */
+#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */
+#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */
+#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */
+#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */
+#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */
+#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */
+
+/*******************************************************************************
+* LCD
+*******************************************************************************/
+
+#define LCD0_BASE 0x403B0000UL
+#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */
+
+/*******************************************************************************
+* USBFS
+*******************************************************************************/
+
+#define USBFS0_BASE 0x403F0000UL
+#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */
+#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */
+#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */
+#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */
+
+/*******************************************************************************
+* SMIF
+*******************************************************************************/
+
+#define SMIF0_BASE 0x40420000UL
+#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */
+#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */
+#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */
+#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */
+#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */
+
+/*******************************************************************************
+* SCB
+*******************************************************************************/
+
+#define SCB0_BASE 0x40610000UL
+#define SCB1_BASE 0x40620000UL
+#define SCB2_BASE 0x40630000UL
+#define SCB3_BASE 0x40640000UL
+#define SCB4_BASE 0x40650000UL
+#define SCB5_BASE 0x40660000UL
+#define SCB6_BASE 0x40670000UL
+#define SCB7_BASE 0x40680000UL
+#define SCB8_BASE 0x40690000UL
+#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */
+#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */
+#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */
+#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */
+#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */
+#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */
+#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */
+#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */
+#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */
+
+/*******************************************************************************
+* CTBM
+*******************************************************************************/
+
+#define CTBM0_BASE 0x41100000UL
+#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */
+
+/*******************************************************************************
+* CTDAC
+*******************************************************************************/
+
+#define CTDAC0_BASE 0x41140000UL
+#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */
+
+/*******************************************************************************
+* SAR
+*******************************************************************************/
+
+#define SAR_BASE 0x411D0000UL
+#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */
+
+/*******************************************************************************
+* PASS
+*******************************************************************************/
+
+#define PASS_BASE 0x411F0000UL
+#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */
+#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */
+
+/*******************************************************************************
+* I2S
+*******************************************************************************/
+
+#define I2S0_BASE 0x42A10000UL
+#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
+
+/*******************************************************************************
+* PDM
+*******************************************************************************/
+
+#define PDM0_BASE 0x42A20000UL
+#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
+
+
+/* Backward compatibility definitions */
+#define CY_SRAM0_BASE CY_SRAM_BASE
+#define CY_SRAM0_SIZE CY_SRAM_SIZE
+#define I2S I2S0
+#define PDM PDM0
+
+/** \} CY8C6247BZI-D54 */
+
+#endif /* _CY8C6247BZI_D54_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/cy_device_headers.h b/platform/ext/target/psoc64/Device/Include/cy_device_headers.h
new file mode 100644
index 0000000000..4a0d2bdfb5
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/cy_device_headers.h
@@ -0,0 +1,246 @@
+/***************************************************************************//**
+* \file cy_device_headers.h
+*
+* \brief
+* Common header file to be included by the drivers.
+*
+* \note
+* Generator version: 1.5.0.1292
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CY_DEVICE_HEADERS_H_
+#define _CY_DEVICE_HEADERS_H_
+
+#if defined (CY_DEVICE_COMMON)
+ #include "cy_device_common.h"
+#elif defined (CY8C6036BZI_F04)
+ #include "cy8c6036bzi_f04.h"
+#elif defined (CY8C6016BZI_F04)
+ #include "cy8c6016bzi_f04.h"
+#elif defined (CY8C6116BZI_F54)
+ #include "cy8c6116bzi_f54.h"
+#elif defined (CY8C6136BZI_F14)
+ #include "cy8c6136bzi_f14.h"
+#elif defined (CY8C6136BZI_F34)
+ #include "cy8c6136bzi_f34.h"
+#elif defined (CY8C6137BZI_F14)
+ #include "cy8c6137bzi_f14.h"
+#elif defined (CY8C6137BZI_F34)
+ #include "cy8c6137bzi_f34.h"
+#elif defined (CY8C6137BZI_F54)
+ #include "cy8c6137bzi_f54.h"
+#elif defined (CY8C6117BZI_F34)
+ #include "cy8c6117bzi_f34.h"
+#elif defined (CY8C6246BZI_D04)
+ #include "cy8c6246bzi_d04.h"
+#elif defined (CY8C6247BZI_D44)
+ #include "cy8c6247bzi_d44.h"
+#elif defined (CY8C6247BZI_D34)
+ #include "cy8c6247bzi_d34.h"
+#elif defined (CY8C6247BZI_D54)
+ #include "cy8c6247bzi_d54.h"
+#elif defined (CY8C6336BZI_BLF03)
+ #include "cy8c6336bzi_blf03.h"
+#elif defined (CY8C6316BZI_BLF03)
+ #include "cy8c6316bzi_blf03.h"
+#elif defined (CY8C6316BZI_BLF53)
+ #include "cy8c6316bzi_blf53.h"
+#elif defined (CY8C6336BZI_BLD13)
+ #include "cy8c6336bzi_bld13.h"
+#elif defined (CY8C6347BZI_BLD43)
+ #include "cy8c6347bzi_bld43.h"
+#elif defined (CY8C6347BZI_BLD33)
+ #include "cy8c6347bzi_bld33.h"
+#elif defined (CY8C6347BZI_BLD53)
+ #include "cy8c6347bzi_bld53.h"
+#elif defined (CY8C6347FMI_BLD13)
+ #include "cy8c6347fmi_bld13.h"
+#elif defined (CY8C6347FMI_BLD43)
+ #include "cy8c6347fmi_bld43.h"
+#elif defined (CY8C6347FMI_BLD33)
+ #include "cy8c6347fmi_bld33.h"
+#elif defined (CY8C6347FMI_BLD53)
+ #include "cy8c6347fmi_bld53.h"
+#elif defined (CY8C637BZI_MD76)
+ #include "cy8c637bzi_md76.h"
+#elif defined (CY8C637BZI_BLD74)
+ #include "cy8c637bzi_bld74.h"
+#elif defined (CY8C637FMI_BLD73)
+ #include "cy8c637fmi_bld73.h"
+#elif defined (CY8C68237BZ_BLE)
+ #include "cy8c68237bz_ble.h"
+#elif defined (CY8C68237FM_BLE)
+ #include "cy8c68237fm_ble.h"
+#elif defined (CY8C6137FDI_F02)
+ #include "cy8c6137fdi_f02.h"
+#elif defined (CY8C6117FDI_F02)
+ #include "cy8c6117fdi_f02.h"
+#elif defined (CY8C6247FDI_D02)
+ #include "cy8c6247fdi_d02.h"
+#elif defined (CY8C6247FDI_D32)
+ #include "cy8c6247fdi_d32.h"
+#elif defined (CY8C6336BZI_BUD13)
+ #include "cy8c6336bzi_bud13.h"
+#elif defined (CY8C6347BZI_BUD43)
+ #include "cy8c6347bzi_bud43.h"
+#elif defined (CY8C6347BZI_BUD33)
+ #include "cy8c6347bzi_bud33.h"
+#elif defined (CY8C6347BZI_BUD53)
+ #include "cy8c6347bzi_bud53.h"
+#elif defined (CY8C6337BZI_BLF13)
+ #include "cy8c6337bzi_blf13.h"
+#elif defined (CY8C6136FDI_F42)
+ #include "cy8c6136fdi_f42.h"
+#elif defined (CY8C6247FDI_D52)
+ #include "cy8c6247fdi_d52.h"
+#elif defined (CY8C6136FTI_F42)
+ #include "cy8c6136fti_f42.h"
+#elif defined (CY8C6247FTI_D52)
+ #include "cy8c6247fti_d52.h"
+#elif defined (CY8C6247BZI_AUD54)
+ #include "cy8c6247bzi_aud54.h"
+#elif defined (CY8C6336BZI_BLF04)
+ #include "cy8c6336bzi_blf04.h"
+#elif defined (CY8C6316BZI_BLF04)
+ #include "cy8c6316bzi_blf04.h"
+#elif defined (CY8C6316BZI_BLF54)
+ #include "cy8c6316bzi_blf54.h"
+#elif defined (CY8C6336BZI_BLD14)
+ #include "cy8c6336bzi_bld14.h"
+#elif defined (CY8C6347BZI_BLD44)
+ #include "cy8c6347bzi_bld44.h"
+#elif defined (CY8C6347BZI_BLD34)
+ #include "cy8c6347bzi_bld34.h"
+#elif defined (CY8C6347BZI_BLD54)
+ #include "cy8c6347bzi_bld54.h"
+#elif defined (CY8C6247BFI_D54)
+ #include "cy8c6247bfi_d54.h"
+#elif defined (CYBLE_416045_02)
+ #include "cyble_416045_02.h"
+#elif defined (CY8C6347FMI_BUD53)
+ #include "cy8c6347fmi_bud53.h"
+#elif defined (CY8C6347FMI_BUD13)
+ #include "cy8c6347fmi_bud13.h"
+#elif defined (CY8C6347FMI_BUD43)
+ #include "cy8c6347fmi_bud43.h"
+#elif defined (CY8C6347FMI_BUD33)
+ #include "cy8c6347fmi_bud33.h"
+#elif defined (CY8C6137WI_F54)
+ #include "cy8c6137wi_f54.h"
+#elif defined (CY8C6117WI_F34)
+ #include "cy8c6117wi_f34.h"
+#elif defined (CY8C6247WI_D54)
+ #include "cy8c6247wi_d54.h"
+#elif defined (CYB06447BZI_BLD54)
+ #include "cyb06447bzi_bld54.h"
+#elif defined (CYB06447BZI_BLD53)
+ #include "cyb06447bzi_bld53.h"
+#elif defined (CYB06447BZI_D54)
+ #include "cyb06447bzi_d54.h"
+#elif defined (CY8C6336LQI_BLF02)
+ #include "cy8c6336lqi_blf02.h"
+#elif defined (CY8C6336LQI_BLF42)
+ #include "cy8c6336lqi_blf42.h"
+#elif defined (CY8C6347LQI_BLD52)
+ #include "cy8c6347lqi_bld52.h"
+#elif defined (CY8C624ABZI_D44)
+ #include "cy8c624abzi_d44.h"
+#elif defined (CY8C624AAZI_D44)
+ #include "cy8c624aazi_d44.h"
+#elif defined (CY8C624AFNI_D43)
+ #include "cy8c624afni_d43.h"
+#elif defined (CY8C624ABZI_D04)
+ #include "cy8c624abzi_d04.h"
+#elif defined (CY8C624ABZI_D14)
+ #include "cy8c624abzi_d14.h"
+#elif defined (CY8C624AAZI_D14)
+ #include "cy8c624aazi_d14.h"
+#elif defined (CY8C6248AZI_D14)
+ #include "cy8c6248azi_d14.h"
+#elif defined (CY8C6248BZI_D44)
+ #include "cy8c6248bzi_d44.h"
+#elif defined (CY8C6248AZI_D44)
+ #include "cy8c6248azi_d44.h"
+#elif defined (CY8C6248FNI_D43)
+ #include "cy8c6248fni_d43.h"
+#elif defined (CY8C624ALQI_D42)
+ #include "cy8c624alqi_d42.h"
+#elif defined (CYB0644ABZI_S2D44)
+ #include "cyb0644abzi_s2d44.h"
+#elif defined (CY8C624ABZI_S2D44A0)
+ #include "cy8c624abzi_s2d44a0.h"
+#elif defined (CY8C624ABZI_S2D44)
+ #include "cy8c624abzi_s2d44.h"
+#elif defined (CY8C624AAZI_S2D44)
+ #include "cy8c624aazi_s2d44.h"
+#elif defined (CY8C624AFNI_S2D43)
+ #include "cy8c624afni_s2d43.h"
+#elif defined (CY8C624ABZI_S2D04)
+ #include "cy8c624abzi_s2d04.h"
+#elif defined (CY8C624ABZI_S2D14)
+ #include "cy8c624abzi_s2d14.h"
+#elif defined (CY8C624AAZI_S2D14)
+ #include "cy8c624aazi_s2d14.h"
+#elif defined (CY8C6248AZI_S2D14)
+ #include "cy8c6248azi_s2d14.h"
+#elif defined (CY8C6248BZI_S2D44)
+ #include "cy8c6248bzi_s2d44.h"
+#elif defined (CY8C6248AZI_S2D44)
+ #include "cy8c6248azi_s2d44.h"
+#elif defined (CY8C6248FNI_S2D43)
+ #include "cy8c6248fni_s2d43.h"
+#elif defined (CY8C6245AZI_S3D72)
+ #include "cy8c6245azi_s3d72.h"
+#elif defined (CY8C6245LQI_S3D72)
+ #include "cy8c6245lqi_s3d72.h"
+#elif defined (CY8C6245FNI_S3D71)
+ #include "cy8c6245fni_s3d71.h"
+#elif defined (CY8C6245AZI_S3D62)
+ #include "cy8c6245azi_s3d62.h"
+#elif defined (CY8C6245LQI_S3D62)
+ #include "cy8c6245lqi_s3d62.h"
+#elif defined (CY8C6245AZI_S3D42)
+ #include "cy8c6245azi_s3d42.h"
+#elif defined (CY8C6245LQI_S3D42)
+ #include "cy8c6245lqi_s3d42.h"
+#elif defined (CYB06445LQI_S3D42)
+ #include "cyb06445lqi_s3d42.h"
+#elif defined (CY8C6245FNI_S3D41)
+ #include "cy8c6245fni_s3d41.h"
+#elif defined (CY8C6245AZI_S3D12)
+ #include "cy8c6245azi_s3d12.h"
+#elif defined (CY8C6245LQI_S3D12)
+ #include "cy8c6245lqi_s3d12.h"
+#elif defined (CY8C6245FNI_S3D11)
+ #include "cy8c6245fni_s3d11.h"
+#elif defined (CY8C6245AZI_S3D02)
+ #include "cy8c6245azi_s3d02.h"
+#elif defined (CY8C6245LQI_S3D02)
+ #include "cy8c6245lqi_s3d02.h"
+#elif defined (CY8C6245W_S3D72)
+ #include "cy8c6245w_s3d72.h"
+#else
+ #include "cy_device_common.h"
+#endif
+
+#endif /* _CY_DEVICE_HEADERS_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/cyb06447bzi_d54.h b/platform/ext/target/psoc64/Device/Include/cyb06447bzi_d54.h
new file mode 100644
index 0000000000..ecc81689f5
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/cyb06447bzi_d54.h
@@ -0,0 +1,1255 @@
+/***************************************************************************//**
+* \file cyb06447bzi_d54.h
+*
+* \brief
+* CYB06447BZI-D54 device header
+*
+* \note
+* Generator version: 1.5.0.1292
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYB06447BZI_D54_H_
+#define _CYB06447BZI_D54_H_
+
+/**
+* \addtogroup group_device CYB06447BZI-D54
+* \{
+*/
+
+/**
+* \addtogroup Configuration_of_CMSIS
+* \{
+*/
+
+/*******************************************************************************
+* Interrupt Number Definition
+*******************************************************************************/
+
+typedef enum {
+#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+ (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
+ (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
+ /* ARM Cortex-M0+ Core Interrupt Numbers */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ /* ARM Cortex-M0+ NVIC Mux inputs. Allow routing of device interrupts to the CM0+ NVIC */
+ NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CM0+ NVIC Mux input 0 */
+ NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CM0+ NVIC Mux input 1 */
+ NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CM0+ NVIC Mux input 2 */
+ NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CM0+ NVIC Mux input 3 */
+ NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CM0+ NVIC Mux input 4 */
+ NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CM0+ NVIC Mux input 5 */
+ NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CM0+ NVIC Mux input 6 */
+ NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CM0+ NVIC Mux input 7 */
+ NvicMux8_IRQn = 8, /*!< 8 [Active] CM0+ NVIC Mux input 8 */
+ NvicMux9_IRQn = 9, /*!< 9 [Active] CM0+ NVIC Mux input 9 */
+ NvicMux10_IRQn = 10, /*!< 10 [Active] CM0+ NVIC Mux input 10 */
+ NvicMux11_IRQn = 11, /*!< 11 [Active] CM0+ NVIC Mux input 11 */
+ NvicMux12_IRQn = 12, /*!< 12 [Active] CM0+ NVIC Mux input 12 */
+ NvicMux13_IRQn = 13, /*!< 13 [Active] CM0+ NVIC Mux input 13 */
+ NvicMux14_IRQn = 14, /*!< 14 [Active] CM0+ NVIC Mux input 14 */
+ NvicMux15_IRQn = 15, /*!< 15 [Active] CM0+ NVIC Mux input 15 */
+ NvicMux16_IRQn = 16, /*!< 16 [Active] CM0+ NVIC Mux input 16 */
+ NvicMux17_IRQn = 17, /*!< 17 [Active] CM0+ NVIC Mux input 17 */
+ NvicMux18_IRQn = 18, /*!< 18 [Active] CM0+ NVIC Mux input 18 */
+ NvicMux19_IRQn = 19, /*!< 19 [Active] CM0+ NVIC Mux input 19 */
+ NvicMux20_IRQn = 20, /*!< 20 [Active] CM0+ NVIC Mux input 20 */
+ NvicMux21_IRQn = 21, /*!< 21 [Active] CM0+ NVIC Mux input 21 */
+ NvicMux22_IRQn = 22, /*!< 22 [Active] CM0+ NVIC Mux input 22 */
+ NvicMux23_IRQn = 23, /*!< 23 [Active] CM0+ NVIC Mux input 23 */
+ NvicMux24_IRQn = 24, /*!< 24 [Active] CM0+ NVIC Mux input 24 */
+ NvicMux25_IRQn = 25, /*!< 25 [Active] CM0+ NVIC Mux input 25 */
+ NvicMux26_IRQn = 26, /*!< 26 [Active] CM0+ NVIC Mux input 26 */
+ NvicMux27_IRQn = 27, /*!< 27 [Active] CM0+ NVIC Mux input 27 */
+ NvicMux28_IRQn = 28, /*!< 28 [Active] CM0+ NVIC Mux input 28 */
+ NvicMux29_IRQn = 29, /*!< 29 [Active] CM0+ NVIC Mux input 29 */
+ NvicMux30_IRQn = 30, /*!< 30 [Active] CM0+ NVIC Mux input 30 */
+ NvicMux31_IRQn = 31, /*!< 31 [Active] CM0+ NVIC Mux input 31 */
+ unconnected_IRQn = 240 /*!< 240 Unconnected */
+#else
+ /* ARM Cortex-M4 Core Interrupt Numbers */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ /* CYB06447BZI-D54 Peripheral Interrupt Numbers */
+ ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
+ ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
+ ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
+ ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
+ ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
+ ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
+ ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
+ ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
+ ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
+ ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
+ ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
+ ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
+ ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
+ ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
+ ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
+ ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
+ ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
+ lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
+ scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
+ srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
+ srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
+ srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
+ srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
+ bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
+ cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
+ cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
+ cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
+ cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
+ cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
+ cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
+ cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
+ cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
+ cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
+ cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
+ cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
+ cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
+ cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
+ cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
+ cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
+ cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
+ scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
+ scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
+ scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
+ scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
+ scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
+ scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
+ scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
+ scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
+ csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
+ cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
+ cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
+ cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
+ cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
+ cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
+ cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
+ cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
+ cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
+ cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
+ cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
+ cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
+ cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
+ cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
+ cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
+ cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
+ cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
+ cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
+ cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
+ cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
+ cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
+ cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
+ cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
+ cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
+ cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
+ cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
+ cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
+ cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
+ cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
+ cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
+ cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
+ cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
+ cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
+ cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
+ cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
+ cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
+ cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
+ cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
+ cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
+ cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
+ cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
+ tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
+ tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
+ tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
+ tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
+ tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
+ tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
+ tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
+ tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
+ tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
+ tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
+ tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
+ tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
+ tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
+ tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
+ tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
+ tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
+ tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
+ tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
+ tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
+ tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
+ tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
+ tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
+ tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
+ tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
+ tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
+ tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
+ tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
+ tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
+ tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
+ tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
+ tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
+ tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
+ udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
+ udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
+ udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
+ udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
+ udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
+ udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
+ udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
+ udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
+ udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
+ udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
+ udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
+ udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
+ udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
+ udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
+ udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
+ udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
+ pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
+ audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
+ audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
+ profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
+ smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
+ usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
+ usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
+ usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
+ pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
+ unconnected_IRQn = 240 /*!< 240 Unconnected */
+#endif
+} IRQn_Type;
+
+
+#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+ (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
+ (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
+
+/* CYB06447BZI-D54 interrupts that can be routed to the CM0+ NVIC */
+typedef enum {
+ ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
+ ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
+ ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
+ ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
+ ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
+ ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
+ ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
+ ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
+ ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
+ ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
+ ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
+ ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
+ ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
+ ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
+ ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
+ ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
+ ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
+ lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
+ scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
+ srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
+ srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
+ srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
+ srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
+ bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
+ cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
+ cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
+ cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
+ cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
+ cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
+ cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
+ cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
+ cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
+ cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
+ cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
+ cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
+ cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
+ cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
+ cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
+ cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
+ cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
+ scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
+ scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
+ scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
+ scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
+ scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
+ scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
+ scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
+ scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
+ csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
+ cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
+ cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
+ cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
+ cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
+ cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
+ cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
+ cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
+ cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
+ cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
+ cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
+ cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
+ cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
+ cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
+ cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
+ cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
+ cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
+ cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
+ cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
+ cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
+ cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
+ cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
+ cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
+ cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
+ cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
+ cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
+ cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
+ cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
+ cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
+ cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
+ cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
+ cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
+ cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
+ cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
+ cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
+ cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
+ cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
+ cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
+ cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
+ cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
+ cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
+ tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
+ tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
+ tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
+ tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
+ tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
+ tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
+ tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
+ tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
+ tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
+ tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
+ tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
+ tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
+ tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
+ tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
+ tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
+ tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
+ tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
+ tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
+ tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
+ tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
+ tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
+ tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
+ tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
+ tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
+ tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
+ tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
+ tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
+ tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
+ tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
+ tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
+ tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
+ tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
+ udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
+ udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
+ udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
+ udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
+ udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
+ udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
+ udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
+ udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
+ udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
+ udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
+ udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
+ udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
+ udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
+ udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
+ udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
+ udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
+ pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
+ audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
+ audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
+ profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
+ smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
+ usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
+ usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
+ usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
+ pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
+ disconnected_IRQn = 240 /*!< 240 Disconnected */
+} cy_en_intr_t;
+
+#endif
+
+/*******************************************************************************
+* Processor and Core Peripheral Section
+*******************************************************************************/
+
+#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+ (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
+ (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
+
+/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
+#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+
+/** \} Configuration_of_CMSIS */
+
+#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */
+
+#else
+
+/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
+#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+#define __CM0P_PRESENT 1 /*!< CM0P present or not */
+#define __DTCM_PRESENT 0 /*!< DTCM present or not */
+#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */
+#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */
+
+/** \} Configuration_of_CMSIS */
+
+#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
+
+#endif
+
+/* Memory Blocks */
+#define CY_ROM_BASE 0x00000000UL
+#define CY_ROM_SIZE 0x00020000UL
+#define CY_SRAM_BASE 0x08000000UL
+#define CY_SRAM_SIZE 0x00048000UL
+#define CY_FLASH_BASE 0x10000000UL
+#define CY_FLASH_SIZE 0x000D0000UL
+#define CY_EM_EEPROM_BASE 0x14000000UL
+#define CY_EM_EEPROM_SIZE 0x00008000UL
+#define CY_XIP_BASE 0x18000000UL
+#define CY_XIP_SIZE 0x08000000UL
+#define CY_SFLASH_BASE 0x16000000UL
+#define CY_SFLASH_SIZE 0x00008000UL
+#define CY_EFUSE_BASE 0x402C0800UL
+#define CY_EFUSE_SIZE 0x00000200UL
+
+#include "system_psoc6.h" /*!< PSoC 6 System */
+
+/* IP List */
+#define CY_IP_MXTCPWM 1u
+#define CY_IP_MXTCPWM_INSTANCES 2u
+#define CY_IP_MXTCPWM_VERSION 1u
+#define CY_IP_MXCSDV2 1u
+#define CY_IP_MXCSDV2_INSTANCES 1u
+#define CY_IP_MXCSDV2_VERSION 1u
+#define CY_IP_MXLCD 1u
+#define CY_IP_MXLCD_INSTANCES 1u
+#define CY_IP_MXLCD_VERSION 1u
+#define CY_IP_MXS40SRSS 1u
+#define CY_IP_MXS40SRSS_INSTANCES 1u
+#define CY_IP_MXS40SRSS_VERSION 1u
+#define CY_IP_MXS40SRSS_RTC 1u
+#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u
+#define CY_IP_MXS40SRSS_RTC_VERSION 1u
+#define CY_IP_MXS40SRSS_MCWDT 1u
+#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
+#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
+#define CY_IP_MXSCB 1u
+#define CY_IP_MXSCB_INSTANCES 9u
+#define CY_IP_MXSCB_VERSION 1u
+#define CY_IP_MXPERI 1u
+#define CY_IP_MXPERI_INSTANCES 1u
+#define CY_IP_MXPERI_VERSION 1u
+#define CY_IP_MXPERI_TR 1u
+#define CY_IP_MXPERI_TR_INSTANCES 1u
+#define CY_IP_MXPERI_TR_VERSION 1u
+#define CY_IP_M4CPUSS 1u
+#define CY_IP_M4CPUSS_INSTANCES 1u
+#define CY_IP_M4CPUSS_VERSION 1u
+#define CY_IP_M4CPUSS_DMA 1u
+#define CY_IP_M4CPUSS_DMA_INSTANCES 2u
+#define CY_IP_M4CPUSS_DMA_VERSION 1u
+#define CY_IP_MXCRYPTO 1u
+#define CY_IP_MXCRYPTO_INSTANCES 1u
+#define CY_IP_MXCRYPTO_VERSION 1u
+#define CY_IP_MXAUDIOSS 1u
+#define CY_IP_MXAUDIOSS_INSTANCES 1u
+#define CY_IP_MXAUDIOSS_VERSION 1u
+#define CY_IP_MXLPCOMP 1u
+#define CY_IP_MXLPCOMP_INSTANCES 1u
+#define CY_IP_MXLPCOMP_VERSION 1u
+#define CY_IP_MXS40PASS 1u
+#define CY_IP_MXS40PASS_INSTANCES 1u
+#define CY_IP_MXS40PASS_VERSION 1u
+#define CY_IP_MXS40PASS_SAR 1u
+#define CY_IP_MXS40PASS_SAR_INSTANCES 1u
+#define CY_IP_MXS40PASS_SAR_VERSION 1u
+#define CY_IP_MXS40PASS_CTDAC 1u
+#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
+#define CY_IP_MXS40PASS_CTDAC_VERSION 1u
+#define CY_IP_MXS40PASS_CTB 1u
+#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
+#define CY_IP_MXS40PASS_CTB_VERSION 1u
+#define CY_IP_MXSMIF 1u
+#define CY_IP_MXSMIF_INSTANCES 1u
+#define CY_IP_MXSMIF_VERSION 1u
+#define CY_IP_MXUSBFS 1u
+#define CY_IP_MXUSBFS_INSTANCES 1u
+#define CY_IP_MXUSBFS_VERSION 1u
+#define CY_IP_MXS40IOSS 1u
+#define CY_IP_MXS40IOSS_INSTANCES 1u
+#define CY_IP_MXS40IOSS_VERSION 1u
+#define CY_IP_MXEFUSE 1u
+#define CY_IP_MXEFUSE_INSTANCES 1u
+#define CY_IP_MXEFUSE_VERSION 1u
+#define CY_IP_MXUDB 1u
+#define CY_IP_MXUDB_INSTANCES 1u
+#define CY_IP_MXUDB_VERSION 1u
+#define CY_IP_MXPROFILE 1u
+#define CY_IP_MXPROFILE_INSTANCES 1u
+#define CY_IP_MXPROFILE_VERSION 1u
+
+#include "psoc6_01_config.h"
+#include "gpio_psoc6_01_124_bga.h"
+
+#define CY_DEVICE_PSOC6ABLE2
+#define CY_SILICON_ID 0xE2622100UL
+#define CY_HF_CLK_MAX_FREQ 150000000UL
+
+#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
+
+/*******************************************************************************
+* SFLASH
+*******************************************************************************/
+
+#define SFLASH_BASE 0x16000000UL
+#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */
+
+/*******************************************************************************
+* PERI
+*******************************************************************************/
+
+#define PERI_BASE 0x40010000UL
+#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL
+#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL
+#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL
+#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL
+#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL
+#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL
+#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL
+#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL
+#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL
+#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL
+#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL
+#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL
+#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL
+#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL
+#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL
+#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL
+#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL
+#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL
+#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL
+#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL
+#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL
+#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL
+#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL
+#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL
+#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL
+#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL
+#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL
+#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL
+#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL
+#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL
+#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL
+#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL
+#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL
+#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL
+#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL
+#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL
+#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL
+#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL
+#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL
+#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL
+#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL
+#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL
+#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL
+#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL
+#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL
+#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL
+#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL
+#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL
+#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL
+#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL
+#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL
+#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL
+#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL
+#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL
+#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL
+#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL
+#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL
+#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL
+#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL
+#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL
+#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL
+#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL
+#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL
+#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL
+#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */
+#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */
+#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */
+#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */
+#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */
+#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */
+#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */
+#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */
+#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */
+#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */
+#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */
+#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */
+#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */
+#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */
+#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */
+#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */
+#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */
+#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */
+#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */
+#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */
+#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */
+#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */
+#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */
+#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */
+#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */
+#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */
+#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */
+#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */
+#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */
+#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */
+#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */
+#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */
+#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */
+#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */
+#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */
+#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */
+#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */
+#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */
+#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */
+#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */
+#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */
+#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */
+#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */
+#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */
+#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */
+#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */
+#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */
+#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */
+#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */
+#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */
+#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */
+#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */
+#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */
+#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */
+#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */
+#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */
+#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */
+#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */
+#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */
+#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */
+#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */
+#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */
+#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */
+#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */
+#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */
+#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */
+#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */
+#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */
+#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */
+#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */
+#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */
+#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */
+#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */
+#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */
+#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */
+#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */
+#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */
+#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */
+#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */
+#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */
+#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */
+#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */
+#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */
+#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */
+#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */
+#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */
+#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */
+#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */
+#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */
+#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */
+#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */
+#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */
+#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */
+#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */
+#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */
+#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */
+#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */
+#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */
+#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */
+#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */
+#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */
+#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */
+#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */
+#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */
+#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */
+#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */
+#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */
+#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */
+#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */
+#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */
+#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */
+#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */
+
+/*******************************************************************************
+* CRYPTO
+*******************************************************************************/
+
+#define CRYPTO_BASE 0x40110000UL
+#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40110000 */
+
+/*******************************************************************************
+* CPUSS
+*******************************************************************************/
+
+#define CPUSS_BASE 0x40210000UL
+#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */
+
+/*******************************************************************************
+* FAULT
+*******************************************************************************/
+
+#define FAULT_BASE 0x40220000UL
+#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */
+#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */
+#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */
+
+/*******************************************************************************
+* IPC
+*******************************************************************************/
+
+#define IPC_BASE 0x40230000UL
+#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */
+#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */
+#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */
+#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */
+#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */
+#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */
+#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */
+#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */
+#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */
+#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */
+#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */
+#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */
+#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */
+#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */
+#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */
+#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */
+#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */
+#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */
+#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */
+#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */
+#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */
+#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */
+#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */
+#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */
+#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */
+#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */
+#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */
+#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */
+#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */
+#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */
+#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */
+#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */
+#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */
+
+/*******************************************************************************
+* PROT
+*******************************************************************************/
+
+#define PROT_BASE 0x40240000UL
+#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */
+#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */
+#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */
+#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */
+#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */
+#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */
+#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */
+#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */
+#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */
+#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */
+#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */
+#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */
+#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */
+#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */
+#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */
+#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */
+#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */
+#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */
+#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */
+#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */
+#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */
+#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */
+#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */
+#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */
+#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */
+#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */
+#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */
+#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */
+#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */
+#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */
+#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */
+#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */
+#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */
+#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */
+#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */
+#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */
+#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */
+#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */
+#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */
+#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */
+#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */
+#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */
+#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */
+#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */
+#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */
+#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */
+#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */
+#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */
+#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */
+#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */
+
+/*******************************************************************************
+* FLASHC
+*******************************************************************************/
+
+#define FLASHC_BASE 0x40250000UL
+#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */
+#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */
+
+/*******************************************************************************
+* SRSS
+*******************************************************************************/
+
+#define SRSS_BASE 0x40260000UL
+#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */
+#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */
+#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */
+
+/*******************************************************************************
+* BACKUP
+*******************************************************************************/
+
+#define BACKUP_BASE 0x40270000UL
+#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */
+
+/*******************************************************************************
+* DW
+*******************************************************************************/
+
+#define DW0_BASE 0x40280000UL
+#define DW1_BASE 0x40281000UL
+#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */
+#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */
+#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */
+#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */
+#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */
+#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */
+#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */
+#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */
+#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */
+#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */
+#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */
+#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */
+#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */
+#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */
+#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */
+#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */
+#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */
+#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */
+#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */
+#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */
+#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */
+#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */
+#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */
+#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */
+#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */
+#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */
+#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */
+#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */
+#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */
+#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */
+#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */
+#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */
+#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */
+#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */
+
+/*******************************************************************************
+* EFUSE
+*******************************************************************************/
+
+#define EFUSE_BASE 0x402C0000UL
+#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */
+
+/*******************************************************************************
+* PROFILE
+*******************************************************************************/
+
+#define PROFILE_BASE 0x402D0000UL
+#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */
+#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */
+#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */
+#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */
+#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */
+#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */
+#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */
+#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */
+#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */
+
+/*******************************************************************************
+* HSIOM
+*******************************************************************************/
+
+#define HSIOM_BASE 0x40310000UL
+#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */
+#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */
+#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */
+#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */
+#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */
+#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */
+#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */
+#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */
+#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */
+#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */
+#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */
+#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */
+#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */
+#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */
+#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */
+#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */
+
+/*******************************************************************************
+* GPIO
+*******************************************************************************/
+
+#define GPIO_BASE 0x40320000UL
+#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */
+#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
+#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
+#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
+#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
+#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
+#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
+#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
+#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
+#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
+#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
+#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
+#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
+#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
+#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
+#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
+
+/*******************************************************************************
+* SMARTIO
+*******************************************************************************/
+
+#define SMARTIO_BASE 0x40330000UL
+#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */
+#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */
+#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */
+
+/*******************************************************************************
+* UDB
+*******************************************************************************/
+
+#define UDB_BASE 0x40340000UL
+#define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */
+#define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */
+#define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */
+#define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */
+#define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */
+#define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */
+#define UDB_UDBPAIR1_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[1]) /* 0x40342280 */
+#define UDB_UDBPAIR2_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[0]) /* 0x40342400 */
+#define UDB_UDBPAIR2_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[1]) /* 0x40342480 */
+#define UDB_UDBPAIR3_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[0]) /* 0x40342600 */
+#define UDB_UDBPAIR3_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[1]) /* 0x40342680 */
+#define UDB_UDBPAIR4_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[0]) /* 0x40342800 */
+#define UDB_UDBPAIR4_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[1]) /* 0x40342880 */
+#define UDB_UDBPAIR5_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[0]) /* 0x40342A00 */
+#define UDB_UDBPAIR5_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[1]) /* 0x40342A80 */
+#define UDB_UDBPAIR0_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[0].ROUTE) /* 0x40342100 */
+#define UDB_UDBPAIR1_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[1].ROUTE) /* 0x40342300 */
+#define UDB_UDBPAIR2_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[2].ROUTE) /* 0x40342500 */
+#define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */
+#define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */
+#define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */
+#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */
+#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */
+#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */
+#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */
+#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */
+#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */
+#define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */
+#define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */
+#define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */
+#define UDB_DSI3 ((UDB_DSI_Type*) &UDB->DSI[3]) /* 0x40346180 */
+#define UDB_DSI4 ((UDB_DSI_Type*) &UDB->DSI[4]) /* 0x40346200 */
+#define UDB_DSI5 ((UDB_DSI_Type*) &UDB->DSI[5]) /* 0x40346280 */
+#define UDB_DSI6 ((UDB_DSI_Type*) &UDB->DSI[6]) /* 0x40346300 */
+#define UDB_DSI7 ((UDB_DSI_Type*) &UDB->DSI[7]) /* 0x40346380 */
+#define UDB_DSI8 ((UDB_DSI_Type*) &UDB->DSI[8]) /* 0x40346400 */
+#define UDB_DSI9 ((UDB_DSI_Type*) &UDB->DSI[9]) /* 0x40346480 */
+#define UDB_DSI10 ((UDB_DSI_Type*) &UDB->DSI[10]) /* 0x40346500 */
+#define UDB_DSI11 ((UDB_DSI_Type*) &UDB->DSI[11]) /* 0x40346580 */
+#define UDB_PA0 ((UDB_PA_Type*) &UDB->PA[0]) /* 0x40347000 */
+#define UDB_PA1 ((UDB_PA_Type*) &UDB->PA[1]) /* 0x40347040 */
+#define UDB_PA2 ((UDB_PA_Type*) &UDB->PA[2]) /* 0x40347080 */
+#define UDB_PA3 ((UDB_PA_Type*) &UDB->PA[3]) /* 0x403470C0 */
+#define UDB_PA4 ((UDB_PA_Type*) &UDB->PA[4]) /* 0x40347100 */
+#define UDB_PA5 ((UDB_PA_Type*) &UDB->PA[5]) /* 0x40347140 */
+#define UDB_PA6 ((UDB_PA_Type*) &UDB->PA[6]) /* 0x40347180 */
+#define UDB_PA7 ((UDB_PA_Type*) &UDB->PA[7]) /* 0x403471C0 */
+#define UDB_PA8 ((UDB_PA_Type*) &UDB->PA[8]) /* 0x40347200 */
+#define UDB_PA9 ((UDB_PA_Type*) &UDB->PA[9]) /* 0x40347240 */
+#define UDB_PA10 ((UDB_PA_Type*) &UDB->PA[10]) /* 0x40347280 */
+#define UDB_PA11 ((UDB_PA_Type*) &UDB->PA[11]) /* 0x403472C0 */
+#define UDB_BCTL ((UDB_BCTL_Type*) &UDB->BCTL) /* 0x40347800 */
+#define UDB_UDBIF ((UDB_UDBIF_Type*) &UDB->UDBIF) /* 0x40347900 */
+
+/*******************************************************************************
+* LPCOMP
+*******************************************************************************/
+
+#define LPCOMP_BASE 0x40350000UL
+#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */
+
+/*******************************************************************************
+* CSD
+*******************************************************************************/
+
+#define CSD0_BASE 0x40360000UL
+#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */
+
+/*******************************************************************************
+* TCPWM
+*******************************************************************************/
+
+#define TCPWM0_BASE 0x40380000UL
+#define TCPWM1_BASE 0x40390000UL
+#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */
+#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */
+#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */
+#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */
+#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */
+#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */
+#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */
+#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */
+#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */
+#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */
+#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */
+#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */
+#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */
+#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */
+#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */
+#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */
+#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */
+#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */
+#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */
+#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */
+#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */
+#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */
+#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */
+#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */
+#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */
+#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */
+#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */
+#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */
+#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */
+#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */
+#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */
+#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */
+#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */
+#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */
+
+/*******************************************************************************
+* LCD
+*******************************************************************************/
+
+#define LCD0_BASE 0x403B0000UL
+#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */
+
+/*******************************************************************************
+* USBFS
+*******************************************************************************/
+
+#define USBFS0_BASE 0x403F0000UL
+#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */
+#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */
+#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */
+#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */
+
+/*******************************************************************************
+* SMIF
+*******************************************************************************/
+
+#define SMIF0_BASE 0x40420000UL
+#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */
+#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */
+#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */
+#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */
+#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */
+
+/*******************************************************************************
+* SCB
+*******************************************************************************/
+
+#define SCB0_BASE 0x40610000UL
+#define SCB1_BASE 0x40620000UL
+#define SCB2_BASE 0x40630000UL
+#define SCB3_BASE 0x40640000UL
+#define SCB4_BASE 0x40650000UL
+#define SCB5_BASE 0x40660000UL
+#define SCB6_BASE 0x40670000UL
+#define SCB7_BASE 0x40680000UL
+#define SCB8_BASE 0x40690000UL
+#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */
+#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */
+#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */
+#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */
+#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */
+#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */
+#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */
+#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */
+#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */
+
+/*******************************************************************************
+* CTBM
+*******************************************************************************/
+
+#define CTBM0_BASE 0x41100000UL
+#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */
+
+/*******************************************************************************
+* CTDAC
+*******************************************************************************/
+
+#define CTDAC0_BASE 0x41140000UL
+#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */
+
+/*******************************************************************************
+* SAR
+*******************************************************************************/
+
+#define SAR_BASE 0x411D0000UL
+#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */
+
+/*******************************************************************************
+* PASS
+*******************************************************************************/
+
+#define PASS_BASE 0x411F0000UL
+#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */
+#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */
+
+/*******************************************************************************
+* I2S
+*******************************************************************************/
+
+#define I2S0_BASE 0x42A10000UL
+#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
+
+/*******************************************************************************
+* PDM
+*******************************************************************************/
+
+#define PDM0_BASE 0x42A20000UL
+#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
+
+
+/* Backward compatibility definitions */
+#define CY_SRAM0_BASE CY_SRAM_BASE
+#define CY_SRAM0_SIZE CY_SRAM_SIZE
+#define I2S I2S0
+#define PDM PDM0
+
+/** \} CYB06447BZI-D54 */
+
+#endif /* _CYB06447BZI_D54_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/device_definition.h b/platform/ext/target/psoc64/Device/Include/device_definition.h
new file mode 100644
index 0000000000..981a0e05f8
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/device_definition.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2017-2018 Arm Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file device_definition.h
+ * \brief The structure definitions in this file are exported based on the peripheral
+ * definitions from device_cfg.h.
+ * This retarget file is meant to be used as a helper for baremetal
+ * applications and/or as an example of how to configure the generic
+ * driver structures.
+ */
+
+#ifndef __DEVICE_DEFINITION_H__
+#define __DEVICE_DEFINITION_H__
+
+#include "device_cfg.h"
+
+
+/* ======= Defines peripheral configuration structures ======= */
+/* ======= and includes generic driver headers if necessary ======= */
+/* CMSDK Timer driver structures */
+#ifdef CMSDK_TIMER0_S
+#include "timer_cmsdk_drv.h"
+extern struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S;
+#endif
+#ifdef CMSDK_TIMER0_NS
+#include "timer_cmsdk_drv.h"
+extern struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS;
+#endif
+
+#ifdef CMSDK_TIMER1_S
+#include "timer_cmsdk_drv.h"
+extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S;
+#endif
+#ifdef CMSDK_TIMER1_NS
+#include "timer_cmsdk_drv.h"
+extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS;
+#endif
+
+#endif /* __DEVICE_DEFINITION_H__ */
diff --git a/platform/ext/target/psoc64/Device/Include/gpio_psoc6_01_124_bga.h b/platform/ext/target/psoc64/Device/Include/gpio_psoc6_01_124_bga.h
new file mode 100644
index 0000000000..2816a3c9b2
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/gpio_psoc6_01_124_bga.h
@@ -0,0 +1,2542 @@
+/***************************************************************************//**
+* \file gpio_psoc6_01_124_bga.h
+*
+* \brief
+* PSoC6_01 device GPIO header for 124-BGA package
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _GPIO_PSOC6_01_124_BGA_H_
+#define _GPIO_PSOC6_01_124_BGA_H_
+
+/* Package type */
+enum
+{
+ CY_GPIO_PACKAGE_QFN,
+ CY_GPIO_PACKAGE_BGA,
+ CY_GPIO_PACKAGE_CSP,
+ CY_GPIO_PACKAGE_WLCSP,
+ CY_GPIO_PACKAGE_LQFP,
+ CY_GPIO_PACKAGE_TQFP,
+ CY_GPIO_PACKAGE_SMT,
+};
+
+#define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_BGA
+#define CY_GPIO_PIN_COUNT 124u
+
+/* AMUXBUS Segments */
+enum
+{
+ AMUXBUS_MAIN,
+ AMUXBUS_ADFT0_VDDD,
+ AMUXBUS_NOISY,
+ AMUXBUS_ADFT1_VDDD,
+ AMUXBUS_CSD0,
+ AMUXBUS_VDDIO_1,
+ AMUXBUS_CSD1,
+ AMUXBUS_SAR,
+ AMUXBUS_ANALOG_VDDD,
+ AMUXBUS_ANALOG_VDDA,
+};
+
+/* AMUX Splitter Controls */
+typedef enum
+{
+ AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */
+ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */
+ AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */
+ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */
+ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */
+ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */
+ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */
+ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */
+ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */
+} cy_en_amux_split_t;
+
+/* Port List */
+/* PORT 0 (GPIO) */
+#define P0_0_PORT GPIO_PRT0
+#define P0_0_PIN 0u
+#define P0_0_NUM 0u
+#define P0_0_AMUXSEGMENT AMUXBUS_MAIN
+#define P0_1_PORT GPIO_PRT0
+#define P0_1_PIN 1u
+#define P0_1_NUM 1u
+#define P0_1_AMUXSEGMENT AMUXBUS_MAIN
+#define P0_2_PORT GPIO_PRT0
+#define P0_2_PIN 2u
+#define P0_2_NUM 2u
+#define P0_2_AMUXSEGMENT AMUXBUS_MAIN
+#define P0_3_PORT GPIO_PRT0
+#define P0_3_PIN 3u
+#define P0_3_NUM 3u
+#define P0_3_AMUXSEGMENT AMUXBUS_MAIN
+#define P0_4_PORT GPIO_PRT0
+#define P0_4_PIN 4u
+#define P0_4_NUM 4u
+#define P0_4_AMUXSEGMENT AMUXBUS_MAIN
+#define P0_5_PORT GPIO_PRT0
+#define P0_5_PIN 5u
+#define P0_5_NUM 5u
+#define P0_5_AMUXSEGMENT AMUXBUS_MAIN
+
+/* PORT 1 (GPIO_OVT) */
+#define P1_0_PORT GPIO_PRT1
+#define P1_0_PIN 0u
+#define P1_0_NUM 0u
+#define P1_0_AMUXSEGMENT AMUXBUS_NOISY
+#define P1_1_PORT GPIO_PRT1
+#define P1_1_PIN 1u
+#define P1_1_NUM 1u
+#define P1_1_AMUXSEGMENT AMUXBUS_NOISY
+#define P1_2_PORT GPIO_PRT1
+#define P1_2_PIN 2u
+#define P1_2_NUM 2u
+#define P1_2_AMUXSEGMENT AMUXBUS_NOISY
+#define P1_3_PORT GPIO_PRT1
+#define P1_3_PIN 3u
+#define P1_3_NUM 3u
+#define P1_3_AMUXSEGMENT AMUXBUS_NOISY
+#define P1_4_PORT GPIO_PRT1
+#define P1_4_PIN 4u
+#define P1_4_NUM 4u
+#define P1_4_AMUXSEGMENT AMUXBUS_NOISY
+#define P1_5_PORT GPIO_PRT1
+#define P1_5_PIN 5u
+#define P1_5_NUM 5u
+#define P1_5_AMUXSEGMENT AMUXBUS_NOISY
+
+/* PORT 2 (GPIO) */
+#define P2_0_PORT GPIO_PRT2
+#define P2_0_PIN 0u
+#define P2_0_NUM 0u
+#define P2_0_AMUXSEGMENT AMUXBUS_NOISY
+#define P2_1_PORT GPIO_PRT2
+#define P2_1_PIN 1u
+#define P2_1_NUM 1u
+#define P2_1_AMUXSEGMENT AMUXBUS_NOISY
+#define P2_2_PORT GPIO_PRT2
+#define P2_2_PIN 2u
+#define P2_2_NUM 2u
+#define P2_2_AMUXSEGMENT AMUXBUS_NOISY
+#define P2_3_PORT GPIO_PRT2
+#define P2_3_PIN 3u
+#define P2_3_NUM 3u
+#define P2_3_AMUXSEGMENT AMUXBUS_NOISY
+#define P2_4_PORT GPIO_PRT2
+#define P2_4_PIN 4u
+#define P2_4_NUM 4u
+#define P2_4_AMUXSEGMENT AMUXBUS_NOISY
+#define P2_5_PORT GPIO_PRT2
+#define P2_5_PIN 5u
+#define P2_5_NUM 5u
+#define P2_5_AMUXSEGMENT AMUXBUS_NOISY
+#define P2_6_PORT GPIO_PRT2
+#define P2_6_PIN 6u
+#define P2_6_NUM 6u
+#define P2_6_AMUXSEGMENT AMUXBUS_NOISY
+#define P2_7_PORT GPIO_PRT2
+#define P2_7_PIN 7u
+#define P2_7_NUM 7u
+#define P2_7_AMUXSEGMENT AMUXBUS_NOISY
+
+/* PORT 3 (GPIO) */
+#define P3_0_PORT GPIO_PRT3
+#define P3_0_PIN 0u
+#define P3_0_NUM 0u
+#define P3_0_AMUXSEGMENT AMUXBUS_NOISY
+#define P3_1_PORT GPIO_PRT3
+#define P3_1_PIN 1u
+#define P3_1_NUM 1u
+#define P3_1_AMUXSEGMENT AMUXBUS_NOISY
+#define P3_2_PORT GPIO_PRT3
+#define P3_2_PIN 2u
+#define P3_2_NUM 2u
+#define P3_2_AMUXSEGMENT AMUXBUS_NOISY
+#define P3_3_PORT GPIO_PRT3
+#define P3_3_PIN 3u
+#define P3_3_NUM 3u
+#define P3_3_AMUXSEGMENT AMUXBUS_NOISY
+#define P3_4_PORT GPIO_PRT3
+#define P3_4_PIN 4u
+#define P3_4_NUM 4u
+#define P3_4_AMUXSEGMENT AMUXBUS_NOISY
+#define P3_5_PORT GPIO_PRT3
+#define P3_5_PIN 5u
+#define P3_5_NUM 5u
+#define P3_5_AMUXSEGMENT AMUXBUS_NOISY
+
+/* PORT 4 (GPIO) */
+#define P4_0_PORT GPIO_PRT4
+#define P4_0_PIN 0u
+#define P4_0_NUM 0u
+#define P4_0_AMUXSEGMENT AMUXBUS_NOISY
+#define P4_1_PORT GPIO_PRT4
+#define P4_1_PIN 1u
+#define P4_1_NUM 1u
+#define P4_1_AMUXSEGMENT AMUXBUS_NOISY
+
+/* PORT 5 (GPIO) */
+#define P5_0_PORT GPIO_PRT5
+#define P5_0_PIN 0u
+#define P5_0_NUM 0u
+#define P5_0_AMUXSEGMENT AMUXBUS_CSD0
+#define P5_1_PORT GPIO_PRT5
+#define P5_1_PIN 1u
+#define P5_1_NUM 1u
+#define P5_1_AMUXSEGMENT AMUXBUS_CSD0
+#define P5_2_PORT GPIO_PRT5
+#define P5_2_PIN 2u
+#define P5_2_NUM 2u
+#define P5_2_AMUXSEGMENT AMUXBUS_CSD0
+#define P5_3_PORT GPIO_PRT5
+#define P5_3_PIN 3u
+#define P5_3_NUM 3u
+#define P5_3_AMUXSEGMENT AMUXBUS_CSD0
+#define P5_4_PORT GPIO_PRT5
+#define P5_4_PIN 4u
+#define P5_4_NUM 4u
+#define P5_4_AMUXSEGMENT AMUXBUS_CSD0
+#define P5_5_PORT GPIO_PRT5
+#define P5_5_PIN 5u
+#define P5_5_NUM 5u
+#define P5_5_AMUXSEGMENT AMUXBUS_CSD0
+#define P5_6_PORT GPIO_PRT5
+#define P5_6_PIN 6u
+#define P5_6_NUM 6u
+#define P5_6_AMUXSEGMENT AMUXBUS_CSD0
+#define P5_7_PORT GPIO_PRT5
+#define P5_7_PIN 7u
+#define P5_7_NUM 7u
+#define P5_7_AMUXSEGMENT AMUXBUS_CSD0
+
+/* PORT 6 (GPIO) */
+#define P6_0_PORT GPIO_PRT6
+#define P6_0_PIN 0u
+#define P6_0_NUM 0u
+#define P6_0_AMUXSEGMENT AMUXBUS_CSD0
+#define P6_1_PORT GPIO_PRT6
+#define P6_1_PIN 1u
+#define P6_1_NUM 1u
+#define P6_1_AMUXSEGMENT AMUXBUS_CSD0
+#define P6_2_PORT GPIO_PRT6
+#define P6_2_PIN 2u
+#define P6_2_NUM 2u
+#define P6_2_AMUXSEGMENT AMUXBUS_CSD0
+#define P6_3_PORT GPIO_PRT6
+#define P6_3_PIN 3u
+#define P6_3_NUM 3u
+#define P6_3_AMUXSEGMENT AMUXBUS_CSD0
+#define P6_4_PORT GPIO_PRT6
+#define P6_4_PIN 4u
+#define P6_4_NUM 4u
+#define P6_4_AMUXSEGMENT AMUXBUS_CSD0
+#define P6_5_PORT GPIO_PRT6
+#define P6_5_PIN 5u
+#define P6_5_NUM 5u
+#define P6_5_AMUXSEGMENT AMUXBUS_CSD0
+#define P6_6_PORT GPIO_PRT6
+#define P6_6_PIN 6u
+#define P6_6_NUM 6u
+#define P6_6_AMUXSEGMENT AMUXBUS_CSD0
+#define P6_7_PORT GPIO_PRT6
+#define P6_7_PIN 7u
+#define P6_7_NUM 7u
+#define P6_7_AMUXSEGMENT AMUXBUS_CSD0
+
+/* PORT 7 (GPIO) */
+#define P7_0_PORT GPIO_PRT7
+#define P7_0_PIN 0u
+#define P7_0_NUM 0u
+#define P7_0_AMUXSEGMENT AMUXBUS_CSD0
+#define P7_1_PORT GPIO_PRT7
+#define P7_1_PIN 1u
+#define P7_1_NUM 1u
+#define P7_1_AMUXSEGMENT AMUXBUS_CSD0
+#define P7_2_PORT GPIO_PRT7
+#define P7_2_PIN 2u
+#define P7_2_NUM 2u
+#define P7_2_AMUXSEGMENT AMUXBUS_CSD0
+#define P7_3_PORT GPIO_PRT7
+#define P7_3_PIN 3u
+#define P7_3_NUM 3u
+#define P7_3_AMUXSEGMENT AMUXBUS_CSD0
+#define P7_4_PORT GPIO_PRT7
+#define P7_4_PIN 4u
+#define P7_4_NUM 4u
+#define P7_4_AMUXSEGMENT AMUXBUS_CSD0
+#define P7_5_PORT GPIO_PRT7
+#define P7_5_PIN 5u
+#define P7_5_NUM 5u
+#define P7_5_AMUXSEGMENT AMUXBUS_CSD0
+#define P7_6_PORT GPIO_PRT7
+#define P7_6_PIN 6u
+#define P7_6_NUM 6u
+#define P7_6_AMUXSEGMENT AMUXBUS_CSD0
+#define P7_7_PORT GPIO_PRT7
+#define P7_7_PIN 7u
+#define P7_7_NUM 7u
+#define P7_7_AMUXSEGMENT AMUXBUS_CSD0
+
+/* PORT 8 (GPIO) */
+#define P8_0_PORT GPIO_PRT8
+#define P8_0_PIN 0u
+#define P8_0_NUM 0u
+#define P8_0_AMUXSEGMENT AMUXBUS_CSD0
+#define P8_1_PORT GPIO_PRT8
+#define P8_1_PIN 1u
+#define P8_1_NUM 1u
+#define P8_1_AMUXSEGMENT AMUXBUS_CSD0
+#define P8_2_PORT GPIO_PRT8
+#define P8_2_PIN 2u
+#define P8_2_NUM 2u
+#define P8_2_AMUXSEGMENT AMUXBUS_CSD0
+#define P8_3_PORT GPIO_PRT8
+#define P8_3_PIN 3u
+#define P8_3_NUM 3u
+#define P8_3_AMUXSEGMENT AMUXBUS_CSD0
+#define P8_4_PORT GPIO_PRT8
+#define P8_4_PIN 4u
+#define P8_4_NUM 4u
+#define P8_4_AMUXSEGMENT AMUXBUS_CSD0
+#define P8_5_PORT GPIO_PRT8
+#define P8_5_PIN 5u
+#define P8_5_NUM 5u
+#define P8_5_AMUXSEGMENT AMUXBUS_CSD0
+#define P8_6_PORT GPIO_PRT8
+#define P8_6_PIN 6u
+#define P8_6_NUM 6u
+#define P8_6_AMUXSEGMENT AMUXBUS_CSD0
+#define P8_7_PORT GPIO_PRT8
+#define P8_7_PIN 7u
+#define P8_7_NUM 7u
+#define P8_7_AMUXSEGMENT AMUXBUS_CSD0
+
+/* PORT 9 (GPIO) */
+#define P9_0_PORT GPIO_PRT9
+#define P9_0_PIN 0u
+#define P9_0_NUM 0u
+#define P9_0_AMUXSEGMENT AMUXBUS_SAR
+#define P9_1_PORT GPIO_PRT9
+#define P9_1_PIN 1u
+#define P9_1_NUM 1u
+#define P9_1_AMUXSEGMENT AMUXBUS_SAR
+#define P9_2_PORT GPIO_PRT9
+#define P9_2_PIN 2u
+#define P9_2_NUM 2u
+#define P9_2_AMUXSEGMENT AMUXBUS_SAR
+#define P9_3_PORT GPIO_PRT9
+#define P9_3_PIN 3u
+#define P9_3_NUM 3u
+#define P9_3_AMUXSEGMENT AMUXBUS_SAR
+#define P9_4_PORT GPIO_PRT9
+#define P9_4_PIN 4u
+#define P9_4_NUM 4u
+#define P9_4_AMUXSEGMENT AMUXBUS_SAR
+#define P9_5_PORT GPIO_PRT9
+#define P9_5_PIN 5u
+#define P9_5_NUM 5u
+#define P9_5_AMUXSEGMENT AMUXBUS_SAR
+#define P9_6_PORT GPIO_PRT9
+#define P9_6_PIN 6u
+#define P9_6_NUM 6u
+#define P9_6_AMUXSEGMENT AMUXBUS_SAR
+#define P9_7_PORT GPIO_PRT9
+#define P9_7_PIN 7u
+#define P9_7_NUM 7u
+#define P9_7_AMUXSEGMENT AMUXBUS_SAR
+
+/* PORT 10 (GPIO) */
+#define P10_0_PORT GPIO_PRT10
+#define P10_0_PIN 0u
+#define P10_0_NUM 0u
+#define P10_0_AMUXSEGMENT AMUXBUS_SAR
+#define P10_1_PORT GPIO_PRT10
+#define P10_1_PIN 1u
+#define P10_1_NUM 1u
+#define P10_1_AMUXSEGMENT AMUXBUS_SAR
+#define P10_2_PORT GPIO_PRT10
+#define P10_2_PIN 2u
+#define P10_2_NUM 2u
+#define P10_2_AMUXSEGMENT AMUXBUS_SAR
+#define P10_3_PORT GPIO_PRT10
+#define P10_3_PIN 3u
+#define P10_3_NUM 3u
+#define P10_3_AMUXSEGMENT AMUXBUS_SAR
+#define P10_4_PORT GPIO_PRT10
+#define P10_4_PIN 4u
+#define P10_4_NUM 4u
+#define P10_4_AMUXSEGMENT AMUXBUS_SAR
+#define P10_5_PORT GPIO_PRT10
+#define P10_5_PIN 5u
+#define P10_5_NUM 5u
+#define P10_5_AMUXSEGMENT AMUXBUS_SAR
+#define P10_6_PORT GPIO_PRT10
+#define P10_6_PIN 6u
+#define P10_6_NUM 6u
+#define P10_6_AMUXSEGMENT AMUXBUS_SAR
+#define P10_7_PORT GPIO_PRT10
+#define P10_7_PIN 7u
+#define P10_7_NUM 7u
+#define P10_7_AMUXSEGMENT AMUXBUS_SAR
+
+/* PORT 11 (GPIO) */
+#define P11_0_PORT GPIO_PRT11
+#define P11_0_PIN 0u
+#define P11_0_NUM 0u
+#define P11_0_AMUXSEGMENT AMUXBUS_MAIN
+#define P11_1_PORT GPIO_PRT11
+#define P11_1_PIN 1u
+#define P11_1_NUM 1u
+#define P11_1_AMUXSEGMENT AMUXBUS_MAIN
+#define P11_2_PORT GPIO_PRT11
+#define P11_2_PIN 2u
+#define P11_2_NUM 2u
+#define P11_2_AMUXSEGMENT AMUXBUS_MAIN
+#define P11_3_PORT GPIO_PRT11
+#define P11_3_PIN 3u
+#define P11_3_NUM 3u
+#define P11_3_AMUXSEGMENT AMUXBUS_MAIN
+#define P11_4_PORT GPIO_PRT11
+#define P11_4_PIN 4u
+#define P11_4_NUM 4u
+#define P11_4_AMUXSEGMENT AMUXBUS_MAIN
+#define P11_5_PORT GPIO_PRT11
+#define P11_5_PIN 5u
+#define P11_5_NUM 5u
+#define P11_5_AMUXSEGMENT AMUXBUS_MAIN
+#define P11_6_PORT GPIO_PRT11
+#define P11_6_PIN 6u
+#define P11_6_NUM 6u
+#define P11_6_AMUXSEGMENT AMUXBUS_MAIN
+#define P11_7_PORT GPIO_PRT11
+#define P11_7_PIN 7u
+#define P11_7_NUM 7u
+#define P11_7_AMUXSEGMENT AMUXBUS_MAIN
+
+/* PORT 12 (GPIO) */
+#define P12_0_PORT GPIO_PRT12
+#define P12_0_PIN 0u
+#define P12_0_NUM 0u
+#define P12_0_AMUXSEGMENT AMUXBUS_MAIN
+#define P12_1_PORT GPIO_PRT12
+#define P12_1_PIN 1u
+#define P12_1_NUM 1u
+#define P12_1_AMUXSEGMENT AMUXBUS_MAIN
+#define P12_2_PORT GPIO_PRT12
+#define P12_2_PIN 2u
+#define P12_2_NUM 2u
+#define P12_2_AMUXSEGMENT AMUXBUS_MAIN
+#define P12_3_PORT GPIO_PRT12
+#define P12_3_PIN 3u
+#define P12_3_NUM 3u
+#define P12_3_AMUXSEGMENT AMUXBUS_MAIN
+#define P12_4_PORT GPIO_PRT12
+#define P12_4_PIN 4u
+#define P12_4_NUM 4u
+#define P12_4_AMUXSEGMENT AMUXBUS_MAIN
+#define P12_5_PORT GPIO_PRT12
+#define P12_5_PIN 5u
+#define P12_5_NUM 5u
+#define P12_5_AMUXSEGMENT AMUXBUS_MAIN
+#define P12_6_PORT GPIO_PRT12
+#define P12_6_PIN 6u
+#define P12_6_NUM 6u
+#define P12_6_AMUXSEGMENT AMUXBUS_MAIN
+#define P12_7_PORT GPIO_PRT12
+#define P12_7_PIN 7u
+#define P12_7_NUM 7u
+#define P12_7_AMUXSEGMENT AMUXBUS_MAIN
+
+/* PORT 13 (GPIO) */
+#define P13_0_PORT GPIO_PRT13
+#define P13_0_PIN 0u
+#define P13_0_NUM 0u
+#define P13_0_AMUXSEGMENT AMUXBUS_MAIN
+#define P13_1_PORT GPIO_PRT13
+#define P13_1_PIN 1u
+#define P13_1_NUM 1u
+#define P13_1_AMUXSEGMENT AMUXBUS_MAIN
+#define P13_2_PORT GPIO_PRT13
+#define P13_2_PIN 2u
+#define P13_2_NUM 2u
+#define P13_2_AMUXSEGMENT AMUXBUS_MAIN
+#define P13_3_PORT GPIO_PRT13
+#define P13_3_PIN 3u
+#define P13_3_NUM 3u
+#define P13_3_AMUXSEGMENT AMUXBUS_MAIN
+#define P13_4_PORT GPIO_PRT13
+#define P13_4_PIN 4u
+#define P13_4_NUM 4u
+#define P13_4_AMUXSEGMENT AMUXBUS_MAIN
+#define P13_5_PORT GPIO_PRT13
+#define P13_5_PIN 5u
+#define P13_5_NUM 5u
+#define P13_5_AMUXSEGMENT AMUXBUS_MAIN
+#define P13_6_PORT GPIO_PRT13
+#define P13_6_PIN 6u
+#define P13_6_NUM 6u
+#define P13_6_AMUXSEGMENT AMUXBUS_MAIN
+#define P13_7_PORT GPIO_PRT13
+#define P13_7_PIN 7u
+#define P13_7_NUM 7u
+#define P13_7_AMUXSEGMENT AMUXBUS_MAIN
+
+/* PORT 14 (AUX) */
+#define USBDP_PORT GPIO_PRT14
+#define USBDP_PIN 0u
+#define USBDP_NUM 0u
+#define USBDP_AMUXSEGMENT AMUXBUS_NOISY
+#define USBDM_PORT GPIO_PRT14
+#define USBDM_PIN 1u
+#define USBDM_NUM 1u
+#define USBDM_AMUXSEGMENT AMUXBUS_NOISY
+
+/* Analog Connections */
+#define CSD_CMODPADD_PORT 7u
+#define CSD_CMODPADD_PIN 1u
+#define CSD_CMODPADS_PORT 7u
+#define CSD_CMODPADS_PIN 1u
+#define CSD_CSH_TANKPADD_PORT 7u
+#define CSD_CSH_TANKPADD_PIN 2u
+#define CSD_CSH_TANKPADS_PORT 7u
+#define CSD_CSH_TANKPADS_PIN 2u
+#define CSD_CSHIELDPADS_PORT 7u
+#define CSD_CSHIELDPADS_PIN 7u
+#define CSD_VREF_EXT_PORT 7u
+#define CSD_VREF_EXT_PIN 3u
+#define IOSS_ADFT0_NET_PORT 10u
+#define IOSS_ADFT0_NET_PIN 0u
+#define IOSS_ADFT1_NET_PORT 10u
+#define IOSS_ADFT1_NET_PIN 1u
+#define LPCOMP_INN_COMP0_PORT 5u
+#define LPCOMP_INN_COMP0_PIN 7u
+#define LPCOMP_INN_COMP1_PORT 6u
+#define LPCOMP_INN_COMP1_PIN 3u
+#define LPCOMP_INP_COMP0_PORT 5u
+#define LPCOMP_INP_COMP0_PIN 6u
+#define LPCOMP_INP_COMP1_PORT 6u
+#define LPCOMP_INP_COMP1_PIN 2u
+#define PASS_AREF_EXT_VREF_PORT 9u
+#define PASS_AREF_EXT_VREF_PIN 7u
+#define PASS_CTB_OA0_OUT_10X_PORT 9u
+#define PASS_CTB_OA0_OUT_10X_PIN 2u
+#define PASS_CTB_OA1_OUT_10X_PORT 9u
+#define PASS_CTB_OA1_OUT_10X_PIN 3u
+#define PASS_CTB_PADS0_PORT 9u
+#define PASS_CTB_PADS0_PIN 0u
+#define PASS_CTB_PADS1_PORT 9u
+#define PASS_CTB_PADS1_PIN 1u
+#define PASS_CTB_PADS2_PORT 9u
+#define PASS_CTB_PADS2_PIN 2u
+#define PASS_CTB_PADS3_PORT 9u
+#define PASS_CTB_PADS3_PIN 3u
+#define PASS_CTB_PADS4_PORT 9u
+#define PASS_CTB_PADS4_PIN 4u
+#define PASS_CTB_PADS5_PORT 9u
+#define PASS_CTB_PADS5_PIN 5u
+#define PASS_CTB_PADS6_PORT 9u
+#define PASS_CTB_PADS6_PIN 6u
+#define PASS_CTB_PADS7_PORT 9u
+#define PASS_CTB_PADS7_PIN 7u
+#define PASS_SARMUX_PADS0_PORT 10u
+#define PASS_SARMUX_PADS0_PIN 0u
+#define PASS_SARMUX_PADS1_PORT 10u
+#define PASS_SARMUX_PADS1_PIN 1u
+#define PASS_SARMUX_PADS2_PORT 10u
+#define PASS_SARMUX_PADS2_PIN 2u
+#define PASS_SARMUX_PADS3_PORT 10u
+#define PASS_SARMUX_PADS3_PIN 3u
+#define PASS_SARMUX_PADS4_PORT 10u
+#define PASS_SARMUX_PADS4_PIN 4u
+#define PASS_SARMUX_PADS5_PORT 10u
+#define PASS_SARMUX_PADS5_PIN 5u
+#define PASS_SARMUX_PADS6_PORT 10u
+#define PASS_SARMUX_PADS6_PIN 6u
+#define PASS_SARMUX_PADS7_PORT 10u
+#define PASS_SARMUX_PADS7_PIN 7u
+#define SRSS_ADFT_PIN0_PORT 10u
+#define SRSS_ADFT_PIN0_PIN 0u
+#define SRSS_ADFT_PIN1_PORT 10u
+#define SRSS_ADFT_PIN1_PIN 1u
+#define SRSS_ECO_IN_PORT 12u
+#define SRSS_ECO_IN_PIN 6u
+#define SRSS_ECO_OUT_PORT 12u
+#define SRSS_ECO_OUT_PIN 7u
+#define SRSS_WCO_IN_PORT 0u
+#define SRSS_WCO_IN_PIN 0u
+#define SRSS_WCO_OUT_PORT 0u
+#define SRSS_WCO_OUT_PIN 1u
+
+/* HSIOM Connections */
+typedef enum
+{
+ /* Generic HSIOM connections */
+ HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */
+ HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */
+ HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */
+ HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */
+ HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */
+ HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */
+ HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */
+ HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */
+ HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */
+ HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */
+ HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */
+ HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */
+ HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */
+ HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */
+ HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */
+ HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */
+ HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */
+ HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */
+ HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */
+ HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */
+ HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */
+ HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */
+ HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */
+ HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */
+ HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */
+ HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */
+ HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */
+
+ /* P0.0 */
+ P0_0_GPIO = 0, /* GPIO controls 'out' */
+ P0_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P0_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P0_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P0_0_AMUXA = 4, /* Analog mux bus A */
+ P0_0_AMUXB = 5, /* Analog mux bus B */
+ P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */
+ P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */
+ P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */
+ P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */
+ P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */
+ P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */
+ P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */
+ P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */
+ P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */
+
+ /* P0.1 */
+ P0_1_GPIO = 0, /* GPIO controls 'out' */
+ P0_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P0_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P0_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P0_1_AMUXA = 4, /* Analog mux bus A */
+ P0_1_AMUXB = 5, /* Analog mux bus B */
+ P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */
+ P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */
+ P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */
+ P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */
+ P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */
+ P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */
+ P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */
+ P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */
+ P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */
+
+ /* P0.2 */
+ P0_2_GPIO = 0, /* GPIO controls 'out' */
+ P0_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P0_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P0_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P0_2_AMUXA = 4, /* Analog mux bus A */
+ P0_2_AMUXB = 5, /* Analog mux bus B */
+ P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */
+ P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */
+ P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */
+ P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */
+ P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */
+ P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */
+ P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */
+ P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */
+ P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */
+
+ /* P0.3 */
+ P0_3_GPIO = 0, /* GPIO controls 'out' */
+ P0_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P0_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P0_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P0_3_AMUXA = 4, /* Analog mux bus A */
+ P0_3_AMUXB = 5, /* Analog mux bus B */
+ P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */
+ P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */
+ P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */
+ P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */
+ P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */
+ P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */
+ P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */
+ P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */
+ P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */
+
+ /* P0.4 */
+ P0_4_GPIO = 0, /* GPIO controls 'out' */
+ P0_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P0_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P0_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P0_4_AMUXA = 4, /* Analog mux bus A */
+ P0_4_AMUXB = 5, /* Analog mux bus B */
+ P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */
+ P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */
+ P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */
+ P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */
+ P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */
+ P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */
+ P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */
+ P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */
+ P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */
+
+ /* P0.5 */
+ P0_5_GPIO = 0, /* GPIO controls 'out' */
+ P0_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P0_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P0_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P0_5_AMUXA = 4, /* Analog mux bus A */
+ P0_5_AMUXB = 5, /* Analog mux bus B */
+ P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */
+ P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */
+ P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */
+ P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */
+ P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */
+ P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */
+ P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */
+ P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */
+ P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */
+ P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */
+
+ /* P1.0 */
+ P1_0_GPIO = 0, /* GPIO controls 'out' */
+ P1_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P1_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P1_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P1_0_AMUXA = 4, /* Analog mux bus A */
+ P1_0_AMUXB = 5, /* Analog mux bus B */
+ P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */
+ P1_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */
+ P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */
+ P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */
+ P1_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */
+ P1_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */
+ P1_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:0 */
+ P1_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:0 */
+ P1_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:0 */
+ P1_0_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */
+
+ /* P1.1 */
+ P1_1_GPIO = 0, /* GPIO controls 'out' */
+ P1_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P1_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P1_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P1_1_AMUXA = 4, /* Analog mux bus A */
+ P1_1_AMUXB = 5, /* Analog mux bus B */
+ P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */
+ P1_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */
+ P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */
+ P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */
+ P1_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */
+ P1_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */
+ P1_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:0 */
+ P1_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:0 */
+ P1_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:0 */
+ P1_1_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */
+
+ /* P1.2 */
+ P1_2_GPIO = 0, /* GPIO controls 'out' */
+ P1_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P1_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P1_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P1_2_AMUXA = 4, /* Analog mux bus A */
+ P1_2_AMUXB = 5, /* Analog mux bus B */
+ P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P1_2_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:4 */
+ P1_2_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:1 */
+ P1_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */
+ P1_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */
+ P1_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */
+ P1_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */
+ P1_2_SCB7_UART_RTS = 18, /* Digital Active - scb[7].uart_rts:0 */
+ P1_2_SCB7_SPI_CLK = 20, /* Digital Active - scb[7].spi_clk:0 */
+
+ /* P1.3 */
+ P1_3_GPIO = 0, /* GPIO controls 'out' */
+ P1_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P1_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P1_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P1_3_AMUXA = 4, /* Analog mux bus A */
+ P1_3_AMUXB = 5, /* Analog mux bus B */
+ P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P1_3_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:4 */
+ P1_3_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:1 */
+ P1_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */
+ P1_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */
+ P1_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */
+ P1_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */
+ P1_3_SCB7_UART_CTS = 18, /* Digital Active - scb[7].uart_cts:0 */
+ P1_3_SCB7_SPI_SELECT0 = 20, /* Digital Active - scb[7].spi_select0:0 */
+
+ /* P1.4 */
+ P1_4_GPIO = 0, /* GPIO controls 'out' */
+ P1_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P1_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P1_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P1_4_AMUXA = 4, /* Analog mux bus A */
+ P1_4_AMUXB = 5, /* Analog mux bus B */
+ P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P1_4_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:4 */
+ P1_4_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:1 */
+ P1_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */
+ P1_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */
+ P1_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */
+ P1_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */
+ P1_4_SCB7_SPI_SELECT1 = 20, /* Digital Active - scb[7].spi_select1:0 */
+
+ /* P1.5 */
+ P1_5_GPIO = 0, /* GPIO controls 'out' */
+ P1_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P1_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P1_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P1_5_AMUXA = 4, /* Analog mux bus A */
+ P1_5_AMUXB = 5, /* Analog mux bus B */
+ P1_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P1_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P1_5_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:4 */
+ P1_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */
+ P1_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */
+ P1_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */
+ P1_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */
+ P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */
+ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */
+
+ /* USBDM */
+ USBDM_GPIO = 0, /* GPIO controls 'out' */
+
+ /* USBDP */
+ USBDP_GPIO = 0, /* GPIO controls 'out' */
+
+ /* P2.0 */
+ P2_0_GPIO = 0, /* GPIO controls 'out' */
+ P2_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P2_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P2_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P2_0_AMUXA = 4, /* Analog mux bus A */
+ P2_0_AMUXB = 5, /* Analog mux bus B */
+ P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P2_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:4 */
+ P2_0_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:1 */
+ P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */
+ P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */
+ P2_0_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */
+ P2_0_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */
+ P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */
+ P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */
+ P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */
+ P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */
+ P2_0_BLESS_MXD_DPSLP_RET_SWITCH_HV = 28, /* Digital Deep Sleep - bless.mxd_dpslp_ret_switch_hv */
+
+ /* P2.1 */
+ P2_1_GPIO = 0, /* GPIO controls 'out' */
+ P2_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P2_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P2_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P2_1_AMUXA = 4, /* Analog mux bus A */
+ P2_1_AMUXB = 5, /* Analog mux bus B */
+ P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P2_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:4 */
+ P2_1_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:1 */
+ P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */
+ P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */
+ P2_1_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */
+ P2_1_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */
+ P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */
+ P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */
+ P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */
+ P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */
+ P2_1_BLESS_MXD_DPSLP_RET_LDO_OL_HV = 28, /* Digital Deep Sleep - bless.mxd_dpslp_ret_ldo_ol_hv */
+
+ /* P2.2 */
+ P2_2_GPIO = 0, /* GPIO controls 'out' */
+ P2_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P2_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P2_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P2_2_AMUXA = 4, /* Analog mux bus A */
+ P2_2_AMUXB = 5, /* Analog mux bus B */
+ P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P2_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:4 */
+ P2_2_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:1 */
+ P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */
+ P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */
+ P2_2_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */
+ P2_2_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */
+ P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */
+ P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */
+ P2_2_BLESS_MXD_DPSLP_BUCK_EN = 28, /* Digital Deep Sleep - bless.mxd_dpslp_buck_en */
+
+ /* P2.3 */
+ P2_3_GPIO = 0, /* GPIO controls 'out' */
+ P2_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P2_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P2_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P2_3_AMUXA = 4, /* Analog mux bus A */
+ P2_3_AMUXB = 5, /* Analog mux bus B */
+ P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P2_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:4 */
+ P2_3_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:1 */
+ P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */
+ P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */
+ P2_3_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */
+ P2_3_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */
+ P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */
+ P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */
+ P2_3_BLESS_MXD_DPSLP_RESET_N = 28, /* Digital Deep Sleep - bless.mxd_dpslp_reset_n */
+
+ /* P2.4 */
+ P2_4_GPIO = 0, /* GPIO controls 'out' */
+ P2_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P2_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P2_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P2_4_AMUXA = 4, /* Analog mux bus A */
+ P2_4_AMUXB = 5, /* Analog mux bus B */
+ P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P2_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */
+ P2_4_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:1 */
+ P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */
+ P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */
+ P2_4_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */
+ P2_4_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */
+ P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */
+ P2_4_BLESS_MXD_DPSLP_CLK_EN = 28, /* Digital Deep Sleep - bless.mxd_dpslp_clk_en */
+
+ /* P2.5 */
+ P2_5_GPIO = 0, /* GPIO controls 'out' */
+ P2_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P2_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P2_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P2_5_AMUXA = 4, /* Analog mux bus A */
+ P2_5_AMUXB = 5, /* Analog mux bus B */
+ P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P2_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */
+ P2_5_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:1 */
+ P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */
+ P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */
+ P2_5_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */
+ P2_5_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */
+ P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */
+ P2_5_BLESS_MXD_DPSLP_ISOLATE_N = 28, /* Digital Deep Sleep - bless.mxd_dpslp_isolate_n */
+
+ /* P2.6 */
+ P2_6_GPIO = 0, /* GPIO controls 'out' */
+ P2_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P2_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P2_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P2_6_AMUXA = 4, /* Analog mux bus A */
+ P2_6_AMUXB = 5, /* Analog mux bus B */
+ P2_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P2_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P2_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */
+ P2_6_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:1 */
+ P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */
+ P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */
+ P2_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */
+ P2_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */
+ P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */
+ P2_6_BLESS_MXD_DPSLP_ACT_LDO_EN = 28, /* Digital Deep Sleep - bless.mxd_dpslp_act_ldo_en */
+
+ /* P2.7 */
+ P2_7_GPIO = 0, /* GPIO controls 'out' */
+ P2_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P2_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P2_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P2_7_AMUXA = 4, /* Analog mux bus A */
+ P2_7_AMUXB = 5, /* Analog mux bus B */
+ P2_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P2_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P2_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */
+ P2_7_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:1 */
+ P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */
+ P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */
+ P2_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */
+ P2_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */
+ P2_7_BLESS_MXD_DPSLP_XTAL_EN = 28, /* Digital Deep Sleep - bless.mxd_dpslp_xtal_en */
+
+ /* P3.0 */
+ P3_0_GPIO = 0, /* GPIO controls 'out' */
+ P3_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P3_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P3_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P3_0_AMUXA = 4, /* Analog mux bus A */
+ P3_0_AMUXB = 5, /* Analog mux bus B */
+ P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P3_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:5 */
+ P3_0_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:1 */
+ P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */
+ P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:20 */
+ P3_0_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:0 */
+ P3_0_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:0 */
+ P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */
+ P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */
+ P3_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:1 */
+ P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */
+ P3_0_BLESS_MXD_DPSLP_DIG_LDO_EN = 28, /* Digital Deep Sleep - bless.mxd_dpslp_dig_ldo_en */
+
+ /* P3.1 */
+ P3_1_GPIO = 0, /* GPIO controls 'out' */
+ P3_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P3_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P3_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P3_1_AMUXA = 4, /* Analog mux bus A */
+ P3_1_AMUXB = 5, /* Analog mux bus B */
+ P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P3_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:5 */
+ P3_1_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:1 */
+ P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:21 */
+ P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:21 */
+ P3_1_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:0 */
+ P3_1_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:0 */
+ P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */
+ P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */
+ P3_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:1 */
+ P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */
+ P3_1_BLESS_MXD_ACT_DBUS_RX_EN = 26, /* Digital Active - bless.mxd_act_dbus_rx_en */
+
+ /* P3.2 */
+ P3_2_GPIO = 0, /* GPIO controls 'out' */
+ P3_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P3_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P3_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P3_2_AMUXA = 4, /* Analog mux bus A */
+ P3_2_AMUXB = 5, /* Analog mux bus B */
+ P3_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P3_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P3_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */
+ P3_2_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:1 */
+ P3_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */
+ P3_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */
+ P3_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */
+ P3_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */
+ P3_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:1 */
+ P3_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:1 */
+ P3_2_BLESS_MXD_ACT_DBUS_TX_EN = 26, /* Digital Active - bless.mxd_act_dbus_tx_en */
+
+ /* P3.3 */
+ P3_3_GPIO = 0, /* GPIO controls 'out' */
+ P3_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P3_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P3_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P3_3_AMUXA = 4, /* Analog mux bus A */
+ P3_3_AMUXB = 5, /* Analog mux bus B */
+ P3_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P3_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P3_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */
+ P3_3_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:1 */
+ P3_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */
+ P3_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */
+ P3_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */
+ P3_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */
+ P3_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:1 */
+ P3_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:1 */
+ P3_3_BLESS_MXD_ACT_BPKTCTL = 26, /* Digital Active - bless.mxd_act_bpktctl */
+
+ /* P3.4 */
+ P3_4_GPIO = 0, /* GPIO controls 'out' */
+ P3_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P3_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P3_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P3_4_AMUXA = 4, /* Analog mux bus A */
+ P3_4_AMUXB = 5, /* Analog mux bus B */
+ P3_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P3_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P3_4_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:5 */
+ P3_4_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:1 */
+ P3_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */
+ P3_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */
+ P3_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */
+ P3_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */
+ P3_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:1 */
+ P3_4_BLESS_MXD_ACT_TXD_RXD = 26, /* Digital Active - bless.mxd_act_txd_rxd */
+
+ /* P3.5 */
+ P3_5_GPIO = 0, /* GPIO controls 'out' */
+ P3_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P3_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P3_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P3_5_AMUXA = 4, /* Analog mux bus A */
+ P3_5_AMUXB = 5, /* Analog mux bus B */
+ P3_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P3_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P3_5_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:5 */
+ P3_5_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:1 */
+ P3_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */
+ P3_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */
+ P3_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */
+ P3_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */
+ P3_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:1 */
+ P3_5_BLESS_MXD_DPSLP_RCB_DATA = 26, /* Digital Active - bless.mxd_dpslp_rcb_data */
+
+ /* P4.0 */
+ P4_0_GPIO = 0, /* GPIO controls 'out' */
+ P4_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P4_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P4_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P4_0_AMUXA = 4, /* Analog mux bus A */
+ P4_0_AMUXB = 5, /* Analog mux bus B */
+ P4_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P4_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P4_0_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:5 */
+ P4_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:1 */
+ P4_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */
+ P4_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */
+ P4_0_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */
+ P4_0_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */
+ P4_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:1 */
+ P4_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:1 */
+ P4_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:1 */
+ P4_0_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */
+ P4_0_BLESS_MXD_DPSLP_RCB_CLK = 26, /* Digital Active - bless.mxd_dpslp_rcb_clk */
+
+ /* P4.1 */
+ P4_1_GPIO = 0, /* GPIO controls 'out' */
+ P4_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P4_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P4_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P4_1_AMUXA = 4, /* Analog mux bus A */
+ P4_1_AMUXB = 5, /* Analog mux bus B */
+ P4_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P4_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P4_1_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:5 */
+ P4_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:1 */
+ P4_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */
+ P4_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */
+ P4_1_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */
+ P4_1_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */
+ P4_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:1 */
+ P4_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:1 */
+ P4_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:1 */
+ P4_1_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */
+ P4_1_BLESS_MXD_DPSLP_RCB_LE = 26, /* Digital Active - bless.mxd_dpslp_rcb_le */
+
+ /* P5.0 */
+ P5_0_GPIO = 0, /* GPIO controls 'out' */
+ P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_0_AMUXA = 4, /* Analog mux bus A */
+ P5_0_AMUXB = 5, /* Analog mux bus B */
+ P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */
+ P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */
+ P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */
+ P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */
+ P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */
+ P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */
+ P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */
+ P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */
+ P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */
+ P5_0_AUDIOSS_CLK_I2S_IF = 22, /* Digital Active - audioss.clk_i2s_if */
+ P5_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:0 */
+ P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */
+
+ /* P5.1 */
+ P5_1_GPIO = 0, /* GPIO controls 'out' */
+ P5_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_1_AMUXA = 4, /* Analog mux bus A */
+ P5_1_AMUXB = 5, /* Analog mux bus B */
+ P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */
+ P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */
+ P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */
+ P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */
+ P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */
+ P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */
+ P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */
+ P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */
+ P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */
+ P5_1_AUDIOSS_TX_SCK = 22, /* Digital Active - audioss.tx_sck */
+ P5_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:0 */
+ P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */
+
+ /* P5.2 */
+ P5_2_GPIO = 0, /* GPIO controls 'out' */
+ P5_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_2_AMUXA = 4, /* Analog mux bus A */
+ P5_2_AMUXB = 5, /* Analog mux bus B */
+ P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */
+ P5_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */
+ P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */
+ P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */
+ P5_2_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */
+ P5_2_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */
+ P5_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */
+ P5_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */
+ P5_2_AUDIOSS_TX_WS = 22, /* Digital Active - audioss.tx_ws */
+ P5_2_AUDIOSS0_TX_WS = 22, /* Digital Active - audioss[0].tx_ws:0 */
+
+ /* P5.3 */
+ P5_3_GPIO = 0, /* GPIO controls 'out' */
+ P5_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_3_AMUXA = 4, /* Analog mux bus A */
+ P5_3_AMUXB = 5, /* Analog mux bus B */
+ P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:0 */
+ P5_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */
+ P5_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */
+ P5_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */
+ P5_3_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */
+ P5_3_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */
+ P5_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */
+ P5_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */
+ P5_3_AUDIOSS_TX_SDO = 22, /* Digital Active - audioss.tx_sdo */
+ P5_3_AUDIOSS0_TX_SDO = 22, /* Digital Active - audioss[0].tx_sdo:0 */
+
+ /* P5.4 */
+ P5_4_GPIO = 0, /* GPIO controls 'out' */
+ P5_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_4_AMUXA = 4, /* Analog mux bus A */
+ P5_4_AMUXB = 5, /* Analog mux bus B */
+ P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */
+ P5_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */
+ P5_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */
+ P5_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */
+ P5_4_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */
+ P5_4_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */
+ P5_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */
+ P5_4_AUDIOSS_RX_SCK = 22, /* Digital Active - audioss.rx_sck */
+ P5_4_AUDIOSS0_RX_SCK = 22, /* Digital Active - audioss[0].rx_sck:0 */
+
+ /* P5.5 */
+ P5_5_GPIO = 0, /* GPIO controls 'out' */
+ P5_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_5_AMUXA = 4, /* Analog mux bus A */
+ P5_5_AMUXB = 5, /* Analog mux bus B */
+ P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:0 */
+ P5_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */
+ P5_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */
+ P5_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */
+ P5_5_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */
+ P5_5_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */
+ P5_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */
+ P5_5_AUDIOSS_RX_WS = 22, /* Digital Active - audioss.rx_ws */
+ P5_5_AUDIOSS0_RX_WS = 22, /* Digital Active - audioss[0].rx_ws:0 */
+
+ /* P5.6 */
+ P5_6_GPIO = 0, /* GPIO controls 'out' */
+ P5_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_6_AMUXA = 4, /* Analog mux bus A */
+ P5_6_AMUXB = 5, /* Analog mux bus B */
+ P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */
+ P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */
+ P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */
+ P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */
+ P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */
+ P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */
+ P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */
+ P5_6_AUDIOSS_RX_SDI = 22, /* Digital Active - audioss.rx_sdi */
+ P5_6_AUDIOSS0_RX_SDI = 22, /* Digital Active - audioss[0].rx_sdi:0 */
+
+ /* P5.7 */
+ P5_7_GPIO = 0, /* GPIO controls 'out' */
+ P5_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_7_AMUXA = 4, /* Analog mux bus A */
+ P5_7_AMUXB = 5, /* Analog mux bus B */
+ P5_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:0 */
+ P5_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */
+ P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */
+ P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */
+ P5_7_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */
+ P5_7_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */
+ P5_7_SCB3_SPI_SELECT3 = 20, /* Digital Active - scb[3].spi_select3:0 */
+
+ /* P6.0 */
+ P6_0_GPIO = 0, /* GPIO controls 'out' */
+ P6_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_0_AMUXA = 4, /* Analog mux bus A */
+ P6_0_AMUXB = 5, /* Analog mux bus B */
+ P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */
+ P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */
+ P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */
+ P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */
+ P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */
+ P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */
+ P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */
+ P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */
+ P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */
+ P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */
+ P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */
+ P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */
+
+ /* P6.1 */
+ P6_1_GPIO = 0, /* GPIO controls 'out' */
+ P6_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_1_AMUXA = 4, /* Analog mux bus A */
+ P6_1_AMUXB = 5, /* Analog mux bus B */
+ P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */
+ P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */
+ P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */
+ P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */
+ P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */
+ P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */
+ P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */
+ P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */
+ P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */
+ P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */
+ P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */
+ P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */
+
+ /* P6.2 */
+ P6_2_GPIO = 0, /* GPIO controls 'out' */
+ P6_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_2_AMUXA = 4, /* Analog mux bus A */
+ P6_2_AMUXB = 5, /* Analog mux bus B */
+ P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */
+ P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */
+ P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */
+ P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */
+ P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */
+ P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */
+ P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */
+ P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */
+ P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */
+
+ /* P6.3 */
+ P6_3_GPIO = 0, /* GPIO controls 'out' */
+ P6_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_3_AMUXA = 4, /* Analog mux bus A */
+ P6_3_AMUXB = 5, /* Analog mux bus B */
+ P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */
+ P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */
+ P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */
+ P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */
+ P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */
+ P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */
+ P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */
+ P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */
+ P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */
+
+ /* P6.4 */
+ P6_4_GPIO = 0, /* GPIO controls 'out' */
+ P6_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_4_AMUXA = 4, /* Analog mux bus A */
+ P6_4_AMUXB = 5, /* Analog mux bus B */
+ P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */
+ P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */
+ P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */
+ P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */
+ P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */
+ P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */
+ P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */
+ P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */
+ P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */
+ P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */
+ P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */
+ P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */
+ P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */
+ P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */
+ P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */
+
+ /* P6.5 */
+ P6_5_GPIO = 0, /* GPIO controls 'out' */
+ P6_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_5_AMUXA = 4, /* Analog mux bus A */
+ P6_5_AMUXB = 5, /* Analog mux bus B */
+ P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */
+ P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */
+ P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */
+ P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */
+ P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */
+ P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */
+ P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */
+ P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */
+ P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */
+ P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */
+ P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */
+ P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */
+ P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */
+ P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */
+ P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */
+
+ /* P6.6 */
+ P6_6_GPIO = 0, /* GPIO controls 'out' */
+ P6_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_6_AMUXA = 4, /* Analog mux bus A */
+ P6_6_AMUXB = 5, /* Analog mux bus B */
+ P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */
+ P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */
+ P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */
+ P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */
+ P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */
+ P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */
+ P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */
+ P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */
+ P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */
+ P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */
+
+ /* P6.7 */
+ P6_7_GPIO = 0, /* GPIO controls 'out' */
+ P6_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_7_AMUXA = 4, /* Analog mux bus A */
+ P6_7_AMUXB = 5, /* Analog mux bus B */
+ P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */
+ P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */
+ P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */
+ P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */
+ P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */
+ P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */
+ P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */
+ P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */
+ P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */
+ P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */
+
+ /* P7.0 */
+ P7_0_GPIO = 0, /* GPIO controls 'out' */
+ P7_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_0_AMUXA = 4, /* Analog mux bus A */
+ P7_0_AMUXB = 5, /* Analog mux bus B */
+ P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */
+ P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */
+ P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */
+ P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */
+ P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */
+ P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */
+ P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */
+ P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */
+ P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */
+ P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */
+ P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */
+
+ /* P7.1 */
+ P7_1_GPIO = 0, /* GPIO controls 'out' */
+ P7_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_1_AMUXA = 4, /* Analog mux bus A */
+ P7_1_AMUXB = 5, /* Analog mux bus B */
+ P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */
+ P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */
+ P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */
+ P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */
+ P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */
+ P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */
+ P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */
+ P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */
+ P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */
+ P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */
+
+ /* P7.2 */
+ P7_2_GPIO = 0, /* GPIO controls 'out' */
+ P7_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_2_AMUXA = 4, /* Analog mux bus A */
+ P7_2_AMUXB = 5, /* Analog mux bus B */
+ P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */
+ P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */
+ P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */
+ P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */
+ P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */
+ P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */
+ P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */
+ P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */
+
+ /* P7.3 */
+ P7_3_GPIO = 0, /* GPIO controls 'out' */
+ P7_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_3_AMUXA = 4, /* Analog mux bus A */
+ P7_3_AMUXB = 5, /* Analog mux bus B */
+ P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */
+ P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */
+ P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */
+ P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */
+ P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */
+ P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */
+ P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */
+ P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */
+
+ /* P7.4 */
+ P7_4_GPIO = 0, /* GPIO controls 'out' */
+ P7_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_4_AMUXA = 4, /* Analog mux bus A */
+ P7_4_AMUXB = 5, /* Analog mux bus B */
+ P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */
+ P7_4_TCPWM1_LINE14 = 9, /* Digital Active - tcpwm[1].line[14]:0 */
+ P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */
+ P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */
+ P7_4_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */
+ P7_4_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */
+ P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */
+ P7_4_BLESS_EXT_LNA_RX_CTL_OUT = 26, /* Digital Active - bless.ext_lna_rx_ctl_out */
+ P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */
+
+ /* P7.5 */
+ P7_5_GPIO = 0, /* GPIO controls 'out' */
+ P7_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_5_AMUXA = 4, /* Analog mux bus A */
+ P7_5_AMUXB = 5, /* Analog mux bus B */
+ P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:1 */
+ P7_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */
+ P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */
+ P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */
+ P7_5_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */
+ P7_5_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */
+ P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */
+ P7_5_BLESS_EXT_PA_TX_CTL_OUT = 26, /* Digital Active - bless.ext_pa_tx_ctl_out */
+ P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */
+
+ /* P7.6 */
+ P7_6_GPIO = 0, /* GPIO controls 'out' */
+ P7_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_6_AMUXA = 4, /* Analog mux bus A */
+ P7_6_AMUXB = 5, /* Analog mux bus B */
+ P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */
+ P7_6_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:0 */
+ P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */
+ P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */
+ P7_6_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */
+ P7_6_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */
+ P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */
+ P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT = 26, /* Digital Active - bless.ext_pa_lna_chip_en_out */
+ P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */
+
+ /* P7.7 */
+ P7_7_GPIO = 0, /* GPIO controls 'out' */
+ P7_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_7_AMUXA = 4, /* Analog mux bus A */
+ P7_7_AMUXB = 5, /* Analog mux bus B */
+ P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */
+ P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */
+ P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */
+ P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */
+ P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */
+ P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */
+ P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */
+ P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */
+ P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */
+
+ /* P8.0 */
+ P8_0_GPIO = 0, /* GPIO controls 'out' */
+ P8_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_0_AMUXA = 4, /* Analog mux bus A */
+ P8_0_AMUXB = 5, /* Analog mux bus B */
+ P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */
+ P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */
+ P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */
+ P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */
+ P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */
+ P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */
+ P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */
+ P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */
+ P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */
+ P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */
+
+ /* P8.1 */
+ P8_1_GPIO = 0, /* GPIO controls 'out' */
+ P8_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_1_AMUXA = 4, /* Analog mux bus A */
+ P8_1_AMUXB = 5, /* Analog mux bus B */
+ P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */
+ P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */
+ P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */
+ P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */
+ P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */
+ P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */
+ P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */
+ P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */
+ P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */
+ P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */
+
+ /* P8.2 */
+ P8_2_GPIO = 0, /* GPIO controls 'out' */
+ P8_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_2_AMUXA = 4, /* Analog mux bus A */
+ P8_2_AMUXB = 5, /* Analog mux bus B */
+ P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */
+ P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */
+ P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */
+ P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */
+ P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */
+ P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */
+ P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */
+ P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */
+ P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */
+
+ /* P8.3 */
+ P8_3_GPIO = 0, /* GPIO controls 'out' */
+ P8_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_3_AMUXA = 4, /* Analog mux bus A */
+ P8_3_AMUXB = 5, /* Analog mux bus B */
+ P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */
+ P8_3_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */
+ P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */
+ P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */
+ P8_3_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */
+ P8_3_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */
+ P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */
+ P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */
+ P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */
+
+ /* P8.4 */
+ P8_4_GPIO = 0, /* GPIO controls 'out' */
+ P8_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_4_AMUXA = 4, /* Analog mux bus A */
+ P8_4_AMUXB = 5, /* Analog mux bus B */
+ P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */
+ P8_4_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:0 */
+ P8_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */
+ P8_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */
+ P8_4_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */
+ P8_4_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */
+ P8_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:0 */
+
+ /* P8.5 */
+ P8_5_GPIO = 0, /* GPIO controls 'out' */
+ P8_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_5_AMUXA = 4, /* Analog mux bus A */
+ P8_5_AMUXB = 5, /* Analog mux bus B */
+ P8_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */
+ P8_5_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:0 */
+ P8_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */
+ P8_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */
+ P8_5_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */
+ P8_5_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */
+ P8_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:0 */
+
+ /* P8.6 */
+ P8_6_GPIO = 0, /* GPIO controls 'out' */
+ P8_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_6_AMUXA = 4, /* Analog mux bus A */
+ P8_6_AMUXB = 5, /* Analog mux bus B */
+ P8_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */
+ P8_6_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:0 */
+ P8_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */
+ P8_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */
+ P8_6_LCD_COM60 = 12, /* Digital Deep Sleep - lcd.com[60]:0 */
+ P8_6_LCD_SEG60 = 13, /* Digital Deep Sleep - lcd.seg[60]:0 */
+ P8_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:0 */
+
+ /* P8.7 */
+ P8_7_GPIO = 0, /* GPIO controls 'out' */
+ P8_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_7_AMUXA = 4, /* Analog mux bus A */
+ P8_7_AMUXB = 5, /* Analog mux bus B */
+ P8_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */
+ P8_7_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:0 */
+ P8_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */
+ P8_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */
+ P8_7_LCD_COM61 = 12, /* Digital Deep Sleep - lcd.com[61]:0 */
+ P8_7_LCD_SEG61 = 13, /* Digital Deep Sleep - lcd.seg[61]:0 */
+ P8_7_SCB3_SPI_SELECT2 = 20, /* Digital Active - scb[3].spi_select2:0 */
+
+ /* P9.0 */
+ P9_0_GPIO = 0, /* GPIO controls 'out' */
+ P9_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_0_AMUXA = 4, /* Analog mux bus A */
+ P9_0_AMUXB = 5, /* Analog mux bus B */
+ P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */
+ P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */
+ P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */
+ P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */
+ P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */
+ P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */
+ P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */
+ P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */
+ P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */
+ P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */
+ P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */
+
+ /* P9.1 */
+ P9_1_GPIO = 0, /* GPIO controls 'out' */
+ P9_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_1_AMUXA = 4, /* Analog mux bus A */
+ P9_1_AMUXB = 5, /* Analog mux bus B */
+ P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */
+ P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */
+ P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */
+ P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */
+ P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */
+ P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */
+ P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */
+ P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */
+ P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */
+ P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */
+ P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */
+ P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */
+
+ /* P9.2 */
+ P9_2_GPIO = 0, /* GPIO controls 'out' */
+ P9_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_2_AMUXA = 4, /* Analog mux bus A */
+ P9_2_AMUXB = 5, /* Analog mux bus B */
+ P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */
+ P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */
+ P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */
+ P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */
+ P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */
+ P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */
+ P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */
+ P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */
+ P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */
+ P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */
+
+ /* P9.3 */
+ P9_3_GPIO = 0, /* GPIO controls 'out' */
+ P9_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_3_AMUXA = 4, /* Analog mux bus A */
+ P9_3_AMUXB = 5, /* Analog mux bus B */
+ P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */
+ P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */
+ P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */
+ P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */
+ P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */
+ P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */
+ P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */
+ P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */
+ P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */
+ P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */
+ P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */
+
+ /* P9.4 */
+ P9_4_GPIO = 0, /* GPIO controls 'out' */
+ P9_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_4_AMUXA = 4, /* Analog mux bus A */
+ P9_4_AMUXB = 5, /* Analog mux bus B */
+ P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_4_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:5 */
+ P9_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */
+ P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:66 */
+ P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:66 */
+ P9_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:1 */
+ P9_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:1 */
+ P9_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:0 */
+
+ /* P9.5 */
+ P9_5_GPIO = 0, /* GPIO controls 'out' */
+ P9_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_5_AMUXA = 4, /* Analog mux bus A */
+ P9_5_AMUXB = 5, /* Analog mux bus B */
+ P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_5_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:5 */
+ P9_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:2 */
+ P9_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:67 */
+ P9_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:67 */
+ P9_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:1 */
+ P9_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:1 */
+ P9_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:0 */
+
+ /* P9.6 */
+ P9_6_GPIO = 0, /* GPIO controls 'out' */
+ P9_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_6_AMUXA = 4, /* Analog mux bus A */
+ P9_6_AMUXB = 5, /* Analog mux bus B */
+ P9_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_6_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */
+ P9_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:2 */
+ P9_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:68 */
+ P9_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:68 */
+ P9_6_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:1 */
+ P9_6_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:1 */
+ P9_6_SCB2_SPI_SELECT3 = 20, /* Digital Active - scb[2].spi_select3:0 */
+
+ /* P9.7 */
+ P9_7_GPIO = 0, /* GPIO controls 'out' */
+ P9_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_7_AMUXA = 4, /* Analog mux bus A */
+ P9_7_AMUXB = 5, /* Analog mux bus B */
+ P9_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_7_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */
+ P9_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */
+ P9_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:69 */
+ P9_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:69 */
+ P9_7_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:1 */
+ P9_7_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:1 */
+
+ /* P10.0 */
+ P10_0_GPIO = 0, /* GPIO controls 'out' */
+ P10_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_0_AMUXA = 4, /* Analog mux bus A */
+ P10_0_AMUXB = 5, /* Analog mux bus B */
+ P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */
+ P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */
+ P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */
+ P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */
+ P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */
+ P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */
+ P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */
+ P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */
+ P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */
+ P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */
+ P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */
+
+ /* P10.1 */
+ P10_1_GPIO = 0, /* GPIO controls 'out' */
+ P10_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_1_AMUXA = 4, /* Analog mux bus A */
+ P10_1_AMUXB = 5, /* Analog mux bus B */
+ P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */
+ P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */
+ P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */
+ P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */
+ P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */
+ P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */
+ P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */
+ P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */
+ P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */
+ P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */
+ P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */
+
+ /* P10.2 */
+ P10_2_GPIO = 0, /* GPIO controls 'out' */
+ P10_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_2_AMUXA = 4, /* Analog mux bus A */
+ P10_2_AMUXB = 5, /* Analog mux bus B */
+ P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:2 */
+ P10_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:0 */
+ P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:72 */
+ P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:72 */
+ P10_2_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:1 */
+ P10_2_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:1 */
+ P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */
+ P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */
+ P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */
+
+ /* P10.3 */
+ P10_3_GPIO = 0, /* GPIO controls 'out' */
+ P10_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_3_AMUXA = 4, /* Analog mux bus A */
+ P10_3_AMUXB = 5, /* Analog mux bus B */
+ P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:2 */
+ P10_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */
+ P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:73 */
+ P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:73 */
+ P10_3_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:1 */
+ P10_3_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:1 */
+ P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */
+ P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */
+ P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */
+
+ /* P10.4 */
+ P10_4_GPIO = 0, /* GPIO controls 'out' */
+ P10_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_4_AMUXA = 4, /* Analog mux bus A */
+ P10_4_AMUXB = 5, /* Analog mux bus B */
+ P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */
+ P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */
+ P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */
+ P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */
+ P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */
+ P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */
+ P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */
+ P10_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:0 */
+ P10_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:0:0 */
+
+ /* P10.5 */
+ P10_5_GPIO = 0, /* GPIO controls 'out' */
+ P10_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_5_AMUXA = 4, /* Analog mux bus A */
+ P10_5_AMUXB = 5, /* Analog mux bus B */
+ P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */
+ P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */
+ P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */
+ P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */
+ P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */
+ P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */
+ P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */
+ P10_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:0 */
+ P10_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:0:0 */
+
+ /* P10.6 */
+ P10_6_GPIO = 0, /* GPIO controls 'out' */
+ P10_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_6_AMUXA = 4, /* Analog mux bus A */
+ P10_6_AMUXB = 5, /* Analog mux bus B */
+ P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */
+ P10_6_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */
+ P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:76 */
+ P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:76 */
+ P10_6_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:1 */
+ P10_6_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:1 */
+ P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */
+
+ /* P10.7 */
+ P10_7_GPIO = 0, /* GPIO controls 'out' */
+ P10_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_7_AMUXA = 4, /* Analog mux bus A */
+ P10_7_AMUXB = 5, /* Analog mux bus B */
+ P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */
+ P10_7_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:2 */
+ P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:77 */
+ P10_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:77 */
+ P10_7_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:1 */
+ P10_7_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:1 */
+
+ /* P11.0 */
+ P11_0_GPIO = 0, /* GPIO controls 'out' */
+ P11_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_0_AMUXA = 4, /* Analog mux bus A */
+ P11_0_AMUXB = 5, /* Analog mux bus B */
+ P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */
+ P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */
+ P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */
+ P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */
+ P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */
+ P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */
+ P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */
+ P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */
+ P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */
+ P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */
+ P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */
+
+ /* P11.1 */
+ P11_1_GPIO = 0, /* GPIO controls 'out' */
+ P11_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_1_AMUXA = 4, /* Analog mux bus A */
+ P11_1_AMUXB = 5, /* Analog mux bus B */
+ P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */
+ P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */
+ P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */
+ P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */
+ P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */
+ P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */
+ P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */
+ P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */
+ P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */
+ P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */
+ P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */
+
+ /* P11.2 */
+ P11_2_GPIO = 0, /* GPIO controls 'out' */
+ P11_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_2_AMUXA = 4, /* Analog mux bus A */
+ P11_2_AMUXB = 5, /* Analog mux bus B */
+ P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */
+ P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */
+ P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */
+ P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */
+ P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */
+ P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */
+ P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */
+ P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */
+ P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */
+
+ /* P11.3 */
+ P11_3_GPIO = 0, /* GPIO controls 'out' */
+ P11_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_3_AMUXA = 4, /* Analog mux bus A */
+ P11_3_AMUXB = 5, /* Analog mux bus B */
+ P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */
+ P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */
+ P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */
+ P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */
+ P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */
+ P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */
+ P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */
+ P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */
+ P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */
+ P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */
+
+ /* P11.4 */
+ P11_4_GPIO = 0, /* GPIO controls 'out' */
+ P11_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_4_AMUXA = 4, /* Analog mux bus A */
+ P11_4_AMUXB = 5, /* Analog mux bus B */
+ P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */
+ P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */
+ P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */
+ P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */
+ P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */
+ P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */
+ P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */
+ P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */
+ P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */
+
+ /* P11.5 */
+ P11_5_GPIO = 0, /* GPIO controls 'out' */
+ P11_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_5_AMUXA = 4, /* Analog mux bus A */
+ P11_5_AMUXB = 5, /* Analog mux bus B */
+ P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */
+ P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */
+ P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */
+ P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */
+ P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */
+ P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */
+ P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */
+ P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */
+
+ /* P11.6 */
+ P11_6_GPIO = 0, /* GPIO controls 'out' */
+ P11_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_6_AMUXA = 4, /* Analog mux bus A */
+ P11_6_AMUXB = 5, /* Analog mux bus B */
+ P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */
+ P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */
+ P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */
+ P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */
+ P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */
+ P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */
+
+ /* P11.7 */
+ P11_7_GPIO = 0, /* GPIO controls 'out' */
+ P11_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_7_AMUXA = 4, /* Analog mux bus A */
+ P11_7_AMUXB = 5, /* Analog mux bus B */
+ P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */
+
+ /* P12.0 */
+ P12_0_GPIO = 0, /* GPIO controls 'out' */
+ P12_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_0_AMUXA = 4, /* Analog mux bus A */
+ P12_0_AMUXB = 5, /* Analog mux bus B */
+ P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:3 */
+ P12_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */
+ P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:85 */
+ P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:85 */
+ P12_0_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:1 */
+ P12_0_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:1 */
+ P12_0_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */
+ P12_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */
+ P12_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */
+ P12_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */
+ P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */
+
+ /* P12.1 */
+ P12_1_GPIO = 0, /* GPIO controls 'out' */
+ P12_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_1_AMUXA = 4, /* Analog mux bus A */
+ P12_1_AMUXB = 5, /* Analog mux bus B */
+ P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:3 */
+ P12_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */
+ P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:86 */
+ P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:86 */
+ P12_1_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:1 */
+ P12_1_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:1 */
+ P12_1_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */
+ P12_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */
+ P12_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */
+ P12_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */
+ P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */
+
+ /* P12.2 */
+ P12_2_GPIO = 0, /* GPIO controls 'out' */
+ P12_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_2_AMUXA = 4, /* Analog mux bus A */
+ P12_2_AMUXB = 5, /* Analog mux bus B */
+ P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:3 */
+ P12_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */
+ P12_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:87 */
+ P12_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:87 */
+ P12_2_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:1 */
+ P12_2_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:1 */
+ P12_2_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */
+ P12_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */
+ P12_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */
+
+ /* P12.3 */
+ P12_3_GPIO = 0, /* GPIO controls 'out' */
+ P12_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_3_AMUXA = 4, /* Analog mux bus A */
+ P12_3_AMUXB = 5, /* Analog mux bus B */
+ P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:3 */
+ P12_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */
+ P12_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:88 */
+ P12_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:88 */
+ P12_3_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:1 */
+ P12_3_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:1 */
+ P12_3_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */
+ P12_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */
+ P12_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */
+
+ /* P12.4 */
+ P12_4_GPIO = 0, /* GPIO controls 'out' */
+ P12_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_4_AMUXA = 4, /* Analog mux bus A */
+ P12_4_AMUXB = 5, /* Analog mux bus B */
+ P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:3 */
+ P12_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */
+ P12_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:89 */
+ P12_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:89 */
+ P12_4_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:1 */
+ P12_4_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:1 */
+ P12_4_SMIF_SPI_SELECT3 = 17, /* Digital Active - smif.spi_select3 */
+ P12_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */
+ P12_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:1 */
+ P12_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:1:0 */
+
+ /* P12.5 */
+ P12_5_GPIO = 0, /* GPIO controls 'out' */
+ P12_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_5_AMUXA = 4, /* Analog mux bus A */
+ P12_5_AMUXB = 5, /* Analog mux bus B */
+ P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:3 */
+ P12_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */
+ P12_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:90 */
+ P12_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:90 */
+ P12_5_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:1 */
+ P12_5_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:1 */
+ P12_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:0 */
+ P12_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:1 */
+ P12_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:1:0 */
+
+ /* P12.6 */
+ P12_6_GPIO = 0, /* GPIO controls 'out' */
+ P12_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_6_AMUXA = 4, /* Analog mux bus A */
+ P12_6_AMUXB = 5, /* Analog mux bus B */
+ P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */
+ P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */
+ P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */
+ P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */
+ P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */
+ P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */
+ P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */
+
+ /* P12.7 */
+ P12_7_GPIO = 0, /* GPIO controls 'out' */
+ P12_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_7_AMUXA = 4, /* Analog mux bus A */
+ P12_7_AMUXB = 5, /* Analog mux bus B */
+ P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */
+ P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */
+ P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */
+ P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */
+ P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */
+ P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */
+
+ /* P13.0 */
+ P13_0_GPIO = 0, /* GPIO controls 'out' */
+ P13_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P13_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P13_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P13_0_AMUXA = 4, /* Analog mux bus A */
+ P13_0_AMUXB = 5, /* Analog mux bus B */
+ P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P13_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */
+ P13_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:1 */
+ P13_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:93 */
+ P13_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:93 */
+ P13_0_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:1 */
+ P13_0_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:1 */
+ P13_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:1 */
+ P13_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:1 */
+ P13_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:1 */
+ P13_0_PERI_TR_IO_INPUT26 = 24, /* Digital Active - peri.tr_io_input[26]:0 */
+
+ /* P13.1 */
+ P13_1_GPIO = 0, /* GPIO controls 'out' */
+ P13_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P13_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P13_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P13_1_AMUXA = 4, /* Analog mux bus A */
+ P13_1_AMUXB = 5, /* Analog mux bus B */
+ P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P13_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */
+ P13_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */
+ P13_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:94 */
+ P13_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:94 */
+ P13_1_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:1 */
+ P13_1_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:1 */
+ P13_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */
+ P13_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */
+ P13_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:1 */
+ P13_1_PERI_TR_IO_INPUT27 = 24, /* Digital Active - peri.tr_io_input[27]:0 */
+
+ /* P13.2 */
+ P13_2_GPIO = 0, /* GPIO controls 'out' */
+ P13_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P13_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P13_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P13_2_AMUXA = 4, /* Analog mux bus A */
+ P13_2_AMUXB = 5, /* Analog mux bus B */
+ P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P13_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */
+ P13_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:1 */
+ P13_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:95 */
+ P13_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:95 */
+ P13_2_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:1 */
+ P13_2_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:1 */
+ P13_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:1 */
+ P13_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:1 */
+
+ /* P13.3 */
+ P13_3_GPIO = 0, /* GPIO controls 'out' */
+ P13_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P13_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P13_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P13_3_AMUXA = 4, /* Analog mux bus A */
+ P13_3_AMUXB = 5, /* Analog mux bus B */
+ P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P13_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */
+ P13_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:1 */
+ P13_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:96 */
+ P13_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:96 */
+ P13_3_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:1 */
+ P13_3_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:1 */
+ P13_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:1 */
+ P13_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:1 */
+
+ /* P13.4 */
+ P13_4_GPIO = 0, /* GPIO controls 'out' */
+ P13_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P13_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P13_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P13_4_AMUXA = 4, /* Analog mux bus A */
+ P13_4_AMUXB = 5, /* Analog mux bus B */
+ P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P13_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */
+ P13_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:1 */
+ P13_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:97 */
+ P13_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:97 */
+ P13_4_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:1 */
+ P13_4_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:1 */
+ P13_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:1 */
+
+ /* P13.5 */
+ P13_5_GPIO = 0, /* GPIO controls 'out' */
+ P13_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P13_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P13_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P13_5_AMUXA = 4, /* Analog mux bus A */
+ P13_5_AMUXB = 5, /* Analog mux bus B */
+ P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P13_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */
+ P13_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:1 */
+ P13_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:98 */
+ P13_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:98 */
+ P13_5_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:1 */
+ P13_5_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:1 */
+ P13_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:1 */
+
+ /* P13.6 */
+ P13_6_GPIO = 0, /* GPIO controls 'out' */
+ P13_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P13_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P13_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P13_6_AMUXA = 4, /* Analog mux bus A */
+ P13_6_AMUXB = 5, /* Analog mux bus B */
+ P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P13_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */
+ P13_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:1 */
+ P13_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:99 */
+ P13_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:99 */
+ P13_6_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:1 */
+ P13_6_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:1 */
+ P13_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:1 */
+
+ /* P13.7 */
+ P13_7_GPIO = 0, /* GPIO controls 'out' */
+ P13_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P13_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P13_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P13_7_AMUXA = 4, /* Analog mux bus A */
+ P13_7_AMUXB = 5, /* Analog mux bus B */
+ P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P13_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */
+ P13_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:1 */
+ P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */
+ P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */
+ P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */
+ P13_7_LCD_SEG38 = 13 /* Digital Deep Sleep - lcd.seg[38]:1 */
+} en_hsiom_sel_t;
+
+#endif /* _GPIO_PSOC6_01_124_BGA_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_backup.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_backup.h
new file mode 100644
index 0000000000..9094b1446b
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_backup.h
@@ -0,0 +1,234 @@
+/***************************************************************************//**
+* \file cyip_backup.h
+*
+* \brief
+* BACKUP IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_BACKUP_H_
+#define _CYIP_BACKUP_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* BACKUP
+*******************************************************************************/
+
+#define BACKUP_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief SRSS Backup Domain (BACKUP)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t RTC_RW; /*!< 0x00000008 RTC Read Write register */
+ __IOM uint32_t CAL_CTL; /*!< 0x0000000C Oscillator calibration for absolute frequency */
+ __IM uint32_t STATUS; /*!< 0x00000010 Status */
+ __IOM uint32_t RTC_TIME; /*!< 0x00000014 Calendar Seconds, Minutes, Hours, Day of Week */
+ __IOM uint32_t RTC_DATE; /*!< 0x00000018 Calendar Day of Month, Month, Year */
+ __IOM uint32_t ALM1_TIME; /*!< 0x0000001C Alarm 1 Seconds, Minute, Hours, Day of Week */
+ __IOM uint32_t ALM1_DATE; /*!< 0x00000020 Alarm 1 Day of Month, Month */
+ __IOM uint32_t ALM2_TIME; /*!< 0x00000024 Alarm 2 Seconds, Minute, Hours, Day of Week */
+ __IOM uint32_t ALM2_DATE; /*!< 0x00000028 Alarm 2 Day of Month, Month */
+ __IOM uint32_t INTR; /*!< 0x0000002C Interrupt request register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000030 Interrupt set request register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000034 Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x00000038 Interrupt masked request register */
+ __IM uint32_t OSCCNT; /*!< 0x0000003C 32kHz oscillator counter */
+ __IM uint32_t TICKS; /*!< 0x00000040 128Hz tick counter */
+ __IOM uint32_t PMIC_CTL; /*!< 0x00000044 PMIC control register */
+ __IOM uint32_t RESET; /*!< 0x00000048 Backup reset register */
+ __IM uint32_t RESERVED1[1005];
+ __IOM uint32_t BREG[64]; /*!< 0x00001000 Backup register region */
+ __IM uint32_t RESERVED2[15232];
+ __IOM uint32_t TRIM; /*!< 0x0000FF00 Trim Register */
+} BACKUP_V1_Type; /*!< Size = 65284 (0xFF04) */
+
+
+/* BACKUP.CTL */
+#define BACKUP_CTL_WCO_EN_Pos 3UL
+#define BACKUP_CTL_WCO_EN_Msk 0x8UL
+#define BACKUP_CTL_CLK_SEL_Pos 8UL
+#define BACKUP_CTL_CLK_SEL_Msk 0x300UL
+#define BACKUP_CTL_PRESCALER_Pos 12UL
+#define BACKUP_CTL_PRESCALER_Msk 0x3000UL
+#define BACKUP_CTL_WCO_BYPASS_Pos 16UL
+#define BACKUP_CTL_WCO_BYPASS_Msk 0x10000UL
+#define BACKUP_CTL_VDDBAK_CTL_Pos 17UL
+#define BACKUP_CTL_VDDBAK_CTL_Msk 0x60000UL
+#define BACKUP_CTL_VBACKUP_MEAS_Pos 19UL
+#define BACKUP_CTL_VBACKUP_MEAS_Msk 0x80000UL
+#define BACKUP_CTL_EN_CHARGE_KEY_Pos 24UL
+#define BACKUP_CTL_EN_CHARGE_KEY_Msk 0xFF000000UL
+/* BACKUP.RTC_RW */
+#define BACKUP_RTC_RW_READ_Pos 0UL
+#define BACKUP_RTC_RW_READ_Msk 0x1UL
+#define BACKUP_RTC_RW_WRITE_Pos 1UL
+#define BACKUP_RTC_RW_WRITE_Msk 0x2UL
+/* BACKUP.CAL_CTL */
+#define BACKUP_CAL_CTL_CALIB_VAL_Pos 0UL
+#define BACKUP_CAL_CTL_CALIB_VAL_Msk 0x3FUL
+#define BACKUP_CAL_CTL_CALIB_SIGN_Pos 6UL
+#define BACKUP_CAL_CTL_CALIB_SIGN_Msk 0x40UL
+#define BACKUP_CAL_CTL_CAL_OUT_Pos 31UL
+#define BACKUP_CAL_CTL_CAL_OUT_Msk 0x80000000UL
+/* BACKUP.STATUS */
+#define BACKUP_STATUS_RTC_BUSY_Pos 0UL
+#define BACKUP_STATUS_RTC_BUSY_Msk 0x1UL
+#define BACKUP_STATUS_WCO_OK_Pos 2UL
+#define BACKUP_STATUS_WCO_OK_Msk 0x4UL
+/* BACKUP.RTC_TIME */
+#define BACKUP_RTC_TIME_RTC_SEC_Pos 0UL
+#define BACKUP_RTC_TIME_RTC_SEC_Msk 0x7FUL
+#define BACKUP_RTC_TIME_RTC_MIN_Pos 8UL
+#define BACKUP_RTC_TIME_RTC_MIN_Msk 0x7F00UL
+#define BACKUP_RTC_TIME_RTC_HOUR_Pos 16UL
+#define BACKUP_RTC_TIME_RTC_HOUR_Msk 0x3F0000UL
+#define BACKUP_RTC_TIME_CTRL_12HR_Pos 22UL
+#define BACKUP_RTC_TIME_CTRL_12HR_Msk 0x400000UL
+#define BACKUP_RTC_TIME_RTC_DAY_Pos 24UL
+#define BACKUP_RTC_TIME_RTC_DAY_Msk 0x7000000UL
+/* BACKUP.RTC_DATE */
+#define BACKUP_RTC_DATE_RTC_DATE_Pos 0UL
+#define BACKUP_RTC_DATE_RTC_DATE_Msk 0x3FUL
+#define BACKUP_RTC_DATE_RTC_MON_Pos 8UL
+#define BACKUP_RTC_DATE_RTC_MON_Msk 0x1F00UL
+#define BACKUP_RTC_DATE_RTC_YEAR_Pos 16UL
+#define BACKUP_RTC_DATE_RTC_YEAR_Msk 0xFF0000UL
+/* BACKUP.ALM1_TIME */
+#define BACKUP_ALM1_TIME_ALM_SEC_Pos 0UL
+#define BACKUP_ALM1_TIME_ALM_SEC_Msk 0x7FUL
+#define BACKUP_ALM1_TIME_ALM_SEC_EN_Pos 7UL
+#define BACKUP_ALM1_TIME_ALM_SEC_EN_Msk 0x80UL
+#define BACKUP_ALM1_TIME_ALM_MIN_Pos 8UL
+#define BACKUP_ALM1_TIME_ALM_MIN_Msk 0x7F00UL
+#define BACKUP_ALM1_TIME_ALM_MIN_EN_Pos 15UL
+#define BACKUP_ALM1_TIME_ALM_MIN_EN_Msk 0x8000UL
+#define BACKUP_ALM1_TIME_ALM_HOUR_Pos 16UL
+#define BACKUP_ALM1_TIME_ALM_HOUR_Msk 0x3F0000UL
+#define BACKUP_ALM1_TIME_ALM_HOUR_EN_Pos 23UL
+#define BACKUP_ALM1_TIME_ALM_HOUR_EN_Msk 0x800000UL
+#define BACKUP_ALM1_TIME_ALM_DAY_Pos 24UL
+#define BACKUP_ALM1_TIME_ALM_DAY_Msk 0x7000000UL
+#define BACKUP_ALM1_TIME_ALM_DAY_EN_Pos 31UL
+#define BACKUP_ALM1_TIME_ALM_DAY_EN_Msk 0x80000000UL
+/* BACKUP.ALM1_DATE */
+#define BACKUP_ALM1_DATE_ALM_DATE_Pos 0UL
+#define BACKUP_ALM1_DATE_ALM_DATE_Msk 0x3FUL
+#define BACKUP_ALM1_DATE_ALM_DATE_EN_Pos 7UL
+#define BACKUP_ALM1_DATE_ALM_DATE_EN_Msk 0x80UL
+#define BACKUP_ALM1_DATE_ALM_MON_Pos 8UL
+#define BACKUP_ALM1_DATE_ALM_MON_Msk 0x1F00UL
+#define BACKUP_ALM1_DATE_ALM_MON_EN_Pos 15UL
+#define BACKUP_ALM1_DATE_ALM_MON_EN_Msk 0x8000UL
+#define BACKUP_ALM1_DATE_ALM_EN_Pos 31UL
+#define BACKUP_ALM1_DATE_ALM_EN_Msk 0x80000000UL
+/* BACKUP.ALM2_TIME */
+#define BACKUP_ALM2_TIME_ALM_SEC_Pos 0UL
+#define BACKUP_ALM2_TIME_ALM_SEC_Msk 0x7FUL
+#define BACKUP_ALM2_TIME_ALM_SEC_EN_Pos 7UL
+#define BACKUP_ALM2_TIME_ALM_SEC_EN_Msk 0x80UL
+#define BACKUP_ALM2_TIME_ALM_MIN_Pos 8UL
+#define BACKUP_ALM2_TIME_ALM_MIN_Msk 0x7F00UL
+#define BACKUP_ALM2_TIME_ALM_MIN_EN_Pos 15UL
+#define BACKUP_ALM2_TIME_ALM_MIN_EN_Msk 0x8000UL
+#define BACKUP_ALM2_TIME_ALM_HOUR_Pos 16UL
+#define BACKUP_ALM2_TIME_ALM_HOUR_Msk 0x3F0000UL
+#define BACKUP_ALM2_TIME_ALM_HOUR_EN_Pos 23UL
+#define BACKUP_ALM2_TIME_ALM_HOUR_EN_Msk 0x800000UL
+#define BACKUP_ALM2_TIME_ALM_DAY_Pos 24UL
+#define BACKUP_ALM2_TIME_ALM_DAY_Msk 0x7000000UL
+#define BACKUP_ALM2_TIME_ALM_DAY_EN_Pos 31UL
+#define BACKUP_ALM2_TIME_ALM_DAY_EN_Msk 0x80000000UL
+/* BACKUP.ALM2_DATE */
+#define BACKUP_ALM2_DATE_ALM_DATE_Pos 0UL
+#define BACKUP_ALM2_DATE_ALM_DATE_Msk 0x3FUL
+#define BACKUP_ALM2_DATE_ALM_DATE_EN_Pos 7UL
+#define BACKUP_ALM2_DATE_ALM_DATE_EN_Msk 0x80UL
+#define BACKUP_ALM2_DATE_ALM_MON_Pos 8UL
+#define BACKUP_ALM2_DATE_ALM_MON_Msk 0x1F00UL
+#define BACKUP_ALM2_DATE_ALM_MON_EN_Pos 15UL
+#define BACKUP_ALM2_DATE_ALM_MON_EN_Msk 0x8000UL
+#define BACKUP_ALM2_DATE_ALM_EN_Pos 31UL
+#define BACKUP_ALM2_DATE_ALM_EN_Msk 0x80000000UL
+/* BACKUP.INTR */
+#define BACKUP_INTR_ALARM1_Pos 0UL
+#define BACKUP_INTR_ALARM1_Msk 0x1UL
+#define BACKUP_INTR_ALARM2_Pos 1UL
+#define BACKUP_INTR_ALARM2_Msk 0x2UL
+#define BACKUP_INTR_CENTURY_Pos 2UL
+#define BACKUP_INTR_CENTURY_Msk 0x4UL
+/* BACKUP.INTR_SET */
+#define BACKUP_INTR_SET_ALARM1_Pos 0UL
+#define BACKUP_INTR_SET_ALARM1_Msk 0x1UL
+#define BACKUP_INTR_SET_ALARM2_Pos 1UL
+#define BACKUP_INTR_SET_ALARM2_Msk 0x2UL
+#define BACKUP_INTR_SET_CENTURY_Pos 2UL
+#define BACKUP_INTR_SET_CENTURY_Msk 0x4UL
+/* BACKUP.INTR_MASK */
+#define BACKUP_INTR_MASK_ALARM1_Pos 0UL
+#define BACKUP_INTR_MASK_ALARM1_Msk 0x1UL
+#define BACKUP_INTR_MASK_ALARM2_Pos 1UL
+#define BACKUP_INTR_MASK_ALARM2_Msk 0x2UL
+#define BACKUP_INTR_MASK_CENTURY_Pos 2UL
+#define BACKUP_INTR_MASK_CENTURY_Msk 0x4UL
+/* BACKUP.INTR_MASKED */
+#define BACKUP_INTR_MASKED_ALARM1_Pos 0UL
+#define BACKUP_INTR_MASKED_ALARM1_Msk 0x1UL
+#define BACKUP_INTR_MASKED_ALARM2_Pos 1UL
+#define BACKUP_INTR_MASKED_ALARM2_Msk 0x2UL
+#define BACKUP_INTR_MASKED_CENTURY_Pos 2UL
+#define BACKUP_INTR_MASKED_CENTURY_Msk 0x4UL
+/* BACKUP.OSCCNT */
+#define BACKUP_OSCCNT_CNT32KHZ_Pos 0UL
+#define BACKUP_OSCCNT_CNT32KHZ_Msk 0xFFUL
+/* BACKUP.TICKS */
+#define BACKUP_TICKS_CNT128HZ_Pos 0UL
+#define BACKUP_TICKS_CNT128HZ_Msk 0x3FUL
+/* BACKUP.PMIC_CTL */
+#define BACKUP_PMIC_CTL_UNLOCK_Pos 8UL
+#define BACKUP_PMIC_CTL_UNLOCK_Msk 0xFF00UL
+#define BACKUP_PMIC_CTL_POLARITY_Pos 16UL
+#define BACKUP_PMIC_CTL_POLARITY_Msk 0x10000UL
+#define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Pos 29UL
+#define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Msk 0x20000000UL
+#define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Pos 30UL
+#define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Msk 0x40000000UL
+#define BACKUP_PMIC_CTL_PMIC_EN_Pos 31UL
+#define BACKUP_PMIC_CTL_PMIC_EN_Msk 0x80000000UL
+/* BACKUP.RESET */
+#define BACKUP_RESET_RESET_Pos 31UL
+#define BACKUP_RESET_RESET_Msk 0x80000000UL
+/* BACKUP.BREG */
+#define BACKUP_BREG_BREG_Pos 0UL
+#define BACKUP_BREG_BREG_Msk 0xFFFFFFFFUL
+/* BACKUP.TRIM */
+#define BACKUP_TRIM_TRIM_Pos 0UL
+#define BACKUP_TRIM_TRIM_Msk 0x3FUL
+
+
+#endif /* _CYIP_BACKUP_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_ble.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_ble.h
new file mode 100644
index 0000000000..ea42cca185
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_ble.h
@@ -0,0 +1,2255 @@
+/***************************************************************************//**
+* \file cyip_ble.h
+*
+* \brief
+* BLE IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_BLE_H_
+#define _CYIP_BLE_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* BLE
+*******************************************************************************/
+
+#define BLE_RCB_RCBLL_SECTION_SIZE 0x00000100UL
+#define BLE_RCB_SECTION_SIZE 0x00000200UL
+#define BLE_BLELL_SECTION_SIZE 0x0001E000UL
+#define BLE_BLESS_SECTION_SIZE 0x00001000UL
+#define BLE_SECTION_SIZE 0x00020000UL
+
+/**
+ * \brief Radio Control Bus (RCB) & Link Layer controller (BLE_RCB_RCBLL)
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< 0x00000000 RCB LL control register. */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t INTR; /*!< 0x00000010 Master interrupt request register. */
+ __IOM uint32_t INTR_SET; /*!< 0x00000014 Master interrupt set request register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000018 Master interrupt mask register. */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000001C Master interrupt masked request register */
+ __IOM uint32_t RADIO_REG1_ADDR; /*!< 0x00000020 Address of Register#1 in Radio (MDON) */
+ __IOM uint32_t RADIO_REG2_ADDR; /*!< 0x00000024 Address of Register#2 in Radio (RSSI) */
+ __IOM uint32_t RADIO_REG3_ADDR; /*!< 0x00000028 Address of Register#3 in Radio (ACCL) */
+ __IOM uint32_t RADIO_REG4_ADDR; /*!< 0x0000002C Address of Register#4 in Radio (ACCH) */
+ __IOM uint32_t RADIO_REG5_ADDR; /*!< 0x00000030 Address of Register#5 in Radio (RSSI ENERGY) */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t CPU_WRITE_REG; /*!< 0x00000040 N/A */
+ __IOM uint32_t CPU_READ_REG; /*!< 0x00000044 N/A */
+ __IM uint32_t RESERVED2[46];
+} BLE_RCB_RCBLL_V1_Type; /*!< Size = 256 (0x100) */
+
+/**
+ * \brief Radio Control Bus (RCB) controller (BLE_RCB)
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< 0x00000000 RCB control register. */
+ __IM uint32_t STATUS; /*!< 0x00000004 RCB status register. */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t TX_CTRL; /*!< 0x00000010 Transmitter control register. */
+ __IOM uint32_t TX_FIFO_CTRL; /*!< 0x00000014 Transmitter FIFO control register. */
+ __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000018 Transmitter FIFO status register. */
+ __OM uint32_t TX_FIFO_WR; /*!< 0x0000001C Transmitter FIFO write register. */
+ __IOM uint32_t RX_CTRL; /*!< 0x00000020 Receiver control register. */
+ __IOM uint32_t RX_FIFO_CTRL; /*!< 0x00000024 Receiver FIFO control register. */
+ __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000028 Receiver FIFO status register. */
+ __IM uint32_t RX_FIFO_RD; /*!< 0x0000002C Receiver FIFO read register. */
+ __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x00000030 Receiver FIFO read register. */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t INTR; /*!< 0x00000040 Master interrupt request register. */
+ __IOM uint32_t INTR_SET; /*!< 0x00000044 Master interrupt set request register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000048 Master interrupt mask register. */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000004C Master interrupt masked request register */
+ __IM uint32_t RESERVED2[44];
+ BLE_RCB_RCBLL_V1_Type RCBLL; /*!< 0x00000100 Radio Control Bus (RCB) & Link Layer controller */
+} BLE_RCB_V1_Type; /*!< Size = 512 (0x200) */
+
+/**
+ * \brief Bluetooth Low Energy Link Layer (BLE_BLELL)
+ */
+typedef struct {
+ __OM uint32_t COMMAND_REGISTER; /*!< 0x00000000 Instruction Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t EVENT_INTR; /*!< 0x00000008 Event(Interrupt) status and Clear register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t EVENT_ENABLE; /*!< 0x00000010 Event indications enable. */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t ADV_PARAMS; /*!< 0x00000018 Advertising parameters register. */
+ __IOM uint32_t ADV_INTERVAL_TIMEOUT; /*!< 0x0000001C Advertising interval register. */
+ __IOM uint32_t ADV_INTR; /*!< 0x00000020 Advertising interrupt status and Clear register */
+ __IM uint32_t ADV_NEXT_INSTANT; /*!< 0x00000024 Advertising next instant. */
+ __IOM uint32_t SCAN_INTERVAL; /*!< 0x00000028 Scan Interval Register */
+ __IOM uint32_t SCAN_WINDOW; /*!< 0x0000002C Scan window Register */
+ __IOM uint32_t SCAN_PARAM; /*!< 0x00000030 Scanning parameters register */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t SCAN_INTR; /*!< 0x00000038 Scan interrupt status and Clear register */
+ __IM uint32_t SCAN_NEXT_INSTANT; /*!< 0x0000003C Advertising next instant. */
+ __IOM uint32_t INIT_INTERVAL; /*!< 0x00000040 Initiator Interval Register */
+ __IOM uint32_t INIT_WINDOW; /*!< 0x00000044 Initiator window Register */
+ __IOM uint32_t INIT_PARAM; /*!< 0x00000048 Initiator parameters register */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t INIT_INTR; /*!< 0x00000050 Scan interrupt status and Clear register */
+ __IM uint32_t INIT_NEXT_INSTANT; /*!< 0x00000054 Initiator next instant. */
+ __IOM uint32_t DEVICE_RAND_ADDR_L; /*!< 0x00000058 Lower 16 bit random address of the device. */
+ __IOM uint32_t DEVICE_RAND_ADDR_M; /*!< 0x0000005C Middle 16 bit random address of the device. */
+ __IOM uint32_t DEVICE_RAND_ADDR_H; /*!< 0x00000060 Higher 16 bit random address of the device. */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t PEER_ADDR_L; /*!< 0x00000068 Lower 16 bit address of the peer device. */
+ __IOM uint32_t PEER_ADDR_M; /*!< 0x0000006C Middle 16 bit address of the peer device. */
+ __IOM uint32_t PEER_ADDR_H; /*!< 0x00000070 Higher 16 bit address of the peer device. */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t WL_ADDR_TYPE; /*!< 0x00000078 whitelist address type */
+ __IOM uint32_t WL_ENABLE; /*!< 0x0000007C whitelist valid entry bit */
+ __IOM uint32_t TRANSMIT_WINDOW_OFFSET; /*!< 0x00000080 Transmit window offset */
+ __IOM uint32_t TRANSMIT_WINDOW_SIZE; /*!< 0x00000084 Transmit window size */
+ __IOM uint32_t DATA_CHANNELS_L0; /*!< 0x00000088 Data channel map 0 (lower word) */
+ __IOM uint32_t DATA_CHANNELS_M0; /*!< 0x0000008C Data channel map 0 (middle word) */
+ __IOM uint32_t DATA_CHANNELS_H0; /*!< 0x00000090 Data channel map 0 (upper word) */
+ __IM uint32_t RESERVED7;
+ __IOM uint32_t DATA_CHANNELS_L1; /*!< 0x00000098 Data channel map 1 (lower word) */
+ __IOM uint32_t DATA_CHANNELS_M1; /*!< 0x0000009C Data channel map 1 (middle word) */
+ __IOM uint32_t DATA_CHANNELS_H1; /*!< 0x000000A0 Data channel map 1 (upper word) */
+ __IM uint32_t RESERVED8;
+ __IOM uint32_t CONN_INTR; /*!< 0x000000A8 Connection interrupt status and Clear register */
+ __IM uint32_t CONN_STATUS; /*!< 0x000000AC Connection channel status */
+ __IOM uint32_t CONN_INDEX; /*!< 0x000000B0 Connection Index register */
+ __IM uint32_t RESERVED9;
+ __IOM uint32_t WAKEUP_CONFIG; /*!< 0x000000B8 Wakeup configuration */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t WAKEUP_CONTROL; /*!< 0x000000C0 Wakeup control */
+ __IOM uint32_t CLOCK_CONFIG; /*!< 0x000000C4 Clock control */
+ __IM uint32_t TIM_COUNTER_L; /*!< 0x000000C8 Reference Clock */
+ __IOM uint32_t WAKEUP_CONFIG_EXTD; /*!< 0x000000CC Wakeup configuration extended */
+ __IM uint32_t RESERVED11[2];
+ __IOM uint32_t POC_REG__TIM_CONTROL; /*!< 0x000000D8 BLE Time Control */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t ADV_TX_DATA_FIFO; /*!< 0x000000E0 Advertising data transmit FIFO. Access ADVCH_TX_FIFO. */
+ __IM uint32_t RESERVED13;
+ __IOM uint32_t ADV_SCN_RSP_TX_FIFO; /*!< 0x000000E8 Advertising scan response data transmit FIFO. Access
+ ADVCH_TX_FIFO. */
+ __IM uint32_t RESERVED14[3];
+ __IM uint32_t INIT_SCN_ADV_RX_FIFO; /*!< 0x000000F8 advertising scan response data receive data FIFO. Access
+ ADVRX_FIFO. */
+ __IM uint32_t RESERVED15;
+ __IOM uint32_t CONN_INTERVAL; /*!< 0x00000100 Connection Interval */
+ __IOM uint32_t SUP_TIMEOUT; /*!< 0x00000104 Supervision timeout */
+ __IOM uint32_t SLAVE_LATENCY; /*!< 0x00000108 Slave Latency */
+ __IOM uint32_t CE_LENGTH; /*!< 0x0000010C Connection event length */
+ __IOM uint32_t PDU_ACCESS_ADDR_L_REGISTER; /*!< 0x00000110 Access address (lower) */
+ __IOM uint32_t PDU_ACCESS_ADDR_H_REGISTER; /*!< 0x00000114 Access address (upper) */
+ __IOM uint32_t CONN_CE_INSTANT; /*!< 0x00000118 Connection event instant */
+ __IOM uint32_t CE_CNFG_STS_REGISTER; /*!< 0x0000011C connection configuration & status register */
+ __IM uint32_t NEXT_CE_INSTANT; /*!< 0x00000120 Next connection event instant */
+ __IM uint32_t CONN_CE_COUNTER; /*!< 0x00000124 connection event counter */
+ __IOM uint32_t DATA_LIST_SENT_UPDATE__STATUS; /*!< 0x00000128 data list sent update and status */
+ __IOM uint32_t DATA_LIST_ACK_UPDATE__STATUS; /*!< 0x0000012C data list ack update and status */
+ __IOM uint32_t CE_CNFG_STS_REGISTER_EXT; /*!< 0x00000130 connection configuration & status register */
+ __IOM uint32_t CONN_EXT_INTR; /*!< 0x00000134 Connection extended interrupt status and Clear register */
+ __IOM uint32_t CONN_EXT_INTR_MASK; /*!< 0x00000138 Connection Extended Interrupt mask */
+ __IM uint32_t RESERVED16;
+ __IOM uint32_t DATA_MEM_DESCRIPTOR[5]; /*!< 0x00000140 Data buffer descriptor 0 to 4 */
+ __IM uint32_t RESERVED17[3];
+ __IOM uint32_t WINDOW_WIDEN_INTVL; /*!< 0x00000160 Window widen for interval */
+ __IOM uint32_t WINDOW_WIDEN_WINOFF; /*!< 0x00000164 Window widen for offset */
+ __IM uint32_t RESERVED18[2];
+ __IOM uint32_t LE_RF_TEST_MODE; /*!< 0x00000170 Direct Test Mode control */
+ __IM uint32_t DTM_RX_PKT_COUNT; /*!< 0x00000174 Direct Test Mode receive packet count */
+ __IOM uint32_t LE_RF_TEST_MODE_EXT; /*!< 0x00000178 Direct Test Mode control */
+ __IM uint32_t RESERVED19[3];
+ __IM uint32_t TXRX_HOP; /*!< 0x00000188 Channel Address register */
+ __IM uint32_t RESERVED20;
+ __IOM uint32_t TX_RX_ON_DELAY; /*!< 0x00000190 Transmit/Receive data delay */
+ __IM uint32_t RESERVED21[5];
+ __IOM uint32_t ADV_ACCADDR_L; /*!< 0x000001A8 ADV packet access code low word */
+ __IOM uint32_t ADV_ACCADDR_H; /*!< 0x000001AC ADV packet access code high word */
+ __IOM uint32_t ADV_CH_TX_POWER_LVL_LS; /*!< 0x000001B0 Advertising channel transmit power setting */
+ __IOM uint32_t ADV_CH_TX_POWER_LVL_MS; /*!< 0x000001B4 Advertising channel transmit power setting extension */
+ __IOM uint32_t CONN_CH_TX_POWER_LVL_LS; /*!< 0x000001B8 Connection channel transmit power setting */
+ __IOM uint32_t CONN_CH_TX_POWER_LVL_MS; /*!< 0x000001BC Connection channel transmit power setting extension */
+ __IOM uint32_t DEV_PUB_ADDR_L; /*!< 0x000001C0 Device public address lower register */
+ __IOM uint32_t DEV_PUB_ADDR_M; /*!< 0x000001C4 Device public address middle register */
+ __IOM uint32_t DEV_PUB_ADDR_H; /*!< 0x000001C8 Device public address higher register */
+ __IM uint32_t RESERVED22;
+ __IOM uint32_t OFFSET_TO_FIRST_INSTANT; /*!< 0x000001D0 Offset to first instant */
+ __IOM uint32_t ADV_CONFIG; /*!< 0x000001D4 Advertiser configuration register */
+ __IOM uint32_t SCAN_CONFIG; /*!< 0x000001D8 Scan configuration register */
+ __IOM uint32_t INIT_CONFIG; /*!< 0x000001DC Initiator configuration register */
+ __IOM uint32_t CONN_CONFIG; /*!< 0x000001E0 Connection configuration register */
+ __IM uint32_t RESERVED23;
+ __IOM uint32_t CONN_PARAM1; /*!< 0x000001E8 Connection parameter 1 */
+ __IOM uint32_t CONN_PARAM2; /*!< 0x000001EC Connection parameter 2 */
+ __IOM uint32_t CONN_INTR_MASK; /*!< 0x000001F0 Connection Interrupt mask */
+ __IOM uint32_t SLAVE_TIMING_CONTROL; /*!< 0x000001F4 slave timing control */
+ __IOM uint32_t RECEIVE_TRIG_CTRL; /*!< 0x000001F8 Receive trigger control */
+ __IM uint32_t RESERVED24;
+ __IM uint32_t LL_DBG_1; /*!< 0x00000200 LL debug register 1 */
+ __IM uint32_t LL_DBG_2; /*!< 0x00000204 LL debug register 2 */
+ __IM uint32_t LL_DBG_3; /*!< 0x00000208 LL debug register 3 */
+ __IM uint32_t LL_DBG_4; /*!< 0x0000020C LL debug register 4 */
+ __IM uint32_t LL_DBG_5; /*!< 0x00000210 LL debug register 5 */
+ __IM uint32_t LL_DBG_6; /*!< 0x00000214 LL debug register 6 */
+ __IM uint32_t LL_DBG_7; /*!< 0x00000218 LL debug register 7 */
+ __IM uint32_t LL_DBG_8; /*!< 0x0000021C LL debug register 8 */
+ __IM uint32_t LL_DBG_9; /*!< 0x00000220 LL debug register 9 */
+ __IM uint32_t LL_DBG_10; /*!< 0x00000224 LL debug register 10 */
+ __IM uint32_t RESERVED25[2];
+ __IOM uint32_t PEER_ADDR_INIT_L; /*!< 0x00000230 Lower 16 bit address of the peer device for INIT. */
+ __IOM uint32_t PEER_ADDR_INIT_M; /*!< 0x00000234 Middle 16 bit address of the peer device for INIT. */
+ __IOM uint32_t PEER_ADDR_INIT_H; /*!< 0x00000238 Higher 16 bit address of the peer device for INIT. */
+ __IOM uint32_t PEER_SEC_ADDR_ADV_L; /*!< 0x0000023C Lower 16 bits of the secondary address of the peer device for
+ ADV_DIR. */
+ __IOM uint32_t PEER_SEC_ADDR_ADV_M; /*!< 0x00000240 Middle 16 bits of the secondary address of the peer device for
+ ADV_DIR. */
+ __IOM uint32_t PEER_SEC_ADDR_ADV_H; /*!< 0x00000244 Higher 16 bits of the secondary address of the peer device for
+ ADV_DIR. */
+ __IOM uint32_t INIT_WINDOW_TIMER_CTRL; /*!< 0x00000248 Initiator Window NI timer control */
+ __IOM uint32_t CONN_CONFIG_EXT; /*!< 0x0000024C Connection extended configuration register */
+ __IM uint32_t RESERVED26[2];
+ __IOM uint32_t DPLL_CONFIG; /*!< 0x00000258 DPLL & CY Correlator configuration register */
+ __IM uint32_t RESERVED27;
+ __IOM uint32_t INIT_NI_VAL; /*!< 0x00000260 Initiator Window NI instant */
+ __IM uint32_t INIT_WINDOW_OFFSET; /*!< 0x00000264 Initiator Window offset captured at conn request */
+ __IM uint32_t INIT_WINDOW_NI_ANCHOR_PT; /*!< 0x00000268 Initiator Window NI anchor point captured at conn request */
+ __IM uint32_t RESERVED28[78];
+ __IOM uint32_t CONN_UPDATE_NEW_INTERVAL; /*!< 0x000003A4 Connection update new interval */
+ __IOM uint32_t CONN_UPDATE_NEW_LATENCY; /*!< 0x000003A8 Connection update new latency */
+ __IOM uint32_t CONN_UPDATE_NEW_SUP_TO; /*!< 0x000003AC Connection update new supervision timeout */
+ __IOM uint32_t CONN_UPDATE_NEW_SL_INTERVAL; /*!< 0x000003B0 Connection update new Slave Latency X Conn interval Value */
+ __IM uint32_t RESERVED29[3];
+ __IOM uint32_t CONN_REQ_WORD0; /*!< 0x000003C0 Connection request address word 0 */
+ __IOM uint32_t CONN_REQ_WORD1; /*!< 0x000003C4 Connection request address word 1 */
+ __IOM uint32_t CONN_REQ_WORD2; /*!< 0x000003C8 Connection request address word 2 */
+ __IOM uint32_t CONN_REQ_WORD3; /*!< 0x000003CC Connection request address word 3 */
+ __IOM uint32_t CONN_REQ_WORD4; /*!< 0x000003D0 Connection request address word 4 */
+ __IOM uint32_t CONN_REQ_WORD5; /*!< 0x000003D4 Connection request address word 5 */
+ __IOM uint32_t CONN_REQ_WORD6; /*!< 0x000003D8 Connection request address word 6 */
+ __IOM uint32_t CONN_REQ_WORD7; /*!< 0x000003DC Connection request address word 7 */
+ __IOM uint32_t CONN_REQ_WORD8; /*!< 0x000003E0 Connection request address word 8 */
+ __IOM uint32_t CONN_REQ_WORD9; /*!< 0x000003E4 Connection request address word 9 */
+ __IOM uint32_t CONN_REQ_WORD10; /*!< 0x000003E8 Connection request address word 10 */
+ __IOM uint32_t CONN_REQ_WORD11; /*!< 0x000003EC Connection request address word 11 */
+ __IM uint32_t RESERVED30[389];
+ __IOM uint32_t PDU_RESP_TIMER; /*!< 0x00000A04 PDU response timer/Generic Timer (MMMS mode) */
+ __IM uint32_t NEXT_RESP_TIMER_EXP; /*!< 0x00000A08 Next response timeout instant */
+ __IM uint32_t NEXT_SUP_TO; /*!< 0x00000A0C Next supervision timeout instant */
+ __IOM uint32_t LLH_FEATURE_CONFIG; /*!< 0x00000A10 Feature enable */
+ __IOM uint32_t WIN_MIN_STEP_SIZE; /*!< 0x00000A14 Window minimum step size */
+ __IOM uint32_t SLV_WIN_ADJ; /*!< 0x00000A18 Slave window adjustment */
+ __IOM uint32_t SL_CONN_INTERVAL; /*!< 0x00000A1C Slave Latency X Conn Interval Value */
+ __IOM uint32_t LE_PING_TIMER_ADDR; /*!< 0x00000A20 LE Ping connection timer address */
+ __IOM uint32_t LE_PING_TIMER_OFFSET; /*!< 0x00000A24 LE Ping connection timer offset */
+ __IM uint32_t LE_PING_TIMER_NEXT_EXP; /*!< 0x00000A28 LE Ping timer next expiry instant */
+ __IM uint32_t LE_PING_TIMER_WRAP_COUNT; /*!< 0x00000A2C LE Ping Timer wrap count */
+ __IM uint32_t RESERVED31[244];
+ __IOM uint32_t TX_EN_EXT_DELAY; /*!< 0x00000E00 Transmit enable extension delay */
+ __IOM uint32_t TX_RX_SYNTH_DELAY; /*!< 0x00000E04 Transmit/Receive enable delay */
+ __IOM uint32_t EXT_PA_LNA_DLY_CNFG; /*!< 0x00000E08 External TX PA and RX LNA delay configuration */
+ __IM uint32_t RESERVED32;
+ __IOM uint32_t LL_CONFIG; /*!< 0x00000E10 Link Layer additional configuration */
+ __IM uint32_t RESERVED33[59];
+ __IOM uint32_t LL_CONTROL; /*!< 0x00000F00 LL Backward compatibility */
+ __IOM uint32_t DEV_PA_ADDR_L; /*!< 0x00000F04 Device Resolvable/Non-Resolvable Private address lower register */
+ __IOM uint32_t DEV_PA_ADDR_M; /*!< 0x00000F08 Device Resolvable/Non-Resolvable Private address middle
+ register */
+ __IOM uint32_t DEV_PA_ADDR_H; /*!< 0x00000F0C Device Resolvable/Non-Resolvable Private address higher
+ register */
+ __IOM uint32_t RSLV_LIST_ENABLE[16]; /*!< 0x00000F10 Resolving list entry control bit */
+ __IM uint32_t RESERVED34[20];
+ __IOM uint32_t WL_CONNECTION_STATUS; /*!< 0x00000FA0 whitelist valid entry bit */
+ __IM uint32_t RESERVED35[535];
+ __IOM uint32_t CONN_RXMEM_BASE_ADDR_DLE; /*!< 0x00001800 DLE Connection RX memory base address */
+ __IM uint32_t RESERVED36[1023];
+ __IOM uint32_t CONN_TXMEM_BASE_ADDR_DLE; /*!< 0x00002800 DLE Connection TX memory base address */
+ __IM uint32_t RESERVED37[16383];
+ __IOM uint32_t CONN_1_PARAM_MEM_BASE_ADDR; /*!< 0x00012800 Connection Parameter memory base address for connection 1 */
+ __IM uint32_t RESERVED38[31];
+ __IOM uint32_t CONN_2_PARAM_MEM_BASE_ADDR; /*!< 0x00012880 Connection Parameter memory base address for connection 2 */
+ __IM uint32_t RESERVED39[31];
+ __IOM uint32_t CONN_3_PARAM_MEM_BASE_ADDR; /*!< 0x00012900 Connection Parameter memory base address for connection 3 */
+ __IM uint32_t RESERVED40[31];
+ __IOM uint32_t CONN_4_PARAM_MEM_BASE_ADDR; /*!< 0x00012980 Connection Parameter memory base address for connection 4 */
+ __IM uint32_t RESERVED41[1439];
+ __IOM uint32_t NI_TIMER; /*!< 0x00014000 Next Instant Timer */
+ __IOM uint32_t US_OFFSET; /*!< 0x00014004 Micro-second Offset */
+ __IOM uint32_t NEXT_CONN; /*!< 0x00014008 Next Connection */
+ __IOM uint32_t NI_ABORT; /*!< 0x0001400C Abort next scheduled connection */
+ __IM uint32_t RESERVED42[4];
+ __IM uint32_t CONN_NI_STATUS; /*!< 0x00014020 Connection NI Status */
+ __IM uint32_t NEXT_SUP_TO_STATUS; /*!< 0x00014024 Next Supervision timeout Status */
+ __IM uint32_t MMMS_CONN_STATUS; /*!< 0x00014028 Connection Status */
+ __IM uint32_t BT_SLOT_CAPT_STATUS; /*!< 0x0001402C BT Slot Captured Status */
+ __IM uint32_t US_CAPT_STATUS; /*!< 0x00014030 Micro-second Capture Status */
+ __IM uint32_t US_OFFSET_STATUS; /*!< 0x00014034 Micro-second Offset Status */
+ __IM uint32_t ACCU_WINDOW_WIDEN_STATUS; /*!< 0x00014038 Accumulated Window Widen Status */
+ __IM uint32_t EARLY_INTR_STATUS; /*!< 0x0001403C Status when early interrupt is raised */
+ __IOM uint32_t MMMS_CONFIG; /*!< 0x00014040 Multi-Master Multi-Slave Config */
+ __IM uint32_t US_COUNTER; /*!< 0x00014044 Running US of the current BT Slot */
+ __IOM uint32_t US_CAPT_PREV; /*!< 0x00014048 Previous captured US of the BT Slot */
+ __IM uint32_t EARLY_INTR_NI; /*!< 0x0001404C NI at early interrupt */
+ __IM uint32_t RESERVED43[12];
+ __IM uint32_t MMMS_MASTER_CREATE_BT_CAPT; /*!< 0x00014080 BT slot capture for master connection creation */
+ __IM uint32_t MMMS_SLAVE_CREATE_BT_CAPT; /*!< 0x00014084 BT slot capture for slave connection creation */
+ __IM uint32_t MMMS_SLAVE_CREATE_US_CAPT; /*!< 0x00014088 Micro second capture for slave connection creation */
+ __IM uint32_t RESERVED44[29];
+ __IOM uint32_t MMMS_DATA_MEM_DESCRIPTOR[16]; /*!< 0x00014100 Data buffer descriptor 0 to 15 */
+ __IM uint32_t RESERVED45[48];
+ __IOM uint32_t CONN_1_DATA_LIST_SENT; /*!< 0x00014200 data list sent update and status for connection 1 */
+ __IOM uint32_t CONN_1_DATA_LIST_ACK; /*!< 0x00014204 data list ack update and status for connection 1 */
+ __IOM uint32_t CONN_1_CE_DATA_LIST_CFG; /*!< 0x00014208 Connection specific pause resume for connection 1 */
+ __IM uint32_t RESERVED46;
+ __IOM uint32_t CONN_2_DATA_LIST_SENT; /*!< 0x00014210 data list sent update and status for connection 2 */
+ __IOM uint32_t CONN_2_DATA_LIST_ACK; /*!< 0x00014214 data list ack update and status for connection 2 */
+ __IOM uint32_t CONN_2_CE_DATA_LIST_CFG; /*!< 0x00014218 Connection specific pause resume for connection 2 */
+ __IM uint32_t RESERVED47;
+ __IOM uint32_t CONN_3_DATA_LIST_SENT; /*!< 0x00014220 data list sent update and status for connection 3 */
+ __IOM uint32_t CONN_3_DATA_LIST_ACK; /*!< 0x00014224 data list ack update and status for connection 3 */
+ __IOM uint32_t CONN_3_CE_DATA_LIST_CFG; /*!< 0x00014228 Connection specific pause resume for connection 3 */
+ __IM uint32_t RESERVED48;
+ __IOM uint32_t CONN_4_DATA_LIST_SENT; /*!< 0x00014230 data list sent update and status for connection 4 */
+ __IOM uint32_t CONN_4_DATA_LIST_ACK; /*!< 0x00014234 data list ack update and status for connection 4 */
+ __IOM uint32_t CONN_4_CE_DATA_LIST_CFG; /*!< 0x00014238 Connection specific pause resume for connection 4 */
+ __IM uint32_t RESERVED49[113];
+ __IOM uint32_t MMMS_ADVCH_NI_ENABLE; /*!< 0x00014400 Enable bits for ADV_NI, SCAN_NI and INIT_NI */
+ __IOM uint32_t MMMS_ADVCH_NI_VALID; /*!< 0x00014404 Next instant valid for ADV, SCAN, INIT */
+ __IOM uint32_t MMMS_ADVCH_NI_ABORT; /*!< 0x00014408 Abort the next instant of ADV, SCAN, INIT */
+ __IM uint32_t RESERVED50;
+ __IOM uint32_t CONN_PARAM_NEXT_SUP_TO; /*!< 0x00014410 Register to configure the supervision timeout for next
+ scheduled connection */
+ __IOM uint32_t CONN_PARAM_ACC_WIN_WIDEN; /*!< 0x00014414 Register to configure Accumulated window widening for next
+ scheduled connection */
+ __IM uint32_t RESERVED51[2];
+ __IOM uint32_t HW_LOAD_OFFSET; /*!< 0x00014420 Register to configure offset from connection anchor point at
+ which connection parameter memory should be read */
+ __IM uint32_t ADV_RAND; /*!< 0x00014424 Random number generated by Hardware for ADV NI calculation */
+ __IM uint32_t MMMS_RX_PKT_CNTR; /*!< 0x00014428 Packet Counter of packets in RX FIFO in MMMS mode */
+ __IM uint32_t RESERVED52;
+ __IM uint32_t CONN_RX_PKT_CNTR[8]; /*!< 0x00014430 Packet Counter for Individual connection index */
+ __IM uint32_t RESERVED53[236];
+ __IOM uint32_t WHITELIST_BASE_ADDR; /*!< 0x00014800 Whitelist base address */
+ __IM uint32_t RESERVED54[47];
+ __IOM uint32_t RSLV_LIST_PEER_IDNTT_BASE_ADDR; /*!< 0x000148C0 Resolving list base address for storing Peer Identity address */
+ __IM uint32_t RESERVED55[47];
+ __IOM uint32_t RSLV_LIST_PEER_RPA_BASE_ADDR; /*!< 0x00014980 Resolving list base address for storing resolved Peer RPA
+ address */
+ __IM uint32_t RESERVED56[47];
+ __IOM uint32_t RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR; /*!< 0x00014A40 Resolving list base address for storing Resolved received INITA
+ RPA */
+ __IM uint32_t RESERVED57[47];
+ __IOM uint32_t RSLV_LIST_TX_INIT_RPA_BASE_ADDR; /*!< 0x00014B00 Resolving list base address for storing generated TX INITA RPA */
+ __IM uint32_t RESERVED58[9535];
+} BLE_BLELL_V1_Type; /*!< Size = 122880 (0x1E000) */
+
+/**
+ * \brief Bluetooth Low Energy Subsystem Miscellaneous (BLE_BLESS)
+ */
+typedef struct {
+ __IM uint32_t RESERVED[24];
+ __IOM uint32_t DDFT_CONFIG; /*!< 0x00000060 BLESS DDFT configuration register */
+ __IOM uint32_t XTAL_CLK_DIV_CONFIG; /*!< 0x00000064 Crystal clock divider configuration register */
+ __IOM uint32_t INTR_STAT; /*!< 0x00000068 Link Layer interrupt status register */
+ __IOM uint32_t INTR_MASK; /*!< 0x0000006C Link Layer interrupt mask register */
+ __IOM uint32_t LL_CLK_EN; /*!< 0x00000070 Link Layer primary clock enable */
+ __IOM uint32_t LF_CLK_CTRL; /*!< 0x00000074 BLESS LF clock control and BLESS revision ID indicator */
+ __IOM uint32_t EXT_PA_LNA_CTRL; /*!< 0x00000078 External TX PA and RX LNA control */
+ __IM uint32_t RESERVED1;
+ __IM uint32_t LL_PKT_RSSI_CH_ENERGY; /*!< 0x00000080 Link Layer Last Received packet RSSI/Channel energy and channel
+ number */
+ __IM uint32_t BT_CLOCK_CAPT; /*!< 0x00000084 BT clock captured on an LL DSM exit */
+ __IM uint32_t RESERVED2[6];
+ __IOM uint32_t MT_CFG; /*!< 0x000000A0 MT Configuration Register */
+ __IOM uint32_t MT_DELAY_CFG; /*!< 0x000000A4 MT Delay configuration for state transitions */
+ __IOM uint32_t MT_DELAY_CFG2; /*!< 0x000000A8 MT Delay configuration for state transitions */
+ __IOM uint32_t MT_DELAY_CFG3; /*!< 0x000000AC MT Delay configuration for state transitions */
+ __IOM uint32_t MT_VIO_CTRL; /*!< 0x000000B0 MT Configuration Register to control VIO switches */
+ __IM uint32_t MT_STATUS; /*!< 0x000000B4 MT Status Register */
+ __IM uint32_t PWR_CTRL_SM_ST; /*!< 0x000000B8 Link Layer Power Control FSM Status Register */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t HVLDO_CTRL; /*!< 0x000000C0 HVLDO Configuration register */
+ __IOM uint32_t MISC_EN_CTRL; /*!< 0x000000C4 Radio Buck and Active regulator enable control */
+ __IM uint32_t RESERVED4[2];
+ __IOM uint32_t EFUSE_CONFIG; /*!< 0x000000D0 EFUSE mode configuration register */
+ __IOM uint32_t EFUSE_TIM_CTRL1; /*!< 0x000000D4 EFUSE timing control register (common for Program and Read
+ modes) */
+ __IOM uint32_t EFUSE_TIM_CTRL2; /*!< 0x000000D8 EFUSE timing control Register (for Read) */
+ __IOM uint32_t EFUSE_TIM_CTRL3; /*!< 0x000000DC EFUSE timing control Register (for Program) */
+ __IM uint32_t EFUSE_RDATA_L; /*!< 0x000000E0 EFUSE Lower read data */
+ __IM uint32_t EFUSE_RDATA_H; /*!< 0x000000E4 EFUSE higher read data */
+ __IOM uint32_t EFUSE_WDATA_L; /*!< 0x000000E8 EFUSE lower write word */
+ __IOM uint32_t EFUSE_WDATA_H; /*!< 0x000000EC EFUSE higher write word */
+ __IOM uint32_t DIV_BY_625_CFG; /*!< 0x000000F0 Divide by 625 for FW Use */
+ __IM uint32_t DIV_BY_625_STS; /*!< 0x000000F4 Output of divide by 625 divider */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t PACKET_COUNTER0; /*!< 0x00000100 Packet counter 0 */
+ __IOM uint32_t PACKET_COUNTER2; /*!< 0x00000104 Packet counter 2 */
+ __IOM uint32_t IV_MASTER0; /*!< 0x00000108 Master Initialization Vector 0 */
+ __IOM uint32_t IV_SLAVE0; /*!< 0x0000010C Slave Initialization Vector 0 */
+ __OM uint32_t ENC_KEY[4]; /*!< 0x00000110 Encryption Key register 0-3 */
+ __IOM uint32_t MIC_IN0; /*!< 0x00000120 MIC input register */
+ __IM uint32_t MIC_OUT0; /*!< 0x00000124 MIC output register */
+ __IOM uint32_t ENC_PARAMS; /*!< 0x00000128 Encryption Parameter register */
+ __IOM uint32_t ENC_CONFIG; /*!< 0x0000012C Encryption Configuration */
+ __IOM uint32_t ENC_INTR_EN; /*!< 0x00000130 Encryption Interrupt enable */
+ __IOM uint32_t ENC_INTR; /*!< 0x00000134 Encryption Interrupt status and clear register */
+ __IM uint32_t RESERVED6[2];
+ __IOM uint32_t B1_DATA_REG[4]; /*!< 0x00000140 Programmable B1 Data register (0-3) */
+ __IOM uint32_t ENC_MEM_BASE_ADDR; /*!< 0x00000150 Encryption memory base address */
+ __IM uint32_t RESERVED7[875];
+ __IOM uint32_t TRIM_LDO_0; /*!< 0x00000F00 LDO Trim register 0 */
+ __IOM uint32_t TRIM_LDO_1; /*!< 0x00000F04 LDO Trim register 1 */
+ __IOM uint32_t TRIM_LDO_2; /*!< 0x00000F08 LDO Trim register 2 */
+ __IOM uint32_t TRIM_LDO_3; /*!< 0x00000F0C LDO Trim register 3 */
+ __IOM uint32_t TRIM_MXD[4]; /*!< 0x00000F10 MXD die Trim registers */
+ __IM uint32_t RESERVED8[4];
+ __IOM uint32_t TRIM_LDO_4; /*!< 0x00000F30 LDO Trim register 4 */
+ __IOM uint32_t TRIM_LDO_5; /*!< 0x00000F34 LDO Trim register 5 */
+ __IM uint32_t RESERVED9[50];
+} BLE_BLESS_V1_Type; /*!< Size = 4096 (0x1000) */
+
+/**
+ * \brief Bluetooth Low Energy Subsystem (BLE)
+ */
+typedef struct {
+ BLE_RCB_V1_Type RCB; /*!< 0x00000000 Radio Control Bus (RCB) controller */
+ __IM uint32_t RESERVED[896];
+ BLE_BLELL_V1_Type BLELL; /*!< 0x00001000 Bluetooth Low Energy Link Layer */
+ BLE_BLESS_V1_Type BLESS; /*!< 0x0001F000 Bluetooth Low Energy Subsystem Miscellaneous */
+} BLE_V1_Type; /*!< Size = 131072 (0x20000) */
+
+
+/* BLE_RCB_RCBLL.CTRL */
+#define BLE_RCB_RCBLL_CTRL_RCBLL_CTRL_Pos 0UL
+#define BLE_RCB_RCBLL_CTRL_RCBLL_CTRL_Msk 0x1UL
+#define BLE_RCB_RCBLL_CTRL_RCBLL_CPU_REQ_Pos 1UL
+#define BLE_RCB_RCBLL_CTRL_RCBLL_CPU_REQ_Msk 0x2UL
+#define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_WRITE_Pos 2UL
+#define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_WRITE_Msk 0x4UL
+#define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_READ_Pos 3UL
+#define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_READ_Msk 0x8UL
+#define BLE_RCB_RCBLL_CTRL_ALLOW_CPU_ACCESS_TX_RX_Pos 4UL
+#define BLE_RCB_RCBLL_CTRL_ALLOW_CPU_ACCESS_TX_RX_Msk 0x10UL
+#define BLE_RCB_RCBLL_CTRL_ENABLE_RADIO_BOD_Pos 5UL
+#define BLE_RCB_RCBLL_CTRL_ENABLE_RADIO_BOD_Msk 0x20UL
+/* BLE_RCB_RCBLL.INTR */
+#define BLE_RCB_RCBLL_INTR_RCB_LL_DONE_Pos 0UL
+#define BLE_RCB_RCBLL_INTR_RCB_LL_DONE_Msk 0x1UL
+#define BLE_RCB_RCBLL_INTR_SINGLE_WRITE_DONE_Pos 2UL
+#define BLE_RCB_RCBLL_INTR_SINGLE_WRITE_DONE_Msk 0x4UL
+#define BLE_RCB_RCBLL_INTR_SINGLE_READ_DONE_Pos 3UL
+#define BLE_RCB_RCBLL_INTR_SINGLE_READ_DONE_Msk 0x8UL
+/* BLE_RCB_RCBLL.INTR_SET */
+#define BLE_RCB_RCBLL_INTR_SET_RCB_LL_DONE_Pos 0UL
+#define BLE_RCB_RCBLL_INTR_SET_RCB_LL_DONE_Msk 0x1UL
+#define BLE_RCB_RCBLL_INTR_SET_SINGLE_WRITE_DONE_Pos 2UL
+#define BLE_RCB_RCBLL_INTR_SET_SINGLE_WRITE_DONE_Msk 0x4UL
+#define BLE_RCB_RCBLL_INTR_SET_SINGLE_READ_DONE_Pos 3UL
+#define BLE_RCB_RCBLL_INTR_SET_SINGLE_READ_DONE_Msk 0x8UL
+/* BLE_RCB_RCBLL.INTR_MASK */
+#define BLE_RCB_RCBLL_INTR_MASK_RCB_LL_DONE_Pos 0UL
+#define BLE_RCB_RCBLL_INTR_MASK_RCB_LL_DONE_Msk 0x1UL
+#define BLE_RCB_RCBLL_INTR_MASK_SINGLE_WRITE_DONE_Pos 2UL
+#define BLE_RCB_RCBLL_INTR_MASK_SINGLE_WRITE_DONE_Msk 0x4UL
+#define BLE_RCB_RCBLL_INTR_MASK_SINGLE_READ_DONE_Pos 3UL
+#define BLE_RCB_RCBLL_INTR_MASK_SINGLE_READ_DONE_Msk 0x8UL
+/* BLE_RCB_RCBLL.INTR_MASKED */
+#define BLE_RCB_RCBLL_INTR_MASKED_RCB_LL_DONE_Pos 0UL
+#define BLE_RCB_RCBLL_INTR_MASKED_RCB_LL_DONE_Msk 0x1UL
+#define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_WRITE_DONE_Pos 2UL
+#define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_WRITE_DONE_Msk 0x4UL
+#define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_READ_DONE_Pos 3UL
+#define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_READ_DONE_Msk 0x8UL
+/* BLE_RCB_RCBLL.RADIO_REG1_ADDR */
+#define BLE_RCB_RCBLL_RADIO_REG1_ADDR_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_RADIO_REG1_ADDR_REG_ADDR_Msk 0xFFFFUL
+/* BLE_RCB_RCBLL.RADIO_REG2_ADDR */
+#define BLE_RCB_RCBLL_RADIO_REG2_ADDR_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_RADIO_REG2_ADDR_REG_ADDR_Msk 0xFFFFUL
+/* BLE_RCB_RCBLL.RADIO_REG3_ADDR */
+#define BLE_RCB_RCBLL_RADIO_REG3_ADDR_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_RADIO_REG3_ADDR_REG_ADDR_Msk 0xFFFFUL
+/* BLE_RCB_RCBLL.RADIO_REG4_ADDR */
+#define BLE_RCB_RCBLL_RADIO_REG4_ADDR_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_RADIO_REG4_ADDR_REG_ADDR_Msk 0xFFFFUL
+/* BLE_RCB_RCBLL.RADIO_REG5_ADDR */
+#define BLE_RCB_RCBLL_RADIO_REG5_ADDR_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_RADIO_REG5_ADDR_REG_ADDR_Msk 0xFFFFUL
+/* BLE_RCB_RCBLL.CPU_WRITE_REG */
+#define BLE_RCB_RCBLL_CPU_WRITE_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_CPU_WRITE_REG_ADDR_Msk 0xFFFFUL
+#define BLE_RCB_RCBLL_CPU_WRITE_REG_WRITE_DATA_Pos 16UL
+#define BLE_RCB_RCBLL_CPU_WRITE_REG_WRITE_DATA_Msk 0xFFFF0000UL
+/* BLE_RCB_RCBLL.CPU_READ_REG */
+#define BLE_RCB_RCBLL_CPU_READ_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_CPU_READ_REG_ADDR_Msk 0xFFFFUL
+#define BLE_RCB_RCBLL_CPU_READ_REG_READ_DATA_Pos 16UL
+#define BLE_RCB_RCBLL_CPU_READ_REG_READ_DATA_Msk 0xFFFF0000UL
+
+
+/* BLE_RCB.CTRL */
+#define BLE_RCB_CTRL_TX_CLK_EDGE_Pos 1UL
+#define BLE_RCB_CTRL_TX_CLK_EDGE_Msk 0x2UL
+#define BLE_RCB_CTRL_RX_CLK_EDGE_Pos 2UL
+#define BLE_RCB_CTRL_RX_CLK_EDGE_Msk 0x4UL
+#define BLE_RCB_CTRL_RX_CLK_SRC_Pos 3UL
+#define BLE_RCB_CTRL_RX_CLK_SRC_Msk 0x8UL
+#define BLE_RCB_CTRL_SCLK_CONTINUOUS_Pos 4UL
+#define BLE_RCB_CTRL_SCLK_CONTINUOUS_Msk 0x10UL
+#define BLE_RCB_CTRL_SSEL_POLARITY_Pos 5UL
+#define BLE_RCB_CTRL_SSEL_POLARITY_Msk 0x20UL
+#define BLE_RCB_CTRL_LEAD_Pos 8UL
+#define BLE_RCB_CTRL_LEAD_Msk 0x300UL
+#define BLE_RCB_CTRL_LAG_Pos 10UL
+#define BLE_RCB_CTRL_LAG_Msk 0xC00UL
+#define BLE_RCB_CTRL_DIV_ENABLED_Pos 12UL
+#define BLE_RCB_CTRL_DIV_ENABLED_Msk 0x1000UL
+#define BLE_RCB_CTRL_DIV_Pos 13UL
+#define BLE_RCB_CTRL_DIV_Msk 0x7E000UL
+#define BLE_RCB_CTRL_ADDR_WIDTH_Pos 19UL
+#define BLE_RCB_CTRL_ADDR_WIDTH_Msk 0x780000UL
+#define BLE_RCB_CTRL_DATA_WIDTH_Pos 23UL
+#define BLE_RCB_CTRL_DATA_WIDTH_Msk 0x800000UL
+#define BLE_RCB_CTRL_ENABLED_Pos 31UL
+#define BLE_RCB_CTRL_ENABLED_Msk 0x80000000UL
+/* BLE_RCB.STATUS */
+#define BLE_RCB_STATUS_BUS_BUSY_Pos 0UL
+#define BLE_RCB_STATUS_BUS_BUSY_Msk 0x1UL
+/* BLE_RCB.TX_CTRL */
+#define BLE_RCB_TX_CTRL_MSB_FIRST_Pos 0UL
+#define BLE_RCB_TX_CTRL_MSB_FIRST_Msk 0x1UL
+#define BLE_RCB_TX_CTRL_FIFO_RECONFIG_Pos 1UL
+#define BLE_RCB_TX_CTRL_FIFO_RECONFIG_Msk 0x2UL
+#define BLE_RCB_TX_CTRL_TX_ENTRIES_Pos 2UL
+#define BLE_RCB_TX_CTRL_TX_ENTRIES_Msk 0x7CUL
+/* BLE_RCB.TX_FIFO_CTRL */
+#define BLE_RCB_TX_FIFO_CTRL_TX_TRIGGER_LEVEL_Pos 0UL
+#define BLE_RCB_TX_FIFO_CTRL_TX_TRIGGER_LEVEL_Msk 0x1FUL
+#define BLE_RCB_TX_FIFO_CTRL_CLEAR_Pos 16UL
+#define BLE_RCB_TX_FIFO_CTRL_CLEAR_Msk 0x10000UL
+/* BLE_RCB.TX_FIFO_STATUS */
+#define BLE_RCB_TX_FIFO_STATUS_USED_Pos 0UL
+#define BLE_RCB_TX_FIFO_STATUS_USED_Msk 0x1FUL
+#define BLE_RCB_TX_FIFO_STATUS_SR_VALID_Pos 15UL
+#define BLE_RCB_TX_FIFO_STATUS_SR_VALID_Msk 0x8000UL
+#define BLE_RCB_TX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define BLE_RCB_TX_FIFO_STATUS_RD_PTR_Msk 0xF0000UL
+#define BLE_RCB_TX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define BLE_RCB_TX_FIFO_STATUS_WR_PTR_Msk 0xF000000UL
+/* BLE_RCB.TX_FIFO_WR */
+#define BLE_RCB_TX_FIFO_WR_DATA_Pos 0UL
+#define BLE_RCB_TX_FIFO_WR_DATA_Msk 0xFFFFFFFFUL
+/* BLE_RCB.RX_CTRL */
+#define BLE_RCB_RX_CTRL_MSB_FIRST_Pos 0UL
+#define BLE_RCB_RX_CTRL_MSB_FIRST_Msk 0x1UL
+/* BLE_RCB.RX_FIFO_CTRL */
+#define BLE_RCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos 0UL
+#define BLE_RCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk 0xFUL
+#define BLE_RCB_RX_FIFO_CTRL_CLEAR_Pos 16UL
+#define BLE_RCB_RX_FIFO_CTRL_CLEAR_Msk 0x10000UL
+/* BLE_RCB.RX_FIFO_STATUS */
+#define BLE_RCB_RX_FIFO_STATUS_USED_Pos 0UL
+#define BLE_RCB_RX_FIFO_STATUS_USED_Msk 0x1FUL
+#define BLE_RCB_RX_FIFO_STATUS_SR_VALID_Pos 15UL
+#define BLE_RCB_RX_FIFO_STATUS_SR_VALID_Msk 0x8000UL
+#define BLE_RCB_RX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define BLE_RCB_RX_FIFO_STATUS_RD_PTR_Msk 0xF0000UL
+#define BLE_RCB_RX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define BLE_RCB_RX_FIFO_STATUS_WR_PTR_Msk 0xF000000UL
+/* BLE_RCB.RX_FIFO_RD */
+#define BLE_RCB_RX_FIFO_RD_DATA_Pos 0UL
+#define BLE_RCB_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL
+/* BLE_RCB.RX_FIFO_RD_SILENT */
+#define BLE_RCB_RX_FIFO_RD_SILENT_DATA_Pos 0UL
+#define BLE_RCB_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL
+/* BLE_RCB.INTR */
+#define BLE_RCB_INTR_RCB_DONE_Pos 0UL
+#define BLE_RCB_INTR_RCB_DONE_Msk 0x1UL
+#define BLE_RCB_INTR_TX_FIFO_TRIGGER_Pos 8UL
+#define BLE_RCB_INTR_TX_FIFO_TRIGGER_Msk 0x100UL
+#define BLE_RCB_INTR_TX_FIFO_NOT_FULL_Pos 9UL
+#define BLE_RCB_INTR_TX_FIFO_NOT_FULL_Msk 0x200UL
+#define BLE_RCB_INTR_TX_FIFO_EMPTY_Pos 10UL
+#define BLE_RCB_INTR_TX_FIFO_EMPTY_Msk 0x400UL
+#define BLE_RCB_INTR_TX_FIFO_OVERFLOW_Pos 11UL
+#define BLE_RCB_INTR_TX_FIFO_OVERFLOW_Msk 0x800UL
+#define BLE_RCB_INTR_TX_FIFO_UNDERFLOW_Pos 12UL
+#define BLE_RCB_INTR_TX_FIFO_UNDERFLOW_Msk 0x1000UL
+#define BLE_RCB_INTR_RX_FIFO_TRIGGER_Pos 16UL
+#define BLE_RCB_INTR_RX_FIFO_TRIGGER_Msk 0x10000UL
+#define BLE_RCB_INTR_RX_FIFO_NOT_EMPTY_Pos 17UL
+#define BLE_RCB_INTR_RX_FIFO_NOT_EMPTY_Msk 0x20000UL
+#define BLE_RCB_INTR_RX_FIFO_FULL_Pos 18UL
+#define BLE_RCB_INTR_RX_FIFO_FULL_Msk 0x40000UL
+#define BLE_RCB_INTR_RX_FIFO_OVERFLOW_Pos 19UL
+#define BLE_RCB_INTR_RX_FIFO_OVERFLOW_Msk 0x80000UL
+#define BLE_RCB_INTR_RX_FIFO_UNDERFLOW_Pos 20UL
+#define BLE_RCB_INTR_RX_FIFO_UNDERFLOW_Msk 0x100000UL
+/* BLE_RCB.INTR_SET */
+#define BLE_RCB_INTR_SET_RCB_DONE_Pos 0UL
+#define BLE_RCB_INTR_SET_RCB_DONE_Msk 0x1UL
+#define BLE_RCB_INTR_SET_TX_FIFO_TRIGGER_Pos 8UL
+#define BLE_RCB_INTR_SET_TX_FIFO_TRIGGER_Msk 0x100UL
+#define BLE_RCB_INTR_SET_TX_FIFO_NOT_FULL_Pos 9UL
+#define BLE_RCB_INTR_SET_TX_FIFO_NOT_FULL_Msk 0x200UL
+#define BLE_RCB_INTR_SET_TX_FIFO_EMPTY_Pos 10UL
+#define BLE_RCB_INTR_SET_TX_FIFO_EMPTY_Msk 0x400UL
+#define BLE_RCB_INTR_SET_TX_FIFO_OVERFLOW_Pos 11UL
+#define BLE_RCB_INTR_SET_TX_FIFO_OVERFLOW_Msk 0x800UL
+#define BLE_RCB_INTR_SET_TX_FIFO_UNDERFLOW_Pos 12UL
+#define BLE_RCB_INTR_SET_TX_FIFO_UNDERFLOW_Msk 0x1000UL
+#define BLE_RCB_INTR_SET_RX_FIFO_TRIGGER_Pos 16UL
+#define BLE_RCB_INTR_SET_RX_FIFO_TRIGGER_Msk 0x10000UL
+#define BLE_RCB_INTR_SET_RX_FIFO_NOT_EMPTY_Pos 17UL
+#define BLE_RCB_INTR_SET_RX_FIFO_NOT_EMPTY_Msk 0x20000UL
+#define BLE_RCB_INTR_SET_RX_FIFO_FULL_Pos 18UL
+#define BLE_RCB_INTR_SET_RX_FIFO_FULL_Msk 0x40000UL
+#define BLE_RCB_INTR_SET_RX_FIFO_OVERFLOW_Pos 19UL
+#define BLE_RCB_INTR_SET_RX_FIFO_OVERFLOW_Msk 0x80000UL
+#define BLE_RCB_INTR_SET_RX_FIFO_UNDERFLOW_Pos 20UL
+#define BLE_RCB_INTR_SET_RX_FIFO_UNDERFLOW_Msk 0x100000UL
+/* BLE_RCB.INTR_MASK */
+#define BLE_RCB_INTR_MASK_RCB_DONE_Pos 0UL
+#define BLE_RCB_INTR_MASK_RCB_DONE_Msk 0x1UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_TRIGGER_Pos 8UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_TRIGGER_Msk 0x100UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_NOT_FULL_Pos 9UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_NOT_FULL_Msk 0x200UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_EMPTY_Pos 10UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_EMPTY_Msk 0x400UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_OVERFLOW_Pos 11UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_OVERFLOW_Msk 0x800UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_UNDERFLOW_Pos 12UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_UNDERFLOW_Msk 0x1000UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_TRIGGER_Pos 16UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_TRIGGER_Msk 0x10000UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_NOT_EMPTY_Pos 17UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_NOT_EMPTY_Msk 0x20000UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_FULL_Pos 18UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_FULL_Msk 0x40000UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_OVERFLOW_Pos 19UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_OVERFLOW_Msk 0x80000UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_UNDERFLOW_Pos 20UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_UNDERFLOW_Msk 0x100000UL
+/* BLE_RCB.INTR_MASKED */
+#define BLE_RCB_INTR_MASKED_RCB_DONE_Pos 0UL
+#define BLE_RCB_INTR_MASKED_RCB_DONE_Msk 0x1UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_TRIGGER_Pos 8UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_TRIGGER_Msk 0x100UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_NOT_FULL_Pos 9UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_NOT_FULL_Msk 0x200UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_EMPTY_Pos 10UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_EMPTY_Msk 0x400UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_OVERFLOW_Pos 11UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_OVERFLOW_Msk 0x800UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_UNDERFLOW_Pos 12UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_UNDERFLOW_Msk 0x1000UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_TRIGGER_Pos 16UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_TRIGGER_Msk 0x10000UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_NOT_EMPTY_Pos 17UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_NOT_EMPTY_Msk 0x20000UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_FULL_Pos 18UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_FULL_Msk 0x40000UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_OVERFLOW_Pos 19UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_OVERFLOW_Msk 0x80000UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_UNDERFLOW_Pos 20UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_UNDERFLOW_Msk 0x100000UL
+
+
+/* BLE_BLELL.COMMAND_REGISTER */
+#define BLE_BLELL_COMMAND_REGISTER_COMMAND_Pos 0UL
+#define BLE_BLELL_COMMAND_REGISTER_COMMAND_Msk 0xFFUL
+/* BLE_BLELL.EVENT_INTR */
+#define BLE_BLELL_EVENT_INTR_ADV_INTR_Pos 0UL
+#define BLE_BLELL_EVENT_INTR_ADV_INTR_Msk 0x1UL
+#define BLE_BLELL_EVENT_INTR_SCAN_INTR_Pos 1UL
+#define BLE_BLELL_EVENT_INTR_SCAN_INTR_Msk 0x2UL
+#define BLE_BLELL_EVENT_INTR_INIT_INTR_Pos 2UL
+#define BLE_BLELL_EVENT_INTR_INIT_INTR_Msk 0x4UL
+#define BLE_BLELL_EVENT_INTR_CONN_INTR_Pos 3UL
+#define BLE_BLELL_EVENT_INTR_CONN_INTR_Msk 0x8UL
+#define BLE_BLELL_EVENT_INTR_SM_INTR_Pos 4UL
+#define BLE_BLELL_EVENT_INTR_SM_INTR_Msk 0x10UL
+#define BLE_BLELL_EVENT_INTR_DSM_INTR_Pos 5UL
+#define BLE_BLELL_EVENT_INTR_DSM_INTR_Msk 0x20UL
+#define BLE_BLELL_EVENT_INTR_ENC_INTR_Pos 6UL
+#define BLE_BLELL_EVENT_INTR_ENC_INTR_Msk 0x40UL
+#define BLE_BLELL_EVENT_INTR_RSSI_RX_DONE_INTR_Pos 7UL
+#define BLE_BLELL_EVENT_INTR_RSSI_RX_DONE_INTR_Msk 0x80UL
+/* BLE_BLELL.EVENT_ENABLE */
+#define BLE_BLELL_EVENT_ENABLE_ADV_INT_EN_Pos 0UL
+#define BLE_BLELL_EVENT_ENABLE_ADV_INT_EN_Msk 0x1UL
+#define BLE_BLELL_EVENT_ENABLE_SCN_INT_EN_Pos 1UL
+#define BLE_BLELL_EVENT_ENABLE_SCN_INT_EN_Msk 0x2UL
+#define BLE_BLELL_EVENT_ENABLE_INIT_INT_EN_Pos 2UL
+#define BLE_BLELL_EVENT_ENABLE_INIT_INT_EN_Msk 0x4UL
+#define BLE_BLELL_EVENT_ENABLE_CONN_INT_EN_Pos 3UL
+#define BLE_BLELL_EVENT_ENABLE_CONN_INT_EN_Msk 0x8UL
+#define BLE_BLELL_EVENT_ENABLE_SM_INT_EN_Pos 4UL
+#define BLE_BLELL_EVENT_ENABLE_SM_INT_EN_Msk 0x10UL
+#define BLE_BLELL_EVENT_ENABLE_DSM_INT_EN_Pos 5UL
+#define BLE_BLELL_EVENT_ENABLE_DSM_INT_EN_Msk 0x20UL
+#define BLE_BLELL_EVENT_ENABLE_ENC_INT_EN_Pos 6UL
+#define BLE_BLELL_EVENT_ENABLE_ENC_INT_EN_Msk 0x40UL
+#define BLE_BLELL_EVENT_ENABLE_RSSI_RX_DONE_INT_EN_Pos 7UL
+#define BLE_BLELL_EVENT_ENABLE_RSSI_RX_DONE_INT_EN_Msk 0x80UL
+/* BLE_BLELL.ADV_PARAMS */
+#define BLE_BLELL_ADV_PARAMS_TX_ADDR_Pos 0UL
+#define BLE_BLELL_ADV_PARAMS_TX_ADDR_Msk 0x1UL
+#define BLE_BLELL_ADV_PARAMS_ADV_TYPE_Pos 1UL
+#define BLE_BLELL_ADV_PARAMS_ADV_TYPE_Msk 0x6UL
+#define BLE_BLELL_ADV_PARAMS_ADV_FILT_POLICY_Pos 3UL
+#define BLE_BLELL_ADV_PARAMS_ADV_FILT_POLICY_Msk 0x18UL
+#define BLE_BLELL_ADV_PARAMS_ADV_CHANNEL_MAP_Pos 5UL
+#define BLE_BLELL_ADV_PARAMS_ADV_CHANNEL_MAP_Msk 0xE0UL
+#define BLE_BLELL_ADV_PARAMS_RX_ADDR_Pos 8UL
+#define BLE_BLELL_ADV_PARAMS_RX_ADDR_Msk 0x100UL
+#define BLE_BLELL_ADV_PARAMS_RX_SEC_ADDR_Pos 9UL
+#define BLE_BLELL_ADV_PARAMS_RX_SEC_ADDR_Msk 0x200UL
+#define BLE_BLELL_ADV_PARAMS_ADV_LOW_DUTY_CYCLE_Pos 10UL
+#define BLE_BLELL_ADV_PARAMS_ADV_LOW_DUTY_CYCLE_Msk 0x400UL
+#define BLE_BLELL_ADV_PARAMS_INITA_RPA_CHECK_Pos 11UL
+#define BLE_BLELL_ADV_PARAMS_INITA_RPA_CHECK_Msk 0x800UL
+#define BLE_BLELL_ADV_PARAMS_TX_ADDR_PRIV_Pos 12UL
+#define BLE_BLELL_ADV_PARAMS_TX_ADDR_PRIV_Msk 0x1000UL
+#define BLE_BLELL_ADV_PARAMS_ADV_RCV_IA_IN_PRIV_Pos 13UL
+#define BLE_BLELL_ADV_PARAMS_ADV_RCV_IA_IN_PRIV_Msk 0x2000UL
+#define BLE_BLELL_ADV_PARAMS_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV_Pos 14UL
+#define BLE_BLELL_ADV_PARAMS_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV_Msk 0x4000UL
+#define BLE_BLELL_ADV_PARAMS_RCV_TX_ADDR_Pos 15UL
+#define BLE_BLELL_ADV_PARAMS_RCV_TX_ADDR_Msk 0x8000UL
+/* BLE_BLELL.ADV_INTERVAL_TIMEOUT */
+#define BLE_BLELL_ADV_INTERVAL_TIMEOUT_ADV_INTERVAL_Pos 0UL
+#define BLE_BLELL_ADV_INTERVAL_TIMEOUT_ADV_INTERVAL_Msk 0x7FFFUL
+/* BLE_BLELL.ADV_INTR */
+#define BLE_BLELL_ADV_INTR_ADV_STRT_INTR_Pos 0UL
+#define BLE_BLELL_ADV_INTR_ADV_STRT_INTR_Msk 0x1UL
+#define BLE_BLELL_ADV_INTR_ADV_CLOSE_INTR_Pos 1UL
+#define BLE_BLELL_ADV_INTR_ADV_CLOSE_INTR_Msk 0x2UL
+#define BLE_BLELL_ADV_INTR_ADV_TX_INTR_Pos 2UL
+#define BLE_BLELL_ADV_INTR_ADV_TX_INTR_Msk 0x4UL
+#define BLE_BLELL_ADV_INTR_SCAN_RSP_TX_INTR_Pos 3UL
+#define BLE_BLELL_ADV_INTR_SCAN_RSP_TX_INTR_Msk 0x8UL
+#define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_INTR_Pos 4UL
+#define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_INTR_Msk 0x10UL
+#define BLE_BLELL_ADV_INTR_CONN_REQ_RX_INTR_Pos 5UL
+#define BLE_BLELL_ADV_INTR_CONN_REQ_RX_INTR_Msk 0x20UL
+#define BLE_BLELL_ADV_INTR_SLV_CONNECTED_Pos 6UL
+#define BLE_BLELL_ADV_INTR_SLV_CONNECTED_Msk 0x40UL
+#define BLE_BLELL_ADV_INTR_ADV_TIMEOUT_Pos 7UL
+#define BLE_BLELL_ADV_INTR_ADV_TIMEOUT_Msk 0x80UL
+#define BLE_BLELL_ADV_INTR_ADV_ON_Pos 8UL
+#define BLE_BLELL_ADV_INTR_ADV_ON_Msk 0x100UL
+#define BLE_BLELL_ADV_INTR_SLV_CONN_PEER_RPA_UNMCH_INTR_Pos 9UL
+#define BLE_BLELL_ADV_INTR_SLV_CONN_PEER_RPA_UNMCH_INTR_Msk 0x200UL
+#define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR_Pos 10UL
+#define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR_Msk 0x400UL
+#define BLE_BLELL_ADV_INTR_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 11UL
+#define BLE_BLELL_ADV_INTR_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x800UL
+#define BLE_BLELL_ADV_INTR_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 12UL
+#define BLE_BLELL_ADV_INTR_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x1000UL
+/* BLE_BLELL.ADV_NEXT_INSTANT */
+#define BLE_BLELL_ADV_NEXT_INSTANT_ADV_NEXT_INSTANT_Pos 0UL
+#define BLE_BLELL_ADV_NEXT_INSTANT_ADV_NEXT_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.SCAN_INTERVAL */
+#define BLE_BLELL_SCAN_INTERVAL_SCAN_INTERVAL_Pos 0UL
+#define BLE_BLELL_SCAN_INTERVAL_SCAN_INTERVAL_Msk 0xFFFFUL
+/* BLE_BLELL.SCAN_WINDOW */
+#define BLE_BLELL_SCAN_WINDOW_SCAN_WINDOW_Pos 0UL
+#define BLE_BLELL_SCAN_WINDOW_SCAN_WINDOW_Msk 0xFFFFUL
+/* BLE_BLELL.SCAN_PARAM */
+#define BLE_BLELL_SCAN_PARAM_TX_ADDR_Pos 0UL
+#define BLE_BLELL_SCAN_PARAM_TX_ADDR_Msk 0x1UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_TYPE_Pos 1UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_TYPE_Msk 0x6UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_FILT_POLICY_Pos 3UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_FILT_POLICY_Msk 0x18UL
+#define BLE_BLELL_SCAN_PARAM_DUP_FILT_EN_Pos 5UL
+#define BLE_BLELL_SCAN_PARAM_DUP_FILT_EN_Msk 0x20UL
+#define BLE_BLELL_SCAN_PARAM_DUP_FILT_CHK_ADV_DIR_Pos 6UL
+#define BLE_BLELL_SCAN_PARAM_DUP_FILT_CHK_ADV_DIR_Msk 0x40UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_RSP_ADVA_CHECK_Pos 7UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_RSP_ADVA_CHECK_Msk 0x80UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_RCV_IA_IN_PRIV_Pos 8UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_RCV_IA_IN_PRIV_Msk 0x100UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV_Pos 9UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV_Msk 0x200UL
+/* BLE_BLELL.SCAN_INTR */
+#define BLE_BLELL_SCAN_INTR_SCAN_STRT_INTR_Pos 0UL
+#define BLE_BLELL_SCAN_INTR_SCAN_STRT_INTR_Msk 0x1UL
+#define BLE_BLELL_SCAN_INTR_SCAN_CLOSE_INTR_Pos 1UL
+#define BLE_BLELL_SCAN_INTR_SCAN_CLOSE_INTR_Msk 0x2UL
+#define BLE_BLELL_SCAN_INTR_SCAN_TX_INTR_Pos 2UL
+#define BLE_BLELL_SCAN_INTR_SCAN_TX_INTR_Msk 0x4UL
+#define BLE_BLELL_SCAN_INTR_ADV_RX_INTR_Pos 3UL
+#define BLE_BLELL_SCAN_INTR_ADV_RX_INTR_Msk 0x8UL
+#define BLE_BLELL_SCAN_INTR_SCAN_RSP_RX_INTR_Pos 4UL
+#define BLE_BLELL_SCAN_INTR_SCAN_RSP_RX_INTR_Msk 0x10UL
+#define BLE_BLELL_SCAN_INTR_ADV_RX_PEER_RPA_UNMCH_INTR_Pos 5UL
+#define BLE_BLELL_SCAN_INTR_ADV_RX_PEER_RPA_UNMCH_INTR_Msk 0x20UL
+#define BLE_BLELL_SCAN_INTR_ADV_RX_SELF_RPA_UNMCH_INTR_Pos 6UL
+#define BLE_BLELL_SCAN_INTR_ADV_RX_SELF_RPA_UNMCH_INTR_Msk 0x40UL
+#define BLE_BLELL_SCAN_INTR_SCANA_TX_ADDR_NOT_SET_INTR_Pos 7UL
+#define BLE_BLELL_SCAN_INTR_SCANA_TX_ADDR_NOT_SET_INTR_Msk 0x80UL
+#define BLE_BLELL_SCAN_INTR_SCAN_ON_Pos 8UL
+#define BLE_BLELL_SCAN_INTR_SCAN_ON_Msk 0x100UL
+#define BLE_BLELL_SCAN_INTR_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 9UL
+#define BLE_BLELL_SCAN_INTR_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x200UL
+#define BLE_BLELL_SCAN_INTR_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 10UL
+#define BLE_BLELL_SCAN_INTR_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x400UL
+/* BLE_BLELL.SCAN_NEXT_INSTANT */
+#define BLE_BLELL_SCAN_NEXT_INSTANT_NEXT_SCAN_INSTANT_Pos 0UL
+#define BLE_BLELL_SCAN_NEXT_INSTANT_NEXT_SCAN_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_INTERVAL */
+#define BLE_BLELL_INIT_INTERVAL_INIT_SCAN_INTERVAL_Pos 0UL
+#define BLE_BLELL_INIT_INTERVAL_INIT_SCAN_INTERVAL_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_WINDOW */
+#define BLE_BLELL_INIT_WINDOW_INIT_SCAN_WINDOW_Pos 0UL
+#define BLE_BLELL_INIT_WINDOW_INIT_SCAN_WINDOW_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_PARAM */
+#define BLE_BLELL_INIT_PARAM_TX_ADDR_Pos 0UL
+#define BLE_BLELL_INIT_PARAM_TX_ADDR_Msk 0x1UL
+#define BLE_BLELL_INIT_PARAM_RX_ADDR__RX_TX_ADDR_Pos 1UL
+#define BLE_BLELL_INIT_PARAM_RX_ADDR__RX_TX_ADDR_Msk 0x2UL
+#define BLE_BLELL_INIT_PARAM_INIT_FILT_POLICY_Pos 3UL
+#define BLE_BLELL_INIT_PARAM_INIT_FILT_POLICY_Msk 0x8UL
+#define BLE_BLELL_INIT_PARAM_INIT_RCV_IA_IN_PRIV_Pos 4UL
+#define BLE_BLELL_INIT_PARAM_INIT_RCV_IA_IN_PRIV_Msk 0x10UL
+/* BLE_BLELL.INIT_INTR */
+#define BLE_BLELL_INIT_INTR_INIT_INTERVAL_EXPIRE_INTR_Pos 0UL
+#define BLE_BLELL_INIT_INTR_INIT_INTERVAL_EXPIRE_INTR_Msk 0x1UL
+#define BLE_BLELL_INIT_INTR_INIT_CLOSE_WINDOW_INR_Pos 1UL
+#define BLE_BLELL_INIT_INTR_INIT_CLOSE_WINDOW_INR_Msk 0x2UL
+#define BLE_BLELL_INIT_INTR_INIT_TX_START_INTR_Pos 2UL
+#define BLE_BLELL_INIT_INTR_INIT_TX_START_INTR_Msk 0x4UL
+#define BLE_BLELL_INIT_INTR_MASTER_CONN_CREATED_Pos 4UL
+#define BLE_BLELL_INIT_INTR_MASTER_CONN_CREATED_Msk 0x10UL
+#define BLE_BLELL_INIT_INTR_ADV_RX_SELF_ADDR_UNMCH_INTR_Pos 5UL
+#define BLE_BLELL_INIT_INTR_ADV_RX_SELF_ADDR_UNMCH_INTR_Msk 0x20UL
+#define BLE_BLELL_INIT_INTR_ADV_RX_PEER_ADDR_UNMCH_INTR_Pos 6UL
+#define BLE_BLELL_INIT_INTR_ADV_RX_PEER_ADDR_UNMCH_INTR_Msk 0x40UL
+#define BLE_BLELL_INIT_INTR_INITA_TX_ADDR_NOT_SET_INTR_Pos 7UL
+#define BLE_BLELL_INIT_INTR_INITA_TX_ADDR_NOT_SET_INTR_Msk 0x80UL
+#define BLE_BLELL_INIT_INTR_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 8UL
+#define BLE_BLELL_INIT_INTR_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x100UL
+#define BLE_BLELL_INIT_INTR_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 9UL
+#define BLE_BLELL_INIT_INTR_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x200UL
+/* BLE_BLELL.INIT_NEXT_INSTANT */
+#define BLE_BLELL_INIT_NEXT_INSTANT_INIT_NEXT_INSTANT_Pos 0UL
+#define BLE_BLELL_INIT_NEXT_INSTANT_INIT_NEXT_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.DEVICE_RAND_ADDR_L */
+#define BLE_BLELL_DEVICE_RAND_ADDR_L_DEVICE_RAND_ADDR_L_Pos 0UL
+#define BLE_BLELL_DEVICE_RAND_ADDR_L_DEVICE_RAND_ADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.DEVICE_RAND_ADDR_M */
+#define BLE_BLELL_DEVICE_RAND_ADDR_M_DEVICE_RAND_ADDR_M_Pos 0UL
+#define BLE_BLELL_DEVICE_RAND_ADDR_M_DEVICE_RAND_ADDR_M_Msk 0xFFFFUL
+/* BLE_BLELL.DEVICE_RAND_ADDR_H */
+#define BLE_BLELL_DEVICE_RAND_ADDR_H_DEVICE_RAND_ADDR_H_Pos 0UL
+#define BLE_BLELL_DEVICE_RAND_ADDR_H_DEVICE_RAND_ADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_ADDR_L */
+#define BLE_BLELL_PEER_ADDR_L_PEER_ADDR_L_Pos 0UL
+#define BLE_BLELL_PEER_ADDR_L_PEER_ADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_ADDR_M */
+#define BLE_BLELL_PEER_ADDR_M_PEER_ADDR_M_Pos 0UL
+#define BLE_BLELL_PEER_ADDR_M_PEER_ADDR_M_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_ADDR_H */
+#define BLE_BLELL_PEER_ADDR_H_PEER_ADDR_H_Pos 0UL
+#define BLE_BLELL_PEER_ADDR_H_PEER_ADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.WL_ADDR_TYPE */
+#define BLE_BLELL_WL_ADDR_TYPE_WL_ADDR_TYPE_Pos 0UL
+#define BLE_BLELL_WL_ADDR_TYPE_WL_ADDR_TYPE_Msk 0xFFFFUL
+/* BLE_BLELL.WL_ENABLE */
+#define BLE_BLELL_WL_ENABLE_WL_ENABLE_Pos 0UL
+#define BLE_BLELL_WL_ENABLE_WL_ENABLE_Msk 0xFFFFUL
+/* BLE_BLELL.TRANSMIT_WINDOW_OFFSET */
+#define BLE_BLELL_TRANSMIT_WINDOW_OFFSET_TX_WINDOW_OFFSET_Pos 0UL
+#define BLE_BLELL_TRANSMIT_WINDOW_OFFSET_TX_WINDOW_OFFSET_Msk 0xFFFFUL
+/* BLE_BLELL.TRANSMIT_WINDOW_SIZE */
+#define BLE_BLELL_TRANSMIT_WINDOW_SIZE_TX_WINDOW_SIZE_Pos 0UL
+#define BLE_BLELL_TRANSMIT_WINDOW_SIZE_TX_WINDOW_SIZE_Msk 0xFFUL
+/* BLE_BLELL.DATA_CHANNELS_L0 */
+#define BLE_BLELL_DATA_CHANNELS_L0_DATA_CHANNELS_L0_Pos 0UL
+#define BLE_BLELL_DATA_CHANNELS_L0_DATA_CHANNELS_L0_Msk 0xFFFFUL
+/* BLE_BLELL.DATA_CHANNELS_M0 */
+#define BLE_BLELL_DATA_CHANNELS_M0_DATA_CHANNELS_M0_Pos 0UL
+#define BLE_BLELL_DATA_CHANNELS_M0_DATA_CHANNELS_M0_Msk 0xFFFFUL
+/* BLE_BLELL.DATA_CHANNELS_H0 */
+#define BLE_BLELL_DATA_CHANNELS_H0_DATA_CHANNELS_H0_Pos 0UL
+#define BLE_BLELL_DATA_CHANNELS_H0_DATA_CHANNELS_H0_Msk 0x1FUL
+/* BLE_BLELL.DATA_CHANNELS_L1 */
+#define BLE_BLELL_DATA_CHANNELS_L1_DATA_CHANNELS_L1_Pos 0UL
+#define BLE_BLELL_DATA_CHANNELS_L1_DATA_CHANNELS_L1_Msk 0xFFFFUL
+/* BLE_BLELL.DATA_CHANNELS_M1 */
+#define BLE_BLELL_DATA_CHANNELS_M1_DATA_CHANNELS_M1_Pos 0UL
+#define BLE_BLELL_DATA_CHANNELS_M1_DATA_CHANNELS_M1_Msk 0xFFFFUL
+/* BLE_BLELL.DATA_CHANNELS_H1 */
+#define BLE_BLELL_DATA_CHANNELS_H1_DATA_CHANNELS_H1_Pos 0UL
+#define BLE_BLELL_DATA_CHANNELS_H1_DATA_CHANNELS_H1_Msk 0x1FUL
+/* BLE_BLELL.CONN_INTR */
+#define BLE_BLELL_CONN_INTR_CONN_CLOSED_Pos 0UL
+#define BLE_BLELL_CONN_INTR_CONN_CLOSED_Msk 0x1UL
+#define BLE_BLELL_CONN_INTR_CONN_ESTB_Pos 1UL
+#define BLE_BLELL_CONN_INTR_CONN_ESTB_Msk 0x2UL
+#define BLE_BLELL_CONN_INTR_MAP_UPDT_DONE_Pos 2UL
+#define BLE_BLELL_CONN_INTR_MAP_UPDT_DONE_Msk 0x4UL
+#define BLE_BLELL_CONN_INTR_START_CE_Pos 3UL
+#define BLE_BLELL_CONN_INTR_START_CE_Msk 0x8UL
+#define BLE_BLELL_CONN_INTR_CLOSE_CE_Pos 4UL
+#define BLE_BLELL_CONN_INTR_CLOSE_CE_Msk 0x10UL
+#define BLE_BLELL_CONN_INTR_CE_TX_ACK_Pos 5UL
+#define BLE_BLELL_CONN_INTR_CE_TX_ACK_Msk 0x20UL
+#define BLE_BLELL_CONN_INTR_CE_RX_Pos 6UL
+#define BLE_BLELL_CONN_INTR_CE_RX_Msk 0x40UL
+#define BLE_BLELL_CONN_INTR_CON_UPDT_DONE_Pos 7UL
+#define BLE_BLELL_CONN_INTR_CON_UPDT_DONE_Msk 0x80UL
+#define BLE_BLELL_CONN_INTR_DISCON_STATUS_Pos 8UL
+#define BLE_BLELL_CONN_INTR_DISCON_STATUS_Msk 0x700UL
+#define BLE_BLELL_CONN_INTR_RX_PDU_STATUS_Pos 11UL
+#define BLE_BLELL_CONN_INTR_RX_PDU_STATUS_Msk 0x3800UL
+#define BLE_BLELL_CONN_INTR_PING_TIMER_EXPIRD_INTR_Pos 14UL
+#define BLE_BLELL_CONN_INTR_PING_TIMER_EXPIRD_INTR_Msk 0x4000UL
+#define BLE_BLELL_CONN_INTR_PING_NEARLY_EXPIRD_INTR_Pos 15UL
+#define BLE_BLELL_CONN_INTR_PING_NEARLY_EXPIRD_INTR_Msk 0x8000UL
+/* BLE_BLELL.CONN_STATUS */
+#define BLE_BLELL_CONN_STATUS_RECEIVE_PACKET_COUNT_Pos 12UL
+#define BLE_BLELL_CONN_STATUS_RECEIVE_PACKET_COUNT_Msk 0xF000UL
+/* BLE_BLELL.CONN_INDEX */
+#define BLE_BLELL_CONN_INDEX_CONN_INDEX_Pos 0UL
+#define BLE_BLELL_CONN_INDEX_CONN_INDEX_Msk 0xFFFFUL
+/* BLE_BLELL.WAKEUP_CONFIG */
+#define BLE_BLELL_WAKEUP_CONFIG_OSC_STARTUP_DELAY_Pos 0UL
+#define BLE_BLELL_WAKEUP_CONFIG_OSC_STARTUP_DELAY_Msk 0xFFUL
+#define BLE_BLELL_WAKEUP_CONFIG_DSM_OFFSET_TO_WAKEUP_INSTANT_Pos 10UL
+#define BLE_BLELL_WAKEUP_CONFIG_DSM_OFFSET_TO_WAKEUP_INSTANT_Msk 0xFC00UL
+/* BLE_BLELL.WAKEUP_CONTROL */
+#define BLE_BLELL_WAKEUP_CONTROL_WAKEUP_INSTANT_Pos 0UL
+#define BLE_BLELL_WAKEUP_CONTROL_WAKEUP_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.CLOCK_CONFIG */
+#define BLE_BLELL_CLOCK_CONFIG_ADV_CLK_GATE_EN_Pos 0UL
+#define BLE_BLELL_CLOCK_CONFIG_ADV_CLK_GATE_EN_Msk 0x1UL
+#define BLE_BLELL_CLOCK_CONFIG_SCAN_CLK_GATE_EN_Pos 1UL
+#define BLE_BLELL_CLOCK_CONFIG_SCAN_CLK_GATE_EN_Msk 0x2UL
+#define BLE_BLELL_CLOCK_CONFIG_INIT_CLK_GATE_EN_Pos 2UL
+#define BLE_BLELL_CLOCK_CONFIG_INIT_CLK_GATE_EN_Msk 0x4UL
+#define BLE_BLELL_CLOCK_CONFIG_CONN_CLK_GATE_EN_Pos 3UL
+#define BLE_BLELL_CLOCK_CONFIG_CONN_CLK_GATE_EN_Msk 0x8UL
+#define BLE_BLELL_CLOCK_CONFIG_CORECLK_GATE_EN_Pos 4UL
+#define BLE_BLELL_CLOCK_CONFIG_CORECLK_GATE_EN_Msk 0x10UL
+#define BLE_BLELL_CLOCK_CONFIG_SYSCLK_GATE_EN_Pos 5UL
+#define BLE_BLELL_CLOCK_CONFIG_SYSCLK_GATE_EN_Msk 0x20UL
+#define BLE_BLELL_CLOCK_CONFIG_PHY_CLK_GATE_EN_Pos 6UL
+#define BLE_BLELL_CLOCK_CONFIG_PHY_CLK_GATE_EN_Msk 0x40UL
+#define BLE_BLELL_CLOCK_CONFIG_LLH_IDLE_Pos 7UL
+#define BLE_BLELL_CLOCK_CONFIG_LLH_IDLE_Msk 0x80UL
+#define BLE_BLELL_CLOCK_CONFIG_LPO_CLK_FREQ_SEL_Pos 8UL
+#define BLE_BLELL_CLOCK_CONFIG_LPO_CLK_FREQ_SEL_Msk 0x100UL
+#define BLE_BLELL_CLOCK_CONFIG_LPO_SEL_EXTERNAL_Pos 9UL
+#define BLE_BLELL_CLOCK_CONFIG_LPO_SEL_EXTERNAL_Msk 0x200UL
+#define BLE_BLELL_CLOCK_CONFIG_SM_AUTO_WKUP_EN_Pos 10UL
+#define BLE_BLELL_CLOCK_CONFIG_SM_AUTO_WKUP_EN_Msk 0x400UL
+#define BLE_BLELL_CLOCK_CONFIG_SM_INTR_EN_Pos 12UL
+#define BLE_BLELL_CLOCK_CONFIG_SM_INTR_EN_Msk 0x1000UL
+#define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_AUTO_WKUP_DISABLE_Pos 13UL
+#define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_AUTO_WKUP_DISABLE_Msk 0x2000UL
+#define BLE_BLELL_CLOCK_CONFIG_SLEEP_MODE_EN_Pos 14UL
+#define BLE_BLELL_CLOCK_CONFIG_SLEEP_MODE_EN_Msk 0x4000UL
+#define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_MODE_EN_Pos 15UL
+#define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_MODE_EN_Msk 0x8000UL
+/* BLE_BLELL.TIM_COUNTER_L */
+#define BLE_BLELL_TIM_COUNTER_L_TIM_REF_CLOCK_Pos 0UL
+#define BLE_BLELL_TIM_COUNTER_L_TIM_REF_CLOCK_Msk 0xFFFFUL
+/* BLE_BLELL.WAKEUP_CONFIG_EXTD */
+#define BLE_BLELL_WAKEUP_CONFIG_EXTD_DSM_LF_OFFSET_Pos 0UL
+#define BLE_BLELL_WAKEUP_CONFIG_EXTD_DSM_LF_OFFSET_Msk 0x1FUL
+/* BLE_BLELL.POC_REG__TIM_CONTROL */
+#define BLE_BLELL_POC_REG__TIM_CONTROL_BB_CLK_FREQ_MINUS_1_Pos 3UL
+#define BLE_BLELL_POC_REG__TIM_CONTROL_BB_CLK_FREQ_MINUS_1_Msk 0xF8UL
+#define BLE_BLELL_POC_REG__TIM_CONTROL_START_SLOT_OFFSET_Pos 8UL
+#define BLE_BLELL_POC_REG__TIM_CONTROL_START_SLOT_OFFSET_Msk 0xF00UL
+/* BLE_BLELL.ADV_TX_DATA_FIFO */
+#define BLE_BLELL_ADV_TX_DATA_FIFO_ADV_TX_DATA_Pos 0UL
+#define BLE_BLELL_ADV_TX_DATA_FIFO_ADV_TX_DATA_Msk 0xFFFFUL
+/* BLE_BLELL.ADV_SCN_RSP_TX_FIFO */
+#define BLE_BLELL_ADV_SCN_RSP_TX_FIFO_SCAN_RSP_DATA_Pos 0UL
+#define BLE_BLELL_ADV_SCN_RSP_TX_FIFO_SCAN_RSP_DATA_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_SCN_ADV_RX_FIFO */
+#define BLE_BLELL_INIT_SCN_ADV_RX_FIFO_ADV_SCAN_RSP_RX_DATA_Pos 0UL
+#define BLE_BLELL_INIT_SCN_ADV_RX_FIFO_ADV_SCAN_RSP_RX_DATA_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_INTERVAL */
+#define BLE_BLELL_CONN_INTERVAL_CONNECTION_INTERVAL_Pos 0UL
+#define BLE_BLELL_CONN_INTERVAL_CONNECTION_INTERVAL_Msk 0xFFFFUL
+/* BLE_BLELL.SUP_TIMEOUT */
+#define BLE_BLELL_SUP_TIMEOUT_SUPERVISION_TIMEOUT_Pos 0UL
+#define BLE_BLELL_SUP_TIMEOUT_SUPERVISION_TIMEOUT_Msk 0xFFFFUL
+/* BLE_BLELL.SLAVE_LATENCY */
+#define BLE_BLELL_SLAVE_LATENCY_SLAVE_LATENCY_Pos 0UL
+#define BLE_BLELL_SLAVE_LATENCY_SLAVE_LATENCY_Msk 0xFFFFUL
+/* BLE_BLELL.CE_LENGTH */
+#define BLE_BLELL_CE_LENGTH_CONNECTION_EVENT_LENGTH_Pos 0UL
+#define BLE_BLELL_CE_LENGTH_CONNECTION_EVENT_LENGTH_Msk 0xFFFFUL
+/* BLE_BLELL.PDU_ACCESS_ADDR_L_REGISTER */
+#define BLE_BLELL_PDU_ACCESS_ADDR_L_REGISTER_PDU_ACCESS_ADDRESS_LOWER_BITS_Pos 0UL
+#define BLE_BLELL_PDU_ACCESS_ADDR_L_REGISTER_PDU_ACCESS_ADDRESS_LOWER_BITS_Msk 0xFFFFUL
+/* BLE_BLELL.PDU_ACCESS_ADDR_H_REGISTER */
+#define BLE_BLELL_PDU_ACCESS_ADDR_H_REGISTER_PDU_ACCESS_ADDRESS_HIGHER_BITS_Pos 0UL
+#define BLE_BLELL_PDU_ACCESS_ADDR_H_REGISTER_PDU_ACCESS_ADDRESS_HIGHER_BITS_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_CE_INSTANT */
+#define BLE_BLELL_CONN_CE_INSTANT_CE_INSTANT_Pos 0UL
+#define BLE_BLELL_CONN_CE_INSTANT_CE_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.CE_CNFG_STS_REGISTER */
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_INDEX_LAST_ACK_INDEX_Pos 0UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_INDEX_LAST_ACK_INDEX_Msk 0xFUL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_HEAD_UP_Pos 4UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_HEAD_UP_Msk 0x10UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_SPARE_Pos 5UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_SPARE_Msk 0x20UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_MD_Pos 6UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_MD_Msk 0x40UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_MAP_INDEX__CURR_INDEX_Pos 7UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_MAP_INDEX__CURR_INDEX_Msk 0x80UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_PAUSE_DATA_Pos 8UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_PAUSE_DATA_Msk 0x100UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_CONN_ACTIVE_Pos 10UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_CONN_ACTIVE_Msk 0x400UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_CURRENT_PDU_INDEX_Pos 12UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_CURRENT_PDU_INDEX_Msk 0xF000UL
+/* BLE_BLELL.NEXT_CE_INSTANT */
+#define BLE_BLELL_NEXT_CE_INSTANT_NEXT_CE_INSTANT_Pos 0UL
+#define BLE_BLELL_NEXT_CE_INSTANT_NEXT_CE_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_CE_COUNTER */
+#define BLE_BLELL_CONN_CE_COUNTER_CONNECTION_EVENT_COUNTER_Pos 0UL
+#define BLE_BLELL_CONN_CE_COUNTER_CONNECTION_EVENT_COUNTER_Msk 0xFFFFUL
+/* BLE_BLELL.DATA_LIST_SENT_UPDATE__STATUS */
+#define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_LIST_INDEX__TX_SENT_3_0_Pos 0UL
+#define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_LIST_INDEX__TX_SENT_3_0_Msk 0xFUL
+#define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_SET_CLEAR_Pos 7UL
+#define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_SET_CLEAR_Msk 0x80UL
+/* BLE_BLELL.DATA_LIST_ACK_UPDATE__STATUS */
+#define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_LIST_INDEX__TX_ACK_3_0_Pos 0UL
+#define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_LIST_INDEX__TX_ACK_3_0_Msk 0xFUL
+#define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_SET_CLEAR_Pos 7UL
+#define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_SET_CLEAR_Msk 0x80UL
+/* BLE_BLELL.CE_CNFG_STS_REGISTER_EXT */
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_TX_2M_Pos 0UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_TX_2M_Msk 0x1UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_RX_2M_Pos 1UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_RX_2M_Msk 0x2UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_SN_Pos 2UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_SN_Msk 0x4UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_NESN_Pos 3UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_NESN_Msk 0x8UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_LAST_UNMAPPED_CHANNEL_Pos 8UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_LAST_UNMAPPED_CHANNEL_Msk 0x3F00UL
+/* BLE_BLELL.CONN_EXT_INTR */
+#define BLE_BLELL_CONN_EXT_INTR_DATARATE_UPDATE_Pos 0UL
+#define BLE_BLELL_CONN_EXT_INTR_DATARATE_UPDATE_Msk 0x1UL
+#define BLE_BLELL_CONN_EXT_INTR_EARLY_INTR_Pos 1UL
+#define BLE_BLELL_CONN_EXT_INTR_EARLY_INTR_Msk 0x2UL
+#define BLE_BLELL_CONN_EXT_INTR_GEN_TIMER_INTR_Pos 2UL
+#define BLE_BLELL_CONN_EXT_INTR_GEN_TIMER_INTR_Msk 0x4UL
+/* BLE_BLELL.CONN_EXT_INTR_MASK */
+#define BLE_BLELL_CONN_EXT_INTR_MASK_DATARATE_UPDATE_Pos 0UL
+#define BLE_BLELL_CONN_EXT_INTR_MASK_DATARATE_UPDATE_Msk 0x1UL
+#define BLE_BLELL_CONN_EXT_INTR_MASK_EARLY_INTR_Pos 1UL
+#define BLE_BLELL_CONN_EXT_INTR_MASK_EARLY_INTR_Msk 0x2UL
+#define BLE_BLELL_CONN_EXT_INTR_MASK_GEN_TIMER_INTR_Pos 2UL
+#define BLE_BLELL_CONN_EXT_INTR_MASK_GEN_TIMER_INTR_Msk 0x4UL
+/* BLE_BLELL.DATA_MEM_DESCRIPTOR */
+#define BLE_BLELL_DATA_MEM_DESCRIPTOR_LLID_Pos 0UL
+#define BLE_BLELL_DATA_MEM_DESCRIPTOR_LLID_Msk 0x3UL
+#define BLE_BLELL_DATA_MEM_DESCRIPTOR_DATA_LENGTH_Pos 2UL
+#define BLE_BLELL_DATA_MEM_DESCRIPTOR_DATA_LENGTH_Msk 0x3FCUL
+/* BLE_BLELL.WINDOW_WIDEN_INTVL */
+#define BLE_BLELL_WINDOW_WIDEN_INTVL_WINDOW_WIDEN_INTVL_Pos 0UL
+#define BLE_BLELL_WINDOW_WIDEN_INTVL_WINDOW_WIDEN_INTVL_Msk 0xFFFUL
+/* BLE_BLELL.WINDOW_WIDEN_WINOFF */
+#define BLE_BLELL_WINDOW_WIDEN_WINOFF_WINDOW_WIDEN_WINOFF_Pos 0UL
+#define BLE_BLELL_WINDOW_WIDEN_WINOFF_WINDOW_WIDEN_WINOFF_Msk 0xFFFUL
+/* BLE_BLELL.LE_RF_TEST_MODE */
+#define BLE_BLELL_LE_RF_TEST_MODE_TEST_FREQUENCY_Pos 0UL
+#define BLE_BLELL_LE_RF_TEST_MODE_TEST_FREQUENCY_Msk 0x3FUL
+#define BLE_BLELL_LE_RF_TEST_MODE_DTM_STATUS__DTM_CONT_RXEN_Pos 6UL
+#define BLE_BLELL_LE_RF_TEST_MODE_DTM_STATUS__DTM_CONT_RXEN_Msk 0x40UL
+#define BLE_BLELL_LE_RF_TEST_MODE_PKT_PAYLOAD_Pos 7UL
+#define BLE_BLELL_LE_RF_TEST_MODE_PKT_PAYLOAD_Msk 0x380UL
+#define BLE_BLELL_LE_RF_TEST_MODE_DTM_CONT_TXEN_Pos 13UL
+#define BLE_BLELL_LE_RF_TEST_MODE_DTM_CONT_TXEN_Msk 0x2000UL
+#define BLE_BLELL_LE_RF_TEST_MODE_DTM_DATA_2MBPS_Pos 15UL
+#define BLE_BLELL_LE_RF_TEST_MODE_DTM_DATA_2MBPS_Msk 0x8000UL
+/* BLE_BLELL.DTM_RX_PKT_COUNT */
+#define BLE_BLELL_DTM_RX_PKT_COUNT_RX_PACKET_COUNT_Pos 0UL
+#define BLE_BLELL_DTM_RX_PKT_COUNT_RX_PACKET_COUNT_Msk 0xFFFFUL
+/* BLE_BLELL.LE_RF_TEST_MODE_EXT */
+#define BLE_BLELL_LE_RF_TEST_MODE_EXT_DTM_PACKET_LENGTH_Pos 0UL
+#define BLE_BLELL_LE_RF_TEST_MODE_EXT_DTM_PACKET_LENGTH_Msk 0xFFUL
+/* BLE_BLELL.TXRX_HOP */
+#define BLE_BLELL_TXRX_HOP_HOP_CH_TX_Pos 0UL
+#define BLE_BLELL_TXRX_HOP_HOP_CH_TX_Msk 0x7FUL
+#define BLE_BLELL_TXRX_HOP_HOP_CH_RX_Pos 8UL
+#define BLE_BLELL_TXRX_HOP_HOP_CH_RX_Msk 0x7F00UL
+/* BLE_BLELL.TX_RX_ON_DELAY */
+#define BLE_BLELL_TX_RX_ON_DELAY_RXON_DELAY_Pos 0UL
+#define BLE_BLELL_TX_RX_ON_DELAY_RXON_DELAY_Msk 0xFFUL
+#define BLE_BLELL_TX_RX_ON_DELAY_TXON_DELAY_Pos 8UL
+#define BLE_BLELL_TX_RX_ON_DELAY_TXON_DELAY_Msk 0xFF00UL
+/* BLE_BLELL.ADV_ACCADDR_L */
+#define BLE_BLELL_ADV_ACCADDR_L_ADV_ACCADDR_L_Pos 0UL
+#define BLE_BLELL_ADV_ACCADDR_L_ADV_ACCADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.ADV_ACCADDR_H */
+#define BLE_BLELL_ADV_ACCADDR_H_ADV_ACCADDR_H_Pos 0UL
+#define BLE_BLELL_ADV_ACCADDR_H_ADV_ACCADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.ADV_CH_TX_POWER_LVL_LS */
+#define BLE_BLELL_ADV_CH_TX_POWER_LVL_LS_ADV_TRANSMIT_POWER_LVL_LS_Pos 0UL
+#define BLE_BLELL_ADV_CH_TX_POWER_LVL_LS_ADV_TRANSMIT_POWER_LVL_LS_Msk 0xFFFFUL
+/* BLE_BLELL.ADV_CH_TX_POWER_LVL_MS */
+#define BLE_BLELL_ADV_CH_TX_POWER_LVL_MS_ADV_TRANSMIT_POWER_LVL_MS_Pos 0UL
+#define BLE_BLELL_ADV_CH_TX_POWER_LVL_MS_ADV_TRANSMIT_POWER_LVL_MS_Msk 0x3UL
+/* BLE_BLELL.CONN_CH_TX_POWER_LVL_LS */
+#define BLE_BLELL_CONN_CH_TX_POWER_LVL_LS_CONNCH_TRANSMIT_POWER_LVL_LS_Pos 0UL
+#define BLE_BLELL_CONN_CH_TX_POWER_LVL_LS_CONNCH_TRANSMIT_POWER_LVL_LS_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_CH_TX_POWER_LVL_MS */
+#define BLE_BLELL_CONN_CH_TX_POWER_LVL_MS_CONNCH_TRANSMIT_POWER_LVL_MS_Pos 0UL
+#define BLE_BLELL_CONN_CH_TX_POWER_LVL_MS_CONNCH_TRANSMIT_POWER_LVL_MS_Msk 0x3UL
+/* BLE_BLELL.DEV_PUB_ADDR_L */
+#define BLE_BLELL_DEV_PUB_ADDR_L_DEV_PUB_ADDR_L_Pos 0UL
+#define BLE_BLELL_DEV_PUB_ADDR_L_DEV_PUB_ADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.DEV_PUB_ADDR_M */
+#define BLE_BLELL_DEV_PUB_ADDR_M_DEV_PUB_ADDR_M_Pos 0UL
+#define BLE_BLELL_DEV_PUB_ADDR_M_DEV_PUB_ADDR_M_Msk 0xFFFFUL
+/* BLE_BLELL.DEV_PUB_ADDR_H */
+#define BLE_BLELL_DEV_PUB_ADDR_H_DEV_PUB_ADDR_H_Pos 0UL
+#define BLE_BLELL_DEV_PUB_ADDR_H_DEV_PUB_ADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.OFFSET_TO_FIRST_INSTANT */
+#define BLE_BLELL_OFFSET_TO_FIRST_INSTANT_OFFSET_TO_FIRST_EVENT_Pos 0UL
+#define BLE_BLELL_OFFSET_TO_FIRST_INSTANT_OFFSET_TO_FIRST_EVENT_Msk 0xFFFFUL
+/* BLE_BLELL.ADV_CONFIG */
+#define BLE_BLELL_ADV_CONFIG_ADV_STRT_EN_Pos 0UL
+#define BLE_BLELL_ADV_CONFIG_ADV_STRT_EN_Msk 0x1UL
+#define BLE_BLELL_ADV_CONFIG_ADV_CLS_EN_Pos 1UL
+#define BLE_BLELL_ADV_CONFIG_ADV_CLS_EN_Msk 0x2UL
+#define BLE_BLELL_ADV_CONFIG_ADV_TX_EN_Pos 2UL
+#define BLE_BLELL_ADV_CONFIG_ADV_TX_EN_Msk 0x4UL
+#define BLE_BLELL_ADV_CONFIG_SCN_RSP_TX_EN_Pos 3UL
+#define BLE_BLELL_ADV_CONFIG_SCN_RSP_TX_EN_Msk 0x8UL
+#define BLE_BLELL_ADV_CONFIG_ADV_SCN_REQ_RX_EN_Pos 4UL
+#define BLE_BLELL_ADV_CONFIG_ADV_SCN_REQ_RX_EN_Msk 0x10UL
+#define BLE_BLELL_ADV_CONFIG_ADV_CONN_REQ_RX_EN_Pos 5UL
+#define BLE_BLELL_ADV_CONFIG_ADV_CONN_REQ_RX_EN_Msk 0x20UL
+#define BLE_BLELL_ADV_CONFIG_SLV_CONNECTED_EN_Pos 6UL
+#define BLE_BLELL_ADV_CONFIG_SLV_CONNECTED_EN_Msk 0x40UL
+#define BLE_BLELL_ADV_CONFIG_ADV_TIMEOUT_EN_Pos 7UL
+#define BLE_BLELL_ADV_CONFIG_ADV_TIMEOUT_EN_Msk 0x80UL
+#define BLE_BLELL_ADV_CONFIG_ADV_RAND_DISABLE_Pos 8UL
+#define BLE_BLELL_ADV_CONFIG_ADV_RAND_DISABLE_Msk 0x100UL
+#define BLE_BLELL_ADV_CONFIG_ADV_SCN_PEER_RPA_UNMCH_EN_Pos 9UL
+#define BLE_BLELL_ADV_CONFIG_ADV_SCN_PEER_RPA_UNMCH_EN_Msk 0x200UL
+#define BLE_BLELL_ADV_CONFIG_ADV_CONN_PEER_RPA_UNMCH_EN_Pos 10UL
+#define BLE_BLELL_ADV_CONFIG_ADV_CONN_PEER_RPA_UNMCH_EN_Msk 0x400UL
+#define BLE_BLELL_ADV_CONFIG_ADV_PKT_INTERVAL_Pos 11UL
+#define BLE_BLELL_ADV_CONFIG_ADV_PKT_INTERVAL_Msk 0xF800UL
+/* BLE_BLELL.SCAN_CONFIG */
+#define BLE_BLELL_SCAN_CONFIG_SCN_STRT_EN_Pos 0UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_STRT_EN_Msk 0x1UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_CLOSE_EN_Pos 1UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_CLOSE_EN_Msk 0x2UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_TX_EN_Pos 2UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_TX_EN_Msk 0x4UL
+#define BLE_BLELL_SCAN_CONFIG_ADV_RX_EN_Pos 3UL
+#define BLE_BLELL_SCAN_CONFIG_ADV_RX_EN_Msk 0x8UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_RSP_RX_EN_Pos 4UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_RSP_RX_EN_Msk 0x10UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN_Pos 5UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN_Msk 0x20UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN_Pos 6UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN_Msk 0x40UL
+#define BLE_BLELL_SCAN_CONFIG_SCANA_TX_ADDR_NOT_SET_INTR_EN_Pos 7UL
+#define BLE_BLELL_SCAN_CONFIG_SCANA_TX_ADDR_NOT_SET_INTR_EN_Msk 0x80UL
+#define BLE_BLELL_SCAN_CONFIG_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN_Pos 8UL
+#define BLE_BLELL_SCAN_CONFIG_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN_Msk 0x100UL
+#define BLE_BLELL_SCAN_CONFIG_BACKOFF_ENABLE_Pos 11UL
+#define BLE_BLELL_SCAN_CONFIG_BACKOFF_ENABLE_Msk 0x800UL
+#define BLE_BLELL_SCAN_CONFIG_SCAN_CHANNEL_MAP_Pos 13UL
+#define BLE_BLELL_SCAN_CONFIG_SCAN_CHANNEL_MAP_Msk 0xE000UL
+/* BLE_BLELL.INIT_CONFIG */
+#define BLE_BLELL_INIT_CONFIG_INIT_STRT_EN_Pos 0UL
+#define BLE_BLELL_INIT_CONFIG_INIT_STRT_EN_Msk 0x1UL
+#define BLE_BLELL_INIT_CONFIG_INIT_CLOSE_EN_Pos 1UL
+#define BLE_BLELL_INIT_CONFIG_INIT_CLOSE_EN_Msk 0x2UL
+#define BLE_BLELL_INIT_CONFIG_CONN_REQ_TX_EN_Pos 2UL
+#define BLE_BLELL_INIT_CONFIG_CONN_REQ_TX_EN_Msk 0x4UL
+#define BLE_BLELL_INIT_CONFIG_CONN_CREATED_Pos 4UL
+#define BLE_BLELL_INIT_CONFIG_CONN_CREATED_Msk 0x10UL
+#define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN_Pos 5UL
+#define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN_Msk 0x20UL
+#define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN_Pos 6UL
+#define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN_Msk 0x40UL
+#define BLE_BLELL_INIT_CONFIG_INITA_TX_ADDR_NOT_SET_INTR_EN_Pos 7UL
+#define BLE_BLELL_INIT_CONFIG_INITA_TX_ADDR_NOT_SET_INTR_EN_Msk 0x80UL
+#define BLE_BLELL_INIT_CONFIG_INIT_CHANNEL_MAP_Pos 13UL
+#define BLE_BLELL_INIT_CONFIG_INIT_CHANNEL_MAP_Msk 0xE000UL
+/* BLE_BLELL.CONN_CONFIG */
+#define BLE_BLELL_CONN_CONFIG_RX_PKT_LIMIT_Pos 0UL
+#define BLE_BLELL_CONN_CONFIG_RX_PKT_LIMIT_Msk 0xFUL
+#define BLE_BLELL_CONN_CONFIG_RX_INTR_THRESHOLD_Pos 4UL
+#define BLE_BLELL_CONN_CONFIG_RX_INTR_THRESHOLD_Msk 0xF0UL
+#define BLE_BLELL_CONN_CONFIG_MD_BIT_CLEAR_Pos 8UL
+#define BLE_BLELL_CONN_CONFIG_MD_BIT_CLEAR_Msk 0x100UL
+#define BLE_BLELL_CONN_CONFIG_DSM_SLOT_VARIANCE_Pos 11UL
+#define BLE_BLELL_CONN_CONFIG_DSM_SLOT_VARIANCE_Msk 0x800UL
+#define BLE_BLELL_CONN_CONFIG_SLV_MD_CONFIG_Pos 12UL
+#define BLE_BLELL_CONN_CONFIG_SLV_MD_CONFIG_Msk 0x1000UL
+#define BLE_BLELL_CONN_CONFIG_EXTEND_CU_TX_WIN_Pos 13UL
+#define BLE_BLELL_CONN_CONFIG_EXTEND_CU_TX_WIN_Msk 0x2000UL
+#define BLE_BLELL_CONN_CONFIG_MASK_SUTO_AT_UPDT_Pos 14UL
+#define BLE_BLELL_CONN_CONFIG_MASK_SUTO_AT_UPDT_Msk 0x4000UL
+#define BLE_BLELL_CONN_CONFIG_CONN_REQ_1SLOT_EARLY_Pos 15UL
+#define BLE_BLELL_CONN_CONFIG_CONN_REQ_1SLOT_EARLY_Msk 0x8000UL
+/* BLE_BLELL.CONN_PARAM1 */
+#define BLE_BLELL_CONN_PARAM1_SCA_PARAM_Pos 0UL
+#define BLE_BLELL_CONN_PARAM1_SCA_PARAM_Msk 0x7UL
+#define BLE_BLELL_CONN_PARAM1_HOP_INCREMENT_PARAM_Pos 3UL
+#define BLE_BLELL_CONN_PARAM1_HOP_INCREMENT_PARAM_Msk 0xF8UL
+#define BLE_BLELL_CONN_PARAM1_CRC_INIT_L_Pos 8UL
+#define BLE_BLELL_CONN_PARAM1_CRC_INIT_L_Msk 0xFF00UL
+/* BLE_BLELL.CONN_PARAM2 */
+#define BLE_BLELL_CONN_PARAM2_CRC_INIT_H_Pos 0UL
+#define BLE_BLELL_CONN_PARAM2_CRC_INIT_H_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_INTR_MASK */
+#define BLE_BLELL_CONN_INTR_MASK_CONN_CL_INT_EN_Pos 0UL
+#define BLE_BLELL_CONN_INTR_MASK_CONN_CL_INT_EN_Msk 0x1UL
+#define BLE_BLELL_CONN_INTR_MASK_CONN_ESTB_INT_EN_Pos 1UL
+#define BLE_BLELL_CONN_INTR_MASK_CONN_ESTB_INT_EN_Msk 0x2UL
+#define BLE_BLELL_CONN_INTR_MASK_MAP_UPDT_INT_EN_Pos 2UL
+#define BLE_BLELL_CONN_INTR_MASK_MAP_UPDT_INT_EN_Msk 0x4UL
+#define BLE_BLELL_CONN_INTR_MASK_START_CE_INT_EN_Pos 3UL
+#define BLE_BLELL_CONN_INTR_MASK_START_CE_INT_EN_Msk 0x8UL
+#define BLE_BLELL_CONN_INTR_MASK_CLOSE_CE_INT_EN_Pos 4UL
+#define BLE_BLELL_CONN_INTR_MASK_CLOSE_CE_INT_EN_Msk 0x10UL
+#define BLE_BLELL_CONN_INTR_MASK_CE_TX_ACK_INT_EN_Pos 5UL
+#define BLE_BLELL_CONN_INTR_MASK_CE_TX_ACK_INT_EN_Msk 0x20UL
+#define BLE_BLELL_CONN_INTR_MASK_CE_RX_INT_EN_Pos 6UL
+#define BLE_BLELL_CONN_INTR_MASK_CE_RX_INT_EN_Msk 0x40UL
+#define BLE_BLELL_CONN_INTR_MASK_CONN_UPDATE_INTR_EN_Pos 7UL
+#define BLE_BLELL_CONN_INTR_MASK_CONN_UPDATE_INTR_EN_Msk 0x80UL
+#define BLE_BLELL_CONN_INTR_MASK_RX_GOOD_PDU_INT_EN_Pos 8UL
+#define BLE_BLELL_CONN_INTR_MASK_RX_GOOD_PDU_INT_EN_Msk 0x100UL
+#define BLE_BLELL_CONN_INTR_MASK_RX_BAD_PDU_INT_EN_Pos 9UL
+#define BLE_BLELL_CONN_INTR_MASK_RX_BAD_PDU_INT_EN_Msk 0x200UL
+#define BLE_BLELL_CONN_INTR_MASK_CE_CLOSE_NULL_RX_INT_EN_Pos 13UL
+#define BLE_BLELL_CONN_INTR_MASK_CE_CLOSE_NULL_RX_INT_EN_Msk 0x2000UL
+#define BLE_BLELL_CONN_INTR_MASK_PING_TIMER_EXPIRD_INTR_Pos 14UL
+#define BLE_BLELL_CONN_INTR_MASK_PING_TIMER_EXPIRD_INTR_Msk 0x4000UL
+#define BLE_BLELL_CONN_INTR_MASK_PING_NEARLY_EXPIRD_INTR_Pos 15UL
+#define BLE_BLELL_CONN_INTR_MASK_PING_NEARLY_EXPIRD_INTR_Msk 0x8000UL
+/* BLE_BLELL.SLAVE_TIMING_CONTROL */
+#define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_SET_VAL_Pos 0UL
+#define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_SET_VAL_Msk 0xFFUL
+#define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_ADJ_VAL_Pos 8UL
+#define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_ADJ_VAL_Msk 0xFF00UL
+/* BLE_BLELL.RECEIVE_TRIG_CTRL */
+#define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_THRESHOLD_Pos 0UL
+#define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_THRESHOLD_Msk 0x3FUL
+#define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_TIMEOUT_Pos 8UL
+#define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_TIMEOUT_Msk 0xFF00UL
+/* BLE_BLELL.LL_DBG_1 */
+#define BLE_BLELL_LL_DBG_1_CONN_RX_WR_PTR_Pos 0UL
+#define BLE_BLELL_LL_DBG_1_CONN_RX_WR_PTR_Msk 0x3FFUL
+/* BLE_BLELL.LL_DBG_2 */
+#define BLE_BLELL_LL_DBG_2_CONN_RX_RD_PTR_Pos 0UL
+#define BLE_BLELL_LL_DBG_2_CONN_RX_RD_PTR_Msk 0x3FFUL
+/* BLE_BLELL.LL_DBG_3 */
+#define BLE_BLELL_LL_DBG_3_CONN_RX_WR_PTR_STORE_Pos 0UL
+#define BLE_BLELL_LL_DBG_3_CONN_RX_WR_PTR_STORE_Msk 0x3FFUL
+/* BLE_BLELL.LL_DBG_4 */
+#define BLE_BLELL_LL_DBG_4_CONNECTION_FSM_STATE_Pos 0UL
+#define BLE_BLELL_LL_DBG_4_CONNECTION_FSM_STATE_Msk 0xFUL
+#define BLE_BLELL_LL_DBG_4_SLAVE_LATENCY_FSM_STATE_Pos 4UL
+#define BLE_BLELL_LL_DBG_4_SLAVE_LATENCY_FSM_STATE_Msk 0x30UL
+#define BLE_BLELL_LL_DBG_4_ADVERTISER_FSM_STATE_Pos 6UL
+#define BLE_BLELL_LL_DBG_4_ADVERTISER_FSM_STATE_Msk 0x7C0UL
+/* BLE_BLELL.LL_DBG_5 */
+#define BLE_BLELL_LL_DBG_5_INIT_FSM_STATE_Pos 0UL
+#define BLE_BLELL_LL_DBG_5_INIT_FSM_STATE_Msk 0x1FUL
+#define BLE_BLELL_LL_DBG_5_SCAN_FSM_STATE_Pos 5UL
+#define BLE_BLELL_LL_DBG_5_SCAN_FSM_STATE_Msk 0x3E0UL
+/* BLE_BLELL.LL_DBG_6 */
+#define BLE_BLELL_LL_DBG_6_ADV_TX_WR_PTR_Pos 0UL
+#define BLE_BLELL_LL_DBG_6_ADV_TX_WR_PTR_Msk 0xFUL
+#define BLE_BLELL_LL_DBG_6_SCAN_RSP_TX_WR_PTR_Pos 4UL
+#define BLE_BLELL_LL_DBG_6_SCAN_RSP_TX_WR_PTR_Msk 0xF0UL
+#define BLE_BLELL_LL_DBG_6_ADV_TX_RD_PTR_Pos 8UL
+#define BLE_BLELL_LL_DBG_6_ADV_TX_RD_PTR_Msk 0x3F00UL
+/* BLE_BLELL.LL_DBG_7 */
+#define BLE_BLELL_LL_DBG_7_ADV_RX_WR_PTR_Pos 0UL
+#define BLE_BLELL_LL_DBG_7_ADV_RX_WR_PTR_Msk 0x7FUL
+#define BLE_BLELL_LL_DBG_7_ADV_RX_RD_PTR_Pos 7UL
+#define BLE_BLELL_LL_DBG_7_ADV_RX_RD_PTR_Msk 0x3F80UL
+/* BLE_BLELL.LL_DBG_8 */
+#define BLE_BLELL_LL_DBG_8_ADV_RX_WR_PTR_STORE_Pos 0UL
+#define BLE_BLELL_LL_DBG_8_ADV_RX_WR_PTR_STORE_Msk 0x7FUL
+#define BLE_BLELL_LL_DBG_8_WLF_PTR_Pos 7UL
+#define BLE_BLELL_LL_DBG_8_WLF_PTR_Msk 0x3F80UL
+/* BLE_BLELL.LL_DBG_9 */
+#define BLE_BLELL_LL_DBG_9_WINDOW_WIDEN_Pos 0UL
+#define BLE_BLELL_LL_DBG_9_WINDOW_WIDEN_Msk 0xFFFFUL
+/* BLE_BLELL.LL_DBG_10 */
+#define BLE_BLELL_LL_DBG_10_RF_CHANNEL_NUM_Pos 0UL
+#define BLE_BLELL_LL_DBG_10_RF_CHANNEL_NUM_Msk 0x3FUL
+/* BLE_BLELL.PEER_ADDR_INIT_L */
+#define BLE_BLELL_PEER_ADDR_INIT_L_PEER_ADDR_L_Pos 0UL
+#define BLE_BLELL_PEER_ADDR_INIT_L_PEER_ADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_ADDR_INIT_M */
+#define BLE_BLELL_PEER_ADDR_INIT_M_PEER_ADDR_M_Pos 0UL
+#define BLE_BLELL_PEER_ADDR_INIT_M_PEER_ADDR_M_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_ADDR_INIT_H */
+#define BLE_BLELL_PEER_ADDR_INIT_H_PEER_ADDR_H_Pos 0UL
+#define BLE_BLELL_PEER_ADDR_INIT_H_PEER_ADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_SEC_ADDR_ADV_L */
+#define BLE_BLELL_PEER_SEC_ADDR_ADV_L_PEER_SEC_ADDR_L_Pos 0UL
+#define BLE_BLELL_PEER_SEC_ADDR_ADV_L_PEER_SEC_ADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_SEC_ADDR_ADV_M */
+#define BLE_BLELL_PEER_SEC_ADDR_ADV_M_PEER_SEC_ADDR_M_Pos 0UL
+#define BLE_BLELL_PEER_SEC_ADDR_ADV_M_PEER_SEC_ADDR_M_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_SEC_ADDR_ADV_H */
+#define BLE_BLELL_PEER_SEC_ADDR_ADV_H_PEER_SEC_ADDR_H_Pos 0UL
+#define BLE_BLELL_PEER_SEC_ADDR_ADV_H_PEER_SEC_ADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_WINDOW_TIMER_CTRL */
+#define BLE_BLELL_INIT_WINDOW_TIMER_CTRL_INIT_WINDOW_OFFSET_SEL_Pos 0UL
+#define BLE_BLELL_INIT_WINDOW_TIMER_CTRL_INIT_WINDOW_OFFSET_SEL_Msk 0x1UL
+/* BLE_BLELL.CONN_CONFIG_EXT */
+#define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_2SLOT_EARLY_Pos 0UL
+#define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_2SLOT_EARLY_Msk 0x1UL
+#define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_3SLOT_EARLY_Pos 1UL
+#define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_3SLOT_EARLY_Msk 0x2UL
+#define BLE_BLELL_CONN_CONFIG_EXT_FW_PKT_RCV_CONN_INDEX_Pos 2UL
+#define BLE_BLELL_CONN_CONFIG_EXT_FW_PKT_RCV_CONN_INDEX_Msk 0x7CUL
+#define BLE_BLELL_CONN_CONFIG_EXT_MMMS_RX_PKT_LIMIT_Pos 8UL
+#define BLE_BLELL_CONN_CONFIG_EXT_MMMS_RX_PKT_LIMIT_Msk 0x3F00UL
+#define BLE_BLELL_CONN_CONFIG_EXT_DEBUG_CE_EXPIRE_Pos 14UL
+#define BLE_BLELL_CONN_CONFIG_EXT_DEBUG_CE_EXPIRE_Msk 0x4000UL
+#define BLE_BLELL_CONN_CONFIG_EXT_MT_PDU_CE_EXPIRE_Pos 15UL
+#define BLE_BLELL_CONN_CONFIG_EXT_MT_PDU_CE_EXPIRE_Msk 0x8000UL
+/* BLE_BLELL.DPLL_CONFIG */
+#define BLE_BLELL_DPLL_CONFIG_DPLL_CORREL_CONFIG_Pos 0UL
+#define BLE_BLELL_DPLL_CONFIG_DPLL_CORREL_CONFIG_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_NI_VAL */
+#define BLE_BLELL_INIT_NI_VAL_INIT_NI_VAL_Pos 0UL
+#define BLE_BLELL_INIT_NI_VAL_INIT_NI_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_WINDOW_OFFSET */
+#define BLE_BLELL_INIT_WINDOW_OFFSET_INIT_WINDOW_NI_Pos 0UL
+#define BLE_BLELL_INIT_WINDOW_OFFSET_INIT_WINDOW_NI_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_WINDOW_NI_ANCHOR_PT */
+#define BLE_BLELL_INIT_WINDOW_NI_ANCHOR_PT_INIT_INT_OFF_CAPT_Pos 0UL
+#define BLE_BLELL_INIT_WINDOW_NI_ANCHOR_PT_INIT_INT_OFF_CAPT_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_UPDATE_NEW_INTERVAL */
+#define BLE_BLELL_CONN_UPDATE_NEW_INTERVAL_CONN_UPDT_INTERVAL_Pos 0UL
+#define BLE_BLELL_CONN_UPDATE_NEW_INTERVAL_CONN_UPDT_INTERVAL_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_UPDATE_NEW_LATENCY */
+#define BLE_BLELL_CONN_UPDATE_NEW_LATENCY_CONN_UPDT_SLV_LATENCY_Pos 0UL
+#define BLE_BLELL_CONN_UPDATE_NEW_LATENCY_CONN_UPDT_SLV_LATENCY_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_UPDATE_NEW_SUP_TO */
+#define BLE_BLELL_CONN_UPDATE_NEW_SUP_TO_CONN_UPDT_SUP_TO_Pos 0UL
+#define BLE_BLELL_CONN_UPDATE_NEW_SUP_TO_CONN_UPDT_SUP_TO_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_UPDATE_NEW_SL_INTERVAL */
+#define BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL_SL_CONN_INTERVAL_VAL_Pos 0UL
+#define BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL_SL_CONN_INTERVAL_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD0 */
+#define BLE_BLELL_CONN_REQ_WORD0_ACCESS_ADDR_LOWER_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD0_ACCESS_ADDR_LOWER_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD1 */
+#define BLE_BLELL_CONN_REQ_WORD1_ACCESS_ADDR_UPPER_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD1_ACCESS_ADDR_UPPER_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD2 */
+#define BLE_BLELL_CONN_REQ_WORD2_TX_WINDOW_SIZE_VAL_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD2_TX_WINDOW_SIZE_VAL_Msk 0xFFUL
+#define BLE_BLELL_CONN_REQ_WORD2_CRC_INIT_LOWER_Pos 8UL
+#define BLE_BLELL_CONN_REQ_WORD2_CRC_INIT_LOWER_Msk 0xFF00UL
+/* BLE_BLELL.CONN_REQ_WORD3 */
+#define BLE_BLELL_CONN_REQ_WORD3_CRC_INIT_UPPER_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD3_CRC_INIT_UPPER_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD4 */
+#define BLE_BLELL_CONN_REQ_WORD4_TX_WINDOW_OFFSET_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD4_TX_WINDOW_OFFSET_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD5 */
+#define BLE_BLELL_CONN_REQ_WORD5_CONNECTION_INTERVAL_VAL_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD5_CONNECTION_INTERVAL_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD6 */
+#define BLE_BLELL_CONN_REQ_WORD6_SLAVE_LATENCY_VAL_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD6_SLAVE_LATENCY_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD7 */
+#define BLE_BLELL_CONN_REQ_WORD7_SUPERVISION_TIMEOUT_VAL_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD7_SUPERVISION_TIMEOUT_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD8 */
+#define BLE_BLELL_CONN_REQ_WORD8_DATA_CHANNELS_LOWER_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD8_DATA_CHANNELS_LOWER_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD9 */
+#define BLE_BLELL_CONN_REQ_WORD9_DATA_CHANNELS_MID_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD9_DATA_CHANNELS_MID_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD10 */
+#define BLE_BLELL_CONN_REQ_WORD10_DATA_CHANNELS_UPPER_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD10_DATA_CHANNELS_UPPER_Msk 0x1FUL
+/* BLE_BLELL.CONN_REQ_WORD11 */
+#define BLE_BLELL_CONN_REQ_WORD11_HOP_INCREMENT_2_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD11_HOP_INCREMENT_2_Msk 0x1FUL
+#define BLE_BLELL_CONN_REQ_WORD11_SCA_2_Pos 5UL
+#define BLE_BLELL_CONN_REQ_WORD11_SCA_2_Msk 0xE0UL
+/* BLE_BLELL.PDU_RESP_TIMER */
+#define BLE_BLELL_PDU_RESP_TIMER_PDU_RESP_TIME_VAL_Pos 0UL
+#define BLE_BLELL_PDU_RESP_TIMER_PDU_RESP_TIME_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.NEXT_RESP_TIMER_EXP */
+#define BLE_BLELL_NEXT_RESP_TIMER_EXP_NEXT_RESPONSE_INSTANT_Pos 0UL
+#define BLE_BLELL_NEXT_RESP_TIMER_EXP_NEXT_RESPONSE_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.NEXT_SUP_TO */
+#define BLE_BLELL_NEXT_SUP_TO_NEXT_TIMEOUT_INSTANT_Pos 0UL
+#define BLE_BLELL_NEXT_SUP_TO_NEXT_TIMEOUT_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.LLH_FEATURE_CONFIG */
+#define BLE_BLELL_LLH_FEATURE_CONFIG_QUICK_TRANSMIT_Pos 0UL
+#define BLE_BLELL_LLH_FEATURE_CONFIG_QUICK_TRANSMIT_Msk 0x1UL
+#define BLE_BLELL_LLH_FEATURE_CONFIG_SL_DSM_EN_Pos 1UL
+#define BLE_BLELL_LLH_FEATURE_CONFIG_SL_DSM_EN_Msk 0x2UL
+#define BLE_BLELL_LLH_FEATURE_CONFIG_US_COUNTER_OFFSET_ADJ_Pos 2UL
+#define BLE_BLELL_LLH_FEATURE_CONFIG_US_COUNTER_OFFSET_ADJ_Msk 0x4UL
+/* BLE_BLELL.WIN_MIN_STEP_SIZE */
+#define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPDN_Pos 0UL
+#define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPDN_Msk 0xFUL
+#define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPUP_Pos 4UL
+#define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPUP_Msk 0xF0UL
+#define BLE_BLELL_WIN_MIN_STEP_SIZE_WINDOW_MIN_FW_Pos 8UL
+#define BLE_BLELL_WIN_MIN_STEP_SIZE_WINDOW_MIN_FW_Msk 0xFF00UL
+/* BLE_BLELL.SLV_WIN_ADJ */
+#define BLE_BLELL_SLV_WIN_ADJ_SLV_WIN_ADJ_Pos 0UL
+#define BLE_BLELL_SLV_WIN_ADJ_SLV_WIN_ADJ_Msk 0x7FFUL
+/* BLE_BLELL.SL_CONN_INTERVAL */
+#define BLE_BLELL_SL_CONN_INTERVAL_SL_CONN_INTERVAL_VAL_Pos 0UL
+#define BLE_BLELL_SL_CONN_INTERVAL_SL_CONN_INTERVAL_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.LE_PING_TIMER_ADDR */
+#define BLE_BLELL_LE_PING_TIMER_ADDR_CONN_PING_TIMER_ADDR_Pos 0UL
+#define BLE_BLELL_LE_PING_TIMER_ADDR_CONN_PING_TIMER_ADDR_Msk 0xFFFFUL
+/* BLE_BLELL.LE_PING_TIMER_OFFSET */
+#define BLE_BLELL_LE_PING_TIMER_OFFSET_CONN_PING_TIMER_OFFSET_Pos 0UL
+#define BLE_BLELL_LE_PING_TIMER_OFFSET_CONN_PING_TIMER_OFFSET_Msk 0xFFFFUL
+/* BLE_BLELL.LE_PING_TIMER_NEXT_EXP */
+#define BLE_BLELL_LE_PING_TIMER_NEXT_EXP_CONN_PING_TIMER_NEXT_EXP_Pos 0UL
+#define BLE_BLELL_LE_PING_TIMER_NEXT_EXP_CONN_PING_TIMER_NEXT_EXP_Msk 0xFFFFUL
+/* BLE_BLELL.LE_PING_TIMER_WRAP_COUNT */
+#define BLE_BLELL_LE_PING_TIMER_WRAP_COUNT_CONN_SEC_CURRENT_WRAP_Pos 0UL
+#define BLE_BLELL_LE_PING_TIMER_WRAP_COUNT_CONN_SEC_CURRENT_WRAP_Msk 0xFFFFUL
+/* BLE_BLELL.TX_EN_EXT_DELAY */
+#define BLE_BLELL_TX_EN_EXT_DELAY_TXEN_EXT_DELAY_Pos 0UL
+#define BLE_BLELL_TX_EN_EXT_DELAY_TXEN_EXT_DELAY_Msk 0xFUL
+#define BLE_BLELL_TX_EN_EXT_DELAY_RXEN_EXT_DELAY_Pos 4UL
+#define BLE_BLELL_TX_EN_EXT_DELAY_RXEN_EXT_DELAY_Msk 0xF0UL
+#define BLE_BLELL_TX_EN_EXT_DELAY_DEMOD_2M_COMP_DLY_Pos 8UL
+#define BLE_BLELL_TX_EN_EXT_DELAY_DEMOD_2M_COMP_DLY_Msk 0xF00UL
+#define BLE_BLELL_TX_EN_EXT_DELAY_MOD_2M_COMP_DLY_Pos 12UL
+#define BLE_BLELL_TX_EN_EXT_DELAY_MOD_2M_COMP_DLY_Msk 0xF000UL
+/* BLE_BLELL.TX_RX_SYNTH_DELAY */
+#define BLE_BLELL_TX_RX_SYNTH_DELAY_RX_EN_DELAY_Pos 0UL
+#define BLE_BLELL_TX_RX_SYNTH_DELAY_RX_EN_DELAY_Msk 0xFFUL
+#define BLE_BLELL_TX_RX_SYNTH_DELAY_TX_EN_DELAY_Pos 8UL
+#define BLE_BLELL_TX_RX_SYNTH_DELAY_TX_EN_DELAY_Msk 0xFF00UL
+/* BLE_BLELL.EXT_PA_LNA_DLY_CNFG */
+#define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_LNA_CTL_DELAY_Pos 0UL
+#define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_LNA_CTL_DELAY_Msk 0xFFUL
+#define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_PA_CTL_DELAY_Pos 8UL
+#define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_PA_CTL_DELAY_Msk 0xFF00UL
+/* BLE_BLELL.LL_CONFIG */
+#define BLE_BLELL_LL_CONFIG_RSSI_SEL_Pos 0UL
+#define BLE_BLELL_LL_CONFIG_RSSI_SEL_Msk 0x1UL
+#define BLE_BLELL_LL_CONFIG_TX_RX_CTRL_SEL_Pos 1UL
+#define BLE_BLELL_LL_CONFIG_TX_RX_CTRL_SEL_Msk 0x2UL
+#define BLE_BLELL_LL_CONFIG_TIFS_ENABLE_Pos 2UL
+#define BLE_BLELL_LL_CONFIG_TIFS_ENABLE_Msk 0x4UL
+#define BLE_BLELL_LL_CONFIG_TIMER_LF_SLOT_ENABLE_Pos 3UL
+#define BLE_BLELL_LL_CONFIG_TIMER_LF_SLOT_ENABLE_Msk 0x8UL
+#define BLE_BLELL_LL_CONFIG_RSSI_INTR_SEL_Pos 5UL
+#define BLE_BLELL_LL_CONFIG_RSSI_INTR_SEL_Msk 0x20UL
+#define BLE_BLELL_LL_CONFIG_RSSI_EARLY_CNFG_Pos 6UL
+#define BLE_BLELL_LL_CONFIG_RSSI_EARLY_CNFG_Msk 0x40UL
+#define BLE_BLELL_LL_CONFIG_TX_RX_PIN_DLY_Pos 7UL
+#define BLE_BLELL_LL_CONFIG_TX_RX_PIN_DLY_Msk 0x80UL
+#define BLE_BLELL_LL_CONFIG_TX_PA_PWR_LVL_TYPE_Pos 8UL
+#define BLE_BLELL_LL_CONFIG_TX_PA_PWR_LVL_TYPE_Msk 0x100UL
+#define BLE_BLELL_LL_CONFIG_RSSI_ENERGY_RD_Pos 9UL
+#define BLE_BLELL_LL_CONFIG_RSSI_ENERGY_RD_Msk 0x200UL
+#define BLE_BLELL_LL_CONFIG_RSSI_EACH_PKT_Pos 10UL
+#define BLE_BLELL_LL_CONFIG_RSSI_EACH_PKT_Msk 0x400UL
+#define BLE_BLELL_LL_CONFIG_FORCE_TRIG_RCB_UPDATE_Pos 11UL
+#define BLE_BLELL_LL_CONFIG_FORCE_TRIG_RCB_UPDATE_Msk 0x800UL
+#define BLE_BLELL_LL_CONFIG_CHECK_DUP_CONN_Pos 12UL
+#define BLE_BLELL_LL_CONFIG_CHECK_DUP_CONN_Msk 0x1000UL
+#define BLE_BLELL_LL_CONFIG_MULTI_ENGINE_LPM_Pos 13UL
+#define BLE_BLELL_LL_CONFIG_MULTI_ENGINE_LPM_Msk 0x2000UL
+#define BLE_BLELL_LL_CONFIG_ADV_DIR_DEVICE_PRIV_EN_Pos 14UL
+#define BLE_BLELL_LL_CONFIG_ADV_DIR_DEVICE_PRIV_EN_Msk 0x4000UL
+/* BLE_BLELL.LL_CONTROL */
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_Pos 0UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_Msk 0x1UL
+#define BLE_BLELL_LL_CONTROL_DLE_Pos 1UL
+#define BLE_BLELL_LL_CONTROL_DLE_Msk 0x2UL
+#define BLE_BLELL_LL_CONTROL_WL_READ_AS_MEM_Pos 2UL
+#define BLE_BLELL_LL_CONTROL_WL_READ_AS_MEM_Msk 0x4UL
+#define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL_Pos 3UL
+#define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL_Msk 0x8UL
+#define BLE_BLELL_LL_CONTROL_HW_RSLV_LIST_FULL_Pos 4UL
+#define BLE_BLELL_LL_CONTROL_HW_RSLV_LIST_FULL_Msk 0x10UL
+#define BLE_BLELL_LL_CONTROL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV_Pos 5UL
+#define BLE_BLELL_LL_CONTROL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV_Msk 0x20UL
+#define BLE_BLELL_LL_CONTROL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV_Pos 6UL
+#define BLE_BLELL_LL_CONTROL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV_Msk 0x40UL
+#define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN_Pos 7UL
+#define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN_Msk 0x80UL
+#define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI_Pos 8UL
+#define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI_Msk 0x100UL
+#define BLE_BLELL_LL_CONTROL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI_Pos 9UL
+#define BLE_BLELL_LL_CONTROL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI_Msk 0x200UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_ADV_Pos 10UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_ADV_Msk 0x400UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_SCAN_Pos 11UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_SCAN_Msk 0x800UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_INIT_Pos 12UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_INIT_Msk 0x1000UL
+#define BLE_BLELL_LL_CONTROL_EN_CONN_RX_EN_MOD_Pos 13UL
+#define BLE_BLELL_LL_CONTROL_EN_CONN_RX_EN_MOD_Msk 0x2000UL
+#define BLE_BLELL_LL_CONTROL_SLV_CONN_PEER_RPA_NOT_RSLVD_Pos 14UL
+#define BLE_BLELL_LL_CONTROL_SLV_CONN_PEER_RPA_NOT_RSLVD_Msk 0x4000UL
+#define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_FLUSH_Pos 15UL
+#define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_FLUSH_Msk 0x8000UL
+/* BLE_BLELL.DEV_PA_ADDR_L */
+#define BLE_BLELL_DEV_PA_ADDR_L_DEV_PA_ADDR_L_Pos 0UL
+#define BLE_BLELL_DEV_PA_ADDR_L_DEV_PA_ADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.DEV_PA_ADDR_M */
+#define BLE_BLELL_DEV_PA_ADDR_M_DEV_PA_ADDR_M_Pos 0UL
+#define BLE_BLELL_DEV_PA_ADDR_M_DEV_PA_ADDR_M_Msk 0xFFFFUL
+/* BLE_BLELL.DEV_PA_ADDR_H */
+#define BLE_BLELL_DEV_PA_ADDR_H_DEV_PA_ADDR_H_Pos 0UL
+#define BLE_BLELL_DEV_PA_ADDR_H_DEV_PA_ADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.RSLV_LIST_ENABLE */
+#define BLE_BLELL_RSLV_LIST_ENABLE_VALID_ENTRY_Pos 0UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_VALID_ENTRY_Msk 0x1UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_IRK_SET_Pos 1UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_IRK_SET_Msk 0x2UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_IRK_SET_RX_Pos 2UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_IRK_SET_RX_Msk 0x4UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_WHITELISTED_PEER_Pos 3UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_WHITELISTED_PEER_Msk 0x8UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_TYPE_Pos 4UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_TYPE_Msk 0x10UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_RPA_VAL_Pos 5UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_RPA_VAL_Msk 0x20UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_RXD_RPA_VAL_Pos 6UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_RXD_RPA_VAL_Msk 0x40UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TX_RPA_VAL_Pos 7UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TX_RPA_VAL_Msk 0x80UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_INIT_RPA_SEL_Pos 8UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_INIT_RPA_SEL_Msk 0x100UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TYPE_TX_Pos 9UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TYPE_TX_Msk 0x200UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_ENTRY_CONNECTED_Pos 10UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_ENTRY_CONNECTED_Msk 0x400UL
+/* BLE_BLELL.WL_CONNECTION_STATUS */
+#define BLE_BLELL_WL_CONNECTION_STATUS_WL_ENTRY_CONNECTED_Pos 0UL
+#define BLE_BLELL_WL_CONNECTION_STATUS_WL_ENTRY_CONNECTED_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_RXMEM_BASE_ADDR_DLE */
+#define BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE_CONN_RX_MEM_BASE_ADDR_DLE_Pos 0UL
+#define BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE_CONN_RX_MEM_BASE_ADDR_DLE_Msk 0xFFFFFFFFUL
+/* BLE_BLELL.CONN_TXMEM_BASE_ADDR_DLE */
+#define BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE_CONN_TX_MEM_BASE_ADDR_DLE_Pos 0UL
+#define BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE_CONN_TX_MEM_BASE_ADDR_DLE_Msk 0xFFFFFFFFUL
+/* BLE_BLELL.CONN_1_PARAM_MEM_BASE_ADDR */
+#define BLE_BLELL_CONN_1_PARAM_MEM_BASE_ADDR_CONN_1_PARAM_Pos 0UL
+#define BLE_BLELL_CONN_1_PARAM_MEM_BASE_ADDR_CONN_1_PARAM_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_2_PARAM_MEM_BASE_ADDR */
+#define BLE_BLELL_CONN_2_PARAM_MEM_BASE_ADDR_CONN_2_PARAM_Pos 0UL
+#define BLE_BLELL_CONN_2_PARAM_MEM_BASE_ADDR_CONN_2_PARAM_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_3_PARAM_MEM_BASE_ADDR */
+#define BLE_BLELL_CONN_3_PARAM_MEM_BASE_ADDR_CONN_3_PARAM_Pos 0UL
+#define BLE_BLELL_CONN_3_PARAM_MEM_BASE_ADDR_CONN_3_PARAM_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_4_PARAM_MEM_BASE_ADDR */
+#define BLE_BLELL_CONN_4_PARAM_MEM_BASE_ADDR_CONN_4_PARAM_Pos 0UL
+#define BLE_BLELL_CONN_4_PARAM_MEM_BASE_ADDR_CONN_4_PARAM_Msk 0xFFFFUL
+/* BLE_BLELL.NI_TIMER */
+#define BLE_BLELL_NI_TIMER_NI_TIMER_Pos 0UL
+#define BLE_BLELL_NI_TIMER_NI_TIMER_Msk 0xFFFFUL
+/* BLE_BLELL.US_OFFSET */
+#define BLE_BLELL_US_OFFSET_US_OFFSET_SLOT_BOUNDARY_Pos 0UL
+#define BLE_BLELL_US_OFFSET_US_OFFSET_SLOT_BOUNDARY_Msk 0x3FFUL
+/* BLE_BLELL.NEXT_CONN */
+#define BLE_BLELL_NEXT_CONN_NEXT_CONN_INDEX_Pos 0UL
+#define BLE_BLELL_NEXT_CONN_NEXT_CONN_INDEX_Msk 0x1FUL
+#define BLE_BLELL_NEXT_CONN_NEXT_CONN_TYPE_Pos 5UL
+#define BLE_BLELL_NEXT_CONN_NEXT_CONN_TYPE_Msk 0x20UL
+#define BLE_BLELL_NEXT_CONN_NI_VALID_Pos 6UL
+#define BLE_BLELL_NEXT_CONN_NI_VALID_Msk 0x40UL
+/* BLE_BLELL.NI_ABORT */
+#define BLE_BLELL_NI_ABORT_NI_ABORT_Pos 0UL
+#define BLE_BLELL_NI_ABORT_NI_ABORT_Msk 0x1UL
+#define BLE_BLELL_NI_ABORT_ABORT_ACK_Pos 1UL
+#define BLE_BLELL_NI_ABORT_ABORT_ACK_Msk 0x2UL
+/* BLE_BLELL.CONN_NI_STATUS */
+#define BLE_BLELL_CONN_NI_STATUS_CONN_NI_Pos 0UL
+#define BLE_BLELL_CONN_NI_STATUS_CONN_NI_Msk 0xFFFFUL
+/* BLE_BLELL.NEXT_SUP_TO_STATUS */
+#define BLE_BLELL_NEXT_SUP_TO_STATUS_NEXT_SUP_TO_Pos 0UL
+#define BLE_BLELL_NEXT_SUP_TO_STATUS_NEXT_SUP_TO_Msk 0xFFFFUL
+/* BLE_BLELL.MMMS_CONN_STATUS */
+#define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_INDEX_Pos 0UL
+#define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_INDEX_Msk 0x1FUL
+#define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_TYPE_Pos 5UL
+#define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_TYPE_Msk 0x20UL
+#define BLE_BLELL_MMMS_CONN_STATUS_SN_CURR_Pos 6UL
+#define BLE_BLELL_MMMS_CONN_STATUS_SN_CURR_Msk 0x40UL
+#define BLE_BLELL_MMMS_CONN_STATUS_NESN_CURR_Pos 7UL
+#define BLE_BLELL_MMMS_CONN_STATUS_NESN_CURR_Msk 0x80UL
+#define BLE_BLELL_MMMS_CONN_STATUS_LAST_UNMAPPED_CHANNEL_Pos 8UL
+#define BLE_BLELL_MMMS_CONN_STATUS_LAST_UNMAPPED_CHANNEL_Msk 0x3F00UL
+#define BLE_BLELL_MMMS_CONN_STATUS_PKT_MISS_Pos 14UL
+#define BLE_BLELL_MMMS_CONN_STATUS_PKT_MISS_Msk 0x4000UL
+#define BLE_BLELL_MMMS_CONN_STATUS_ANCHOR_PT_STATE_Pos 15UL
+#define BLE_BLELL_MMMS_CONN_STATUS_ANCHOR_PT_STATE_Msk 0x8000UL
+/* BLE_BLELL.BT_SLOT_CAPT_STATUS */
+#define BLE_BLELL_BT_SLOT_CAPT_STATUS_BT_SLOT_Pos 0UL
+#define BLE_BLELL_BT_SLOT_CAPT_STATUS_BT_SLOT_Msk 0xFFFFUL
+/* BLE_BLELL.US_CAPT_STATUS */
+#define BLE_BLELL_US_CAPT_STATUS_US_CAPT_Pos 0UL
+#define BLE_BLELL_US_CAPT_STATUS_US_CAPT_Msk 0x3FFUL
+/* BLE_BLELL.US_OFFSET_STATUS */
+#define BLE_BLELL_US_OFFSET_STATUS_US_OFFSET_Pos 0UL
+#define BLE_BLELL_US_OFFSET_STATUS_US_OFFSET_Msk 0xFFFFUL
+/* BLE_BLELL.ACCU_WINDOW_WIDEN_STATUS */
+#define BLE_BLELL_ACCU_WINDOW_WIDEN_STATUS_ACCU_WINDOW_WIDEN_Pos 0UL
+#define BLE_BLELL_ACCU_WINDOW_WIDEN_STATUS_ACCU_WINDOW_WIDEN_Msk 0xFFFFUL
+/* BLE_BLELL.EARLY_INTR_STATUS */
+#define BLE_BLELL_EARLY_INTR_STATUS_CONN_INDEX_FOR_EARLY_INTR_Pos 0UL
+#define BLE_BLELL_EARLY_INTR_STATUS_CONN_INDEX_FOR_EARLY_INTR_Msk 0x1FUL
+#define BLE_BLELL_EARLY_INTR_STATUS_CONN_TYPE_FOR_EARLY_INTR_Pos 5UL
+#define BLE_BLELL_EARLY_INTR_STATUS_CONN_TYPE_FOR_EARLY_INTR_Msk 0x20UL
+#define BLE_BLELL_EARLY_INTR_STATUS_US_FOR_EARLY_INTR_Pos 6UL
+#define BLE_BLELL_EARLY_INTR_STATUS_US_FOR_EARLY_INTR_Msk 0xFFC0UL
+/* BLE_BLELL.MMMS_CONFIG */
+#define BLE_BLELL_MMMS_CONFIG_MMMS_ENABLE_Pos 0UL
+#define BLE_BLELL_MMMS_CONFIG_MMMS_ENABLE_Msk 0x1UL
+#define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_REQ_PARAM_IN_MEM_Pos 1UL
+#define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_REQ_PARAM_IN_MEM_Msk 0x2UL
+#define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_PARAM_MEM_WR_Pos 2UL
+#define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_PARAM_MEM_WR_Msk 0x4UL
+#define BLE_BLELL_MMMS_CONFIG_CONN_PARAM_FROM_REG_Pos 3UL
+#define BLE_BLELL_MMMS_CONFIG_CONN_PARAM_FROM_REG_Msk 0x8UL
+#define BLE_BLELL_MMMS_CONFIG_ADV_CONN_INDEX_Pos 4UL
+#define BLE_BLELL_MMMS_CONFIG_ADV_CONN_INDEX_Msk 0x1F0UL
+#define BLE_BLELL_MMMS_CONFIG_CE_LEN_IMMEDIATE_EXPIRE_Pos 9UL
+#define BLE_BLELL_MMMS_CONFIG_CE_LEN_IMMEDIATE_EXPIRE_Msk 0x200UL
+#define BLE_BLELL_MMMS_CONFIG_RESET_RX_FIFO_PTR_Pos 10UL
+#define BLE_BLELL_MMMS_CONFIG_RESET_RX_FIFO_PTR_Msk 0x400UL
+/* BLE_BLELL.US_COUNTER */
+#define BLE_BLELL_US_COUNTER_US_COUNTER_Pos 0UL
+#define BLE_BLELL_US_COUNTER_US_COUNTER_Msk 0x3FFUL
+/* BLE_BLELL.US_CAPT_PREV */
+#define BLE_BLELL_US_CAPT_PREV_US_CAPT_LOAD_Pos 0UL
+#define BLE_BLELL_US_CAPT_PREV_US_CAPT_LOAD_Msk 0x3FFUL
+/* BLE_BLELL.EARLY_INTR_NI */
+#define BLE_BLELL_EARLY_INTR_NI_EARLY_INTR_NI_Pos 0UL
+#define BLE_BLELL_EARLY_INTR_NI_EARLY_INTR_NI_Msk 0xFFFFUL
+/* BLE_BLELL.MMMS_MASTER_CREATE_BT_CAPT */
+#define BLE_BLELL_MMMS_MASTER_CREATE_BT_CAPT_BT_SLOT_Pos 0UL
+#define BLE_BLELL_MMMS_MASTER_CREATE_BT_CAPT_BT_SLOT_Msk 0xFFFFUL
+/* BLE_BLELL.MMMS_SLAVE_CREATE_BT_CAPT */
+#define BLE_BLELL_MMMS_SLAVE_CREATE_BT_CAPT_US_CAPT_Pos 0UL
+#define BLE_BLELL_MMMS_SLAVE_CREATE_BT_CAPT_US_CAPT_Msk 0x3FFUL
+/* BLE_BLELL.MMMS_SLAVE_CREATE_US_CAPT */
+#define BLE_BLELL_MMMS_SLAVE_CREATE_US_CAPT_US_OFFSET_SLAVE_CREATED_Pos 0UL
+#define BLE_BLELL_MMMS_SLAVE_CREATE_US_CAPT_US_OFFSET_SLAVE_CREATED_Msk 0xFFFFUL
+/* BLE_BLELL.MMMS_DATA_MEM_DESCRIPTOR */
+#define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_LLID_C1_Pos 0UL
+#define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_LLID_C1_Msk 0x3UL
+#define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_DATA_LENGTH_C1_Pos 2UL
+#define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_DATA_LENGTH_C1_Msk 0x3FCUL
+/* BLE_BLELL.CONN_1_DATA_LIST_SENT */
+#define BLE_BLELL_CONN_1_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_1_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_1_DATA_LIST_SENT_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_1_DATA_LIST_SENT_SET_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_1_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos 8UL
+#define BLE_BLELL_CONN_1_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk 0xF00UL
+/* BLE_BLELL.CONN_1_DATA_LIST_ACK */
+#define BLE_BLELL_CONN_1_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_1_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_1_DATA_LIST_ACK_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_1_DATA_LIST_ACK_SET_CLEAR_C1_Msk 0x80UL
+/* BLE_BLELL.CONN_1_CE_DATA_LIST_CFG */
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos 0UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos 4UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk 0x10UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos 5UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk 0x20UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_C1_Pos 6UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_C1_Msk 0x40UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos 8UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk 0x100UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_Pos 9UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_Msk 0x200UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos 10UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk 0x400UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos 11UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk 0x800UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos 12UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk 0xF000UL
+/* BLE_BLELL.CONN_2_DATA_LIST_SENT */
+#define BLE_BLELL_CONN_2_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_2_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_2_DATA_LIST_SENT_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_2_DATA_LIST_SENT_SET_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_2_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos 8UL
+#define BLE_BLELL_CONN_2_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk 0xF00UL
+/* BLE_BLELL.CONN_2_DATA_LIST_ACK */
+#define BLE_BLELL_CONN_2_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_2_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_2_DATA_LIST_ACK_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_2_DATA_LIST_ACK_SET_CLEAR_C1_Msk 0x80UL
+/* BLE_BLELL.CONN_2_CE_DATA_LIST_CFG */
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos 0UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos 4UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk 0x10UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos 5UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk 0x20UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_C1_Pos 6UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_C1_Msk 0x40UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos 8UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk 0x100UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_Pos 9UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_Msk 0x200UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos 10UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk 0x400UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos 11UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk 0x800UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos 12UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk 0xF000UL
+/* BLE_BLELL.CONN_3_DATA_LIST_SENT */
+#define BLE_BLELL_CONN_3_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_3_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_3_DATA_LIST_SENT_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_3_DATA_LIST_SENT_SET_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_3_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos 8UL
+#define BLE_BLELL_CONN_3_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk 0xF00UL
+/* BLE_BLELL.CONN_3_DATA_LIST_ACK */
+#define BLE_BLELL_CONN_3_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_3_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_3_DATA_LIST_ACK_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_3_DATA_LIST_ACK_SET_CLEAR_C1_Msk 0x80UL
+/* BLE_BLELL.CONN_3_CE_DATA_LIST_CFG */
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos 0UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos 4UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk 0x10UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos 5UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk 0x20UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_C1_Pos 6UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_C1_Msk 0x40UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos 8UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk 0x100UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_Pos 9UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_Msk 0x200UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos 10UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk 0x400UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos 11UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk 0x800UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos 12UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk 0xF000UL
+/* BLE_BLELL.CONN_4_DATA_LIST_SENT */
+#define BLE_BLELL_CONN_4_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_4_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_4_DATA_LIST_SENT_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_4_DATA_LIST_SENT_SET_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_4_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos 8UL
+#define BLE_BLELL_CONN_4_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk 0xF00UL
+/* BLE_BLELL.CONN_4_DATA_LIST_ACK */
+#define BLE_BLELL_CONN_4_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_4_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_4_DATA_LIST_ACK_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_4_DATA_LIST_ACK_SET_CLEAR_C1_Msk 0x80UL
+/* BLE_BLELL.CONN_4_CE_DATA_LIST_CFG */
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos 0UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos 4UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk 0x10UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos 5UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk 0x20UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_C1_Pos 6UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_C1_Msk 0x40UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos 8UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk 0x100UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_Pos 9UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_Msk 0x200UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos 10UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk 0x400UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos 11UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk 0x800UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos 12UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk 0xF000UL
+/* BLE_BLELL.MMMS_ADVCH_NI_ENABLE */
+#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_ADV_NI_ENABLE_Pos 0UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_ADV_NI_ENABLE_Msk 0x1UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_SCAN_NI_ENABLE_Pos 1UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_SCAN_NI_ENABLE_Msk 0x2UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_INIT_NI_ENABLE_Pos 2UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_INIT_NI_ENABLE_Msk 0x4UL
+/* BLE_BLELL.MMMS_ADVCH_NI_VALID */
+#define BLE_BLELL_MMMS_ADVCH_NI_VALID_ADV_NI_VALID_Pos 0UL
+#define BLE_BLELL_MMMS_ADVCH_NI_VALID_ADV_NI_VALID_Msk 0x1UL
+#define BLE_BLELL_MMMS_ADVCH_NI_VALID_SCAN_NI_VALID_Pos 1UL
+#define BLE_BLELL_MMMS_ADVCH_NI_VALID_SCAN_NI_VALID_Msk 0x2UL
+#define BLE_BLELL_MMMS_ADVCH_NI_VALID_INIT_NI_VALID_Pos 2UL
+#define BLE_BLELL_MMMS_ADVCH_NI_VALID_INIT_NI_VALID_Msk 0x4UL
+/* BLE_BLELL.MMMS_ADVCH_NI_ABORT */
+#define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_NI_ABORT_Pos 0UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_NI_ABORT_Msk 0x1UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_ABORT_STATUS_Pos 1UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_ABORT_STATUS_Msk 0x2UL
+/* BLE_BLELL.CONN_PARAM_NEXT_SUP_TO */
+#define BLE_BLELL_CONN_PARAM_NEXT_SUP_TO_NEXT_SUP_TO_LOAD_Pos 0UL
+#define BLE_BLELL_CONN_PARAM_NEXT_SUP_TO_NEXT_SUP_TO_LOAD_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_PARAM_ACC_WIN_WIDEN */
+#define BLE_BLELL_CONN_PARAM_ACC_WIN_WIDEN_ACC_WINDOW_WIDEN_Pos 0UL
+#define BLE_BLELL_CONN_PARAM_ACC_WIN_WIDEN_ACC_WINDOW_WIDEN_Msk 0x3FFUL
+/* BLE_BLELL.HW_LOAD_OFFSET */
+#define BLE_BLELL_HW_LOAD_OFFSET_LOAD_OFFSET_Pos 0UL
+#define BLE_BLELL_HW_LOAD_OFFSET_LOAD_OFFSET_Msk 0x1FUL
+/* BLE_BLELL.ADV_RAND */
+#define BLE_BLELL_ADV_RAND_ADV_RAND_Pos 0UL
+#define BLE_BLELL_ADV_RAND_ADV_RAND_Msk 0xFUL
+/* BLE_BLELL.MMMS_RX_PKT_CNTR */
+#define BLE_BLELL_MMMS_RX_PKT_CNTR_MMMS_RX_PKT_CNT_Pos 0UL
+#define BLE_BLELL_MMMS_RX_PKT_CNTR_MMMS_RX_PKT_CNT_Msk 0x3FUL
+/* BLE_BLELL.CONN_RX_PKT_CNTR */
+#define BLE_BLELL_CONN_RX_PKT_CNTR_RX_PKT_CNT_Pos 0UL
+#define BLE_BLELL_CONN_RX_PKT_CNTR_RX_PKT_CNT_Msk 0x3FUL
+/* BLE_BLELL.WHITELIST_BASE_ADDR */
+#define BLE_BLELL_WHITELIST_BASE_ADDR_WL_BASE_ADDR_Pos 0UL
+#define BLE_BLELL_WHITELIST_BASE_ADDR_WL_BASE_ADDR_Msk 0xFFFFUL
+/* BLE_BLELL.RSLV_LIST_PEER_IDNTT_BASE_ADDR */
+#define BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR_RSLV_LIST_PEER_IDNTT_BASE_ADDR_Pos 0UL
+#define BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR_RSLV_LIST_PEER_IDNTT_BASE_ADDR_Msk 0xFFFFUL
+/* BLE_BLELL.RSLV_LIST_PEER_RPA_BASE_ADDR */
+#define BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR_RSLV_LIST_PEER_RPA_BASE_ADDR_Pos 0UL
+#define BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR_RSLV_LIST_PEER_RPA_BASE_ADDR_Msk 0xFFFFUL
+/* BLE_BLELL.RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR */
+#define BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_Pos 0UL
+#define BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_Msk 0xFFFFUL
+/* BLE_BLELL.RSLV_LIST_TX_INIT_RPA_BASE_ADDR */
+#define BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_Pos 0UL
+#define BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_Msk 0xFFFFUL
+
+
+/* BLE_BLESS.DDFT_CONFIG */
+#define BLE_BLESS_DDFT_CONFIG_DDFT_ENABLE_Pos 0UL
+#define BLE_BLESS_DDFT_CONFIG_DDFT_ENABLE_Msk 0x1UL
+#define BLE_BLESS_DDFT_CONFIG_BLERD_DDFT_EN_Pos 1UL
+#define BLE_BLESS_DDFT_CONFIG_BLERD_DDFT_EN_Msk 0x2UL
+#define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG1_Pos 8UL
+#define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG1_Msk 0x1F00UL
+#define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG2_Pos 16UL
+#define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG2_Msk 0x1F0000UL
+/* BLE_BLESS.XTAL_CLK_DIV_CONFIG */
+#define BLE_BLESS_XTAL_CLK_DIV_CONFIG_SYSCLK_DIV_Pos 0UL
+#define BLE_BLESS_XTAL_CLK_DIV_CONFIG_SYSCLK_DIV_Msk 0x3UL
+#define BLE_BLESS_XTAL_CLK_DIV_CONFIG_LLCLK_DIV_Pos 2UL
+#define BLE_BLESS_XTAL_CLK_DIV_CONFIG_LLCLK_DIV_Msk 0xCUL
+/* BLE_BLESS.INTR_STAT */
+#define BLE_BLESS_INTR_STAT_DSM_ENTERED_INTR_Pos 0UL
+#define BLE_BLESS_INTR_STAT_DSM_ENTERED_INTR_Msk 0x1UL
+#define BLE_BLESS_INTR_STAT_DSM_EXITED_INTR_Pos 1UL
+#define BLE_BLESS_INTR_STAT_DSM_EXITED_INTR_Msk 0x2UL
+#define BLE_BLESS_INTR_STAT_RCBLL_DONE_INTR_Pos 2UL
+#define BLE_BLESS_INTR_STAT_RCBLL_DONE_INTR_Msk 0x4UL
+#define BLE_BLESS_INTR_STAT_BLERD_ACTIVE_INTR_Pos 3UL
+#define BLE_BLESS_INTR_STAT_BLERD_ACTIVE_INTR_Msk 0x8UL
+#define BLE_BLESS_INTR_STAT_RCB_INTR_Pos 4UL
+#define BLE_BLESS_INTR_STAT_RCB_INTR_Msk 0x10UL
+#define BLE_BLESS_INTR_STAT_LL_INTR_Pos 5UL
+#define BLE_BLESS_INTR_STAT_LL_INTR_Msk 0x20UL
+#define BLE_BLESS_INTR_STAT_GPIO_INTR_Pos 6UL
+#define BLE_BLESS_INTR_STAT_GPIO_INTR_Msk 0x40UL
+#define BLE_BLESS_INTR_STAT_EFUSE_INTR_Pos 7UL
+#define BLE_BLESS_INTR_STAT_EFUSE_INTR_Msk 0x80UL
+#define BLE_BLESS_INTR_STAT_XTAL_ON_INTR_Pos 8UL
+#define BLE_BLESS_INTR_STAT_XTAL_ON_INTR_Msk 0x100UL
+#define BLE_BLESS_INTR_STAT_ENC_INTR_Pos 9UL
+#define BLE_BLESS_INTR_STAT_ENC_INTR_Msk 0x200UL
+#define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_POS_Pos 10UL
+#define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_POS_Msk 0x400UL
+#define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_NEG_Pos 11UL
+#define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_NEG_Msk 0x800UL
+/* BLE_BLESS.INTR_MASK */
+#define BLE_BLESS_INTR_MASK_DSM_EXIT_Pos 0UL
+#define BLE_BLESS_INTR_MASK_DSM_EXIT_Msk 0x1UL
+#define BLE_BLESS_INTR_MASK_DSM_ENTERED_INTR_MASK_Pos 1UL
+#define BLE_BLESS_INTR_MASK_DSM_ENTERED_INTR_MASK_Msk 0x2UL
+#define BLE_BLESS_INTR_MASK_DSM_EXITED_INTR_MASK_Pos 2UL
+#define BLE_BLESS_INTR_MASK_DSM_EXITED_INTR_MASK_Msk 0x4UL
+#define BLE_BLESS_INTR_MASK_XTAL_ON_INTR_MASK_Pos 3UL
+#define BLE_BLESS_INTR_MASK_XTAL_ON_INTR_MASK_Msk 0x8UL
+#define BLE_BLESS_INTR_MASK_RCBLL_INTR_MASK_Pos 4UL
+#define BLE_BLESS_INTR_MASK_RCBLL_INTR_MASK_Msk 0x10UL
+#define BLE_BLESS_INTR_MASK_BLERD_ACTIVE_INTR_MASK_Pos 5UL
+#define BLE_BLESS_INTR_MASK_BLERD_ACTIVE_INTR_MASK_Msk 0x20UL
+#define BLE_BLESS_INTR_MASK_RCB_INTR_MASK_Pos 6UL
+#define BLE_BLESS_INTR_MASK_RCB_INTR_MASK_Msk 0x40UL
+#define BLE_BLESS_INTR_MASK_LL_INTR_MASK_Pos 7UL
+#define BLE_BLESS_INTR_MASK_LL_INTR_MASK_Msk 0x80UL
+#define BLE_BLESS_INTR_MASK_GPIO_INTR_MASK_Pos 8UL
+#define BLE_BLESS_INTR_MASK_GPIO_INTR_MASK_Msk 0x100UL
+#define BLE_BLESS_INTR_MASK_EFUSE_INTR_MASK_Pos 9UL
+#define BLE_BLESS_INTR_MASK_EFUSE_INTR_MASK_Msk 0x200UL
+#define BLE_BLESS_INTR_MASK_ENC_INTR_MASK_Pos 10UL
+#define BLE_BLESS_INTR_MASK_ENC_INTR_MASK_Msk 0x400UL
+#define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_POS_MASK_Pos 11UL
+#define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_POS_MASK_Msk 0x800UL
+#define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_NEG_MASK_Pos 12UL
+#define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_NEG_MASK_Msk 0x1000UL
+/* BLE_BLESS.LL_CLK_EN */
+#define BLE_BLESS_LL_CLK_EN_CLK_EN_Pos 0UL
+#define BLE_BLESS_LL_CLK_EN_CLK_EN_Msk 0x1UL
+#define BLE_BLESS_LL_CLK_EN_CY_CORREL_EN_Pos 1UL
+#define BLE_BLESS_LL_CLK_EN_CY_CORREL_EN_Msk 0x2UL
+#define BLE_BLESS_LL_CLK_EN_MXD_IF_OPTION_Pos 2UL
+#define BLE_BLESS_LL_CLK_EN_MXD_IF_OPTION_Msk 0x4UL
+#define BLE_BLESS_LL_CLK_EN_SEL_RCB_CLK_Pos 3UL
+#define BLE_BLESS_LL_CLK_EN_SEL_RCB_CLK_Msk 0x8UL
+#define BLE_BLESS_LL_CLK_EN_BLESS_RESET_Pos 4UL
+#define BLE_BLESS_LL_CLK_EN_BLESS_RESET_Msk 0x10UL
+#define BLE_BLESS_LL_CLK_EN_DPSLP_HWRCB_EN_Pos 5UL
+#define BLE_BLESS_LL_CLK_EN_DPSLP_HWRCB_EN_Msk 0x20UL
+/* BLE_BLESS.LF_CLK_CTRL */
+#define BLE_BLESS_LF_CLK_CTRL_DISABLE_LF_CLK_Pos 0UL
+#define BLE_BLESS_LF_CLK_CTRL_DISABLE_LF_CLK_Msk 0x1UL
+#define BLE_BLESS_LF_CLK_CTRL_ENABLE_ENC_CLK_Pos 1UL
+#define BLE_BLESS_LF_CLK_CTRL_ENABLE_ENC_CLK_Msk 0x2UL
+#define BLE_BLESS_LF_CLK_CTRL_M0S8BLESS_REV_ID_Pos 29UL
+#define BLE_BLESS_LF_CLK_CTRL_M0S8BLESS_REV_ID_Msk 0xE0000000UL
+/* BLE_BLESS.EXT_PA_LNA_CTRL */
+#define BLE_BLESS_EXT_PA_LNA_CTRL_ENABLE_EXT_PA_LNA_Pos 1UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_ENABLE_EXT_PA_LNA_Msk 0x2UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_CHIP_EN_POL_Pos 2UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_CHIP_EN_POL_Msk 0x4UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_PA_CTRL_POL_Pos 3UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_PA_CTRL_POL_Msk 0x8UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_LNA_CTRL_POL_Pos 4UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_LNA_CTRL_POL_Msk 0x10UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_OUT_EN_DRIVE_VAL_Pos 5UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_OUT_EN_DRIVE_VAL_Msk 0x20UL
+/* BLE_BLESS.LL_PKT_RSSI_CH_ENERGY */
+#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RSSI_Pos 0UL
+#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RSSI_Msk 0xFFFFUL
+#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RX_CHANNEL_Pos 16UL
+#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RX_CHANNEL_Msk 0x3F0000UL
+#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_PKT_RSSI_OR_CH_ENERGY_Pos 22UL
+#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_PKT_RSSI_OR_CH_ENERGY_Msk 0x400000UL
+/* BLE_BLESS.BT_CLOCK_CAPT */
+#define BLE_BLESS_BT_CLOCK_CAPT_BT_CLOCK_Pos 0UL
+#define BLE_BLESS_BT_CLOCK_CAPT_BT_CLOCK_Msk 0xFFFFUL
+/* BLE_BLESS.MT_CFG */
+#define BLE_BLESS_MT_CFG_ENABLE_BLERD_Pos 0UL
+#define BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk 0x1UL
+#define BLE_BLESS_MT_CFG_DEEPSLEEP_EXIT_CFG_Pos 1UL
+#define BLE_BLESS_MT_CFG_DEEPSLEEP_EXIT_CFG_Msk 0x2UL
+#define BLE_BLESS_MT_CFG_DEEPSLEEP_EXITED_Pos 2UL
+#define BLE_BLESS_MT_CFG_DEEPSLEEP_EXITED_Msk 0x4UL
+#define BLE_BLESS_MT_CFG_ACT_LDO_NOT_BUCK_Pos 3UL
+#define BLE_BLESS_MT_CFG_ACT_LDO_NOT_BUCK_Msk 0x8UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Pos 4UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Msk 0x10UL
+#define BLE_BLESS_MT_CFG_HVLDO_BYPASS_Pos 5UL
+#define BLE_BLESS_MT_CFG_HVLDO_BYPASS_Msk 0x20UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_ACT_REGULATOR_Pos 6UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_ACT_REGULATOR_Msk 0x40UL
+#define BLE_BLESS_MT_CFG_ACT_REGULATOR_EN_Pos 7UL
+#define BLE_BLESS_MT_CFG_ACT_REGULATOR_EN_Msk 0x80UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_DIG_REGULATOR_Pos 8UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_DIG_REGULATOR_Msk 0x100UL
+#define BLE_BLESS_MT_CFG_DIG_REGULATOR_EN_Pos 9UL
+#define BLE_BLESS_MT_CFG_DIG_REGULATOR_EN_Msk 0x200UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_RET_SWITCH_Pos 10UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_RET_SWITCH_Msk 0x400UL
+#define BLE_BLESS_MT_CFG_RET_SWITCH_Pos 11UL
+#define BLE_BLESS_MT_CFG_RET_SWITCH_Msk 0x800UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_ISOLATE_Pos 12UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_ISOLATE_Msk 0x1000UL
+#define BLE_BLESS_MT_CFG_ISOLATE_N_Pos 13UL
+#define BLE_BLESS_MT_CFG_ISOLATE_N_Msk 0x2000UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_LL_CLK_EN_Pos 14UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_LL_CLK_EN_Msk 0x4000UL
+#define BLE_BLESS_MT_CFG_LL_CLK_EN_Pos 15UL
+#define BLE_BLESS_MT_CFG_LL_CLK_EN_Msk 0x8000UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Pos 16UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Msk 0x10000UL
+#define BLE_BLESS_MT_CFG_HVLDO_EN_Pos 17UL
+#define BLE_BLESS_MT_CFG_HVLDO_EN_Msk 0x20000UL
+#define BLE_BLESS_MT_CFG_DPSLP_ECO_ON_Pos 18UL
+#define BLE_BLESS_MT_CFG_DPSLP_ECO_ON_Msk 0x40000UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_RESET_N_Pos 19UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_RESET_N_Msk 0x80000UL
+#define BLE_BLESS_MT_CFG_RESET_N_Pos 20UL
+#define BLE_BLESS_MT_CFG_RESET_N_Msk 0x100000UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_XTAL_EN_Pos 21UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_XTAL_EN_Msk 0x200000UL
+#define BLE_BLESS_MT_CFG_XTAL_EN_Pos 22UL
+#define BLE_BLESS_MT_CFG_XTAL_EN_Msk 0x400000UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_CLK_EN_Pos 23UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_CLK_EN_Msk 0x800000UL
+#define BLE_BLESS_MT_CFG_BLERD_CLK_EN_Pos 24UL
+#define BLE_BLESS_MT_CFG_BLERD_CLK_EN_Msk 0x1000000UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_RET_LDO_OL_Pos 25UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_RET_LDO_OL_Msk 0x2000000UL
+#define BLE_BLESS_MT_CFG_RET_LDO_OL_Pos 26UL
+#define BLE_BLESS_MT_CFG_RET_LDO_OL_Msk 0x4000000UL
+#define BLE_BLESS_MT_CFG_HVLDO_POR_HV_Pos 27UL
+#define BLE_BLESS_MT_CFG_HVLDO_POR_HV_Msk 0x8000000UL
+/* BLE_BLESS.MT_DELAY_CFG */
+#define BLE_BLESS_MT_DELAY_CFG_HVLDO_STARTUP_DELAY_Pos 0UL
+#define BLE_BLESS_MT_DELAY_CFG_HVLDO_STARTUP_DELAY_Msk 0xFFUL
+#define BLE_BLESS_MT_DELAY_CFG_ISOLATE_DEASSERT_DELAY_Pos 8UL
+#define BLE_BLESS_MT_DELAY_CFG_ISOLATE_DEASSERT_DELAY_Msk 0xFF00UL
+#define BLE_BLESS_MT_DELAY_CFG_ACT_TO_SWITCH_DELAY_Pos 16UL
+#define BLE_BLESS_MT_DELAY_CFG_ACT_TO_SWITCH_DELAY_Msk 0xFF0000UL
+#define BLE_BLESS_MT_DELAY_CFG_HVLDO_DISABLE_DELAY_Pos 24UL
+#define BLE_BLESS_MT_DELAY_CFG_HVLDO_DISABLE_DELAY_Msk 0xFF000000UL
+/* BLE_BLESS.MT_DELAY_CFG2 */
+#define BLE_BLESS_MT_DELAY_CFG2_OSC_STARTUP_DELAY_LF_Pos 0UL
+#define BLE_BLESS_MT_DELAY_CFG2_OSC_STARTUP_DELAY_LF_Msk 0xFFUL
+#define BLE_BLESS_MT_DELAY_CFG2_DSM_OFFSET_TO_WAKEUP_INSTANT_LF_Pos 8UL
+#define BLE_BLESS_MT_DELAY_CFG2_DSM_OFFSET_TO_WAKEUP_INSTANT_LF_Msk 0xFF00UL
+#define BLE_BLESS_MT_DELAY_CFG2_ACT_STARTUP_DELAY_Pos 16UL
+#define BLE_BLESS_MT_DELAY_CFG2_ACT_STARTUP_DELAY_Msk 0xFF0000UL
+#define BLE_BLESS_MT_DELAY_CFG2_DIG_LDO_STARTUP_DELAY_Pos 24UL
+#define BLE_BLESS_MT_DELAY_CFG2_DIG_LDO_STARTUP_DELAY_Msk 0xFF000000UL
+/* BLE_BLESS.MT_DELAY_CFG3 */
+#define BLE_BLESS_MT_DELAY_CFG3_XTAL_DISABLE_DELAY_Pos 0UL
+#define BLE_BLESS_MT_DELAY_CFG3_XTAL_DISABLE_DELAY_Msk 0xFFUL
+#define BLE_BLESS_MT_DELAY_CFG3_DIG_LDO_DISABLE_DELAY_Pos 8UL
+#define BLE_BLESS_MT_DELAY_CFG3_DIG_LDO_DISABLE_DELAY_Msk 0xFF00UL
+#define BLE_BLESS_MT_DELAY_CFG3_VDDR_STABLE_DELAY_Pos 16UL
+#define BLE_BLESS_MT_DELAY_CFG3_VDDR_STABLE_DELAY_Msk 0xFF0000UL
+/* BLE_BLESS.MT_VIO_CTRL */
+#define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Pos 0UL
+#define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Msk 0x1UL
+#define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_DLY_Pos 1UL
+#define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_DLY_Msk 0x2UL
+/* BLE_BLESS.MT_STATUS */
+#define BLE_BLESS_MT_STATUS_BLESS_STATE_Pos 0UL
+#define BLE_BLESS_MT_STATUS_BLESS_STATE_Msk 0x1UL
+#define BLE_BLESS_MT_STATUS_MT_CURR_STATE_Pos 1UL
+#define BLE_BLESS_MT_STATUS_MT_CURR_STATE_Msk 0x1EUL
+#define BLE_BLESS_MT_STATUS_HVLDO_STARTUP_CURR_STATE_Pos 5UL
+#define BLE_BLESS_MT_STATUS_HVLDO_STARTUP_CURR_STATE_Msk 0xE0UL
+#define BLE_BLESS_MT_STATUS_LL_CLK_STATE_Pos 8UL
+#define BLE_BLESS_MT_STATUS_LL_CLK_STATE_Msk 0x100UL
+/* BLE_BLESS.PWR_CTRL_SM_ST */
+#define BLE_BLESS_PWR_CTRL_SM_ST_PWR_CTRL_SM_CURR_STATE_Pos 0UL
+#define BLE_BLESS_PWR_CTRL_SM_ST_PWR_CTRL_SM_CURR_STATE_Msk 0xFUL
+/* BLE_BLESS.HVLDO_CTRL */
+#define BLE_BLESS_HVLDO_CTRL_ADFT_EN_Pos 0UL
+#define BLE_BLESS_HVLDO_CTRL_ADFT_EN_Msk 0x1UL
+#define BLE_BLESS_HVLDO_CTRL_ADFT_CTRL_Pos 1UL
+#define BLE_BLESS_HVLDO_CTRL_ADFT_CTRL_Msk 0x1EUL
+#define BLE_BLESS_HVLDO_CTRL_VREF_EXT_EN_Pos 6UL
+#define BLE_BLESS_HVLDO_CTRL_VREF_EXT_EN_Msk 0x40UL
+#define BLE_BLESS_HVLDO_CTRL_STATUS_Pos 31UL
+#define BLE_BLESS_HVLDO_CTRL_STATUS_Msk 0x80000000UL
+/* BLE_BLESS.MISC_EN_CTRL */
+#define BLE_BLESS_MISC_EN_CTRL_BUCK_EN_CTRL_Pos 0UL
+#define BLE_BLESS_MISC_EN_CTRL_BUCK_EN_CTRL_Msk 0x1UL
+#define BLE_BLESS_MISC_EN_CTRL_ACT_REG_EN_CTRL_Pos 1UL
+#define BLE_BLESS_MISC_EN_CTRL_ACT_REG_EN_CTRL_Msk 0x2UL
+#define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_EN_Pos 2UL
+#define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_EN_Msk 0x4UL
+#define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_MULTI_Pos 3UL
+#define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_MULTI_Msk 0x8UL
+#define BLE_BLESS_MISC_EN_CTRL_LPM_ENTRY_CTRL_MODE_Pos 4UL
+#define BLE_BLESS_MISC_EN_CTRL_LPM_ENTRY_CTRL_MODE_Msk 0x10UL
+/* BLE_BLESS.EFUSE_CONFIG */
+#define BLE_BLESS_EFUSE_CONFIG_EFUSE_MODE_Pos 0UL
+#define BLE_BLESS_EFUSE_CONFIG_EFUSE_MODE_Msk 0x1UL
+#define BLE_BLESS_EFUSE_CONFIG_EFUSE_READ_Pos 1UL
+#define BLE_BLESS_EFUSE_CONFIG_EFUSE_READ_Msk 0x2UL
+#define BLE_BLESS_EFUSE_CONFIG_EFUSE_WRITE_Pos 2UL
+#define BLE_BLESS_EFUSE_CONFIG_EFUSE_WRITE_Msk 0x4UL
+/* BLE_BLESS.EFUSE_TIM_CTRL1 */
+#define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_HIGH_Pos 0UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_HIGH_Msk 0xFFUL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_LOW_Pos 8UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_LOW_Msk 0xFF00UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_SETUP_TIME_Pos 16UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_SETUP_TIME_Msk 0xF0000UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_HOLD_TIME_Pos 20UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_HOLD_TIME_Msk 0xF00000UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_SETUP_TIME_Pos 24UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_SETUP_TIME_Msk 0xF000000UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_HOLD_TIME_Pos 28UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_HOLD_TIME_Msk 0xF0000000UL
+/* BLE_BLESS.EFUSE_TIM_CTRL2 */
+#define BLE_BLESS_EFUSE_TIM_CTRL2_DATA_SAMPLE_TIME_Pos 0UL
+#define BLE_BLESS_EFUSE_TIM_CTRL2_DATA_SAMPLE_TIME_Msk 0xFFUL
+#define BLE_BLESS_EFUSE_TIM_CTRL2_DOUT_CS_HOLD_TIME_Pos 8UL
+#define BLE_BLESS_EFUSE_TIM_CTRL2_DOUT_CS_HOLD_TIME_Msk 0xF00UL
+/* BLE_BLESS.EFUSE_TIM_CTRL3 */
+#define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_SETUP_TIME_Pos 0UL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_SETUP_TIME_Msk 0xFUL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_HOLD_TIME_Pos 4UL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_HOLD_TIME_Msk 0xF0UL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_SETUP_TIME_Pos 8UL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_SETUP_TIME_Msk 0xFF00UL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_HOLD_TIME_Pos 16UL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_HOLD_TIME_Msk 0xFF0000UL
+/* BLE_BLESS.EFUSE_RDATA_L */
+#define BLE_BLESS_EFUSE_RDATA_L_DATA_Pos 0UL
+#define BLE_BLESS_EFUSE_RDATA_L_DATA_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.EFUSE_RDATA_H */
+#define BLE_BLESS_EFUSE_RDATA_H_DATA_Pos 0UL
+#define BLE_BLESS_EFUSE_RDATA_H_DATA_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.EFUSE_WDATA_L */
+#define BLE_BLESS_EFUSE_WDATA_L_DATA_Pos 0UL
+#define BLE_BLESS_EFUSE_WDATA_L_DATA_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.EFUSE_WDATA_H */
+#define BLE_BLESS_EFUSE_WDATA_H_DATA_Pos 0UL
+#define BLE_BLESS_EFUSE_WDATA_H_DATA_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.DIV_BY_625_CFG */
+#define BLE_BLESS_DIV_BY_625_CFG_ENABLE_Pos 1UL
+#define BLE_BLESS_DIV_BY_625_CFG_ENABLE_Msk 0x2UL
+#define BLE_BLESS_DIV_BY_625_CFG_DIVIDEND_Pos 8UL
+#define BLE_BLESS_DIV_BY_625_CFG_DIVIDEND_Msk 0xFFFF00UL
+/* BLE_BLESS.DIV_BY_625_STS */
+#define BLE_BLESS_DIV_BY_625_STS_QUOTIENT_Pos 0UL
+#define BLE_BLESS_DIV_BY_625_STS_QUOTIENT_Msk 0x3FUL
+#define BLE_BLESS_DIV_BY_625_STS_REMAINDER_Pos 8UL
+#define BLE_BLESS_DIV_BY_625_STS_REMAINDER_Msk 0x3FF00UL
+/* BLE_BLESS.PACKET_COUNTER0 */
+#define BLE_BLESS_PACKET_COUNTER0_PACKET_COUNTER_LOWER_Pos 0UL
+#define BLE_BLESS_PACKET_COUNTER0_PACKET_COUNTER_LOWER_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.PACKET_COUNTER2 */
+#define BLE_BLESS_PACKET_COUNTER2_PACKET_COUNTER_UPPER_Pos 0UL
+#define BLE_BLESS_PACKET_COUNTER2_PACKET_COUNTER_UPPER_Msk 0xFFUL
+/* BLE_BLESS.IV_MASTER0 */
+#define BLE_BLESS_IV_MASTER0_IV_MASTER_Pos 0UL
+#define BLE_BLESS_IV_MASTER0_IV_MASTER_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.IV_SLAVE0 */
+#define BLE_BLESS_IV_SLAVE0_IV_SLAVE_Pos 0UL
+#define BLE_BLESS_IV_SLAVE0_IV_SLAVE_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.ENC_KEY */
+#define BLE_BLESS_ENC_KEY_ENC_KEY_Pos 0UL
+#define BLE_BLESS_ENC_KEY_ENC_KEY_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.MIC_IN0 */
+#define BLE_BLESS_MIC_IN0_MIC_IN_Pos 0UL
+#define BLE_BLESS_MIC_IN0_MIC_IN_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.MIC_OUT0 */
+#define BLE_BLESS_MIC_OUT0_MIC_OUT_Pos 0UL
+#define BLE_BLESS_MIC_OUT0_MIC_OUT_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.ENC_PARAMS */
+#define BLE_BLESS_ENC_PARAMS_DATA_PDU_HEADER_Pos 0UL
+#define BLE_BLESS_ENC_PARAMS_DATA_PDU_HEADER_Msk 0x3UL
+#define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_Pos 2UL
+#define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_Msk 0x7CUL
+#define BLE_BLESS_ENC_PARAMS_DIRECTION_Pos 7UL
+#define BLE_BLESS_ENC_PARAMS_DIRECTION_Msk 0x80UL
+#define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_EXT_Pos 8UL
+#define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_EXT_Msk 0x700UL
+#define BLE_BLESS_ENC_PARAMS_MEM_LATENCY_HIDE_Pos 11UL
+#define BLE_BLESS_ENC_PARAMS_MEM_LATENCY_HIDE_Msk 0x800UL
+/* BLE_BLESS.ENC_CONFIG */
+#define BLE_BLESS_ENC_CONFIG_START_PROC_Pos 0UL
+#define BLE_BLESS_ENC_CONFIG_START_PROC_Msk 0x1UL
+#define BLE_BLESS_ENC_CONFIG_ECB_CCM_Pos 1UL
+#define BLE_BLESS_ENC_CONFIG_ECB_CCM_Msk 0x2UL
+#define BLE_BLESS_ENC_CONFIG_DEC_ENC_Pos 2UL
+#define BLE_BLESS_ENC_CONFIG_DEC_ENC_Msk 0x4UL
+#define BLE_BLESS_ENC_CONFIG_PAYLOAD_LENGTH_MSB_Pos 8UL
+#define BLE_BLESS_ENC_CONFIG_PAYLOAD_LENGTH_MSB_Msk 0xFF00UL
+#define BLE_BLESS_ENC_CONFIG_B0_FLAGS_Pos 16UL
+#define BLE_BLESS_ENC_CONFIG_B0_FLAGS_Msk 0xFF0000UL
+#define BLE_BLESS_ENC_CONFIG_AES_B0_DATA_OVERRIDE_Pos 24UL
+#define BLE_BLESS_ENC_CONFIG_AES_B0_DATA_OVERRIDE_Msk 0x1000000UL
+/* BLE_BLESS.ENC_INTR_EN */
+#define BLE_BLESS_ENC_INTR_EN_AUTH_PASS_INTR_EN_Pos 0UL
+#define BLE_BLESS_ENC_INTR_EN_AUTH_PASS_INTR_EN_Msk 0x1UL
+#define BLE_BLESS_ENC_INTR_EN_ECB_PROC_INTR_EN_Pos 1UL
+#define BLE_BLESS_ENC_INTR_EN_ECB_PROC_INTR_EN_Msk 0x2UL
+#define BLE_BLESS_ENC_INTR_EN_CCM_PROC_INTR_EN_Pos 2UL
+#define BLE_BLESS_ENC_INTR_EN_CCM_PROC_INTR_EN_Msk 0x4UL
+/* BLE_BLESS.ENC_INTR */
+#define BLE_BLESS_ENC_INTR_AUTH_PASS_INTR_Pos 0UL
+#define BLE_BLESS_ENC_INTR_AUTH_PASS_INTR_Msk 0x1UL
+#define BLE_BLESS_ENC_INTR_ECB_PROC_INTR_Pos 1UL
+#define BLE_BLESS_ENC_INTR_ECB_PROC_INTR_Msk 0x2UL
+#define BLE_BLESS_ENC_INTR_CCM_PROC_INTR_Pos 2UL
+#define BLE_BLESS_ENC_INTR_CCM_PROC_INTR_Msk 0x4UL
+#define BLE_BLESS_ENC_INTR_IN_DATA_CLEAR_Pos 3UL
+#define BLE_BLESS_ENC_INTR_IN_DATA_CLEAR_Msk 0x8UL
+/* BLE_BLESS.B1_DATA_REG */
+#define BLE_BLESS_B1_DATA_REG_B1_DATA_Pos 0UL
+#define BLE_BLESS_B1_DATA_REG_B1_DATA_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.ENC_MEM_BASE_ADDR */
+#define BLE_BLESS_ENC_MEM_BASE_ADDR_ENC_MEM_Pos 0UL
+#define BLE_BLESS_ENC_MEM_BASE_ADDR_ENC_MEM_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.TRIM_LDO_0 */
+#define BLE_BLESS_TRIM_LDO_0_ACT_LDO_VREG_Pos 0UL
+#define BLE_BLESS_TRIM_LDO_0_ACT_LDO_VREG_Msk 0xFUL
+#define BLE_BLESS_TRIM_LDO_0_ACT_LDO_ITAIL_Pos 4UL
+#define BLE_BLESS_TRIM_LDO_0_ACT_LDO_ITAIL_Msk 0xF0UL
+/* BLE_BLESS.TRIM_LDO_1 */
+#define BLE_BLESS_TRIM_LDO_1_ACT_REF_BGR_Pos 0UL
+#define BLE_BLESS_TRIM_LDO_1_ACT_REF_BGR_Msk 0xFUL
+#define BLE_BLESS_TRIM_LDO_1_SB_BGRES_Pos 4UL
+#define BLE_BLESS_TRIM_LDO_1_SB_BGRES_Msk 0xF0UL
+/* BLE_BLESS.TRIM_LDO_2 */
+#define BLE_BLESS_TRIM_LDO_2_SB_BMULT_RES_Pos 0UL
+#define BLE_BLESS_TRIM_LDO_2_SB_BMULT_RES_Msk 0x1FUL
+#define BLE_BLESS_TRIM_LDO_2_SB_BMULT_NBIAS_Pos 5UL
+#define BLE_BLESS_TRIM_LDO_2_SB_BMULT_NBIAS_Msk 0x60UL
+/* BLE_BLESS.TRIM_LDO_3 */
+#define BLE_BLESS_TRIM_LDO_3_LVDET_Pos 0UL
+#define BLE_BLESS_TRIM_LDO_3_LVDET_Msk 0x1FUL
+#define BLE_BLESS_TRIM_LDO_3_SLOPE_SB_BMULT_Pos 5UL
+#define BLE_BLESS_TRIM_LDO_3_SLOPE_SB_BMULT_Msk 0x60UL
+/* BLE_BLESS.TRIM_MXD */
+#define BLE_BLESS_TRIM_MXD_MXD_TRIM_BITS_Pos 0UL
+#define BLE_BLESS_TRIM_MXD_MXD_TRIM_BITS_Msk 0xFFUL
+/* BLE_BLESS.TRIM_LDO_4 */
+#define BLE_BLESS_TRIM_LDO_4_T_LDO_Pos 0UL
+#define BLE_BLESS_TRIM_LDO_4_T_LDO_Msk 0xFFUL
+/* BLE_BLESS.TRIM_LDO_5 */
+#define BLE_BLESS_TRIM_LDO_5_RESERVED_Pos 0UL
+#define BLE_BLESS_TRIM_LDO_5_RESERVED_Msk 0xFFUL
+
+
+#endif /* _CYIP_BLE_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_canfd.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_canfd.h
new file mode 100644
index 0000000000..dfaeaab56d
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_canfd.h
@@ -0,0 +1,953 @@
+/***************************************************************************//**
+* \file cyip_canfd.h
+*
+* \brief
+* CANFD IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_CANFD_H_
+#define _CYIP_CANFD_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* CANFD
+*******************************************************************************/
+
+#define CANFD_CH_M_TTCAN_SECTION_SIZE 0x00000180UL
+#define CANFD_CH_SECTION_SIZE 0x00000200UL
+#define CANFD_SECTION_SIZE 0x00020000UL
+
+/**
+ * \brief TTCAN 3PIP, includes FD (CANFD_CH_M_TTCAN)
+ */
+typedef struct {
+ __IM uint32_t CREL; /*!< 0x00000000 Core Release Register */
+ __IM uint32_t ENDN; /*!< 0x00000004 Endian Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t DBTP; /*!< 0x0000000C Data Bit Timing & Prescaler Register */
+ __IOM uint32_t TEST; /*!< 0x00000010 Test Register */
+ __IOM uint32_t RWD; /*!< 0x00000014 RAM Watchdog */
+ __IOM uint32_t CCCR; /*!< 0x00000018 CC Control Register */
+ __IOM uint32_t NBTP; /*!< 0x0000001C Nominal Bit Timing & Prescaler Register */
+ __IOM uint32_t TSCC; /*!< 0x00000020 Timestamp Counter Configuration */
+ __IOM uint32_t TSCV; /*!< 0x00000024 Timestamp Counter Value */
+ __IOM uint32_t TOCC; /*!< 0x00000028 Timeout Counter Configuration */
+ __IOM uint32_t TOCV; /*!< 0x0000002C Timeout Counter Value */
+ __IM uint32_t RESERVED1[4];
+ __IM uint32_t ECR; /*!< 0x00000040 Error Counter Register */
+ __IM uint32_t PSR; /*!< 0x00000044 Protocol Status Register */
+ __IOM uint32_t TDCR; /*!< 0x00000048 Transmitter Delay Compensation Register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t IR; /*!< 0x00000050 Interrupt Register */
+ __IOM uint32_t IE; /*!< 0x00000054 Interrupt Enable */
+ __IOM uint32_t ILS; /*!< 0x00000058 Interrupt Line Select */
+ __IOM uint32_t ILE; /*!< 0x0000005C Interrupt Line Enable */
+ __IM uint32_t RESERVED3[8];
+ __IOM uint32_t GFC; /*!< 0x00000080 Global Filter Configuration */
+ __IOM uint32_t SIDFC; /*!< 0x00000084 Standard ID Filter Configuration */
+ __IOM uint32_t XIDFC; /*!< 0x00000088 Extended ID Filter Configuration */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t XIDAM; /*!< 0x00000090 Extended ID AND Mask */
+ __IM uint32_t HPMS; /*!< 0x00000094 High Priority Message Status */
+ __IOM uint32_t NDAT1; /*!< 0x00000098 New Data 1 */
+ __IOM uint32_t NDAT2; /*!< 0x0000009C New Data 2 */
+ __IOM uint32_t RXF0C; /*!< 0x000000A0 Rx FIFO 0 Configuration */
+ __IM uint32_t RXF0S; /*!< 0x000000A4 Rx FIFO 0 Status */
+ __IOM uint32_t RXF0A; /*!< 0x000000A8 Rx FIFO 0 Acknowledge */
+ __IOM uint32_t RXBC; /*!< 0x000000AC Rx Buffer Configuration */
+ __IOM uint32_t RXF1C; /*!< 0x000000B0 Rx FIFO 1 Configuration */
+ __IM uint32_t RXF1S; /*!< 0x000000B4 Rx FIFO 1 Status */
+ __IOM uint32_t RXF1A; /*!< 0x000000B8 Rx FIFO 1 Acknowledge */
+ __IOM uint32_t RXESC; /*!< 0x000000BC Rx Buffer / FIFO Element Size Configuration */
+ __IOM uint32_t TXBC; /*!< 0x000000C0 Tx Buffer Configuration */
+ __IM uint32_t TXFQS; /*!< 0x000000C4 Tx FIFO/Queue Status */
+ __IOM uint32_t TXESC; /*!< 0x000000C8 Tx Buffer Element Size Configuration */
+ __IM uint32_t TXBRP; /*!< 0x000000CC Tx Buffer Request Pending */
+ __IOM uint32_t TXBAR; /*!< 0x000000D0 Tx Buffer Add Request */
+ __IOM uint32_t TXBCR; /*!< 0x000000D4 Tx Buffer Cancellation Request */
+ __IM uint32_t TXBTO; /*!< 0x000000D8 Tx Buffer Transmission Occurred */
+ __IM uint32_t TXBCF; /*!< 0x000000DC Tx Buffer Cancellation Finished */
+ __IOM uint32_t TXBTIE; /*!< 0x000000E0 Tx Buffer Transmission Interrupt Enable */
+ __IOM uint32_t TXBCIE; /*!< 0x000000E4 Tx Buffer Cancellation Finished Interrupt Enable */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t TXEFC; /*!< 0x000000F0 Tx Event FIFO Configuration */
+ __IM uint32_t TXEFS; /*!< 0x000000F4 Tx Event FIFO Status */
+ __IOM uint32_t TXEFA; /*!< 0x000000F8 Tx Event FIFO Acknowledge */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t TTTMC; /*!< 0x00000100 TT Trigger Memory Configuration */
+ __IOM uint32_t TTRMC; /*!< 0x00000104 TT Reference Message Configuration */
+ __IOM uint32_t TTOCF; /*!< 0x00000108 TT Operation Configuration */
+ __IOM uint32_t TTMLM; /*!< 0x0000010C TT Matrix Limits */
+ __IOM uint32_t TURCF; /*!< 0x00000110 TUR Configuration */
+ __IOM uint32_t TTOCN; /*!< 0x00000114 TT Operation Control */
+ __IOM uint32_t TTGTP; /*!< 0x00000118 TT Global Time Preset */
+ __IOM uint32_t TTTMK; /*!< 0x0000011C TT Time Mark */
+ __IOM uint32_t TTIR; /*!< 0x00000120 TT Interrupt Register */
+ __IOM uint32_t TTIE; /*!< 0x00000124 TT Interrupt Enable */
+ __IOM uint32_t TTILS; /*!< 0x00000128 TT Interrupt Line Select */
+ __IM uint32_t TTOST; /*!< 0x0000012C TT Operation Status */
+ __IM uint32_t TURNA; /*!< 0x00000130 TUR Numerator Actual */
+ __IM uint32_t TTLGT; /*!< 0x00000134 TT Local & Global Time */
+ __IM uint32_t TTCTC; /*!< 0x00000138 TT Cycle Time & Count */
+ __IM uint32_t TTCPT; /*!< 0x0000013C TT Capture Time */
+ __IM uint32_t TTCSM; /*!< 0x00000140 TT Cycle Sync Mark */
+ __IM uint32_t RESERVED7[15];
+} CANFD_CH_M_TTCAN_V1_Type; /*!< Size = 384 (0x180) */
+
+/**
+ * \brief FIFO wrapper around M_TTCAN 3PIP, to enable DMA (CANFD_CH)
+ */
+typedef struct {
+ CANFD_CH_M_TTCAN_V1_Type M_TTCAN; /*!< 0x00000000 TTCAN 3PIP, includes FD */
+ __IOM uint32_t RXFTOP_CTL; /*!< 0x00000180 Receive FIFO Top control */
+ __IM uint32_t RESERVED[7];
+ __IM uint32_t RXFTOP0_STAT; /*!< 0x000001A0 Receive FIFO 0 Top Status */
+ __IM uint32_t RESERVED1;
+ __IM uint32_t RXFTOP0_DATA; /*!< 0x000001A8 Receive FIFO 0 Top Data */
+ __IM uint32_t RESERVED2;
+ __IM uint32_t RXFTOP1_STAT; /*!< 0x000001B0 Receive FIFO 1 Top Status */
+ __IM uint32_t RESERVED3;
+ __IM uint32_t RXFTOP1_DATA; /*!< 0x000001B8 Receive FIFO 1 Top Data */
+ __IM uint32_t RESERVED4[17];
+} CANFD_CH_V1_Type; /*!< Size = 512 (0x200) */
+
+/**
+ * \brief CAN Controller (CANFD)
+ */
+typedef struct {
+ CANFD_CH_V1_Type CH[8]; /*!< 0x00000000 FIFO wrapper around M_TTCAN 3PIP, to enable DMA */
+ __IOM uint32_t CTL; /*!< 0x00001000 Global CAN control register */
+ __IM uint32_t STATUS; /*!< 0x00001004 Global CAN status register */
+ __IM uint32_t RESERVED[2];
+ __IM uint32_t INTR0_CAUSE; /*!< 0x00001010 Consolidated interrupt0 cause register */
+ __IM uint32_t INTR1_CAUSE; /*!< 0x00001014 Consolidated interrupt1 cause register */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t TS_CTL; /*!< 0x00001020 Time Stamp control register */
+ __IOM uint32_t TS_CNT; /*!< 0x00001024 Time Stamp counter value */
+ __IM uint32_t RESERVED2[22];
+ __IOM uint32_t ECC_CTL; /*!< 0x00001080 ECC control */
+ __IOM uint32_t ECC_ERR_INJ; /*!< 0x00001084 ECC error injection */
+} CANFD_V1_Type; /*!< Size = 4232 (0x1088) */
+
+
+/* CANFD_CH_M_TTCAN.CREL */
+#define CANFD_CH_M_TTCAN_CREL_DAY_Pos 0UL
+#define CANFD_CH_M_TTCAN_CREL_DAY_Msk 0xFFUL
+#define CANFD_CH_M_TTCAN_CREL_MON_Pos 8UL
+#define CANFD_CH_M_TTCAN_CREL_MON_Msk 0xFF00UL
+#define CANFD_CH_M_TTCAN_CREL_YEAR_Pos 16UL
+#define CANFD_CH_M_TTCAN_CREL_YEAR_Msk 0xF0000UL
+#define CANFD_CH_M_TTCAN_CREL_SUBSTEP_Pos 20UL
+#define CANFD_CH_M_TTCAN_CREL_SUBSTEP_Msk 0xF00000UL
+#define CANFD_CH_M_TTCAN_CREL_STEP_Pos 24UL
+#define CANFD_CH_M_TTCAN_CREL_STEP_Msk 0xF000000UL
+#define CANFD_CH_M_TTCAN_CREL_REL_Pos 28UL
+#define CANFD_CH_M_TTCAN_CREL_REL_Msk 0xF0000000UL
+/* CANFD_CH_M_TTCAN.ENDN */
+#define CANFD_CH_M_TTCAN_ENDN_ETV_Pos 0UL
+#define CANFD_CH_M_TTCAN_ENDN_ETV_Msk 0xFFFFFFFFUL
+/* CANFD_CH_M_TTCAN.DBTP */
+#define CANFD_CH_M_TTCAN_DBTP_DSJW_Pos 0UL
+#define CANFD_CH_M_TTCAN_DBTP_DSJW_Msk 0xFUL
+#define CANFD_CH_M_TTCAN_DBTP_DTSEG2_Pos 4UL
+#define CANFD_CH_M_TTCAN_DBTP_DTSEG2_Msk 0xF0UL
+#define CANFD_CH_M_TTCAN_DBTP_DTSEG1_Pos 8UL
+#define CANFD_CH_M_TTCAN_DBTP_DTSEG1_Msk 0x1F00UL
+#define CANFD_CH_M_TTCAN_DBTP_DBRP_Pos 16UL
+#define CANFD_CH_M_TTCAN_DBTP_DBRP_Msk 0x1F0000UL
+#define CANFD_CH_M_TTCAN_DBTP_TDC_Pos 23UL
+#define CANFD_CH_M_TTCAN_DBTP_TDC_Msk 0x800000UL
+/* CANFD_CH_M_TTCAN.TEST */
+#define CANFD_CH_M_TTCAN_TEST_TAM_Pos 0UL
+#define CANFD_CH_M_TTCAN_TEST_TAM_Msk 0x1UL
+#define CANFD_CH_M_TTCAN_TEST_TAT_Pos 1UL
+#define CANFD_CH_M_TTCAN_TEST_TAT_Msk 0x2UL
+#define CANFD_CH_M_TTCAN_TEST_CAM_Pos 2UL
+#define CANFD_CH_M_TTCAN_TEST_CAM_Msk 0x4UL
+#define CANFD_CH_M_TTCAN_TEST_CAT_Pos 3UL
+#define CANFD_CH_M_TTCAN_TEST_CAT_Msk 0x8UL
+#define CANFD_CH_M_TTCAN_TEST_LBCK_Pos 4UL
+#define CANFD_CH_M_TTCAN_TEST_LBCK_Msk 0x10UL
+#define CANFD_CH_M_TTCAN_TEST_TX_Pos 5UL
+#define CANFD_CH_M_TTCAN_TEST_TX_Msk 0x60UL
+#define CANFD_CH_M_TTCAN_TEST_RX_Pos 7UL
+#define CANFD_CH_M_TTCAN_TEST_RX_Msk 0x80UL
+/* CANFD_CH_M_TTCAN.RWD */
+#define CANFD_CH_M_TTCAN_RWD_WDC_Pos 0UL
+#define CANFD_CH_M_TTCAN_RWD_WDC_Msk 0xFFUL
+#define CANFD_CH_M_TTCAN_RWD_WDV_Pos 8UL
+#define CANFD_CH_M_TTCAN_RWD_WDV_Msk 0xFF00UL
+/* CANFD_CH_M_TTCAN.CCCR */
+#define CANFD_CH_M_TTCAN_CCCR_INIT_Pos 0UL
+#define CANFD_CH_M_TTCAN_CCCR_INIT_Msk 0x1UL
+#define CANFD_CH_M_TTCAN_CCCR_CCE_Pos 1UL
+#define CANFD_CH_M_TTCAN_CCCR_CCE_Msk 0x2UL
+#define CANFD_CH_M_TTCAN_CCCR_ASM_Pos 2UL
+#define CANFD_CH_M_TTCAN_CCCR_ASM_Msk 0x4UL
+#define CANFD_CH_M_TTCAN_CCCR_CSA_Pos 3UL
+#define CANFD_CH_M_TTCAN_CCCR_CSA_Msk 0x8UL
+#define CANFD_CH_M_TTCAN_CCCR_CSR_Pos 4UL
+#define CANFD_CH_M_TTCAN_CCCR_CSR_Msk 0x10UL
+#define CANFD_CH_M_TTCAN_CCCR_MON__Pos 5UL
+#define CANFD_CH_M_TTCAN_CCCR_MON__Msk 0x20UL
+#define CANFD_CH_M_TTCAN_CCCR_DAR_Pos 6UL
+#define CANFD_CH_M_TTCAN_CCCR_DAR_Msk 0x40UL
+#define CANFD_CH_M_TTCAN_CCCR_TEST_Pos 7UL
+#define CANFD_CH_M_TTCAN_CCCR_TEST_Msk 0x80UL
+#define CANFD_CH_M_TTCAN_CCCR_FDOE_Pos 8UL
+#define CANFD_CH_M_TTCAN_CCCR_FDOE_Msk 0x100UL
+#define CANFD_CH_M_TTCAN_CCCR_BRSE_Pos 9UL
+#define CANFD_CH_M_TTCAN_CCCR_BRSE_Msk 0x200UL
+#define CANFD_CH_M_TTCAN_CCCR_PXHD_Pos 12UL
+#define CANFD_CH_M_TTCAN_CCCR_PXHD_Msk 0x1000UL
+#define CANFD_CH_M_TTCAN_CCCR_EFBI_Pos 13UL
+#define CANFD_CH_M_TTCAN_CCCR_EFBI_Msk 0x2000UL
+#define CANFD_CH_M_TTCAN_CCCR_TXP_Pos 14UL
+#define CANFD_CH_M_TTCAN_CCCR_TXP_Msk 0x4000UL
+#define CANFD_CH_M_TTCAN_CCCR_NISO_Pos 15UL
+#define CANFD_CH_M_TTCAN_CCCR_NISO_Msk 0x8000UL
+/* CANFD_CH_M_TTCAN.NBTP */
+#define CANFD_CH_M_TTCAN_NBTP_NTSEG2_Pos 0UL
+#define CANFD_CH_M_TTCAN_NBTP_NTSEG2_Msk 0x7FUL
+#define CANFD_CH_M_TTCAN_NBTP_NTSEG1_Pos 8UL
+#define CANFD_CH_M_TTCAN_NBTP_NTSEG1_Msk 0xFF00UL
+#define CANFD_CH_M_TTCAN_NBTP_NBRP_Pos 16UL
+#define CANFD_CH_M_TTCAN_NBTP_NBRP_Msk 0x1FF0000UL
+#define CANFD_CH_M_TTCAN_NBTP_NSJW_Pos 25UL
+#define CANFD_CH_M_TTCAN_NBTP_NSJW_Msk 0xFE000000UL
+/* CANFD_CH_M_TTCAN.TSCC */
+#define CANFD_CH_M_TTCAN_TSCC_TSS_Pos 0UL
+#define CANFD_CH_M_TTCAN_TSCC_TSS_Msk 0x3UL
+#define CANFD_CH_M_TTCAN_TSCC_TCP_Pos 16UL
+#define CANFD_CH_M_TTCAN_TSCC_TCP_Msk 0xF0000UL
+/* CANFD_CH_M_TTCAN.TSCV */
+#define CANFD_CH_M_TTCAN_TSCV_TSC_Pos 0UL
+#define CANFD_CH_M_TTCAN_TSCV_TSC_Msk 0xFFFFUL
+/* CANFD_CH_M_TTCAN.TOCC */
+#define CANFD_CH_M_TTCAN_TOCC_ETOC_Pos 0UL
+#define CANFD_CH_M_TTCAN_TOCC_ETOC_Msk 0x1UL
+#define CANFD_CH_M_TTCAN_TOCC_TOS_Pos 1UL
+#define CANFD_CH_M_TTCAN_TOCC_TOS_Msk 0x6UL
+#define CANFD_CH_M_TTCAN_TOCC_TOP_Pos 16UL
+#define CANFD_CH_M_TTCAN_TOCC_TOP_Msk 0xFFFF0000UL
+/* CANFD_CH_M_TTCAN.TOCV */
+#define CANFD_CH_M_TTCAN_TOCV_TOC_Pos 0UL
+#define CANFD_CH_M_TTCAN_TOCV_TOC_Msk 0xFFFFUL
+/* CANFD_CH_M_TTCAN.ECR */
+#define CANFD_CH_M_TTCAN_ECR_TEC_Pos 0UL
+#define CANFD_CH_M_TTCAN_ECR_TEC_Msk 0xFFUL
+#define CANFD_CH_M_TTCAN_ECR_REC_Pos 8UL
+#define CANFD_CH_M_TTCAN_ECR_REC_Msk 0x7F00UL
+#define CANFD_CH_M_TTCAN_ECR_RP_Pos 15UL
+#define CANFD_CH_M_TTCAN_ECR_RP_Msk 0x8000UL
+#define CANFD_CH_M_TTCAN_ECR_CEL_Pos 16UL
+#define CANFD_CH_M_TTCAN_ECR_CEL_Msk 0xFF0000UL
+/* CANFD_CH_M_TTCAN.PSR */
+#define CANFD_CH_M_TTCAN_PSR_LEC_Pos 0UL
+#define CANFD_CH_M_TTCAN_PSR_LEC_Msk 0x7UL
+#define CANFD_CH_M_TTCAN_PSR_ACT_Pos 3UL
+#define CANFD_CH_M_TTCAN_PSR_ACT_Msk 0x18UL
+#define CANFD_CH_M_TTCAN_PSR_EP_Pos 5UL
+#define CANFD_CH_M_TTCAN_PSR_EP_Msk 0x20UL
+#define CANFD_CH_M_TTCAN_PSR_EW_Pos 6UL
+#define CANFD_CH_M_TTCAN_PSR_EW_Msk 0x40UL
+#define CANFD_CH_M_TTCAN_PSR_BO_Pos 7UL
+#define CANFD_CH_M_TTCAN_PSR_BO_Msk 0x80UL
+#define CANFD_CH_M_TTCAN_PSR_DLEC_Pos 8UL
+#define CANFD_CH_M_TTCAN_PSR_DLEC_Msk 0x700UL
+#define CANFD_CH_M_TTCAN_PSR_RESI_Pos 11UL
+#define CANFD_CH_M_TTCAN_PSR_RESI_Msk 0x800UL
+#define CANFD_CH_M_TTCAN_PSR_RBRS_Pos 12UL
+#define CANFD_CH_M_TTCAN_PSR_RBRS_Msk 0x1000UL
+#define CANFD_CH_M_TTCAN_PSR_RFDF_Pos 13UL
+#define CANFD_CH_M_TTCAN_PSR_RFDF_Msk 0x2000UL
+#define CANFD_CH_M_TTCAN_PSR_PXE_Pos 14UL
+#define CANFD_CH_M_TTCAN_PSR_PXE_Msk 0x4000UL
+#define CANFD_CH_M_TTCAN_PSR_TDCV_Pos 16UL
+#define CANFD_CH_M_TTCAN_PSR_TDCV_Msk 0x7F0000UL
+/* CANFD_CH_M_TTCAN.TDCR */
+#define CANFD_CH_M_TTCAN_TDCR_TDCF_Pos 0UL
+#define CANFD_CH_M_TTCAN_TDCR_TDCF_Msk 0x7FUL
+#define CANFD_CH_M_TTCAN_TDCR_TDCO_Pos 8UL
+#define CANFD_CH_M_TTCAN_TDCR_TDCO_Msk 0x7F00UL
+/* CANFD_CH_M_TTCAN.IR */
+#define CANFD_CH_M_TTCAN_IR_RF0N_Pos 0UL
+#define CANFD_CH_M_TTCAN_IR_RF0N_Msk 0x1UL
+#define CANFD_CH_M_TTCAN_IR_RF0W_Pos 1UL
+#define CANFD_CH_M_TTCAN_IR_RF0W_Msk 0x2UL
+#define CANFD_CH_M_TTCAN_IR_RF0F_Pos 2UL
+#define CANFD_CH_M_TTCAN_IR_RF0F_Msk 0x4UL
+#define CANFD_CH_M_TTCAN_IR_RF0L__Pos 3UL
+#define CANFD_CH_M_TTCAN_IR_RF0L__Msk 0x8UL
+#define CANFD_CH_M_TTCAN_IR_RF1N_Pos 4UL
+#define CANFD_CH_M_TTCAN_IR_RF1N_Msk 0x10UL
+#define CANFD_CH_M_TTCAN_IR_RF1W_Pos 5UL
+#define CANFD_CH_M_TTCAN_IR_RF1W_Msk 0x20UL
+#define CANFD_CH_M_TTCAN_IR_RF1F_Pos 6UL
+#define CANFD_CH_M_TTCAN_IR_RF1F_Msk 0x40UL
+#define CANFD_CH_M_TTCAN_IR_RF1L__Pos 7UL
+#define CANFD_CH_M_TTCAN_IR_RF1L__Msk 0x80UL
+#define CANFD_CH_M_TTCAN_IR_HPM_Pos 8UL
+#define CANFD_CH_M_TTCAN_IR_HPM_Msk 0x100UL
+#define CANFD_CH_M_TTCAN_IR_TC_Pos 9UL
+#define CANFD_CH_M_TTCAN_IR_TC_Msk 0x200UL
+#define CANFD_CH_M_TTCAN_IR_TCF_Pos 10UL
+#define CANFD_CH_M_TTCAN_IR_TCF_Msk 0x400UL
+#define CANFD_CH_M_TTCAN_IR_TFE_Pos 11UL
+#define CANFD_CH_M_TTCAN_IR_TFE_Msk 0x800UL
+#define CANFD_CH_M_TTCAN_IR_TEFN_Pos 12UL
+#define CANFD_CH_M_TTCAN_IR_TEFN_Msk 0x1000UL
+#define CANFD_CH_M_TTCAN_IR_TEFW_Pos 13UL
+#define CANFD_CH_M_TTCAN_IR_TEFW_Msk 0x2000UL
+#define CANFD_CH_M_TTCAN_IR_TEFF_Pos 14UL
+#define CANFD_CH_M_TTCAN_IR_TEFF_Msk 0x4000UL
+#define CANFD_CH_M_TTCAN_IR_TEFL__Pos 15UL
+#define CANFD_CH_M_TTCAN_IR_TEFL__Msk 0x8000UL
+#define CANFD_CH_M_TTCAN_IR_TSW_Pos 16UL
+#define CANFD_CH_M_TTCAN_IR_TSW_Msk 0x10000UL
+#define CANFD_CH_M_TTCAN_IR_MRAF_Pos 17UL
+#define CANFD_CH_M_TTCAN_IR_MRAF_Msk 0x20000UL
+#define CANFD_CH_M_TTCAN_IR_TOO_Pos 18UL
+#define CANFD_CH_M_TTCAN_IR_TOO_Msk 0x40000UL
+#define CANFD_CH_M_TTCAN_IR_DRX_Pos 19UL
+#define CANFD_CH_M_TTCAN_IR_DRX_Msk 0x80000UL
+#define CANFD_CH_M_TTCAN_IR_BEC_Pos 20UL
+#define CANFD_CH_M_TTCAN_IR_BEC_Msk 0x100000UL
+#define CANFD_CH_M_TTCAN_IR_BEU_Pos 21UL
+#define CANFD_CH_M_TTCAN_IR_BEU_Msk 0x200000UL
+#define CANFD_CH_M_TTCAN_IR_ELO_Pos 22UL
+#define CANFD_CH_M_TTCAN_IR_ELO_Msk 0x400000UL
+#define CANFD_CH_M_TTCAN_IR_EP__Pos 23UL
+#define CANFD_CH_M_TTCAN_IR_EP__Msk 0x800000UL
+#define CANFD_CH_M_TTCAN_IR_EW__Pos 24UL
+#define CANFD_CH_M_TTCAN_IR_EW__Msk 0x1000000UL
+#define CANFD_CH_M_TTCAN_IR_BO__Pos 25UL
+#define CANFD_CH_M_TTCAN_IR_BO__Msk 0x2000000UL
+#define CANFD_CH_M_TTCAN_IR_WDI_Pos 26UL
+#define CANFD_CH_M_TTCAN_IR_WDI_Msk 0x4000000UL
+#define CANFD_CH_M_TTCAN_IR_PEA_Pos 27UL
+#define CANFD_CH_M_TTCAN_IR_PEA_Msk 0x8000000UL
+#define CANFD_CH_M_TTCAN_IR_PED_Pos 28UL
+#define CANFD_CH_M_TTCAN_IR_PED_Msk 0x10000000UL
+#define CANFD_CH_M_TTCAN_IR_ARA_Pos 29UL
+#define CANFD_CH_M_TTCAN_IR_ARA_Msk 0x20000000UL
+/* CANFD_CH_M_TTCAN.IE */
+#define CANFD_CH_M_TTCAN_IE_RF0NE_Pos 0UL
+#define CANFD_CH_M_TTCAN_IE_RF0NE_Msk 0x1UL
+#define CANFD_CH_M_TTCAN_IE_RF0WE_Pos 1UL
+#define CANFD_CH_M_TTCAN_IE_RF0WE_Msk 0x2UL
+#define CANFD_CH_M_TTCAN_IE_RF0FE_Pos 2UL
+#define CANFD_CH_M_TTCAN_IE_RF0FE_Msk 0x4UL
+#define CANFD_CH_M_TTCAN_IE_RF0LE_Pos 3UL
+#define CANFD_CH_M_TTCAN_IE_RF0LE_Msk 0x8UL
+#define CANFD_CH_M_TTCAN_IE_RF1NE_Pos 4UL
+#define CANFD_CH_M_TTCAN_IE_RF1NE_Msk 0x10UL
+#define CANFD_CH_M_TTCAN_IE_RF1WE_Pos 5UL
+#define CANFD_CH_M_TTCAN_IE_RF1WE_Msk 0x20UL
+#define CANFD_CH_M_TTCAN_IE_RF1FE_Pos 6UL
+#define CANFD_CH_M_TTCAN_IE_RF1FE_Msk 0x40UL
+#define CANFD_CH_M_TTCAN_IE_RF1LE_Pos 7UL
+#define CANFD_CH_M_TTCAN_IE_RF1LE_Msk 0x80UL
+#define CANFD_CH_M_TTCAN_IE_HPME_Pos 8UL
+#define CANFD_CH_M_TTCAN_IE_HPME_Msk 0x100UL
+#define CANFD_CH_M_TTCAN_IE_TCE_Pos 9UL
+#define CANFD_CH_M_TTCAN_IE_TCE_Msk 0x200UL
+#define CANFD_CH_M_TTCAN_IE_TCFE_Pos 10UL
+#define CANFD_CH_M_TTCAN_IE_TCFE_Msk 0x400UL
+#define CANFD_CH_M_TTCAN_IE_TFEE_Pos 11UL
+#define CANFD_CH_M_TTCAN_IE_TFEE_Msk 0x800UL
+#define CANFD_CH_M_TTCAN_IE_TEFNE_Pos 12UL
+#define CANFD_CH_M_TTCAN_IE_TEFNE_Msk 0x1000UL
+#define CANFD_CH_M_TTCAN_IE_TEFWE_Pos 13UL
+#define CANFD_CH_M_TTCAN_IE_TEFWE_Msk 0x2000UL
+#define CANFD_CH_M_TTCAN_IE_TEFFE_Pos 14UL
+#define CANFD_CH_M_TTCAN_IE_TEFFE_Msk 0x4000UL
+#define CANFD_CH_M_TTCAN_IE_TEFLE_Pos 15UL
+#define CANFD_CH_M_TTCAN_IE_TEFLE_Msk 0x8000UL
+#define CANFD_CH_M_TTCAN_IE_TSWE_Pos 16UL
+#define CANFD_CH_M_TTCAN_IE_TSWE_Msk 0x10000UL
+#define CANFD_CH_M_TTCAN_IE_MRAFE_Pos 17UL
+#define CANFD_CH_M_TTCAN_IE_MRAFE_Msk 0x20000UL
+#define CANFD_CH_M_TTCAN_IE_TOOE_Pos 18UL
+#define CANFD_CH_M_TTCAN_IE_TOOE_Msk 0x40000UL
+#define CANFD_CH_M_TTCAN_IE_DRXE_Pos 19UL
+#define CANFD_CH_M_TTCAN_IE_DRXE_Msk 0x80000UL
+#define CANFD_CH_M_TTCAN_IE_BECE_Pos 20UL
+#define CANFD_CH_M_TTCAN_IE_BECE_Msk 0x100000UL
+#define CANFD_CH_M_TTCAN_IE_BEUE_Pos 21UL
+#define CANFD_CH_M_TTCAN_IE_BEUE_Msk 0x200000UL
+#define CANFD_CH_M_TTCAN_IE_ELOE_Pos 22UL
+#define CANFD_CH_M_TTCAN_IE_ELOE_Msk 0x400000UL
+#define CANFD_CH_M_TTCAN_IE_EPE_Pos 23UL
+#define CANFD_CH_M_TTCAN_IE_EPE_Msk 0x800000UL
+#define CANFD_CH_M_TTCAN_IE_EWE_Pos 24UL
+#define CANFD_CH_M_TTCAN_IE_EWE_Msk 0x1000000UL
+#define CANFD_CH_M_TTCAN_IE_BOE_Pos 25UL
+#define CANFD_CH_M_TTCAN_IE_BOE_Msk 0x2000000UL
+#define CANFD_CH_M_TTCAN_IE_WDIE_Pos 26UL
+#define CANFD_CH_M_TTCAN_IE_WDIE_Msk 0x4000000UL
+#define CANFD_CH_M_TTCAN_IE_PEAE_Pos 27UL
+#define CANFD_CH_M_TTCAN_IE_PEAE_Msk 0x8000000UL
+#define CANFD_CH_M_TTCAN_IE_PEDE_Pos 28UL
+#define CANFD_CH_M_TTCAN_IE_PEDE_Msk 0x10000000UL
+#define CANFD_CH_M_TTCAN_IE_ARAE_Pos 29UL
+#define CANFD_CH_M_TTCAN_IE_ARAE_Msk 0x20000000UL
+/* CANFD_CH_M_TTCAN.ILS */
+#define CANFD_CH_M_TTCAN_ILS_RF0NL_Pos 0UL
+#define CANFD_CH_M_TTCAN_ILS_RF0NL_Msk 0x1UL
+#define CANFD_CH_M_TTCAN_ILS_RF0WL_Pos 1UL
+#define CANFD_CH_M_TTCAN_ILS_RF0WL_Msk 0x2UL
+#define CANFD_CH_M_TTCAN_ILS_RF0FL_Pos 2UL
+#define CANFD_CH_M_TTCAN_ILS_RF0FL_Msk 0x4UL
+#define CANFD_CH_M_TTCAN_ILS_RF0LL_Pos 3UL
+#define CANFD_CH_M_TTCAN_ILS_RF0LL_Msk 0x8UL
+#define CANFD_CH_M_TTCAN_ILS_RF1NL_Pos 4UL
+#define CANFD_CH_M_TTCAN_ILS_RF1NL_Msk 0x10UL
+#define CANFD_CH_M_TTCAN_ILS_RF1WL_Pos 5UL
+#define CANFD_CH_M_TTCAN_ILS_RF1WL_Msk 0x20UL
+#define CANFD_CH_M_TTCAN_ILS_RF1FL_Pos 6UL
+#define CANFD_CH_M_TTCAN_ILS_RF1FL_Msk 0x40UL
+#define CANFD_CH_M_TTCAN_ILS_RF1LL_Pos 7UL
+#define CANFD_CH_M_TTCAN_ILS_RF1LL_Msk 0x80UL
+#define CANFD_CH_M_TTCAN_ILS_HPML_Pos 8UL
+#define CANFD_CH_M_TTCAN_ILS_HPML_Msk 0x100UL
+#define CANFD_CH_M_TTCAN_ILS_TCL_Pos 9UL
+#define CANFD_CH_M_TTCAN_ILS_TCL_Msk 0x200UL
+#define CANFD_CH_M_TTCAN_ILS_TCFL_Pos 10UL
+#define CANFD_CH_M_TTCAN_ILS_TCFL_Msk 0x400UL
+#define CANFD_CH_M_TTCAN_ILS_TFEL_Pos 11UL
+#define CANFD_CH_M_TTCAN_ILS_TFEL_Msk 0x800UL
+#define CANFD_CH_M_TTCAN_ILS_TEFNL_Pos 12UL
+#define CANFD_CH_M_TTCAN_ILS_TEFNL_Msk 0x1000UL
+#define CANFD_CH_M_TTCAN_ILS_TEFWL_Pos 13UL
+#define CANFD_CH_M_TTCAN_ILS_TEFWL_Msk 0x2000UL
+#define CANFD_CH_M_TTCAN_ILS_TEFFL_Pos 14UL
+#define CANFD_CH_M_TTCAN_ILS_TEFFL_Msk 0x4000UL
+#define CANFD_CH_M_TTCAN_ILS_TEFLL_Pos 15UL
+#define CANFD_CH_M_TTCAN_ILS_TEFLL_Msk 0x8000UL
+#define CANFD_CH_M_TTCAN_ILS_TSWL_Pos 16UL
+#define CANFD_CH_M_TTCAN_ILS_TSWL_Msk 0x10000UL
+#define CANFD_CH_M_TTCAN_ILS_MRAFL_Pos 17UL
+#define CANFD_CH_M_TTCAN_ILS_MRAFL_Msk 0x20000UL
+#define CANFD_CH_M_TTCAN_ILS_TOOL_Pos 18UL
+#define CANFD_CH_M_TTCAN_ILS_TOOL_Msk 0x40000UL
+#define CANFD_CH_M_TTCAN_ILS_DRXL_Pos 19UL
+#define CANFD_CH_M_TTCAN_ILS_DRXL_Msk 0x80000UL
+#define CANFD_CH_M_TTCAN_ILS_BECL_Pos 20UL
+#define CANFD_CH_M_TTCAN_ILS_BECL_Msk 0x100000UL
+#define CANFD_CH_M_TTCAN_ILS_BEUL_Pos 21UL
+#define CANFD_CH_M_TTCAN_ILS_BEUL_Msk 0x200000UL
+#define CANFD_CH_M_TTCAN_ILS_ELOL_Pos 22UL
+#define CANFD_CH_M_TTCAN_ILS_ELOL_Msk 0x400000UL
+#define CANFD_CH_M_TTCAN_ILS_EPL_Pos 23UL
+#define CANFD_CH_M_TTCAN_ILS_EPL_Msk 0x800000UL
+#define CANFD_CH_M_TTCAN_ILS_EWL_Pos 24UL
+#define CANFD_CH_M_TTCAN_ILS_EWL_Msk 0x1000000UL
+#define CANFD_CH_M_TTCAN_ILS_BOL_Pos 25UL
+#define CANFD_CH_M_TTCAN_ILS_BOL_Msk 0x2000000UL
+#define CANFD_CH_M_TTCAN_ILS_WDIL_Pos 26UL
+#define CANFD_CH_M_TTCAN_ILS_WDIL_Msk 0x4000000UL
+#define CANFD_CH_M_TTCAN_ILS_PEAL_Pos 27UL
+#define CANFD_CH_M_TTCAN_ILS_PEAL_Msk 0x8000000UL
+#define CANFD_CH_M_TTCAN_ILS_PEDL_Pos 28UL
+#define CANFD_CH_M_TTCAN_ILS_PEDL_Msk 0x10000000UL
+#define CANFD_CH_M_TTCAN_ILS_ARAL_Pos 29UL
+#define CANFD_CH_M_TTCAN_ILS_ARAL_Msk 0x20000000UL
+/* CANFD_CH_M_TTCAN.ILE */
+#define CANFD_CH_M_TTCAN_ILE_EINT0_Pos 0UL
+#define CANFD_CH_M_TTCAN_ILE_EINT0_Msk 0x1UL
+#define CANFD_CH_M_TTCAN_ILE_EINT1_Pos 1UL
+#define CANFD_CH_M_TTCAN_ILE_EINT1_Msk 0x2UL
+/* CANFD_CH_M_TTCAN.GFC */
+#define CANFD_CH_M_TTCAN_GFC_RRFE_Pos 0UL
+#define CANFD_CH_M_TTCAN_GFC_RRFE_Msk 0x1UL
+#define CANFD_CH_M_TTCAN_GFC_RRFS_Pos 1UL
+#define CANFD_CH_M_TTCAN_GFC_RRFS_Msk 0x2UL
+#define CANFD_CH_M_TTCAN_GFC_ANFE_Pos 2UL
+#define CANFD_CH_M_TTCAN_GFC_ANFE_Msk 0xCUL
+#define CANFD_CH_M_TTCAN_GFC_ANFS_Pos 4UL
+#define CANFD_CH_M_TTCAN_GFC_ANFS_Msk 0x30UL
+/* CANFD_CH_M_TTCAN.SIDFC */
+#define CANFD_CH_M_TTCAN_SIDFC_FLSSA_Pos 2UL
+#define CANFD_CH_M_TTCAN_SIDFC_FLSSA_Msk 0xFFFCUL
+#define CANFD_CH_M_TTCAN_SIDFC_LSS_Pos 16UL
+#define CANFD_CH_M_TTCAN_SIDFC_LSS_Msk 0xFF0000UL
+/* CANFD_CH_M_TTCAN.XIDFC */
+#define CANFD_CH_M_TTCAN_XIDFC_FLESA_Pos 2UL
+#define CANFD_CH_M_TTCAN_XIDFC_FLESA_Msk 0xFFFCUL
+#define CANFD_CH_M_TTCAN_XIDFC_LSE_Pos 16UL
+#define CANFD_CH_M_TTCAN_XIDFC_LSE_Msk 0x7F0000UL
+/* CANFD_CH_M_TTCAN.XIDAM */
+#define CANFD_CH_M_TTCAN_XIDAM_EIDM_Pos 0UL
+#define CANFD_CH_M_TTCAN_XIDAM_EIDM_Msk 0x1FFFFFFFUL
+/* CANFD_CH_M_TTCAN.HPMS */
+#define CANFD_CH_M_TTCAN_HPMS_BIDX_Pos 0UL
+#define CANFD_CH_M_TTCAN_HPMS_BIDX_Msk 0x3FUL
+#define CANFD_CH_M_TTCAN_HPMS_MSI_Pos 6UL
+#define CANFD_CH_M_TTCAN_HPMS_MSI_Msk 0xC0UL
+#define CANFD_CH_M_TTCAN_HPMS_FIDX_Pos 8UL
+#define CANFD_CH_M_TTCAN_HPMS_FIDX_Msk 0x7F00UL
+#define CANFD_CH_M_TTCAN_HPMS_FLST_Pos 15UL
+#define CANFD_CH_M_TTCAN_HPMS_FLST_Msk 0x8000UL
+/* CANFD_CH_M_TTCAN.NDAT1 */
+#define CANFD_CH_M_TTCAN_NDAT1_ND_Pos 0UL
+#define CANFD_CH_M_TTCAN_NDAT1_ND_Msk 0xFFFFFFFFUL
+/* CANFD_CH_M_TTCAN.NDAT2 */
+#define CANFD_CH_M_TTCAN_NDAT2_ND_Pos 0UL
+#define CANFD_CH_M_TTCAN_NDAT2_ND_Msk 0xFFFFFFFFUL
+/* CANFD_CH_M_TTCAN.RXF0C */
+#define CANFD_CH_M_TTCAN_RXF0C_F0SA_Pos 2UL
+#define CANFD_CH_M_TTCAN_RXF0C_F0SA_Msk 0xFFFCUL
+#define CANFD_CH_M_TTCAN_RXF0C_F0S_Pos 16UL
+#define CANFD_CH_M_TTCAN_RXF0C_F0S_Msk 0x7F0000UL
+#define CANFD_CH_M_TTCAN_RXF0C_F0WM_Pos 24UL
+#define CANFD_CH_M_TTCAN_RXF0C_F0WM_Msk 0x7F000000UL
+#define CANFD_CH_M_TTCAN_RXF0C_F0OM_Pos 31UL
+#define CANFD_CH_M_TTCAN_RXF0C_F0OM_Msk 0x80000000UL
+/* CANFD_CH_M_TTCAN.RXF0S */
+#define CANFD_CH_M_TTCAN_RXF0S_F0FL_Pos 0UL
+#define CANFD_CH_M_TTCAN_RXF0S_F0FL_Msk 0x7FUL
+#define CANFD_CH_M_TTCAN_RXF0S_F0GI_Pos 8UL
+#define CANFD_CH_M_TTCAN_RXF0S_F0GI_Msk 0x3F00UL
+#define CANFD_CH_M_TTCAN_RXF0S_F0PI_Pos 16UL
+#define CANFD_CH_M_TTCAN_RXF0S_F0PI_Msk 0x3F0000UL
+#define CANFD_CH_M_TTCAN_RXF0S_F0F_Pos 24UL
+#define CANFD_CH_M_TTCAN_RXF0S_F0F_Msk 0x1000000UL
+#define CANFD_CH_M_TTCAN_RXF0S_RF0L_Pos 25UL
+#define CANFD_CH_M_TTCAN_RXF0S_RF0L_Msk 0x2000000UL
+/* CANFD_CH_M_TTCAN.RXF0A */
+#define CANFD_CH_M_TTCAN_RXF0A_F0AI_Pos 0UL
+#define CANFD_CH_M_TTCAN_RXF0A_F0AI_Msk 0x3FUL
+/* CANFD_CH_M_TTCAN.RXBC */
+#define CANFD_CH_M_TTCAN_RXBC_RBSA_Pos 2UL
+#define CANFD_CH_M_TTCAN_RXBC_RBSA_Msk 0xFFFCUL
+/* CANFD_CH_M_TTCAN.RXF1C */
+#define CANFD_CH_M_TTCAN_RXF1C_F1SA_Pos 2UL
+#define CANFD_CH_M_TTCAN_RXF1C_F1SA_Msk 0xFFFCUL
+#define CANFD_CH_M_TTCAN_RXF1C_F1S_Pos 16UL
+#define CANFD_CH_M_TTCAN_RXF1C_F1S_Msk 0x7F0000UL
+#define CANFD_CH_M_TTCAN_RXF1C_F1WM_Pos 24UL
+#define CANFD_CH_M_TTCAN_RXF1C_F1WM_Msk 0x7F000000UL
+#define CANFD_CH_M_TTCAN_RXF1C_F1OM_Pos 31UL
+#define CANFD_CH_M_TTCAN_RXF1C_F1OM_Msk 0x80000000UL
+/* CANFD_CH_M_TTCAN.RXF1S */
+#define CANFD_CH_M_TTCAN_RXF1S_F1FL_Pos 0UL
+#define CANFD_CH_M_TTCAN_RXF1S_F1FL_Msk 0x7FUL
+#define CANFD_CH_M_TTCAN_RXF1S_F1GI_Pos 8UL
+#define CANFD_CH_M_TTCAN_RXF1S_F1GI_Msk 0x3F00UL
+#define CANFD_CH_M_TTCAN_RXF1S_F1PI_Pos 16UL
+#define CANFD_CH_M_TTCAN_RXF1S_F1PI_Msk 0x3F0000UL
+#define CANFD_CH_M_TTCAN_RXF1S_F1F_Pos 24UL
+#define CANFD_CH_M_TTCAN_RXF1S_F1F_Msk 0x1000000UL
+#define CANFD_CH_M_TTCAN_RXF1S_RF1L_Pos 25UL
+#define CANFD_CH_M_TTCAN_RXF1S_RF1L_Msk 0x2000000UL
+#define CANFD_CH_M_TTCAN_RXF1S_DMS_Pos 30UL
+#define CANFD_CH_M_TTCAN_RXF1S_DMS_Msk 0xC0000000UL
+/* CANFD_CH_M_TTCAN.RXF1A */
+#define CANFD_CH_M_TTCAN_RXF1A_F1AI_Pos 0UL
+#define CANFD_CH_M_TTCAN_RXF1A_F1AI_Msk 0x3FUL
+/* CANFD_CH_M_TTCAN.RXESC */
+#define CANFD_CH_M_TTCAN_RXESC_F0DS_Pos 0UL
+#define CANFD_CH_M_TTCAN_RXESC_F0DS_Msk 0x7UL
+#define CANFD_CH_M_TTCAN_RXESC_F1DS_Pos 4UL
+#define CANFD_CH_M_TTCAN_RXESC_F1DS_Msk 0x70UL
+#define CANFD_CH_M_TTCAN_RXESC_RBDS_Pos 8UL
+#define CANFD_CH_M_TTCAN_RXESC_RBDS_Msk 0x700UL
+/* CANFD_CH_M_TTCAN.TXBC */
+#define CANFD_CH_M_TTCAN_TXBC_TBSA_Pos 2UL
+#define CANFD_CH_M_TTCAN_TXBC_TBSA_Msk 0xFFFCUL
+#define CANFD_CH_M_TTCAN_TXBC_NDTB_Pos 16UL
+#define CANFD_CH_M_TTCAN_TXBC_NDTB_Msk 0x3F0000UL
+#define CANFD_CH_M_TTCAN_TXBC_TFQS_Pos 24UL
+#define CANFD_CH_M_TTCAN_TXBC_TFQS_Msk 0x3F000000UL
+#define CANFD_CH_M_TTCAN_TXBC_TFQM_Pos 30UL
+#define CANFD_CH_M_TTCAN_TXBC_TFQM_Msk 0x40000000UL
+/* CANFD_CH_M_TTCAN.TXFQS */
+#define CANFD_CH_M_TTCAN_TXFQS_TFFL_Pos 0UL
+#define CANFD_CH_M_TTCAN_TXFQS_TFFL_Msk 0x3FUL
+#define CANFD_CH_M_TTCAN_TXFQS_TFGI_Pos 8UL
+#define CANFD_CH_M_TTCAN_TXFQS_TFGI_Msk 0x1F00UL
+#define CANFD_CH_M_TTCAN_TXFQS_TFQPI_Pos 16UL
+#define CANFD_CH_M_TTCAN_TXFQS_TFQPI_Msk 0x1F0000UL
+#define CANFD_CH_M_TTCAN_TXFQS_TFQF_Pos 21UL
+#define CANFD_CH_M_TTCAN_TXFQS_TFQF_Msk 0x200000UL
+/* CANFD_CH_M_TTCAN.TXESC */
+#define CANFD_CH_M_TTCAN_TXESC_TBDS_Pos 0UL
+#define CANFD_CH_M_TTCAN_TXESC_TBDS_Msk 0x7UL
+/* CANFD_CH_M_TTCAN.TXBRP */
+#define CANFD_CH_M_TTCAN_TXBRP_TRP_Pos 0UL
+#define CANFD_CH_M_TTCAN_TXBRP_TRP_Msk 0xFFFFFFFFUL
+/* CANFD_CH_M_TTCAN.TXBAR */
+#define CANFD_CH_M_TTCAN_TXBAR_AR_Pos 0UL
+#define CANFD_CH_M_TTCAN_TXBAR_AR_Msk 0xFFFFFFFFUL
+/* CANFD_CH_M_TTCAN.TXBCR */
+#define CANFD_CH_M_TTCAN_TXBCR_CR_Pos 0UL
+#define CANFD_CH_M_TTCAN_TXBCR_CR_Msk 0xFFFFFFFFUL
+/* CANFD_CH_M_TTCAN.TXBTO */
+#define CANFD_CH_M_TTCAN_TXBTO_TO_Pos 0UL
+#define CANFD_CH_M_TTCAN_TXBTO_TO_Msk 0xFFFFFFFFUL
+/* CANFD_CH_M_TTCAN.TXBCF */
+#define CANFD_CH_M_TTCAN_TXBCF_CF_Pos 0UL
+#define CANFD_CH_M_TTCAN_TXBCF_CF_Msk 0xFFFFFFFFUL
+/* CANFD_CH_M_TTCAN.TXBTIE */
+#define CANFD_CH_M_TTCAN_TXBTIE_TIE_Pos 0UL
+#define CANFD_CH_M_TTCAN_TXBTIE_TIE_Msk 0xFFFFFFFFUL
+/* CANFD_CH_M_TTCAN.TXBCIE */
+#define CANFD_CH_M_TTCAN_TXBCIE_CFIE_Pos 0UL
+#define CANFD_CH_M_TTCAN_TXBCIE_CFIE_Msk 0xFFFFFFFFUL
+/* CANFD_CH_M_TTCAN.TXEFC */
+#define CANFD_CH_M_TTCAN_TXEFC_EFSA_Pos 2UL
+#define CANFD_CH_M_TTCAN_TXEFC_EFSA_Msk 0xFFFCUL
+#define CANFD_CH_M_TTCAN_TXEFC_EFS_Pos 16UL
+#define CANFD_CH_M_TTCAN_TXEFC_EFS_Msk 0x3F0000UL
+#define CANFD_CH_M_TTCAN_TXEFC_EFWM_Pos 24UL
+#define CANFD_CH_M_TTCAN_TXEFC_EFWM_Msk 0x3F000000UL
+/* CANFD_CH_M_TTCAN.TXEFS */
+#define CANFD_CH_M_TTCAN_TXEFS_EFFL_Pos 0UL
+#define CANFD_CH_M_TTCAN_TXEFS_EFFL_Msk 0x3FUL
+#define CANFD_CH_M_TTCAN_TXEFS_EFGI_Pos 8UL
+#define CANFD_CH_M_TTCAN_TXEFS_EFGI_Msk 0x1F00UL
+#define CANFD_CH_M_TTCAN_TXEFS_EFPI_Pos 16UL
+#define CANFD_CH_M_TTCAN_TXEFS_EFPI_Msk 0x1F0000UL
+#define CANFD_CH_M_TTCAN_TXEFS_EFF_Pos 24UL
+#define CANFD_CH_M_TTCAN_TXEFS_EFF_Msk 0x1000000UL
+#define CANFD_CH_M_TTCAN_TXEFS_TEFL_Pos 25UL
+#define CANFD_CH_M_TTCAN_TXEFS_TEFL_Msk 0x2000000UL
+/* CANFD_CH_M_TTCAN.TXEFA */
+#define CANFD_CH_M_TTCAN_TXEFA_EFAI_Pos 0UL
+#define CANFD_CH_M_TTCAN_TXEFA_EFAI_Msk 0x1FUL
+/* CANFD_CH_M_TTCAN.TTTMC */
+#define CANFD_CH_M_TTCAN_TTTMC_TMSA_Pos 2UL
+#define CANFD_CH_M_TTCAN_TTTMC_TMSA_Msk 0xFFFCUL
+#define CANFD_CH_M_TTCAN_TTTMC_TME_Pos 16UL
+#define CANFD_CH_M_TTCAN_TTTMC_TME_Msk 0x7F0000UL
+/* CANFD_CH_M_TTCAN.TTRMC */
+#define CANFD_CH_M_TTCAN_TTRMC_RID_Pos 0UL
+#define CANFD_CH_M_TTCAN_TTRMC_RID_Msk 0x1FFFFFFFUL
+#define CANFD_CH_M_TTCAN_TTRMC_XTD_Pos 30UL
+#define CANFD_CH_M_TTCAN_TTRMC_XTD_Msk 0x40000000UL
+#define CANFD_CH_M_TTCAN_TTRMC_RMPS_Pos 31UL
+#define CANFD_CH_M_TTCAN_TTRMC_RMPS_Msk 0x80000000UL
+/* CANFD_CH_M_TTCAN.TTOCF */
+#define CANFD_CH_M_TTCAN_TTOCF_OM_Pos 0UL
+#define CANFD_CH_M_TTCAN_TTOCF_OM_Msk 0x3UL
+#define CANFD_CH_M_TTCAN_TTOCF_GEN_Pos 3UL
+#define CANFD_CH_M_TTCAN_TTOCF_GEN_Msk 0x8UL
+#define CANFD_CH_M_TTCAN_TTOCF_TM_Pos 4UL
+#define CANFD_CH_M_TTCAN_TTOCF_TM_Msk 0x10UL
+#define CANFD_CH_M_TTCAN_TTOCF_LDSDL_Pos 5UL
+#define CANFD_CH_M_TTCAN_TTOCF_LDSDL_Msk 0xE0UL
+#define CANFD_CH_M_TTCAN_TTOCF_IRTO_Pos 8UL
+#define CANFD_CH_M_TTCAN_TTOCF_IRTO_Msk 0x7F00UL
+#define CANFD_CH_M_TTCAN_TTOCF_EECS_Pos 15UL
+#define CANFD_CH_M_TTCAN_TTOCF_EECS_Msk 0x8000UL
+#define CANFD_CH_M_TTCAN_TTOCF_AWL_Pos 16UL
+#define CANFD_CH_M_TTCAN_TTOCF_AWL_Msk 0xFF0000UL
+#define CANFD_CH_M_TTCAN_TTOCF_EGTF_Pos 24UL
+#define CANFD_CH_M_TTCAN_TTOCF_EGTF_Msk 0x1000000UL
+#define CANFD_CH_M_TTCAN_TTOCF_ECC_Pos 25UL
+#define CANFD_CH_M_TTCAN_TTOCF_ECC_Msk 0x2000000UL
+#define CANFD_CH_M_TTCAN_TTOCF_EVTP_Pos 26UL
+#define CANFD_CH_M_TTCAN_TTOCF_EVTP_Msk 0x4000000UL
+/* CANFD_CH_M_TTCAN.TTMLM */
+#define CANFD_CH_M_TTCAN_TTMLM_CCM_Pos 0UL
+#define CANFD_CH_M_TTCAN_TTMLM_CCM_Msk 0x3FUL
+#define CANFD_CH_M_TTCAN_TTMLM_CSS_Pos 6UL
+#define CANFD_CH_M_TTCAN_TTMLM_CSS_Msk 0xC0UL
+#define CANFD_CH_M_TTCAN_TTMLM_TXEW_Pos 8UL
+#define CANFD_CH_M_TTCAN_TTMLM_TXEW_Msk 0xF00UL
+#define CANFD_CH_M_TTCAN_TTMLM_ENTT_Pos 16UL
+#define CANFD_CH_M_TTCAN_TTMLM_ENTT_Msk 0xFFF0000UL
+/* CANFD_CH_M_TTCAN.TURCF */
+#define CANFD_CH_M_TTCAN_TURCF_NCL_Pos 0UL
+#define CANFD_CH_M_TTCAN_TURCF_NCL_Msk 0xFFFFUL
+#define CANFD_CH_M_TTCAN_TURCF_DC_Pos 16UL
+#define CANFD_CH_M_TTCAN_TURCF_DC_Msk 0x3FFF0000UL
+#define CANFD_CH_M_TTCAN_TURCF_ELT_Pos 31UL
+#define CANFD_CH_M_TTCAN_TURCF_ELT_Msk 0x80000000UL
+/* CANFD_CH_M_TTCAN.TTOCN */
+#define CANFD_CH_M_TTCAN_TTOCN_SGT_Pos 0UL
+#define CANFD_CH_M_TTCAN_TTOCN_SGT_Msk 0x1UL
+#define CANFD_CH_M_TTCAN_TTOCN_ECS_Pos 1UL
+#define CANFD_CH_M_TTCAN_TTOCN_ECS_Msk 0x2UL
+#define CANFD_CH_M_TTCAN_TTOCN_SWP_Pos 2UL
+#define CANFD_CH_M_TTCAN_TTOCN_SWP_Msk 0x4UL
+#define CANFD_CH_M_TTCAN_TTOCN_SWS_Pos 3UL
+#define CANFD_CH_M_TTCAN_TTOCN_SWS_Msk 0x18UL
+#define CANFD_CH_M_TTCAN_TTOCN_RTIE_Pos 5UL
+#define CANFD_CH_M_TTCAN_TTOCN_RTIE_Msk 0x20UL
+#define CANFD_CH_M_TTCAN_TTOCN_TMC_Pos 6UL
+#define CANFD_CH_M_TTCAN_TTOCN_TMC_Msk 0xC0UL
+#define CANFD_CH_M_TTCAN_TTOCN_TTIE_Pos 8UL
+#define CANFD_CH_M_TTCAN_TTOCN_TTIE_Msk 0x100UL
+#define CANFD_CH_M_TTCAN_TTOCN_GCS_Pos 9UL
+#define CANFD_CH_M_TTCAN_TTOCN_GCS_Msk 0x200UL
+#define CANFD_CH_M_TTCAN_TTOCN_FGP_Pos 10UL
+#define CANFD_CH_M_TTCAN_TTOCN_FGP_Msk 0x400UL
+#define CANFD_CH_M_TTCAN_TTOCN_TMG_Pos 11UL
+#define CANFD_CH_M_TTCAN_TTOCN_TMG_Msk 0x800UL
+#define CANFD_CH_M_TTCAN_TTOCN_NIG_Pos 12UL
+#define CANFD_CH_M_TTCAN_TTOCN_NIG_Msk 0x1000UL
+#define CANFD_CH_M_TTCAN_TTOCN_ESCN_Pos 13UL
+#define CANFD_CH_M_TTCAN_TTOCN_ESCN_Msk 0x2000UL
+#define CANFD_CH_M_TTCAN_TTOCN_LCKC_Pos 15UL
+#define CANFD_CH_M_TTCAN_TTOCN_LCKC_Msk 0x8000UL
+/* CANFD_CH_M_TTCAN.TTGTP */
+#define CANFD_CH_M_TTCAN_TTGTP_TP_Pos 0UL
+#define CANFD_CH_M_TTCAN_TTGTP_TP_Msk 0xFFFFUL
+#define CANFD_CH_M_TTCAN_TTGTP_CTP_Pos 16UL
+#define CANFD_CH_M_TTCAN_TTGTP_CTP_Msk 0xFFFF0000UL
+/* CANFD_CH_M_TTCAN.TTTMK */
+#define CANFD_CH_M_TTCAN_TTTMK_TM__Pos 0UL
+#define CANFD_CH_M_TTCAN_TTTMK_TM__Msk 0xFFFFUL
+#define CANFD_CH_M_TTCAN_TTTMK_TICC_Pos 16UL
+#define CANFD_CH_M_TTCAN_TTTMK_TICC_Msk 0x7F0000UL
+#define CANFD_CH_M_TTCAN_TTTMK_LCKM_Pos 31UL
+#define CANFD_CH_M_TTCAN_TTTMK_LCKM_Msk 0x80000000UL
+/* CANFD_CH_M_TTCAN.TTIR */
+#define CANFD_CH_M_TTCAN_TTIR_SBC_Pos 0UL
+#define CANFD_CH_M_TTCAN_TTIR_SBC_Msk 0x1UL
+#define CANFD_CH_M_TTCAN_TTIR_SMC_Pos 1UL
+#define CANFD_CH_M_TTCAN_TTIR_SMC_Msk 0x2UL
+#define CANFD_CH_M_TTCAN_TTIR_CSM__Pos 2UL
+#define CANFD_CH_M_TTCAN_TTIR_CSM__Msk 0x4UL
+#define CANFD_CH_M_TTCAN_TTIR_SOG_Pos 3UL
+#define CANFD_CH_M_TTCAN_TTIR_SOG_Msk 0x8UL
+#define CANFD_CH_M_TTCAN_TTIR_RTMI_Pos 4UL
+#define CANFD_CH_M_TTCAN_TTIR_RTMI_Msk 0x10UL
+#define CANFD_CH_M_TTCAN_TTIR_TTMI_Pos 5UL
+#define CANFD_CH_M_TTCAN_TTIR_TTMI_Msk 0x20UL
+#define CANFD_CH_M_TTCAN_TTIR_SWE_Pos 6UL
+#define CANFD_CH_M_TTCAN_TTIR_SWE_Msk 0x40UL
+#define CANFD_CH_M_TTCAN_TTIR_GTW_Pos 7UL
+#define CANFD_CH_M_TTCAN_TTIR_GTW_Msk 0x80UL
+#define CANFD_CH_M_TTCAN_TTIR_GTD_Pos 8UL
+#define CANFD_CH_M_TTCAN_TTIR_GTD_Msk 0x100UL
+#define CANFD_CH_M_TTCAN_TTIR_GTE_Pos 9UL
+#define CANFD_CH_M_TTCAN_TTIR_GTE_Msk 0x200UL
+#define CANFD_CH_M_TTCAN_TTIR_TXU_Pos 10UL
+#define CANFD_CH_M_TTCAN_TTIR_TXU_Msk 0x400UL
+#define CANFD_CH_M_TTCAN_TTIR_TXO_Pos 11UL
+#define CANFD_CH_M_TTCAN_TTIR_TXO_Msk 0x800UL
+#define CANFD_CH_M_TTCAN_TTIR_SE1_Pos 12UL
+#define CANFD_CH_M_TTCAN_TTIR_SE1_Msk 0x1000UL
+#define CANFD_CH_M_TTCAN_TTIR_SE2_Pos 13UL
+#define CANFD_CH_M_TTCAN_TTIR_SE2_Msk 0x2000UL
+#define CANFD_CH_M_TTCAN_TTIR_ELC_Pos 14UL
+#define CANFD_CH_M_TTCAN_TTIR_ELC_Msk 0x4000UL
+#define CANFD_CH_M_TTCAN_TTIR_IWT_Pos 15UL
+#define CANFD_CH_M_TTCAN_TTIR_IWT_Msk 0x8000UL
+#define CANFD_CH_M_TTCAN_TTIR_WT_Pos 16UL
+#define CANFD_CH_M_TTCAN_TTIR_WT_Msk 0x10000UL
+#define CANFD_CH_M_TTCAN_TTIR_AW_Pos 17UL
+#define CANFD_CH_M_TTCAN_TTIR_AW_Msk 0x20000UL
+#define CANFD_CH_M_TTCAN_TTIR_CER_Pos 18UL
+#define CANFD_CH_M_TTCAN_TTIR_CER_Msk 0x40000UL
+/* CANFD_CH_M_TTCAN.TTIE */
+#define CANFD_CH_M_TTCAN_TTIE_SBCE_Pos 0UL
+#define CANFD_CH_M_TTCAN_TTIE_SBCE_Msk 0x1UL
+#define CANFD_CH_M_TTCAN_TTIE_SMCE_Pos 1UL
+#define CANFD_CH_M_TTCAN_TTIE_SMCE_Msk 0x2UL
+#define CANFD_CH_M_TTCAN_TTIE_CSME_Pos 2UL
+#define CANFD_CH_M_TTCAN_TTIE_CSME_Msk 0x4UL
+#define CANFD_CH_M_TTCAN_TTIE_SOGE_Pos 3UL
+#define CANFD_CH_M_TTCAN_TTIE_SOGE_Msk 0x8UL
+#define CANFD_CH_M_TTCAN_TTIE_RTMIE_Pos 4UL
+#define CANFD_CH_M_TTCAN_TTIE_RTMIE_Msk 0x10UL
+#define CANFD_CH_M_TTCAN_TTIE_TTMIE_Pos 5UL
+#define CANFD_CH_M_TTCAN_TTIE_TTMIE_Msk 0x20UL
+#define CANFD_CH_M_TTCAN_TTIE_SWEE_Pos 6UL
+#define CANFD_CH_M_TTCAN_TTIE_SWEE_Msk 0x40UL
+#define CANFD_CH_M_TTCAN_TTIE_GTWE_Pos 7UL
+#define CANFD_CH_M_TTCAN_TTIE_GTWE_Msk 0x80UL
+#define CANFD_CH_M_TTCAN_TTIE_GTDE_Pos 8UL
+#define CANFD_CH_M_TTCAN_TTIE_GTDE_Msk 0x100UL
+#define CANFD_CH_M_TTCAN_TTIE_GTEE_Pos 9UL
+#define CANFD_CH_M_TTCAN_TTIE_GTEE_Msk 0x200UL
+#define CANFD_CH_M_TTCAN_TTIE_TXUE_Pos 10UL
+#define CANFD_CH_M_TTCAN_TTIE_TXUE_Msk 0x400UL
+#define CANFD_CH_M_TTCAN_TTIE_TXOE_Pos 11UL
+#define CANFD_CH_M_TTCAN_TTIE_TXOE_Msk 0x800UL
+#define CANFD_CH_M_TTCAN_TTIE_SE1E_Pos 12UL
+#define CANFD_CH_M_TTCAN_TTIE_SE1E_Msk 0x1000UL
+#define CANFD_CH_M_TTCAN_TTIE_SE2E_Pos 13UL
+#define CANFD_CH_M_TTCAN_TTIE_SE2E_Msk 0x2000UL
+#define CANFD_CH_M_TTCAN_TTIE_ELCE_Pos 14UL
+#define CANFD_CH_M_TTCAN_TTIE_ELCE_Msk 0x4000UL
+#define CANFD_CH_M_TTCAN_TTIE_IWTE_Pos 15UL
+#define CANFD_CH_M_TTCAN_TTIE_IWTE_Msk 0x8000UL
+#define CANFD_CH_M_TTCAN_TTIE_WTE_Pos 16UL
+#define CANFD_CH_M_TTCAN_TTIE_WTE_Msk 0x10000UL
+#define CANFD_CH_M_TTCAN_TTIE_AWE__Pos 17UL
+#define CANFD_CH_M_TTCAN_TTIE_AWE__Msk 0x20000UL
+#define CANFD_CH_M_TTCAN_TTIE_CERE_Pos 18UL
+#define CANFD_CH_M_TTCAN_TTIE_CERE_Msk 0x40000UL
+/* CANFD_CH_M_TTCAN.TTILS */
+#define CANFD_CH_M_TTCAN_TTILS_SBCL_Pos 0UL
+#define CANFD_CH_M_TTCAN_TTILS_SBCL_Msk 0x1UL
+#define CANFD_CH_M_TTCAN_TTILS_SMCL_Pos 1UL
+#define CANFD_CH_M_TTCAN_TTILS_SMCL_Msk 0x2UL
+#define CANFD_CH_M_TTCAN_TTILS_CSML_Pos 2UL
+#define CANFD_CH_M_TTCAN_TTILS_CSML_Msk 0x4UL
+#define CANFD_CH_M_TTCAN_TTILS_SOGL_Pos 3UL
+#define CANFD_CH_M_TTCAN_TTILS_SOGL_Msk 0x8UL
+#define CANFD_CH_M_TTCAN_TTILS_RTMIL_Pos 4UL
+#define CANFD_CH_M_TTCAN_TTILS_RTMIL_Msk 0x10UL
+#define CANFD_CH_M_TTCAN_TTILS_TTMIL_Pos 5UL
+#define CANFD_CH_M_TTCAN_TTILS_TTMIL_Msk 0x20UL
+#define CANFD_CH_M_TTCAN_TTILS_SWEL_Pos 6UL
+#define CANFD_CH_M_TTCAN_TTILS_SWEL_Msk 0x40UL
+#define CANFD_CH_M_TTCAN_TTILS_GTWL_Pos 7UL
+#define CANFD_CH_M_TTCAN_TTILS_GTWL_Msk 0x80UL
+#define CANFD_CH_M_TTCAN_TTILS_GTDL_Pos 8UL
+#define CANFD_CH_M_TTCAN_TTILS_GTDL_Msk 0x100UL
+#define CANFD_CH_M_TTCAN_TTILS_GTEL_Pos 9UL
+#define CANFD_CH_M_TTCAN_TTILS_GTEL_Msk 0x200UL
+#define CANFD_CH_M_TTCAN_TTILS_TXUL_Pos 10UL
+#define CANFD_CH_M_TTCAN_TTILS_TXUL_Msk 0x400UL
+#define CANFD_CH_M_TTCAN_TTILS_TXOL_Pos 11UL
+#define CANFD_CH_M_TTCAN_TTILS_TXOL_Msk 0x800UL
+#define CANFD_CH_M_TTCAN_TTILS_SE1L_Pos 12UL
+#define CANFD_CH_M_TTCAN_TTILS_SE1L_Msk 0x1000UL
+#define CANFD_CH_M_TTCAN_TTILS_SE2L_Pos 13UL
+#define CANFD_CH_M_TTCAN_TTILS_SE2L_Msk 0x2000UL
+#define CANFD_CH_M_TTCAN_TTILS_ELCL_Pos 14UL
+#define CANFD_CH_M_TTCAN_TTILS_ELCL_Msk 0x4000UL
+#define CANFD_CH_M_TTCAN_TTILS_IWTL_Pos 15UL
+#define CANFD_CH_M_TTCAN_TTILS_IWTL_Msk 0x8000UL
+#define CANFD_CH_M_TTCAN_TTILS_WTL_Pos 16UL
+#define CANFD_CH_M_TTCAN_TTILS_WTL_Msk 0x10000UL
+#define CANFD_CH_M_TTCAN_TTILS_AWL__Pos 17UL
+#define CANFD_CH_M_TTCAN_TTILS_AWL__Msk 0x20000UL
+#define CANFD_CH_M_TTCAN_TTILS_CERL_Pos 18UL
+#define CANFD_CH_M_TTCAN_TTILS_CERL_Msk 0x40000UL
+/* CANFD_CH_M_TTCAN.TTOST */
+#define CANFD_CH_M_TTCAN_TTOST_EL_Pos 0UL
+#define CANFD_CH_M_TTCAN_TTOST_EL_Msk 0x3UL
+#define CANFD_CH_M_TTCAN_TTOST_MS_Pos 2UL
+#define CANFD_CH_M_TTCAN_TTOST_MS_Msk 0xCUL
+#define CANFD_CH_M_TTCAN_TTOST_SYS_Pos 4UL
+#define CANFD_CH_M_TTCAN_TTOST_SYS_Msk 0x30UL
+#define CANFD_CH_M_TTCAN_TTOST_QGTP_Pos 6UL
+#define CANFD_CH_M_TTCAN_TTOST_QGTP_Msk 0x40UL
+#define CANFD_CH_M_TTCAN_TTOST_QCS_Pos 7UL
+#define CANFD_CH_M_TTCAN_TTOST_QCS_Msk 0x80UL
+#define CANFD_CH_M_TTCAN_TTOST_RTO_Pos 8UL
+#define CANFD_CH_M_TTCAN_TTOST_RTO_Msk 0xFF00UL
+#define CANFD_CH_M_TTCAN_TTOST_WGTD_Pos 22UL
+#define CANFD_CH_M_TTCAN_TTOST_WGTD_Msk 0x400000UL
+#define CANFD_CH_M_TTCAN_TTOST_GFI_Pos 23UL
+#define CANFD_CH_M_TTCAN_TTOST_GFI_Msk 0x800000UL
+#define CANFD_CH_M_TTCAN_TTOST_TMP_Pos 24UL
+#define CANFD_CH_M_TTCAN_TTOST_TMP_Msk 0x7000000UL
+#define CANFD_CH_M_TTCAN_TTOST_GSI_Pos 27UL
+#define CANFD_CH_M_TTCAN_TTOST_GSI_Msk 0x8000000UL
+#define CANFD_CH_M_TTCAN_TTOST_WFE_Pos 28UL
+#define CANFD_CH_M_TTCAN_TTOST_WFE_Msk 0x10000000UL
+#define CANFD_CH_M_TTCAN_TTOST_AWE_Pos 29UL
+#define CANFD_CH_M_TTCAN_TTOST_AWE_Msk 0x20000000UL
+#define CANFD_CH_M_TTCAN_TTOST_WECS_Pos 30UL
+#define CANFD_CH_M_TTCAN_TTOST_WECS_Msk 0x40000000UL
+#define CANFD_CH_M_TTCAN_TTOST_SPL_Pos 31UL
+#define CANFD_CH_M_TTCAN_TTOST_SPL_Msk 0x80000000UL
+/* CANFD_CH_M_TTCAN.TURNA */
+#define CANFD_CH_M_TTCAN_TURNA_NAV_Pos 0UL
+#define CANFD_CH_M_TTCAN_TURNA_NAV_Msk 0x3FFFFUL
+/* CANFD_CH_M_TTCAN.TTLGT */
+#define CANFD_CH_M_TTCAN_TTLGT_LT_Pos 0UL
+#define CANFD_CH_M_TTCAN_TTLGT_LT_Msk 0xFFFFUL
+#define CANFD_CH_M_TTCAN_TTLGT_GT_Pos 16UL
+#define CANFD_CH_M_TTCAN_TTLGT_GT_Msk 0xFFFF0000UL
+/* CANFD_CH_M_TTCAN.TTCTC */
+#define CANFD_CH_M_TTCAN_TTCTC_CT_Pos 0UL
+#define CANFD_CH_M_TTCAN_TTCTC_CT_Msk 0xFFFFUL
+#define CANFD_CH_M_TTCAN_TTCTC_CC_Pos 16UL
+#define CANFD_CH_M_TTCAN_TTCTC_CC_Msk 0x3F0000UL
+/* CANFD_CH_M_TTCAN.TTCPT */
+#define CANFD_CH_M_TTCAN_TTCPT_CCV_Pos 0UL
+#define CANFD_CH_M_TTCAN_TTCPT_CCV_Msk 0x3FUL
+#define CANFD_CH_M_TTCAN_TTCPT_SWV_Pos 16UL
+#define CANFD_CH_M_TTCAN_TTCPT_SWV_Msk 0xFFFF0000UL
+/* CANFD_CH_M_TTCAN.TTCSM */
+#define CANFD_CH_M_TTCAN_TTCSM_CSM_Pos 0UL
+#define CANFD_CH_M_TTCAN_TTCSM_CSM_Msk 0xFFFFUL
+
+
+/* CANFD_CH.RXFTOP_CTL */
+#define CANFD_CH_RXFTOP_CTL_F0TPE_Pos 0UL
+#define CANFD_CH_RXFTOP_CTL_F0TPE_Msk 0x1UL
+#define CANFD_CH_RXFTOP_CTL_F1TPE_Pos 1UL
+#define CANFD_CH_RXFTOP_CTL_F1TPE_Msk 0x2UL
+/* CANFD_CH.RXFTOP0_STAT */
+#define CANFD_CH_RXFTOP0_STAT_F0TA_Pos 0UL
+#define CANFD_CH_RXFTOP0_STAT_F0TA_Msk 0xFFFFUL
+/* CANFD_CH.RXFTOP0_DATA */
+#define CANFD_CH_RXFTOP0_DATA_F0TD_Pos 0UL
+#define CANFD_CH_RXFTOP0_DATA_F0TD_Msk 0xFFFFFFFFUL
+/* CANFD_CH.RXFTOP1_STAT */
+#define CANFD_CH_RXFTOP1_STAT_F1TA_Pos 0UL
+#define CANFD_CH_RXFTOP1_STAT_F1TA_Msk 0xFFFFUL
+/* CANFD_CH.RXFTOP1_DATA */
+#define CANFD_CH_RXFTOP1_DATA_F1TD_Pos 0UL
+#define CANFD_CH_RXFTOP1_DATA_F1TD_Msk 0xFFFFFFFFUL
+
+
+/* CANFD.CTL */
+#define CANFD_CTL_STOP_REQ_Pos 0UL
+#define CANFD_CTL_STOP_REQ_Msk 0xFFUL
+#define CANFD_CTL_MRAM_OFF_Pos 31UL
+#define CANFD_CTL_MRAM_OFF_Msk 0x80000000UL
+/* CANFD.STATUS */
+#define CANFD_STATUS_STOP_ACK_Pos 0UL
+#define CANFD_STATUS_STOP_ACK_Msk 0xFFUL
+/* CANFD.INTR0_CAUSE */
+#define CANFD_INTR0_CAUSE_INT0_Pos 0UL
+#define CANFD_INTR0_CAUSE_INT0_Msk 0xFFUL
+/* CANFD.INTR1_CAUSE */
+#define CANFD_INTR1_CAUSE_INT1_Pos 0UL
+#define CANFD_INTR1_CAUSE_INT1_Msk 0xFFUL
+/* CANFD.TS_CTL */
+#define CANFD_TS_CTL_PRESCALE_Pos 0UL
+#define CANFD_TS_CTL_PRESCALE_Msk 0xFFFFUL
+#define CANFD_TS_CTL_ENABLED_Pos 31UL
+#define CANFD_TS_CTL_ENABLED_Msk 0x80000000UL
+/* CANFD.TS_CNT */
+#define CANFD_TS_CNT_VALUE_Pos 0UL
+#define CANFD_TS_CNT_VALUE_Msk 0xFFFFUL
+/* CANFD.ECC_CTL */
+#define CANFD_ECC_CTL_ECC_EN_Pos 16UL
+#define CANFD_ECC_CTL_ECC_EN_Msk 0x10000UL
+/* CANFD.ECC_ERR_INJ */
+#define CANFD_ECC_ERR_INJ_ERR_ADDR_Pos 2UL
+#define CANFD_ECC_ERR_INJ_ERR_ADDR_Msk 0xFFFCUL
+#define CANFD_ECC_ERR_INJ_ERR_EN_Pos 20UL
+#define CANFD_ECC_ERR_INJ_ERR_EN_Msk 0x100000UL
+#define CANFD_ECC_ERR_INJ_ERR_PAR_Pos 24UL
+#define CANFD_ECC_ERR_INJ_ERR_PAR_Msk 0x7F000000UL
+
+
+#endif /* _CYIP_CANFD_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_cpuss.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_cpuss.h
new file mode 100644
index 0000000000..07e5d7c5ec
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_cpuss.h
@@ -0,0 +1,356 @@
+/***************************************************************************//**
+* \file cyip_cpuss.h
+*
+* \brief
+* CPUSS IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_CPUSS_H_
+#define _CYIP_CPUSS_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* CPUSS
+*******************************************************************************/
+
+#define CPUSS_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief CPU subsystem (CPUSS) (CPUSS)
+ */
+typedef struct {
+ __IOM uint32_t CM0_CTL; /*!< 0x00000000 CM0+ control */
+ __IM uint32_t RESERVED;
+ __IM uint32_t CM0_STATUS; /*!< 0x00000008 CM0+ status */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t CM0_CLOCK_CTL; /*!< 0x00000010 CM0+ clock control */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t CM0_INT_CTL0; /*!< 0x00000020 CM0+ interrupt control 0 */
+ __IOM uint32_t CM0_INT_CTL1; /*!< 0x00000024 CM0+ interrupt control 1 */
+ __IOM uint32_t CM0_INT_CTL2; /*!< 0x00000028 CM0+ interrupt control 2 */
+ __IOM uint32_t CM0_INT_CTL3; /*!< 0x0000002C CM0+ interrupt control 3 */
+ __IOM uint32_t CM0_INT_CTL4; /*!< 0x00000030 CM0+ interrupt control 4 */
+ __IOM uint32_t CM0_INT_CTL5; /*!< 0x00000034 CM0+ interrupt control 5 */
+ __IOM uint32_t CM0_INT_CTL6; /*!< 0x00000038 CM0+ interrupt control 6 */
+ __IOM uint32_t CM0_INT_CTL7; /*!< 0x0000003C CM0+ interrupt control 7 */
+ __IM uint32_t RESERVED3[16];
+ __IOM uint32_t CM4_PWR_CTL; /*!< 0x00000080 CM4 power control */
+ __IOM uint32_t CM4_PWR_DELAY_CTL; /*!< 0x00000084 CM4 power control */
+ __IM uint32_t CM4_STATUS; /*!< 0x00000088 CM4 status */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t CM4_CLOCK_CTL; /*!< 0x00000090 CM4 clock control */
+ __IM uint32_t RESERVED5[3];
+ __IOM uint32_t CM4_NMI_CTL; /*!< 0x000000A0 CM4 NMI control */
+ __IM uint32_t RESERVED6[23];
+ __IOM uint32_t RAM0_CTL0; /*!< 0x00000100 RAM 0 control 0 */
+ __IM uint32_t RESERVED7[15];
+ __IOM uint32_t RAM0_PWR_MACRO_CTL[16]; /*!< 0x00000140 RAM 0 power control */
+ __IOM uint32_t RAM1_CTL0; /*!< 0x00000180 RAM 1 control 0 */
+ __IM uint32_t RESERVED8[3];
+ __IOM uint32_t RAM1_PWR_CTL; /*!< 0x00000190 RAM1 power control */
+ __IM uint32_t RESERVED9[3];
+ __IOM uint32_t RAM2_CTL0; /*!< 0x000001A0 RAM 2 control 0 */
+ __IM uint32_t RESERVED10[3];
+ __IOM uint32_t RAM2_PWR_CTL; /*!< 0x000001B0 RAM2 power control */
+ __IM uint32_t RESERVED11[3];
+ __IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x000001C0 Power up delay used for all SRAM power domains */
+ __IM uint32_t RESERVED12[3];
+ __IOM uint32_t ROM_CTL; /*!< 0x000001D0 ROM control */
+ __IM uint32_t RESERVED13[7];
+ __IOM uint32_t UDB_PWR_CTL; /*!< 0x000001F0 UDB power control */
+ __IOM uint32_t UDB_PWR_DELAY_CTL; /*!< 0x000001F4 UDB power control */
+ __IM uint32_t RESERVED14[4];
+ __IM uint32_t DP_STATUS; /*!< 0x00000208 Debug port status */
+ __IM uint32_t RESERVED15[5];
+ __IOM uint32_t BUFF_CTL; /*!< 0x00000220 Buffer control */
+ __IM uint32_t RESERVED16[3];
+ __IOM uint32_t DDFT_CTL; /*!< 0x00000230 DDFT control */
+ __IM uint32_t RESERVED17[3];
+ __IOM uint32_t SYSTICK_CTL; /*!< 0x00000240 SysTick timer control */
+ __IM uint32_t RESERVED18[27];
+ __IOM uint32_t CM0_VECTOR_TABLE_BASE; /*!< 0x000002B0 CM0+ vector table base */
+ __IM uint32_t RESERVED19[3];
+ __IOM uint32_t CM4_VECTOR_TABLE_BASE; /*!< 0x000002C0 CM4 vector table base */
+ __IM uint32_t RESERVED20[23];
+ __IOM uint32_t CM0_PC0_HANDLER; /*!< 0x00000320 CM0+ protection context 0 handler */
+ __IM uint32_t RESERVED21[55];
+ __IM uint32_t IDENTITY; /*!< 0x00000400 Identity */
+ __IM uint32_t RESERVED22[63];
+ __IOM uint32_t PROTECTION; /*!< 0x00000500 Protection status */
+ __IM uint32_t RESERVED23[7];
+ __IOM uint32_t CM0_NMI_CTL; /*!< 0x00000520 CM0+ NMI control */
+ __IM uint32_t RESERVED24[7];
+ __IOM uint32_t AP_CTL; /*!< 0x00000540 Access port control */
+ __IM uint32_t RESERVED25[23];
+ __IM uint32_t MBIST_STAT; /*!< 0x000005A0 Memory BIST status */
+ __IM uint32_t RESERVED26[14999];
+ __IOM uint32_t TRIM_ROM_CTL; /*!< 0x0000F000 ROM trim control */
+ __IOM uint32_t TRIM_RAM_CTL; /*!< 0x0000F004 RAM trim control */
+} CPUSS_V1_Type; /*!< Size = 61448 (0xF008) */
+
+
+/* CPUSS.CM0_CTL */
+#define CPUSS_CM0_CTL_SLV_STALL_Pos 0UL
+#define CPUSS_CM0_CTL_SLV_STALL_Msk 0x1UL
+#define CPUSS_CM0_CTL_ENABLED_Pos 1UL
+#define CPUSS_CM0_CTL_ENABLED_Msk 0x2UL
+#define CPUSS_CM0_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_CM0_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.CM0_STATUS */
+#define CPUSS_CM0_STATUS_SLEEPING_Pos 0UL
+#define CPUSS_CM0_STATUS_SLEEPING_Msk 0x1UL
+#define CPUSS_CM0_STATUS_SLEEPDEEP_Pos 1UL
+#define CPUSS_CM0_STATUS_SLEEPDEEP_Msk 0x2UL
+/* CPUSS.CM0_CLOCK_CTL */
+#define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Pos 8UL
+#define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Msk 0xFF00UL
+#define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Pos 24UL
+#define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL0 */
+#define CPUSS_CM0_INT_CTL0_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL0_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL0_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL0_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL0_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL0_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL0_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL0_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL1 */
+#define CPUSS_CM0_INT_CTL1_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL1_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL1_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL1_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL1_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL1_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL1_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL1_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL2 */
+#define CPUSS_CM0_INT_CTL2_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL2_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL2_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL2_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL2_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL2_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL2_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL2_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL3 */
+#define CPUSS_CM0_INT_CTL3_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL3_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL3_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL3_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL3_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL3_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL3_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL3_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL4 */
+#define CPUSS_CM0_INT_CTL4_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL4_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL4_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL4_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL4_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL4_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL4_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL4_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL5 */
+#define CPUSS_CM0_INT_CTL5_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL5_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL5_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL5_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL5_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL5_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL5_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL5_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL6 */
+#define CPUSS_CM0_INT_CTL6_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL6_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL6_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL6_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL6_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL6_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL6_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL6_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL7 */
+#define CPUSS_CM0_INT_CTL7_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL7_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL7_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL7_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL7_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL7_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL7_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL7_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM4_PWR_CTL */
+#define CPUSS_CM4_PWR_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_CM4_PWR_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.CM4_PWR_DELAY_CTL */
+#define CPUSS_CM4_PWR_DELAY_CTL_UP_Pos 0UL
+#define CPUSS_CM4_PWR_DELAY_CTL_UP_Msk 0x3FFUL
+/* CPUSS.CM4_STATUS */
+#define CPUSS_CM4_STATUS_SLEEPING_Pos 0UL
+#define CPUSS_CM4_STATUS_SLEEPING_Msk 0x1UL
+#define CPUSS_CM4_STATUS_SLEEPDEEP_Pos 1UL
+#define CPUSS_CM4_STATUS_SLEEPDEEP_Msk 0x2UL
+#define CPUSS_CM4_STATUS_PWR_DONE_Pos 4UL
+#define CPUSS_CM4_STATUS_PWR_DONE_Msk 0x10UL
+/* CPUSS.CM4_CLOCK_CTL */
+#define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Pos 8UL
+#define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Msk 0xFF00UL
+/* CPUSS.CM4_NMI_CTL */
+#define CPUSS_CM4_NMI_CTL_MUX0_SEL_Pos 0UL
+#define CPUSS_CM4_NMI_CTL_MUX0_SEL_Msk 0xFFUL
+/* CPUSS.RAM0_CTL0 */
+#define CPUSS_RAM0_CTL0_SLOW_WS_Pos 0UL
+#define CPUSS_RAM0_CTL0_SLOW_WS_Msk 0x3UL
+#define CPUSS_RAM0_CTL0_FAST_WS_Pos 8UL
+#define CPUSS_RAM0_CTL0_FAST_WS_Msk 0x300UL
+/* CPUSS.RAM0_PWR_MACRO_CTL */
+#define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.RAM1_CTL0 */
+#define CPUSS_RAM1_CTL0_SLOW_WS_Pos 0UL
+#define CPUSS_RAM1_CTL0_SLOW_WS_Msk 0x3UL
+#define CPUSS_RAM1_CTL0_FAST_WS_Pos 8UL
+#define CPUSS_RAM1_CTL0_FAST_WS_Msk 0x300UL
+/* CPUSS.RAM1_PWR_CTL */
+#define CPUSS_RAM1_PWR_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_RAM1_PWR_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.RAM2_CTL0 */
+#define CPUSS_RAM2_CTL0_SLOW_WS_Pos 0UL
+#define CPUSS_RAM2_CTL0_SLOW_WS_Msk 0x3UL
+#define CPUSS_RAM2_CTL0_FAST_WS_Pos 8UL
+#define CPUSS_RAM2_CTL0_FAST_WS_Msk 0x300UL
+/* CPUSS.RAM2_PWR_CTL */
+#define CPUSS_RAM2_PWR_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_RAM2_PWR_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.RAM_PWR_DELAY_CTL */
+#define CPUSS_RAM_PWR_DELAY_CTL_UP_Pos 0UL
+#define CPUSS_RAM_PWR_DELAY_CTL_UP_Msk 0x3FFUL
+/* CPUSS.ROM_CTL */
+#define CPUSS_ROM_CTL_SLOW_WS_Pos 0UL
+#define CPUSS_ROM_CTL_SLOW_WS_Msk 0x3UL
+#define CPUSS_ROM_CTL_FAST_WS_Pos 8UL
+#define CPUSS_ROM_CTL_FAST_WS_Msk 0x300UL
+/* CPUSS.UDB_PWR_CTL */
+#define CPUSS_UDB_PWR_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_UDB_PWR_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.UDB_PWR_DELAY_CTL */
+#define CPUSS_UDB_PWR_DELAY_CTL_UP_Pos 0UL
+#define CPUSS_UDB_PWR_DELAY_CTL_UP_Msk 0x3FFUL
+/* CPUSS.DP_STATUS */
+#define CPUSS_DP_STATUS_SWJ_CONNECTED_Pos 0UL
+#define CPUSS_DP_STATUS_SWJ_CONNECTED_Msk 0x1UL
+#define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Pos 1UL
+#define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Msk 0x2UL
+#define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Pos 2UL
+#define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Msk 0x4UL
+/* CPUSS.BUFF_CTL */
+#define CPUSS_BUFF_CTL_WRITE_BUFF_Pos 0UL
+#define CPUSS_BUFF_CTL_WRITE_BUFF_Msk 0x1UL
+/* CPUSS.DDFT_CTL */
+#define CPUSS_DDFT_CTL_DDFT_OUT0_SEL_Pos 0UL
+#define CPUSS_DDFT_CTL_DDFT_OUT0_SEL_Msk 0x1FUL
+#define CPUSS_DDFT_CTL_DDFT_OUT1_SEL_Pos 8UL
+#define CPUSS_DDFT_CTL_DDFT_OUT1_SEL_Msk 0x1F00UL
+/* CPUSS.SYSTICK_CTL */
+#define CPUSS_SYSTICK_CTL_TENMS_Pos 0UL
+#define CPUSS_SYSTICK_CTL_TENMS_Msk 0xFFFFFFUL
+#define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Pos 24UL
+#define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Msk 0x3000000UL
+#define CPUSS_SYSTICK_CTL_SKEW_Pos 30UL
+#define CPUSS_SYSTICK_CTL_SKEW_Msk 0x40000000UL
+#define CPUSS_SYSTICK_CTL_NOREF_Pos 31UL
+#define CPUSS_SYSTICK_CTL_NOREF_Msk 0x80000000UL
+/* CPUSS.CM0_VECTOR_TABLE_BASE */
+#define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Pos 8UL
+#define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Msk 0xFFFFFF00UL
+/* CPUSS.CM4_VECTOR_TABLE_BASE */
+#define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Pos 10UL
+#define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Msk 0xFFFFFC00UL
+/* CPUSS.CM0_PC0_HANDLER */
+#define CPUSS_CM0_PC0_HANDLER_ADDR_Pos 0UL
+#define CPUSS_CM0_PC0_HANDLER_ADDR_Msk 0xFFFFFFFFUL
+/* CPUSS.IDENTITY */
+#define CPUSS_IDENTITY_P_Pos 0UL
+#define CPUSS_IDENTITY_P_Msk 0x1UL
+#define CPUSS_IDENTITY_NS_Pos 1UL
+#define CPUSS_IDENTITY_NS_Msk 0x2UL
+#define CPUSS_IDENTITY_PC_Pos 4UL
+#define CPUSS_IDENTITY_PC_Msk 0xF0UL
+#define CPUSS_IDENTITY_MS_Pos 8UL
+#define CPUSS_IDENTITY_MS_Msk 0xF00UL
+/* CPUSS.PROTECTION */
+#define CPUSS_PROTECTION_STATE_Pos 0UL
+#define CPUSS_PROTECTION_STATE_Msk 0x7UL
+/* CPUSS.CM0_NMI_CTL */
+#define CPUSS_CM0_NMI_CTL_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_NMI_CTL_MUX0_SEL_Msk 0xFFUL
+/* CPUSS.AP_CTL */
+#define CPUSS_AP_CTL_CM0_ENABLE_Pos 0UL
+#define CPUSS_AP_CTL_CM0_ENABLE_Msk 0x1UL
+#define CPUSS_AP_CTL_CM4_ENABLE_Pos 1UL
+#define CPUSS_AP_CTL_CM4_ENABLE_Msk 0x2UL
+#define CPUSS_AP_CTL_SYS_ENABLE_Pos 2UL
+#define CPUSS_AP_CTL_SYS_ENABLE_Msk 0x4UL
+#define CPUSS_AP_CTL_CM0_DISABLE_Pos 16UL
+#define CPUSS_AP_CTL_CM0_DISABLE_Msk 0x10000UL
+#define CPUSS_AP_CTL_CM4_DISABLE_Pos 17UL
+#define CPUSS_AP_CTL_CM4_DISABLE_Msk 0x20000UL
+#define CPUSS_AP_CTL_SYS_DISABLE_Pos 18UL
+#define CPUSS_AP_CTL_SYS_DISABLE_Msk 0x40000UL
+/* CPUSS.MBIST_STAT */
+#define CPUSS_MBIST_STAT_SFP_READY_Pos 0UL
+#define CPUSS_MBIST_STAT_SFP_READY_Msk 0x1UL
+#define CPUSS_MBIST_STAT_SFP_FAIL_Pos 1UL
+#define CPUSS_MBIST_STAT_SFP_FAIL_Msk 0x2UL
+/* CPUSS.TRIM_ROM_CTL */
+#define CPUSS_TRIM_ROM_CTL_RM_Pos 0UL
+#define CPUSS_TRIM_ROM_CTL_RM_Msk 0xFUL
+#define CPUSS_TRIM_ROM_CTL_RME_Pos 4UL
+#define CPUSS_TRIM_ROM_CTL_RME_Msk 0x10UL
+/* CPUSS.TRIM_RAM_CTL */
+#define CPUSS_TRIM_RAM_CTL_RM_Pos 0UL
+#define CPUSS_TRIM_RAM_CTL_RM_Msk 0xFUL
+#define CPUSS_TRIM_RAM_CTL_RME_Pos 4UL
+#define CPUSS_TRIM_RAM_CTL_RME_Msk 0x10UL
+#define CPUSS_TRIM_RAM_CTL_WPULSE_Pos 5UL
+#define CPUSS_TRIM_RAM_CTL_WPULSE_Msk 0xE0UL
+#define CPUSS_TRIM_RAM_CTL_RA_Pos 8UL
+#define CPUSS_TRIM_RAM_CTL_RA_Msk 0x300UL
+#define CPUSS_TRIM_RAM_CTL_WA_Pos 12UL
+#define CPUSS_TRIM_RAM_CTL_WA_Msk 0x7000UL
+
+
+#endif /* _CYIP_CPUSS_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_cpuss_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_cpuss_v2.h
new file mode 100644
index 0000000000..de0b8e6275
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_cpuss_v2.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+* \file cyip_cpuss_v2.h
+*
+* \brief
+* CPUSS IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_CPUSS_V2_H_
+#define _CYIP_CPUSS_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* CPUSS
+*******************************************************************************/
+
+#define CPUSS_V2_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief CPU subsystem (CPUSS) (CPUSS)
+ */
+typedef struct {
+ __IM uint32_t IDENTITY; /*!< 0x00000000 Identity */
+ __IM uint32_t CM4_STATUS; /*!< 0x00000004 CM4 status */
+ __IOM uint32_t CM4_CLOCK_CTL; /*!< 0x00000008 CM4 clock control */
+ __IOM uint32_t CM4_CTL; /*!< 0x0000000C CM4 control */
+ __IM uint32_t RESERVED[60];
+ __IM uint32_t CM4_INT0_STATUS; /*!< 0x00000100 CM4 interrupt 0 status */
+ __IM uint32_t CM4_INT1_STATUS; /*!< 0x00000104 CM4 interrupt 1 status */
+ __IM uint32_t CM4_INT2_STATUS; /*!< 0x00000108 CM4 interrupt 2 status */
+ __IM uint32_t CM4_INT3_STATUS; /*!< 0x0000010C CM4 interrupt 3 status */
+ __IM uint32_t CM4_INT4_STATUS; /*!< 0x00000110 CM4 interrupt 4 status */
+ __IM uint32_t CM4_INT5_STATUS; /*!< 0x00000114 CM4 interrupt 5 status */
+ __IM uint32_t CM4_INT6_STATUS; /*!< 0x00000118 CM4 interrupt 6 status */
+ __IM uint32_t CM4_INT7_STATUS; /*!< 0x0000011C CM4 interrupt 7 status */
+ __IM uint32_t RESERVED1[56];
+ __IOM uint32_t CM4_VECTOR_TABLE_BASE; /*!< 0x00000200 CM4 vector table base */
+ __IM uint32_t RESERVED2[15];
+ __IOM uint32_t CM4_NMI_CTL[4]; /*!< 0x00000240 CM4 NMI control */
+ __IM uint32_t RESERVED3[44];
+ __IOM uint32_t UDB_PWR_CTL; /*!< 0x00000300 UDB power control */
+ __IOM uint32_t UDB_PWR_DELAY_CTL; /*!< 0x00000304 UDB power control */
+ __IM uint32_t RESERVED4[830];
+ __IOM uint32_t CM0_CTL; /*!< 0x00001000 CM0+ control */
+ __IM uint32_t CM0_STATUS; /*!< 0x00001004 CM0+ status */
+ __IOM uint32_t CM0_CLOCK_CTL; /*!< 0x00001008 CM0+ clock control */
+ __IM uint32_t RESERVED5[61];
+ __IM uint32_t CM0_INT0_STATUS; /*!< 0x00001100 CM0+ interrupt 0 status */
+ __IM uint32_t CM0_INT1_STATUS; /*!< 0x00001104 CM0+ interrupt 1 status */
+ __IM uint32_t CM0_INT2_STATUS; /*!< 0x00001108 CM0+ interrupt 2 status */
+ __IM uint32_t CM0_INT3_STATUS; /*!< 0x0000110C CM0+ interrupt 3 status */
+ __IM uint32_t CM0_INT4_STATUS; /*!< 0x00001110 CM0+ interrupt 4 status */
+ __IM uint32_t CM0_INT5_STATUS; /*!< 0x00001114 CM0+ interrupt 5 status */
+ __IM uint32_t CM0_INT6_STATUS; /*!< 0x00001118 CM0+ interrupt 6 status */
+ __IM uint32_t CM0_INT7_STATUS; /*!< 0x0000111C CM0+ interrupt 7 status */
+ __IOM uint32_t CM0_VECTOR_TABLE_BASE; /*!< 0x00001120 CM0+ vector table base */
+ __IM uint32_t RESERVED6[7];
+ __IOM uint32_t CM0_NMI_CTL[4]; /*!< 0x00001140 CM0+ NMI control */
+ __IM uint32_t RESERVED7[44];
+ __IOM uint32_t CM4_PWR_CTL; /*!< 0x00001200 CM4 power control */
+ __IOM uint32_t CM4_PWR_DELAY_CTL; /*!< 0x00001204 CM4 power control */
+ __IM uint32_t RESERVED8[62];
+ __IOM uint32_t RAM0_CTL0; /*!< 0x00001300 RAM 0 control */
+ __IM uint32_t RAM0_STATUS; /*!< 0x00001304 RAM 0 status */
+ __IM uint32_t RESERVED9[14];
+ __IOM uint32_t RAM0_PWR_MACRO_CTL[16]; /*!< 0x00001340 RAM 0 power control */
+ __IOM uint32_t RAM1_CTL0; /*!< 0x00001380 RAM 1 control */
+ __IM uint32_t RAM1_STATUS; /*!< 0x00001384 RAM 1 status */
+ __IOM uint32_t RAM1_PWR_CTL; /*!< 0x00001388 RAM 1 power control */
+ __IM uint32_t RESERVED10[5];
+ __IOM uint32_t RAM2_CTL0; /*!< 0x000013A0 RAM 2 control */
+ __IM uint32_t RAM2_STATUS; /*!< 0x000013A4 RAM 2 status */
+ __IOM uint32_t RAM2_PWR_CTL; /*!< 0x000013A8 RAM 2 power control */
+ __IM uint32_t RESERVED11[5];
+ __IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x000013C0 Power up delay used for all SRAM power domains */
+ __IOM uint32_t ROM_CTL; /*!< 0x000013C4 ROM control */
+ __IOM uint32_t ECC_CTL; /*!< 0x000013C8 ECC control */
+ __IM uint32_t RESERVED12[13];
+ __IM uint32_t PRODUCT_ID; /*!< 0x00001400 Product identifier and version (same as CoreSight RomTables) */
+ __IM uint32_t RESERVED13[3];
+ __IM uint32_t DP_STATUS; /*!< 0x00001410 Debug port status */
+ __IOM uint32_t AP_CTL; /*!< 0x00001414 Access port control */
+ __IM uint32_t RESERVED14[58];
+ __IOM uint32_t BUFF_CTL; /*!< 0x00001500 Buffer control */
+ __IM uint32_t RESERVED15[63];
+ __IOM uint32_t SYSTICK_CTL; /*!< 0x00001600 SysTick timer control */
+ __IM uint32_t RESERVED16[64];
+ __IM uint32_t MBIST_STAT; /*!< 0x00001704 Memory BIST status */
+ __IM uint32_t RESERVED17[62];
+ __IOM uint32_t CAL_SUP_SET; /*!< 0x00001800 Calibration support set and read */
+ __IOM uint32_t CAL_SUP_CLR; /*!< 0x00001804 Calibration support clear and reset */
+ __IM uint32_t RESERVED18[510];
+ __IOM uint32_t CM0_PC_CTL; /*!< 0x00002000 CM0+ protection context control */
+ __IM uint32_t RESERVED19[15];
+ __IOM uint32_t CM0_PC0_HANDLER; /*!< 0x00002040 CM0+ protection context 0 handler */
+ __IOM uint32_t CM0_PC1_HANDLER; /*!< 0x00002044 CM0+ protection context 1 handler */
+ __IOM uint32_t CM0_PC2_HANDLER; /*!< 0x00002048 CM0+ protection context 2 handler */
+ __IOM uint32_t CM0_PC3_HANDLER; /*!< 0x0000204C CM0+ protection context 3 handler */
+ __IM uint32_t RESERVED20[29];
+ __IOM uint32_t PROTECTION; /*!< 0x000020C4 Protection status */
+ __IM uint32_t RESERVED21[14];
+ __IOM uint32_t TRIM_ROM_CTL; /*!< 0x00002100 ROM trim control */
+ __IOM uint32_t TRIM_RAM_CTL; /*!< 0x00002104 RAM trim control */
+ __IM uint32_t RESERVED22[6078];
+ __IOM uint32_t CM0_SYSTEM_INT_CTL[1023]; /*!< 0x00008000 CM0+ system interrupt control */
+ __IM uint32_t RESERVED23[1025];
+ __IOM uint32_t CM4_SYSTEM_INT_CTL[1023]; /*!< 0x0000A000 CM4 system interrupt control */
+} CPUSS_V2_Type; /*!< Size = 45052 (0xAFFC) */
+
+
+/* CPUSS.IDENTITY */
+#define CPUSS_V2_IDENTITY_P_Pos 0UL
+#define CPUSS_V2_IDENTITY_P_Msk 0x1UL
+#define CPUSS_V2_IDENTITY_NS_Pos 1UL
+#define CPUSS_V2_IDENTITY_NS_Msk 0x2UL
+#define CPUSS_V2_IDENTITY_PC_Pos 4UL
+#define CPUSS_V2_IDENTITY_PC_Msk 0xF0UL
+#define CPUSS_V2_IDENTITY_MS_Pos 8UL
+#define CPUSS_V2_IDENTITY_MS_Msk 0xF00UL
+/* CPUSS.CM4_STATUS */
+#define CPUSS_V2_CM4_STATUS_SLEEPING_Pos 0UL
+#define CPUSS_V2_CM4_STATUS_SLEEPING_Msk 0x1UL
+#define CPUSS_V2_CM4_STATUS_SLEEPDEEP_Pos 1UL
+#define CPUSS_V2_CM4_STATUS_SLEEPDEEP_Msk 0x2UL
+#define CPUSS_V2_CM4_STATUS_PWR_DONE_Pos 4UL
+#define CPUSS_V2_CM4_STATUS_PWR_DONE_Msk 0x10UL
+/* CPUSS.CM4_CLOCK_CTL */
+#define CPUSS_V2_CM4_CLOCK_CTL_FAST_INT_DIV_Pos 8UL
+#define CPUSS_V2_CM4_CLOCK_CTL_FAST_INT_DIV_Msk 0xFF00UL
+/* CPUSS.CM4_CTL */
+#define CPUSS_V2_CM4_CTL_IOC_MASK_Pos 24UL
+#define CPUSS_V2_CM4_CTL_IOC_MASK_Msk 0x1000000UL
+#define CPUSS_V2_CM4_CTL_DZC_MASK_Pos 25UL
+#define CPUSS_V2_CM4_CTL_DZC_MASK_Msk 0x2000000UL
+#define CPUSS_V2_CM4_CTL_OFC_MASK_Pos 26UL
+#define CPUSS_V2_CM4_CTL_OFC_MASK_Msk 0x4000000UL
+#define CPUSS_V2_CM4_CTL_UFC_MASK_Pos 27UL
+#define CPUSS_V2_CM4_CTL_UFC_MASK_Msk 0x8000000UL
+#define CPUSS_V2_CM4_CTL_IXC_MASK_Pos 28UL
+#define CPUSS_V2_CM4_CTL_IXC_MASK_Msk 0x10000000UL
+#define CPUSS_V2_CM4_CTL_IDC_MASK_Pos 31UL
+#define CPUSS_V2_CM4_CTL_IDC_MASK_Msk 0x80000000UL
+/* CPUSS.CM4_INT0_STATUS */
+#define CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM4_INT1_STATUS */
+#define CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM4_INT2_STATUS */
+#define CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM4_INT3_STATUS */
+#define CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM4_INT4_STATUS */
+#define CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM4_INT5_STATUS */
+#define CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM4_INT6_STATUS */
+#define CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM4_INT7_STATUS */
+#define CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM4_VECTOR_TABLE_BASE */
+#define CPUSS_V2_CM4_VECTOR_TABLE_BASE_ADDR22_Pos 10UL
+#define CPUSS_V2_CM4_VECTOR_TABLE_BASE_ADDR22_Msk 0xFFFFFC00UL
+/* CPUSS.CM4_NMI_CTL */
+#define CPUSS_V2_CM4_NMI_CTL_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM4_NMI_CTL_SYSTEM_INT_IDX_Msk 0x3FFUL
+/* CPUSS.UDB_PWR_CTL */
+#define CPUSS_V2_UDB_PWR_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_V2_UDB_PWR_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_V2_UDB_PWR_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_V2_UDB_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.UDB_PWR_DELAY_CTL */
+#define CPUSS_V2_UDB_PWR_DELAY_CTL_UP_Pos 0UL
+#define CPUSS_V2_UDB_PWR_DELAY_CTL_UP_Msk 0x3FFUL
+/* CPUSS.CM0_CTL */
+#define CPUSS_V2_CM0_CTL_SLV_STALL_Pos 0UL
+#define CPUSS_V2_CM0_CTL_SLV_STALL_Msk 0x1UL
+#define CPUSS_V2_CM0_CTL_ENABLED_Pos 1UL
+#define CPUSS_V2_CM0_CTL_ENABLED_Msk 0x2UL
+#define CPUSS_V2_CM0_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_V2_CM0_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.CM0_STATUS */
+#define CPUSS_V2_CM0_STATUS_SLEEPING_Pos 0UL
+#define CPUSS_V2_CM0_STATUS_SLEEPING_Msk 0x1UL
+#define CPUSS_V2_CM0_STATUS_SLEEPDEEP_Pos 1UL
+#define CPUSS_V2_CM0_STATUS_SLEEPDEEP_Msk 0x2UL
+/* CPUSS.CM0_CLOCK_CTL */
+#define CPUSS_V2_CM0_CLOCK_CTL_SLOW_INT_DIV_Pos 8UL
+#define CPUSS_V2_CM0_CLOCK_CTL_SLOW_INT_DIV_Msk 0xFF00UL
+#define CPUSS_V2_CM0_CLOCK_CTL_PERI_INT_DIV_Pos 24UL
+#define CPUSS_V2_CM0_CLOCK_CTL_PERI_INT_DIV_Msk 0xFF000000UL
+/* CPUSS.CM0_INT0_STATUS */
+#define CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM0_INT1_STATUS */
+#define CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM0_INT2_STATUS */
+#define CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM0_INT3_STATUS */
+#define CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM0_INT4_STATUS */
+#define CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM0_INT5_STATUS */
+#define CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM0_INT6_STATUS */
+#define CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM0_INT7_STATUS */
+#define CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
+#define CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM0_VECTOR_TABLE_BASE */
+#define CPUSS_V2_CM0_VECTOR_TABLE_BASE_ADDR24_Pos 8UL
+#define CPUSS_V2_CM0_VECTOR_TABLE_BASE_ADDR24_Msk 0xFFFFFF00UL
+/* CPUSS.CM0_NMI_CTL */
+#define CPUSS_V2_CM0_NMI_CTL_SYSTEM_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM0_NMI_CTL_SYSTEM_INT_IDX_Msk 0x3FFUL
+/* CPUSS.CM4_PWR_CTL */
+#define CPUSS_V2_CM4_PWR_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_V2_CM4_PWR_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_V2_CM4_PWR_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_V2_CM4_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.CM4_PWR_DELAY_CTL */
+#define CPUSS_V2_CM4_PWR_DELAY_CTL_UP_Pos 0UL
+#define CPUSS_V2_CM4_PWR_DELAY_CTL_UP_Msk 0x3FFUL
+/* CPUSS.RAM0_CTL0 */
+#define CPUSS_V2_RAM0_CTL0_SLOW_WS_Pos 0UL
+#define CPUSS_V2_RAM0_CTL0_SLOW_WS_Msk 0x3UL
+#define CPUSS_V2_RAM0_CTL0_FAST_WS_Pos 8UL
+#define CPUSS_V2_RAM0_CTL0_FAST_WS_Msk 0x300UL
+#define CPUSS_V2_RAM0_CTL0_ECC_EN_Pos 16UL
+#define CPUSS_V2_RAM0_CTL0_ECC_EN_Msk 0x10000UL
+#define CPUSS_V2_RAM0_CTL0_ECC_AUTO_CORRECT_Pos 17UL
+#define CPUSS_V2_RAM0_CTL0_ECC_AUTO_CORRECT_Msk 0x20000UL
+#define CPUSS_V2_RAM0_CTL0_ECC_INJ_EN_Pos 18UL
+#define CPUSS_V2_RAM0_CTL0_ECC_INJ_EN_Msk 0x40000UL
+/* CPUSS.RAM0_STATUS */
+#define CPUSS_V2_RAM0_STATUS_WB_EMPTY_Pos 0UL
+#define CPUSS_V2_RAM0_STATUS_WB_EMPTY_Msk 0x1UL
+/* CPUSS.RAM0_PWR_MACRO_CTL */
+#define CPUSS_V2_RAM0_PWR_MACRO_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_V2_RAM0_PWR_MACRO_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_V2_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_V2_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.RAM1_CTL0 */
+#define CPUSS_V2_RAM1_CTL0_SLOW_WS_Pos 0UL
+#define CPUSS_V2_RAM1_CTL0_SLOW_WS_Msk 0x3UL
+#define CPUSS_V2_RAM1_CTL0_FAST_WS_Pos 8UL
+#define CPUSS_V2_RAM1_CTL0_FAST_WS_Msk 0x300UL
+#define CPUSS_V2_RAM1_CTL0_ECC_EN_Pos 16UL
+#define CPUSS_V2_RAM1_CTL0_ECC_EN_Msk 0x10000UL
+#define CPUSS_V2_RAM1_CTL0_ECC_AUTO_CORRECT_Pos 17UL
+#define CPUSS_V2_RAM1_CTL0_ECC_AUTO_CORRECT_Msk 0x20000UL
+#define CPUSS_V2_RAM1_CTL0_ECC_INJ_EN_Pos 18UL
+#define CPUSS_V2_RAM1_CTL0_ECC_INJ_EN_Msk 0x40000UL
+/* CPUSS.RAM1_STATUS */
+#define CPUSS_V2_RAM1_STATUS_WB_EMPTY_Pos 0UL
+#define CPUSS_V2_RAM1_STATUS_WB_EMPTY_Msk 0x1UL
+/* CPUSS.RAM1_PWR_CTL */
+#define CPUSS_V2_RAM1_PWR_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_V2_RAM1_PWR_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_V2_RAM1_PWR_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_V2_RAM1_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.RAM2_CTL0 */
+#define CPUSS_V2_RAM2_CTL0_SLOW_WS_Pos 0UL
+#define CPUSS_V2_RAM2_CTL0_SLOW_WS_Msk 0x3UL
+#define CPUSS_V2_RAM2_CTL0_FAST_WS_Pos 8UL
+#define CPUSS_V2_RAM2_CTL0_FAST_WS_Msk 0x300UL
+#define CPUSS_V2_RAM2_CTL0_ECC_EN_Pos 16UL
+#define CPUSS_V2_RAM2_CTL0_ECC_EN_Msk 0x10000UL
+#define CPUSS_V2_RAM2_CTL0_ECC_AUTO_CORRECT_Pos 17UL
+#define CPUSS_V2_RAM2_CTL0_ECC_AUTO_CORRECT_Msk 0x20000UL
+#define CPUSS_V2_RAM2_CTL0_ECC_INJ_EN_Pos 18UL
+#define CPUSS_V2_RAM2_CTL0_ECC_INJ_EN_Msk 0x40000UL
+/* CPUSS.RAM2_STATUS */
+#define CPUSS_V2_RAM2_STATUS_WB_EMPTY_Pos 0UL
+#define CPUSS_V2_RAM2_STATUS_WB_EMPTY_Msk 0x1UL
+/* CPUSS.RAM2_PWR_CTL */
+#define CPUSS_V2_RAM2_PWR_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_V2_RAM2_PWR_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_V2_RAM2_PWR_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_V2_RAM2_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.RAM_PWR_DELAY_CTL */
+#define CPUSS_V2_RAM_PWR_DELAY_CTL_UP_Pos 0UL
+#define CPUSS_V2_RAM_PWR_DELAY_CTL_UP_Msk 0x3FFUL
+/* CPUSS.ROM_CTL */
+#define CPUSS_V2_ROM_CTL_SLOW_WS_Pos 0UL
+#define CPUSS_V2_ROM_CTL_SLOW_WS_Msk 0x3UL
+#define CPUSS_V2_ROM_CTL_FAST_WS_Pos 8UL
+#define CPUSS_V2_ROM_CTL_FAST_WS_Msk 0x300UL
+/* CPUSS.ECC_CTL */
+#define CPUSS_V2_ECC_CTL_WORD_ADDR_Pos 0UL
+#define CPUSS_V2_ECC_CTL_WORD_ADDR_Msk 0x1FFFFFFUL
+#define CPUSS_V2_ECC_CTL_PARITY_Pos 25UL
+#define CPUSS_V2_ECC_CTL_PARITY_Msk 0xFE000000UL
+/* CPUSS.PRODUCT_ID */
+#define CPUSS_V2_PRODUCT_ID_FAMILY_ID_Pos 0UL
+#define CPUSS_V2_PRODUCT_ID_FAMILY_ID_Msk 0xFFFUL
+#define CPUSS_V2_PRODUCT_ID_MAJOR_REV_Pos 16UL
+#define CPUSS_V2_PRODUCT_ID_MAJOR_REV_Msk 0xF0000UL
+#define CPUSS_V2_PRODUCT_ID_MINOR_REV_Pos 20UL
+#define CPUSS_V2_PRODUCT_ID_MINOR_REV_Msk 0xF00000UL
+/* CPUSS.DP_STATUS */
+#define CPUSS_V2_DP_STATUS_SWJ_CONNECTED_Pos 0UL
+#define CPUSS_V2_DP_STATUS_SWJ_CONNECTED_Msk 0x1UL
+#define CPUSS_V2_DP_STATUS_SWJ_DEBUG_EN_Pos 1UL
+#define CPUSS_V2_DP_STATUS_SWJ_DEBUG_EN_Msk 0x2UL
+#define CPUSS_V2_DP_STATUS_SWJ_JTAG_SEL_Pos 2UL
+#define CPUSS_V2_DP_STATUS_SWJ_JTAG_SEL_Msk 0x4UL
+/* CPUSS.AP_CTL */
+#define CPUSS_V2_AP_CTL_CM0_ENABLE_Pos 0UL
+#define CPUSS_V2_AP_CTL_CM0_ENABLE_Msk 0x1UL
+#define CPUSS_V2_AP_CTL_CM4_ENABLE_Pos 1UL
+#define CPUSS_V2_AP_CTL_CM4_ENABLE_Msk 0x2UL
+#define CPUSS_V2_AP_CTL_SYS_ENABLE_Pos 2UL
+#define CPUSS_V2_AP_CTL_SYS_ENABLE_Msk 0x4UL
+#define CPUSS_V2_AP_CTL_CM0_DISABLE_Pos 16UL
+#define CPUSS_V2_AP_CTL_CM0_DISABLE_Msk 0x10000UL
+#define CPUSS_V2_AP_CTL_CM4_DISABLE_Pos 17UL
+#define CPUSS_V2_AP_CTL_CM4_DISABLE_Msk 0x20000UL
+#define CPUSS_V2_AP_CTL_SYS_DISABLE_Pos 18UL
+#define CPUSS_V2_AP_CTL_SYS_DISABLE_Msk 0x40000UL
+/* CPUSS.BUFF_CTL */
+#define CPUSS_V2_BUFF_CTL_WRITE_BUFF_Pos 0UL
+#define CPUSS_V2_BUFF_CTL_WRITE_BUFF_Msk 0x1UL
+/* CPUSS.SYSTICK_CTL */
+#define CPUSS_V2_SYSTICK_CTL_TENMS_Pos 0UL
+#define CPUSS_V2_SYSTICK_CTL_TENMS_Msk 0xFFFFFFUL
+#define CPUSS_V2_SYSTICK_CTL_CLOCK_SOURCE_Pos 24UL
+#define CPUSS_V2_SYSTICK_CTL_CLOCK_SOURCE_Msk 0x3000000UL
+#define CPUSS_V2_SYSTICK_CTL_SKEW_Pos 30UL
+#define CPUSS_V2_SYSTICK_CTL_SKEW_Msk 0x40000000UL
+#define CPUSS_V2_SYSTICK_CTL_NOREF_Pos 31UL
+#define CPUSS_V2_SYSTICK_CTL_NOREF_Msk 0x80000000UL
+/* CPUSS.MBIST_STAT */
+#define CPUSS_V2_MBIST_STAT_SFP_READY_Pos 0UL
+#define CPUSS_V2_MBIST_STAT_SFP_READY_Msk 0x1UL
+#define CPUSS_V2_MBIST_STAT_SFP_FAIL_Pos 1UL
+#define CPUSS_V2_MBIST_STAT_SFP_FAIL_Msk 0x2UL
+/* CPUSS.CAL_SUP_SET */
+#define CPUSS_V2_CAL_SUP_SET_DATA_Pos 0UL
+#define CPUSS_V2_CAL_SUP_SET_DATA_Msk 0xFFFFFFFFUL
+/* CPUSS.CAL_SUP_CLR */
+#define CPUSS_V2_CAL_SUP_CLR_DATA_Pos 0UL
+#define CPUSS_V2_CAL_SUP_CLR_DATA_Msk 0xFFFFFFFFUL
+/* CPUSS.CM0_PC_CTL */
+#define CPUSS_V2_CM0_PC_CTL_VALID_Pos 0UL
+#define CPUSS_V2_CM0_PC_CTL_VALID_Msk 0xFUL
+/* CPUSS.CM0_PC0_HANDLER */
+#define CPUSS_V2_CM0_PC0_HANDLER_ADDR_Pos 0UL
+#define CPUSS_V2_CM0_PC0_HANDLER_ADDR_Msk 0xFFFFFFFFUL
+/* CPUSS.CM0_PC1_HANDLER */
+#define CPUSS_V2_CM0_PC1_HANDLER_ADDR_Pos 0UL
+#define CPUSS_V2_CM0_PC1_HANDLER_ADDR_Msk 0xFFFFFFFFUL
+/* CPUSS.CM0_PC2_HANDLER */
+#define CPUSS_V2_CM0_PC2_HANDLER_ADDR_Pos 0UL
+#define CPUSS_V2_CM0_PC2_HANDLER_ADDR_Msk 0xFFFFFFFFUL
+/* CPUSS.CM0_PC3_HANDLER */
+#define CPUSS_V2_CM0_PC3_HANDLER_ADDR_Pos 0UL
+#define CPUSS_V2_CM0_PC3_HANDLER_ADDR_Msk 0xFFFFFFFFUL
+/* CPUSS.PROTECTION */
+#define CPUSS_V2_PROTECTION_STATE_Pos 0UL
+#define CPUSS_V2_PROTECTION_STATE_Msk 0x7UL
+/* CPUSS.TRIM_ROM_CTL */
+#define CPUSS_V2_TRIM_ROM_CTL_TRIM_Pos 0UL
+#define CPUSS_V2_TRIM_ROM_CTL_TRIM_Msk 0xFFFFFFFFUL
+/* CPUSS.TRIM_RAM_CTL */
+#define CPUSS_V2_TRIM_RAM_CTL_TRIM_Pos 0UL
+#define CPUSS_V2_TRIM_RAM_CTL_TRIM_Msk 0xFFFFFFFFUL
+/* CPUSS.CM0_SYSTEM_INT_CTL */
+#define CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Msk 0x7UL
+#define CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk 0x80000000UL
+/* CPUSS.CM4_SYSTEM_INT_CTL */
+#define CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Pos 0UL
+#define CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Msk 0x7UL
+#define CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Pos 31UL
+#define CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Msk 0x80000000UL
+
+
+#endif /* _CYIP_CPUSS_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_crypto.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_crypto.h
new file mode 100644
index 0000000000..f04a7ffa12
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_crypto.h
@@ -0,0 +1,384 @@
+/***************************************************************************//**
+* \file cyip_crypto.h
+*
+* \brief
+* CRYPTO IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_CRYPTO_H_
+#define _CYIP_CRYPTO_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* CRYPTO
+*******************************************************************************/
+
+#define CRYPTO_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Cryptography component (CRYPTO)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t STATUS; /*!< 0x00000004 Status */
+ __IOM uint32_t RAM_PWRUP_DELAY; /*!< 0x00000008 Power up delay used for SRAM power domain */
+ __IM uint32_t RESERVED[5];
+ __IM uint32_t ERROR_STATUS0; /*!< 0x00000020 Error status 0 */
+ __IOM uint32_t ERROR_STATUS1; /*!< 0x00000024 Error status 1 */
+ __IM uint32_t RESERVED1[6];
+ __IOM uint32_t INSTR_FF_CTL; /*!< 0x00000040 Instruction FIFO control */
+ __IM uint32_t INSTR_FF_STATUS; /*!< 0x00000044 Instruction FIFO status */
+ __OM uint32_t INSTR_FF_WR; /*!< 0x00000048 Instruction FIFO write */
+ __IM uint32_t RESERVED2[13];
+ __IM uint32_t RF_DATA[16]; /*!< 0x00000080 Register-file */
+ __IM uint32_t RESERVED3[16];
+ __IOM uint32_t AES_CTL; /*!< 0x00000100 AES control */
+ __IM uint32_t RESERVED4[31];
+ __IM uint32_t STR_RESULT; /*!< 0x00000180 String result */
+ __IM uint32_t RESERVED5[31];
+ __IOM uint32_t PR_LFSR_CTL0; /*!< 0x00000200 Pseudo random LFSR control 0 */
+ __IOM uint32_t PR_LFSR_CTL1; /*!< 0x00000204 Pseudo random LFSR control 1 */
+ __IOM uint32_t PR_LFSR_CTL2; /*!< 0x00000208 Pseudo random LFSR control 2 */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t PR_RESULT; /*!< 0x00000210 Pseudo random result */
+ __IM uint32_t RESERVED7[27];
+ __IOM uint32_t TR_CTL0; /*!< 0x00000280 True random control 0 */
+ __IOM uint32_t TR_CTL1; /*!< 0x00000284 True random control 1 */
+ __IOM uint32_t TR_RESULT; /*!< 0x00000288 True random result */
+ __IM uint32_t RESERVED8[5];
+ __IOM uint32_t TR_GARO_CTL; /*!< 0x000002A0 True random GARO control */
+ __IOM uint32_t TR_FIRO_CTL; /*!< 0x000002A4 True random FIRO control */
+ __IM uint32_t RESERVED9[6];
+ __IOM uint32_t TR_MON_CTL; /*!< 0x000002C0 True random monitor control */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t TR_MON_CMD; /*!< 0x000002C8 True random monitor command */
+ __IM uint32_t RESERVED11;
+ __IOM uint32_t TR_MON_RC_CTL; /*!< 0x000002D0 True random monitor RC control */
+ __IM uint32_t RESERVED12;
+ __IM uint32_t TR_MON_RC_STATUS0; /*!< 0x000002D8 True random monitor RC status 0 */
+ __IM uint32_t TR_MON_RC_STATUS1; /*!< 0x000002DC True random monitor RC status 1 */
+ __IOM uint32_t TR_MON_AP_CTL; /*!< 0x000002E0 True random monitor AP control */
+ __IM uint32_t RESERVED13;
+ __IM uint32_t TR_MON_AP_STATUS0; /*!< 0x000002E8 True random monitor AP status 0 */
+ __IM uint32_t TR_MON_AP_STATUS1; /*!< 0x000002EC True random monitor AP status 1 */
+ __IM uint32_t RESERVED14[4];
+ __IOM uint32_t SHA_CTL; /*!< 0x00000300 SHA control */
+ __IM uint32_t RESERVED15[63];
+ __IOM uint32_t CRC_CTL; /*!< 0x00000400 CRC control */
+ __IM uint32_t RESERVED16[3];
+ __IOM uint32_t CRC_DATA_CTL; /*!< 0x00000410 CRC data control */
+ __IM uint32_t RESERVED17[3];
+ __IOM uint32_t CRC_POL_CTL; /*!< 0x00000420 CRC polynomial control */
+ __IM uint32_t RESERVED18[3];
+ __IOM uint32_t CRC_LFSR_CTL; /*!< 0x00000430 CRC LFSR control */
+ __IM uint32_t RESERVED19[3];
+ __IOM uint32_t CRC_REM_CTL; /*!< 0x00000440 CRC remainder control */
+ __IM uint32_t RESERVED20;
+ __IM uint32_t CRC_REM_RESULT; /*!< 0x00000448 CRC remainder result */
+ __IM uint32_t RESERVED21[13];
+ __IOM uint32_t VU_CTL0; /*!< 0x00000480 Vector unit control 0 */
+ __IOM uint32_t VU_CTL1; /*!< 0x00000484 Vector unit control 1 */
+ __IM uint32_t RESERVED22[2];
+ __IM uint32_t VU_STATUS; /*!< 0x00000490 Vector unit status */
+ __IM uint32_t RESERVED23[203];
+ __IOM uint32_t INTR; /*!< 0x000007C0 Interrupt register */
+ __IOM uint32_t INTR_SET; /*!< 0x000007C4 Interrupt set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x000007CC Interrupt masked register */
+ __IM uint32_t RESERVED24[3596];
+ __IOM uint32_t MEM_BUFF[4096]; /*!< 0x00004000 Memory buffer */
+} CRYPTO_V1_Type; /*!< Size = 32768 (0x8000) */
+
+
+/* CRYPTO.CTL */
+#define CRYPTO_CTL_PWR_MODE_Pos 0UL
+#define CRYPTO_CTL_PWR_MODE_Msk 0x3UL
+#define CRYPTO_CTL_ENABLED_Pos 31UL
+#define CRYPTO_CTL_ENABLED_Msk 0x80000000UL
+/* CRYPTO.STATUS */
+#define CRYPTO_STATUS_AES_BUSY_Pos 0UL
+#define CRYPTO_STATUS_AES_BUSY_Msk 0x1UL
+#define CRYPTO_STATUS_DES_BUSY_Pos 1UL
+#define CRYPTO_STATUS_DES_BUSY_Msk 0x2UL
+#define CRYPTO_STATUS_SHA_BUSY_Pos 2UL
+#define CRYPTO_STATUS_SHA_BUSY_Msk 0x4UL
+#define CRYPTO_STATUS_CRC_BUSY_Pos 3UL
+#define CRYPTO_STATUS_CRC_BUSY_Msk 0x8UL
+#define CRYPTO_STATUS_STR_BUSY_Pos 4UL
+#define CRYPTO_STATUS_STR_BUSY_Msk 0x10UL
+#define CRYPTO_STATUS_PR_BUSY_Pos 5UL
+#define CRYPTO_STATUS_PR_BUSY_Msk 0x20UL
+#define CRYPTO_STATUS_TR_BUSY_Pos 6UL
+#define CRYPTO_STATUS_TR_BUSY_Msk 0x40UL
+#define CRYPTO_STATUS_VU_BUSY_Pos 7UL
+#define CRYPTO_STATUS_VU_BUSY_Msk 0x80UL
+#define CRYPTO_STATUS_CMD_FF_BUSY_Pos 31UL
+#define CRYPTO_STATUS_CMD_FF_BUSY_Msk 0x80000000UL
+/* CRYPTO.RAM_PWRUP_DELAY */
+#define CRYPTO_RAM_PWRUP_DELAY_PWRUP_DELAY_Pos 0UL
+#define CRYPTO_RAM_PWRUP_DELAY_PWRUP_DELAY_Msk 0x3FFUL
+/* CRYPTO.ERROR_STATUS0 */
+#define CRYPTO_ERROR_STATUS0_DATA32_Pos 0UL
+#define CRYPTO_ERROR_STATUS0_DATA32_Msk 0xFFFFFFFFUL
+/* CRYPTO.ERROR_STATUS1 */
+#define CRYPTO_ERROR_STATUS1_DATA23_Pos 0UL
+#define CRYPTO_ERROR_STATUS1_DATA23_Msk 0xFFFFFFUL
+#define CRYPTO_ERROR_STATUS1_IDX_Pos 24UL
+#define CRYPTO_ERROR_STATUS1_IDX_Msk 0x7000000UL
+#define CRYPTO_ERROR_STATUS1_VALID_Pos 31UL
+#define CRYPTO_ERROR_STATUS1_VALID_Msk 0x80000000UL
+/* CRYPTO.INSTR_FF_CTL */
+#define CRYPTO_INSTR_FF_CTL_EVENT_LEVEL_Pos 0UL
+#define CRYPTO_INSTR_FF_CTL_EVENT_LEVEL_Msk 0x7UL
+#define CRYPTO_INSTR_FF_CTL_CLEAR_Pos 16UL
+#define CRYPTO_INSTR_FF_CTL_CLEAR_Msk 0x10000UL
+#define CRYPTO_INSTR_FF_CTL_BLOCK_Pos 17UL
+#define CRYPTO_INSTR_FF_CTL_BLOCK_Msk 0x20000UL
+/* CRYPTO.INSTR_FF_STATUS */
+#define CRYPTO_INSTR_FF_STATUS_USED_Pos 0UL
+#define CRYPTO_INSTR_FF_STATUS_USED_Msk 0xFUL
+#define CRYPTO_INSTR_FF_STATUS_EVENT_Pos 16UL
+#define CRYPTO_INSTR_FF_STATUS_EVENT_Msk 0x10000UL
+#define CRYPTO_INSTR_FF_STATUS_BUSY_Pos 31UL
+#define CRYPTO_INSTR_FF_STATUS_BUSY_Msk 0x80000000UL
+/* CRYPTO.INSTR_FF_WR */
+#define CRYPTO_INSTR_FF_WR_DATA32_Pos 0UL
+#define CRYPTO_INSTR_FF_WR_DATA32_Msk 0xFFFFFFFFUL
+/* CRYPTO.RF_DATA */
+#define CRYPTO_RF_DATA_DATA32_Pos 0UL
+#define CRYPTO_RF_DATA_DATA32_Msk 0xFFFFFFFFUL
+/* CRYPTO.AES_CTL */
+#define CRYPTO_AES_CTL_KEY_SIZE_Pos 0UL
+#define CRYPTO_AES_CTL_KEY_SIZE_Msk 0x3UL
+/* CRYPTO.STR_RESULT */
+#define CRYPTO_STR_RESULT_MEMCMP_Pos 0UL
+#define CRYPTO_STR_RESULT_MEMCMP_Msk 0x1UL
+/* CRYPTO.PR_LFSR_CTL0 */
+#define CRYPTO_PR_LFSR_CTL0_LFSR32_Pos 0UL
+#define CRYPTO_PR_LFSR_CTL0_LFSR32_Msk 0xFFFFFFFFUL
+/* CRYPTO.PR_LFSR_CTL1 */
+#define CRYPTO_PR_LFSR_CTL1_LFSR31_Pos 0UL
+#define CRYPTO_PR_LFSR_CTL1_LFSR31_Msk 0x7FFFFFFFUL
+/* CRYPTO.PR_LFSR_CTL2 */
+#define CRYPTO_PR_LFSR_CTL2_LFSR29_Pos 0UL
+#define CRYPTO_PR_LFSR_CTL2_LFSR29_Msk 0x1FFFFFFFUL
+/* CRYPTO.PR_RESULT */
+#define CRYPTO_PR_RESULT_DATA32_Pos 0UL
+#define CRYPTO_PR_RESULT_DATA32_Msk 0xFFFFFFFFUL
+/* CRYPTO.TR_CTL0 */
+#define CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV_Pos 0UL
+#define CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV_Msk 0xFFUL
+#define CRYPTO_TR_CTL0_RED_CLOCK_DIV_Pos 8UL
+#define CRYPTO_TR_CTL0_RED_CLOCK_DIV_Msk 0xFF00UL
+#define CRYPTO_TR_CTL0_INIT_DELAY_Pos 16UL
+#define CRYPTO_TR_CTL0_INIT_DELAY_Msk 0xFF0000UL
+#define CRYPTO_TR_CTL0_VON_NEUMANN_CORR_Pos 24UL
+#define CRYPTO_TR_CTL0_VON_NEUMANN_CORR_Msk 0x1000000UL
+#define CRYPTO_TR_CTL0_STOP_ON_AP_DETECT_Pos 28UL
+#define CRYPTO_TR_CTL0_STOP_ON_AP_DETECT_Msk 0x10000000UL
+#define CRYPTO_TR_CTL0_STOP_ON_RC_DETECT_Pos 29UL
+#define CRYPTO_TR_CTL0_STOP_ON_RC_DETECT_Msk 0x20000000UL
+/* CRYPTO.TR_CTL1 */
+#define CRYPTO_TR_CTL1_RO11_EN_Pos 0UL
+#define CRYPTO_TR_CTL1_RO11_EN_Msk 0x1UL
+#define CRYPTO_TR_CTL1_RO15_EN_Pos 1UL
+#define CRYPTO_TR_CTL1_RO15_EN_Msk 0x2UL
+#define CRYPTO_TR_CTL1_GARO15_EN_Pos 2UL
+#define CRYPTO_TR_CTL1_GARO15_EN_Msk 0x4UL
+#define CRYPTO_TR_CTL1_GARO31_EN_Pos 3UL
+#define CRYPTO_TR_CTL1_GARO31_EN_Msk 0x8UL
+#define CRYPTO_TR_CTL1_FIRO15_EN_Pos 4UL
+#define CRYPTO_TR_CTL1_FIRO15_EN_Msk 0x10UL
+#define CRYPTO_TR_CTL1_FIRO31_EN_Pos 5UL
+#define CRYPTO_TR_CTL1_FIRO31_EN_Msk 0x20UL
+/* CRYPTO.TR_RESULT */
+#define CRYPTO_TR_RESULT_DATA32_Pos 0UL
+#define CRYPTO_TR_RESULT_DATA32_Msk 0xFFFFFFFFUL
+/* CRYPTO.TR_GARO_CTL */
+#define CRYPTO_TR_GARO_CTL_POLYNOMIAL31_Pos 0UL
+#define CRYPTO_TR_GARO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL
+/* CRYPTO.TR_FIRO_CTL */
+#define CRYPTO_TR_FIRO_CTL_POLYNOMIAL31_Pos 0UL
+#define CRYPTO_TR_FIRO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL
+/* CRYPTO.TR_MON_CTL */
+#define CRYPTO_TR_MON_CTL_BITSTREAM_SEL_Pos 0UL
+#define CRYPTO_TR_MON_CTL_BITSTREAM_SEL_Msk 0x3UL
+/* CRYPTO.TR_MON_CMD */
+#define CRYPTO_TR_MON_CMD_START_AP_Pos 0UL
+#define CRYPTO_TR_MON_CMD_START_AP_Msk 0x1UL
+#define CRYPTO_TR_MON_CMD_START_RC_Pos 1UL
+#define CRYPTO_TR_MON_CMD_START_RC_Msk 0x2UL
+/* CRYPTO.TR_MON_RC_CTL */
+#define CRYPTO_TR_MON_RC_CTL_CUTOFF_COUNT8_Pos 0UL
+#define CRYPTO_TR_MON_RC_CTL_CUTOFF_COUNT8_Msk 0xFFUL
+/* CRYPTO.TR_MON_RC_STATUS0 */
+#define CRYPTO_TR_MON_RC_STATUS0_BIT_Pos 0UL
+#define CRYPTO_TR_MON_RC_STATUS0_BIT_Msk 0x1UL
+/* CRYPTO.TR_MON_RC_STATUS1 */
+#define CRYPTO_TR_MON_RC_STATUS1_REP_COUNT_Pos 0UL
+#define CRYPTO_TR_MON_RC_STATUS1_REP_COUNT_Msk 0xFFUL
+/* CRYPTO.TR_MON_AP_CTL */
+#define CRYPTO_TR_MON_AP_CTL_CUTOFF_COUNT16_Pos 0UL
+#define CRYPTO_TR_MON_AP_CTL_CUTOFF_COUNT16_Msk 0xFFFFUL
+#define CRYPTO_TR_MON_AP_CTL_WINDOW_SIZE_Pos 16UL
+#define CRYPTO_TR_MON_AP_CTL_WINDOW_SIZE_Msk 0xFFFF0000UL
+/* CRYPTO.TR_MON_AP_STATUS0 */
+#define CRYPTO_TR_MON_AP_STATUS0_BIT_Pos 0UL
+#define CRYPTO_TR_MON_AP_STATUS0_BIT_Msk 0x1UL
+/* CRYPTO.TR_MON_AP_STATUS1 */
+#define CRYPTO_TR_MON_AP_STATUS1_OCC_COUNT_Pos 0UL
+#define CRYPTO_TR_MON_AP_STATUS1_OCC_COUNT_Msk 0xFFFFUL
+#define CRYPTO_TR_MON_AP_STATUS1_WINDOW_INDEX_Pos 16UL
+#define CRYPTO_TR_MON_AP_STATUS1_WINDOW_INDEX_Msk 0xFFFF0000UL
+/* CRYPTO.SHA_CTL */
+#define CRYPTO_SHA_CTL_MODE_Pos 0UL
+#define CRYPTO_SHA_CTL_MODE_Msk 0x7UL
+/* CRYPTO.CRC_CTL */
+#define CRYPTO_CRC_CTL_DATA_REVERSE_Pos 0UL
+#define CRYPTO_CRC_CTL_DATA_REVERSE_Msk 0x1UL
+#define CRYPTO_CRC_CTL_REM_REVERSE_Pos 8UL
+#define CRYPTO_CRC_CTL_REM_REVERSE_Msk 0x100UL
+/* CRYPTO.CRC_DATA_CTL */
+#define CRYPTO_CRC_DATA_CTL_DATA_XOR_Pos 0UL
+#define CRYPTO_CRC_DATA_CTL_DATA_XOR_Msk 0xFFUL
+/* CRYPTO.CRC_POL_CTL */
+#define CRYPTO_CRC_POL_CTL_POLYNOMIAL_Pos 0UL
+#define CRYPTO_CRC_POL_CTL_POLYNOMIAL_Msk 0xFFFFFFFFUL
+/* CRYPTO.CRC_LFSR_CTL */
+#define CRYPTO_CRC_LFSR_CTL_LFSR32_Pos 0UL
+#define CRYPTO_CRC_LFSR_CTL_LFSR32_Msk 0xFFFFFFFFUL
+/* CRYPTO.CRC_REM_CTL */
+#define CRYPTO_CRC_REM_CTL_REM_XOR_Pos 0UL
+#define CRYPTO_CRC_REM_CTL_REM_XOR_Msk 0xFFFFFFFFUL
+/* CRYPTO.CRC_REM_RESULT */
+#define CRYPTO_CRC_REM_RESULT_REM_Pos 0UL
+#define CRYPTO_CRC_REM_RESULT_REM_Msk 0xFFFFFFFFUL
+/* CRYPTO.VU_CTL0 */
+#define CRYPTO_VU_CTL0_ALWAYS_EXECUTE_Pos 0UL
+#define CRYPTO_VU_CTL0_ALWAYS_EXECUTE_Msk 0x1UL
+/* CRYPTO.VU_CTL1 */
+#define CRYPTO_VU_CTL1_ADDR_Pos 14UL
+#define CRYPTO_VU_CTL1_ADDR_Msk 0xFFFFC000UL
+/* CRYPTO.VU_STATUS */
+#define CRYPTO_VU_STATUS_CARRY_Pos 0UL
+#define CRYPTO_VU_STATUS_CARRY_Msk 0x1UL
+#define CRYPTO_VU_STATUS_EVEN_Pos 1UL
+#define CRYPTO_VU_STATUS_EVEN_Msk 0x2UL
+#define CRYPTO_VU_STATUS_ZERO_Pos 2UL
+#define CRYPTO_VU_STATUS_ZERO_Msk 0x4UL
+#define CRYPTO_VU_STATUS_ONE_Pos 3UL
+#define CRYPTO_VU_STATUS_ONE_Msk 0x8UL
+/* CRYPTO.INTR */
+#define CRYPTO_INTR_INSTR_FF_LEVEL_Pos 0UL
+#define CRYPTO_INTR_INSTR_FF_LEVEL_Msk 0x1UL
+#define CRYPTO_INTR_INSTR_FF_OVERFLOW_Pos 1UL
+#define CRYPTO_INTR_INSTR_FF_OVERFLOW_Msk 0x2UL
+#define CRYPTO_INTR_TR_INITIALIZED_Pos 2UL
+#define CRYPTO_INTR_TR_INITIALIZED_Msk 0x4UL
+#define CRYPTO_INTR_TR_DATA_AVAILABLE_Pos 3UL
+#define CRYPTO_INTR_TR_DATA_AVAILABLE_Msk 0x8UL
+#define CRYPTO_INTR_PR_DATA_AVAILABLE_Pos 4UL
+#define CRYPTO_INTR_PR_DATA_AVAILABLE_Msk 0x10UL
+#define CRYPTO_INTR_INSTR_OPC_ERROR_Pos 16UL
+#define CRYPTO_INTR_INSTR_OPC_ERROR_Msk 0x10000UL
+#define CRYPTO_INTR_INSTR_CC_ERROR_Pos 17UL
+#define CRYPTO_INTR_INSTR_CC_ERROR_Msk 0x20000UL
+#define CRYPTO_INTR_BUS_ERROR_Pos 18UL
+#define CRYPTO_INTR_BUS_ERROR_Msk 0x40000UL
+#define CRYPTO_INTR_TR_AP_DETECT_ERROR_Pos 19UL
+#define CRYPTO_INTR_TR_AP_DETECT_ERROR_Msk 0x80000UL
+#define CRYPTO_INTR_TR_RC_DETECT_ERROR_Pos 20UL
+#define CRYPTO_INTR_TR_RC_DETECT_ERROR_Msk 0x100000UL
+/* CRYPTO.INTR_SET */
+#define CRYPTO_INTR_SET_INSTR_FF_LEVEL_Pos 0UL
+#define CRYPTO_INTR_SET_INSTR_FF_LEVEL_Msk 0x1UL
+#define CRYPTO_INTR_SET_INSTR_FF_OVERFLOW_Pos 1UL
+#define CRYPTO_INTR_SET_INSTR_FF_OVERFLOW_Msk 0x2UL
+#define CRYPTO_INTR_SET_TR_INITIALIZED_Pos 2UL
+#define CRYPTO_INTR_SET_TR_INITIALIZED_Msk 0x4UL
+#define CRYPTO_INTR_SET_TR_DATA_AVAILABLE_Pos 3UL
+#define CRYPTO_INTR_SET_TR_DATA_AVAILABLE_Msk 0x8UL
+#define CRYPTO_INTR_SET_PR_DATA_AVAILABLE_Pos 4UL
+#define CRYPTO_INTR_SET_PR_DATA_AVAILABLE_Msk 0x10UL
+#define CRYPTO_INTR_SET_INSTR_OPC_ERROR_Pos 16UL
+#define CRYPTO_INTR_SET_INSTR_OPC_ERROR_Msk 0x10000UL
+#define CRYPTO_INTR_SET_INSTR_CC_ERROR_Pos 17UL
+#define CRYPTO_INTR_SET_INSTR_CC_ERROR_Msk 0x20000UL
+#define CRYPTO_INTR_SET_BUS_ERROR_Pos 18UL
+#define CRYPTO_INTR_SET_BUS_ERROR_Msk 0x40000UL
+#define CRYPTO_INTR_SET_TR_AP_DETECT_ERROR_Pos 19UL
+#define CRYPTO_INTR_SET_TR_AP_DETECT_ERROR_Msk 0x80000UL
+#define CRYPTO_INTR_SET_TR_RC_DETECT_ERROR_Pos 20UL
+#define CRYPTO_INTR_SET_TR_RC_DETECT_ERROR_Msk 0x100000UL
+/* CRYPTO.INTR_MASK */
+#define CRYPTO_INTR_MASK_INSTR_FF_LEVEL_Pos 0UL
+#define CRYPTO_INTR_MASK_INSTR_FF_LEVEL_Msk 0x1UL
+#define CRYPTO_INTR_MASK_INSTR_FF_OVERFLOW_Pos 1UL
+#define CRYPTO_INTR_MASK_INSTR_FF_OVERFLOW_Msk 0x2UL
+#define CRYPTO_INTR_MASK_TR_INITIALIZED_Pos 2UL
+#define CRYPTO_INTR_MASK_TR_INITIALIZED_Msk 0x4UL
+#define CRYPTO_INTR_MASK_TR_DATA_AVAILABLE_Pos 3UL
+#define CRYPTO_INTR_MASK_TR_DATA_AVAILABLE_Msk 0x8UL
+#define CRYPTO_INTR_MASK_PR_DATA_AVAILABLE_Pos 4UL
+#define CRYPTO_INTR_MASK_PR_DATA_AVAILABLE_Msk 0x10UL
+#define CRYPTO_INTR_MASK_INSTR_OPC_ERROR_Pos 16UL
+#define CRYPTO_INTR_MASK_INSTR_OPC_ERROR_Msk 0x10000UL
+#define CRYPTO_INTR_MASK_INSTR_CC_ERROR_Pos 17UL
+#define CRYPTO_INTR_MASK_INSTR_CC_ERROR_Msk 0x20000UL
+#define CRYPTO_INTR_MASK_BUS_ERROR_Pos 18UL
+#define CRYPTO_INTR_MASK_BUS_ERROR_Msk 0x40000UL
+#define CRYPTO_INTR_MASK_TR_AP_DETECT_ERROR_Pos 19UL
+#define CRYPTO_INTR_MASK_TR_AP_DETECT_ERROR_Msk 0x80000UL
+#define CRYPTO_INTR_MASK_TR_RC_DETECT_ERROR_Pos 20UL
+#define CRYPTO_INTR_MASK_TR_RC_DETECT_ERROR_Msk 0x100000UL
+/* CRYPTO.INTR_MASKED */
+#define CRYPTO_INTR_MASKED_INSTR_FF_LEVEL_Pos 0UL
+#define CRYPTO_INTR_MASKED_INSTR_FF_LEVEL_Msk 0x1UL
+#define CRYPTO_INTR_MASKED_INSTR_FF_OVERFLOW_Pos 1UL
+#define CRYPTO_INTR_MASKED_INSTR_FF_OVERFLOW_Msk 0x2UL
+#define CRYPTO_INTR_MASKED_TR_INITIALIZED_Pos 2UL
+#define CRYPTO_INTR_MASKED_TR_INITIALIZED_Msk 0x4UL
+#define CRYPTO_INTR_MASKED_TR_DATA_AVAILABLE_Pos 3UL
+#define CRYPTO_INTR_MASKED_TR_DATA_AVAILABLE_Msk 0x8UL
+#define CRYPTO_INTR_MASKED_PR_DATA_AVAILABLE_Pos 4UL
+#define CRYPTO_INTR_MASKED_PR_DATA_AVAILABLE_Msk 0x10UL
+#define CRYPTO_INTR_MASKED_INSTR_OPC_ERROR_Pos 16UL
+#define CRYPTO_INTR_MASKED_INSTR_OPC_ERROR_Msk 0x10000UL
+#define CRYPTO_INTR_MASKED_INSTR_CC_ERROR_Pos 17UL
+#define CRYPTO_INTR_MASKED_INSTR_CC_ERROR_Msk 0x20000UL
+#define CRYPTO_INTR_MASKED_BUS_ERROR_Pos 18UL
+#define CRYPTO_INTR_MASKED_BUS_ERROR_Msk 0x40000UL
+#define CRYPTO_INTR_MASKED_TR_AP_DETECT_ERROR_Pos 19UL
+#define CRYPTO_INTR_MASKED_TR_AP_DETECT_ERROR_Msk 0x80000UL
+#define CRYPTO_INTR_MASKED_TR_RC_DETECT_ERROR_Pos 20UL
+#define CRYPTO_INTR_MASKED_TR_RC_DETECT_ERROR_Msk 0x100000UL
+/* CRYPTO.MEM_BUFF */
+#define CRYPTO_MEM_BUFF_DATA32_Pos 0UL
+#define CRYPTO_MEM_BUFF_DATA32_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_CRYPTO_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_crypto_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_crypto_v2.h
new file mode 100644
index 0000000000..1f4429b023
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_crypto_v2.h
@@ -0,0 +1,463 @@
+/***************************************************************************//**
+* \file cyip_crypto_v2.h
+*
+* \brief
+* CRYPTO IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_CRYPTO_V2_H_
+#define _CYIP_CRYPTO_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* CRYPTO
+*******************************************************************************/
+
+#define CRYPTO_V2_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Cryptography component (CRYPTO)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t RAM_PWR_CTL; /*!< 0x00000008 SRAM power control */
+ __IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x0000000C SRAM power delay control */
+ __IOM uint32_t ECC_CTL; /*!< 0x00000010 ECC control */
+ __IM uint32_t RESERVED1[3];
+ __IM uint32_t ERROR_STATUS0; /*!< 0x00000020 Error status 0 */
+ __IOM uint32_t ERROR_STATUS1; /*!< 0x00000024 Error status 1 */
+ __IM uint32_t RESERVED2[54];
+ __IOM uint32_t INTR; /*!< 0x00000100 Interrupt register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000104 Interrupt set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000108 Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000010C Interrupt masked register */
+ __IM uint32_t RESERVED3[60];
+ __IOM uint32_t PR_LFSR_CTL0; /*!< 0x00000200 Pseudo random LFSR control 0 */
+ __IOM uint32_t PR_LFSR_CTL1; /*!< 0x00000204 Pseudo random LFSR control 1 */
+ __IOM uint32_t PR_LFSR_CTL2; /*!< 0x00000208 Pseudo random LFSR control 2 */
+ __IOM uint32_t PR_MAX_CTL; /*!< 0x0000020C Pseudo random maximum control */
+ __IOM uint32_t PR_CMD; /*!< 0x00000210 Pseudo random command */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t PR_RESULT; /*!< 0x00000218 Pseudo random result */
+ __IM uint32_t RESERVED5[25];
+ __IOM uint32_t TR_CTL0; /*!< 0x00000280 True random control 0 */
+ __IOM uint32_t TR_CTL1; /*!< 0x00000284 True random control 1 */
+ __IOM uint32_t TR_CTL2; /*!< 0x00000288 True random control 2 */
+ __IM uint32_t TR_STATUS; /*!< 0x0000028C True random status */
+ __IOM uint32_t TR_CMD; /*!< 0x00000290 True random command */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t TR_RESULT; /*!< 0x00000298 True random result */
+ __IM uint32_t RESERVED7;
+ __IOM uint32_t TR_GARO_CTL; /*!< 0x000002A0 True random GARO control */
+ __IOM uint32_t TR_FIRO_CTL; /*!< 0x000002A4 True random FIRO control */
+ __IM uint32_t RESERVED8[6];
+ __IOM uint32_t TR_MON_CTL; /*!< 0x000002C0 True random monitor control */
+ __IM uint32_t RESERVED9;
+ __IOM uint32_t TR_MON_CMD; /*!< 0x000002C8 True random monitor command */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t TR_MON_RC_CTL; /*!< 0x000002D0 True random monitor RC control */
+ __IM uint32_t RESERVED11;
+ __IM uint32_t TR_MON_RC_STATUS0; /*!< 0x000002D8 True random monitor RC status 0 */
+ __IM uint32_t TR_MON_RC_STATUS1; /*!< 0x000002DC True random monitor RC status 1 */
+ __IOM uint32_t TR_MON_AP_CTL; /*!< 0x000002E0 True random monitor AP control */
+ __IM uint32_t RESERVED12;
+ __IM uint32_t TR_MON_AP_STATUS0; /*!< 0x000002E8 True random monitor AP status 0 */
+ __IM uint32_t TR_MON_AP_STATUS1; /*!< 0x000002EC True random monitor AP status 1 */
+ __IM uint32_t RESERVED13[837];
+ __IM uint32_t STATUS; /*!< 0x00001004 Status */
+ __IM uint32_t RESERVED14[14];
+ __IOM uint32_t INSTR_FF_CTL; /*!< 0x00001040 Instruction FIFO control */
+ __IM uint32_t INSTR_FF_STATUS; /*!< 0x00001044 Instruction FIFO status */
+ __OM uint32_t INSTR_FF_WR; /*!< 0x00001048 Instruction FIFO write */
+ __IM uint32_t RESERVED15[29];
+ __IM uint32_t LOAD0_FF_STATUS; /*!< 0x000010C0 Load 0 FIFO status */
+ __IM uint32_t RESERVED16[3];
+ __IM uint32_t LOAD1_FF_STATUS; /*!< 0x000010D0 Load 1 FIFO status */
+ __IM uint32_t RESERVED17[7];
+ __IM uint32_t STORE_FF_STATUS; /*!< 0x000010F0 Store FIFO status */
+ __IM uint32_t RESERVED18[3];
+ __IOM uint32_t AES_CTL; /*!< 0x00001100 AES control */
+ __IM uint32_t RESERVED19[31];
+ __IOM uint32_t RESULT; /*!< 0x00001180 Result */
+ __IM uint32_t RESERVED20[159];
+ __IOM uint32_t CRC_CTL; /*!< 0x00001400 CRC control */
+ __IM uint32_t RESERVED21[3];
+ __IOM uint32_t CRC_DATA_CTL; /*!< 0x00001410 CRC data control */
+ __IM uint32_t RESERVED22[3];
+ __IOM uint32_t CRC_POL_CTL; /*!< 0x00001420 CRC polynomial control */
+ __IM uint32_t RESERVED23[7];
+ __IOM uint32_t CRC_REM_CTL; /*!< 0x00001440 CRC remainder control */
+ __IM uint32_t RESERVED24;
+ __IM uint32_t CRC_REM_RESULT; /*!< 0x00001448 CRC remainder result */
+ __IM uint32_t RESERVED25[13];
+ __IOM uint32_t VU_CTL0; /*!< 0x00001480 Vector unit control 0 */
+ __IOM uint32_t VU_CTL1; /*!< 0x00001484 Vector unit control 1 */
+ __IOM uint32_t VU_CTL2; /*!< 0x00001488 Vector unit control 2 */
+ __IM uint32_t RESERVED26;
+ __IM uint32_t VU_STATUS; /*!< 0x00001490 Vector unit status */
+ __IM uint32_t RESERVED27[11];
+ __IM uint32_t VU_RF_DATA[16]; /*!< 0x000014C0 Vector unit register-file */
+ __IM uint32_t RESERVED28[704];
+ __IOM uint32_t DEV_KEY_ADDR0_CTL; /*!< 0x00002000 Device key address 0 control */
+ __IOM uint32_t DEV_KEY_ADDR0; /*!< 0x00002004 Device key address 0 */
+ __IM uint32_t RESERVED29[6];
+ __IOM uint32_t DEV_KEY_ADDR1_CTL; /*!< 0x00002020 Device key address 1 control */
+ __IOM uint32_t DEV_KEY_ADDR1; /*!< 0x00002024 Device key address 1 control */
+ __IM uint32_t RESERVED30[22];
+ __IM uint32_t DEV_KEY_STATUS; /*!< 0x00002080 Device key status */
+ __IM uint32_t RESERVED31[31];
+ __IOM uint32_t DEV_KEY_CTL0; /*!< 0x00002100 Device key control 0 */
+ __IM uint32_t RESERVED32[7];
+ __IOM uint32_t DEV_KEY_CTL1; /*!< 0x00002120 Device key control 1 */
+ __IM uint32_t RESERVED33[6071];
+ __IOM uint32_t MEM_BUFF[8192]; /*!< 0x00008000 Memory buffer */
+} CRYPTO_V2_Type; /*!< Size = 65536 (0x10000) */
+
+
+/* CRYPTO.CTL */
+#define CRYPTO_V2_CTL_P_Pos 0UL
+#define CRYPTO_V2_CTL_P_Msk 0x1UL
+#define CRYPTO_V2_CTL_NS_Pos 1UL
+#define CRYPTO_V2_CTL_NS_Msk 0x2UL
+#define CRYPTO_V2_CTL_PC_Pos 4UL
+#define CRYPTO_V2_CTL_PC_Msk 0xF0UL
+#define CRYPTO_V2_CTL_ECC_EN_Pos 16UL
+#define CRYPTO_V2_CTL_ECC_EN_Msk 0x10000UL
+#define CRYPTO_V2_CTL_ECC_INJ_EN_Pos 17UL
+#define CRYPTO_V2_CTL_ECC_INJ_EN_Msk 0x20000UL
+#define CRYPTO_V2_CTL_ENABLED_Pos 31UL
+#define CRYPTO_V2_CTL_ENABLED_Msk 0x80000000UL
+/* CRYPTO.RAM_PWR_CTL */
+#define CRYPTO_V2_RAM_PWR_CTL_PWR_MODE_Pos 0UL
+#define CRYPTO_V2_RAM_PWR_CTL_PWR_MODE_Msk 0x3UL
+/* CRYPTO.RAM_PWR_DELAY_CTL */
+#define CRYPTO_V2_RAM_PWR_DELAY_CTL_UP_Pos 0UL
+#define CRYPTO_V2_RAM_PWR_DELAY_CTL_UP_Msk 0x3FFUL
+/* CRYPTO.ECC_CTL */
+#define CRYPTO_V2_ECC_CTL_WORD_ADDR_Pos 0UL
+#define CRYPTO_V2_ECC_CTL_WORD_ADDR_Msk 0x1FFFUL
+#define CRYPTO_V2_ECC_CTL_PARITY_Pos 25UL
+#define CRYPTO_V2_ECC_CTL_PARITY_Msk 0xFE000000UL
+/* CRYPTO.ERROR_STATUS0 */
+#define CRYPTO_V2_ERROR_STATUS0_DATA32_Pos 0UL
+#define CRYPTO_V2_ERROR_STATUS0_DATA32_Msk 0xFFFFFFFFUL
+/* CRYPTO.ERROR_STATUS1 */
+#define CRYPTO_V2_ERROR_STATUS1_DATA24_Pos 0UL
+#define CRYPTO_V2_ERROR_STATUS1_DATA24_Msk 0xFFFFFFUL
+#define CRYPTO_V2_ERROR_STATUS1_IDX_Pos 24UL
+#define CRYPTO_V2_ERROR_STATUS1_IDX_Msk 0x7000000UL
+#define CRYPTO_V2_ERROR_STATUS1_VALID_Pos 31UL
+#define CRYPTO_V2_ERROR_STATUS1_VALID_Msk 0x80000000UL
+/* CRYPTO.INTR */
+#define CRYPTO_V2_INTR_INSTR_FF_LEVEL_Pos 0UL
+#define CRYPTO_V2_INTR_INSTR_FF_LEVEL_Msk 0x1UL
+#define CRYPTO_V2_INTR_INSTR_FF_OVERFLOW_Pos 1UL
+#define CRYPTO_V2_INTR_INSTR_FF_OVERFLOW_Msk 0x2UL
+#define CRYPTO_V2_INTR_TR_INITIALIZED_Pos 2UL
+#define CRYPTO_V2_INTR_TR_INITIALIZED_Msk 0x4UL
+#define CRYPTO_V2_INTR_TR_DATA_AVAILABLE_Pos 3UL
+#define CRYPTO_V2_INTR_TR_DATA_AVAILABLE_Msk 0x8UL
+#define CRYPTO_V2_INTR_PR_DATA_AVAILABLE_Pos 4UL
+#define CRYPTO_V2_INTR_PR_DATA_AVAILABLE_Msk 0x10UL
+#define CRYPTO_V2_INTR_INSTR_OPC_ERROR_Pos 16UL
+#define CRYPTO_V2_INTR_INSTR_OPC_ERROR_Msk 0x10000UL
+#define CRYPTO_V2_INTR_INSTR_CC_ERROR_Pos 17UL
+#define CRYPTO_V2_INTR_INSTR_CC_ERROR_Msk 0x20000UL
+#define CRYPTO_V2_INTR_BUS_ERROR_Pos 18UL
+#define CRYPTO_V2_INTR_BUS_ERROR_Msk 0x40000UL
+#define CRYPTO_V2_INTR_TR_AP_DETECT_ERROR_Pos 19UL
+#define CRYPTO_V2_INTR_TR_AP_DETECT_ERROR_Msk 0x80000UL
+#define CRYPTO_V2_INTR_TR_RC_DETECT_ERROR_Pos 20UL
+#define CRYPTO_V2_INTR_TR_RC_DETECT_ERROR_Msk 0x100000UL
+#define CRYPTO_V2_INTR_INSTR_DEV_KEY_ERROR_Pos 21UL
+#define CRYPTO_V2_INTR_INSTR_DEV_KEY_ERROR_Msk 0x200000UL
+/* CRYPTO.INTR_SET */
+#define CRYPTO_V2_INTR_SET_INSTR_FF_LEVEL_Pos 0UL
+#define CRYPTO_V2_INTR_SET_INSTR_FF_LEVEL_Msk 0x1UL
+#define CRYPTO_V2_INTR_SET_INSTR_FF_OVERFLOW_Pos 1UL
+#define CRYPTO_V2_INTR_SET_INSTR_FF_OVERFLOW_Msk 0x2UL
+#define CRYPTO_V2_INTR_SET_TR_INITIALIZED_Pos 2UL
+#define CRYPTO_V2_INTR_SET_TR_INITIALIZED_Msk 0x4UL
+#define CRYPTO_V2_INTR_SET_TR_DATA_AVAILABLE_Pos 3UL
+#define CRYPTO_V2_INTR_SET_TR_DATA_AVAILABLE_Msk 0x8UL
+#define CRYPTO_V2_INTR_SET_PR_DATA_AVAILABLE_Pos 4UL
+#define CRYPTO_V2_INTR_SET_PR_DATA_AVAILABLE_Msk 0x10UL
+#define CRYPTO_V2_INTR_SET_INSTR_OPC_ERROR_Pos 16UL
+#define CRYPTO_V2_INTR_SET_INSTR_OPC_ERROR_Msk 0x10000UL
+#define CRYPTO_V2_INTR_SET_INSTR_CC_ERROR_Pos 17UL
+#define CRYPTO_V2_INTR_SET_INSTR_CC_ERROR_Msk 0x20000UL
+#define CRYPTO_V2_INTR_SET_BUS_ERROR_Pos 18UL
+#define CRYPTO_V2_INTR_SET_BUS_ERROR_Msk 0x40000UL
+#define CRYPTO_V2_INTR_SET_TR_AP_DETECT_ERROR_Pos 19UL
+#define CRYPTO_V2_INTR_SET_TR_AP_DETECT_ERROR_Msk 0x80000UL
+#define CRYPTO_V2_INTR_SET_TR_RC_DETECT_ERROR_Pos 20UL
+#define CRYPTO_V2_INTR_SET_TR_RC_DETECT_ERROR_Msk 0x100000UL
+#define CRYPTO_V2_INTR_SET_INSTR_DEV_KEY_ERROR_Pos 21UL
+#define CRYPTO_V2_INTR_SET_INSTR_DEV_KEY_ERROR_Msk 0x200000UL
+/* CRYPTO.INTR_MASK */
+#define CRYPTO_V2_INTR_MASK_INSTR_FF_LEVEL_Pos 0UL
+#define CRYPTO_V2_INTR_MASK_INSTR_FF_LEVEL_Msk 0x1UL
+#define CRYPTO_V2_INTR_MASK_INSTR_FF_OVERFLOW_Pos 1UL
+#define CRYPTO_V2_INTR_MASK_INSTR_FF_OVERFLOW_Msk 0x2UL
+#define CRYPTO_V2_INTR_MASK_TR_INITIALIZED_Pos 2UL
+#define CRYPTO_V2_INTR_MASK_TR_INITIALIZED_Msk 0x4UL
+#define CRYPTO_V2_INTR_MASK_TR_DATA_AVAILABLE_Pos 3UL
+#define CRYPTO_V2_INTR_MASK_TR_DATA_AVAILABLE_Msk 0x8UL
+#define CRYPTO_V2_INTR_MASK_PR_DATA_AVAILABLE_Pos 4UL
+#define CRYPTO_V2_INTR_MASK_PR_DATA_AVAILABLE_Msk 0x10UL
+#define CRYPTO_V2_INTR_MASK_INSTR_OPC_ERROR_Pos 16UL
+#define CRYPTO_V2_INTR_MASK_INSTR_OPC_ERROR_Msk 0x10000UL
+#define CRYPTO_V2_INTR_MASK_INSTR_CC_ERROR_Pos 17UL
+#define CRYPTO_V2_INTR_MASK_INSTR_CC_ERROR_Msk 0x20000UL
+#define CRYPTO_V2_INTR_MASK_BUS_ERROR_Pos 18UL
+#define CRYPTO_V2_INTR_MASK_BUS_ERROR_Msk 0x40000UL
+#define CRYPTO_V2_INTR_MASK_TR_AP_DETECT_ERROR_Pos 19UL
+#define CRYPTO_V2_INTR_MASK_TR_AP_DETECT_ERROR_Msk 0x80000UL
+#define CRYPTO_V2_INTR_MASK_TR_RC_DETECT_ERROR_Pos 20UL
+#define CRYPTO_V2_INTR_MASK_TR_RC_DETECT_ERROR_Msk 0x100000UL
+#define CRYPTO_V2_INTR_MASK_INSTR_DEV_KEY_ERROR_Pos 21UL
+#define CRYPTO_V2_INTR_MASK_INSTR_DEV_KEY_ERROR_Msk 0x200000UL
+/* CRYPTO.INTR_MASKED */
+#define CRYPTO_V2_INTR_MASKED_INSTR_FF_LEVEL_Pos 0UL
+#define CRYPTO_V2_INTR_MASKED_INSTR_FF_LEVEL_Msk 0x1UL
+#define CRYPTO_V2_INTR_MASKED_INSTR_FF_OVERFLOW_Pos 1UL
+#define CRYPTO_V2_INTR_MASKED_INSTR_FF_OVERFLOW_Msk 0x2UL
+#define CRYPTO_V2_INTR_MASKED_TR_INITIALIZED_Pos 2UL
+#define CRYPTO_V2_INTR_MASKED_TR_INITIALIZED_Msk 0x4UL
+#define CRYPTO_V2_INTR_MASKED_TR_DATA_AVAILABLE_Pos 3UL
+#define CRYPTO_V2_INTR_MASKED_TR_DATA_AVAILABLE_Msk 0x8UL
+#define CRYPTO_V2_INTR_MASKED_PR_DATA_AVAILABLE_Pos 4UL
+#define CRYPTO_V2_INTR_MASKED_PR_DATA_AVAILABLE_Msk 0x10UL
+#define CRYPTO_V2_INTR_MASKED_INSTR_OPC_ERROR_Pos 16UL
+#define CRYPTO_V2_INTR_MASKED_INSTR_OPC_ERROR_Msk 0x10000UL
+#define CRYPTO_V2_INTR_MASKED_INSTR_CC_ERROR_Pos 17UL
+#define CRYPTO_V2_INTR_MASKED_INSTR_CC_ERROR_Msk 0x20000UL
+#define CRYPTO_V2_INTR_MASKED_BUS_ERROR_Pos 18UL
+#define CRYPTO_V2_INTR_MASKED_BUS_ERROR_Msk 0x40000UL
+#define CRYPTO_V2_INTR_MASKED_TR_AP_DETECT_ERROR_Pos 19UL
+#define CRYPTO_V2_INTR_MASKED_TR_AP_DETECT_ERROR_Msk 0x80000UL
+#define CRYPTO_V2_INTR_MASKED_TR_RC_DETECT_ERROR_Pos 20UL
+#define CRYPTO_V2_INTR_MASKED_TR_RC_DETECT_ERROR_Msk 0x100000UL
+#define CRYPTO_V2_INTR_MASKED_INSTR_DEV_KEY_ERROR_Pos 21UL
+#define CRYPTO_V2_INTR_MASKED_INSTR_DEV_KEY_ERROR_Msk 0x200000UL
+/* CRYPTO.PR_LFSR_CTL0 */
+#define CRYPTO_V2_PR_LFSR_CTL0_LFSR32_Pos 0UL
+#define CRYPTO_V2_PR_LFSR_CTL0_LFSR32_Msk 0xFFFFFFFFUL
+/* CRYPTO.PR_LFSR_CTL1 */
+#define CRYPTO_V2_PR_LFSR_CTL1_LFSR31_Pos 0UL
+#define CRYPTO_V2_PR_LFSR_CTL1_LFSR31_Msk 0x7FFFFFFFUL
+/* CRYPTO.PR_LFSR_CTL2 */
+#define CRYPTO_V2_PR_LFSR_CTL2_LFSR29_Pos 0UL
+#define CRYPTO_V2_PR_LFSR_CTL2_LFSR29_Msk 0x1FFFFFFFUL
+/* CRYPTO.PR_MAX_CTL */
+#define CRYPTO_V2_PR_MAX_CTL_DATA32_Pos 0UL
+#define CRYPTO_V2_PR_MAX_CTL_DATA32_Msk 0xFFFFFFFFUL
+/* CRYPTO.PR_CMD */
+#define CRYPTO_V2_PR_CMD_START_Pos 0UL
+#define CRYPTO_V2_PR_CMD_START_Msk 0x1UL
+/* CRYPTO.PR_RESULT */
+#define CRYPTO_V2_PR_RESULT_DATA32_Pos 0UL
+#define CRYPTO_V2_PR_RESULT_DATA32_Msk 0xFFFFFFFFUL
+/* CRYPTO.TR_CTL0 */
+#define CRYPTO_V2_TR_CTL0_SAMPLE_CLOCK_DIV_Pos 0UL
+#define CRYPTO_V2_TR_CTL0_SAMPLE_CLOCK_DIV_Msk 0xFFUL
+#define CRYPTO_V2_TR_CTL0_RED_CLOCK_DIV_Pos 8UL
+#define CRYPTO_V2_TR_CTL0_RED_CLOCK_DIV_Msk 0xFF00UL
+#define CRYPTO_V2_TR_CTL0_INIT_DELAY_Pos 16UL
+#define CRYPTO_V2_TR_CTL0_INIT_DELAY_Msk 0xFF0000UL
+#define CRYPTO_V2_TR_CTL0_VON_NEUMANN_CORR_Pos 24UL
+#define CRYPTO_V2_TR_CTL0_VON_NEUMANN_CORR_Msk 0x1000000UL
+#define CRYPTO_V2_TR_CTL0_STOP_ON_AP_DETECT_Pos 28UL
+#define CRYPTO_V2_TR_CTL0_STOP_ON_AP_DETECT_Msk 0x10000000UL
+#define CRYPTO_V2_TR_CTL0_STOP_ON_RC_DETECT_Pos 29UL
+#define CRYPTO_V2_TR_CTL0_STOP_ON_RC_DETECT_Msk 0x20000000UL
+/* CRYPTO.TR_CTL1 */
+#define CRYPTO_V2_TR_CTL1_RO11_EN_Pos 0UL
+#define CRYPTO_V2_TR_CTL1_RO11_EN_Msk 0x1UL
+#define CRYPTO_V2_TR_CTL1_RO15_EN_Pos 1UL
+#define CRYPTO_V2_TR_CTL1_RO15_EN_Msk 0x2UL
+#define CRYPTO_V2_TR_CTL1_GARO15_EN_Pos 2UL
+#define CRYPTO_V2_TR_CTL1_GARO15_EN_Msk 0x4UL
+#define CRYPTO_V2_TR_CTL1_GARO31_EN_Pos 3UL
+#define CRYPTO_V2_TR_CTL1_GARO31_EN_Msk 0x8UL
+#define CRYPTO_V2_TR_CTL1_FIRO15_EN_Pos 4UL
+#define CRYPTO_V2_TR_CTL1_FIRO15_EN_Msk 0x10UL
+#define CRYPTO_V2_TR_CTL1_FIRO31_EN_Pos 5UL
+#define CRYPTO_V2_TR_CTL1_FIRO31_EN_Msk 0x20UL
+/* CRYPTO.TR_CTL2 */
+#define CRYPTO_V2_TR_CTL2_SIZE_Pos 0UL
+#define CRYPTO_V2_TR_CTL2_SIZE_Msk 0x3FUL
+/* CRYPTO.TR_STATUS */
+#define CRYPTO_V2_TR_STATUS_INITIALIZED_Pos 0UL
+#define CRYPTO_V2_TR_STATUS_INITIALIZED_Msk 0x1UL
+/* CRYPTO.TR_CMD */
+#define CRYPTO_V2_TR_CMD_START_Pos 0UL
+#define CRYPTO_V2_TR_CMD_START_Msk 0x1UL
+/* CRYPTO.TR_RESULT */
+#define CRYPTO_V2_TR_RESULT_DATA32_Pos 0UL
+#define CRYPTO_V2_TR_RESULT_DATA32_Msk 0xFFFFFFFFUL
+/* CRYPTO.TR_GARO_CTL */
+#define CRYPTO_V2_TR_GARO_CTL_POLYNOMIAL31_Pos 0UL
+#define CRYPTO_V2_TR_GARO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL
+/* CRYPTO.TR_FIRO_CTL */
+#define CRYPTO_V2_TR_FIRO_CTL_POLYNOMIAL31_Pos 0UL
+#define CRYPTO_V2_TR_FIRO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL
+/* CRYPTO.TR_MON_CTL */
+#define CRYPTO_V2_TR_MON_CTL_BITSTREAM_SEL_Pos 0UL
+#define CRYPTO_V2_TR_MON_CTL_BITSTREAM_SEL_Msk 0x3UL
+/* CRYPTO.TR_MON_CMD */
+#define CRYPTO_V2_TR_MON_CMD_START_AP_Pos 0UL
+#define CRYPTO_V2_TR_MON_CMD_START_AP_Msk 0x1UL
+#define CRYPTO_V2_TR_MON_CMD_START_RC_Pos 1UL
+#define CRYPTO_V2_TR_MON_CMD_START_RC_Msk 0x2UL
+/* CRYPTO.TR_MON_RC_CTL */
+#define CRYPTO_V2_TR_MON_RC_CTL_CUTOFF_COUNT8_Pos 0UL
+#define CRYPTO_V2_TR_MON_RC_CTL_CUTOFF_COUNT8_Msk 0xFFUL
+/* CRYPTO.TR_MON_RC_STATUS0 */
+#define CRYPTO_V2_TR_MON_RC_STATUS0_BIT_Pos 0UL
+#define CRYPTO_V2_TR_MON_RC_STATUS0_BIT_Msk 0x1UL
+/* CRYPTO.TR_MON_RC_STATUS1 */
+#define CRYPTO_V2_TR_MON_RC_STATUS1_REP_COUNT_Pos 0UL
+#define CRYPTO_V2_TR_MON_RC_STATUS1_REP_COUNT_Msk 0xFFUL
+/* CRYPTO.TR_MON_AP_CTL */
+#define CRYPTO_V2_TR_MON_AP_CTL_CUTOFF_COUNT16_Pos 0UL
+#define CRYPTO_V2_TR_MON_AP_CTL_CUTOFF_COUNT16_Msk 0xFFFFUL
+#define CRYPTO_V2_TR_MON_AP_CTL_WINDOW_SIZE_Pos 16UL
+#define CRYPTO_V2_TR_MON_AP_CTL_WINDOW_SIZE_Msk 0xFFFF0000UL
+/* CRYPTO.TR_MON_AP_STATUS0 */
+#define CRYPTO_V2_TR_MON_AP_STATUS0_BIT_Pos 0UL
+#define CRYPTO_V2_TR_MON_AP_STATUS0_BIT_Msk 0x1UL
+/* CRYPTO.TR_MON_AP_STATUS1 */
+#define CRYPTO_V2_TR_MON_AP_STATUS1_OCC_COUNT_Pos 0UL
+#define CRYPTO_V2_TR_MON_AP_STATUS1_OCC_COUNT_Msk 0xFFFFUL
+#define CRYPTO_V2_TR_MON_AP_STATUS1_WINDOW_INDEX_Pos 16UL
+#define CRYPTO_V2_TR_MON_AP_STATUS1_WINDOW_INDEX_Msk 0xFFFF0000UL
+/* CRYPTO.STATUS */
+#define CRYPTO_V2_STATUS_BUSY_Pos 31UL
+#define CRYPTO_V2_STATUS_BUSY_Msk 0x80000000UL
+/* CRYPTO.INSTR_FF_CTL */
+#define CRYPTO_V2_INSTR_FF_CTL_EVENT_LEVEL_Pos 0UL
+#define CRYPTO_V2_INSTR_FF_CTL_EVENT_LEVEL_Msk 0x7UL
+#define CRYPTO_V2_INSTR_FF_CTL_CLEAR_Pos 16UL
+#define CRYPTO_V2_INSTR_FF_CTL_CLEAR_Msk 0x10000UL
+#define CRYPTO_V2_INSTR_FF_CTL_BLOCK_Pos 17UL
+#define CRYPTO_V2_INSTR_FF_CTL_BLOCK_Msk 0x20000UL
+/* CRYPTO.INSTR_FF_STATUS */
+#define CRYPTO_V2_INSTR_FF_STATUS_USED_Pos 0UL
+#define CRYPTO_V2_INSTR_FF_STATUS_USED_Msk 0xFUL
+#define CRYPTO_V2_INSTR_FF_STATUS_EVENT_Pos 16UL
+#define CRYPTO_V2_INSTR_FF_STATUS_EVENT_Msk 0x10000UL
+/* CRYPTO.INSTR_FF_WR */
+#define CRYPTO_V2_INSTR_FF_WR_DATA32_Pos 0UL
+#define CRYPTO_V2_INSTR_FF_WR_DATA32_Msk 0xFFFFFFFFUL
+/* CRYPTO.LOAD0_FF_STATUS */
+#define CRYPTO_V2_LOAD0_FF_STATUS_USED5_Pos 0UL
+#define CRYPTO_V2_LOAD0_FF_STATUS_USED5_Msk 0x1FUL
+#define CRYPTO_V2_LOAD0_FF_STATUS_BUSY_Pos 31UL
+#define CRYPTO_V2_LOAD0_FF_STATUS_BUSY_Msk 0x80000000UL
+/* CRYPTO.LOAD1_FF_STATUS */
+#define CRYPTO_V2_LOAD1_FF_STATUS_USED5_Pos 0UL
+#define CRYPTO_V2_LOAD1_FF_STATUS_USED5_Msk 0x1FUL
+#define CRYPTO_V2_LOAD1_FF_STATUS_BUSY_Pos 31UL
+#define CRYPTO_V2_LOAD1_FF_STATUS_BUSY_Msk 0x80000000UL
+/* CRYPTO.STORE_FF_STATUS */
+#define CRYPTO_V2_STORE_FF_STATUS_USED5_Pos 0UL
+#define CRYPTO_V2_STORE_FF_STATUS_USED5_Msk 0x1FUL
+#define CRYPTO_V2_STORE_FF_STATUS_BUSY_Pos 31UL
+#define CRYPTO_V2_STORE_FF_STATUS_BUSY_Msk 0x80000000UL
+/* CRYPTO.AES_CTL */
+#define CRYPTO_V2_AES_CTL_KEY_SIZE_Pos 0UL
+#define CRYPTO_V2_AES_CTL_KEY_SIZE_Msk 0x3UL
+/* CRYPTO.RESULT */
+#define CRYPTO_V2_RESULT_DATA_Pos 0UL
+#define CRYPTO_V2_RESULT_DATA_Msk 0xFFFFFFFFUL
+/* CRYPTO.CRC_CTL */
+#define CRYPTO_V2_CRC_CTL_DATA_REVERSE_Pos 0UL
+#define CRYPTO_V2_CRC_CTL_DATA_REVERSE_Msk 0x1UL
+#define CRYPTO_V2_CRC_CTL_REM_REVERSE_Pos 8UL
+#define CRYPTO_V2_CRC_CTL_REM_REVERSE_Msk 0x100UL
+/* CRYPTO.CRC_DATA_CTL */
+#define CRYPTO_V2_CRC_DATA_CTL_DATA_XOR_Pos 0UL
+#define CRYPTO_V2_CRC_DATA_CTL_DATA_XOR_Msk 0xFFUL
+/* CRYPTO.CRC_POL_CTL */
+#define CRYPTO_V2_CRC_POL_CTL_POLYNOMIAL_Pos 0UL
+#define CRYPTO_V2_CRC_POL_CTL_POLYNOMIAL_Msk 0xFFFFFFFFUL
+/* CRYPTO.CRC_REM_CTL */
+#define CRYPTO_V2_CRC_REM_CTL_REM_XOR_Pos 0UL
+#define CRYPTO_V2_CRC_REM_CTL_REM_XOR_Msk 0xFFFFFFFFUL
+/* CRYPTO.CRC_REM_RESULT */
+#define CRYPTO_V2_CRC_REM_RESULT_REM_Pos 0UL
+#define CRYPTO_V2_CRC_REM_RESULT_REM_Msk 0xFFFFFFFFUL
+/* CRYPTO.VU_CTL0 */
+#define CRYPTO_V2_VU_CTL0_ALWAYS_EXECUTE_Pos 0UL
+#define CRYPTO_V2_VU_CTL0_ALWAYS_EXECUTE_Msk 0x1UL
+/* CRYPTO.VU_CTL1 */
+#define CRYPTO_V2_VU_CTL1_ADDR24_Pos 8UL
+#define CRYPTO_V2_VU_CTL1_ADDR24_Msk 0xFFFFFF00UL
+/* CRYPTO.VU_CTL2 */
+#define CRYPTO_V2_VU_CTL2_MASK_Pos 8UL
+#define CRYPTO_V2_VU_CTL2_MASK_Msk 0x7F00UL
+/* CRYPTO.VU_STATUS */
+#define CRYPTO_V2_VU_STATUS_CARRY_Pos 0UL
+#define CRYPTO_V2_VU_STATUS_CARRY_Msk 0x1UL
+#define CRYPTO_V2_VU_STATUS_EVEN_Pos 1UL
+#define CRYPTO_V2_VU_STATUS_EVEN_Msk 0x2UL
+#define CRYPTO_V2_VU_STATUS_ZERO_Pos 2UL
+#define CRYPTO_V2_VU_STATUS_ZERO_Msk 0x4UL
+#define CRYPTO_V2_VU_STATUS_ONE_Pos 3UL
+#define CRYPTO_V2_VU_STATUS_ONE_Msk 0x8UL
+/* CRYPTO.VU_RF_DATA */
+#define CRYPTO_V2_VU_RF_DATA_DATA32_Pos 0UL
+#define CRYPTO_V2_VU_RF_DATA_DATA32_Msk 0xFFFFFFFFUL
+/* CRYPTO.DEV_KEY_ADDR0_CTL */
+#define CRYPTO_V2_DEV_KEY_ADDR0_CTL_VALID_Pos 31UL
+#define CRYPTO_V2_DEV_KEY_ADDR0_CTL_VALID_Msk 0x80000000UL
+/* CRYPTO.DEV_KEY_ADDR0 */
+#define CRYPTO_V2_DEV_KEY_ADDR0_ADDR32_Pos 0UL
+#define CRYPTO_V2_DEV_KEY_ADDR0_ADDR32_Msk 0xFFFFFFFFUL
+/* CRYPTO.DEV_KEY_ADDR1_CTL */
+#define CRYPTO_V2_DEV_KEY_ADDR1_CTL_VALID_Pos 31UL
+#define CRYPTO_V2_DEV_KEY_ADDR1_CTL_VALID_Msk 0x80000000UL
+/* CRYPTO.DEV_KEY_ADDR1 */
+#define CRYPTO_V2_DEV_KEY_ADDR1_ADDR32_Pos 0UL
+#define CRYPTO_V2_DEV_KEY_ADDR1_ADDR32_Msk 0xFFFFFFFFUL
+/* CRYPTO.DEV_KEY_STATUS */
+#define CRYPTO_V2_DEV_KEY_STATUS_LOADED_Pos 0UL
+#define CRYPTO_V2_DEV_KEY_STATUS_LOADED_Msk 0x1UL
+/* CRYPTO.DEV_KEY_CTL0 */
+#define CRYPTO_V2_DEV_KEY_CTL0_ALLOWED_Pos 0UL
+#define CRYPTO_V2_DEV_KEY_CTL0_ALLOWED_Msk 0x1UL
+/* CRYPTO.DEV_KEY_CTL1 */
+#define CRYPTO_V2_DEV_KEY_CTL1_ALLOWED_Pos 0UL
+#define CRYPTO_V2_DEV_KEY_CTL1_ALLOWED_Msk 0x1UL
+/* CRYPTO.MEM_BUFF */
+#define CRYPTO_V2_MEM_BUFF_DATA32_Pos 0UL
+#define CRYPTO_V2_MEM_BUFF_DATA32_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_CRYPTO_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_csd.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_csd.h
new file mode 100644
index 0000000000..caf4e0d69d
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_csd.h
@@ -0,0 +1,486 @@
+/***************************************************************************//**
+* \file cyip_csd.h
+*
+* \brief
+* CSD IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_CSD_H_
+#define _CYIP_CSD_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* CSD
+*******************************************************************************/
+
+#define CSD_SECTION_SIZE 0x00001000UL
+
+/**
+ * \brief Capsense Controller (CSD)
+ */
+typedef struct {
+ __IOM uint32_t CONFIG; /*!< 0x00000000 Configuration and Control */
+ __IOM uint32_t SPARE; /*!< 0x00000004 Spare MMIO */
+ __IM uint32_t RESERVED[30];
+ __IM uint32_t STATUS; /*!< 0x00000080 Status Register */
+ __IM uint32_t STAT_SEQ; /*!< 0x00000084 Current Sequencer status */
+ __IM uint32_t STAT_CNTS; /*!< 0x00000088 Current status counts */
+ __IM uint32_t STAT_HCNT; /*!< 0x0000008C Current count of the HSCMP counter */
+ __IM uint32_t RESERVED1[16];
+ __IM uint32_t RESULT_VAL1; /*!< 0x000000D0 Result CSD/CSX accumulation counter value 1 */
+ __IM uint32_t RESULT_VAL2; /*!< 0x000000D4 Result CSX accumulation counter value 2 */
+ __IM uint32_t RESERVED2[2];
+ __IM uint32_t ADC_RES; /*!< 0x000000E0 ADC measurement */
+ __IM uint32_t RESERVED3[3];
+ __IOM uint32_t INTR; /*!< 0x000000F0 CSD Interrupt Request Register */
+ __IOM uint32_t INTR_SET; /*!< 0x000000F4 CSD Interrupt set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x000000F8 CSD Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x000000FC CSD Interrupt masked register */
+ __IM uint32_t RESERVED4[32];
+ __IOM uint32_t HSCMP; /*!< 0x00000180 High Speed Comparator configuration */
+ __IOM uint32_t AMBUF; /*!< 0x00000184 Reference Generator configuration */
+ __IOM uint32_t REFGEN; /*!< 0x00000188 Reference Generator configuration */
+ __IOM uint32_t CSDCMP; /*!< 0x0000018C CSD Comparator configuration */
+ __IM uint32_t RESERVED5[24];
+ __IOM uint32_t SW_RES; /*!< 0x000001F0 Switch Resistance configuration */
+ __IM uint32_t RESERVED6[3];
+ __IOM uint32_t SENSE_PERIOD; /*!< 0x00000200 Sense clock period */
+ __IOM uint32_t SENSE_DUTY; /*!< 0x00000204 Sense clock duty cycle */
+ __IM uint32_t RESERVED7[30];
+ __IOM uint32_t SW_HS_P_SEL; /*!< 0x00000280 HSCMP Pos input switch Waveform selection */
+ __IOM uint32_t SW_HS_N_SEL; /*!< 0x00000284 HSCMP Neg input switch Waveform selection */
+ __IOM uint32_t SW_SHIELD_SEL; /*!< 0x00000288 Shielding switches Waveform selection */
+ __IM uint32_t RESERVED8;
+ __IOM uint32_t SW_AMUXBUF_SEL; /*!< 0x00000290 Amuxbuffer switches Waveform selection */
+ __IOM uint32_t SW_BYP_SEL; /*!< 0x00000294 AMUXBUS bypass switches Waveform selection */
+ __IM uint32_t RESERVED9[2];
+ __IOM uint32_t SW_CMP_P_SEL; /*!< 0x000002A0 CSDCMP Pos Switch Waveform selection */
+ __IOM uint32_t SW_CMP_N_SEL; /*!< 0x000002A4 CSDCMP Neg Switch Waveform selection */
+ __IOM uint32_t SW_REFGEN_SEL; /*!< 0x000002A8 Reference Generator Switch Waveform selection */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t SW_FW_MOD_SEL; /*!< 0x000002B0 Full Wave Cmod Switch Waveform selection */
+ __IOM uint32_t SW_FW_TANK_SEL; /*!< 0x000002B4 Full Wave Csh_tank Switch Waveform selection */
+ __IM uint32_t RESERVED11[2];
+ __IOM uint32_t SW_DSI_SEL; /*!< 0x000002C0 DSI output switch control Waveform selection */
+ __IM uint32_t RESERVED12[3];
+ __IOM uint32_t IO_SEL; /*!< 0x000002D0 IO output control Waveform selection */
+ __IM uint32_t RESERVED13[11];
+ __IOM uint32_t SEQ_TIME; /*!< 0x00000300 Sequencer Timing */
+ __IM uint32_t RESERVED14[3];
+ __IOM uint32_t SEQ_INIT_CNT; /*!< 0x00000310 Sequencer Initial conversion and sample counts */
+ __IOM uint32_t SEQ_NORM_CNT; /*!< 0x00000314 Sequencer Normal conversion and sample counts */
+ __IM uint32_t RESERVED15[2];
+ __IOM uint32_t ADC_CTL; /*!< 0x00000320 ADC Control */
+ __IM uint32_t RESERVED16[7];
+ __IOM uint32_t SEQ_START; /*!< 0x00000340 Sequencer start */
+ __IM uint32_t RESERVED17[47];
+ __IOM uint32_t IDACA; /*!< 0x00000400 IDACA Configuration */
+ __IM uint32_t RESERVED18[63];
+ __IOM uint32_t IDACB; /*!< 0x00000500 IDACB Configuration */
+} CSD_V1_Type; /*!< Size = 1284 (0x504) */
+
+
+/* CSD.CONFIG */
+#define CSD_CONFIG_IREF_SEL_Pos 0UL
+#define CSD_CONFIG_IREF_SEL_Msk 0x1UL
+#define CSD_CONFIG_FILTER_DELAY_Pos 4UL
+#define CSD_CONFIG_FILTER_DELAY_Msk 0x1F0UL
+#define CSD_CONFIG_SHIELD_DELAY_Pos 10UL
+#define CSD_CONFIG_SHIELD_DELAY_Msk 0xC00UL
+#define CSD_CONFIG_SENSE_EN_Pos 12UL
+#define CSD_CONFIG_SENSE_EN_Msk 0x1000UL
+#define CSD_CONFIG_FULL_WAVE_Pos 17UL
+#define CSD_CONFIG_FULL_WAVE_Msk 0x20000UL
+#define CSD_CONFIG_MUTUAL_CAP_Pos 18UL
+#define CSD_CONFIG_MUTUAL_CAP_Msk 0x40000UL
+#define CSD_CONFIG_CSX_DUAL_CNT_Pos 19UL
+#define CSD_CONFIG_CSX_DUAL_CNT_Msk 0x80000UL
+#define CSD_CONFIG_DSI_COUNT_SEL_Pos 24UL
+#define CSD_CONFIG_DSI_COUNT_SEL_Msk 0x1000000UL
+#define CSD_CONFIG_DSI_SAMPLE_EN_Pos 25UL
+#define CSD_CONFIG_DSI_SAMPLE_EN_Msk 0x2000000UL
+#define CSD_CONFIG_SAMPLE_SYNC_Pos 26UL
+#define CSD_CONFIG_SAMPLE_SYNC_Msk 0x4000000UL
+#define CSD_CONFIG_DSI_SENSE_EN_Pos 27UL
+#define CSD_CONFIG_DSI_SENSE_EN_Msk 0x8000000UL
+#define CSD_CONFIG_LP_MODE_Pos 30UL
+#define CSD_CONFIG_LP_MODE_Msk 0x40000000UL
+#define CSD_CONFIG_ENABLE_Pos 31UL
+#define CSD_CONFIG_ENABLE_Msk 0x80000000UL
+/* CSD.SPARE */
+#define CSD_SPARE_SPARE_Pos 0UL
+#define CSD_SPARE_SPARE_Msk 0xFUL
+/* CSD.STATUS */
+#define CSD_STATUS_CSD_SENSE_Pos 1UL
+#define CSD_STATUS_CSD_SENSE_Msk 0x2UL
+#define CSD_STATUS_HSCMP_OUT_Pos 2UL
+#define CSD_STATUS_HSCMP_OUT_Msk 0x4UL
+#define CSD_STATUS_CSDCMP_OUT_Pos 3UL
+#define CSD_STATUS_CSDCMP_OUT_Msk 0x8UL
+/* CSD.STAT_SEQ */
+#define CSD_STAT_SEQ_SEQ_STATE_Pos 0UL
+#define CSD_STAT_SEQ_SEQ_STATE_Msk 0x7UL
+#define CSD_STAT_SEQ_ADC_STATE_Pos 16UL
+#define CSD_STAT_SEQ_ADC_STATE_Msk 0x70000UL
+/* CSD.STAT_CNTS */
+#define CSD_STAT_CNTS_NUM_CONV_Pos 0UL
+#define CSD_STAT_CNTS_NUM_CONV_Msk 0xFFFFUL
+/* CSD.STAT_HCNT */
+#define CSD_STAT_HCNT_CNT_Pos 0UL
+#define CSD_STAT_HCNT_CNT_Msk 0xFFFFUL
+/* CSD.RESULT_VAL1 */
+#define CSD_RESULT_VAL1_VALUE_Pos 0UL
+#define CSD_RESULT_VAL1_VALUE_Msk 0xFFFFUL
+#define CSD_RESULT_VAL1_BAD_CONVS_Pos 16UL
+#define CSD_RESULT_VAL1_BAD_CONVS_Msk 0xFF0000UL
+/* CSD.RESULT_VAL2 */
+#define CSD_RESULT_VAL2_VALUE_Pos 0UL
+#define CSD_RESULT_VAL2_VALUE_Msk 0xFFFFUL
+/* CSD.ADC_RES */
+#define CSD_ADC_RES_VIN_CNT_Pos 0UL
+#define CSD_ADC_RES_VIN_CNT_Msk 0xFFFFUL
+#define CSD_ADC_RES_HSCMP_POL_Pos 16UL
+#define CSD_ADC_RES_HSCMP_POL_Msk 0x10000UL
+#define CSD_ADC_RES_ADC_OVERFLOW_Pos 30UL
+#define CSD_ADC_RES_ADC_OVERFLOW_Msk 0x40000000UL
+#define CSD_ADC_RES_ADC_ABORT_Pos 31UL
+#define CSD_ADC_RES_ADC_ABORT_Msk 0x80000000UL
+/* CSD.INTR */
+#define CSD_INTR_SAMPLE_Pos 1UL
+#define CSD_INTR_SAMPLE_Msk 0x2UL
+#define CSD_INTR_INIT_Pos 2UL
+#define CSD_INTR_INIT_Msk 0x4UL
+#define CSD_INTR_ADC_RES_Pos 8UL
+#define CSD_INTR_ADC_RES_Msk 0x100UL
+/* CSD.INTR_SET */
+#define CSD_INTR_SET_SAMPLE_Pos 1UL
+#define CSD_INTR_SET_SAMPLE_Msk 0x2UL
+#define CSD_INTR_SET_INIT_Pos 2UL
+#define CSD_INTR_SET_INIT_Msk 0x4UL
+#define CSD_INTR_SET_ADC_RES_Pos 8UL
+#define CSD_INTR_SET_ADC_RES_Msk 0x100UL
+/* CSD.INTR_MASK */
+#define CSD_INTR_MASK_SAMPLE_Pos 1UL
+#define CSD_INTR_MASK_SAMPLE_Msk 0x2UL
+#define CSD_INTR_MASK_INIT_Pos 2UL
+#define CSD_INTR_MASK_INIT_Msk 0x4UL
+#define CSD_INTR_MASK_ADC_RES_Pos 8UL
+#define CSD_INTR_MASK_ADC_RES_Msk 0x100UL
+/* CSD.INTR_MASKED */
+#define CSD_INTR_MASKED_SAMPLE_Pos 1UL
+#define CSD_INTR_MASKED_SAMPLE_Msk 0x2UL
+#define CSD_INTR_MASKED_INIT_Pos 2UL
+#define CSD_INTR_MASKED_INIT_Msk 0x4UL
+#define CSD_INTR_MASKED_ADC_RES_Pos 8UL
+#define CSD_INTR_MASKED_ADC_RES_Msk 0x100UL
+/* CSD.HSCMP */
+#define CSD_HSCMP_HSCMP_EN_Pos 0UL
+#define CSD_HSCMP_HSCMP_EN_Msk 0x1UL
+#define CSD_HSCMP_HSCMP_INVERT_Pos 4UL
+#define CSD_HSCMP_HSCMP_INVERT_Msk 0x10UL
+#define CSD_HSCMP_AZ_EN_Pos 31UL
+#define CSD_HSCMP_AZ_EN_Msk 0x80000000UL
+/* CSD.AMBUF */
+#define CSD_AMBUF_PWR_MODE_Pos 0UL
+#define CSD_AMBUF_PWR_MODE_Msk 0x3UL
+/* CSD.REFGEN */
+#define CSD_REFGEN_REFGEN_EN_Pos 0UL
+#define CSD_REFGEN_REFGEN_EN_Msk 0x1UL
+#define CSD_REFGEN_BYPASS_Pos 4UL
+#define CSD_REFGEN_BYPASS_Msk 0x10UL
+#define CSD_REFGEN_VDDA_EN_Pos 5UL
+#define CSD_REFGEN_VDDA_EN_Msk 0x20UL
+#define CSD_REFGEN_RES_EN_Pos 6UL
+#define CSD_REFGEN_RES_EN_Msk 0x40UL
+#define CSD_REFGEN_GAIN_Pos 8UL
+#define CSD_REFGEN_GAIN_Msk 0x1F00UL
+#define CSD_REFGEN_VREFLO_SEL_Pos 16UL
+#define CSD_REFGEN_VREFLO_SEL_Msk 0x1F0000UL
+#define CSD_REFGEN_VREFLO_INT_Pos 23UL
+#define CSD_REFGEN_VREFLO_INT_Msk 0x800000UL
+/* CSD.CSDCMP */
+#define CSD_CSDCMP_CSDCMP_EN_Pos 0UL
+#define CSD_CSDCMP_CSDCMP_EN_Msk 0x1UL
+#define CSD_CSDCMP_POLARITY_SEL_Pos 4UL
+#define CSD_CSDCMP_POLARITY_SEL_Msk 0x30UL
+#define CSD_CSDCMP_CMP_PHASE_Pos 8UL
+#define CSD_CSDCMP_CMP_PHASE_Msk 0x300UL
+#define CSD_CSDCMP_CMP_MODE_Pos 28UL
+#define CSD_CSDCMP_CMP_MODE_Msk 0x10000000UL
+#define CSD_CSDCMP_FEEDBACK_MODE_Pos 29UL
+#define CSD_CSDCMP_FEEDBACK_MODE_Msk 0x20000000UL
+#define CSD_CSDCMP_AZ_EN_Pos 31UL
+#define CSD_CSDCMP_AZ_EN_Msk 0x80000000UL
+/* CSD.SW_RES */
+#define CSD_SW_RES_RES_HCAV_Pos 0UL
+#define CSD_SW_RES_RES_HCAV_Msk 0x3UL
+#define CSD_SW_RES_RES_HCAG_Pos 2UL
+#define CSD_SW_RES_RES_HCAG_Msk 0xCUL
+#define CSD_SW_RES_RES_HCBV_Pos 4UL
+#define CSD_SW_RES_RES_HCBV_Msk 0x30UL
+#define CSD_SW_RES_RES_HCBG_Pos 6UL
+#define CSD_SW_RES_RES_HCBG_Msk 0xC0UL
+#define CSD_SW_RES_RES_F1PM_Pos 16UL
+#define CSD_SW_RES_RES_F1PM_Msk 0x30000UL
+#define CSD_SW_RES_RES_F2PT_Pos 18UL
+#define CSD_SW_RES_RES_F2PT_Msk 0xC0000UL
+/* CSD.SENSE_PERIOD */
+#define CSD_SENSE_PERIOD_SENSE_DIV_Pos 0UL
+#define CSD_SENSE_PERIOD_SENSE_DIV_Msk 0xFFFUL
+#define CSD_SENSE_PERIOD_LFSR_SIZE_Pos 16UL
+#define CSD_SENSE_PERIOD_LFSR_SIZE_Msk 0x70000UL
+#define CSD_SENSE_PERIOD_LFSR_SCALE_Pos 20UL
+#define CSD_SENSE_PERIOD_LFSR_SCALE_Msk 0xF00000UL
+#define CSD_SENSE_PERIOD_LFSR_CLEAR_Pos 24UL
+#define CSD_SENSE_PERIOD_LFSR_CLEAR_Msk 0x1000000UL
+#define CSD_SENSE_PERIOD_SEL_LFSR_MSB_Pos 25UL
+#define CSD_SENSE_PERIOD_SEL_LFSR_MSB_Msk 0x2000000UL
+#define CSD_SENSE_PERIOD_LFSR_BITS_Pos 26UL
+#define CSD_SENSE_PERIOD_LFSR_BITS_Msk 0xC000000UL
+/* CSD.SENSE_DUTY */
+#define CSD_SENSE_DUTY_SENSE_WIDTH_Pos 0UL
+#define CSD_SENSE_DUTY_SENSE_WIDTH_Msk 0xFFFUL
+#define CSD_SENSE_DUTY_SENSE_POL_Pos 16UL
+#define CSD_SENSE_DUTY_SENSE_POL_Msk 0x10000UL
+#define CSD_SENSE_DUTY_OVERLAP_PHI1_Pos 18UL
+#define CSD_SENSE_DUTY_OVERLAP_PHI1_Msk 0x40000UL
+#define CSD_SENSE_DUTY_OVERLAP_PHI2_Pos 19UL
+#define CSD_SENSE_DUTY_OVERLAP_PHI2_Msk 0x80000UL
+/* CSD.SW_HS_P_SEL */
+#define CSD_SW_HS_P_SEL_SW_HMPM_Pos 0UL
+#define CSD_SW_HS_P_SEL_SW_HMPM_Msk 0x1UL
+#define CSD_SW_HS_P_SEL_SW_HMPT_Pos 4UL
+#define CSD_SW_HS_P_SEL_SW_HMPT_Msk 0x10UL
+#define CSD_SW_HS_P_SEL_SW_HMPS_Pos 8UL
+#define CSD_SW_HS_P_SEL_SW_HMPS_Msk 0x100UL
+#define CSD_SW_HS_P_SEL_SW_HMMA_Pos 12UL
+#define CSD_SW_HS_P_SEL_SW_HMMA_Msk 0x1000UL
+#define CSD_SW_HS_P_SEL_SW_HMMB_Pos 16UL
+#define CSD_SW_HS_P_SEL_SW_HMMB_Msk 0x10000UL
+#define CSD_SW_HS_P_SEL_SW_HMCA_Pos 20UL
+#define CSD_SW_HS_P_SEL_SW_HMCA_Msk 0x100000UL
+#define CSD_SW_HS_P_SEL_SW_HMCB_Pos 24UL
+#define CSD_SW_HS_P_SEL_SW_HMCB_Msk 0x1000000UL
+#define CSD_SW_HS_P_SEL_SW_HMRH_Pos 28UL
+#define CSD_SW_HS_P_SEL_SW_HMRH_Msk 0x10000000UL
+/* CSD.SW_HS_N_SEL */
+#define CSD_SW_HS_N_SEL_SW_HCCC_Pos 16UL
+#define CSD_SW_HS_N_SEL_SW_HCCC_Msk 0x10000UL
+#define CSD_SW_HS_N_SEL_SW_HCCD_Pos 20UL
+#define CSD_SW_HS_N_SEL_SW_HCCD_Msk 0x100000UL
+#define CSD_SW_HS_N_SEL_SW_HCRH_Pos 24UL
+#define CSD_SW_HS_N_SEL_SW_HCRH_Msk 0x7000000UL
+#define CSD_SW_HS_N_SEL_SW_HCRL_Pos 28UL
+#define CSD_SW_HS_N_SEL_SW_HCRL_Msk 0x70000000UL
+/* CSD.SW_SHIELD_SEL */
+#define CSD_SW_SHIELD_SEL_SW_HCAV_Pos 0UL
+#define CSD_SW_SHIELD_SEL_SW_HCAV_Msk 0x7UL
+#define CSD_SW_SHIELD_SEL_SW_HCAG_Pos 4UL
+#define CSD_SW_SHIELD_SEL_SW_HCAG_Msk 0x70UL
+#define CSD_SW_SHIELD_SEL_SW_HCBV_Pos 8UL
+#define CSD_SW_SHIELD_SEL_SW_HCBV_Msk 0x700UL
+#define CSD_SW_SHIELD_SEL_SW_HCBG_Pos 12UL
+#define CSD_SW_SHIELD_SEL_SW_HCBG_Msk 0x7000UL
+#define CSD_SW_SHIELD_SEL_SW_HCCV_Pos 16UL
+#define CSD_SW_SHIELD_SEL_SW_HCCV_Msk 0x10000UL
+#define CSD_SW_SHIELD_SEL_SW_HCCG_Pos 20UL
+#define CSD_SW_SHIELD_SEL_SW_HCCG_Msk 0x100000UL
+/* CSD.SW_AMUXBUF_SEL */
+#define CSD_SW_AMUXBUF_SEL_SW_IRBY_Pos 4UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRBY_Msk 0x10UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRLB_Pos 8UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRLB_Msk 0x100UL
+#define CSD_SW_AMUXBUF_SEL_SW_ICA_Pos 12UL
+#define CSD_SW_AMUXBUF_SEL_SW_ICA_Msk 0x1000UL
+#define CSD_SW_AMUXBUF_SEL_SW_ICB_Pos 16UL
+#define CSD_SW_AMUXBUF_SEL_SW_ICB_Msk 0x70000UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRLI_Pos 20UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRLI_Msk 0x100000UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRH_Pos 24UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRH_Msk 0x1000000UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRL_Pos 28UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRL_Msk 0x10000000UL
+/* CSD.SW_BYP_SEL */
+#define CSD_SW_BYP_SEL_SW_BYA_Pos 12UL
+#define CSD_SW_BYP_SEL_SW_BYA_Msk 0x1000UL
+#define CSD_SW_BYP_SEL_SW_BYB_Pos 16UL
+#define CSD_SW_BYP_SEL_SW_BYB_Msk 0x10000UL
+#define CSD_SW_BYP_SEL_SW_CBCC_Pos 20UL
+#define CSD_SW_BYP_SEL_SW_CBCC_Msk 0x100000UL
+/* CSD.SW_CMP_P_SEL */
+#define CSD_SW_CMP_P_SEL_SW_SFPM_Pos 0UL
+#define CSD_SW_CMP_P_SEL_SW_SFPM_Msk 0x7UL
+#define CSD_SW_CMP_P_SEL_SW_SFPT_Pos 4UL
+#define CSD_SW_CMP_P_SEL_SW_SFPT_Msk 0x70UL
+#define CSD_SW_CMP_P_SEL_SW_SFPS_Pos 8UL
+#define CSD_SW_CMP_P_SEL_SW_SFPS_Msk 0x700UL
+#define CSD_SW_CMP_P_SEL_SW_SFMA_Pos 12UL
+#define CSD_SW_CMP_P_SEL_SW_SFMA_Msk 0x1000UL
+#define CSD_SW_CMP_P_SEL_SW_SFMB_Pos 16UL
+#define CSD_SW_CMP_P_SEL_SW_SFMB_Msk 0x10000UL
+#define CSD_SW_CMP_P_SEL_SW_SFCA_Pos 20UL
+#define CSD_SW_CMP_P_SEL_SW_SFCA_Msk 0x100000UL
+#define CSD_SW_CMP_P_SEL_SW_SFCB_Pos 24UL
+#define CSD_SW_CMP_P_SEL_SW_SFCB_Msk 0x1000000UL
+/* CSD.SW_CMP_N_SEL */
+#define CSD_SW_CMP_N_SEL_SW_SCRH_Pos 24UL
+#define CSD_SW_CMP_N_SEL_SW_SCRH_Msk 0x7000000UL
+#define CSD_SW_CMP_N_SEL_SW_SCRL_Pos 28UL
+#define CSD_SW_CMP_N_SEL_SW_SCRL_Msk 0x70000000UL
+/* CSD.SW_REFGEN_SEL */
+#define CSD_SW_REFGEN_SEL_SW_IAIB_Pos 0UL
+#define CSD_SW_REFGEN_SEL_SW_IAIB_Msk 0x1UL
+#define CSD_SW_REFGEN_SEL_SW_IBCB_Pos 4UL
+#define CSD_SW_REFGEN_SEL_SW_IBCB_Msk 0x10UL
+#define CSD_SW_REFGEN_SEL_SW_SGMB_Pos 16UL
+#define CSD_SW_REFGEN_SEL_SW_SGMB_Msk 0x10000UL
+#define CSD_SW_REFGEN_SEL_SW_SGRP_Pos 20UL
+#define CSD_SW_REFGEN_SEL_SW_SGRP_Msk 0x100000UL
+#define CSD_SW_REFGEN_SEL_SW_SGRE_Pos 24UL
+#define CSD_SW_REFGEN_SEL_SW_SGRE_Msk 0x1000000UL
+#define CSD_SW_REFGEN_SEL_SW_SGR_Pos 28UL
+#define CSD_SW_REFGEN_SEL_SW_SGR_Msk 0x10000000UL
+/* CSD.SW_FW_MOD_SEL */
+#define CSD_SW_FW_MOD_SEL_SW_F1PM_Pos 0UL
+#define CSD_SW_FW_MOD_SEL_SW_F1PM_Msk 0x1UL
+#define CSD_SW_FW_MOD_SEL_SW_F1MA_Pos 8UL
+#define CSD_SW_FW_MOD_SEL_SW_F1MA_Msk 0x700UL
+#define CSD_SW_FW_MOD_SEL_SW_F1CA_Pos 16UL
+#define CSD_SW_FW_MOD_SEL_SW_F1CA_Msk 0x70000UL
+#define CSD_SW_FW_MOD_SEL_SW_C1CC_Pos 20UL
+#define CSD_SW_FW_MOD_SEL_SW_C1CC_Msk 0x100000UL
+#define CSD_SW_FW_MOD_SEL_SW_C1CD_Pos 24UL
+#define CSD_SW_FW_MOD_SEL_SW_C1CD_Msk 0x1000000UL
+#define CSD_SW_FW_MOD_SEL_SW_C1F1_Pos 28UL
+#define CSD_SW_FW_MOD_SEL_SW_C1F1_Msk 0x10000000UL
+/* CSD.SW_FW_TANK_SEL */
+#define CSD_SW_FW_TANK_SEL_SW_F2PT_Pos 4UL
+#define CSD_SW_FW_TANK_SEL_SW_F2PT_Msk 0x10UL
+#define CSD_SW_FW_TANK_SEL_SW_F2MA_Pos 8UL
+#define CSD_SW_FW_TANK_SEL_SW_F2MA_Msk 0x700UL
+#define CSD_SW_FW_TANK_SEL_SW_F2CA_Pos 12UL
+#define CSD_SW_FW_TANK_SEL_SW_F2CA_Msk 0x7000UL
+#define CSD_SW_FW_TANK_SEL_SW_F2CB_Pos 16UL
+#define CSD_SW_FW_TANK_SEL_SW_F2CB_Msk 0x70000UL
+#define CSD_SW_FW_TANK_SEL_SW_C2CC_Pos 20UL
+#define CSD_SW_FW_TANK_SEL_SW_C2CC_Msk 0x100000UL
+#define CSD_SW_FW_TANK_SEL_SW_C2CD_Pos 24UL
+#define CSD_SW_FW_TANK_SEL_SW_C2CD_Msk 0x1000000UL
+#define CSD_SW_FW_TANK_SEL_SW_C2F2_Pos 28UL
+#define CSD_SW_FW_TANK_SEL_SW_C2F2_Msk 0x10000000UL
+/* CSD.SW_DSI_SEL */
+#define CSD_SW_DSI_SEL_DSI_CSH_TANK_Pos 0UL
+#define CSD_SW_DSI_SEL_DSI_CSH_TANK_Msk 0xFUL
+#define CSD_SW_DSI_SEL_DSI_CMOD_Pos 4UL
+#define CSD_SW_DSI_SEL_DSI_CMOD_Msk 0xF0UL
+/* CSD.IO_SEL */
+#define CSD_IO_SEL_CSD_TX_OUT_Pos 0UL
+#define CSD_IO_SEL_CSD_TX_OUT_Msk 0xFUL
+#define CSD_IO_SEL_CSD_TX_OUT_EN_Pos 4UL
+#define CSD_IO_SEL_CSD_TX_OUT_EN_Msk 0xF0UL
+#define CSD_IO_SEL_CSD_TX_AMUXB_EN_Pos 12UL
+#define CSD_IO_SEL_CSD_TX_AMUXB_EN_Msk 0xF000UL
+#define CSD_IO_SEL_CSD_TX_N_OUT_Pos 16UL
+#define CSD_IO_SEL_CSD_TX_N_OUT_Msk 0xF0000UL
+#define CSD_IO_SEL_CSD_TX_N_OUT_EN_Pos 20UL
+#define CSD_IO_SEL_CSD_TX_N_OUT_EN_Msk 0xF00000UL
+#define CSD_IO_SEL_CSD_TX_N_AMUXA_EN_Pos 24UL
+#define CSD_IO_SEL_CSD_TX_N_AMUXA_EN_Msk 0xF000000UL
+/* CSD.SEQ_TIME */
+#define CSD_SEQ_TIME_AZ_TIME_Pos 0UL
+#define CSD_SEQ_TIME_AZ_TIME_Msk 0xFFUL
+/* CSD.SEQ_INIT_CNT */
+#define CSD_SEQ_INIT_CNT_CONV_CNT_Pos 0UL
+#define CSD_SEQ_INIT_CNT_CONV_CNT_Msk 0xFFFFUL
+/* CSD.SEQ_NORM_CNT */
+#define CSD_SEQ_NORM_CNT_CONV_CNT_Pos 0UL
+#define CSD_SEQ_NORM_CNT_CONV_CNT_Msk 0xFFFFUL
+/* CSD.ADC_CTL */
+#define CSD_ADC_CTL_ADC_TIME_Pos 0UL
+#define CSD_ADC_CTL_ADC_TIME_Msk 0xFFUL
+#define CSD_ADC_CTL_ADC_MODE_Pos 16UL
+#define CSD_ADC_CTL_ADC_MODE_Msk 0x30000UL
+/* CSD.SEQ_START */
+#define CSD_SEQ_START_START_Pos 0UL
+#define CSD_SEQ_START_START_Msk 0x1UL
+#define CSD_SEQ_START_SEQ_MODE_Pos 1UL
+#define CSD_SEQ_START_SEQ_MODE_Msk 0x2UL
+#define CSD_SEQ_START_ABORT_Pos 3UL
+#define CSD_SEQ_START_ABORT_Msk 0x8UL
+#define CSD_SEQ_START_DSI_START_EN_Pos 4UL
+#define CSD_SEQ_START_DSI_START_EN_Msk 0x10UL
+#define CSD_SEQ_START_AZ0_SKIP_Pos 8UL
+#define CSD_SEQ_START_AZ0_SKIP_Msk 0x100UL
+#define CSD_SEQ_START_AZ1_SKIP_Pos 9UL
+#define CSD_SEQ_START_AZ1_SKIP_Msk 0x200UL
+/* CSD.IDACA */
+#define CSD_IDACA_VAL_Pos 0UL
+#define CSD_IDACA_VAL_Msk 0x7FUL
+#define CSD_IDACA_POL_DYN_Pos 7UL
+#define CSD_IDACA_POL_DYN_Msk 0x80UL
+#define CSD_IDACA_POLARITY_Pos 8UL
+#define CSD_IDACA_POLARITY_Msk 0x300UL
+#define CSD_IDACA_BAL_MODE_Pos 10UL
+#define CSD_IDACA_BAL_MODE_Msk 0xC00UL
+#define CSD_IDACA_LEG1_MODE_Pos 16UL
+#define CSD_IDACA_LEG1_MODE_Msk 0x30000UL
+#define CSD_IDACA_LEG2_MODE_Pos 18UL
+#define CSD_IDACA_LEG2_MODE_Msk 0xC0000UL
+#define CSD_IDACA_DSI_CTRL_EN_Pos 21UL
+#define CSD_IDACA_DSI_CTRL_EN_Msk 0x200000UL
+#define CSD_IDACA_RANGE_Pos 22UL
+#define CSD_IDACA_RANGE_Msk 0xC00000UL
+#define CSD_IDACA_LEG1_EN_Pos 24UL
+#define CSD_IDACA_LEG1_EN_Msk 0x1000000UL
+#define CSD_IDACA_LEG2_EN_Pos 25UL
+#define CSD_IDACA_LEG2_EN_Msk 0x2000000UL
+/* CSD.IDACB */
+#define CSD_IDACB_VAL_Pos 0UL
+#define CSD_IDACB_VAL_Msk 0x7FUL
+#define CSD_IDACB_POL_DYN_Pos 7UL
+#define CSD_IDACB_POL_DYN_Msk 0x80UL
+#define CSD_IDACB_POLARITY_Pos 8UL
+#define CSD_IDACB_POLARITY_Msk 0x300UL
+#define CSD_IDACB_BAL_MODE_Pos 10UL
+#define CSD_IDACB_BAL_MODE_Msk 0xC00UL
+#define CSD_IDACB_LEG1_MODE_Pos 16UL
+#define CSD_IDACB_LEG1_MODE_Msk 0x30000UL
+#define CSD_IDACB_LEG2_MODE_Pos 18UL
+#define CSD_IDACB_LEG2_MODE_Msk 0xC0000UL
+#define CSD_IDACB_DSI_CTRL_EN_Pos 21UL
+#define CSD_IDACB_DSI_CTRL_EN_Msk 0x200000UL
+#define CSD_IDACB_RANGE_Pos 22UL
+#define CSD_IDACB_RANGE_Msk 0xC00000UL
+#define CSD_IDACB_LEG1_EN_Pos 24UL
+#define CSD_IDACB_LEG1_EN_Msk 0x1000000UL
+#define CSD_IDACB_LEG2_EN_Pos 25UL
+#define CSD_IDACB_LEG2_EN_Msk 0x2000000UL
+#define CSD_IDACB_LEG3_EN_Pos 26UL
+#define CSD_IDACB_LEG3_EN_Msk 0x4000000UL
+
+
+#endif /* _CYIP_CSD_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_ctbm.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_ctbm.h
new file mode 100644
index 0000000000..0e9ae3497c
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_ctbm.h
@@ -0,0 +1,296 @@
+/***************************************************************************//**
+* \file cyip_ctbm.h
+*
+* \brief
+* CTBM IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_CTBM_H_
+#define _CYIP_CTBM_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* CTBM
+*******************************************************************************/
+
+#define CTBM_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Continuous Time Block Mini (CTBM)
+ */
+typedef struct {
+ __IOM uint32_t CTB_CTRL; /*!< 0x00000000 global CTB and power control */
+ __IOM uint32_t OA_RES0_CTRL; /*!< 0x00000004 Opamp0 and resistor0 control */
+ __IOM uint32_t OA_RES1_CTRL; /*!< 0x00000008 Opamp1 and resistor1 control */
+ __IM uint32_t COMP_STAT; /*!< 0x0000000C Comparator status */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t INTR; /*!< 0x00000020 Interrupt request register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt request set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt request mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt request masked */
+ __IM uint32_t RESERVED1[20];
+ __IOM uint32_t OA0_SW; /*!< 0x00000080 Opamp0 switch control */
+ __IOM uint32_t OA0_SW_CLEAR; /*!< 0x00000084 Opamp0 switch control clear */
+ __IOM uint32_t OA1_SW; /*!< 0x00000088 Opamp1 switch control */
+ __IOM uint32_t OA1_SW_CLEAR; /*!< 0x0000008C Opamp1 switch control clear */
+ __IM uint32_t RESERVED2[4];
+ __IOM uint32_t CTD_SW; /*!< 0x000000A0 CTDAC connection switch control */
+ __IOM uint32_t CTD_SW_CLEAR; /*!< 0x000000A4 CTDAC connection switch control clear */
+ __IM uint32_t RESERVED3[6];
+ __IOM uint32_t CTB_SW_DS_CTRL; /*!< 0x000000C0 CTB bus switch control */
+ __IOM uint32_t CTB_SW_SQ_CTRL; /*!< 0x000000C4 CTB bus switch Sar Sequencer control */
+ __IM uint32_t CTB_SW_STATUS; /*!< 0x000000C8 CTB bus switch control status */
+ __IM uint32_t RESERVED4[909];
+ __IOM uint32_t OA0_OFFSET_TRIM; /*!< 0x00000F00 Opamp0 trim control */
+ __IOM uint32_t OA0_SLOPE_OFFSET_TRIM; /*!< 0x00000F04 Opamp0 trim control */
+ __IOM uint32_t OA0_COMP_TRIM; /*!< 0x00000F08 Opamp0 trim control */
+ __IOM uint32_t OA1_OFFSET_TRIM; /*!< 0x00000F0C Opamp1 trim control */
+ __IOM uint32_t OA1_SLOPE_OFFSET_TRIM; /*!< 0x00000F10 Opamp1 trim control */
+ __IOM uint32_t OA1_COMP_TRIM; /*!< 0x00000F14 Opamp1 trim control */
+} CTBM_V1_Type; /*!< Size = 3864 (0xF18) */
+
+
+/* CTBM.CTB_CTRL */
+#define CTBM_CTB_CTRL_DEEPSLEEP_ON_Pos 30UL
+#define CTBM_CTB_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL
+#define CTBM_CTB_CTRL_ENABLED_Pos 31UL
+#define CTBM_CTB_CTRL_ENABLED_Msk 0x80000000UL
+/* CTBM.OA_RES0_CTRL */
+#define CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Pos 0UL
+#define CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Msk 0x7UL
+#define CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos 3UL
+#define CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Msk 0x8UL
+#define CTBM_OA_RES0_CTRL_OA0_COMP_EN_Pos 4UL
+#define CTBM_OA_RES0_CTRL_OA0_COMP_EN_Msk 0x10UL
+#define CTBM_OA_RES0_CTRL_OA0_HYST_EN_Pos 5UL
+#define CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk 0x20UL
+#define CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Pos 6UL
+#define CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk 0x40UL
+#define CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Pos 7UL
+#define CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk 0x80UL
+#define CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos 8UL
+#define CTBM_OA_RES0_CTRL_OA0_COMPINT_Msk 0x300UL
+#define CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Pos 11UL
+#define CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk 0x800UL
+#define CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Pos 12UL
+#define CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Msk 0x1000UL
+/* CTBM.OA_RES1_CTRL */
+#define CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Pos 0UL
+#define CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Msk 0x7UL
+#define CTBM_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Pos 3UL
+#define CTBM_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Msk 0x8UL
+#define CTBM_OA_RES1_CTRL_OA1_COMP_EN_Pos 4UL
+#define CTBM_OA_RES1_CTRL_OA1_COMP_EN_Msk 0x10UL
+#define CTBM_OA_RES1_CTRL_OA1_HYST_EN_Pos 5UL
+#define CTBM_OA_RES1_CTRL_OA1_HYST_EN_Msk 0x20UL
+#define CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Pos 6UL
+#define CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk 0x40UL
+#define CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Pos 7UL
+#define CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk 0x80UL
+#define CTBM_OA_RES1_CTRL_OA1_COMPINT_Pos 8UL
+#define CTBM_OA_RES1_CTRL_OA1_COMPINT_Msk 0x300UL
+#define CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Pos 11UL
+#define CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk 0x800UL
+#define CTBM_OA_RES1_CTRL_OA1_BOOST_EN_Pos 12UL
+#define CTBM_OA_RES1_CTRL_OA1_BOOST_EN_Msk 0x1000UL
+/* CTBM.COMP_STAT */
+#define CTBM_COMP_STAT_OA0_COMP_Pos 0UL
+#define CTBM_COMP_STAT_OA0_COMP_Msk 0x1UL
+#define CTBM_COMP_STAT_OA1_COMP_Pos 16UL
+#define CTBM_COMP_STAT_OA1_COMP_Msk 0x10000UL
+/* CTBM.INTR */
+#define CTBM_INTR_COMP0_Pos 0UL
+#define CTBM_INTR_COMP0_Msk 0x1UL
+#define CTBM_INTR_COMP1_Pos 1UL
+#define CTBM_INTR_COMP1_Msk 0x2UL
+/* CTBM.INTR_SET */
+#define CTBM_INTR_SET_COMP0_SET_Pos 0UL
+#define CTBM_INTR_SET_COMP0_SET_Msk 0x1UL
+#define CTBM_INTR_SET_COMP1_SET_Pos 1UL
+#define CTBM_INTR_SET_COMP1_SET_Msk 0x2UL
+/* CTBM.INTR_MASK */
+#define CTBM_INTR_MASK_COMP0_MASK_Pos 0UL
+#define CTBM_INTR_MASK_COMP0_MASK_Msk 0x1UL
+#define CTBM_INTR_MASK_COMP1_MASK_Pos 1UL
+#define CTBM_INTR_MASK_COMP1_MASK_Msk 0x2UL
+/* CTBM.INTR_MASKED */
+#define CTBM_INTR_MASKED_COMP0_MASKED_Pos 0UL
+#define CTBM_INTR_MASKED_COMP0_MASKED_Msk 0x1UL
+#define CTBM_INTR_MASKED_COMP1_MASKED_Pos 1UL
+#define CTBM_INTR_MASKED_COMP1_MASKED_Msk 0x2UL
+/* CTBM.OA0_SW */
+#define CTBM_OA0_SW_OA0P_A00_Pos 0UL
+#define CTBM_OA0_SW_OA0P_A00_Msk 0x1UL
+#define CTBM_OA0_SW_OA0P_A20_Pos 2UL
+#define CTBM_OA0_SW_OA0P_A20_Msk 0x4UL
+#define CTBM_OA0_SW_OA0P_A30_Pos 3UL
+#define CTBM_OA0_SW_OA0P_A30_Msk 0x8UL
+#define CTBM_OA0_SW_OA0M_A11_Pos 8UL
+#define CTBM_OA0_SW_OA0M_A11_Msk 0x100UL
+#define CTBM_OA0_SW_OA0M_A81_Pos 14UL
+#define CTBM_OA0_SW_OA0M_A81_Msk 0x4000UL
+#define CTBM_OA0_SW_OA0O_D51_Pos 18UL
+#define CTBM_OA0_SW_OA0O_D51_Msk 0x40000UL
+#define CTBM_OA0_SW_OA0O_D81_Pos 21UL
+#define CTBM_OA0_SW_OA0O_D81_Msk 0x200000UL
+/* CTBM.OA0_SW_CLEAR */
+#define CTBM_OA0_SW_CLEAR_OA0P_A00_Pos 0UL
+#define CTBM_OA0_SW_CLEAR_OA0P_A00_Msk 0x1UL
+#define CTBM_OA0_SW_CLEAR_OA0P_A20_Pos 2UL
+#define CTBM_OA0_SW_CLEAR_OA0P_A20_Msk 0x4UL
+#define CTBM_OA0_SW_CLEAR_OA0P_A30_Pos 3UL
+#define CTBM_OA0_SW_CLEAR_OA0P_A30_Msk 0x8UL
+#define CTBM_OA0_SW_CLEAR_OA0M_A11_Pos 8UL
+#define CTBM_OA0_SW_CLEAR_OA0M_A11_Msk 0x100UL
+#define CTBM_OA0_SW_CLEAR_OA0M_A81_Pos 14UL
+#define CTBM_OA0_SW_CLEAR_OA0M_A81_Msk 0x4000UL
+#define CTBM_OA0_SW_CLEAR_OA0O_D51_Pos 18UL
+#define CTBM_OA0_SW_CLEAR_OA0O_D51_Msk 0x40000UL
+#define CTBM_OA0_SW_CLEAR_OA0O_D81_Pos 21UL
+#define CTBM_OA0_SW_CLEAR_OA0O_D81_Msk 0x200000UL
+/* CTBM.OA1_SW */
+#define CTBM_OA1_SW_OA1P_A03_Pos 0UL
+#define CTBM_OA1_SW_OA1P_A03_Msk 0x1UL
+#define CTBM_OA1_SW_OA1P_A13_Pos 1UL
+#define CTBM_OA1_SW_OA1P_A13_Msk 0x2UL
+#define CTBM_OA1_SW_OA1P_A43_Pos 4UL
+#define CTBM_OA1_SW_OA1P_A43_Msk 0x10UL
+#define CTBM_OA1_SW_OA1P_A73_Pos 7UL
+#define CTBM_OA1_SW_OA1P_A73_Msk 0x80UL
+#define CTBM_OA1_SW_OA1M_A22_Pos 8UL
+#define CTBM_OA1_SW_OA1M_A22_Msk 0x100UL
+#define CTBM_OA1_SW_OA1M_A82_Pos 14UL
+#define CTBM_OA1_SW_OA1M_A82_Msk 0x4000UL
+#define CTBM_OA1_SW_OA1O_D52_Pos 18UL
+#define CTBM_OA1_SW_OA1O_D52_Msk 0x40000UL
+#define CTBM_OA1_SW_OA1O_D62_Pos 19UL
+#define CTBM_OA1_SW_OA1O_D62_Msk 0x80000UL
+#define CTBM_OA1_SW_OA1O_D82_Pos 21UL
+#define CTBM_OA1_SW_OA1O_D82_Msk 0x200000UL
+/* CTBM.OA1_SW_CLEAR */
+#define CTBM_OA1_SW_CLEAR_OA1P_A03_Pos 0UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A03_Msk 0x1UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A13_Pos 1UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A13_Msk 0x2UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A43_Pos 4UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A43_Msk 0x10UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A73_Pos 7UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A73_Msk 0x80UL
+#define CTBM_OA1_SW_CLEAR_OA1M_A22_Pos 8UL
+#define CTBM_OA1_SW_CLEAR_OA1M_A22_Msk 0x100UL
+#define CTBM_OA1_SW_CLEAR_OA1M_A82_Pos 14UL
+#define CTBM_OA1_SW_CLEAR_OA1M_A82_Msk 0x4000UL
+#define CTBM_OA1_SW_CLEAR_OA1O_D52_Pos 18UL
+#define CTBM_OA1_SW_CLEAR_OA1O_D52_Msk 0x40000UL
+#define CTBM_OA1_SW_CLEAR_OA1O_D62_Pos 19UL
+#define CTBM_OA1_SW_CLEAR_OA1O_D62_Msk 0x80000UL
+#define CTBM_OA1_SW_CLEAR_OA1O_D82_Pos 21UL
+#define CTBM_OA1_SW_CLEAR_OA1O_D82_Msk 0x200000UL
+/* CTBM.CTD_SW */
+#define CTBM_CTD_SW_CTDD_CRD_Pos 1UL
+#define CTBM_CTD_SW_CTDD_CRD_Msk 0x2UL
+#define CTBM_CTD_SW_CTDS_CRS_Pos 4UL
+#define CTBM_CTD_SW_CTDS_CRS_Msk 0x10UL
+#define CTBM_CTD_SW_CTDS_COR_Pos 5UL
+#define CTBM_CTD_SW_CTDS_COR_Msk 0x20UL
+#define CTBM_CTD_SW_CTDO_C6H_Pos 8UL
+#define CTBM_CTD_SW_CTDO_C6H_Msk 0x100UL
+#define CTBM_CTD_SW_CTDO_COS_Pos 9UL
+#define CTBM_CTD_SW_CTDO_COS_Msk 0x200UL
+#define CTBM_CTD_SW_CTDH_COB_Pos 10UL
+#define CTBM_CTD_SW_CTDH_COB_Msk 0x400UL
+#define CTBM_CTD_SW_CTDH_CHD_Pos 12UL
+#define CTBM_CTD_SW_CTDH_CHD_Msk 0x1000UL
+#define CTBM_CTD_SW_CTDH_CA0_Pos 13UL
+#define CTBM_CTD_SW_CTDH_CA0_Msk 0x2000UL
+#define CTBM_CTD_SW_CTDH_CIS_Pos 14UL
+#define CTBM_CTD_SW_CTDH_CIS_Msk 0x4000UL
+#define CTBM_CTD_SW_CTDH_ILR_Pos 15UL
+#define CTBM_CTD_SW_CTDH_ILR_Msk 0x8000UL
+/* CTBM.CTD_SW_CLEAR */
+#define CTBM_CTD_SW_CLEAR_CTDD_CRD_Pos 1UL
+#define CTBM_CTD_SW_CLEAR_CTDD_CRD_Msk 0x2UL
+#define CTBM_CTD_SW_CLEAR_CTDS_CRS_Pos 4UL
+#define CTBM_CTD_SW_CLEAR_CTDS_CRS_Msk 0x10UL
+#define CTBM_CTD_SW_CLEAR_CTDS_COR_Pos 5UL
+#define CTBM_CTD_SW_CLEAR_CTDS_COR_Msk 0x20UL
+#define CTBM_CTD_SW_CLEAR_CTDO_C6H_Pos 8UL
+#define CTBM_CTD_SW_CLEAR_CTDO_C6H_Msk 0x100UL
+#define CTBM_CTD_SW_CLEAR_CTDO_COS_Pos 9UL
+#define CTBM_CTD_SW_CLEAR_CTDO_COS_Msk 0x200UL
+#define CTBM_CTD_SW_CLEAR_CTDH_COB_Pos 10UL
+#define CTBM_CTD_SW_CLEAR_CTDH_COB_Msk 0x400UL
+#define CTBM_CTD_SW_CLEAR_CTDH_CHD_Pos 12UL
+#define CTBM_CTD_SW_CLEAR_CTDH_CHD_Msk 0x1000UL
+#define CTBM_CTD_SW_CLEAR_CTDH_CA0_Pos 13UL
+#define CTBM_CTD_SW_CLEAR_CTDH_CA0_Msk 0x2000UL
+#define CTBM_CTD_SW_CLEAR_CTDH_CIS_Pos 14UL
+#define CTBM_CTD_SW_CLEAR_CTDH_CIS_Msk 0x4000UL
+#define CTBM_CTD_SW_CLEAR_CTDH_ILR_Pos 15UL
+#define CTBM_CTD_SW_CLEAR_CTDH_ILR_Msk 0x8000UL
+/* CTBM.CTB_SW_DS_CTRL */
+#define CTBM_CTB_SW_DS_CTRL_P2_DS_CTRL23_Pos 10UL
+#define CTBM_CTB_SW_DS_CTRL_P2_DS_CTRL23_Msk 0x400UL
+#define CTBM_CTB_SW_DS_CTRL_P3_DS_CTRL23_Pos 11UL
+#define CTBM_CTB_SW_DS_CTRL_P3_DS_CTRL23_Msk 0x800UL
+#define CTBM_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Pos 31UL
+#define CTBM_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Msk 0x80000000UL
+/* CTBM.CTB_SW_SQ_CTRL */
+#define CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Pos 10UL
+#define CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk 0x400UL
+#define CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Pos 11UL
+#define CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk 0x800UL
+/* CTBM.CTB_SW_STATUS */
+#define CTBM_CTB_SW_STATUS_OA0O_D51_STAT_Pos 28UL
+#define CTBM_CTB_SW_STATUS_OA0O_D51_STAT_Msk 0x10000000UL
+#define CTBM_CTB_SW_STATUS_OA1O_D52_STAT_Pos 29UL
+#define CTBM_CTB_SW_STATUS_OA1O_D52_STAT_Msk 0x20000000UL
+#define CTBM_CTB_SW_STATUS_OA1O_D62_STAT_Pos 30UL
+#define CTBM_CTB_SW_STATUS_OA1O_D62_STAT_Msk 0x40000000UL
+#define CTBM_CTB_SW_STATUS_CTD_COS_STAT_Pos 31UL
+#define CTBM_CTB_SW_STATUS_CTD_COS_STAT_Msk 0x80000000UL
+/* CTBM.OA0_OFFSET_TRIM */
+#define CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Pos 0UL
+#define CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Msk 0x3FUL
+/* CTBM.OA0_SLOPE_OFFSET_TRIM */
+#define CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Pos 0UL
+#define CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Msk 0x3FUL
+/* CTBM.OA0_COMP_TRIM */
+#define CTBM_OA0_COMP_TRIM_OA0_COMP_TRIM_Pos 0UL
+#define CTBM_OA0_COMP_TRIM_OA0_COMP_TRIM_Msk 0x3UL
+/* CTBM.OA1_OFFSET_TRIM */
+#define CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Pos 0UL
+#define CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Msk 0x3FUL
+/* CTBM.OA1_SLOPE_OFFSET_TRIM */
+#define CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Pos 0UL
+#define CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Msk 0x3FUL
+/* CTBM.OA1_COMP_TRIM */
+#define CTBM_OA1_COMP_TRIM_OA1_COMP_TRIM_Pos 0UL
+#define CTBM_OA1_COMP_TRIM_OA1_COMP_TRIM_Msk 0x3UL
+
+
+#endif /* _CYIP_CTBM_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_ctdac.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_ctdac.h
new file mode 100644
index 0000000000..b40fd990a9
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_ctdac.h
@@ -0,0 +1,114 @@
+/***************************************************************************//**
+* \file cyip_ctdac.h
+*
+* \brief
+* CTDAC IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_CTDAC_H_
+#define _CYIP_CTDAC_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* CTDAC
+*******************************************************************************/
+
+#define CTDAC_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Continuous Time DAC (CTDAC)
+ */
+typedef struct {
+ __IOM uint32_t CTDAC_CTRL; /*!< 0x00000000 Global CTDAC control */
+ __IM uint32_t RESERVED[7];
+ __IOM uint32_t INTR; /*!< 0x00000020 Interrupt request register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt request set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt request mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt request masked */
+ __IM uint32_t RESERVED1[32];
+ __IOM uint32_t CTDAC_SW; /*!< 0x000000B0 CTDAC switch control */
+ __IOM uint32_t CTDAC_SW_CLEAR; /*!< 0x000000B4 CTDAC switch control clear */
+ __IM uint32_t RESERVED2[18];
+ __IOM uint32_t CTDAC_VAL; /*!< 0x00000100 DAC Value */
+ __IOM uint32_t CTDAC_VAL_NXT; /*!< 0x00000104 Next DAC value (double buffering) */
+} CTDAC_V1_Type; /*!< Size = 264 (0x108) */
+
+
+/* CTDAC.CTDAC_CTRL */
+#define CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Pos 0UL
+#define CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk 0x3FUL
+#define CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Pos 8UL
+#define CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk 0x100UL
+#define CTDAC_CTDAC_CTRL_DEGLITCH_COS_Pos 9UL
+#define CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk 0x200UL
+#define CTDAC_CTDAC_CTRL_OUT_EN_Pos 22UL
+#define CTDAC_CTDAC_CTRL_OUT_EN_Msk 0x400000UL
+#define CTDAC_CTDAC_CTRL_CTDAC_RANGE_Pos 23UL
+#define CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk 0x800000UL
+#define CTDAC_CTDAC_CTRL_CTDAC_MODE_Pos 24UL
+#define CTDAC_CTDAC_CTRL_CTDAC_MODE_Msk 0x3000000UL
+#define CTDAC_CTDAC_CTRL_DISABLED_MODE_Pos 27UL
+#define CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk 0x8000000UL
+#define CTDAC_CTDAC_CTRL_DSI_STROBE_EN_Pos 28UL
+#define CTDAC_CTDAC_CTRL_DSI_STROBE_EN_Msk 0x10000000UL
+#define CTDAC_CTDAC_CTRL_DSI_STROBE_LEVEL_Pos 29UL
+#define CTDAC_CTDAC_CTRL_DSI_STROBE_LEVEL_Msk 0x20000000UL
+#define CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Pos 30UL
+#define CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL
+#define CTDAC_CTDAC_CTRL_ENABLED_Pos 31UL
+#define CTDAC_CTDAC_CTRL_ENABLED_Msk 0x80000000UL
+/* CTDAC.INTR */
+#define CTDAC_INTR_VDAC_EMPTY_Pos 0UL
+#define CTDAC_INTR_VDAC_EMPTY_Msk 0x1UL
+/* CTDAC.INTR_SET */
+#define CTDAC_INTR_SET_VDAC_EMPTY_SET_Pos 0UL
+#define CTDAC_INTR_SET_VDAC_EMPTY_SET_Msk 0x1UL
+/* CTDAC.INTR_MASK */
+#define CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Pos 0UL
+#define CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Msk 0x1UL
+/* CTDAC.INTR_MASKED */
+#define CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Pos 0UL
+#define CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Msk 0x1UL
+/* CTDAC.CTDAC_SW */
+#define CTDAC_CTDAC_SW_CTDD_CVD_Pos 0UL
+#define CTDAC_CTDAC_SW_CTDD_CVD_Msk 0x1UL
+#define CTDAC_CTDAC_SW_CTDO_CO6_Pos 8UL
+#define CTDAC_CTDAC_SW_CTDO_CO6_Msk 0x100UL
+/* CTDAC.CTDAC_SW_CLEAR */
+#define CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Pos 0UL
+#define CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk 0x1UL
+#define CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Pos 8UL
+#define CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Msk 0x100UL
+/* CTDAC.CTDAC_VAL */
+#define CTDAC_CTDAC_VAL_VALUE_Pos 0UL
+#define CTDAC_CTDAC_VAL_VALUE_Msk 0xFFFUL
+/* CTDAC.CTDAC_VAL_NXT */
+#define CTDAC_CTDAC_VAL_NXT_VALUE_Pos 0UL
+#define CTDAC_CTDAC_VAL_NXT_VALUE_Msk 0xFFFUL
+
+
+#endif /* _CYIP_CTDAC_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_dmac_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_dmac_v2.h
new file mode 100644
index 0000000000..1b9d340197
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_dmac_v2.h
@@ -0,0 +1,243 @@
+/***************************************************************************//**
+* \file cyip_dmac_v2.h
+*
+* \brief
+* DMAC IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_DMAC_V2_H_
+#define _CYIP_DMAC_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* DMAC
+*******************************************************************************/
+
+#define DMAC_CH_V2_SECTION_SIZE 0x00000100UL
+#define DMAC_V2_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief DMA controller channel (DMAC_CH)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Channel control */
+ __IM uint32_t RESERVED[3];
+ __IM uint32_t IDX; /*!< 0x00000010 Channel current indices */
+ __IM uint32_t SRC; /*!< 0x00000014 Channel current source address */
+ __IM uint32_t DST; /*!< 0x00000018 Channel current destination address */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t CURR; /*!< 0x00000020 Channel current descriptor pointer */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t TR_CMD; /*!< 0x00000028 Channle software trigger */
+ __IM uint32_t RESERVED3[5];
+ __IM uint32_t DESCR_STATUS; /*!< 0x00000040 Channel descriptor status */
+ __IM uint32_t RESERVED4[7];
+ __IM uint32_t DESCR_CTL; /*!< 0x00000060 Channel descriptor control */
+ __IM uint32_t DESCR_SRC; /*!< 0x00000064 Channel descriptor source */
+ __IM uint32_t DESCR_DST; /*!< 0x00000068 Channel descriptor destination */
+ __IM uint32_t DESCR_X_SIZE; /*!< 0x0000006C Channel descriptor X size */
+ __IM uint32_t DESCR_X_INCR; /*!< 0x00000070 Channel descriptor X increment */
+ __IM uint32_t DESCR_Y_SIZE; /*!< 0x00000074 Channel descriptor Y size */
+ __IM uint32_t DESCR_Y_INCR; /*!< 0x00000078 Channel descriptor Y increment */
+ __IM uint32_t DESCR_NEXT; /*!< 0x0000007C Channel descriptor next pointer */
+ __IOM uint32_t INTR; /*!< 0x00000080 Interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x00000084 Interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000088 Interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000008C Interrupt masked */
+ __IM uint32_t RESERVED5[28];
+} DMAC_CH_V2_Type; /*!< Size = 256 (0x100) */
+
+/**
+ * \brief DMAC (DMAC)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t RESERVED;
+ __IM uint32_t ACTIVE; /*!< 0x00000008 Active channels */
+ __IM uint32_t RESERVED1[1021];
+ DMAC_CH_V2_Type CH[8]; /*!< 0x00001000 DMA controller channel */
+} DMAC_V2_Type; /*!< Size = 6144 (0x1800) */
+
+
+/* DMAC_CH.CTL */
+#define DMAC_CH_V2_CTL_P_Pos 0UL
+#define DMAC_CH_V2_CTL_P_Msk 0x1UL
+#define DMAC_CH_V2_CTL_NS_Pos 1UL
+#define DMAC_CH_V2_CTL_NS_Msk 0x2UL
+#define DMAC_CH_V2_CTL_B_Pos 2UL
+#define DMAC_CH_V2_CTL_B_Msk 0x4UL
+#define DMAC_CH_V2_CTL_PC_Pos 4UL
+#define DMAC_CH_V2_CTL_PC_Msk 0xF0UL
+#define DMAC_CH_V2_CTL_PRIO_Pos 8UL
+#define DMAC_CH_V2_CTL_PRIO_Msk 0x300UL
+#define DMAC_CH_V2_CTL_ENABLED_Pos 31UL
+#define DMAC_CH_V2_CTL_ENABLED_Msk 0x80000000UL
+/* DMAC_CH.IDX */
+#define DMAC_CH_V2_IDX_X_Pos 0UL
+#define DMAC_CH_V2_IDX_X_Msk 0xFFFFUL
+#define DMAC_CH_V2_IDX_Y_Pos 16UL
+#define DMAC_CH_V2_IDX_Y_Msk 0xFFFF0000UL
+/* DMAC_CH.SRC */
+#define DMAC_CH_V2_SRC_ADDR_Pos 0UL
+#define DMAC_CH_V2_SRC_ADDR_Msk 0xFFFFFFFFUL
+/* DMAC_CH.DST */
+#define DMAC_CH_V2_DST_ADDR_Pos 0UL
+#define DMAC_CH_V2_DST_ADDR_Msk 0xFFFFFFFFUL
+/* DMAC_CH.CURR */
+#define DMAC_CH_V2_CURR_PTR_Pos 2UL
+#define DMAC_CH_V2_CURR_PTR_Msk 0xFFFFFFFCUL
+/* DMAC_CH.TR_CMD */
+#define DMAC_CH_V2_TR_CMD_ACTIVATE_Pos 0UL
+#define DMAC_CH_V2_TR_CMD_ACTIVATE_Msk 0x1UL
+/* DMAC_CH.DESCR_STATUS */
+#define DMAC_CH_V2_DESCR_STATUS_VALID_Pos 31UL
+#define DMAC_CH_V2_DESCR_STATUS_VALID_Msk 0x80000000UL
+/* DMAC_CH.DESCR_CTL */
+#define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL
+#define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL
+#define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Pos 2UL
+#define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Msk 0xCUL
+#define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Pos 4UL
+#define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Msk 0x30UL
+#define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Pos 6UL
+#define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Msk 0xC0UL
+#define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Pos 8UL
+#define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Msk 0x100UL
+#define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Pos 16UL
+#define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Msk 0x30000UL
+#define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Pos 24UL
+#define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Msk 0x1000000UL
+#define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Pos 26UL
+#define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Msk 0x4000000UL
+#define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Pos 27UL
+#define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Msk 0x8000000UL
+#define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Pos 28UL
+#define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Msk 0x70000000UL
+/* DMAC_CH.DESCR_SRC */
+#define DMAC_CH_V2_DESCR_SRC_ADDR_Pos 0UL
+#define DMAC_CH_V2_DESCR_SRC_ADDR_Msk 0xFFFFFFFFUL
+/* DMAC_CH.DESCR_DST */
+#define DMAC_CH_V2_DESCR_DST_ADDR_Pos 0UL
+#define DMAC_CH_V2_DESCR_DST_ADDR_Msk 0xFFFFFFFFUL
+/* DMAC_CH.DESCR_X_SIZE */
+#define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Pos 0UL
+#define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Msk 0xFFFFUL
+/* DMAC_CH.DESCR_X_INCR */
+#define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Pos 0UL
+#define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Msk 0xFFFFUL
+#define DMAC_CH_V2_DESCR_X_INCR_DST_X_Pos 16UL
+#define DMAC_CH_V2_DESCR_X_INCR_DST_X_Msk 0xFFFF0000UL
+/* DMAC_CH.DESCR_Y_SIZE */
+#define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Pos 0UL
+#define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Msk 0xFFFFUL
+/* DMAC_CH.DESCR_Y_INCR */
+#define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Pos 0UL
+#define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Msk 0xFFFFUL
+#define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Pos 16UL
+#define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Msk 0xFFFF0000UL
+/* DMAC_CH.DESCR_NEXT */
+#define DMAC_CH_V2_DESCR_NEXT_PTR_Pos 2UL
+#define DMAC_CH_V2_DESCR_NEXT_PTR_Msk 0xFFFFFFFCUL
+/* DMAC_CH.INTR */
+#define DMAC_CH_V2_INTR_COMPLETION_Pos 0UL
+#define DMAC_CH_V2_INTR_COMPLETION_Msk 0x1UL
+#define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Pos 1UL
+#define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Msk 0x2UL
+#define DMAC_CH_V2_INTR_DST_BUS_ERROR_Pos 2UL
+#define DMAC_CH_V2_INTR_DST_BUS_ERROR_Msk 0x4UL
+#define DMAC_CH_V2_INTR_SRC_MISAL_Pos 3UL
+#define DMAC_CH_V2_INTR_SRC_MISAL_Msk 0x8UL
+#define DMAC_CH_V2_INTR_DST_MISAL_Pos 4UL
+#define DMAC_CH_V2_INTR_DST_MISAL_Msk 0x10UL
+#define DMAC_CH_V2_INTR_CURR_PTR_NULL_Pos 5UL
+#define DMAC_CH_V2_INTR_CURR_PTR_NULL_Msk 0x20UL
+#define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Pos 6UL
+#define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Msk 0x40UL
+#define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Pos 7UL
+#define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Msk 0x80UL
+/* DMAC_CH.INTR_SET */
+#define DMAC_CH_V2_INTR_SET_COMPLETION_Pos 0UL
+#define DMAC_CH_V2_INTR_SET_COMPLETION_Msk 0x1UL
+#define DMAC_CH_V2_INTR_SET_SRC_BUS_ERROR_Pos 1UL
+#define DMAC_CH_V2_INTR_SET_SRC_BUS_ERROR_Msk 0x2UL
+#define DMAC_CH_V2_INTR_SET_DST_BUS_ERROR_Pos 2UL
+#define DMAC_CH_V2_INTR_SET_DST_BUS_ERROR_Msk 0x4UL
+#define DMAC_CH_V2_INTR_SET_SRC_MISAL_Pos 3UL
+#define DMAC_CH_V2_INTR_SET_SRC_MISAL_Msk 0x8UL
+#define DMAC_CH_V2_INTR_SET_DST_MISAL_Pos 4UL
+#define DMAC_CH_V2_INTR_SET_DST_MISAL_Msk 0x10UL
+#define DMAC_CH_V2_INTR_SET_CURR_PTR_NULL_Pos 5UL
+#define DMAC_CH_V2_INTR_SET_CURR_PTR_NULL_Msk 0x20UL
+#define DMAC_CH_V2_INTR_SET_ACTIVE_CH_DISABLED_Pos 6UL
+#define DMAC_CH_V2_INTR_SET_ACTIVE_CH_DISABLED_Msk 0x40UL
+#define DMAC_CH_V2_INTR_SET_DESCR_BUS_ERROR_Pos 7UL
+#define DMAC_CH_V2_INTR_SET_DESCR_BUS_ERROR_Msk 0x80UL
+/* DMAC_CH.INTR_MASK */
+#define DMAC_CH_V2_INTR_MASK_COMPLETION_Pos 0UL
+#define DMAC_CH_V2_INTR_MASK_COMPLETION_Msk 0x1UL
+#define DMAC_CH_V2_INTR_MASK_SRC_BUS_ERROR_Pos 1UL
+#define DMAC_CH_V2_INTR_MASK_SRC_BUS_ERROR_Msk 0x2UL
+#define DMAC_CH_V2_INTR_MASK_DST_BUS_ERROR_Pos 2UL
+#define DMAC_CH_V2_INTR_MASK_DST_BUS_ERROR_Msk 0x4UL
+#define DMAC_CH_V2_INTR_MASK_SRC_MISAL_Pos 3UL
+#define DMAC_CH_V2_INTR_MASK_SRC_MISAL_Msk 0x8UL
+#define DMAC_CH_V2_INTR_MASK_DST_MISAL_Pos 4UL
+#define DMAC_CH_V2_INTR_MASK_DST_MISAL_Msk 0x10UL
+#define DMAC_CH_V2_INTR_MASK_CURR_PTR_NULL_Pos 5UL
+#define DMAC_CH_V2_INTR_MASK_CURR_PTR_NULL_Msk 0x20UL
+#define DMAC_CH_V2_INTR_MASK_ACTIVE_CH_DISABLED_Pos 6UL
+#define DMAC_CH_V2_INTR_MASK_ACTIVE_CH_DISABLED_Msk 0x40UL
+#define DMAC_CH_V2_INTR_MASK_DESCR_BUS_ERROR_Pos 7UL
+#define DMAC_CH_V2_INTR_MASK_DESCR_BUS_ERROR_Msk 0x80UL
+/* DMAC_CH.INTR_MASKED */
+#define DMAC_CH_V2_INTR_MASKED_COMPLETION_Pos 0UL
+#define DMAC_CH_V2_INTR_MASKED_COMPLETION_Msk 0x1UL
+#define DMAC_CH_V2_INTR_MASKED_SRC_BUS_ERROR_Pos 1UL
+#define DMAC_CH_V2_INTR_MASKED_SRC_BUS_ERROR_Msk 0x2UL
+#define DMAC_CH_V2_INTR_MASKED_DST_BUS_ERROR_Pos 2UL
+#define DMAC_CH_V2_INTR_MASKED_DST_BUS_ERROR_Msk 0x4UL
+#define DMAC_CH_V2_INTR_MASKED_SRC_MISAL_Pos 3UL
+#define DMAC_CH_V2_INTR_MASKED_SRC_MISAL_Msk 0x8UL
+#define DMAC_CH_V2_INTR_MASKED_DST_MISAL_Pos 4UL
+#define DMAC_CH_V2_INTR_MASKED_DST_MISAL_Msk 0x10UL
+#define DMAC_CH_V2_INTR_MASKED_CURR_PTR_NULL_Pos 5UL
+#define DMAC_CH_V2_INTR_MASKED_CURR_PTR_NULL_Msk 0x20UL
+#define DMAC_CH_V2_INTR_MASKED_ACTIVE_CH_DISABLED_Pos 6UL
+#define DMAC_CH_V2_INTR_MASKED_ACTIVE_CH_DISABLED_Msk 0x40UL
+#define DMAC_CH_V2_INTR_MASKED_DESCR_BUS_ERROR_Pos 7UL
+#define DMAC_CH_V2_INTR_MASKED_DESCR_BUS_ERROR_Msk 0x80UL
+
+
+/* DMAC.CTL */
+#define DMAC_V2_CTL_ENABLED_Pos 31UL
+#define DMAC_V2_CTL_ENABLED_Msk 0x80000000UL
+/* DMAC.ACTIVE */
+#define DMAC_V2_ACTIVE_ACTIVE_Pos 0UL
+#define DMAC_V2_ACTIVE_ACTIVE_Msk 0xFFUL
+
+
+#endif /* _CYIP_DMAC_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_dw.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_dw.h
new file mode 100644
index 0000000000..5f9a36e3fd
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_dw.h
@@ -0,0 +1,180 @@
+/***************************************************************************//**
+* \file cyip_dw.h
+*
+* \brief
+* DW IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_DW_H_
+#define _CYIP_DW_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* DW
+*******************************************************************************/
+
+#define DW_CH_STRUCT_SECTION_SIZE 0x00000020UL
+#define DW_SECTION_SIZE 0x00001000UL
+
+/**
+ * \brief DW channel structure (DW_CH_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t CH_CTL; /*!< 0x00000000 Channel control */
+ __IM uint32_t CH_STATUS; /*!< 0x00000004 Channel status */
+ __IOM uint32_t CH_IDX; /*!< 0x00000008 Channel current indices */
+ __IOM uint32_t CH_CURR_PTR; /*!< 0x0000000C Channel current descriptor pointer */
+ __IOM uint32_t INTR; /*!< 0x00000010 Interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked */
+} DW_CH_STRUCT_V1_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief Datawire Controller (DW)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t STATUS; /*!< 0x00000004 Status */
+ __IM uint32_t PENDING; /*!< 0x00000008 Pending channels */
+ __IM uint32_t RESERVED;
+ __IM uint32_t STATUS_INTR; /*!< 0x00000010 System interrupt control */
+ __IM uint32_t STATUS_INTR_MASKED; /*!< 0x00000014 Status of interrupts masked */
+ __IM uint32_t RESERVED1[2];
+ __IM uint32_t ACT_DESCR_CTL; /*!< 0x00000020 Active descriptor control */
+ __IM uint32_t ACT_DESCR_SRC; /*!< 0x00000024 Active descriptor source */
+ __IM uint32_t ACT_DESCR_DST; /*!< 0x00000028 Active descriptor destination */
+ __IM uint32_t RESERVED2;
+ __IM uint32_t ACT_DESCR_X_CTL; /*!< 0x00000030 Active descriptor X loop control */
+ __IM uint32_t ACT_DESCR_Y_CTL; /*!< 0x00000034 Active descriptor Y loop control */
+ __IM uint32_t ACT_DESCR_NEXT_PTR; /*!< 0x00000038 Active descriptor next pointer */
+ __IM uint32_t RESERVED3;
+ __IM uint32_t ACT_SRC; /*!< 0x00000040 Active source */
+ __IM uint32_t ACT_DST; /*!< 0x00000044 Active destination */
+ __IM uint32_t RESERVED4[494];
+ DW_CH_STRUCT_V1_Type CH_STRUCT[32]; /*!< 0x00000800 DW channel structure */
+} DW_V1_Type; /*!< Size = 3072 (0xC00) */
+
+
+/* DW_CH_STRUCT.CH_CTL */
+#define DW_CH_STRUCT_CH_CTL_P_Pos 0UL
+#define DW_CH_STRUCT_CH_CTL_P_Msk 0x1UL
+#define DW_CH_STRUCT_CH_CTL_NS_Pos 1UL
+#define DW_CH_STRUCT_CH_CTL_NS_Msk 0x2UL
+#define DW_CH_STRUCT_CH_CTL_B_Pos 2UL
+#define DW_CH_STRUCT_CH_CTL_B_Msk 0x4UL
+#define DW_CH_STRUCT_CH_CTL_PC_Pos 4UL
+#define DW_CH_STRUCT_CH_CTL_PC_Msk 0xF0UL
+#define DW_CH_STRUCT_CH_CTL_PRIO_Pos 16UL
+#define DW_CH_STRUCT_CH_CTL_PRIO_Msk 0x30000UL
+#define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos 18UL
+#define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Msk 0x40000UL
+#define DW_CH_STRUCT_CH_CTL_ENABLED_Pos 31UL
+#define DW_CH_STRUCT_CH_CTL_ENABLED_Msk 0x80000000UL
+/* DW_CH_STRUCT.CH_STATUS */
+#define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Pos 0UL
+#define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Msk 0xFUL
+/* DW_CH_STRUCT.CH_IDX */
+#define DW_CH_STRUCT_CH_IDX_X_IDX_Pos 0UL
+#define DW_CH_STRUCT_CH_IDX_X_IDX_Msk 0xFFUL
+#define DW_CH_STRUCT_CH_IDX_Y_IDX_Pos 8UL
+#define DW_CH_STRUCT_CH_IDX_Y_IDX_Msk 0xFF00UL
+/* DW_CH_STRUCT.CH_CURR_PTR */
+#define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Pos 2UL
+#define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Msk 0xFFFFFFFCUL
+/* DW_CH_STRUCT.INTR */
+#define DW_CH_STRUCT_INTR_CH_Pos 0UL
+#define DW_CH_STRUCT_INTR_CH_Msk 0x1UL
+/* DW_CH_STRUCT.INTR_SET */
+#define DW_CH_STRUCT_INTR_SET_CH_Pos 0UL
+#define DW_CH_STRUCT_INTR_SET_CH_Msk 0x1UL
+/* DW_CH_STRUCT.INTR_MASK */
+#define DW_CH_STRUCT_INTR_MASK_CH_Pos 0UL
+#define DW_CH_STRUCT_INTR_MASK_CH_Msk 0x1UL
+/* DW_CH_STRUCT.INTR_MASKED */
+#define DW_CH_STRUCT_INTR_MASKED_CH_Pos 0UL
+#define DW_CH_STRUCT_INTR_MASKED_CH_Msk 0x1UL
+
+
+/* DW.CTL */
+#define DW_CTL_ENABLED_Pos 31UL
+#define DW_CTL_ENABLED_Msk 0x80000000UL
+/* DW.STATUS */
+#define DW_STATUS_P_Pos 0UL
+#define DW_STATUS_P_Msk 0x1UL
+#define DW_STATUS_NS_Pos 1UL
+#define DW_STATUS_NS_Msk 0x2UL
+#define DW_STATUS_B_Pos 2UL
+#define DW_STATUS_B_Msk 0x4UL
+#define DW_STATUS_PC_Pos 4UL
+#define DW_STATUS_PC_Msk 0xF0UL
+#define DW_STATUS_CH_IDX_Pos 8UL
+#define DW_STATUS_CH_IDX_Msk 0x1F00UL
+#define DW_STATUS_PRIO_Pos 16UL
+#define DW_STATUS_PRIO_Msk 0x30000UL
+#define DW_STATUS_PREEMPTABLE_Pos 18UL
+#define DW_STATUS_PREEMPTABLE_Msk 0x40000UL
+#define DW_STATUS_STATE_Pos 20UL
+#define DW_STATUS_STATE_Msk 0x700000UL
+#define DW_STATUS_ACTIVE_Pos 31UL
+#define DW_STATUS_ACTIVE_Msk 0x80000000UL
+/* DW.PENDING */
+#define DW_PENDING_CH_PENDING_Pos 0UL
+#define DW_PENDING_CH_PENDING_Msk 0xFFFFFFFFUL
+/* DW.STATUS_INTR */
+#define DW_STATUS_INTR_CH_Pos 0UL
+#define DW_STATUS_INTR_CH_Msk 0xFFFFFFFFUL
+/* DW.STATUS_INTR_MASKED */
+#define DW_STATUS_INTR_MASKED_CH_Pos 0UL
+#define DW_STATUS_INTR_MASKED_CH_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_CTL */
+#define DW_ACT_DESCR_CTL_DATA_Pos 0UL
+#define DW_ACT_DESCR_CTL_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_SRC */
+#define DW_ACT_DESCR_SRC_DATA_Pos 0UL
+#define DW_ACT_DESCR_SRC_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_DST */
+#define DW_ACT_DESCR_DST_DATA_Pos 0UL
+#define DW_ACT_DESCR_DST_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_X_CTL */
+#define DW_ACT_DESCR_X_CTL_DATA_Pos 0UL
+#define DW_ACT_DESCR_X_CTL_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_Y_CTL */
+#define DW_ACT_DESCR_Y_CTL_DATA_Pos 0UL
+#define DW_ACT_DESCR_Y_CTL_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_NEXT_PTR */
+#define DW_ACT_DESCR_NEXT_PTR_ADDR_Pos 2UL
+#define DW_ACT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL
+/* DW.ACT_SRC */
+#define DW_ACT_SRC_SRC_ADDR_Pos 0UL
+#define DW_ACT_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL
+/* DW.ACT_DST */
+#define DW_ACT_DST_DST_ADDR_Pos 0UL
+#define DW_ACT_DST_DST_ADDR_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_DW_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_dw_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_dw_v2.h
new file mode 100644
index 0000000000..4dd7bb35ba
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_dw_v2.h
@@ -0,0 +1,225 @@
+/***************************************************************************//**
+* \file cyip_dw_v2.h
+*
+* \brief
+* DW IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_DW_V2_H_
+#define _CYIP_DW_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* DW
+*******************************************************************************/
+
+#define DW_CH_STRUCT_V2_SECTION_SIZE 0x00000040UL
+#define DW_V2_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief DW channel structure (DW_CH_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t CH_CTL; /*!< 0x00000000 Channel control */
+ __IM uint32_t CH_STATUS; /*!< 0x00000004 Channel status */
+ __IOM uint32_t CH_IDX; /*!< 0x00000008 Channel current indices */
+ __IOM uint32_t CH_CURR_PTR; /*!< 0x0000000C Channel current descriptor pointer */
+ __IOM uint32_t INTR; /*!< 0x00000010 Interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked */
+ __IOM uint32_t SRAM_DATA0; /*!< 0x00000020 SRAM data 0 */
+ __IOM uint32_t SRAM_DATA1; /*!< 0x00000024 SRAM data 1 */
+ __IOM uint32_t TR_CMD; /*!< 0x00000028 Channel software trigger */
+ __IM uint32_t RESERVED[5];
+} DW_CH_STRUCT_V2_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief Datawire Controller (DW)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t STATUS; /*!< 0x00000004 Status */
+ __IM uint32_t RESERVED[6];
+ __IM uint32_t ACT_DESCR_CTL; /*!< 0x00000020 Active descriptor control */
+ __IM uint32_t ACT_DESCR_SRC; /*!< 0x00000024 Active descriptor source */
+ __IM uint32_t ACT_DESCR_DST; /*!< 0x00000028 Active descriptor destination */
+ __IM uint32_t RESERVED1;
+ __IM uint32_t ACT_DESCR_X_CTL; /*!< 0x00000030 Active descriptor X loop control */
+ __IM uint32_t ACT_DESCR_Y_CTL; /*!< 0x00000034 Active descriptor Y loop control */
+ __IM uint32_t ACT_DESCR_NEXT_PTR; /*!< 0x00000038 Active descriptor next pointer */
+ __IM uint32_t RESERVED2;
+ __IM uint32_t ACT_SRC; /*!< 0x00000040 Active source */
+ __IM uint32_t ACT_DST; /*!< 0x00000044 Active destination */
+ __IM uint32_t RESERVED3[14];
+ __IOM uint32_t ECC_CTL; /*!< 0x00000080 ECC control */
+ __IM uint32_t RESERVED4[31];
+ __IOM uint32_t CRC_CTL; /*!< 0x00000100 CRC control */
+ __IM uint32_t RESERVED5[3];
+ __IOM uint32_t CRC_DATA_CTL; /*!< 0x00000110 CRC data control */
+ __IM uint32_t RESERVED6[3];
+ __IOM uint32_t CRC_POL_CTL; /*!< 0x00000120 CRC polynomial control */
+ __IM uint32_t RESERVED7[3];
+ __IOM uint32_t CRC_LFSR_CTL; /*!< 0x00000130 CRC LFSR control */
+ __IM uint32_t RESERVED8[3];
+ __IOM uint32_t CRC_REM_CTL; /*!< 0x00000140 CRC remainder control */
+ __IM uint32_t RESERVED9;
+ __IM uint32_t CRC_REM_RESULT; /*!< 0x00000148 CRC remainder result */
+ __IM uint32_t RESERVED10[8109];
+ DW_CH_STRUCT_V2_Type CH_STRUCT[512]; /*!< 0x00008000 DW channel structure */
+} DW_V2_Type; /*!< Size = 65536 (0x10000) */
+
+
+/* DW_CH_STRUCT.CH_CTL */
+#define DW_CH_STRUCT_V2_CH_CTL_P_Pos 0UL
+#define DW_CH_STRUCT_V2_CH_CTL_P_Msk 0x1UL
+#define DW_CH_STRUCT_V2_CH_CTL_NS_Pos 1UL
+#define DW_CH_STRUCT_V2_CH_CTL_NS_Msk 0x2UL
+#define DW_CH_STRUCT_V2_CH_CTL_B_Pos 2UL
+#define DW_CH_STRUCT_V2_CH_CTL_B_Msk 0x4UL
+#define DW_CH_STRUCT_V2_CH_CTL_PC_Pos 4UL
+#define DW_CH_STRUCT_V2_CH_CTL_PC_Msk 0xF0UL
+#define DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos 8UL
+#define DW_CH_STRUCT_V2_CH_CTL_PRIO_Msk 0x300UL
+#define DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos 11UL
+#define DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Msk 0x800UL
+#define DW_CH_STRUCT_V2_CH_CTL_ENABLED_Pos 31UL
+#define DW_CH_STRUCT_V2_CH_CTL_ENABLED_Msk 0x80000000UL
+/* DW_CH_STRUCT.CH_STATUS */
+#define DW_CH_STRUCT_V2_CH_STATUS_INTR_CAUSE_Pos 0UL
+#define DW_CH_STRUCT_V2_CH_STATUS_INTR_CAUSE_Msk 0xFUL
+#define DW_CH_STRUCT_V2_CH_STATUS_PENDING_Pos 31UL
+#define DW_CH_STRUCT_V2_CH_STATUS_PENDING_Msk 0x80000000UL
+/* DW_CH_STRUCT.CH_IDX */
+#define DW_CH_STRUCT_V2_CH_IDX_X_IDX_Pos 0UL
+#define DW_CH_STRUCT_V2_CH_IDX_X_IDX_Msk 0xFFUL
+#define DW_CH_STRUCT_V2_CH_IDX_Y_IDX_Pos 8UL
+#define DW_CH_STRUCT_V2_CH_IDX_Y_IDX_Msk 0xFF00UL
+/* DW_CH_STRUCT.CH_CURR_PTR */
+#define DW_CH_STRUCT_V2_CH_CURR_PTR_ADDR_Pos 2UL
+#define DW_CH_STRUCT_V2_CH_CURR_PTR_ADDR_Msk 0xFFFFFFFCUL
+/* DW_CH_STRUCT.INTR */
+#define DW_CH_STRUCT_V2_INTR_CH_Pos 0UL
+#define DW_CH_STRUCT_V2_INTR_CH_Msk 0x1UL
+/* DW_CH_STRUCT.INTR_SET */
+#define DW_CH_STRUCT_V2_INTR_SET_CH_Pos 0UL
+#define DW_CH_STRUCT_V2_INTR_SET_CH_Msk 0x1UL
+/* DW_CH_STRUCT.INTR_MASK */
+#define DW_CH_STRUCT_V2_INTR_MASK_CH_Pos 0UL
+#define DW_CH_STRUCT_V2_INTR_MASK_CH_Msk 0x1UL
+/* DW_CH_STRUCT.INTR_MASKED */
+#define DW_CH_STRUCT_V2_INTR_MASKED_CH_Pos 0UL
+#define DW_CH_STRUCT_V2_INTR_MASKED_CH_Msk 0x1UL
+/* DW_CH_STRUCT.SRAM_DATA0 */
+#define DW_CH_STRUCT_V2_SRAM_DATA0_DATA_Pos 0UL
+#define DW_CH_STRUCT_V2_SRAM_DATA0_DATA_Msk 0xFFFFFFFFUL
+/* DW_CH_STRUCT.SRAM_DATA1 */
+#define DW_CH_STRUCT_V2_SRAM_DATA1_DATA_Pos 0UL
+#define DW_CH_STRUCT_V2_SRAM_DATA1_DATA_Msk 0xFFFFFFFFUL
+/* DW_CH_STRUCT.TR_CMD */
+#define DW_CH_STRUCT_V2_TR_CMD_ACTIVATE_Pos 0UL
+#define DW_CH_STRUCT_V2_TR_CMD_ACTIVATE_Msk 0x1UL
+
+
+/* DW.CTL */
+#define DW_V2_CTL_ECC_EN_Pos 0UL
+#define DW_V2_CTL_ECC_EN_Msk 0x1UL
+#define DW_V2_CTL_ECC_INJ_EN_Pos 1UL
+#define DW_V2_CTL_ECC_INJ_EN_Msk 0x2UL
+#define DW_V2_CTL_ENABLED_Pos 31UL
+#define DW_V2_CTL_ENABLED_Msk 0x80000000UL
+/* DW.STATUS */
+#define DW_V2_STATUS_P_Pos 0UL
+#define DW_V2_STATUS_P_Msk 0x1UL
+#define DW_V2_STATUS_NS_Pos 1UL
+#define DW_V2_STATUS_NS_Msk 0x2UL
+#define DW_V2_STATUS_B_Pos 2UL
+#define DW_V2_STATUS_B_Msk 0x4UL
+#define DW_V2_STATUS_PC_Pos 4UL
+#define DW_V2_STATUS_PC_Msk 0xF0UL
+#define DW_V2_STATUS_PRIO_Pos 8UL
+#define DW_V2_STATUS_PRIO_Msk 0x300UL
+#define DW_V2_STATUS_PREEMPTABLE_Pos 11UL
+#define DW_V2_STATUS_PREEMPTABLE_Msk 0x800UL
+#define DW_V2_STATUS_CH_IDX_Pos 16UL
+#define DW_V2_STATUS_CH_IDX_Msk 0x1FF0000UL
+#define DW_V2_STATUS_STATE_Pos 28UL
+#define DW_V2_STATUS_STATE_Msk 0x70000000UL
+#define DW_V2_STATUS_ACTIVE_Pos 31UL
+#define DW_V2_STATUS_ACTIVE_Msk 0x80000000UL
+/* DW.ACT_DESCR_CTL */
+#define DW_V2_ACT_DESCR_CTL_DATA_Pos 0UL
+#define DW_V2_ACT_DESCR_CTL_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_SRC */
+#define DW_V2_ACT_DESCR_SRC_DATA_Pos 0UL
+#define DW_V2_ACT_DESCR_SRC_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_DST */
+#define DW_V2_ACT_DESCR_DST_DATA_Pos 0UL
+#define DW_V2_ACT_DESCR_DST_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_X_CTL */
+#define DW_V2_ACT_DESCR_X_CTL_DATA_Pos 0UL
+#define DW_V2_ACT_DESCR_X_CTL_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_Y_CTL */
+#define DW_V2_ACT_DESCR_Y_CTL_DATA_Pos 0UL
+#define DW_V2_ACT_DESCR_Y_CTL_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_NEXT_PTR */
+#define DW_V2_ACT_DESCR_NEXT_PTR_ADDR_Pos 2UL
+#define DW_V2_ACT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL
+/* DW.ACT_SRC */
+#define DW_V2_ACT_SRC_SRC_ADDR_Pos 0UL
+#define DW_V2_ACT_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL
+/* DW.ACT_DST */
+#define DW_V2_ACT_DST_DST_ADDR_Pos 0UL
+#define DW_V2_ACT_DST_DST_ADDR_Msk 0xFFFFFFFFUL
+/* DW.ECC_CTL */
+#define DW_V2_ECC_CTL_WORD_ADDR_Pos 0UL
+#define DW_V2_ECC_CTL_WORD_ADDR_Msk 0x3FFUL
+#define DW_V2_ECC_CTL_PARITY_Pos 25UL
+#define DW_V2_ECC_CTL_PARITY_Msk 0xFE000000UL
+/* DW.CRC_CTL */
+#define DW_V2_CRC_CTL_DATA_REVERSE_Pos 0UL
+#define DW_V2_CRC_CTL_DATA_REVERSE_Msk 0x1UL
+#define DW_V2_CRC_CTL_REM_REVERSE_Pos 8UL
+#define DW_V2_CRC_CTL_REM_REVERSE_Msk 0x100UL
+/* DW.CRC_DATA_CTL */
+#define DW_V2_CRC_DATA_CTL_DATA_XOR_Pos 0UL
+#define DW_V2_CRC_DATA_CTL_DATA_XOR_Msk 0xFFUL
+/* DW.CRC_POL_CTL */
+#define DW_V2_CRC_POL_CTL_POLYNOMIAL_Pos 0UL
+#define DW_V2_CRC_POL_CTL_POLYNOMIAL_Msk 0xFFFFFFFFUL
+/* DW.CRC_LFSR_CTL */
+#define DW_V2_CRC_LFSR_CTL_LFSR32_Pos 0UL
+#define DW_V2_CRC_LFSR_CTL_LFSR32_Msk 0xFFFFFFFFUL
+/* DW.CRC_REM_CTL */
+#define DW_V2_CRC_REM_CTL_REM_XOR_Pos 0UL
+#define DW_V2_CRC_REM_CTL_REM_XOR_Msk 0xFFFFFFFFUL
+/* DW.CRC_REM_RESULT */
+#define DW_V2_CRC_REM_RESULT_REM_Pos 0UL
+#define DW_V2_CRC_REM_RESULT_REM_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_DW_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_efuse.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_efuse.h
new file mode 100644
index 0000000000..5ca86eec26
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_efuse.h
@@ -0,0 +1,327 @@
+/***************************************************************************//**
+* \file cyip_efuse.h
+*
+* \brief
+* EFUSE IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_EFUSE_H_
+#define _CYIP_EFUSE_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* EFUSE
+*******************************************************************************/
+
+#define EFUSE_SECTION_SIZE 0x00000080UL
+
+/**
+ * \brief EFUSE MXS40 registers (EFUSE)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t CMD; /*!< 0x00000010 Command */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t SEQ_DEFAULT; /*!< 0x00000020 Sequencer Default value */
+ __IM uint32_t RESERVED2[7];
+ __IOM uint32_t SEQ_READ_CTL_0; /*!< 0x00000040 Sequencer read control 0 */
+ __IOM uint32_t SEQ_READ_CTL_1; /*!< 0x00000044 Sequencer read control 1 */
+ __IOM uint32_t SEQ_READ_CTL_2; /*!< 0x00000048 Sequencer read control 2 */
+ __IOM uint32_t SEQ_READ_CTL_3; /*!< 0x0000004C Sequencer read control 3 */
+ __IOM uint32_t SEQ_READ_CTL_4; /*!< 0x00000050 Sequencer read control 4 */
+ __IOM uint32_t SEQ_READ_CTL_5; /*!< 0x00000054 Sequencer read control 5 */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t SEQ_PROGRAM_CTL_0; /*!< 0x00000060 Sequencer program control 0 */
+ __IOM uint32_t SEQ_PROGRAM_CTL_1; /*!< 0x00000064 Sequencer program control 1 */
+ __IOM uint32_t SEQ_PROGRAM_CTL_2; /*!< 0x00000068 Sequencer program control 2 */
+ __IOM uint32_t SEQ_PROGRAM_CTL_3; /*!< 0x0000006C Sequencer program control 3 */
+ __IOM uint32_t SEQ_PROGRAM_CTL_4; /*!< 0x00000070 Sequencer program control 4 */
+ __IOM uint32_t SEQ_PROGRAM_CTL_5; /*!< 0x00000074 Sequencer program control 5 */
+} EFUSE_V1_Type; /*!< Size = 120 (0x78) */
+
+
+/* EFUSE.CTL */
+#define EFUSE_CTL_ENABLED_Pos 31UL
+#define EFUSE_CTL_ENABLED_Msk 0x80000000UL
+/* EFUSE.CMD */
+#define EFUSE_CMD_BIT_DATA_Pos 0UL
+#define EFUSE_CMD_BIT_DATA_Msk 0x1UL
+#define EFUSE_CMD_BIT_ADDR_Pos 4UL
+#define EFUSE_CMD_BIT_ADDR_Msk 0x70UL
+#define EFUSE_CMD_BYTE_ADDR_Pos 8UL
+#define EFUSE_CMD_BYTE_ADDR_Msk 0x1F00UL
+#define EFUSE_CMD_MACRO_ADDR_Pos 16UL
+#define EFUSE_CMD_MACRO_ADDR_Msk 0xF0000UL
+#define EFUSE_CMD_START_Pos 31UL
+#define EFUSE_CMD_START_Msk 0x80000000UL
+/* EFUSE.SEQ_DEFAULT */
+#define EFUSE_SEQ_DEFAULT_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_DEFAULT_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_DEFAULT_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_DEFAULT_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_DEFAULT_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_DEFAULT_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_DEFAULT_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_DEFAULT_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_DEFAULT_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_DEFAULT_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_DEFAULT_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_DEFAULT_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_DEFAULT_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_DEFAULT_STROBE_G_Msk 0x400000UL
+/* EFUSE.SEQ_READ_CTL_0 */
+#define EFUSE_SEQ_READ_CTL_0_CYCLES_Pos 0UL
+#define EFUSE_SEQ_READ_CTL_0_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_READ_CTL_0_DONE_Pos 31UL
+#define EFUSE_SEQ_READ_CTL_0_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_READ_CTL_1 */
+#define EFUSE_SEQ_READ_CTL_1_CYCLES_Pos 0UL
+#define EFUSE_SEQ_READ_CTL_1_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_READ_CTL_1_DONE_Pos 31UL
+#define EFUSE_SEQ_READ_CTL_1_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_READ_CTL_2 */
+#define EFUSE_SEQ_READ_CTL_2_CYCLES_Pos 0UL
+#define EFUSE_SEQ_READ_CTL_2_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_READ_CTL_2_DONE_Pos 31UL
+#define EFUSE_SEQ_READ_CTL_2_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_READ_CTL_3 */
+#define EFUSE_SEQ_READ_CTL_3_CYCLES_Pos 0UL
+#define EFUSE_SEQ_READ_CTL_3_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_READ_CTL_3_DONE_Pos 31UL
+#define EFUSE_SEQ_READ_CTL_3_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_READ_CTL_4 */
+#define EFUSE_SEQ_READ_CTL_4_CYCLES_Pos 0UL
+#define EFUSE_SEQ_READ_CTL_4_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_READ_CTL_4_DONE_Pos 31UL
+#define EFUSE_SEQ_READ_CTL_4_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_READ_CTL_5 */
+#define EFUSE_SEQ_READ_CTL_5_CYCLES_Pos 0UL
+#define EFUSE_SEQ_READ_CTL_5_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_READ_CTL_5_DONE_Pos 31UL
+#define EFUSE_SEQ_READ_CTL_5_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_PROGRAM_CTL_0 */
+#define EFUSE_SEQ_PROGRAM_CTL_0_CYCLES_Pos 0UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_DONE_Pos 31UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_PROGRAM_CTL_1 */
+#define EFUSE_SEQ_PROGRAM_CTL_1_CYCLES_Pos 0UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_DONE_Pos 31UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_PROGRAM_CTL_2 */
+#define EFUSE_SEQ_PROGRAM_CTL_2_CYCLES_Pos 0UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_DONE_Pos 31UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_PROGRAM_CTL_3 */
+#define EFUSE_SEQ_PROGRAM_CTL_3_CYCLES_Pos 0UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_DONE_Pos 31UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_PROGRAM_CTL_4 */
+#define EFUSE_SEQ_PROGRAM_CTL_4_CYCLES_Pos 0UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_DONE_Pos 31UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_PROGRAM_CTL_5 */
+#define EFUSE_SEQ_PROGRAM_CTL_5_CYCLES_Pos 0UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_DONE_Pos 31UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_DONE_Msk 0x80000000UL
+
+
+#endif /* _CYIP_EFUSE_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_efuse_data_psoc6_01.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_efuse_data_psoc6_01.h
new file mode 100644
index 0000000000..4e126f48b8
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_efuse_data_psoc6_01.h
@@ -0,0 +1,114 @@
+/***************************************************************************//**
+* \file cyip_efuse_data_psoc6_01.h
+*
+* \brief
+* EFUSE_DATA IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_EFUSE_DATA_PSOC6_01_H_
+#define _CYIP_EFUSE_DATA_PSOC6_01_H_
+
+#include "cyip_headers.h"
+
+/**
+ * \brief DEAD access restrictions (DEAD_ACCESS_RESTRICT0)
+ */
+typedef struct {
+ uint8_t CM0_DISABLE;
+ uint8_t CM4_DISABLE;
+ uint8_t SYS_DISABLE;
+ uint8_t SYS_AP_MPU_ENABLE;
+ uint8_t SFLASH_ALLOWED[2];
+ uint8_t MMIO_ALLOWED[2];
+} cy_stc_dead_access_restrict0_t;
+
+/**
+ * \brief DEAD access restrictions (DEAD_ACCESS_RESTRICT1)
+ */
+typedef struct {
+ uint8_t FLASH_ALLOWED[3];
+ uint8_t SRAM_ALLOWED[3];
+ uint8_t UNUSED;
+ uint8_t DIRECT_EXECUTE_DISABLE;
+} cy_stc_dead_access_restrict1_t;
+
+/**
+ * \brief SECURE access restrictions (SECURE_ACCESS_RESTRICT0)
+ */
+typedef struct {
+ uint8_t CM0_DISABLE;
+ uint8_t CM4_DISABLE;
+ uint8_t SYS_DISABLE;
+ uint8_t SYS_AP_MPU_ENABLE;
+ uint8_t SFLASH_ALLOWED[2];
+ uint8_t MMIO_ALLOWED[2];
+} cy_stc_secure_access_restrict0_t;
+
+/**
+ * \brief SECURE access restrictions (SECURE_ACCESS_RESTRICT1)
+ */
+typedef struct {
+ uint8_t FLASH_ALLOWED[3];
+ uint8_t SRAM_ALLOWED[3];
+ uint8_t SMIF_XIP_ALLOWED;
+ uint8_t DIRECT_EXECUTE_DISABLE;
+} cy_stc_secure_access_restrict1_t;
+
+/**
+ * \brief NORMAL, SECURE_WITH_DEBUG, and SECURE fuse bits (LIFECYCLE_STAGE)
+ */
+typedef struct {
+ uint8_t NORMAL;
+ uint8_t SECURE_WITH_DEBUG;
+ uint8_t SECURE;
+ uint8_t RMA;
+ uint8_t RESERVED[4];
+} cy_stc_lifecycle_stage_t;
+
+/**
+ * \brief Customer data (CUSTOMER_DATA)
+ */
+typedef struct {
+ uint8_t CUSTOMER_USE[8];
+} cy_stc_customer_data_t;
+
+
+/**
+ * \brief eFUSE memory (EFUSE_DATA)
+ */
+typedef struct {
+ uint8_t RESERVED[312];
+ cy_stc_dead_access_restrict0_t DEAD_ACCESS_RESTRICT0;
+ cy_stc_dead_access_restrict1_t DEAD_ACCESS_RESTRICT1;
+ cy_stc_secure_access_restrict0_t SECURE_ACCESS_RESTRICT0;
+ cy_stc_secure_access_restrict1_t SECURE_ACCESS_RESTRICT1;
+ cy_stc_lifecycle_stage_t LIFECYCLE_STAGE;
+ uint8_t RESERVED1[160];
+ cy_stc_customer_data_t CUSTOMER_DATA[64];
+} cy_stc_efuse_data_t;
+
+
+#endif /* _CYIP_EFUSE_DATA_PSOC6_01_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_efuse_data_psoc6_02.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_efuse_data_psoc6_02.h
new file mode 100644
index 0000000000..7dcc98f844
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_efuse_data_psoc6_02.h
@@ -0,0 +1,250 @@
+/***************************************************************************//**
+* \file cyip_efuse_data_psoc6_02.h
+*
+* \brief
+* EFUSE_DATA IP definitions
+*
+* \note
+* Generator version: 1.5.0.1287
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_EFUSE_DATA_PSOC6_02_H_
+#define _CYIP_EFUSE_DATA_PSOC6_02_H_
+
+#include "cyip_headers.h"
+
+/**
+ * \brief Access restrictions for DEAD life cycle stage (DEAD_ACCESS_RESTRICT0)
+ */
+typedef struct {
+ uint8_t CM0_DISABLE;
+ uint8_t CM4_DISABLE;
+ uint8_t SYS_DISABLE;
+ uint8_t SYS_AP_MPU_ENABLE;
+ uint8_t SFLASH_ALLOWED[2];
+ uint8_t MMIO_ALLOWED[2];
+} cy_stc_dead_access_restrict0_t;
+
+/**
+ * \brief Access restrictions for DEAD life cycle stage (DEAD_ACCESS_RESTRICT1)
+ */
+typedef struct {
+ uint8_t FLASH_ALLOWED[3];
+ uint8_t SRAM_ALLOWED[3];
+ uint8_t UNUSED;
+ uint8_t DIRECT_EXECUTE_DISABLE;
+} cy_stc_dead_access_restrict1_t;
+
+/**
+ * \brief Access restrictions for SECURE life cycle stage (SECURE_ACCESS_RESTRICT0)
+ */
+typedef struct {
+ uint8_t CM0_DISABLE;
+ uint8_t CM4_DISABLE;
+ uint8_t SYS_DISABLE;
+ uint8_t SYS_AP_MPU_ENABLE;
+ uint8_t SFLASH_ALLOWED[2];
+ uint8_t MMIO_ALLOWED[2];
+} cy_stc_secure_access_restrict0_t;
+
+/**
+ * \brief Access restrictions for SECURE life cycle stage (SECURE_ACCESS_RESTRICT1)
+ */
+typedef struct {
+ uint8_t FLASH_ALLOWED[3];
+ uint8_t SRAM_ALLOWED[3];
+ uint8_t UNUSED;
+ uint8_t DIRECT_EXECUTE_DISABLE;
+} cy_stc_secure_access_restrict1_t;
+
+/**
+ * \brief NORMAL, SECURE_WITH_DEBUG, SECURE, and RMA fuse bits (LIFECYCLE_STAGE)
+ */
+typedef struct {
+ uint8_t NORMAL;
+ uint8_t SECURE_WITH_DEBUG;
+ uint8_t SECURE;
+ uint8_t RMA;
+ uint8_t RESERVED[4];
+} cy_stc_lifecycle_stage_t;
+
+/**
+ * \brief Cypress asset hash byte 0 (CY_ASSET_HASH0)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash0_t;
+
+/**
+ * \brief Cypress asset hash byte 1 (CY_ASSET_HASH1)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash1_t;
+
+/**
+ * \brief Cypress asset hash byte 2 (CY_ASSET_HASH2)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash2_t;
+
+/**
+ * \brief Cypress asset hash byte 3 (CY_ASSET_HASH3)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash3_t;
+
+/**
+ * \brief Cypress asset hash byte 4 (CY_ASSET_HASH4)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash4_t;
+
+/**
+ * \brief Cypress asset hash byte 5 (CY_ASSET_HASH5)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash5_t;
+
+/**
+ * \brief Cypress asset hash byte 6 (CY_ASSET_HASH6)
+ */
+typedef struct {
+ uint8_t CY_ASSET_HASH[8];
+} cy_stc_cy_asset_hash6_t;
+
+/**
+ * \brief Cypress asset hash byte 7 (CY_ASSET_HASH7)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash7_t;
+
+/**
+ * \brief Cypress asset hash byte 8 (CY_ASSET_HASH8)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash8_t;
+
+/**
+ * \brief Cypress asset hash byte 9 (CY_ASSET_HASH9)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash9_t;
+
+/**
+ * \brief Cypress asset hash byte 10 (CY_ASSET_HASH10)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash10_t;
+
+/**
+ * \brief Cypress asset hash byte 11 (CY_ASSET_HASH11)
+ */
+typedef struct {
+ uint8_t CY_ASSET_HASH[8];
+} cy_stc_cy_asset_hash11_t;
+
+/**
+ * \brief Cypress asset hash byte 12 (CY_ASSET_HASH12)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash12_t;
+
+/**
+ * \brief Cypress asset hash byte 13 (CY_ASSET_HASH13)
+ */
+typedef struct {
+ uint8_t CY_ASSET_HASH[8];
+} cy_stc_cy_asset_hash13_t;
+
+/**
+ * \brief Cypress asset hash byte 14 (CY_ASSET_HASH14)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash14_t;
+
+/**
+ * \brief Cypress asset hash byte 15 (CY_ASSET_HASH15)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash15_t;
+
+/**
+ * \brief Number of zeros in Cypress asset hash (CY_ASSET_HASH_ZEROS)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash_zeros_t;
+
+/**
+ * \brief Customer data (CUSTOMER_DATA)
+ */
+typedef struct {
+ uint8_t CUSTOMER_USE[8];
+} cy_stc_customer_data_t;
+
+
+/**
+ * \brief eFUSE memory (EFUSE_DATA)
+ */
+typedef struct {
+ uint8_t RESERVED[312];
+ cy_stc_dead_access_restrict0_t DEAD_ACCESS_RESTRICT0;
+ cy_stc_dead_access_restrict1_t DEAD_ACCESS_RESTRICT1;
+ cy_stc_secure_access_restrict0_t SECURE_ACCESS_RESTRICT0;
+ cy_stc_secure_access_restrict1_t SECURE_ACCESS_RESTRICT1;
+ cy_stc_lifecycle_stage_t LIFECYCLE_STAGE;
+ uint8_t RESERVED1[160];
+ cy_stc_cy_asset_hash0_t CY_ASSET_HASH0;
+ cy_stc_cy_asset_hash1_t CY_ASSET_HASH1;
+ cy_stc_cy_asset_hash2_t CY_ASSET_HASH2;
+ cy_stc_cy_asset_hash3_t CY_ASSET_HASH3;
+ cy_stc_cy_asset_hash4_t CY_ASSET_HASH4;
+ cy_stc_cy_asset_hash5_t CY_ASSET_HASH5;
+ cy_stc_cy_asset_hash6_t CY_ASSET_HASH6;
+ cy_stc_cy_asset_hash7_t CY_ASSET_HASH7;
+ cy_stc_cy_asset_hash8_t CY_ASSET_HASH8;
+ cy_stc_cy_asset_hash9_t CY_ASSET_HASH9;
+ cy_stc_cy_asset_hash10_t CY_ASSET_HASH10;
+ cy_stc_cy_asset_hash11_t CY_ASSET_HASH11;
+ cy_stc_cy_asset_hash12_t CY_ASSET_HASH12;
+ cy_stc_cy_asset_hash13_t CY_ASSET_HASH13;
+ cy_stc_cy_asset_hash14_t CY_ASSET_HASH14;
+ cy_stc_cy_asset_hash15_t CY_ASSET_HASH15;
+ cy_stc_cy_asset_hash_zeros_t CY_ASSET_HASH_ZEROS;
+ cy_stc_customer_data_t CUSTOMER_DATA[47];
+} cy_stc_efuse_data_t;
+
+
+#endif /* _CYIP_EFUSE_DATA_PSOC6_02_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_efuse_data_psoc6_03.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_efuse_data_psoc6_03.h
new file mode 100644
index 0000000000..b934c88e42
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_efuse_data_psoc6_03.h
@@ -0,0 +1,250 @@
+/***************************************************************************//**
+* \file cyip_efuse_data_psoc6_03.h
+*
+* \brief
+* EFUSE_DATA IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_EFUSE_DATA_PSOC6_03_H_
+#define _CYIP_EFUSE_DATA_PSOC6_03_H_
+
+#include "cyip_headers.h"
+
+/**
+ * \brief Access restrictions for DEAD life cycle stage (DEAD_ACCESS_RESTRICT0)
+ */
+typedef struct {
+ uint8_t CM0_DISABLE;
+ uint8_t CM4_DISABLE;
+ uint8_t SYS_DISABLE;
+ uint8_t SYS_AP_MPU_ENABLE;
+ uint8_t SFLASH_ALLOWED[2];
+ uint8_t MMIO_ALLOWED[2];
+} cy_stc_dead_access_restrict0_t;
+
+/**
+ * \brief Access restrictions for DEAD life cycle stage (DEAD_ACCESS_RESTRICT1)
+ */
+typedef struct {
+ uint8_t FLASH_ALLOWED[3];
+ uint8_t SRAM_ALLOWED[3];
+ uint8_t UNUSED;
+ uint8_t DIRECT_EXECUTE_DISABLE;
+} cy_stc_dead_access_restrict1_t;
+
+/**
+ * \brief Access restrictions for SECURE life cycle stage (SECURE_ACCESS_RESTRICT0)
+ */
+typedef struct {
+ uint8_t CM0_DISABLE;
+ uint8_t CM4_DISABLE;
+ uint8_t SYS_DISABLE;
+ uint8_t SYS_AP_MPU_ENABLE;
+ uint8_t SFLASH_ALLOWED[2];
+ uint8_t MMIO_ALLOWED[2];
+} cy_stc_secure_access_restrict0_t;
+
+/**
+ * \brief Access restrictions for SECURE life cycle stage (SECURE_ACCESS_RESTRICT1)
+ */
+typedef struct {
+ uint8_t FLASH_ALLOWED[3];
+ uint8_t SRAM_ALLOWED[3];
+ uint8_t UNUSED;
+ uint8_t DIRECT_EXECUTE_DISABLE;
+} cy_stc_secure_access_restrict1_t;
+
+/**
+ * \brief NORMAL, SECURE_WITH_DEBUG, SECURE, and RMA fuse bits (LIFECYCLE_STAGE)
+ */
+typedef struct {
+ uint8_t NORMAL;
+ uint8_t SECURE_WITH_DEBUG;
+ uint8_t SECURE;
+ uint8_t RMA;
+ uint8_t RESERVED[4];
+} cy_stc_lifecycle_stage_t;
+
+/**
+ * \brief Cypress asset hash byte 0 (CY_ASSET_HASH0)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash0_t;
+
+/**
+ * \brief Cypress asset hash byte 1 (CY_ASSET_HASH1)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash1_t;
+
+/**
+ * \brief Cypress asset hash byte 2 (CY_ASSET_HASH2)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash2_t;
+
+/**
+ * \brief Cypress asset hash byte 3 (CY_ASSET_HASH3)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash3_t;
+
+/**
+ * \brief Cypress asset hash byte 4 (CY_ASSET_HASH4)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash4_t;
+
+/**
+ * \brief Cypress asset hash byte 5 (CY_ASSET_HASH5)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash5_t;
+
+/**
+ * \brief Cypress asset hash byte 6 (CY_ASSET_HASH6)
+ */
+typedef struct {
+ uint8_t CY_ASSET_HASH[8];
+} cy_stc_cy_asset_hash6_t;
+
+/**
+ * \brief Cypress asset hash byte 7 (CY_ASSET_HASH7)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash7_t;
+
+/**
+ * \brief Cypress asset hash byte 8 (CY_ASSET_HASH8)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash8_t;
+
+/**
+ * \brief Cypress asset hash byte 9 (CY_ASSET_HASH9)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash9_t;
+
+/**
+ * \brief Cypress asset hash byte 10 (CY_ASSET_HASH10)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash10_t;
+
+/**
+ * \brief Cypress asset hash byte 11 (CY_ASSET_HASH11)
+ */
+typedef struct {
+ uint8_t CY_ASSET_HASH[8];
+} cy_stc_cy_asset_hash11_t;
+
+/**
+ * \brief Cypress asset hash byte 12 (CY_ASSET_HASH12)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash12_t;
+
+/**
+ * \brief Cypress asset hash byte 13 (CY_ASSET_HASH13)
+ */
+typedef struct {
+ uint8_t CY_ASSET_HASH[8];
+} cy_stc_cy_asset_hash13_t;
+
+/**
+ * \brief Cypress asset hash byte 14 (CY_ASSET_HASH14)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash14_t;
+
+/**
+ * \brief Cypress asset hash byte 15 (CY_ASSET_HASH15)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash15_t;
+
+/**
+ * \brief Number of zeros in Cypress asset hash (CY_ASSET_HASH_ZEROS)
+ */
+typedef struct {
+ uint8_t HASH_BYTE[8];
+} cy_stc_cy_asset_hash_zeros_t;
+
+/**
+ * \brief Customer data (CUSTOMER_DATA)
+ */
+typedef struct {
+ uint8_t CUSTOMER_USE[8];
+} cy_stc_customer_data_t;
+
+
+/**
+ * \brief eFUSE memory (EFUSE_DATA)
+ */
+typedef struct {
+ uint8_t RESERVED[312];
+ cy_stc_dead_access_restrict0_t DEAD_ACCESS_RESTRICT0;
+ cy_stc_dead_access_restrict1_t DEAD_ACCESS_RESTRICT1;
+ cy_stc_secure_access_restrict0_t SECURE_ACCESS_RESTRICT0;
+ cy_stc_secure_access_restrict1_t SECURE_ACCESS_RESTRICT1;
+ cy_stc_lifecycle_stage_t LIFECYCLE_STAGE;
+ uint8_t RESERVED1[160];
+ cy_stc_cy_asset_hash0_t CY_ASSET_HASH0;
+ cy_stc_cy_asset_hash1_t CY_ASSET_HASH1;
+ cy_stc_cy_asset_hash2_t CY_ASSET_HASH2;
+ cy_stc_cy_asset_hash3_t CY_ASSET_HASH3;
+ cy_stc_cy_asset_hash4_t CY_ASSET_HASH4;
+ cy_stc_cy_asset_hash5_t CY_ASSET_HASH5;
+ cy_stc_cy_asset_hash6_t CY_ASSET_HASH6;
+ cy_stc_cy_asset_hash7_t CY_ASSET_HASH7;
+ cy_stc_cy_asset_hash8_t CY_ASSET_HASH8;
+ cy_stc_cy_asset_hash9_t CY_ASSET_HASH9;
+ cy_stc_cy_asset_hash10_t CY_ASSET_HASH10;
+ cy_stc_cy_asset_hash11_t CY_ASSET_HASH11;
+ cy_stc_cy_asset_hash12_t CY_ASSET_HASH12;
+ cy_stc_cy_asset_hash13_t CY_ASSET_HASH13;
+ cy_stc_cy_asset_hash14_t CY_ASSET_HASH14;
+ cy_stc_cy_asset_hash15_t CY_ASSET_HASH15;
+ cy_stc_cy_asset_hash_zeros_t CY_ASSET_HASH_ZEROS;
+ cy_stc_customer_data_t CUSTOMER_DATA[47];
+} cy_stc_efuse_data_t;
+
+
+#endif /* _CYIP_EFUSE_DATA_PSOC6_03_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_fault.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_fault.h
new file mode 100644
index 0000000000..f957f54944
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_fault.h
@@ -0,0 +1,122 @@
+/***************************************************************************//**
+* \file cyip_fault.h
+*
+* \brief
+* FAULT IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_FAULT_H_
+#define _CYIP_FAULT_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* FAULT
+*******************************************************************************/
+
+#define FAULT_STRUCT_SECTION_SIZE 0x00000100UL
+#define FAULT_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Fault structure (FAULT_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Fault control */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t STATUS; /*!< 0x0000000C Fault status */
+ __IM uint32_t DATA[4]; /*!< 0x00000010 Fault data */
+ __IM uint32_t RESERVED1[8];
+ __IM uint32_t PENDING0; /*!< 0x00000040 Fault pending 0 */
+ __IM uint32_t PENDING1; /*!< 0x00000044 Fault pending 1 */
+ __IM uint32_t PENDING2; /*!< 0x00000048 Fault pending 2 */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t MASK0; /*!< 0x00000050 Fault mask 0 */
+ __IOM uint32_t MASK1; /*!< 0x00000054 Fault mask 1 */
+ __IOM uint32_t MASK2; /*!< 0x00000058 Fault mask 2 */
+ __IM uint32_t RESERVED3[25];
+ __IOM uint32_t INTR; /*!< 0x000000C0 Interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x000000C4 Interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x000000C8 Interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x000000CC Interrupt masked */
+ __IM uint32_t RESERVED4[12];
+} FAULT_STRUCT_V1_Type; /*!< Size = 256 (0x100) */
+
+/**
+ * \brief Fault structures (FAULT)
+ */
+typedef struct {
+ FAULT_STRUCT_V1_Type STRUCT[4]; /*!< 0x00000000 Fault structure */
+} FAULT_V1_Type; /*!< Size = 1024 (0x400) */
+
+
+/* FAULT_STRUCT.CTL */
+#define FAULT_STRUCT_CTL_TR_EN_Pos 0UL
+#define FAULT_STRUCT_CTL_TR_EN_Msk 0x1UL
+#define FAULT_STRUCT_CTL_OUT_EN_Pos 1UL
+#define FAULT_STRUCT_CTL_OUT_EN_Msk 0x2UL
+#define FAULT_STRUCT_CTL_RESET_REQ_EN_Pos 2UL
+#define FAULT_STRUCT_CTL_RESET_REQ_EN_Msk 0x4UL
+/* FAULT_STRUCT.STATUS */
+#define FAULT_STRUCT_STATUS_IDX_Pos 0UL
+#define FAULT_STRUCT_STATUS_IDX_Msk 0x7FUL
+#define FAULT_STRUCT_STATUS_VALID_Pos 31UL
+#define FAULT_STRUCT_STATUS_VALID_Msk 0x80000000UL
+/* FAULT_STRUCT.DATA */
+#define FAULT_STRUCT_DATA_DATA_Pos 0UL
+#define FAULT_STRUCT_DATA_DATA_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.PENDING0 */
+#define FAULT_STRUCT_PENDING0_SOURCE_Pos 0UL
+#define FAULT_STRUCT_PENDING0_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.PENDING1 */
+#define FAULT_STRUCT_PENDING1_SOURCE_Pos 0UL
+#define FAULT_STRUCT_PENDING1_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.PENDING2 */
+#define FAULT_STRUCT_PENDING2_SOURCE_Pos 0UL
+#define FAULT_STRUCT_PENDING2_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.MASK0 */
+#define FAULT_STRUCT_MASK0_SOURCE_Pos 0UL
+#define FAULT_STRUCT_MASK0_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.MASK1 */
+#define FAULT_STRUCT_MASK1_SOURCE_Pos 0UL
+#define FAULT_STRUCT_MASK1_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.MASK2 */
+#define FAULT_STRUCT_MASK2_SOURCE_Pos 0UL
+#define FAULT_STRUCT_MASK2_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.INTR */
+#define FAULT_STRUCT_INTR_FAULT_Pos 0UL
+#define FAULT_STRUCT_INTR_FAULT_Msk 0x1UL
+/* FAULT_STRUCT.INTR_SET */
+#define FAULT_STRUCT_INTR_SET_FAULT_Pos 0UL
+#define FAULT_STRUCT_INTR_SET_FAULT_Msk 0x1UL
+/* FAULT_STRUCT.INTR_MASK */
+#define FAULT_STRUCT_INTR_MASK_FAULT_Pos 0UL
+#define FAULT_STRUCT_INTR_MASK_FAULT_Msk 0x1UL
+/* FAULT_STRUCT.INTR_MASKED */
+#define FAULT_STRUCT_INTR_MASKED_FAULT_Pos 0UL
+#define FAULT_STRUCT_INTR_MASKED_FAULT_Msk 0x1UL
+
+
+#endif /* _CYIP_FAULT_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_fault_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_fault_v2.h
new file mode 100644
index 0000000000..24d9bb9eb1
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_fault_v2.h
@@ -0,0 +1,122 @@
+/***************************************************************************//**
+* \file cyip_fault_v2.h
+*
+* \brief
+* FAULT IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_FAULT_V2_H_
+#define _CYIP_FAULT_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* FAULT
+*******************************************************************************/
+
+#define FAULT_STRUCT_V2_SECTION_SIZE 0x00000100UL
+#define FAULT_V2_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Fault structure (FAULT_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Fault control */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t STATUS; /*!< 0x0000000C Fault status */
+ __IOM uint32_t DATA[4]; /*!< 0x00000010 Fault data */
+ __IM uint32_t RESERVED1[8];
+ __IM uint32_t PENDING0; /*!< 0x00000040 Fault pending 0 */
+ __IM uint32_t PENDING1; /*!< 0x00000044 Fault pending 1 */
+ __IM uint32_t PENDING2; /*!< 0x00000048 Fault pending 2 */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t MASK0; /*!< 0x00000050 Fault mask 0 */
+ __IOM uint32_t MASK1; /*!< 0x00000054 Fault mask 1 */
+ __IOM uint32_t MASK2; /*!< 0x00000058 Fault mask 2 */
+ __IM uint32_t RESERVED3[25];
+ __IOM uint32_t INTR; /*!< 0x000000C0 Interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x000000C4 Interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x000000C8 Interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x000000CC Interrupt masked */
+ __IM uint32_t RESERVED4[12];
+} FAULT_STRUCT_V2_Type; /*!< Size = 256 (0x100) */
+
+/**
+ * \brief Fault structures (FAULT)
+ */
+typedef struct {
+ FAULT_STRUCT_V2_Type STRUCT[4]; /*!< 0x00000000 Fault structure */
+} FAULT_V2_Type; /*!< Size = 1024 (0x400) */
+
+
+/* FAULT_STRUCT.CTL */
+#define FAULT_STRUCT_V2_CTL_TR_EN_Pos 0UL
+#define FAULT_STRUCT_V2_CTL_TR_EN_Msk 0x1UL
+#define FAULT_STRUCT_V2_CTL_OUT_EN_Pos 1UL
+#define FAULT_STRUCT_V2_CTL_OUT_EN_Msk 0x2UL
+#define FAULT_STRUCT_V2_CTL_RESET_REQ_EN_Pos 2UL
+#define FAULT_STRUCT_V2_CTL_RESET_REQ_EN_Msk 0x4UL
+/* FAULT_STRUCT.STATUS */
+#define FAULT_STRUCT_V2_STATUS_IDX_Pos 0UL
+#define FAULT_STRUCT_V2_STATUS_IDX_Msk 0x7FUL
+#define FAULT_STRUCT_V2_STATUS_VALID_Pos 31UL
+#define FAULT_STRUCT_V2_STATUS_VALID_Msk 0x80000000UL
+/* FAULT_STRUCT.DATA */
+#define FAULT_STRUCT_V2_DATA_DATA_Pos 0UL
+#define FAULT_STRUCT_V2_DATA_DATA_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.PENDING0 */
+#define FAULT_STRUCT_V2_PENDING0_SOURCE_Pos 0UL
+#define FAULT_STRUCT_V2_PENDING0_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.PENDING1 */
+#define FAULT_STRUCT_V2_PENDING1_SOURCE_Pos 0UL
+#define FAULT_STRUCT_V2_PENDING1_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.PENDING2 */
+#define FAULT_STRUCT_V2_PENDING2_SOURCE_Pos 0UL
+#define FAULT_STRUCT_V2_PENDING2_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.MASK0 */
+#define FAULT_STRUCT_V2_MASK0_SOURCE_Pos 0UL
+#define FAULT_STRUCT_V2_MASK0_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.MASK1 */
+#define FAULT_STRUCT_V2_MASK1_SOURCE_Pos 0UL
+#define FAULT_STRUCT_V2_MASK1_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.MASK2 */
+#define FAULT_STRUCT_V2_MASK2_SOURCE_Pos 0UL
+#define FAULT_STRUCT_V2_MASK2_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.INTR */
+#define FAULT_STRUCT_V2_INTR_FAULT_Pos 0UL
+#define FAULT_STRUCT_V2_INTR_FAULT_Msk 0x1UL
+/* FAULT_STRUCT.INTR_SET */
+#define FAULT_STRUCT_V2_INTR_SET_FAULT_Pos 0UL
+#define FAULT_STRUCT_V2_INTR_SET_FAULT_Msk 0x1UL
+/* FAULT_STRUCT.INTR_MASK */
+#define FAULT_STRUCT_V2_INTR_MASK_FAULT_Pos 0UL
+#define FAULT_STRUCT_V2_INTR_MASK_FAULT_Msk 0x1UL
+/* FAULT_STRUCT.INTR_MASKED */
+#define FAULT_STRUCT_V2_INTR_MASKED_FAULT_Pos 0UL
+#define FAULT_STRUCT_V2_INTR_MASKED_FAULT_Msk 0x1UL
+
+
+#endif /* _CYIP_FAULT_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_flashc.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_flashc.h
new file mode 100644
index 0000000000..cd949a2e04
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_flashc.h
@@ -0,0 +1,603 @@
+/***************************************************************************//**
+* \file cyip_flashc.h
+*
+* \brief
+* FLASHC IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_FLASHC_H_
+#define _CYIP_FLASHC_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* FLASHC
+*******************************************************************************/
+
+#define FLASHC_FM_CTL_SECTION_SIZE 0x00001000UL
+#define FLASHC_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Flash Macro Registers (FLASHC_FM_CTL)
+ */
+typedef struct {
+ __IOM uint32_t FM_CTL; /*!< 0x00000000 Flash macro control */
+ __IM uint32_t STATUS; /*!< 0x00000004 Status */
+ __IOM uint32_t FM_ADDR; /*!< 0x00000008 Flash macro address */
+ __IM uint32_t GEOMETRY; /*!< 0x0000000C Regular flash geometry */
+ __IM uint32_t GEOMETRY_SUPERVISORY; /*!< 0x00000010 Supervisory flash geometry */
+ __IOM uint32_t TIMER_CTL; /*!< 0x00000014 Timer control */
+ __IOM uint32_t ANA_CTL0; /*!< 0x00000018 Analog control 0 */
+ __IOM uint32_t ANA_CTL1; /*!< 0x0000001C Analog control 1 */
+ __IM uint32_t GEOMETRY_GEN; /*!< 0x00000020 N/A, DNU */
+ __IOM uint32_t TEST_CTL; /*!< 0x00000024 Test mode control */
+ __IOM uint32_t WAIT_CTL; /*!< 0x00000028 Wiat State control */
+ __IM uint32_t MONITOR_STATUS; /*!< 0x0000002C Monitor Status */
+ __IOM uint32_t SCRATCH_CTL; /*!< 0x00000030 Scratch Control */
+ __IOM uint32_t HV_CTL; /*!< 0x00000034 High voltage control */
+ __OM uint32_t ACLK_CTL; /*!< 0x00000038 Aclk control */
+ __IOM uint32_t INTR; /*!< 0x0000003C Interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x00000040 Interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000044 Interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x00000048 Interrupt masked */
+ __OM uint32_t FM_HV_DATA_ALL; /*!< 0x0000004C Flash macro high Voltage page latches data (for all page
+ latches) */
+ __IOM uint32_t CAL_CTL0; /*!< 0x00000050 Cal control BG LO trim bits */
+ __IOM uint32_t CAL_CTL1; /*!< 0x00000054 Cal control BG HI trim bits */
+ __IOM uint32_t CAL_CTL2; /*!< 0x00000058 Cal control BG LO&HI ipref trim, ref sel, fm_active, turbo_ext */
+ __IOM uint32_t CAL_CTL3; /*!< 0x0000005C Cal control osc trim bits, idac, sdac, itim, bdac. */
+ __OM uint32_t BOOKMARK; /*!< 0x00000060 Bookmark register - keeps the current FW HV seq */
+ __IM uint32_t RESERVED[7];
+ __IOM uint32_t RED_CTL01; /*!< 0x00000080 Redundancy Control normal sectors 0,1 */
+ __IOM uint32_t RED_CTL23; /*!< 0x00000084 Redundancy Controll normal sectors 2,3 */
+ __IOM uint32_t RED_CTL45; /*!< 0x00000088 Redundancy Controll normal sectors 4,5 */
+ __IOM uint32_t RED_CTL67; /*!< 0x0000008C Redundancy Controll normal sectors 6,7 */
+ __IOM uint32_t RED_CTL_SM01; /*!< 0x00000090 Redundancy Controll special sectors 0,1 */
+ __IM uint32_t RESERVED1[27];
+ __IM uint32_t TM_CMPR[32]; /*!< 0x00000100 Do Not Use */
+ __IM uint32_t RESERVED2[416];
+ __IOM uint32_t FM_HV_DATA[256]; /*!< 0x00000800 Flash macro high Voltage page latches data */
+ __IM uint32_t FM_MEM_DATA[256]; /*!< 0x00000C00 Flash macro memory sense amplifier and column decoder data */
+} FLASHC_FM_CTL_V1_Type; /*!< Size = 4096 (0x1000) */
+
+/**
+ * \brief Flash controller (FLASHC)
+ */
+typedef struct {
+ __IOM uint32_t FLASH_CTL; /*!< 0x00000000 Control */
+ __IOM uint32_t FLASH_PWR_CTL; /*!< 0x00000004 Flash power control */
+ __IOM uint32_t FLASH_CMD; /*!< 0x00000008 Command */
+ __IM uint32_t RESERVED[61];
+ __IOM uint32_t BIST_CTL; /*!< 0x00000100 BIST control */
+ __IOM uint32_t BIST_CMD; /*!< 0x00000104 BIST command */
+ __IOM uint32_t BIST_ADDR_START; /*!< 0x00000108 BIST address start register */
+ __IOM uint32_t BIST_DATA[8]; /*!< 0x0000010C BIST data register(s) */
+ __IM uint32_t BIST_DATA_ACT[8]; /*!< 0x0000012C BIST data actual register(s) */
+ __IM uint32_t BIST_DATA_EXP[8]; /*!< 0x0000014C BIST data expected register(s) */
+ __IM uint32_t BIST_ADDR; /*!< 0x0000016C BIST address register */
+ __IOM uint32_t BIST_STATUS; /*!< 0x00000170 BIST status register */
+ __IM uint32_t RESERVED1[163];
+ __IOM uint32_t CM0_CA_CTL0; /*!< 0x00000400 CM0+ cache control */
+ __IOM uint32_t CM0_CA_CTL1; /*!< 0x00000404 CM0+ cache control */
+ __IOM uint32_t CM0_CA_CTL2; /*!< 0x00000408 CM0+ cache control */
+ __IOM uint32_t CM0_CA_CMD; /*!< 0x0000040C CM0+ cache command */
+ __IM uint32_t RESERVED2[12];
+ __IM uint32_t CM0_CA_STATUS0; /*!< 0x00000440 CM0+ cache status 0 */
+ __IM uint32_t CM0_CA_STATUS1; /*!< 0x00000444 CM0+ cache status 1 */
+ __IM uint32_t CM0_CA_STATUS2; /*!< 0x00000448 CM0+ cache status 2 */
+ __IM uint32_t RESERVED3[13];
+ __IOM uint32_t CM4_CA_CTL0; /*!< 0x00000480 CM4 cache control */
+ __IOM uint32_t CM4_CA_CTL1; /*!< 0x00000484 CM4 cache control */
+ __IOM uint32_t CM4_CA_CTL2; /*!< 0x00000488 CM4 cache control */
+ __IOM uint32_t CM4_CA_CMD; /*!< 0x0000048C CM4 cache command */
+ __IM uint32_t RESERVED4[12];
+ __IM uint32_t CM4_CA_STATUS0; /*!< 0x000004C0 CM4 cache status 0 */
+ __IM uint32_t CM4_CA_STATUS1; /*!< 0x000004C4 CM4 cache status 1 */
+ __IM uint32_t CM4_CA_STATUS2; /*!< 0x000004C8 CM4 cache status 2 */
+ __IM uint32_t RESERVED5[13];
+ __IOM uint32_t CRYPTO_BUFF_CTL; /*!< 0x00000500 Cryptography buffer control */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t CRYPTO_BUFF_CMD; /*!< 0x00000508 Cryptography buffer command */
+ __IM uint32_t RESERVED7[29];
+ __IOM uint32_t DW0_BUFF_CTL; /*!< 0x00000580 Datawire 0 buffer control */
+ __IM uint32_t RESERVED8;
+ __IOM uint32_t DW0_BUFF_CMD; /*!< 0x00000588 Datawire 0 buffer command */
+ __IM uint32_t RESERVED9[29];
+ __IOM uint32_t DW1_BUFF_CTL; /*!< 0x00000600 Datawire 1 buffer control */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t DW1_BUFF_CMD; /*!< 0x00000608 Datawire 1 buffer command */
+ __IM uint32_t RESERVED11[29];
+ __IOM uint32_t DAP_BUFF_CTL; /*!< 0x00000680 Debug access port buffer control */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t DAP_BUFF_CMD; /*!< 0x00000688 Debug access port buffer command */
+ __IM uint32_t RESERVED13[29];
+ __IOM uint32_t EXT_MS0_BUFF_CTL; /*!< 0x00000700 External master 0 buffer control */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t EXT_MS0_BUFF_CMD; /*!< 0x00000708 External master 0 buffer command */
+ __IM uint32_t RESERVED15[29];
+ __IOM uint32_t EXT_MS1_BUFF_CTL; /*!< 0x00000780 External master 1 buffer control */
+ __IM uint32_t RESERVED16;
+ __IOM uint32_t EXT_MS1_BUFF_CMD; /*!< 0x00000788 External master 1 buffer command */
+ __IM uint32_t RESERVED17[14877];
+ FLASHC_FM_CTL_V1_Type FM_CTL; /*!< 0x0000F000 Flash Macro Registers */
+} FLASHC_V1_Type; /*!< Size = 65536 (0x10000) */
+
+
+/* FLASHC_FM_CTL.FM_CTL */
+#define FLASHC_FM_CTL_FM_CTL_FM_MODE_Pos 0UL
+#define FLASHC_FM_CTL_FM_CTL_FM_MODE_Msk 0xFUL
+#define FLASHC_FM_CTL_FM_CTL_FM_SEQ_Pos 8UL
+#define FLASHC_FM_CTL_FM_CTL_FM_SEQ_Msk 0x300UL
+#define FLASHC_FM_CTL_FM_CTL_DAA_MUX_SEL_Pos 16UL
+#define FLASHC_FM_CTL_FM_CTL_DAA_MUX_SEL_Msk 0x7F0000UL
+#define FLASHC_FM_CTL_FM_CTL_IF_SEL_Pos 24UL
+#define FLASHC_FM_CTL_FM_CTL_IF_SEL_Msk 0x1000000UL
+#define FLASHC_FM_CTL_FM_CTL_WR_EN_Pos 25UL
+#define FLASHC_FM_CTL_FM_CTL_WR_EN_Msk 0x2000000UL
+/* FLASHC_FM_CTL.STATUS */
+#define FLASHC_FM_CTL_STATUS_HV_TIMER_RUNNING_Pos 0UL
+#define FLASHC_FM_CTL_STATUS_HV_TIMER_RUNNING_Msk 0x1UL
+#define FLASHC_FM_CTL_STATUS_HV_REGS_ISOLATED_Pos 1UL
+#define FLASHC_FM_CTL_STATUS_HV_REGS_ISOLATED_Msk 0x2UL
+#define FLASHC_FM_CTL_STATUS_ILLEGAL_HVOP_Pos 2UL
+#define FLASHC_FM_CTL_STATUS_ILLEGAL_HVOP_Msk 0x4UL
+#define FLASHC_FM_CTL_STATUS_TURBO_N_Pos 3UL
+#define FLASHC_FM_CTL_STATUS_TURBO_N_Msk 0x8UL
+#define FLASHC_FM_CTL_STATUS_WR_EN_MON_Pos 4UL
+#define FLASHC_FM_CTL_STATUS_WR_EN_MON_Msk 0x10UL
+#define FLASHC_FM_CTL_STATUS_IF_SEL_MON_Pos 5UL
+#define FLASHC_FM_CTL_STATUS_IF_SEL_MON_Msk 0x20UL
+/* FLASHC_FM_CTL.FM_ADDR */
+#define FLASHC_FM_CTL_FM_ADDR_RA_Pos 0UL
+#define FLASHC_FM_CTL_FM_ADDR_RA_Msk 0xFFFFUL
+#define FLASHC_FM_CTL_FM_ADDR_BA_Pos 16UL
+#define FLASHC_FM_CTL_FM_ADDR_BA_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_FM_ADDR_AXA_Pos 24UL
+#define FLASHC_FM_CTL_FM_ADDR_AXA_Msk 0x1000000UL
+/* FLASHC_FM_CTL.GEOMETRY */
+#define FLASHC_FM_CTL_GEOMETRY_WORD_SIZE_LOG2_Pos 0UL
+#define FLASHC_FM_CTL_GEOMETRY_WORD_SIZE_LOG2_Msk 0xFUL
+#define FLASHC_FM_CTL_GEOMETRY_PAGE_SIZE_LOG2_Pos 4UL
+#define FLASHC_FM_CTL_GEOMETRY_PAGE_SIZE_LOG2_Msk 0xF0UL
+#define FLASHC_FM_CTL_GEOMETRY_ROW_COUNT_Pos 8UL
+#define FLASHC_FM_CTL_GEOMETRY_ROW_COUNT_Msk 0xFFFF00UL
+#define FLASHC_FM_CTL_GEOMETRY_BANK_COUNT_Pos 24UL
+#define FLASHC_FM_CTL_GEOMETRY_BANK_COUNT_Msk 0xFF000000UL
+/* FLASHC_FM_CTL.GEOMETRY_SUPERVISORY */
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Pos 0UL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Msk 0xFUL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Pos 4UL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Msk 0xF0UL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_ROW_COUNT_Pos 8UL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_ROW_COUNT_Msk 0xFFFF00UL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_BANK_COUNT_Pos 24UL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_BANK_COUNT_Msk 0xFF000000UL
+/* FLASHC_FM_CTL.TIMER_CTL */
+#define FLASHC_FM_CTL_TIMER_CTL_PERIOD_Pos 0UL
+#define FLASHC_FM_CTL_TIMER_CTL_PERIOD_Msk 0xFFFFUL
+#define FLASHC_FM_CTL_TIMER_CTL_SCALE_Pos 16UL
+#define FLASHC_FM_CTL_TIMER_CTL_SCALE_Msk 0x10000UL
+#define FLASHC_FM_CTL_TIMER_CTL_PUMP_CLOCK_SEL_Pos 24UL
+#define FLASHC_FM_CTL_TIMER_CTL_PUMP_CLOCK_SEL_Msk 0x1000000UL
+#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_Pos 25UL
+#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_Msk 0x2000000UL
+#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_CSL_Pos 26UL
+#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_CSL_Msk 0x4000000UL
+#define FLASHC_FM_CTL_TIMER_CTL_PUMP_EN_Pos 29UL
+#define FLASHC_FM_CTL_TIMER_CTL_PUMP_EN_Msk 0x20000000UL
+#define FLASHC_FM_CTL_TIMER_CTL_ACLK_EN_Pos 30UL
+#define FLASHC_FM_CTL_TIMER_CTL_ACLK_EN_Msk 0x40000000UL
+#define FLASHC_FM_CTL_TIMER_CTL_TIMER_EN_Pos 31UL
+#define FLASHC_FM_CTL_TIMER_CTL_TIMER_EN_Msk 0x80000000UL
+/* FLASHC_FM_CTL.ANA_CTL0 */
+#define FLASHC_FM_CTL_ANA_CTL0_CSLDAC_Pos 8UL
+#define FLASHC_FM_CTL_ANA_CTL0_CSLDAC_Msk 0x700UL
+#define FLASHC_FM_CTL_ANA_CTL0_VCC_SEL_Pos 24UL
+#define FLASHC_FM_CTL_ANA_CTL0_VCC_SEL_Msk 0x1000000UL
+#define FLASHC_FM_CTL_ANA_CTL0_FLIP_AMUXBUS_AB_Pos 27UL
+#define FLASHC_FM_CTL_ANA_CTL0_FLIP_AMUXBUS_AB_Msk 0x8000000UL
+/* FLASHC_FM_CTL.ANA_CTL1 */
+#define FLASHC_FM_CTL_ANA_CTL1_MDAC_Pos 0UL
+#define FLASHC_FM_CTL_ANA_CTL1_MDAC_Msk 0xFFUL
+#define FLASHC_FM_CTL_ANA_CTL1_PDAC_Pos 16UL
+#define FLASHC_FM_CTL_ANA_CTL1_PDAC_Msk 0xF0000UL
+#define FLASHC_FM_CTL_ANA_CTL1_NDAC_Pos 24UL
+#define FLASHC_FM_CTL_ANA_CTL1_NDAC_Msk 0xF000000UL
+#define FLASHC_FM_CTL_ANA_CTL1_VPROT_OVERRIDE_Pos 28UL
+#define FLASHC_FM_CTL_ANA_CTL1_VPROT_OVERRIDE_Msk 0x10000000UL
+#define FLASHC_FM_CTL_ANA_CTL1_R_GRANT_CTL_Pos 29UL
+#define FLASHC_FM_CTL_ANA_CTL1_R_GRANT_CTL_Msk 0x20000000UL
+#define FLASHC_FM_CTL_ANA_CTL1_RST_SFT_HVPL_Pos 30UL
+#define FLASHC_FM_CTL_ANA_CTL1_RST_SFT_HVPL_Msk 0x40000000UL
+/* FLASHC_FM_CTL.GEOMETRY_GEN */
+#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_1_Pos 1UL
+#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_1_Msk 0x2UL
+#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_2_Pos 2UL
+#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_2_Msk 0x4UL
+#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_3_Pos 3UL
+#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_3_Msk 0x8UL
+/* FLASHC_FM_CTL.TEST_CTL */
+#define FLASHC_FM_CTL_TEST_CTL_TEST_MODE_Pos 0UL
+#define FLASHC_FM_CTL_TEST_CTL_TEST_MODE_Msk 0x1FUL
+#define FLASHC_FM_CTL_TEST_CTL_PN_CTL_Pos 8UL
+#define FLASHC_FM_CTL_TEST_CTL_PN_CTL_Msk 0x100UL
+#define FLASHC_FM_CTL_TEST_CTL_TM_PE_Pos 9UL
+#define FLASHC_FM_CTL_TEST_CTL_TM_PE_Msk 0x200UL
+#define FLASHC_FM_CTL_TEST_CTL_TM_DISPOS_Pos 10UL
+#define FLASHC_FM_CTL_TEST_CTL_TM_DISPOS_Msk 0x400UL
+#define FLASHC_FM_CTL_TEST_CTL_TM_DISNEG_Pos 11UL
+#define FLASHC_FM_CTL_TEST_CTL_TM_DISNEG_Msk 0x800UL
+#define FLASHC_FM_CTL_TEST_CTL_EN_CLK_MON_Pos 16UL
+#define FLASHC_FM_CTL_TEST_CTL_EN_CLK_MON_Msk 0x10000UL
+#define FLASHC_FM_CTL_TEST_CTL_CSL_DEBUG_Pos 17UL
+#define FLASHC_FM_CTL_TEST_CTL_CSL_DEBUG_Msk 0x20000UL
+#define FLASHC_FM_CTL_TEST_CTL_ENABLE_OSC_Pos 18UL
+#define FLASHC_FM_CTL_TEST_CTL_ENABLE_OSC_Msk 0x40000UL
+#define FLASHC_FM_CTL_TEST_CTL_UNSCRAMBLE_WA_Pos 31UL
+#define FLASHC_FM_CTL_TEST_CTL_UNSCRAMBLE_WA_Msk 0x80000000UL
+/* FLASHC_FM_CTL.WAIT_CTL */
+#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_MEM_RD_Pos 0UL
+#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_MEM_RD_Msk 0xFUL
+#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_RD_Pos 8UL
+#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_RD_Msk 0xF00UL
+#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_WR_Pos 16UL
+#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_WR_Msk 0x70000UL
+/* FLASHC_FM_CTL.MONITOR_STATUS */
+#define FLASHC_FM_CTL_MONITOR_STATUS_POS_PUMP_VLO_Pos 1UL
+#define FLASHC_FM_CTL_MONITOR_STATUS_POS_PUMP_VLO_Msk 0x2UL
+#define FLASHC_FM_CTL_MONITOR_STATUS_NEG_PUMP_VHI_Pos 2UL
+#define FLASHC_FM_CTL_MONITOR_STATUS_NEG_PUMP_VHI_Msk 0x4UL
+/* FLASHC_FM_CTL.SCRATCH_CTL */
+#define FLASHC_FM_CTL_SCRATCH_CTL_DUMMY32_Pos 0UL
+#define FLASHC_FM_CTL_SCRATCH_CTL_DUMMY32_Msk 0xFFFFFFFFUL
+/* FLASHC_FM_CTL.HV_CTL */
+#define FLASHC_FM_CTL_HV_CTL_TIMER_CLOCK_FREQ_Pos 0UL
+#define FLASHC_FM_CTL_HV_CTL_TIMER_CLOCK_FREQ_Msk 0xFFUL
+/* FLASHC_FM_CTL.ACLK_CTL */
+#define FLASHC_FM_CTL_ACLK_CTL_ACLK_GEN_Pos 0UL
+#define FLASHC_FM_CTL_ACLK_CTL_ACLK_GEN_Msk 0x1UL
+/* FLASHC_FM_CTL.INTR */
+#define FLASHC_FM_CTL_INTR_TIMER_EXPIRED_Pos 0UL
+#define FLASHC_FM_CTL_INTR_TIMER_EXPIRED_Msk 0x1UL
+/* FLASHC_FM_CTL.INTR_SET */
+#define FLASHC_FM_CTL_INTR_SET_TIMER_EXPIRED_Pos 0UL
+#define FLASHC_FM_CTL_INTR_SET_TIMER_EXPIRED_Msk 0x1UL
+/* FLASHC_FM_CTL.INTR_MASK */
+#define FLASHC_FM_CTL_INTR_MASK_TIMER_EXPIRED_Pos 0UL
+#define FLASHC_FM_CTL_INTR_MASK_TIMER_EXPIRED_Msk 0x1UL
+/* FLASHC_FM_CTL.INTR_MASKED */
+#define FLASHC_FM_CTL_INTR_MASKED_TIMER_EXPIRED_Pos 0UL
+#define FLASHC_FM_CTL_INTR_MASKED_TIMER_EXPIRED_Msk 0x1UL
+/* FLASHC_FM_CTL.FM_HV_DATA_ALL */
+#define FLASHC_FM_CTL_FM_HV_DATA_ALL_DATA32_Pos 0UL
+#define FLASHC_FM_CTL_FM_HV_DATA_ALL_DATA32_Msk 0xFFFFFFFFUL
+/* FLASHC_FM_CTL.CAL_CTL0 */
+#define FLASHC_FM_CTL_CAL_CTL0_VCT_TRIM_LO_HV_Pos 0UL
+#define FLASHC_FM_CTL_CAL_CTL0_VCT_TRIM_LO_HV_Msk 0x1FUL
+#define FLASHC_FM_CTL_CAL_CTL0_CDAC_LO_HV_Pos 5UL
+#define FLASHC_FM_CTL_CAL_CTL0_CDAC_LO_HV_Msk 0xE0UL
+#define FLASHC_FM_CTL_CAL_CTL0_VBG_TRIM_LO_HV_Pos 8UL
+#define FLASHC_FM_CTL_CAL_CTL0_VBG_TRIM_LO_HV_Msk 0x1F00UL
+#define FLASHC_FM_CTL_CAL_CTL0_VBG_TC_TRIM_LO_HV_Pos 13UL
+#define FLASHC_FM_CTL_CAL_CTL0_VBG_TC_TRIM_LO_HV_Msk 0xE000UL
+#define FLASHC_FM_CTL_CAL_CTL0_IPREF_TRIM_LO_HV_Pos 16UL
+#define FLASHC_FM_CTL_CAL_CTL0_IPREF_TRIM_LO_HV_Msk 0xF0000UL
+/* FLASHC_FM_CTL.CAL_CTL1 */
+#define FLASHC_FM_CTL_CAL_CTL1_VCT_TRIM_HI_HV_Pos 0UL
+#define FLASHC_FM_CTL_CAL_CTL1_VCT_TRIM_HI_HV_Msk 0x1FUL
+#define FLASHC_FM_CTL_CAL_CTL1_CDAC_HI_HV_Pos 5UL
+#define FLASHC_FM_CTL_CAL_CTL1_CDAC_HI_HV_Msk 0xE0UL
+#define FLASHC_FM_CTL_CAL_CTL1_VBG_TRIM_HI_HV_Pos 8UL
+#define FLASHC_FM_CTL_CAL_CTL1_VBG_TRIM_HI_HV_Msk 0x1F00UL
+#define FLASHC_FM_CTL_CAL_CTL1_VBG_TC_TRIM_HI_HV_Pos 13UL
+#define FLASHC_FM_CTL_CAL_CTL1_VBG_TC_TRIM_HI_HV_Msk 0xE000UL
+#define FLASHC_FM_CTL_CAL_CTL1_IPREF_TRIM_HI_HV_Pos 16UL
+#define FLASHC_FM_CTL_CAL_CTL1_IPREF_TRIM_HI_HV_Msk 0xF0000UL
+/* FLASHC_FM_CTL.CAL_CTL2 */
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_LO_HV_Pos 0UL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_LO_HV_Msk 0x1FUL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_LO_HV_Pos 5UL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_LO_HV_Msk 0xE0UL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_HI_HV_Pos 8UL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_HI_HV_Msk 0x1F00UL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_HI_HV_Pos 13UL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_HI_HV_Msk 0xE000UL
+#define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_HV_Pos 16UL
+#define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_HV_Msk 0x10000UL
+#define FLASHC_FM_CTL_CAL_CTL2_IREF_SEL_HV_Pos 17UL
+#define FLASHC_FM_CTL_CAL_CTL2_IREF_SEL_HV_Msk 0x20000UL
+#define FLASHC_FM_CTL_CAL_CTL2_FM_ACTIVE_HV_Pos 18UL
+#define FLASHC_FM_CTL_CAL_CTL2_FM_ACTIVE_HV_Msk 0x40000UL
+#define FLASHC_FM_CTL_CAL_CTL2_TURBO_EXT_HV_Pos 19UL
+#define FLASHC_FM_CTL_CAL_CTL2_TURBO_EXT_HV_Msk 0x80000UL
+/* FLASHC_FM_CTL.CAL_CTL3 */
+#define FLASHC_FM_CTL_CAL_CTL3_OSC_TRIM_HV_Pos 0UL
+#define FLASHC_FM_CTL_CAL_CTL3_OSC_TRIM_HV_Msk 0xFUL
+#define FLASHC_FM_CTL_CAL_CTL3_OSC_RANGE_TRIM_HV_Pos 4UL
+#define FLASHC_FM_CTL_CAL_CTL3_OSC_RANGE_TRIM_HV_Msk 0x10UL
+#define FLASHC_FM_CTL_CAL_CTL3_IDAC_HV_Pos 5UL
+#define FLASHC_FM_CTL_CAL_CTL3_IDAC_HV_Msk 0x1E0UL
+#define FLASHC_FM_CTL_CAL_CTL3_SDAC_HV_Pos 9UL
+#define FLASHC_FM_CTL_CAL_CTL3_SDAC_HV_Msk 0x600UL
+#define FLASHC_FM_CTL_CAL_CTL3_ITIM_HV_Pos 11UL
+#define FLASHC_FM_CTL_CAL_CTL3_ITIM_HV_Msk 0x7800UL
+#define FLASHC_FM_CTL_CAL_CTL3_VDDHI_HV_Pos 15UL
+#define FLASHC_FM_CTL_CAL_CTL3_VDDHI_HV_Msk 0x8000UL
+#define FLASHC_FM_CTL_CAL_CTL3_TURBO_PULSEW_HV_Pos 16UL
+#define FLASHC_FM_CTL_CAL_CTL3_TURBO_PULSEW_HV_Msk 0x30000UL
+#define FLASHC_FM_CTL_CAL_CTL3_BGLO_EN_HV_Pos 18UL
+#define FLASHC_FM_CTL_CAL_CTL3_BGLO_EN_HV_Msk 0x40000UL
+#define FLASHC_FM_CTL_CAL_CTL3_BGHI_EN_HV_Pos 19UL
+#define FLASHC_FM_CTL_CAL_CTL3_BGHI_EN_HV_Msk 0x80000UL
+/* FLASHC_FM_CTL.BOOKMARK */
+#define FLASHC_FM_CTL_BOOKMARK_BOOKMARK_Pos 0UL
+#define FLASHC_FM_CTL_BOOKMARK_BOOKMARK_Msk 0xFFFFFFFFUL
+/* FLASHC_FM_CTL.RED_CTL01 */
+#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_0_Pos 0UL
+#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_0_Msk 0xFFUL
+#define FLASHC_FM_CTL_RED_CTL01_RED_EN_0_Pos 8UL
+#define FLASHC_FM_CTL_RED_CTL01_RED_EN_0_Msk 0x100UL
+#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_1_Pos 16UL
+#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_1_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_RED_CTL01_RED_EN_1_Pos 24UL
+#define FLASHC_FM_CTL_RED_CTL01_RED_EN_1_Msk 0x1000000UL
+/* FLASHC_FM_CTL.RED_CTL23 */
+#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_2_Pos 0UL
+#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_2_Msk 0xFFUL
+#define FLASHC_FM_CTL_RED_CTL23_RED_EN_2_Pos 8UL
+#define FLASHC_FM_CTL_RED_CTL23_RED_EN_2_Msk 0x100UL
+#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_3_Pos 16UL
+#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_3_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_RED_CTL23_RED_EN_3_Pos 24UL
+#define FLASHC_FM_CTL_RED_CTL23_RED_EN_3_Msk 0x1000000UL
+/* FLASHC_FM_CTL.RED_CTL45 */
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_1_Pos 0UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_1_Msk 0x1UL
+#define FLASHC_FM_CTL_RED_CTL45_REG_ACT_HV_Pos 1UL
+#define FLASHC_FM_CTL_RED_CTL45_REG_ACT_HV_Msk 0x2UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_3_Pos 2UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_3_Msk 0x4UL
+#define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_0_Pos 3UL
+#define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_0_Msk 0x8UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_5_Pos 4UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_5_Msk 0x10UL
+#define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_1_Pos 5UL
+#define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_1_Msk 0x20UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_6_Pos 6UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_6_Msk 0x40UL
+#define FLASHC_FM_CTL_RED_CTL45_VLIM_TRIM_HV_0_Pos 7UL
+#define FLASHC_FM_CTL_RED_CTL45_VLIM_TRIM_HV_0_Msk 0x80UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_8_Pos 8UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_8_Msk 0x100UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_23_16_Pos 16UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_23_16_Msk 0xFF0000UL
+/* FLASHC_FM_CTL.RED_CTL67 */
+#define FLASHC_FM_CTL_RED_CTL67_VLIM_TRIM_HV_1_Pos 0UL
+#define FLASHC_FM_CTL_RED_CTL67_VLIM_TRIM_HV_1_Msk 0x1UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_1_Pos 1UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_1_Msk 0x2UL
+#define FLASHC_FM_CTL_RED_CTL67_VPROT_ACT_HV_Pos 2UL
+#define FLASHC_FM_CTL_RED_CTL67_VPROT_ACT_HV_Msk 0x4UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_3_Pos 3UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_3_Msk 0x8UL
+#define FLASHC_FM_CTL_RED_CTL67_IPREF_TC_HV_Pos 4UL
+#define FLASHC_FM_CTL_RED_CTL67_IPREF_TC_HV_Msk 0x10UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_5_Pos 5UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_5_Msk 0x20UL
+#define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_HI_HV_Pos 6UL
+#define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_HI_HV_Msk 0x40UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_7_Pos 7UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_7_Msk 0x80UL
+#define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_LO_HV_Pos 8UL
+#define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_LO_HV_Msk 0x100UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_23_16_Pos 16UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_23_16_Msk 0xFF0000UL
+/* FLASHC_FM_CTL.RED_CTL_SM01 */
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM0_Pos 0UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM0_Msk 0xFFUL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM0_Pos 8UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM0_Msk 0x100UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM1_Pos 16UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM1_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM1_Pos 24UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM1_Msk 0x1000000UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_TRKD_Pos 30UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_TRKD_Msk 0x40000000UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_R_GRANT_EN_Pos 31UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_R_GRANT_EN_Msk 0x80000000UL
+/* FLASHC_FM_CTL.TM_CMPR */
+#define FLASHC_FM_CTL_TM_CMPR_DATA_COMP_RESULT_Pos 0UL
+#define FLASHC_FM_CTL_TM_CMPR_DATA_COMP_RESULT_Msk 0x1UL
+/* FLASHC_FM_CTL.FM_HV_DATA */
+#define FLASHC_FM_CTL_FM_HV_DATA_DATA32_Pos 0UL
+#define FLASHC_FM_CTL_FM_HV_DATA_DATA32_Msk 0xFFFFFFFFUL
+/* FLASHC_FM_CTL.FM_MEM_DATA */
+#define FLASHC_FM_CTL_FM_MEM_DATA_DATA32_Pos 0UL
+#define FLASHC_FM_CTL_FM_MEM_DATA_DATA32_Msk 0xFFFFFFFFUL
+
+
+/* FLASHC.FLASH_CTL */
+#define FLASHC_FLASH_CTL_MAIN_WS_Pos 0UL
+#define FLASHC_FLASH_CTL_MAIN_WS_Msk 0xFUL
+#define FLASHC_FLASH_CTL_REMAP_Pos 8UL
+#define FLASHC_FLASH_CTL_REMAP_Msk 0x100UL
+/* FLASHC.FLASH_PWR_CTL */
+#define FLASHC_FLASH_PWR_CTL_ENABLE_Pos 0UL
+#define FLASHC_FLASH_PWR_CTL_ENABLE_Msk 0x1UL
+#define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Pos 1UL
+#define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Msk 0x2UL
+/* FLASHC.FLASH_CMD */
+#define FLASHC_FLASH_CMD_INV_Pos 0UL
+#define FLASHC_FLASH_CMD_INV_Msk 0x1UL
+/* FLASHC.BIST_CTL */
+#define FLASHC_BIST_CTL_OPCODE_Pos 0UL
+#define FLASHC_BIST_CTL_OPCODE_Msk 0x3UL
+#define FLASHC_BIST_CTL_UP_Pos 2UL
+#define FLASHC_BIST_CTL_UP_Msk 0x4UL
+#define FLASHC_BIST_CTL_ROW_FIRST_Pos 3UL
+#define FLASHC_BIST_CTL_ROW_FIRST_Msk 0x8UL
+#define FLASHC_BIST_CTL_ADDR_START_ENABLED_Pos 4UL
+#define FLASHC_BIST_CTL_ADDR_START_ENABLED_Msk 0x10UL
+#define FLASHC_BIST_CTL_ADDR_COMPLIMENT_ENABLED_Pos 5UL
+#define FLASHC_BIST_CTL_ADDR_COMPLIMENT_ENABLED_Msk 0x20UL
+#define FLASHC_BIST_CTL_INCR_DECR_BOTH_Pos 6UL
+#define FLASHC_BIST_CTL_INCR_DECR_BOTH_Msk 0x40UL
+#define FLASHC_BIST_CTL_STOP_ON_ERROR_Pos 7UL
+#define FLASHC_BIST_CTL_STOP_ON_ERROR_Msk 0x80UL
+/* FLASHC.BIST_CMD */
+#define FLASHC_BIST_CMD_START_Pos 0UL
+#define FLASHC_BIST_CMD_START_Msk 0x1UL
+/* FLASHC.BIST_ADDR_START */
+#define FLASHC_BIST_ADDR_START_COL_ADDR_START_Pos 0UL
+#define FLASHC_BIST_ADDR_START_COL_ADDR_START_Msk 0xFFFFUL
+#define FLASHC_BIST_ADDR_START_ROW_ADDR_START_Pos 16UL
+#define FLASHC_BIST_ADDR_START_ROW_ADDR_START_Msk 0xFFFF0000UL
+/* FLASHC.BIST_DATA */
+#define FLASHC_BIST_DATA_DATA_Pos 0UL
+#define FLASHC_BIST_DATA_DATA_Msk 0xFFFFFFFFUL
+/* FLASHC.BIST_DATA_ACT */
+#define FLASHC_BIST_DATA_ACT_DATA_Pos 0UL
+#define FLASHC_BIST_DATA_ACT_DATA_Msk 0xFFFFFFFFUL
+/* FLASHC.BIST_DATA_EXP */
+#define FLASHC_BIST_DATA_EXP_DATA_Pos 0UL
+#define FLASHC_BIST_DATA_EXP_DATA_Msk 0xFFFFFFFFUL
+/* FLASHC.BIST_ADDR */
+#define FLASHC_BIST_ADDR_COL_ADDR_Pos 0UL
+#define FLASHC_BIST_ADDR_COL_ADDR_Msk 0xFFFFUL
+#define FLASHC_BIST_ADDR_ROW_ADDR_Pos 16UL
+#define FLASHC_BIST_ADDR_ROW_ADDR_Msk 0xFFFF0000UL
+/* FLASHC.BIST_STATUS */
+#define FLASHC_BIST_STATUS_FAIL_Pos 0UL
+#define FLASHC_BIST_STATUS_FAIL_Msk 0x1UL
+/* FLASHC.CM0_CA_CTL0 */
+#define FLASHC_CM0_CA_CTL0_WAY_Pos 16UL
+#define FLASHC_CM0_CA_CTL0_WAY_Msk 0x30000UL
+#define FLASHC_CM0_CA_CTL0_SET_ADDR_Pos 24UL
+#define FLASHC_CM0_CA_CTL0_SET_ADDR_Msk 0x7000000UL
+#define FLASHC_CM0_CA_CTL0_PREF_EN_Pos 30UL
+#define FLASHC_CM0_CA_CTL0_PREF_EN_Msk 0x40000000UL
+#define FLASHC_CM0_CA_CTL0_ENABLED_Pos 31UL
+#define FLASHC_CM0_CA_CTL0_ENABLED_Msk 0x80000000UL
+/* FLASHC.CM0_CA_CTL1 */
+#define FLASHC_CM0_CA_CTL1_PWR_MODE_Pos 0UL
+#define FLASHC_CM0_CA_CTL1_PWR_MODE_Msk 0x3UL
+#define FLASHC_CM0_CA_CTL1_VECTKEYSTAT_Pos 16UL
+#define FLASHC_CM0_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* FLASHC.CM0_CA_CTL2 */
+#define FLASHC_CM0_CA_CTL2_PWRUP_DELAY_Pos 0UL
+#define FLASHC_CM0_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL
+/* FLASHC.CM0_CA_CMD */
+#define FLASHC_CM0_CA_CMD_INV_Pos 0UL
+#define FLASHC_CM0_CA_CMD_INV_Msk 0x1UL
+/* FLASHC.CM0_CA_STATUS0 */
+#define FLASHC_CM0_CA_STATUS0_VALID16_Pos 0UL
+#define FLASHC_CM0_CA_STATUS0_VALID16_Msk 0xFFFFUL
+/* FLASHC.CM0_CA_STATUS1 */
+#define FLASHC_CM0_CA_STATUS1_TAG_Pos 0UL
+#define FLASHC_CM0_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL
+/* FLASHC.CM0_CA_STATUS2 */
+#define FLASHC_CM0_CA_STATUS2_LRU_Pos 0UL
+#define FLASHC_CM0_CA_STATUS2_LRU_Msk 0x3FUL
+/* FLASHC.CM4_CA_CTL0 */
+#define FLASHC_CM4_CA_CTL0_WAY_Pos 16UL
+#define FLASHC_CM4_CA_CTL0_WAY_Msk 0x30000UL
+#define FLASHC_CM4_CA_CTL0_SET_ADDR_Pos 24UL
+#define FLASHC_CM4_CA_CTL0_SET_ADDR_Msk 0x7000000UL
+#define FLASHC_CM4_CA_CTL0_PREF_EN_Pos 30UL
+#define FLASHC_CM4_CA_CTL0_PREF_EN_Msk 0x40000000UL
+#define FLASHC_CM4_CA_CTL0_ENABLED_Pos 31UL
+#define FLASHC_CM4_CA_CTL0_ENABLED_Msk 0x80000000UL
+/* FLASHC.CM4_CA_CTL1 */
+#define FLASHC_CM4_CA_CTL1_PWR_MODE_Pos 0UL
+#define FLASHC_CM4_CA_CTL1_PWR_MODE_Msk 0x3UL
+#define FLASHC_CM4_CA_CTL1_VECTKEYSTAT_Pos 16UL
+#define FLASHC_CM4_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* FLASHC.CM4_CA_CTL2 */
+#define FLASHC_CM4_CA_CTL2_PWRUP_DELAY_Pos 0UL
+#define FLASHC_CM4_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL
+/* FLASHC.CM4_CA_CMD */
+#define FLASHC_CM4_CA_CMD_INV_Pos 0UL
+#define FLASHC_CM4_CA_CMD_INV_Msk 0x1UL
+/* FLASHC.CM4_CA_STATUS0 */
+#define FLASHC_CM4_CA_STATUS0_VALID16_Pos 0UL
+#define FLASHC_CM4_CA_STATUS0_VALID16_Msk 0xFFFFUL
+/* FLASHC.CM4_CA_STATUS1 */
+#define FLASHC_CM4_CA_STATUS1_TAG_Pos 0UL
+#define FLASHC_CM4_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL
+/* FLASHC.CM4_CA_STATUS2 */
+#define FLASHC_CM4_CA_STATUS2_LRU_Pos 0UL
+#define FLASHC_CM4_CA_STATUS2_LRU_Msk 0x3FUL
+/* FLASHC.CRYPTO_BUFF_CTL */
+#define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+#define FLASHC_CRYPTO_BUFF_CTL_ENABLED_Pos 31UL
+#define FLASHC_CRYPTO_BUFF_CTL_ENABLED_Msk 0x80000000UL
+/* FLASHC.CRYPTO_BUFF_CMD */
+#define FLASHC_CRYPTO_BUFF_CMD_INV_Pos 0UL
+#define FLASHC_CRYPTO_BUFF_CMD_INV_Msk 0x1UL
+/* FLASHC.DW0_BUFF_CTL */
+#define FLASHC_DW0_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_DW0_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+#define FLASHC_DW0_BUFF_CTL_ENABLED_Pos 31UL
+#define FLASHC_DW0_BUFF_CTL_ENABLED_Msk 0x80000000UL
+/* FLASHC.DW0_BUFF_CMD */
+#define FLASHC_DW0_BUFF_CMD_INV_Pos 0UL
+#define FLASHC_DW0_BUFF_CMD_INV_Msk 0x1UL
+/* FLASHC.DW1_BUFF_CTL */
+#define FLASHC_DW1_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_DW1_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+#define FLASHC_DW1_BUFF_CTL_ENABLED_Pos 31UL
+#define FLASHC_DW1_BUFF_CTL_ENABLED_Msk 0x80000000UL
+/* FLASHC.DW1_BUFF_CMD */
+#define FLASHC_DW1_BUFF_CMD_INV_Pos 0UL
+#define FLASHC_DW1_BUFF_CMD_INV_Msk 0x1UL
+/* FLASHC.DAP_BUFF_CTL */
+#define FLASHC_DAP_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_DAP_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+#define FLASHC_DAP_BUFF_CTL_ENABLED_Pos 31UL
+#define FLASHC_DAP_BUFF_CTL_ENABLED_Msk 0x80000000UL
+/* FLASHC.DAP_BUFF_CMD */
+#define FLASHC_DAP_BUFF_CMD_INV_Pos 0UL
+#define FLASHC_DAP_BUFF_CMD_INV_Msk 0x1UL
+/* FLASHC.EXT_MS0_BUFF_CTL */
+#define FLASHC_EXT_MS0_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_EXT_MS0_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+#define FLASHC_EXT_MS0_BUFF_CTL_ENABLED_Pos 31UL
+#define FLASHC_EXT_MS0_BUFF_CTL_ENABLED_Msk 0x80000000UL
+/* FLASHC.EXT_MS0_BUFF_CMD */
+#define FLASHC_EXT_MS0_BUFF_CMD_INV_Pos 0UL
+#define FLASHC_EXT_MS0_BUFF_CMD_INV_Msk 0x1UL
+/* FLASHC.EXT_MS1_BUFF_CTL */
+#define FLASHC_EXT_MS1_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_EXT_MS1_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+#define FLASHC_EXT_MS1_BUFF_CTL_ENABLED_Pos 31UL
+#define FLASHC_EXT_MS1_BUFF_CTL_ENABLED_Msk 0x80000000UL
+/* FLASHC.EXT_MS1_BUFF_CMD */
+#define FLASHC_EXT_MS1_BUFF_CMD_INV_Pos 0UL
+#define FLASHC_EXT_MS1_BUFF_CMD_INV_Msk 0x1UL
+
+
+#endif /* _CYIP_FLASHC_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_flashc_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_flashc_v2.h
new file mode 100644
index 0000000000..4eceb50692
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_flashc_v2.h
@@ -0,0 +1,718 @@
+/***************************************************************************//**
+* \file cyip_flashc_v2.h
+*
+* \brief
+* FLASHC IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_FLASHC_V2_H_
+#define _CYIP_FLASHC_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* FLASHC
+*******************************************************************************/
+
+#define FLASHC_FM_CTL_V2_SECTION_SIZE 0x00001000UL
+#define FLASHC_V2_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Flash Macro Registers (FLASHC_FM_CTL)
+ */
+typedef struct {
+ __IOM uint32_t FM_CTL; /*!< 0x00000000 Flash macro control */
+ __IM uint32_t STATUS; /*!< 0x00000004 Status */
+ __IOM uint32_t FM_ADDR; /*!< 0x00000008 Flash macro address */
+ __IOM uint32_t BOOKMARK; /*!< 0x0000000C Bookmark register - keeps the current FW HV seq */
+ __IM uint32_t GEOMETRY; /*!< 0x00000010 Regular flash geometry */
+ __IM uint32_t GEOMETRY_SUPERVISORY; /*!< 0x00000014 Supervisory flash geometry */
+ __IOM uint32_t ANA_CTL0; /*!< 0x00000018 Analog control 0 */
+ __IOM uint32_t ANA_CTL1; /*!< 0x0000001C Analog control 1 */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t WAIT_CTL; /*!< 0x00000028 Wait State control */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t TIMER_CLK_CTL; /*!< 0x00000034 Timer prescaler (clk_t to timer clock frequency divider) */
+ __IOM uint32_t TIMER_CTL; /*!< 0x00000038 Timer control */
+ __OM uint32_t ACLK_CTL; /*!< 0x0000003C MPCON clock */
+ __IOM uint32_t INTR; /*!< 0x00000040 Interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x00000044 Interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000048 Interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000004C Interrupt masked */
+ __IOM uint32_t CAL_CTL0; /*!< 0x00000050 Cal control BG LO trim bits */
+ __IOM uint32_t CAL_CTL1; /*!< 0x00000054 Cal control BG HI trim bits */
+ __IOM uint32_t CAL_CTL2; /*!< 0x00000058 Cal control BG LO&HI trim bits */
+ __IOM uint32_t CAL_CTL3; /*!< 0x0000005C Cal control osc trim bits, idac, sdac, itim */
+ __IOM uint32_t CAL_CTL4; /*!< 0x00000060 Cal Control Vlim, SA, fdiv, reg_act */
+ __IOM uint32_t CAL_CTL5; /*!< 0x00000064 Cal control */
+ __IOM uint32_t CAL_CTL6; /*!< 0x00000068 SA trim LP/ULP */
+ __IOM uint32_t CAL_CTL7; /*!< 0x0000006C Cal control */
+ __IM uint32_t RESERVED2[4];
+ __IOM uint32_t RED_CTL01; /*!< 0x00000080 Redundancy Control normal sectors 0,1 */
+ __IOM uint32_t RED_CTL23; /*!< 0x00000084 Redundancy Control normal sectors 2,3 */
+ __IOM uint32_t RED_CTL45; /*!< 0x00000088 Redundancy Control normal sectors 4,5 */
+ __IOM uint32_t RED_CTL67; /*!< 0x0000008C Redundancy Control normal sectors 6,7 */
+ __IOM uint32_t RED_CTL_SM01; /*!< 0x00000090 Redundancy Control special sectors 0,1 */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t RGRANT_DELAY_PRG; /*!< 0x00000098 R-grant delay for program */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t PW_SEQ12; /*!< 0x000000A0 HV Pulse Delay for seq 1&2 pre */
+ __IOM uint32_t PW_SEQ23; /*!< 0x000000A4 HV Pulse Delay for seq2 post & seq3 */
+ __IOM uint32_t RGRANT_SCALE_ERS; /*!< 0x000000A8 R-grant delay scale for erase */
+ __IOM uint32_t RGRANT_DELAY_ERS; /*!< 0x000000AC R-grant delay for erase */
+ __IM uint32_t RESERVED5[467];
+ __IOM uint32_t FM_PL_WRDATA_ALL; /*!< 0x000007FC Flash macro write page latches all */
+ __IOM uint32_t FM_PL_DATA[256]; /*!< 0x00000800 Flash macro Page Latches data */
+ __IM uint32_t FM_MEM_DATA[256]; /*!< 0x00000C00 Flash macro memory sense amplifier and column decoder data */
+} FLASHC_FM_CTL_V2_Type; /*!< Size = 4096 (0x1000) */
+
+/**
+ * \brief Flash controller (FLASHC)
+ */
+typedef struct {
+ __IOM uint32_t FLASH_CTL; /*!< 0x00000000 Control */
+ __IOM uint32_t FLASH_PWR_CTL; /*!< 0x00000004 Flash power control */
+ __IOM uint32_t FLASH_CMD; /*!< 0x00000008 Command */
+ __IM uint32_t RESERVED[165];
+ __IOM uint32_t ECC_CTL; /*!< 0x000002A0 ECC control */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t FM_SRAM_ECC_CTL0; /*!< 0x000002B0 eCT Flash SRAM ECC control 0 */
+ __IOM uint32_t FM_SRAM_ECC_CTL1; /*!< 0x000002B4 eCT Flash SRAM ECC control 1 */
+ __IM uint32_t FM_SRAM_ECC_CTL2; /*!< 0x000002B8 eCT Flash SRAM ECC control 2 */
+ __IOM uint32_t FM_SRAM_ECC_CTL3; /*!< 0x000002BC eCT Flash SRAM ECC control 3 */
+ __IM uint32_t RESERVED2[80];
+ __IOM uint32_t CM0_CA_CTL0; /*!< 0x00000400 CM0+ cache control */
+ __IOM uint32_t CM0_CA_CTL1; /*!< 0x00000404 CM0+ cache control */
+ __IOM uint32_t CM0_CA_CTL2; /*!< 0x00000408 CM0+ cache control */
+ __IM uint32_t RESERVED3[13];
+ __IM uint32_t CM0_CA_STATUS0; /*!< 0x00000440 CM0+ cache status 0 */
+ __IM uint32_t CM0_CA_STATUS1; /*!< 0x00000444 CM0+ cache status 1 */
+ __IM uint32_t CM0_CA_STATUS2; /*!< 0x00000448 CM0+ cache status 2 */
+ __IM uint32_t RESERVED4[5];
+ __IOM uint32_t CM0_STATUS; /*!< 0x00000460 CM0+ interface status */
+ __IM uint32_t RESERVED5[7];
+ __IOM uint32_t CM4_CA_CTL0; /*!< 0x00000480 CM4 cache control */
+ __IOM uint32_t CM4_CA_CTL1; /*!< 0x00000484 CM4 cache control */
+ __IOM uint32_t CM4_CA_CTL2; /*!< 0x00000488 CM4 cache control */
+ __IM uint32_t RESERVED6[13];
+ __IM uint32_t CM4_CA_STATUS0; /*!< 0x000004C0 CM4 cache status 0 */
+ __IM uint32_t CM4_CA_STATUS1; /*!< 0x000004C4 CM4 cache status 1 */
+ __IM uint32_t CM4_CA_STATUS2; /*!< 0x000004C8 CM4 cache status 2 */
+ __IM uint32_t RESERVED7[5];
+ __IOM uint32_t CM4_STATUS; /*!< 0x000004E0 CM4 interface status */
+ __IM uint32_t RESERVED8[7];
+ __IOM uint32_t CRYPTO_BUFF_CTL; /*!< 0x00000500 Cryptography buffer control */
+ __IM uint32_t RESERVED9[31];
+ __IOM uint32_t DW0_BUFF_CTL; /*!< 0x00000580 Datawire 0 buffer control */
+ __IM uint32_t RESERVED10[31];
+ __IOM uint32_t DW1_BUFF_CTL; /*!< 0x00000600 Datawire 1 buffer control */
+ __IM uint32_t RESERVED11[31];
+ __IOM uint32_t DMAC_BUFF_CTL; /*!< 0x00000680 DMA controller buffer control */
+ __IM uint32_t RESERVED12[31];
+ __IOM uint32_t EXT_MS0_BUFF_CTL; /*!< 0x00000700 External master 0 buffer control */
+ __IM uint32_t RESERVED13[31];
+ __IOM uint32_t EXT_MS1_BUFF_CTL; /*!< 0x00000780 External master 1 buffer control */
+ __IM uint32_t RESERVED14[14879];
+ FLASHC_FM_CTL_V2_Type FM_CTL; /*!< 0x0000F000 Flash Macro Registers */
+} FLASHC_V2_Type; /*!< Size = 65536 (0x10000) */
+
+
+/* FLASHC_FM_CTL.FM_CTL */
+#define FLASHC_FM_CTL_V2_FM_CTL_FM_MODE_Pos 0UL
+#define FLASHC_FM_CTL_V2_FM_CTL_FM_MODE_Msk 0xFUL
+#define FLASHC_FM_CTL_V2_FM_CTL_FM_SEQ_Pos 8UL
+#define FLASHC_FM_CTL_V2_FM_CTL_FM_SEQ_Msk 0x300UL
+#define FLASHC_FM_CTL_V2_FM_CTL_DAA_MUX_SEL_Pos 16UL
+#define FLASHC_FM_CTL_V2_FM_CTL_DAA_MUX_SEL_Msk 0x7F0000UL
+#define FLASHC_FM_CTL_V2_FM_CTL_IF_SEL_Pos 24UL
+#define FLASHC_FM_CTL_V2_FM_CTL_IF_SEL_Msk 0x1000000UL
+#define FLASHC_FM_CTL_V2_FM_CTL_WR_EN_Pos 25UL
+#define FLASHC_FM_CTL_V2_FM_CTL_WR_EN_Msk 0x2000000UL
+/* FLASHC_FM_CTL.STATUS */
+#define FLASHC_FM_CTL_V2_STATUS_TIMER_ENABLED_Pos 0UL
+#define FLASHC_FM_CTL_V2_STATUS_TIMER_ENABLED_Msk 0x1UL
+#define FLASHC_FM_CTL_V2_STATUS_HV_REGS_ISOLATED_Pos 1UL
+#define FLASHC_FM_CTL_V2_STATUS_HV_REGS_ISOLATED_Msk 0x2UL
+#define FLASHC_FM_CTL_V2_STATUS_ILLEGAL_HVOP_Pos 2UL
+#define FLASHC_FM_CTL_V2_STATUS_ILLEGAL_HVOP_Msk 0x4UL
+#define FLASHC_FM_CTL_V2_STATUS_TURBO_N_Pos 3UL
+#define FLASHC_FM_CTL_V2_STATUS_TURBO_N_Msk 0x8UL
+#define FLASHC_FM_CTL_V2_STATUS_WR_EN_MON_Pos 4UL
+#define FLASHC_FM_CTL_V2_STATUS_WR_EN_MON_Msk 0x10UL
+#define FLASHC_FM_CTL_V2_STATUS_IF_SEL_MON_Pos 5UL
+#define FLASHC_FM_CTL_V2_STATUS_IF_SEL_MON_Msk 0x20UL
+#define FLASHC_FM_CTL_V2_STATUS_TIMER_STATUS_Pos 6UL
+#define FLASHC_FM_CTL_V2_STATUS_TIMER_STATUS_Msk 0x40UL
+#define FLASHC_FM_CTL_V2_STATUS_R_GRANT_DELAY_STATUS_Pos 7UL
+#define FLASHC_FM_CTL_V2_STATUS_R_GRANT_DELAY_STATUS_Msk 0x80UL
+#define FLASHC_FM_CTL_V2_STATUS_FM_BUSY_Pos 8UL
+#define FLASHC_FM_CTL_V2_STATUS_FM_BUSY_Msk 0x100UL
+#define FLASHC_FM_CTL_V2_STATUS_FM_READY_Pos 9UL
+#define FLASHC_FM_CTL_V2_STATUS_FM_READY_Msk 0x200UL
+#define FLASHC_FM_CTL_V2_STATUS_POS_PUMP_VLO_Pos 10UL
+#define FLASHC_FM_CTL_V2_STATUS_POS_PUMP_VLO_Msk 0x400UL
+#define FLASHC_FM_CTL_V2_STATUS_NEG_PUMP_VHI_Pos 11UL
+#define FLASHC_FM_CTL_V2_STATUS_NEG_PUMP_VHI_Msk 0x800UL
+#define FLASHC_FM_CTL_V2_STATUS_RWW_Pos 12UL
+#define FLASHC_FM_CTL_V2_STATUS_RWW_Msk 0x1000UL
+#define FLASHC_FM_CTL_V2_STATUS_MAX_DOUT_WIDTH_Pos 13UL
+#define FLASHC_FM_CTL_V2_STATUS_MAX_DOUT_WIDTH_Msk 0x2000UL
+#define FLASHC_FM_CTL_V2_STATUS_SECTOR0_SR_Pos 14UL
+#define FLASHC_FM_CTL_V2_STATUS_SECTOR0_SR_Msk 0x4000UL
+#define FLASHC_FM_CTL_V2_STATUS_RESET_MM_Pos 15UL
+#define FLASHC_FM_CTL_V2_STATUS_RESET_MM_Msk 0x8000UL
+#define FLASHC_FM_CTL_V2_STATUS_ROW_ODD_Pos 16UL
+#define FLASHC_FM_CTL_V2_STATUS_ROW_ODD_Msk 0x10000UL
+#define FLASHC_FM_CTL_V2_STATUS_ROW_EVEN_Pos 17UL
+#define FLASHC_FM_CTL_V2_STATUS_ROW_EVEN_Msk 0x20000UL
+#define FLASHC_FM_CTL_V2_STATUS_HVOP_SUB_SECTOR_N_Pos 18UL
+#define FLASHC_FM_CTL_V2_STATUS_HVOP_SUB_SECTOR_N_Msk 0x40000UL
+#define FLASHC_FM_CTL_V2_STATUS_HVOP_SECTOR_Pos 19UL
+#define FLASHC_FM_CTL_V2_STATUS_HVOP_SECTOR_Msk 0x80000UL
+#define FLASHC_FM_CTL_V2_STATUS_HVOP_BULK_ALL_Pos 20UL
+#define FLASHC_FM_CTL_V2_STATUS_HVOP_BULK_ALL_Msk 0x100000UL
+#define FLASHC_FM_CTL_V2_STATUS_CBUS_RA_MATCH_Pos 21UL
+#define FLASHC_FM_CTL_V2_STATUS_CBUS_RA_MATCH_Msk 0x200000UL
+#define FLASHC_FM_CTL_V2_STATUS_CBUS_RED_ROW_EN_Pos 22UL
+#define FLASHC_FM_CTL_V2_STATUS_CBUS_RED_ROW_EN_Msk 0x400000UL
+#define FLASHC_FM_CTL_V2_STATUS_RQ_ERROR_Pos 23UL
+#define FLASHC_FM_CTL_V2_STATUS_RQ_ERROR_Msk 0x800000UL
+#define FLASHC_FM_CTL_V2_STATUS_PUMP_PDAC_Pos 24UL
+#define FLASHC_FM_CTL_V2_STATUS_PUMP_PDAC_Msk 0xF000000UL
+#define FLASHC_FM_CTL_V2_STATUS_PUMP_NDAC_Pos 28UL
+#define FLASHC_FM_CTL_V2_STATUS_PUMP_NDAC_Msk 0xF0000000UL
+/* FLASHC_FM_CTL.FM_ADDR */
+#define FLASHC_FM_CTL_V2_FM_ADDR_RA_Pos 0UL
+#define FLASHC_FM_CTL_V2_FM_ADDR_RA_Msk 0xFFFFUL
+#define FLASHC_FM_CTL_V2_FM_ADDR_BA_Pos 16UL
+#define FLASHC_FM_CTL_V2_FM_ADDR_BA_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_V2_FM_ADDR_AXA_Pos 24UL
+#define FLASHC_FM_CTL_V2_FM_ADDR_AXA_Msk 0x1000000UL
+/* FLASHC_FM_CTL.BOOKMARK */
+#define FLASHC_FM_CTL_V2_BOOKMARK_BOOKMARK_Pos 0UL
+#define FLASHC_FM_CTL_V2_BOOKMARK_BOOKMARK_Msk 0xFFFFFFFFUL
+/* FLASHC_FM_CTL.GEOMETRY */
+#define FLASHC_FM_CTL_V2_GEOMETRY_ROW_COUNT_Pos 0UL
+#define FLASHC_FM_CTL_V2_GEOMETRY_ROW_COUNT_Msk 0xFFFFUL
+#define FLASHC_FM_CTL_V2_GEOMETRY_BANK_COUNT_Pos 16UL
+#define FLASHC_FM_CTL_V2_GEOMETRY_BANK_COUNT_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_V2_GEOMETRY_WORD_SIZE_LOG2_Pos 24UL
+#define FLASHC_FM_CTL_V2_GEOMETRY_WORD_SIZE_LOG2_Msk 0xF000000UL
+#define FLASHC_FM_CTL_V2_GEOMETRY_PAGE_SIZE_LOG2_Pos 28UL
+#define FLASHC_FM_CTL_V2_GEOMETRY_PAGE_SIZE_LOG2_Msk 0xF0000000UL
+/* FLASHC_FM_CTL.GEOMETRY_SUPERVISORY */
+#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_ROW_COUNT_Pos 0UL
+#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_ROW_COUNT_Msk 0xFFFFUL
+#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_BANK_COUNT_Pos 16UL
+#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_BANK_COUNT_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Pos 24UL
+#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Msk 0xF000000UL
+#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Pos 28UL
+#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Msk 0xF0000000UL
+/* FLASHC_FM_CTL.ANA_CTL0 */
+#define FLASHC_FM_CTL_V2_ANA_CTL0_MDAC_Pos 0UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_MDAC_Msk 0xFFUL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_CSLDAC_Pos 8UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_CSLDAC_Msk 0x700UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_FLIP_AMUXBUS_AB_Pos 11UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_FLIP_AMUXBUS_AB_Msk 0x800UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_NDAC_MIN_Pos 12UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_NDAC_MIN_Msk 0xF000UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_PDAC_MIN_Pos 16UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_PDAC_MIN_Msk 0xF0000UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_SEQ01_Pos 20UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_SEQ01_Msk 0x300000UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_SEQ12_Pos 22UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_SEQ12_Msk 0xC00000UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_SEQ23_Pos 24UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_SEQ23_Msk 0x3000000UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_SEQ30_Pos 26UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_SEQ30_Msk 0xC000000UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_PEON_Pos 28UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_PEON_Msk 0x30000000UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_PEOFF_Pos 30UL
+#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_PEOFF_Msk 0xC0000000UL
+/* FLASHC_FM_CTL.ANA_CTL1 */
+#define FLASHC_FM_CTL_V2_ANA_CTL1_NDAC_MAX_Pos 0UL
+#define FLASHC_FM_CTL_V2_ANA_CTL1_NDAC_MAX_Msk 0xFUL
+#define FLASHC_FM_CTL_V2_ANA_CTL1_NDAC_STEP_Pos 4UL
+#define FLASHC_FM_CTL_V2_ANA_CTL1_NDAC_STEP_Msk 0xF0UL
+#define FLASHC_FM_CTL_V2_ANA_CTL1_PDAC_MAX_Pos 8UL
+#define FLASHC_FM_CTL_V2_ANA_CTL1_PDAC_MAX_Msk 0xF00UL
+#define FLASHC_FM_CTL_V2_ANA_CTL1_PDAC_STEP_Pos 12UL
+#define FLASHC_FM_CTL_V2_ANA_CTL1_PDAC_STEP_Msk 0xF000UL
+#define FLASHC_FM_CTL_V2_ANA_CTL1_NPDAC_STEP_TIME_Pos 16UL
+#define FLASHC_FM_CTL_V2_ANA_CTL1_NPDAC_STEP_TIME_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_V2_ANA_CTL1_NPDAC_ZERO_TIME_Pos 24UL
+#define FLASHC_FM_CTL_V2_ANA_CTL1_NPDAC_ZERO_TIME_Msk 0xFF000000UL
+/* FLASHC_FM_CTL.WAIT_CTL */
+#define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_MEM_RD_Pos 0UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_MEM_RD_Msk 0xFUL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_HV_RD_Pos 8UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_HV_RD_Msk 0xF00UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_HV_WR_Pos 16UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_HV_WR_Msk 0x70000UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_FM_RWW_MODE_Pos 24UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_FM_RWW_MODE_Msk 0x3000000UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_LV_SPARE_1_Pos 26UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_LV_SPARE_1_Msk 0x4000000UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_DRMM_Pos 27UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_DRMM_Msk 0x8000000UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_MBA_Pos 28UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_MBA_Msk 0x10000000UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_PL_SOFT_SET_EN_Pos 29UL
+#define FLASHC_FM_CTL_V2_WAIT_CTL_PL_SOFT_SET_EN_Msk 0x20000000UL
+/* FLASHC_FM_CTL.TIMER_CLK_CTL */
+#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_TIMER_CLOCK_FREQ_Pos 0UL
+#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_TIMER_CLOCK_FREQ_Msk 0xFFUL
+#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PRG_PEON_Pos 8UL
+#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PRG_PEON_Msk 0xFF00UL
+#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PRG_PEOFF_Pos 16UL
+#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PRG_PEOFF_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PRG_SEQ01_Pos 24UL
+#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PRG_SEQ01_Msk 0xFF000000UL
+/* FLASHC_FM_CTL.TIMER_CTL */
+#define FLASHC_FM_CTL_V2_TIMER_CTL_PERIOD_Pos 0UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_PERIOD_Msk 0x7FFFUL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_SCALE_Pos 15UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_SCALE_Msk 0x8000UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_AUTO_SEQUENCE_Pos 24UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_AUTO_SEQUENCE_Msk 0x1000000UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_PRE_PROG_Pos 25UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_PRE_PROG_Msk 0x2000000UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_PRE_PROG_CSL_Pos 26UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_PRE_PROG_CSL_Msk 0x4000000UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_PUMP_EN_Pos 29UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_PUMP_EN_Msk 0x20000000UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_ACLK_EN_Pos 30UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_ACLK_EN_Msk 0x40000000UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_TIMER_EN_Pos 31UL
+#define FLASHC_FM_CTL_V2_TIMER_CTL_TIMER_EN_Msk 0x80000000UL
+/* FLASHC_FM_CTL.ACLK_CTL */
+#define FLASHC_FM_CTL_V2_ACLK_CTL_ACLK_GEN_Pos 0UL
+#define FLASHC_FM_CTL_V2_ACLK_CTL_ACLK_GEN_Msk 0x1UL
+/* FLASHC_FM_CTL.INTR */
+#define FLASHC_FM_CTL_V2_INTR_TIMER_EXPIRED_Pos 0UL
+#define FLASHC_FM_CTL_V2_INTR_TIMER_EXPIRED_Msk 0x1UL
+/* FLASHC_FM_CTL.INTR_SET */
+#define FLASHC_FM_CTL_V2_INTR_SET_TIMER_EXPIRED_Pos 0UL
+#define FLASHC_FM_CTL_V2_INTR_SET_TIMER_EXPIRED_Msk 0x1UL
+/* FLASHC_FM_CTL.INTR_MASK */
+#define FLASHC_FM_CTL_V2_INTR_MASK_TIMER_EXPIRED_Pos 0UL
+#define FLASHC_FM_CTL_V2_INTR_MASK_TIMER_EXPIRED_Msk 0x1UL
+/* FLASHC_FM_CTL.INTR_MASKED */
+#define FLASHC_FM_CTL_V2_INTR_MASKED_TIMER_EXPIRED_Pos 0UL
+#define FLASHC_FM_CTL_V2_INTR_MASKED_TIMER_EXPIRED_Msk 0x1UL
+/* FLASHC_FM_CTL.CAL_CTL0 */
+#define FLASHC_FM_CTL_V2_CAL_CTL0_VCT_TRIM_LO_HV_Pos 0UL
+#define FLASHC_FM_CTL_V2_CAL_CTL0_VCT_TRIM_LO_HV_Msk 0x1FUL
+#define FLASHC_FM_CTL_V2_CAL_CTL0_CDAC_LO_HV_Pos 5UL
+#define FLASHC_FM_CTL_V2_CAL_CTL0_CDAC_LO_HV_Msk 0xE0UL
+#define FLASHC_FM_CTL_V2_CAL_CTL0_VBG_TRIM_LO_HV_Pos 8UL
+#define FLASHC_FM_CTL_V2_CAL_CTL0_VBG_TRIM_LO_HV_Msk 0x1F00UL
+#define FLASHC_FM_CTL_V2_CAL_CTL0_VBG_TC_TRIM_LO_HV_Pos 13UL
+#define FLASHC_FM_CTL_V2_CAL_CTL0_VBG_TC_TRIM_LO_HV_Msk 0xE000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL0_ICREF_TC_TRIM_LO_HV_Pos 16UL
+#define FLASHC_FM_CTL_V2_CAL_CTL0_ICREF_TC_TRIM_LO_HV_Msk 0x70000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL0_IPREF_TRIMA_LO_HV_Pos 19UL
+#define FLASHC_FM_CTL_V2_CAL_CTL0_IPREF_TRIMA_LO_HV_Msk 0x80000UL
+/* FLASHC_FM_CTL.CAL_CTL1 */
+#define FLASHC_FM_CTL_V2_CAL_CTL1_VCT_TRIM_HI_HV_Pos 0UL
+#define FLASHC_FM_CTL_V2_CAL_CTL1_VCT_TRIM_HI_HV_Msk 0x1FUL
+#define FLASHC_FM_CTL_V2_CAL_CTL1_CDAC_HI_HV_Pos 5UL
+#define FLASHC_FM_CTL_V2_CAL_CTL1_CDAC_HI_HV_Msk 0xE0UL
+#define FLASHC_FM_CTL_V2_CAL_CTL1_VBG_TRIM_HI_HV_Pos 8UL
+#define FLASHC_FM_CTL_V2_CAL_CTL1_VBG_TRIM_HI_HV_Msk 0x1F00UL
+#define FLASHC_FM_CTL_V2_CAL_CTL1_VBG_TC_TRIM_HI_HV_Pos 13UL
+#define FLASHC_FM_CTL_V2_CAL_CTL1_VBG_TC_TRIM_HI_HV_Msk 0xE000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL1_ICREF_TC_TRIM_HI_HV_Pos 16UL
+#define FLASHC_FM_CTL_V2_CAL_CTL1_ICREF_TC_TRIM_HI_HV_Msk 0x70000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL1_IPREF_TRIMA_HI_HV_Pos 19UL
+#define FLASHC_FM_CTL_V2_CAL_CTL1_IPREF_TRIMA_HI_HV_Msk 0x80000UL
+/* FLASHC_FM_CTL.CAL_CTL2 */
+#define FLASHC_FM_CTL_V2_CAL_CTL2_ICREF_TRIM_LO_HV_Pos 0UL
+#define FLASHC_FM_CTL_V2_CAL_CTL2_ICREF_TRIM_LO_HV_Msk 0x1FUL
+#define FLASHC_FM_CTL_V2_CAL_CTL2_ICREF_TRIM_HI_HV_Pos 5UL
+#define FLASHC_FM_CTL_V2_CAL_CTL2_ICREF_TRIM_HI_HV_Msk 0x3E0UL
+#define FLASHC_FM_CTL_V2_CAL_CTL2_IPREF_TRIM_LO_HV_Pos 10UL
+#define FLASHC_FM_CTL_V2_CAL_CTL2_IPREF_TRIM_LO_HV_Msk 0x7C00UL
+#define FLASHC_FM_CTL_V2_CAL_CTL2_IPREF_TRIM_HI_HV_Pos 15UL
+#define FLASHC_FM_CTL_V2_CAL_CTL2_IPREF_TRIM_HI_HV_Msk 0xF8000UL
+/* FLASHC_FM_CTL.CAL_CTL3 */
+#define FLASHC_FM_CTL_V2_CAL_CTL3_OSC_TRIM_HV_Pos 0UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_OSC_TRIM_HV_Msk 0xFUL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_OSC_RANGE_TRIM_HV_Pos 4UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_OSC_RANGE_TRIM_HV_Msk 0x10UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_VPROT_ACT_HV_Pos 5UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_VPROT_ACT_HV_Msk 0x20UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_IPREF_TC_HV_Pos 6UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_IPREF_TC_HV_Msk 0x40UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_VREF_SEL_HV_Pos 7UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_VREF_SEL_HV_Msk 0x80UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_IREF_SEL_HV_Pos 8UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_IREF_SEL_HV_Msk 0x100UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_REG_ACT_HV_Pos 9UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_REG_ACT_HV_Msk 0x200UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_FDIV_TRIM_HV_Pos 10UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_FDIV_TRIM_HV_Msk 0xC00UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_VDDHI_HV_Pos 12UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_VDDHI_HV_Msk 0x1000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_TURBO_PULSEW_HV_Pos 13UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_TURBO_PULSEW_HV_Msk 0x6000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_BGLO_EN_HV_Pos 15UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_BGLO_EN_HV_Msk 0x8000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_BGHI_EN_HV_Pos 16UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_BGHI_EN_HV_Msk 0x10000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_CL_ISO_DIS_HV_Pos 17UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_CL_ISO_DIS_HV_Msk 0x20000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_R_GRANT_EN_HV_Pos 18UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_R_GRANT_EN_HV_Msk 0x40000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_LP_ULP_SW_HV_Pos 19UL
+#define FLASHC_FM_CTL_V2_CAL_CTL3_LP_ULP_SW_HV_Msk 0x80000UL
+/* FLASHC_FM_CTL.CAL_CTL4 */
+#define FLASHC_FM_CTL_V2_CAL_CTL4_VLIM_TRIM_ULP_HV_Pos 0UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_VLIM_TRIM_ULP_HV_Msk 0x3UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_IDAC_ULP_HV_Pos 2UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_IDAC_ULP_HV_Msk 0x3CUL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_SDAC_ULP_HV_Pos 6UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_SDAC_ULP_HV_Msk 0xC0UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_ITIM_ULP_HV_Pos 8UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_ITIM_ULP_HV_Msk 0x1F00UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_FM_READY_DEL_ULP_HV_Pos 13UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_FM_READY_DEL_ULP_HV_Msk 0x6000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_SPARE451_ULP_HV_Pos 15UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_SPARE451_ULP_HV_Msk 0x8000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_READY_RESTART_N_HV_Pos 16UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_READY_RESTART_N_HV_Msk 0x10000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_VBST_S_DIS_HV_Pos 17UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_VBST_S_DIS_HV_Msk 0x20000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_AUTO_HVPULSE_HV_Pos 18UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_AUTO_HVPULSE_HV_Msk 0x40000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_UGB_EN_HV_Pos 19UL
+#define FLASHC_FM_CTL_V2_CAL_CTL4_UGB_EN_HV_Msk 0x80000UL
+/* FLASHC_FM_CTL.CAL_CTL5 */
+#define FLASHC_FM_CTL_V2_CAL_CTL5_VLIM_TRIM_LP_HV_Pos 0UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_VLIM_TRIM_LP_HV_Msk 0x3UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_IDAC_LP_HV_Pos 2UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_IDAC_LP_HV_Msk 0x3CUL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_SDAC_LP_HV_Pos 6UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_SDAC_LP_HV_Msk 0xC0UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_ITIM_LP_HV_Pos 8UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_ITIM_LP_HV_Msk 0x1F00UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_FM_READY_DEL_LP_HV_Pos 13UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_FM_READY_DEL_LP_HV_Msk 0x6000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_SPARE451_LP_HV_Pos 15UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_SPARE451_LP_HV_Msk 0x8000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_SPARE52_HV_Pos 16UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_SPARE52_HV_Msk 0x30000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_AMUX_SEL_HV_Pos 18UL
+#define FLASHC_FM_CTL_V2_CAL_CTL5_AMUX_SEL_HV_Msk 0xC0000UL
+/* FLASHC_FM_CTL.CAL_CTL6 */
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T1_ULP_HV_Pos 0UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T1_ULP_HV_Msk 0x1UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T4_ULP_HV_Pos 1UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T4_ULP_HV_Msk 0xEUL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T5_ULP_HV_Pos 4UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T5_ULP_HV_Msk 0x70UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T6_ULP_HV_Pos 7UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T6_ULP_HV_Msk 0x180UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T8_ULP_HV_Pos 9UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T8_ULP_HV_Msk 0x200UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T1_LP_HV_Pos 10UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T1_LP_HV_Msk 0x400UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T4_LP_HV_Pos 11UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T4_LP_HV_Msk 0x3800UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T5_LP_HV_Pos 14UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T5_LP_HV_Msk 0x1C000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T6_LP_HV_Pos 17UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T6_LP_HV_Msk 0x60000UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T8_LP_HV_Pos 19UL
+#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T8_LP_HV_Msk 0x80000UL
+/* FLASHC_FM_CTL.CAL_CTL7 */
+#define FLASHC_FM_CTL_V2_CAL_CTL7_ERSX8_CLK_SEL_HV_Pos 0UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_ERSX8_CLK_SEL_HV_Msk 0x3UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_FM_ACTIVE_HV_Pos 2UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_FM_ACTIVE_HV_Msk 0x4UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_TURBO_EXT_HV_Pos 3UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_TURBO_EXT_HV_Msk 0x8UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_NPDAC_HWCTL_DIS_HV_Pos 4UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_NPDAC_HWCTL_DIS_HV_Msk 0x10UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_FM_READY_DIS_HV_Pos 5UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_FM_READY_DIS_HV_Msk 0x20UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_ERSX8_EN_ALL_HV_Pos 6UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_ERSX8_EN_ALL_HV_Msk 0x40UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_DISABLE_LOAD_ONCE_HV_Pos 7UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_DISABLE_LOAD_ONCE_HV_Msk 0x80UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_HV_Pos 8UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_HV_Msk 0x300UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_ULP_HV_Pos 10UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_ULP_HV_Msk 0x7C00UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_LP_HV_Pos 15UL
+#define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_LP_HV_Msk 0xF8000UL
+/* FLASHC_FM_CTL.RED_CTL01 */
+#define FLASHC_FM_CTL_V2_RED_CTL01_RED_ADDR_0_Pos 0UL
+#define FLASHC_FM_CTL_V2_RED_CTL01_RED_ADDR_0_Msk 0xFFUL
+#define FLASHC_FM_CTL_V2_RED_CTL01_RED_EN_0_Pos 8UL
+#define FLASHC_FM_CTL_V2_RED_CTL01_RED_EN_0_Msk 0x100UL
+#define FLASHC_FM_CTL_V2_RED_CTL01_RED_ADDR_1_Pos 16UL
+#define FLASHC_FM_CTL_V2_RED_CTL01_RED_ADDR_1_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_V2_RED_CTL01_RED_EN_1_Pos 24UL
+#define FLASHC_FM_CTL_V2_RED_CTL01_RED_EN_1_Msk 0x1000000UL
+/* FLASHC_FM_CTL.RED_CTL23 */
+#define FLASHC_FM_CTL_V2_RED_CTL23_RED_ADDR_2_Pos 0UL
+#define FLASHC_FM_CTL_V2_RED_CTL23_RED_ADDR_2_Msk 0xFFUL
+#define FLASHC_FM_CTL_V2_RED_CTL23_RED_EN_2_Pos 8UL
+#define FLASHC_FM_CTL_V2_RED_CTL23_RED_EN_2_Msk 0x100UL
+#define FLASHC_FM_CTL_V2_RED_CTL23_RED_ADDR_3_Pos 16UL
+#define FLASHC_FM_CTL_V2_RED_CTL23_RED_ADDR_3_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_V2_RED_CTL23_RED_EN_3_Pos 24UL
+#define FLASHC_FM_CTL_V2_RED_CTL23_RED_EN_3_Msk 0x1000000UL
+/* FLASHC_FM_CTL.RED_CTL45 */
+#define FLASHC_FM_CTL_V2_RED_CTL45_RED_ADDR_4_Pos 0UL
+#define FLASHC_FM_CTL_V2_RED_CTL45_RED_ADDR_4_Msk 0xFFUL
+#define FLASHC_FM_CTL_V2_RED_CTL45_RED_EN_4_Pos 8UL
+#define FLASHC_FM_CTL_V2_RED_CTL45_RED_EN_4_Msk 0x100UL
+#define FLASHC_FM_CTL_V2_RED_CTL45_RED_ADDR_5_Pos 16UL
+#define FLASHC_FM_CTL_V2_RED_CTL45_RED_ADDR_5_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_V2_RED_CTL45_RED_EN_5_Pos 24UL
+#define FLASHC_FM_CTL_V2_RED_CTL45_RED_EN_5_Msk 0x1000000UL
+/* FLASHC_FM_CTL.RED_CTL67 */
+#define FLASHC_FM_CTL_V2_RED_CTL67_RED_ADDR_6_Pos 0UL
+#define FLASHC_FM_CTL_V2_RED_CTL67_RED_ADDR_6_Msk 0xFFUL
+#define FLASHC_FM_CTL_V2_RED_CTL67_RED_EN_6_Pos 8UL
+#define FLASHC_FM_CTL_V2_RED_CTL67_RED_EN_6_Msk 0x100UL
+#define FLASHC_FM_CTL_V2_RED_CTL67_RED_ADDR_7_Pos 16UL
+#define FLASHC_FM_CTL_V2_RED_CTL67_RED_ADDR_7_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_V2_RED_CTL67_RED_EN_7_Pos 24UL
+#define FLASHC_FM_CTL_V2_RED_CTL67_RED_EN_7_Msk 0x1000000UL
+/* FLASHC_FM_CTL.RED_CTL_SM01 */
+#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_ADDR_SM0_Pos 0UL
+#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_ADDR_SM0_Msk 0xFFUL
+#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_EN_SM0_Pos 8UL
+#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_EN_SM0_Msk 0x100UL
+#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_ADDR_SM1_Pos 16UL
+#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_ADDR_SM1_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_EN_SM1_Pos 24UL
+#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_EN_SM1_Msk 0x1000000UL
+/* FLASHC_FM_CTL.RGRANT_DELAY_PRG */
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_PRG_SEQ12_Pos 0UL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_PRG_SEQ12_Msk 0xFFUL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_PRG_SEQ23_Pos 8UL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_PRG_SEQ23_Msk 0xFF00UL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_SEQ30_Pos 16UL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_SEQ30_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_CLK_Pos 24UL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_CLK_Msk 0xF000000UL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_HV_PARAMS_LOADED_Pos 31UL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_HV_PARAMS_LOADED_Msk 0x80000000UL
+/* FLASHC_FM_CTL.PW_SEQ12 */
+#define FLASHC_FM_CTL_V2_PW_SEQ12_PW_SEQ1_Pos 0UL
+#define FLASHC_FM_CTL_V2_PW_SEQ12_PW_SEQ1_Msk 0xFFFFUL
+#define FLASHC_FM_CTL_V2_PW_SEQ12_PW_SEQ2_PRE_Pos 16UL
+#define FLASHC_FM_CTL_V2_PW_SEQ12_PW_SEQ2_PRE_Msk 0xFFFF0000UL
+/* FLASHC_FM_CTL.PW_SEQ23 */
+#define FLASHC_FM_CTL_V2_PW_SEQ23_PW_SEQ2_POST_Pos 0UL
+#define FLASHC_FM_CTL_V2_PW_SEQ23_PW_SEQ2_POST_Msk 0xFFFFUL
+#define FLASHC_FM_CTL_V2_PW_SEQ23_PW_SEQ3_Pos 16UL
+#define FLASHC_FM_CTL_V2_PW_SEQ23_PW_SEQ3_Msk 0xFFFF0000UL
+/* FLASHC_FM_CTL.RGRANT_SCALE_ERS */
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_SEQ01_Pos 0UL
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_SEQ01_Msk 0x3UL
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_SEQ12_Pos 2UL
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_SEQ12_Msk 0xCUL
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_SEQ23_Pos 4UL
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_SEQ23_Msk 0x30UL
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_PEON_Pos 6UL
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_PEON_Msk 0xC0UL
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_PEOFF_Pos 8UL
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_PEOFF_Msk 0x300UL
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_RGRANT_DELAY_ERS_PEON_Pos 16UL
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_RGRANT_DELAY_ERS_PEON_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_RGRANT_DELAY_ERS_PEOFF_Pos 24UL
+#define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_RGRANT_DELAY_ERS_PEOFF_Msk 0xFF000000UL
+/* FLASHC_FM_CTL.RGRANT_DELAY_ERS */
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ01_Pos 0UL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ01_Msk 0xFFUL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ12_Pos 8UL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ12_Msk 0xFF00UL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ23_Pos 16UL
+#define FLASHC_FM_CTL_V2_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ23_Msk 0xFF0000UL
+/* FLASHC_FM_CTL.FM_PL_WRDATA_ALL */
+#define FLASHC_FM_CTL_V2_FM_PL_WRDATA_ALL_DATA32_Pos 0UL
+#define FLASHC_FM_CTL_V2_FM_PL_WRDATA_ALL_DATA32_Msk 0xFFFFFFFFUL
+/* FLASHC_FM_CTL.FM_PL_DATA */
+#define FLASHC_FM_CTL_V2_FM_PL_DATA_DATA32_Pos 0UL
+#define FLASHC_FM_CTL_V2_FM_PL_DATA_DATA32_Msk 0xFFFFFFFFUL
+/* FLASHC_FM_CTL.FM_MEM_DATA */
+#define FLASHC_FM_CTL_V2_FM_MEM_DATA_DATA32_Pos 0UL
+#define FLASHC_FM_CTL_V2_FM_MEM_DATA_DATA32_Msk 0xFFFFFFFFUL
+
+
+/* FLASHC.FLASH_CTL */
+#define FLASHC_V2_FLASH_CTL_MAIN_WS_Pos 0UL
+#define FLASHC_V2_FLASH_CTL_MAIN_WS_Msk 0xFUL
+#define FLASHC_V2_FLASH_CTL_MAIN_MAP_Pos 8UL
+#define FLASHC_V2_FLASH_CTL_MAIN_MAP_Msk 0x100UL
+#define FLASHC_V2_FLASH_CTL_WORK_MAP_Pos 9UL
+#define FLASHC_V2_FLASH_CTL_WORK_MAP_Msk 0x200UL
+#define FLASHC_V2_FLASH_CTL_MAIN_BANK_MODE_Pos 12UL
+#define FLASHC_V2_FLASH_CTL_MAIN_BANK_MODE_Msk 0x1000UL
+#define FLASHC_V2_FLASH_CTL_WORK_BANK_MODE_Pos 13UL
+#define FLASHC_V2_FLASH_CTL_WORK_BANK_MODE_Msk 0x2000UL
+#define FLASHC_V2_FLASH_CTL_MAIN_ECC_EN_Pos 16UL
+#define FLASHC_V2_FLASH_CTL_MAIN_ECC_EN_Msk 0x10000UL
+#define FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN_Pos 17UL
+#define FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN_Msk 0x20000UL
+#define FLASHC_V2_FLASH_CTL_MAIN_ERR_SILENT_Pos 18UL
+#define FLASHC_V2_FLASH_CTL_MAIN_ERR_SILENT_Msk 0x40000UL
+#define FLASHC_V2_FLASH_CTL_WORK_ECC_EN_Pos 20UL
+#define FLASHC_V2_FLASH_CTL_WORK_ECC_EN_Msk 0x100000UL
+#define FLASHC_V2_FLASH_CTL_WORK_ECC_INJ_EN_Pos 21UL
+#define FLASHC_V2_FLASH_CTL_WORK_ECC_INJ_EN_Msk 0x200000UL
+#define FLASHC_V2_FLASH_CTL_WORK_ERR_SILENT_Pos 22UL
+#define FLASHC_V2_FLASH_CTL_WORK_ERR_SILENT_Msk 0x400000UL
+/* FLASHC.FLASH_PWR_CTL */
+#define FLASHC_V2_FLASH_PWR_CTL_ENABLE_Pos 0UL
+#define FLASHC_V2_FLASH_PWR_CTL_ENABLE_Msk 0x1UL
+#define FLASHC_V2_FLASH_PWR_CTL_ENABLE_HV_Pos 1UL
+#define FLASHC_V2_FLASH_PWR_CTL_ENABLE_HV_Msk 0x2UL
+/* FLASHC.FLASH_CMD */
+#define FLASHC_V2_FLASH_CMD_INV_Pos 0UL
+#define FLASHC_V2_FLASH_CMD_INV_Msk 0x1UL
+#define FLASHC_V2_FLASH_CMD_BUFF_INV_Pos 1UL
+#define FLASHC_V2_FLASH_CMD_BUFF_INV_Msk 0x2UL
+/* FLASHC.ECC_CTL */
+#define FLASHC_V2_ECC_CTL_WORD_ADDR_Pos 0UL
+#define FLASHC_V2_ECC_CTL_WORD_ADDR_Msk 0xFFFFFFUL
+#define FLASHC_V2_ECC_CTL_PARITY_Pos 24UL
+#define FLASHC_V2_ECC_CTL_PARITY_Msk 0xFF000000UL
+/* FLASHC.FM_SRAM_ECC_CTL0 */
+#define FLASHC_V2_FM_SRAM_ECC_CTL0_ECC_INJ_DATA_Pos 0UL
+#define FLASHC_V2_FM_SRAM_ECC_CTL0_ECC_INJ_DATA_Msk 0xFFFFFFFFUL
+/* FLASHC.FM_SRAM_ECC_CTL1 */
+#define FLASHC_V2_FM_SRAM_ECC_CTL1_ECC_INJ_PARITY_Pos 0UL
+#define FLASHC_V2_FM_SRAM_ECC_CTL1_ECC_INJ_PARITY_Msk 0x7FUL
+/* FLASHC.FM_SRAM_ECC_CTL2 */
+#define FLASHC_V2_FM_SRAM_ECC_CTL2_CORRECTED_DATA_Pos 0UL
+#define FLASHC_V2_FM_SRAM_ECC_CTL2_CORRECTED_DATA_Msk 0xFFFFFFFFUL
+/* FLASHC.FM_SRAM_ECC_CTL3 */
+#define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_ENABLE_Pos 0UL
+#define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_ENABLE_Msk 0x1UL
+#define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_INJ_EN_Pos 4UL
+#define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_INJ_EN_Msk 0x10UL
+#define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_TEST_FAIL_Pos 8UL
+#define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_TEST_FAIL_Msk 0x100UL
+/* FLASHC.CM0_CA_CTL0 */
+#define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_EN_Pos 0UL
+#define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_EN_Msk 0x1UL
+#define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_INJ_EN_Pos 1UL
+#define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_INJ_EN_Msk 0x2UL
+#define FLASHC_V2_CM0_CA_CTL0_WAY_Pos 16UL
+#define FLASHC_V2_CM0_CA_CTL0_WAY_Msk 0x30000UL
+#define FLASHC_V2_CM0_CA_CTL0_SET_ADDR_Pos 24UL
+#define FLASHC_V2_CM0_CA_CTL0_SET_ADDR_Msk 0x7000000UL
+#define FLASHC_V2_CM0_CA_CTL0_PREF_EN_Pos 30UL
+#define FLASHC_V2_CM0_CA_CTL0_PREF_EN_Msk 0x40000000UL
+#define FLASHC_V2_CM0_CA_CTL0_CA_EN_Pos 31UL
+#define FLASHC_V2_CM0_CA_CTL0_CA_EN_Msk 0x80000000UL
+/* FLASHC.CM0_CA_CTL1 */
+#define FLASHC_V2_CM0_CA_CTL1_PWR_MODE_Pos 0UL
+#define FLASHC_V2_CM0_CA_CTL1_PWR_MODE_Msk 0x3UL
+#define FLASHC_V2_CM0_CA_CTL1_VECTKEYSTAT_Pos 16UL
+#define FLASHC_V2_CM0_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* FLASHC.CM0_CA_CTL2 */
+#define FLASHC_V2_CM0_CA_CTL2_PWRUP_DELAY_Pos 0UL
+#define FLASHC_V2_CM0_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL
+/* FLASHC.CM0_CA_STATUS0 */
+#define FLASHC_V2_CM0_CA_STATUS0_VALID32_Pos 0UL
+#define FLASHC_V2_CM0_CA_STATUS0_VALID32_Msk 0xFFFFFFFFUL
+/* FLASHC.CM0_CA_STATUS1 */
+#define FLASHC_V2_CM0_CA_STATUS1_TAG_Pos 0UL
+#define FLASHC_V2_CM0_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL
+/* FLASHC.CM0_CA_STATUS2 */
+#define FLASHC_V2_CM0_CA_STATUS2_LRU_Pos 0UL
+#define FLASHC_V2_CM0_CA_STATUS2_LRU_Msk 0x3FUL
+/* FLASHC.CM0_STATUS */
+#define FLASHC_V2_CM0_STATUS_MAIN_INTERNAL_ERR_Pos 0UL
+#define FLASHC_V2_CM0_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL
+#define FLASHC_V2_CM0_STATUS_WORK_INTERNAL_ERR_Pos 1UL
+#define FLASHC_V2_CM0_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL
+/* FLASHC.CM4_CA_CTL0 */
+#define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_EN_Pos 0UL
+#define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_EN_Msk 0x1UL
+#define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_INJ_EN_Pos 1UL
+#define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_INJ_EN_Msk 0x2UL
+#define FLASHC_V2_CM4_CA_CTL0_WAY_Pos 16UL
+#define FLASHC_V2_CM4_CA_CTL0_WAY_Msk 0x30000UL
+#define FLASHC_V2_CM4_CA_CTL0_SET_ADDR_Pos 24UL
+#define FLASHC_V2_CM4_CA_CTL0_SET_ADDR_Msk 0x7000000UL
+#define FLASHC_V2_CM4_CA_CTL0_PREF_EN_Pos 30UL
+#define FLASHC_V2_CM4_CA_CTL0_PREF_EN_Msk 0x40000000UL
+#define FLASHC_V2_CM4_CA_CTL0_CA_EN_Pos 31UL
+#define FLASHC_V2_CM4_CA_CTL0_CA_EN_Msk 0x80000000UL
+/* FLASHC.CM4_CA_CTL1 */
+#define FLASHC_V2_CM4_CA_CTL1_PWR_MODE_Pos 0UL
+#define FLASHC_V2_CM4_CA_CTL1_PWR_MODE_Msk 0x3UL
+#define FLASHC_V2_CM4_CA_CTL1_VECTKEYSTAT_Pos 16UL
+#define FLASHC_V2_CM4_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* FLASHC.CM4_CA_CTL2 */
+#define FLASHC_V2_CM4_CA_CTL2_PWRUP_DELAY_Pos 0UL
+#define FLASHC_V2_CM4_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL
+/* FLASHC.CM4_CA_STATUS0 */
+#define FLASHC_V2_CM4_CA_STATUS0_VALID32_Pos 0UL
+#define FLASHC_V2_CM4_CA_STATUS0_VALID32_Msk 0xFFFFFFFFUL
+/* FLASHC.CM4_CA_STATUS1 */
+#define FLASHC_V2_CM4_CA_STATUS1_TAG_Pos 0UL
+#define FLASHC_V2_CM4_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL
+/* FLASHC.CM4_CA_STATUS2 */
+#define FLASHC_V2_CM4_CA_STATUS2_LRU_Pos 0UL
+#define FLASHC_V2_CM4_CA_STATUS2_LRU_Msk 0x3FUL
+/* FLASHC.CM4_STATUS */
+#define FLASHC_V2_CM4_STATUS_MAIN_INTERNAL_ERR_Pos 0UL
+#define FLASHC_V2_CM4_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL
+#define FLASHC_V2_CM4_STATUS_WORK_INTERNAL_ERR_Pos 1UL
+#define FLASHC_V2_CM4_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL
+/* FLASHC.CRYPTO_BUFF_CTL */
+#define FLASHC_V2_CRYPTO_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_V2_CRYPTO_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+/* FLASHC.DW0_BUFF_CTL */
+#define FLASHC_V2_DW0_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_V2_DW0_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+/* FLASHC.DW1_BUFF_CTL */
+#define FLASHC_V2_DW1_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_V2_DW1_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+/* FLASHC.DMAC_BUFF_CTL */
+#define FLASHC_V2_DMAC_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_V2_DMAC_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+/* FLASHC.EXT_MS0_BUFF_CTL */
+#define FLASHC_V2_EXT_MS0_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_V2_EXT_MS0_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+/* FLASHC.EXT_MS1_BUFF_CTL */
+#define FLASHC_V2_EXT_MS1_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_V2_EXT_MS1_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+
+
+#endif /* _CYIP_FLASHC_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_gpio.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_gpio.h
new file mode 100644
index 0000000000..cca8ff92a6
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_gpio.h
@@ -0,0 +1,477 @@
+/***************************************************************************//**
+* \file cyip_gpio.h
+*
+* \brief
+* GPIO IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_GPIO_H_
+#define _CYIP_GPIO_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* GPIO
+*******************************************************************************/
+
+#define GPIO_PRT_SECTION_SIZE 0x00000080UL
+#define GPIO_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief GPIO port registers (GPIO_PRT)
+ */
+typedef struct {
+ __IOM uint32_t OUT; /*!< 0x00000000 Port output data register */
+ __IOM uint32_t OUT_CLR; /*!< 0x00000004 Port output data clear register */
+ __IOM uint32_t OUT_SET; /*!< 0x00000008 Port output data set register */
+ __IOM uint32_t OUT_INV; /*!< 0x0000000C Port output data invert register */
+ __IM uint32_t IN; /*!< 0x00000010 Port input state register */
+ __IOM uint32_t INTR; /*!< 0x00000014 Port interrupt status register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000018 Port interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000001C Port interrupt masked status register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000020 Port interrupt set register */
+ __IOM uint32_t INTR_CFG; /*!< 0x00000024 Port interrupt configuration register */
+ __IOM uint32_t CFG; /*!< 0x00000028 Port configuration register */
+ __IOM uint32_t CFG_IN; /*!< 0x0000002C Port input buffer configuration register */
+ __IOM uint32_t CFG_OUT; /*!< 0x00000030 Port output buffer configuration register */
+ __IOM uint32_t CFG_SIO; /*!< 0x00000034 Port SIO configuration register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t CFG_IN_GPIO5V; /*!< 0x0000003C Port GPIO5V input buffer configuration register */
+ __IM uint32_t RESERVED1[16];
+} GPIO_PRT_V1_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * \brief GPIO port control/configuration (GPIO)
+ */
+typedef struct {
+ GPIO_PRT_V1_Type PRT[128]; /*!< 0x00000000 GPIO port registers */
+ __IM uint32_t INTR_CAUSE0; /*!< 0x00004000 Interrupt port cause register 0 */
+ __IM uint32_t INTR_CAUSE1; /*!< 0x00004004 Interrupt port cause register 1 */
+ __IM uint32_t INTR_CAUSE2; /*!< 0x00004008 Interrupt port cause register 2 */
+ __IM uint32_t INTR_CAUSE3; /*!< 0x0000400C Interrupt port cause register 3 */
+ __IM uint32_t VDD_ACTIVE; /*!< 0x00004010 Extern power supply detection register */
+ __IOM uint32_t VDD_INTR; /*!< 0x00004014 Supply detection interrupt register */
+ __IOM uint32_t VDD_INTR_MASK; /*!< 0x00004018 Supply detection interrupt mask register */
+ __IM uint32_t VDD_INTR_MASKED; /*!< 0x0000401C Supply detection interrupt masked register */
+ __IOM uint32_t VDD_INTR_SET; /*!< 0x00004020 Supply detection interrupt set register */
+} GPIO_V1_Type; /*!< Size = 16420 (0x4024) */
+
+
+/* GPIO_PRT.OUT */
+#define GPIO_PRT_OUT_OUT0_Pos 0UL
+#define GPIO_PRT_OUT_OUT0_Msk 0x1UL
+#define GPIO_PRT_OUT_OUT1_Pos 1UL
+#define GPIO_PRT_OUT_OUT1_Msk 0x2UL
+#define GPIO_PRT_OUT_OUT2_Pos 2UL
+#define GPIO_PRT_OUT_OUT2_Msk 0x4UL
+#define GPIO_PRT_OUT_OUT3_Pos 3UL
+#define GPIO_PRT_OUT_OUT3_Msk 0x8UL
+#define GPIO_PRT_OUT_OUT4_Pos 4UL
+#define GPIO_PRT_OUT_OUT4_Msk 0x10UL
+#define GPIO_PRT_OUT_OUT5_Pos 5UL
+#define GPIO_PRT_OUT_OUT5_Msk 0x20UL
+#define GPIO_PRT_OUT_OUT6_Pos 6UL
+#define GPIO_PRT_OUT_OUT6_Msk 0x40UL
+#define GPIO_PRT_OUT_OUT7_Pos 7UL
+#define GPIO_PRT_OUT_OUT7_Msk 0x80UL
+/* GPIO_PRT.OUT_CLR */
+#define GPIO_PRT_OUT_CLR_OUT0_Pos 0UL
+#define GPIO_PRT_OUT_CLR_OUT0_Msk 0x1UL
+#define GPIO_PRT_OUT_CLR_OUT1_Pos 1UL
+#define GPIO_PRT_OUT_CLR_OUT1_Msk 0x2UL
+#define GPIO_PRT_OUT_CLR_OUT2_Pos 2UL
+#define GPIO_PRT_OUT_CLR_OUT2_Msk 0x4UL
+#define GPIO_PRT_OUT_CLR_OUT3_Pos 3UL
+#define GPIO_PRT_OUT_CLR_OUT3_Msk 0x8UL
+#define GPIO_PRT_OUT_CLR_OUT4_Pos 4UL
+#define GPIO_PRT_OUT_CLR_OUT4_Msk 0x10UL
+#define GPIO_PRT_OUT_CLR_OUT5_Pos 5UL
+#define GPIO_PRT_OUT_CLR_OUT5_Msk 0x20UL
+#define GPIO_PRT_OUT_CLR_OUT6_Pos 6UL
+#define GPIO_PRT_OUT_CLR_OUT6_Msk 0x40UL
+#define GPIO_PRT_OUT_CLR_OUT7_Pos 7UL
+#define GPIO_PRT_OUT_CLR_OUT7_Msk 0x80UL
+/* GPIO_PRT.OUT_SET */
+#define GPIO_PRT_OUT_SET_OUT0_Pos 0UL
+#define GPIO_PRT_OUT_SET_OUT0_Msk 0x1UL
+#define GPIO_PRT_OUT_SET_OUT1_Pos 1UL
+#define GPIO_PRT_OUT_SET_OUT1_Msk 0x2UL
+#define GPIO_PRT_OUT_SET_OUT2_Pos 2UL
+#define GPIO_PRT_OUT_SET_OUT2_Msk 0x4UL
+#define GPIO_PRT_OUT_SET_OUT3_Pos 3UL
+#define GPIO_PRT_OUT_SET_OUT3_Msk 0x8UL
+#define GPIO_PRT_OUT_SET_OUT4_Pos 4UL
+#define GPIO_PRT_OUT_SET_OUT4_Msk 0x10UL
+#define GPIO_PRT_OUT_SET_OUT5_Pos 5UL
+#define GPIO_PRT_OUT_SET_OUT5_Msk 0x20UL
+#define GPIO_PRT_OUT_SET_OUT6_Pos 6UL
+#define GPIO_PRT_OUT_SET_OUT6_Msk 0x40UL
+#define GPIO_PRT_OUT_SET_OUT7_Pos 7UL
+#define GPIO_PRT_OUT_SET_OUT7_Msk 0x80UL
+/* GPIO_PRT.OUT_INV */
+#define GPIO_PRT_OUT_INV_OUT0_Pos 0UL
+#define GPIO_PRT_OUT_INV_OUT0_Msk 0x1UL
+#define GPIO_PRT_OUT_INV_OUT1_Pos 1UL
+#define GPIO_PRT_OUT_INV_OUT1_Msk 0x2UL
+#define GPIO_PRT_OUT_INV_OUT2_Pos 2UL
+#define GPIO_PRT_OUT_INV_OUT2_Msk 0x4UL
+#define GPIO_PRT_OUT_INV_OUT3_Pos 3UL
+#define GPIO_PRT_OUT_INV_OUT3_Msk 0x8UL
+#define GPIO_PRT_OUT_INV_OUT4_Pos 4UL
+#define GPIO_PRT_OUT_INV_OUT4_Msk 0x10UL
+#define GPIO_PRT_OUT_INV_OUT5_Pos 5UL
+#define GPIO_PRT_OUT_INV_OUT5_Msk 0x20UL
+#define GPIO_PRT_OUT_INV_OUT6_Pos 6UL
+#define GPIO_PRT_OUT_INV_OUT6_Msk 0x40UL
+#define GPIO_PRT_OUT_INV_OUT7_Pos 7UL
+#define GPIO_PRT_OUT_INV_OUT7_Msk 0x80UL
+/* GPIO_PRT.IN */
+#define GPIO_PRT_IN_IN0_Pos 0UL
+#define GPIO_PRT_IN_IN0_Msk 0x1UL
+#define GPIO_PRT_IN_IN1_Pos 1UL
+#define GPIO_PRT_IN_IN1_Msk 0x2UL
+#define GPIO_PRT_IN_IN2_Pos 2UL
+#define GPIO_PRT_IN_IN2_Msk 0x4UL
+#define GPIO_PRT_IN_IN3_Pos 3UL
+#define GPIO_PRT_IN_IN3_Msk 0x8UL
+#define GPIO_PRT_IN_IN4_Pos 4UL
+#define GPIO_PRT_IN_IN4_Msk 0x10UL
+#define GPIO_PRT_IN_IN5_Pos 5UL
+#define GPIO_PRT_IN_IN5_Msk 0x20UL
+#define GPIO_PRT_IN_IN6_Pos 6UL
+#define GPIO_PRT_IN_IN6_Msk 0x40UL
+#define GPIO_PRT_IN_IN7_Pos 7UL
+#define GPIO_PRT_IN_IN7_Msk 0x80UL
+#define GPIO_PRT_IN_FLT_IN_Pos 8UL
+#define GPIO_PRT_IN_FLT_IN_Msk 0x100UL
+/* GPIO_PRT.INTR */
+#define GPIO_PRT_INTR_EDGE0_Pos 0UL
+#define GPIO_PRT_INTR_EDGE0_Msk 0x1UL
+#define GPIO_PRT_INTR_EDGE1_Pos 1UL
+#define GPIO_PRT_INTR_EDGE1_Msk 0x2UL
+#define GPIO_PRT_INTR_EDGE2_Pos 2UL
+#define GPIO_PRT_INTR_EDGE2_Msk 0x4UL
+#define GPIO_PRT_INTR_EDGE3_Pos 3UL
+#define GPIO_PRT_INTR_EDGE3_Msk 0x8UL
+#define GPIO_PRT_INTR_EDGE4_Pos 4UL
+#define GPIO_PRT_INTR_EDGE4_Msk 0x10UL
+#define GPIO_PRT_INTR_EDGE5_Pos 5UL
+#define GPIO_PRT_INTR_EDGE5_Msk 0x20UL
+#define GPIO_PRT_INTR_EDGE6_Pos 6UL
+#define GPIO_PRT_INTR_EDGE6_Msk 0x40UL
+#define GPIO_PRT_INTR_EDGE7_Pos 7UL
+#define GPIO_PRT_INTR_EDGE7_Msk 0x80UL
+#define GPIO_PRT_INTR_FLT_EDGE_Pos 8UL
+#define GPIO_PRT_INTR_FLT_EDGE_Msk 0x100UL
+#define GPIO_PRT_INTR_IN_IN0_Pos 16UL
+#define GPIO_PRT_INTR_IN_IN0_Msk 0x10000UL
+#define GPIO_PRT_INTR_IN_IN1_Pos 17UL
+#define GPIO_PRT_INTR_IN_IN1_Msk 0x20000UL
+#define GPIO_PRT_INTR_IN_IN2_Pos 18UL
+#define GPIO_PRT_INTR_IN_IN2_Msk 0x40000UL
+#define GPIO_PRT_INTR_IN_IN3_Pos 19UL
+#define GPIO_PRT_INTR_IN_IN3_Msk 0x80000UL
+#define GPIO_PRT_INTR_IN_IN4_Pos 20UL
+#define GPIO_PRT_INTR_IN_IN4_Msk 0x100000UL
+#define GPIO_PRT_INTR_IN_IN5_Pos 21UL
+#define GPIO_PRT_INTR_IN_IN5_Msk 0x200000UL
+#define GPIO_PRT_INTR_IN_IN6_Pos 22UL
+#define GPIO_PRT_INTR_IN_IN6_Msk 0x400000UL
+#define GPIO_PRT_INTR_IN_IN7_Pos 23UL
+#define GPIO_PRT_INTR_IN_IN7_Msk 0x800000UL
+#define GPIO_PRT_INTR_FLT_IN_IN_Pos 24UL
+#define GPIO_PRT_INTR_FLT_IN_IN_Msk 0x1000000UL
+/* GPIO_PRT.INTR_MASK */
+#define GPIO_PRT_INTR_MASK_EDGE0_Pos 0UL
+#define GPIO_PRT_INTR_MASK_EDGE0_Msk 0x1UL
+#define GPIO_PRT_INTR_MASK_EDGE1_Pos 1UL
+#define GPIO_PRT_INTR_MASK_EDGE1_Msk 0x2UL
+#define GPIO_PRT_INTR_MASK_EDGE2_Pos 2UL
+#define GPIO_PRT_INTR_MASK_EDGE2_Msk 0x4UL
+#define GPIO_PRT_INTR_MASK_EDGE3_Pos 3UL
+#define GPIO_PRT_INTR_MASK_EDGE3_Msk 0x8UL
+#define GPIO_PRT_INTR_MASK_EDGE4_Pos 4UL
+#define GPIO_PRT_INTR_MASK_EDGE4_Msk 0x10UL
+#define GPIO_PRT_INTR_MASK_EDGE5_Pos 5UL
+#define GPIO_PRT_INTR_MASK_EDGE5_Msk 0x20UL
+#define GPIO_PRT_INTR_MASK_EDGE6_Pos 6UL
+#define GPIO_PRT_INTR_MASK_EDGE6_Msk 0x40UL
+#define GPIO_PRT_INTR_MASK_EDGE7_Pos 7UL
+#define GPIO_PRT_INTR_MASK_EDGE7_Msk 0x80UL
+#define GPIO_PRT_INTR_MASK_FLT_EDGE_Pos 8UL
+#define GPIO_PRT_INTR_MASK_FLT_EDGE_Msk 0x100UL
+/* GPIO_PRT.INTR_MASKED */
+#define GPIO_PRT_INTR_MASKED_EDGE0_Pos 0UL
+#define GPIO_PRT_INTR_MASKED_EDGE0_Msk 0x1UL
+#define GPIO_PRT_INTR_MASKED_EDGE1_Pos 1UL
+#define GPIO_PRT_INTR_MASKED_EDGE1_Msk 0x2UL
+#define GPIO_PRT_INTR_MASKED_EDGE2_Pos 2UL
+#define GPIO_PRT_INTR_MASKED_EDGE2_Msk 0x4UL
+#define GPIO_PRT_INTR_MASKED_EDGE3_Pos 3UL
+#define GPIO_PRT_INTR_MASKED_EDGE3_Msk 0x8UL
+#define GPIO_PRT_INTR_MASKED_EDGE4_Pos 4UL
+#define GPIO_PRT_INTR_MASKED_EDGE4_Msk 0x10UL
+#define GPIO_PRT_INTR_MASKED_EDGE5_Pos 5UL
+#define GPIO_PRT_INTR_MASKED_EDGE5_Msk 0x20UL
+#define GPIO_PRT_INTR_MASKED_EDGE6_Pos 6UL
+#define GPIO_PRT_INTR_MASKED_EDGE6_Msk 0x40UL
+#define GPIO_PRT_INTR_MASKED_EDGE7_Pos 7UL
+#define GPIO_PRT_INTR_MASKED_EDGE7_Msk 0x80UL
+#define GPIO_PRT_INTR_MASKED_FLT_EDGE_Pos 8UL
+#define GPIO_PRT_INTR_MASKED_FLT_EDGE_Msk 0x100UL
+/* GPIO_PRT.INTR_SET */
+#define GPIO_PRT_INTR_SET_EDGE0_Pos 0UL
+#define GPIO_PRT_INTR_SET_EDGE0_Msk 0x1UL
+#define GPIO_PRT_INTR_SET_EDGE1_Pos 1UL
+#define GPIO_PRT_INTR_SET_EDGE1_Msk 0x2UL
+#define GPIO_PRT_INTR_SET_EDGE2_Pos 2UL
+#define GPIO_PRT_INTR_SET_EDGE2_Msk 0x4UL
+#define GPIO_PRT_INTR_SET_EDGE3_Pos 3UL
+#define GPIO_PRT_INTR_SET_EDGE3_Msk 0x8UL
+#define GPIO_PRT_INTR_SET_EDGE4_Pos 4UL
+#define GPIO_PRT_INTR_SET_EDGE4_Msk 0x10UL
+#define GPIO_PRT_INTR_SET_EDGE5_Pos 5UL
+#define GPIO_PRT_INTR_SET_EDGE5_Msk 0x20UL
+#define GPIO_PRT_INTR_SET_EDGE6_Pos 6UL
+#define GPIO_PRT_INTR_SET_EDGE6_Msk 0x40UL
+#define GPIO_PRT_INTR_SET_EDGE7_Pos 7UL
+#define GPIO_PRT_INTR_SET_EDGE7_Msk 0x80UL
+#define GPIO_PRT_INTR_SET_FLT_EDGE_Pos 8UL
+#define GPIO_PRT_INTR_SET_FLT_EDGE_Msk 0x100UL
+/* GPIO_PRT.INTR_CFG */
+#define GPIO_PRT_INTR_CFG_EDGE0_SEL_Pos 0UL
+#define GPIO_PRT_INTR_CFG_EDGE0_SEL_Msk 0x3UL
+#define GPIO_PRT_INTR_CFG_EDGE1_SEL_Pos 2UL
+#define GPIO_PRT_INTR_CFG_EDGE1_SEL_Msk 0xCUL
+#define GPIO_PRT_INTR_CFG_EDGE2_SEL_Pos 4UL
+#define GPIO_PRT_INTR_CFG_EDGE2_SEL_Msk 0x30UL
+#define GPIO_PRT_INTR_CFG_EDGE3_SEL_Pos 6UL
+#define GPIO_PRT_INTR_CFG_EDGE3_SEL_Msk 0xC0UL
+#define GPIO_PRT_INTR_CFG_EDGE4_SEL_Pos 8UL
+#define GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk 0x300UL
+#define GPIO_PRT_INTR_CFG_EDGE5_SEL_Pos 10UL
+#define GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk 0xC00UL
+#define GPIO_PRT_INTR_CFG_EDGE6_SEL_Pos 12UL
+#define GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk 0x3000UL
+#define GPIO_PRT_INTR_CFG_EDGE7_SEL_Pos 14UL
+#define GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk 0xC000UL
+#define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Pos 16UL
+#define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk 0x30000UL
+#define GPIO_PRT_INTR_CFG_FLT_SEL_Pos 18UL
+#define GPIO_PRT_INTR_CFG_FLT_SEL_Msk 0x1C0000UL
+/* GPIO_PRT.CFG */
+#define GPIO_PRT_CFG_DRIVE_MODE0_Pos 0UL
+#define GPIO_PRT_CFG_DRIVE_MODE0_Msk 0x7UL
+#define GPIO_PRT_CFG_IN_EN0_Pos 3UL
+#define GPIO_PRT_CFG_IN_EN0_Msk 0x8UL
+#define GPIO_PRT_CFG_DRIVE_MODE1_Pos 4UL
+#define GPIO_PRT_CFG_DRIVE_MODE1_Msk 0x70UL
+#define GPIO_PRT_CFG_IN_EN1_Pos 7UL
+#define GPIO_PRT_CFG_IN_EN1_Msk 0x80UL
+#define GPIO_PRT_CFG_DRIVE_MODE2_Pos 8UL
+#define GPIO_PRT_CFG_DRIVE_MODE2_Msk 0x700UL
+#define GPIO_PRT_CFG_IN_EN2_Pos 11UL
+#define GPIO_PRT_CFG_IN_EN2_Msk 0x800UL
+#define GPIO_PRT_CFG_DRIVE_MODE3_Pos 12UL
+#define GPIO_PRT_CFG_DRIVE_MODE3_Msk 0x7000UL
+#define GPIO_PRT_CFG_IN_EN3_Pos 15UL
+#define GPIO_PRT_CFG_IN_EN3_Msk 0x8000UL
+#define GPIO_PRT_CFG_DRIVE_MODE4_Pos 16UL
+#define GPIO_PRT_CFG_DRIVE_MODE4_Msk 0x70000UL
+#define GPIO_PRT_CFG_IN_EN4_Pos 19UL
+#define GPIO_PRT_CFG_IN_EN4_Msk 0x80000UL
+#define GPIO_PRT_CFG_DRIVE_MODE5_Pos 20UL
+#define GPIO_PRT_CFG_DRIVE_MODE5_Msk 0x700000UL
+#define GPIO_PRT_CFG_IN_EN5_Pos 23UL
+#define GPIO_PRT_CFG_IN_EN5_Msk 0x800000UL
+#define GPIO_PRT_CFG_DRIVE_MODE6_Pos 24UL
+#define GPIO_PRT_CFG_DRIVE_MODE6_Msk 0x7000000UL
+#define GPIO_PRT_CFG_IN_EN6_Pos 27UL
+#define GPIO_PRT_CFG_IN_EN6_Msk 0x8000000UL
+#define GPIO_PRT_CFG_DRIVE_MODE7_Pos 28UL
+#define GPIO_PRT_CFG_DRIVE_MODE7_Msk 0x70000000UL
+#define GPIO_PRT_CFG_IN_EN7_Pos 31UL
+#define GPIO_PRT_CFG_IN_EN7_Msk 0x80000000UL
+/* GPIO_PRT.CFG_IN */
+#define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Pos 0UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Msk 0x1UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Pos 1UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Msk 0x2UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Pos 2UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Msk 0x4UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Pos 3UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Msk 0x8UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Pos 4UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Msk 0x10UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Pos 5UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Msk 0x20UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Pos 6UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Msk 0x40UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Pos 7UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Msk 0x80UL
+/* GPIO_PRT.CFG_OUT */
+#define GPIO_PRT_CFG_OUT_SLOW0_Pos 0UL
+#define GPIO_PRT_CFG_OUT_SLOW0_Msk 0x1UL
+#define GPIO_PRT_CFG_OUT_SLOW1_Pos 1UL
+#define GPIO_PRT_CFG_OUT_SLOW1_Msk 0x2UL
+#define GPIO_PRT_CFG_OUT_SLOW2_Pos 2UL
+#define GPIO_PRT_CFG_OUT_SLOW2_Msk 0x4UL
+#define GPIO_PRT_CFG_OUT_SLOW3_Pos 3UL
+#define GPIO_PRT_CFG_OUT_SLOW3_Msk 0x8UL
+#define GPIO_PRT_CFG_OUT_SLOW4_Pos 4UL
+#define GPIO_PRT_CFG_OUT_SLOW4_Msk 0x10UL
+#define GPIO_PRT_CFG_OUT_SLOW5_Pos 5UL
+#define GPIO_PRT_CFG_OUT_SLOW5_Msk 0x20UL
+#define GPIO_PRT_CFG_OUT_SLOW6_Pos 6UL
+#define GPIO_PRT_CFG_OUT_SLOW6_Msk 0x40UL
+#define GPIO_PRT_CFG_OUT_SLOW7_Pos 7UL
+#define GPIO_PRT_CFG_OUT_SLOW7_Msk 0x80UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Pos 16UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Msk 0x30000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Pos 18UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Msk 0xC0000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Pos 20UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Msk 0x300000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Pos 22UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Msk 0xC00000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Pos 24UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Msk 0x3000000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Pos 26UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Msk 0xC000000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Pos 28UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Msk 0x30000000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Pos 30UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Msk 0xC0000000UL
+/* GPIO_PRT.CFG_SIO */
+#define GPIO_PRT_CFG_SIO_VREG_EN01_Pos 0UL
+#define GPIO_PRT_CFG_SIO_VREG_EN01_Msk 0x1UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL01_Pos 1UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL01_Msk 0x2UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Pos 2UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Msk 0x4UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL01_Pos 3UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL01_Msk 0x18UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL01_Pos 5UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL01_Msk 0xE0UL
+#define GPIO_PRT_CFG_SIO_VREG_EN23_Pos 8UL
+#define GPIO_PRT_CFG_SIO_VREG_EN23_Msk 0x100UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL23_Pos 9UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL23_Msk 0x200UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Pos 10UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Msk 0x400UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL23_Pos 11UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL23_Msk 0x1800UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL23_Pos 13UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL23_Msk 0xE000UL
+#define GPIO_PRT_CFG_SIO_VREG_EN45_Pos 16UL
+#define GPIO_PRT_CFG_SIO_VREG_EN45_Msk 0x10000UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL45_Pos 17UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL45_Msk 0x20000UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Pos 18UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Msk 0x40000UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL45_Pos 19UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL45_Msk 0x180000UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL45_Pos 21UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL45_Msk 0xE00000UL
+#define GPIO_PRT_CFG_SIO_VREG_EN67_Pos 24UL
+#define GPIO_PRT_CFG_SIO_VREG_EN67_Msk 0x1000000UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL67_Pos 25UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL67_Msk 0x2000000UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Pos 26UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Msk 0x4000000UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL67_Pos 27UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL67_Msk 0x18000000UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL67_Pos 29UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL67_Msk 0xE0000000UL
+/* GPIO_PRT.CFG_IN_GPIO5V */
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL0_1_Pos 0UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL0_1_Msk 0x1UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL1_1_Pos 1UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL1_1_Msk 0x2UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL2_1_Pos 2UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL2_1_Msk 0x4UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL3_1_Pos 3UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL3_1_Msk 0x8UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL4_1_Pos 4UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL4_1_Msk 0x10UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL5_1_Pos 5UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL5_1_Msk 0x20UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL6_1_Pos 6UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL6_1_Msk 0x40UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL7_1_Pos 7UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL7_1_Msk 0x80UL
+
+
+/* GPIO.INTR_CAUSE0 */
+#define GPIO_INTR_CAUSE0_PORT_INT_Pos 0UL
+#define GPIO_INTR_CAUSE0_PORT_INT_Msk 0xFFFFFFFFUL
+/* GPIO.INTR_CAUSE1 */
+#define GPIO_INTR_CAUSE1_PORT_INT_Pos 0UL
+#define GPIO_INTR_CAUSE1_PORT_INT_Msk 0xFFFFFFFFUL
+/* GPIO.INTR_CAUSE2 */
+#define GPIO_INTR_CAUSE2_PORT_INT_Pos 0UL
+#define GPIO_INTR_CAUSE2_PORT_INT_Msk 0xFFFFFFFFUL
+/* GPIO.INTR_CAUSE3 */
+#define GPIO_INTR_CAUSE3_PORT_INT_Pos 0UL
+#define GPIO_INTR_CAUSE3_PORT_INT_Msk 0xFFFFFFFFUL
+/* GPIO.VDD_ACTIVE */
+#define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Pos 30UL
+#define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Pos 31UL
+#define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Msk 0x80000000UL
+/* GPIO.VDD_INTR */
+#define GPIO_VDD_INTR_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_VDD_INTR_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_VDD_INTR_VDDA_ACTIVE_Pos 30UL
+#define GPIO_VDD_INTR_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_VDD_INTR_VDDD_ACTIVE_Pos 31UL
+#define GPIO_VDD_INTR_VDDD_ACTIVE_Msk 0x80000000UL
+/* GPIO.VDD_INTR_MASK */
+#define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Pos 30UL
+#define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Pos 31UL
+#define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Msk 0x80000000UL
+/* GPIO.VDD_INTR_MASKED */
+#define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Pos 30UL
+#define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Pos 31UL
+#define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Msk 0x80000000UL
+/* GPIO.VDD_INTR_SET */
+#define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Pos 30UL
+#define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Pos 31UL
+#define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Msk 0x80000000UL
+
+
+#endif /* _CYIP_GPIO_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_gpio_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_gpio_v2.h
new file mode 100644
index 0000000000..5eca17e057
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_gpio_v2.h
@@ -0,0 +1,478 @@
+/***************************************************************************//**
+* \file cyip_gpio_v2.h
+*
+* \brief
+* GPIO IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_GPIO_V2_H_
+#define _CYIP_GPIO_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* GPIO
+*******************************************************************************/
+
+#define GPIO_PRT_V2_SECTION_SIZE 0x00000080UL
+#define GPIO_V2_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief GPIO port registers (GPIO_PRT)
+ */
+typedef struct {
+ __IOM uint32_t OUT; /*!< 0x00000000 Port output data register */
+ __IOM uint32_t OUT_CLR; /*!< 0x00000004 Port output data clear register */
+ __IOM uint32_t OUT_SET; /*!< 0x00000008 Port output data set register */
+ __IOM uint32_t OUT_INV; /*!< 0x0000000C Port output data invert register */
+ __IM uint32_t IN; /*!< 0x00000010 Port input state register */
+ __IOM uint32_t INTR; /*!< 0x00000014 Port interrupt status register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000018 Port interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000001C Port interrupt masked status register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000020 Port interrupt set register */
+ __IM uint32_t RESERVED[7];
+ __IOM uint32_t INTR_CFG; /*!< 0x00000040 Port interrupt configuration register */
+ __IOM uint32_t CFG; /*!< 0x00000044 Port configuration register */
+ __IOM uint32_t CFG_IN; /*!< 0x00000048 Port input buffer configuration register */
+ __IOM uint32_t CFG_OUT; /*!< 0x0000004C Port output buffer configuration register */
+ __IOM uint32_t CFG_SIO; /*!< 0x00000050 Port SIO configuration register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t CFG_IN_AUTOLVL; /*!< 0x00000058 Port input buffer AUTOLVL configuration register for S40E GPIO */
+ __IM uint32_t RESERVED2[9];
+} GPIO_PRT_V2_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * \brief GPIO port control/configuration (GPIO)
+ */
+typedef struct {
+ GPIO_PRT_V2_Type PRT[128]; /*!< 0x00000000 GPIO port registers */
+ __IM uint32_t INTR_CAUSE0; /*!< 0x00004000 Interrupt port cause register 0 */
+ __IM uint32_t INTR_CAUSE1; /*!< 0x00004004 Interrupt port cause register 1 */
+ __IM uint32_t INTR_CAUSE2; /*!< 0x00004008 Interrupt port cause register 2 */
+ __IM uint32_t INTR_CAUSE3; /*!< 0x0000400C Interrupt port cause register 3 */
+ __IM uint32_t VDD_ACTIVE; /*!< 0x00004010 Extern power supply detection register */
+ __IOM uint32_t VDD_INTR; /*!< 0x00004014 Supply detection interrupt register */
+ __IOM uint32_t VDD_INTR_MASK; /*!< 0x00004018 Supply detection interrupt mask register */
+ __IM uint32_t VDD_INTR_MASKED; /*!< 0x0000401C Supply detection interrupt masked register */
+ __IOM uint32_t VDD_INTR_SET; /*!< 0x00004020 Supply detection interrupt set register */
+} GPIO_V2_Type; /*!< Size = 16420 (0x4024) */
+
+
+/* GPIO_PRT.OUT */
+#define GPIO_PRT_V2_OUT_OUT0_Pos 0UL
+#define GPIO_PRT_V2_OUT_OUT0_Msk 0x1UL
+#define GPIO_PRT_V2_OUT_OUT1_Pos 1UL
+#define GPIO_PRT_V2_OUT_OUT1_Msk 0x2UL
+#define GPIO_PRT_V2_OUT_OUT2_Pos 2UL
+#define GPIO_PRT_V2_OUT_OUT2_Msk 0x4UL
+#define GPIO_PRT_V2_OUT_OUT3_Pos 3UL
+#define GPIO_PRT_V2_OUT_OUT3_Msk 0x8UL
+#define GPIO_PRT_V2_OUT_OUT4_Pos 4UL
+#define GPIO_PRT_V2_OUT_OUT4_Msk 0x10UL
+#define GPIO_PRT_V2_OUT_OUT5_Pos 5UL
+#define GPIO_PRT_V2_OUT_OUT5_Msk 0x20UL
+#define GPIO_PRT_V2_OUT_OUT6_Pos 6UL
+#define GPIO_PRT_V2_OUT_OUT6_Msk 0x40UL
+#define GPIO_PRT_V2_OUT_OUT7_Pos 7UL
+#define GPIO_PRT_V2_OUT_OUT7_Msk 0x80UL
+/* GPIO_PRT.OUT_CLR */
+#define GPIO_PRT_V2_OUT_CLR_OUT0_Pos 0UL
+#define GPIO_PRT_V2_OUT_CLR_OUT0_Msk 0x1UL
+#define GPIO_PRT_V2_OUT_CLR_OUT1_Pos 1UL
+#define GPIO_PRT_V2_OUT_CLR_OUT1_Msk 0x2UL
+#define GPIO_PRT_V2_OUT_CLR_OUT2_Pos 2UL
+#define GPIO_PRT_V2_OUT_CLR_OUT2_Msk 0x4UL
+#define GPIO_PRT_V2_OUT_CLR_OUT3_Pos 3UL
+#define GPIO_PRT_V2_OUT_CLR_OUT3_Msk 0x8UL
+#define GPIO_PRT_V2_OUT_CLR_OUT4_Pos 4UL
+#define GPIO_PRT_V2_OUT_CLR_OUT4_Msk 0x10UL
+#define GPIO_PRT_V2_OUT_CLR_OUT5_Pos 5UL
+#define GPIO_PRT_V2_OUT_CLR_OUT5_Msk 0x20UL
+#define GPIO_PRT_V2_OUT_CLR_OUT6_Pos 6UL
+#define GPIO_PRT_V2_OUT_CLR_OUT6_Msk 0x40UL
+#define GPIO_PRT_V2_OUT_CLR_OUT7_Pos 7UL
+#define GPIO_PRT_V2_OUT_CLR_OUT7_Msk 0x80UL
+/* GPIO_PRT.OUT_SET */
+#define GPIO_PRT_V2_OUT_SET_OUT0_Pos 0UL
+#define GPIO_PRT_V2_OUT_SET_OUT0_Msk 0x1UL
+#define GPIO_PRT_V2_OUT_SET_OUT1_Pos 1UL
+#define GPIO_PRT_V2_OUT_SET_OUT1_Msk 0x2UL
+#define GPIO_PRT_V2_OUT_SET_OUT2_Pos 2UL
+#define GPIO_PRT_V2_OUT_SET_OUT2_Msk 0x4UL
+#define GPIO_PRT_V2_OUT_SET_OUT3_Pos 3UL
+#define GPIO_PRT_V2_OUT_SET_OUT3_Msk 0x8UL
+#define GPIO_PRT_V2_OUT_SET_OUT4_Pos 4UL
+#define GPIO_PRT_V2_OUT_SET_OUT4_Msk 0x10UL
+#define GPIO_PRT_V2_OUT_SET_OUT5_Pos 5UL
+#define GPIO_PRT_V2_OUT_SET_OUT5_Msk 0x20UL
+#define GPIO_PRT_V2_OUT_SET_OUT6_Pos 6UL
+#define GPIO_PRT_V2_OUT_SET_OUT6_Msk 0x40UL
+#define GPIO_PRT_V2_OUT_SET_OUT7_Pos 7UL
+#define GPIO_PRT_V2_OUT_SET_OUT7_Msk 0x80UL
+/* GPIO_PRT.OUT_INV */
+#define GPIO_PRT_V2_OUT_INV_OUT0_Pos 0UL
+#define GPIO_PRT_V2_OUT_INV_OUT0_Msk 0x1UL
+#define GPIO_PRT_V2_OUT_INV_OUT1_Pos 1UL
+#define GPIO_PRT_V2_OUT_INV_OUT1_Msk 0x2UL
+#define GPIO_PRT_V2_OUT_INV_OUT2_Pos 2UL
+#define GPIO_PRT_V2_OUT_INV_OUT2_Msk 0x4UL
+#define GPIO_PRT_V2_OUT_INV_OUT3_Pos 3UL
+#define GPIO_PRT_V2_OUT_INV_OUT3_Msk 0x8UL
+#define GPIO_PRT_V2_OUT_INV_OUT4_Pos 4UL
+#define GPIO_PRT_V2_OUT_INV_OUT4_Msk 0x10UL
+#define GPIO_PRT_V2_OUT_INV_OUT5_Pos 5UL
+#define GPIO_PRT_V2_OUT_INV_OUT5_Msk 0x20UL
+#define GPIO_PRT_V2_OUT_INV_OUT6_Pos 6UL
+#define GPIO_PRT_V2_OUT_INV_OUT6_Msk 0x40UL
+#define GPIO_PRT_V2_OUT_INV_OUT7_Pos 7UL
+#define GPIO_PRT_V2_OUT_INV_OUT7_Msk 0x80UL
+/* GPIO_PRT.IN */
+#define GPIO_PRT_V2_IN_IN0_Pos 0UL
+#define GPIO_PRT_V2_IN_IN0_Msk 0x1UL
+#define GPIO_PRT_V2_IN_IN1_Pos 1UL
+#define GPIO_PRT_V2_IN_IN1_Msk 0x2UL
+#define GPIO_PRT_V2_IN_IN2_Pos 2UL
+#define GPIO_PRT_V2_IN_IN2_Msk 0x4UL
+#define GPIO_PRT_V2_IN_IN3_Pos 3UL
+#define GPIO_PRT_V2_IN_IN3_Msk 0x8UL
+#define GPIO_PRT_V2_IN_IN4_Pos 4UL
+#define GPIO_PRT_V2_IN_IN4_Msk 0x10UL
+#define GPIO_PRT_V2_IN_IN5_Pos 5UL
+#define GPIO_PRT_V2_IN_IN5_Msk 0x20UL
+#define GPIO_PRT_V2_IN_IN6_Pos 6UL
+#define GPIO_PRT_V2_IN_IN6_Msk 0x40UL
+#define GPIO_PRT_V2_IN_IN7_Pos 7UL
+#define GPIO_PRT_V2_IN_IN7_Msk 0x80UL
+#define GPIO_PRT_V2_IN_FLT_IN_Pos 8UL
+#define GPIO_PRT_V2_IN_FLT_IN_Msk 0x100UL
+/* GPIO_PRT.INTR */
+#define GPIO_PRT_V2_INTR_EDGE0_Pos 0UL
+#define GPIO_PRT_V2_INTR_EDGE0_Msk 0x1UL
+#define GPIO_PRT_V2_INTR_EDGE1_Pos 1UL
+#define GPIO_PRT_V2_INTR_EDGE1_Msk 0x2UL
+#define GPIO_PRT_V2_INTR_EDGE2_Pos 2UL
+#define GPIO_PRT_V2_INTR_EDGE2_Msk 0x4UL
+#define GPIO_PRT_V2_INTR_EDGE3_Pos 3UL
+#define GPIO_PRT_V2_INTR_EDGE3_Msk 0x8UL
+#define GPIO_PRT_V2_INTR_EDGE4_Pos 4UL
+#define GPIO_PRT_V2_INTR_EDGE4_Msk 0x10UL
+#define GPIO_PRT_V2_INTR_EDGE5_Pos 5UL
+#define GPIO_PRT_V2_INTR_EDGE5_Msk 0x20UL
+#define GPIO_PRT_V2_INTR_EDGE6_Pos 6UL
+#define GPIO_PRT_V2_INTR_EDGE6_Msk 0x40UL
+#define GPIO_PRT_V2_INTR_EDGE7_Pos 7UL
+#define GPIO_PRT_V2_INTR_EDGE7_Msk 0x80UL
+#define GPIO_PRT_V2_INTR_FLT_EDGE_Pos 8UL
+#define GPIO_PRT_V2_INTR_FLT_EDGE_Msk 0x100UL
+#define GPIO_PRT_V2_INTR_IN_IN0_Pos 16UL
+#define GPIO_PRT_V2_INTR_IN_IN0_Msk 0x10000UL
+#define GPIO_PRT_V2_INTR_IN_IN1_Pos 17UL
+#define GPIO_PRT_V2_INTR_IN_IN1_Msk 0x20000UL
+#define GPIO_PRT_V2_INTR_IN_IN2_Pos 18UL
+#define GPIO_PRT_V2_INTR_IN_IN2_Msk 0x40000UL
+#define GPIO_PRT_V2_INTR_IN_IN3_Pos 19UL
+#define GPIO_PRT_V2_INTR_IN_IN3_Msk 0x80000UL
+#define GPIO_PRT_V2_INTR_IN_IN4_Pos 20UL
+#define GPIO_PRT_V2_INTR_IN_IN4_Msk 0x100000UL
+#define GPIO_PRT_V2_INTR_IN_IN5_Pos 21UL
+#define GPIO_PRT_V2_INTR_IN_IN5_Msk 0x200000UL
+#define GPIO_PRT_V2_INTR_IN_IN6_Pos 22UL
+#define GPIO_PRT_V2_INTR_IN_IN6_Msk 0x400000UL
+#define GPIO_PRT_V2_INTR_IN_IN7_Pos 23UL
+#define GPIO_PRT_V2_INTR_IN_IN7_Msk 0x800000UL
+#define GPIO_PRT_V2_INTR_FLT_IN_IN_Pos 24UL
+#define GPIO_PRT_V2_INTR_FLT_IN_IN_Msk 0x1000000UL
+/* GPIO_PRT.INTR_MASK */
+#define GPIO_PRT_V2_INTR_MASK_EDGE0_Pos 0UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE0_Msk 0x1UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE1_Pos 1UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE1_Msk 0x2UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE2_Pos 2UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE2_Msk 0x4UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE3_Pos 3UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE3_Msk 0x8UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE4_Pos 4UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE4_Msk 0x10UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE5_Pos 5UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE5_Msk 0x20UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE6_Pos 6UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE6_Msk 0x40UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE7_Pos 7UL
+#define GPIO_PRT_V2_INTR_MASK_EDGE7_Msk 0x80UL
+#define GPIO_PRT_V2_INTR_MASK_FLT_EDGE_Pos 8UL
+#define GPIO_PRT_V2_INTR_MASK_FLT_EDGE_Msk 0x100UL
+/* GPIO_PRT.INTR_MASKED */
+#define GPIO_PRT_V2_INTR_MASKED_EDGE0_Pos 0UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE0_Msk 0x1UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE1_Pos 1UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE1_Msk 0x2UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE2_Pos 2UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE2_Msk 0x4UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE3_Pos 3UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE3_Msk 0x8UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE4_Pos 4UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE4_Msk 0x10UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE5_Pos 5UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE5_Msk 0x20UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE6_Pos 6UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE6_Msk 0x40UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE7_Pos 7UL
+#define GPIO_PRT_V2_INTR_MASKED_EDGE7_Msk 0x80UL
+#define GPIO_PRT_V2_INTR_MASKED_FLT_EDGE_Pos 8UL
+#define GPIO_PRT_V2_INTR_MASKED_FLT_EDGE_Msk 0x100UL
+/* GPIO_PRT.INTR_SET */
+#define GPIO_PRT_V2_INTR_SET_EDGE0_Pos 0UL
+#define GPIO_PRT_V2_INTR_SET_EDGE0_Msk 0x1UL
+#define GPIO_PRT_V2_INTR_SET_EDGE1_Pos 1UL
+#define GPIO_PRT_V2_INTR_SET_EDGE1_Msk 0x2UL
+#define GPIO_PRT_V2_INTR_SET_EDGE2_Pos 2UL
+#define GPIO_PRT_V2_INTR_SET_EDGE2_Msk 0x4UL
+#define GPIO_PRT_V2_INTR_SET_EDGE3_Pos 3UL
+#define GPIO_PRT_V2_INTR_SET_EDGE3_Msk 0x8UL
+#define GPIO_PRT_V2_INTR_SET_EDGE4_Pos 4UL
+#define GPIO_PRT_V2_INTR_SET_EDGE4_Msk 0x10UL
+#define GPIO_PRT_V2_INTR_SET_EDGE5_Pos 5UL
+#define GPIO_PRT_V2_INTR_SET_EDGE5_Msk 0x20UL
+#define GPIO_PRT_V2_INTR_SET_EDGE6_Pos 6UL
+#define GPIO_PRT_V2_INTR_SET_EDGE6_Msk 0x40UL
+#define GPIO_PRT_V2_INTR_SET_EDGE7_Pos 7UL
+#define GPIO_PRT_V2_INTR_SET_EDGE7_Msk 0x80UL
+#define GPIO_PRT_V2_INTR_SET_FLT_EDGE_Pos 8UL
+#define GPIO_PRT_V2_INTR_SET_FLT_EDGE_Msk 0x100UL
+/* GPIO_PRT.INTR_CFG */
+#define GPIO_PRT_V2_INTR_CFG_EDGE0_SEL_Pos 0UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE0_SEL_Msk 0x3UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE1_SEL_Pos 2UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE1_SEL_Msk 0xCUL
+#define GPIO_PRT_V2_INTR_CFG_EDGE2_SEL_Pos 4UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE2_SEL_Msk 0x30UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE3_SEL_Pos 6UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE3_SEL_Msk 0xC0UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE4_SEL_Pos 8UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE4_SEL_Msk 0x300UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE5_SEL_Pos 10UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE5_SEL_Msk 0xC00UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE6_SEL_Pos 12UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE6_SEL_Msk 0x3000UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE7_SEL_Pos 14UL
+#define GPIO_PRT_V2_INTR_CFG_EDGE7_SEL_Msk 0xC000UL
+#define GPIO_PRT_V2_INTR_CFG_FLT_EDGE_SEL_Pos 16UL
+#define GPIO_PRT_V2_INTR_CFG_FLT_EDGE_SEL_Msk 0x30000UL
+#define GPIO_PRT_V2_INTR_CFG_FLT_SEL_Pos 18UL
+#define GPIO_PRT_V2_INTR_CFG_FLT_SEL_Msk 0x1C0000UL
+/* GPIO_PRT.CFG */
+#define GPIO_PRT_V2_CFG_DRIVE_MODE0_Pos 0UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE0_Msk 0x7UL
+#define GPIO_PRT_V2_CFG_IN_EN0_Pos 3UL
+#define GPIO_PRT_V2_CFG_IN_EN0_Msk 0x8UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE1_Pos 4UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE1_Msk 0x70UL
+#define GPIO_PRT_V2_CFG_IN_EN1_Pos 7UL
+#define GPIO_PRT_V2_CFG_IN_EN1_Msk 0x80UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE2_Pos 8UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE2_Msk 0x700UL
+#define GPIO_PRT_V2_CFG_IN_EN2_Pos 11UL
+#define GPIO_PRT_V2_CFG_IN_EN2_Msk 0x800UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE3_Pos 12UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE3_Msk 0x7000UL
+#define GPIO_PRT_V2_CFG_IN_EN3_Pos 15UL
+#define GPIO_PRT_V2_CFG_IN_EN3_Msk 0x8000UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE4_Pos 16UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE4_Msk 0x70000UL
+#define GPIO_PRT_V2_CFG_IN_EN4_Pos 19UL
+#define GPIO_PRT_V2_CFG_IN_EN4_Msk 0x80000UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE5_Pos 20UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE5_Msk 0x700000UL
+#define GPIO_PRT_V2_CFG_IN_EN5_Pos 23UL
+#define GPIO_PRT_V2_CFG_IN_EN5_Msk 0x800000UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE6_Pos 24UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE6_Msk 0x7000000UL
+#define GPIO_PRT_V2_CFG_IN_EN6_Pos 27UL
+#define GPIO_PRT_V2_CFG_IN_EN6_Msk 0x8000000UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE7_Pos 28UL
+#define GPIO_PRT_V2_CFG_DRIVE_MODE7_Msk 0x70000000UL
+#define GPIO_PRT_V2_CFG_IN_EN7_Pos 31UL
+#define GPIO_PRT_V2_CFG_IN_EN7_Msk 0x80000000UL
+/* GPIO_PRT.CFG_IN */
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL0_0_Pos 0UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL0_0_Msk 0x1UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL1_0_Pos 1UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL1_0_Msk 0x2UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL2_0_Pos 2UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL2_0_Msk 0x4UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL3_0_Pos 3UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL3_0_Msk 0x8UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL4_0_Pos 4UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL4_0_Msk 0x10UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL5_0_Pos 5UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL5_0_Msk 0x20UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL6_0_Pos 6UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL6_0_Msk 0x40UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL7_0_Pos 7UL
+#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL7_0_Msk 0x80UL
+/* GPIO_PRT.CFG_OUT */
+#define GPIO_PRT_V2_CFG_OUT_SLOW0_Pos 0UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW0_Msk 0x1UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW1_Pos 1UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW1_Msk 0x2UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW2_Pos 2UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW2_Msk 0x4UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW3_Pos 3UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW3_Msk 0x8UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW4_Pos 4UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW4_Msk 0x10UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW5_Pos 5UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW5_Msk 0x20UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW6_Pos 6UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW6_Msk 0x40UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW7_Pos 7UL
+#define GPIO_PRT_V2_CFG_OUT_SLOW7_Msk 0x80UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL0_Pos 16UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL0_Msk 0x30000UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL1_Pos 18UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL1_Msk 0xC0000UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL2_Pos 20UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL2_Msk 0x300000UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL3_Pos 22UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL3_Msk 0xC00000UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL4_Pos 24UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL4_Msk 0x3000000UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL5_Pos 26UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL5_Msk 0xC000000UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL6_Pos 28UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL6_Msk 0x30000000UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL7_Pos 30UL
+#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL7_Msk 0xC0000000UL
+/* GPIO_PRT.CFG_SIO */
+#define GPIO_PRT_V2_CFG_SIO_VREG_EN01_Pos 0UL
+#define GPIO_PRT_V2_CFG_SIO_VREG_EN01_Msk 0x1UL
+#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL01_Pos 1UL
+#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL01_Msk 0x2UL
+#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL01_Pos 2UL
+#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL01_Msk 0x4UL
+#define GPIO_PRT_V2_CFG_SIO_VREF_SEL01_Pos 3UL
+#define GPIO_PRT_V2_CFG_SIO_VREF_SEL01_Msk 0x18UL
+#define GPIO_PRT_V2_CFG_SIO_VOH_SEL01_Pos 5UL
+#define GPIO_PRT_V2_CFG_SIO_VOH_SEL01_Msk 0xE0UL
+#define GPIO_PRT_V2_CFG_SIO_VREG_EN23_Pos 8UL
+#define GPIO_PRT_V2_CFG_SIO_VREG_EN23_Msk 0x100UL
+#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL23_Pos 9UL
+#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL23_Msk 0x200UL
+#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL23_Pos 10UL
+#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL23_Msk 0x400UL
+#define GPIO_PRT_V2_CFG_SIO_VREF_SEL23_Pos 11UL
+#define GPIO_PRT_V2_CFG_SIO_VREF_SEL23_Msk 0x1800UL
+#define GPIO_PRT_V2_CFG_SIO_VOH_SEL23_Pos 13UL
+#define GPIO_PRT_V2_CFG_SIO_VOH_SEL23_Msk 0xE000UL
+#define GPIO_PRT_V2_CFG_SIO_VREG_EN45_Pos 16UL
+#define GPIO_PRT_V2_CFG_SIO_VREG_EN45_Msk 0x10000UL
+#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL45_Pos 17UL
+#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL45_Msk 0x20000UL
+#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL45_Pos 18UL
+#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL45_Msk 0x40000UL
+#define GPIO_PRT_V2_CFG_SIO_VREF_SEL45_Pos 19UL
+#define GPIO_PRT_V2_CFG_SIO_VREF_SEL45_Msk 0x180000UL
+#define GPIO_PRT_V2_CFG_SIO_VOH_SEL45_Pos 21UL
+#define GPIO_PRT_V2_CFG_SIO_VOH_SEL45_Msk 0xE00000UL
+#define GPIO_PRT_V2_CFG_SIO_VREG_EN67_Pos 24UL
+#define GPIO_PRT_V2_CFG_SIO_VREG_EN67_Msk 0x1000000UL
+#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL67_Pos 25UL
+#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL67_Msk 0x2000000UL
+#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL67_Pos 26UL
+#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL67_Msk 0x4000000UL
+#define GPIO_PRT_V2_CFG_SIO_VREF_SEL67_Pos 27UL
+#define GPIO_PRT_V2_CFG_SIO_VREF_SEL67_Msk 0x18000000UL
+#define GPIO_PRT_V2_CFG_SIO_VOH_SEL67_Pos 29UL
+#define GPIO_PRT_V2_CFG_SIO_VOH_SEL67_Msk 0xE0000000UL
+/* GPIO_PRT.CFG_IN_AUTOLVL */
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Pos 0UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Msk 0x1UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Pos 1UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Msk 0x2UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Pos 2UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Msk 0x4UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Pos 3UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Msk 0x8UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Pos 4UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Msk 0x10UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Pos 5UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Msk 0x20UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Pos 6UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Msk 0x40UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Pos 7UL
+#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Msk 0x80UL
+
+
+/* GPIO.INTR_CAUSE0 */
+#define GPIO_V2_INTR_CAUSE0_PORT_INT_Pos 0UL
+#define GPIO_V2_INTR_CAUSE0_PORT_INT_Msk 0xFFFFFFFFUL
+/* GPIO.INTR_CAUSE1 */
+#define GPIO_V2_INTR_CAUSE1_PORT_INT_Pos 0UL
+#define GPIO_V2_INTR_CAUSE1_PORT_INT_Msk 0xFFFFFFFFUL
+/* GPIO.INTR_CAUSE2 */
+#define GPIO_V2_INTR_CAUSE2_PORT_INT_Pos 0UL
+#define GPIO_V2_INTR_CAUSE2_PORT_INT_Msk 0xFFFFFFFFUL
+/* GPIO.INTR_CAUSE3 */
+#define GPIO_V2_INTR_CAUSE3_PORT_INT_Pos 0UL
+#define GPIO_V2_INTR_CAUSE3_PORT_INT_Msk 0xFFFFFFFFUL
+/* GPIO.VDD_ACTIVE */
+#define GPIO_V2_VDD_ACTIVE_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_V2_VDD_ACTIVE_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_V2_VDD_ACTIVE_VDDA_ACTIVE_Pos 30UL
+#define GPIO_V2_VDD_ACTIVE_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_V2_VDD_ACTIVE_VDDD_ACTIVE_Pos 31UL
+#define GPIO_V2_VDD_ACTIVE_VDDD_ACTIVE_Msk 0x80000000UL
+/* GPIO.VDD_INTR */
+#define GPIO_V2_VDD_INTR_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_V2_VDD_INTR_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_V2_VDD_INTR_VDDA_ACTIVE_Pos 30UL
+#define GPIO_V2_VDD_INTR_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_V2_VDD_INTR_VDDD_ACTIVE_Pos 31UL
+#define GPIO_V2_VDD_INTR_VDDD_ACTIVE_Msk 0x80000000UL
+/* GPIO.VDD_INTR_MASK */
+#define GPIO_V2_VDD_INTR_MASK_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_V2_VDD_INTR_MASK_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_V2_VDD_INTR_MASK_VDDA_ACTIVE_Pos 30UL
+#define GPIO_V2_VDD_INTR_MASK_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_V2_VDD_INTR_MASK_VDDD_ACTIVE_Pos 31UL
+#define GPIO_V2_VDD_INTR_MASK_VDDD_ACTIVE_Msk 0x80000000UL
+/* GPIO.VDD_INTR_MASKED */
+#define GPIO_V2_VDD_INTR_MASKED_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_V2_VDD_INTR_MASKED_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_V2_VDD_INTR_MASKED_VDDA_ACTIVE_Pos 30UL
+#define GPIO_V2_VDD_INTR_MASKED_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_V2_VDD_INTR_MASKED_VDDD_ACTIVE_Pos 31UL
+#define GPIO_V2_VDD_INTR_MASKED_VDDD_ACTIVE_Msk 0x80000000UL
+/* GPIO.VDD_INTR_SET */
+#define GPIO_V2_VDD_INTR_SET_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_V2_VDD_INTR_SET_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_V2_VDD_INTR_SET_VDDA_ACTIVE_Pos 30UL
+#define GPIO_V2_VDD_INTR_SET_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_V2_VDD_INTR_SET_VDDD_ACTIVE_Pos 31UL
+#define GPIO_V2_VDD_INTR_SET_VDDD_ACTIVE_Msk 0x80000000UL
+
+
+#endif /* _CYIP_GPIO_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_headers.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_headers.h
new file mode 100644
index 0000000000..788f18fd76
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_headers.h
@@ -0,0 +1,44 @@
+/***************************************************************************//**
+* \file cyip_headers.h
+*
+* \brief
+* Common header file to be included by all IP definition headers
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_HEADERS_H_
+#define _CYIP_HEADERS_H_
+
+#include <stdint.h>
+
+/* These are CMSIS-CORE defines used for structure members definitions */
+#ifndef __IM
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#endif
+#ifndef __OM
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#endif
+#ifndef __IOM
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+#endif
+
+#endif /* _CYIP_HEADERS_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_hsiom.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_hsiom.h
new file mode 100644
index 0000000000..62509103f6
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_hsiom.h
@@ -0,0 +1,97 @@
+/***************************************************************************//**
+* \file cyip_hsiom.h
+*
+* \brief
+* HSIOM IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_HSIOM_H_
+#define _CYIP_HSIOM_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* HSIOM
+*******************************************************************************/
+
+#define HSIOM_PRT_SECTION_SIZE 0x00000010UL
+#define HSIOM_SECTION_SIZE 0x00004000UL
+
+/**
+ * \brief HSIOM port registers (HSIOM_PRT)
+ */
+typedef struct {
+ __IOM uint32_t PORT_SEL0; /*!< 0x00000000 Port selection 0 */
+ __IOM uint32_t PORT_SEL1; /*!< 0x00000004 Port selection 1 */
+ __IM uint32_t RESERVED[2];
+} HSIOM_PRT_V1_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * \brief High Speed IO Matrix (HSIOM) (HSIOM)
+ */
+typedef struct {
+ HSIOM_PRT_V1_Type PRT[128]; /*!< 0x00000000 HSIOM port registers */
+ __IM uint32_t RESERVED[1536];
+ __IOM uint32_t AMUX_SPLIT_CTL[64]; /*!< 0x00002000 AMUX splitter cell control */
+} HSIOM_V1_Type; /*!< Size = 8448 (0x2100) */
+
+
+/* HSIOM_PRT.PORT_SEL0 */
+#define HSIOM_PRT_PORT_SEL0_IO0_SEL_Pos 0UL
+#define HSIOM_PRT_PORT_SEL0_IO0_SEL_Msk 0x1FUL
+#define HSIOM_PRT_PORT_SEL0_IO1_SEL_Pos 8UL
+#define HSIOM_PRT_PORT_SEL0_IO1_SEL_Msk 0x1F00UL
+#define HSIOM_PRT_PORT_SEL0_IO2_SEL_Pos 16UL
+#define HSIOM_PRT_PORT_SEL0_IO2_SEL_Msk 0x1F0000UL
+#define HSIOM_PRT_PORT_SEL0_IO3_SEL_Pos 24UL
+#define HSIOM_PRT_PORT_SEL0_IO3_SEL_Msk 0x1F000000UL
+/* HSIOM_PRT.PORT_SEL1 */
+#define HSIOM_PRT_PORT_SEL1_IO4_SEL_Pos 0UL
+#define HSIOM_PRT_PORT_SEL1_IO4_SEL_Msk 0x1FUL
+#define HSIOM_PRT_PORT_SEL1_IO5_SEL_Pos 8UL
+#define HSIOM_PRT_PORT_SEL1_IO5_SEL_Msk 0x1F00UL
+#define HSIOM_PRT_PORT_SEL1_IO6_SEL_Pos 16UL
+#define HSIOM_PRT_PORT_SEL1_IO6_SEL_Msk 0x1F0000UL
+#define HSIOM_PRT_PORT_SEL1_IO7_SEL_Pos 24UL
+#define HSIOM_PRT_PORT_SEL1_IO7_SEL_Msk 0x1F000000UL
+
+
+/* HSIOM.AMUX_SPLIT_CTL */
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos 0UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk 0x1UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Pos 1UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk 0x2UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Pos 2UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk 0x4UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos 4UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk 0x10UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Pos 5UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk 0x20UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Pos 6UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk 0x40UL
+
+
+#endif /* _CYIP_HSIOM_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_hsiom_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_hsiom_v2.h
new file mode 100644
index 0000000000..350edad2a1
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_hsiom_v2.h
@@ -0,0 +1,119 @@
+/***************************************************************************//**
+* \file cyip_hsiom_v2.h
+*
+* \brief
+* HSIOM IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_HSIOM_V2_H_
+#define _CYIP_HSIOM_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* HSIOM
+*******************************************************************************/
+
+#define HSIOM_PRT_V2_SECTION_SIZE 0x00000010UL
+#define HSIOM_V2_SECTION_SIZE 0x00004000UL
+
+/**
+ * \brief HSIOM port registers (HSIOM_PRT)
+ */
+typedef struct {
+ __IOM uint32_t PORT_SEL0; /*!< 0x00000000 Port selection 0 */
+ __IOM uint32_t PORT_SEL1; /*!< 0x00000004 Port selection 1 */
+ __IM uint32_t RESERVED[2];
+} HSIOM_PRT_V2_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * \brief High Speed IO Matrix (HSIOM) (HSIOM)
+ */
+typedef struct {
+ HSIOM_PRT_V2_Type PRT[128]; /*!< 0x00000000 HSIOM port registers */
+ __IM uint32_t RESERVED[1536];
+ __IOM uint32_t AMUX_SPLIT_CTL[64]; /*!< 0x00002000 AMUX splitter cell control */
+ __IM uint32_t RESERVED1[64];
+ __IOM uint32_t MONITOR_CTL_0; /*!< 0x00002200 Power/Ground Monitor cell control 0 */
+ __IOM uint32_t MONITOR_CTL_1; /*!< 0x00002204 Power/Ground Monitor cell control 1 */
+ __IOM uint32_t MONITOR_CTL_2; /*!< 0x00002208 Power/Ground Monitor cell control 2 */
+ __IOM uint32_t MONITOR_CTL_3; /*!< 0x0000220C Power/Ground Monitor cell control 3 */
+ __IM uint32_t RESERVED2[12];
+ __IOM uint32_t ALT_JTAG_EN; /*!< 0x00002240 Alternate JTAG IF selection register */
+} HSIOM_V2_Type; /*!< Size = 8772 (0x2244) */
+
+
+/* HSIOM_PRT.PORT_SEL0 */
+#define HSIOM_PRT_V2_PORT_SEL0_IO0_SEL_Pos 0UL
+#define HSIOM_PRT_V2_PORT_SEL0_IO0_SEL_Msk 0x1FUL
+#define HSIOM_PRT_V2_PORT_SEL0_IO1_SEL_Pos 8UL
+#define HSIOM_PRT_V2_PORT_SEL0_IO1_SEL_Msk 0x1F00UL
+#define HSIOM_PRT_V2_PORT_SEL0_IO2_SEL_Pos 16UL
+#define HSIOM_PRT_V2_PORT_SEL0_IO2_SEL_Msk 0x1F0000UL
+#define HSIOM_PRT_V2_PORT_SEL0_IO3_SEL_Pos 24UL
+#define HSIOM_PRT_V2_PORT_SEL0_IO3_SEL_Msk 0x1F000000UL
+/* HSIOM_PRT.PORT_SEL1 */
+#define HSIOM_PRT_V2_PORT_SEL1_IO4_SEL_Pos 0UL
+#define HSIOM_PRT_V2_PORT_SEL1_IO4_SEL_Msk 0x1FUL
+#define HSIOM_PRT_V2_PORT_SEL1_IO5_SEL_Pos 8UL
+#define HSIOM_PRT_V2_PORT_SEL1_IO5_SEL_Msk 0x1F00UL
+#define HSIOM_PRT_V2_PORT_SEL1_IO6_SEL_Pos 16UL
+#define HSIOM_PRT_V2_PORT_SEL1_IO6_SEL_Msk 0x1F0000UL
+#define HSIOM_PRT_V2_PORT_SEL1_IO7_SEL_Pos 24UL
+#define HSIOM_PRT_V2_PORT_SEL1_IO7_SEL_Msk 0x1F000000UL
+
+
+/* HSIOM.AMUX_SPLIT_CTL */
+#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos 0UL
+#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk 0x1UL
+#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Pos 1UL
+#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk 0x2UL
+#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_S0_Pos 2UL
+#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk 0x4UL
+#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos 4UL
+#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk 0x10UL
+#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Pos 5UL
+#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk 0x20UL
+#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_S0_Pos 6UL
+#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk 0x40UL
+/* HSIOM.MONITOR_CTL_0 */
+#define HSIOM_V2_MONITOR_CTL_0_MONITOR_EN_Pos 0UL
+#define HSIOM_V2_MONITOR_CTL_0_MONITOR_EN_Msk 0xFFFFFFFFUL
+/* HSIOM.MONITOR_CTL_1 */
+#define HSIOM_V2_MONITOR_CTL_1_MONITOR_EN_Pos 0UL
+#define HSIOM_V2_MONITOR_CTL_1_MONITOR_EN_Msk 0xFFFFFFFFUL
+/* HSIOM.MONITOR_CTL_2 */
+#define HSIOM_V2_MONITOR_CTL_2_MONITOR_EN_Pos 0UL
+#define HSIOM_V2_MONITOR_CTL_2_MONITOR_EN_Msk 0xFFFFFFFFUL
+/* HSIOM.MONITOR_CTL_3 */
+#define HSIOM_V2_MONITOR_CTL_3_MONITOR_EN_Pos 0UL
+#define HSIOM_V2_MONITOR_CTL_3_MONITOR_EN_Msk 0xFFFFFFFFUL
+/* HSIOM.ALT_JTAG_EN */
+#define HSIOM_V2_ALT_JTAG_EN_ENABLE_Pos 31UL
+#define HSIOM_V2_ALT_JTAG_EN_ENABLE_Msk 0x80000000UL
+
+
+#endif /* _CYIP_HSIOM_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_i2s.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_i2s.h
new file mode 100644
index 0000000000..e3c0b247e1
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_i2s.h
@@ -0,0 +1,289 @@
+/***************************************************************************//**
+* \file cyip_i2s.h
+*
+* \brief
+* I2S IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_I2S_H_
+#define _CYIP_I2S_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* I2S
+*******************************************************************************/
+
+#define I2S_SECTION_SIZE 0x00001000UL
+
+/**
+ * \brief I2S registers (I2S)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t CMD; /*!< 0x00000020 Command */
+ __IM uint32_t RESERVED2[7];
+ __IOM uint32_t TR_CTL; /*!< 0x00000040 Trigger control */
+ __IM uint32_t RESERVED3[15];
+ __IOM uint32_t TX_CTL; /*!< 0x00000080 Transmitter control */
+ __IOM uint32_t TX_WATCHDOG; /*!< 0x00000084 Transmitter watchdog */
+ __IM uint32_t RESERVED4[6];
+ __IOM uint32_t RX_CTL; /*!< 0x000000A0 Receiver control */
+ __IOM uint32_t RX_WATCHDOG; /*!< 0x000000A4 Receiver watchdog */
+ __IM uint32_t RESERVED5[86];
+ __IOM uint32_t TX_FIFO_CTL; /*!< 0x00000200 TX FIFO control */
+ __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000204 TX FIFO status */
+ __OM uint32_t TX_FIFO_WR; /*!< 0x00000208 TX FIFO write */
+ __IM uint32_t RESERVED6[61];
+ __IOM uint32_t RX_FIFO_CTL; /*!< 0x00000300 RX FIFO control */
+ __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000304 RX FIFO status */
+ __IM uint32_t RX_FIFO_RD; /*!< 0x00000308 RX FIFO read */
+ __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000030C RX FIFO silent read */
+ __IM uint32_t RESERVED7[764];
+ __IOM uint32_t INTR; /*!< 0x00000F00 Interrupt register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000F04 Interrupt set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000F08 Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x00000F0C Interrupt masked register */
+} I2S_V1_Type; /*!< Size = 3856 (0xF10) */
+
+
+/* I2S.CTL */
+#define I2S_CTL_TX_ENABLED_Pos 30UL
+#define I2S_CTL_TX_ENABLED_Msk 0x40000000UL
+#define I2S_CTL_RX_ENABLED_Pos 31UL
+#define I2S_CTL_RX_ENABLED_Msk 0x80000000UL
+/* I2S.CLOCK_CTL */
+#define I2S_CLOCK_CTL_CLOCK_DIV_Pos 0UL
+#define I2S_CLOCK_CTL_CLOCK_DIV_Msk 0x3FUL
+#define I2S_CLOCK_CTL_CLOCK_SEL_Pos 8UL
+#define I2S_CLOCK_CTL_CLOCK_SEL_Msk 0x100UL
+/* I2S.CMD */
+#define I2S_CMD_TX_START_Pos 0UL
+#define I2S_CMD_TX_START_Msk 0x1UL
+#define I2S_CMD_TX_PAUSE_Pos 8UL
+#define I2S_CMD_TX_PAUSE_Msk 0x100UL
+#define I2S_CMD_RX_START_Pos 16UL
+#define I2S_CMD_RX_START_Msk 0x10000UL
+/* I2S.TR_CTL */
+#define I2S_TR_CTL_TX_REQ_EN_Pos 0UL
+#define I2S_TR_CTL_TX_REQ_EN_Msk 0x1UL
+#define I2S_TR_CTL_RX_REQ_EN_Pos 16UL
+#define I2S_TR_CTL_RX_REQ_EN_Msk 0x10000UL
+/* I2S.TX_CTL */
+#define I2S_TX_CTL_B_CLOCK_INV_Pos 3UL
+#define I2S_TX_CTL_B_CLOCK_INV_Msk 0x8UL
+#define I2S_TX_CTL_CH_NR_Pos 4UL
+#define I2S_TX_CTL_CH_NR_Msk 0x70UL
+#define I2S_TX_CTL_MS_Pos 7UL
+#define I2S_TX_CTL_MS_Msk 0x80UL
+#define I2S_TX_CTL_I2S_MODE_Pos 8UL
+#define I2S_TX_CTL_I2S_MODE_Msk 0x300UL
+#define I2S_TX_CTL_WS_PULSE_Pos 10UL
+#define I2S_TX_CTL_WS_PULSE_Msk 0x400UL
+#define I2S_TX_CTL_OVHDATA_Pos 12UL
+#define I2S_TX_CTL_OVHDATA_Msk 0x1000UL
+#define I2S_TX_CTL_WD_EN_Pos 13UL
+#define I2S_TX_CTL_WD_EN_Msk 0x2000UL
+#define I2S_TX_CTL_CH_LEN_Pos 16UL
+#define I2S_TX_CTL_CH_LEN_Msk 0x70000UL
+#define I2S_TX_CTL_WORD_LEN_Pos 20UL
+#define I2S_TX_CTL_WORD_LEN_Msk 0x700000UL
+#define I2S_TX_CTL_SCKO_POL_Pos 24UL
+#define I2S_TX_CTL_SCKO_POL_Msk 0x1000000UL
+#define I2S_TX_CTL_SCKI_POL_Pos 25UL
+#define I2S_TX_CTL_SCKI_POL_Msk 0x2000000UL
+/* I2S.TX_WATCHDOG */
+#define I2S_TX_WATCHDOG_WD_COUNTER_Pos 0UL
+#define I2S_TX_WATCHDOG_WD_COUNTER_Msk 0xFFFFFFFFUL
+/* I2S.RX_CTL */
+#define I2S_RX_CTL_B_CLOCK_INV_Pos 3UL
+#define I2S_RX_CTL_B_CLOCK_INV_Msk 0x8UL
+#define I2S_RX_CTL_CH_NR_Pos 4UL
+#define I2S_RX_CTL_CH_NR_Msk 0x70UL
+#define I2S_RX_CTL_MS_Pos 7UL
+#define I2S_RX_CTL_MS_Msk 0x80UL
+#define I2S_RX_CTL_I2S_MODE_Pos 8UL
+#define I2S_RX_CTL_I2S_MODE_Msk 0x300UL
+#define I2S_RX_CTL_WS_PULSE_Pos 10UL
+#define I2S_RX_CTL_WS_PULSE_Msk 0x400UL
+#define I2S_RX_CTL_WD_EN_Pos 13UL
+#define I2S_RX_CTL_WD_EN_Msk 0x2000UL
+#define I2S_RX_CTL_CH_LEN_Pos 16UL
+#define I2S_RX_CTL_CH_LEN_Msk 0x70000UL
+#define I2S_RX_CTL_WORD_LEN_Pos 20UL
+#define I2S_RX_CTL_WORD_LEN_Msk 0x700000UL
+#define I2S_RX_CTL_BIT_EXTENSION_Pos 23UL
+#define I2S_RX_CTL_BIT_EXTENSION_Msk 0x800000UL
+#define I2S_RX_CTL_SCKO_POL_Pos 24UL
+#define I2S_RX_CTL_SCKO_POL_Msk 0x1000000UL
+#define I2S_RX_CTL_SCKI_POL_Pos 25UL
+#define I2S_RX_CTL_SCKI_POL_Msk 0x2000000UL
+/* I2S.RX_WATCHDOG */
+#define I2S_RX_WATCHDOG_WD_COUNTER_Pos 0UL
+#define I2S_RX_WATCHDOG_WD_COUNTER_Msk 0xFFFFFFFFUL
+/* I2S.TX_FIFO_CTL */
+#define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
+#define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
+#define I2S_TX_FIFO_CTL_CLEAR_Pos 16UL
+#define I2S_TX_FIFO_CTL_CLEAR_Msk 0x10000UL
+#define I2S_TX_FIFO_CTL_FREEZE_Pos 17UL
+#define I2S_TX_FIFO_CTL_FREEZE_Msk 0x20000UL
+/* I2S.TX_FIFO_STATUS */
+#define I2S_TX_FIFO_STATUS_USED_Pos 0UL
+#define I2S_TX_FIFO_STATUS_USED_Msk 0x1FFUL
+#define I2S_TX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define I2S_TX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
+#define I2S_TX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define I2S_TX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
+/* I2S.TX_FIFO_WR */
+#define I2S_TX_FIFO_WR_DATA_Pos 0UL
+#define I2S_TX_FIFO_WR_DATA_Msk 0xFFFFFFFFUL
+/* I2S.RX_FIFO_CTL */
+#define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
+#define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
+#define I2S_RX_FIFO_CTL_CLEAR_Pos 16UL
+#define I2S_RX_FIFO_CTL_CLEAR_Msk 0x10000UL
+#define I2S_RX_FIFO_CTL_FREEZE_Pos 17UL
+#define I2S_RX_FIFO_CTL_FREEZE_Msk 0x20000UL
+/* I2S.RX_FIFO_STATUS */
+#define I2S_RX_FIFO_STATUS_USED_Pos 0UL
+#define I2S_RX_FIFO_STATUS_USED_Msk 0x1FFUL
+#define I2S_RX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define I2S_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
+#define I2S_RX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define I2S_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
+/* I2S.RX_FIFO_RD */
+#define I2S_RX_FIFO_RD_DATA_Pos 0UL
+#define I2S_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL
+/* I2S.RX_FIFO_RD_SILENT */
+#define I2S_RX_FIFO_RD_SILENT_DATA_Pos 0UL
+#define I2S_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL
+/* I2S.INTR */
+#define I2S_INTR_TX_TRIGGER_Pos 0UL
+#define I2S_INTR_TX_TRIGGER_Msk 0x1UL
+#define I2S_INTR_TX_NOT_FULL_Pos 1UL
+#define I2S_INTR_TX_NOT_FULL_Msk 0x2UL
+#define I2S_INTR_TX_EMPTY_Pos 4UL
+#define I2S_INTR_TX_EMPTY_Msk 0x10UL
+#define I2S_INTR_TX_OVERFLOW_Pos 5UL
+#define I2S_INTR_TX_OVERFLOW_Msk 0x20UL
+#define I2S_INTR_TX_UNDERFLOW_Pos 6UL
+#define I2S_INTR_TX_UNDERFLOW_Msk 0x40UL
+#define I2S_INTR_TX_WD_Pos 8UL
+#define I2S_INTR_TX_WD_Msk 0x100UL
+#define I2S_INTR_RX_TRIGGER_Pos 16UL
+#define I2S_INTR_RX_TRIGGER_Msk 0x10000UL
+#define I2S_INTR_RX_NOT_EMPTY_Pos 18UL
+#define I2S_INTR_RX_NOT_EMPTY_Msk 0x40000UL
+#define I2S_INTR_RX_FULL_Pos 19UL
+#define I2S_INTR_RX_FULL_Msk 0x80000UL
+#define I2S_INTR_RX_OVERFLOW_Pos 21UL
+#define I2S_INTR_RX_OVERFLOW_Msk 0x200000UL
+#define I2S_INTR_RX_UNDERFLOW_Pos 22UL
+#define I2S_INTR_RX_UNDERFLOW_Msk 0x400000UL
+#define I2S_INTR_RX_WD_Pos 24UL
+#define I2S_INTR_RX_WD_Msk 0x1000000UL
+/* I2S.INTR_SET */
+#define I2S_INTR_SET_TX_TRIGGER_Pos 0UL
+#define I2S_INTR_SET_TX_TRIGGER_Msk 0x1UL
+#define I2S_INTR_SET_TX_NOT_FULL_Pos 1UL
+#define I2S_INTR_SET_TX_NOT_FULL_Msk 0x2UL
+#define I2S_INTR_SET_TX_EMPTY_Pos 4UL
+#define I2S_INTR_SET_TX_EMPTY_Msk 0x10UL
+#define I2S_INTR_SET_TX_OVERFLOW_Pos 5UL
+#define I2S_INTR_SET_TX_OVERFLOW_Msk 0x20UL
+#define I2S_INTR_SET_TX_UNDERFLOW_Pos 6UL
+#define I2S_INTR_SET_TX_UNDERFLOW_Msk 0x40UL
+#define I2S_INTR_SET_TX_WD_Pos 8UL
+#define I2S_INTR_SET_TX_WD_Msk 0x100UL
+#define I2S_INTR_SET_RX_TRIGGER_Pos 16UL
+#define I2S_INTR_SET_RX_TRIGGER_Msk 0x10000UL
+#define I2S_INTR_SET_RX_NOT_EMPTY_Pos 18UL
+#define I2S_INTR_SET_RX_NOT_EMPTY_Msk 0x40000UL
+#define I2S_INTR_SET_RX_FULL_Pos 19UL
+#define I2S_INTR_SET_RX_FULL_Msk 0x80000UL
+#define I2S_INTR_SET_RX_OVERFLOW_Pos 21UL
+#define I2S_INTR_SET_RX_OVERFLOW_Msk 0x200000UL
+#define I2S_INTR_SET_RX_UNDERFLOW_Pos 22UL
+#define I2S_INTR_SET_RX_UNDERFLOW_Msk 0x400000UL
+#define I2S_INTR_SET_RX_WD_Pos 24UL
+#define I2S_INTR_SET_RX_WD_Msk 0x1000000UL
+/* I2S.INTR_MASK */
+#define I2S_INTR_MASK_TX_TRIGGER_Pos 0UL
+#define I2S_INTR_MASK_TX_TRIGGER_Msk 0x1UL
+#define I2S_INTR_MASK_TX_NOT_FULL_Pos 1UL
+#define I2S_INTR_MASK_TX_NOT_FULL_Msk 0x2UL
+#define I2S_INTR_MASK_TX_EMPTY_Pos 4UL
+#define I2S_INTR_MASK_TX_EMPTY_Msk 0x10UL
+#define I2S_INTR_MASK_TX_OVERFLOW_Pos 5UL
+#define I2S_INTR_MASK_TX_OVERFLOW_Msk 0x20UL
+#define I2S_INTR_MASK_TX_UNDERFLOW_Pos 6UL
+#define I2S_INTR_MASK_TX_UNDERFLOW_Msk 0x40UL
+#define I2S_INTR_MASK_TX_WD_Pos 8UL
+#define I2S_INTR_MASK_TX_WD_Msk 0x100UL
+#define I2S_INTR_MASK_RX_TRIGGER_Pos 16UL
+#define I2S_INTR_MASK_RX_TRIGGER_Msk 0x10000UL
+#define I2S_INTR_MASK_RX_NOT_EMPTY_Pos 18UL
+#define I2S_INTR_MASK_RX_NOT_EMPTY_Msk 0x40000UL
+#define I2S_INTR_MASK_RX_FULL_Pos 19UL
+#define I2S_INTR_MASK_RX_FULL_Msk 0x80000UL
+#define I2S_INTR_MASK_RX_OVERFLOW_Pos 21UL
+#define I2S_INTR_MASK_RX_OVERFLOW_Msk 0x200000UL
+#define I2S_INTR_MASK_RX_UNDERFLOW_Pos 22UL
+#define I2S_INTR_MASK_RX_UNDERFLOW_Msk 0x400000UL
+#define I2S_INTR_MASK_RX_WD_Pos 24UL
+#define I2S_INTR_MASK_RX_WD_Msk 0x1000000UL
+/* I2S.INTR_MASKED */
+#define I2S_INTR_MASKED_TX_TRIGGER_Pos 0UL
+#define I2S_INTR_MASKED_TX_TRIGGER_Msk 0x1UL
+#define I2S_INTR_MASKED_TX_NOT_FULL_Pos 1UL
+#define I2S_INTR_MASKED_TX_NOT_FULL_Msk 0x2UL
+#define I2S_INTR_MASKED_TX_EMPTY_Pos 4UL
+#define I2S_INTR_MASKED_TX_EMPTY_Msk 0x10UL
+#define I2S_INTR_MASKED_TX_OVERFLOW_Pos 5UL
+#define I2S_INTR_MASKED_TX_OVERFLOW_Msk 0x20UL
+#define I2S_INTR_MASKED_TX_UNDERFLOW_Pos 6UL
+#define I2S_INTR_MASKED_TX_UNDERFLOW_Msk 0x40UL
+#define I2S_INTR_MASKED_TX_WD_Pos 8UL
+#define I2S_INTR_MASKED_TX_WD_Msk 0x100UL
+#define I2S_INTR_MASKED_RX_TRIGGER_Pos 16UL
+#define I2S_INTR_MASKED_RX_TRIGGER_Msk 0x10000UL
+#define I2S_INTR_MASKED_RX_NOT_EMPTY_Pos 18UL
+#define I2S_INTR_MASKED_RX_NOT_EMPTY_Msk 0x40000UL
+#define I2S_INTR_MASKED_RX_FULL_Pos 19UL
+#define I2S_INTR_MASKED_RX_FULL_Msk 0x80000UL
+#define I2S_INTR_MASKED_RX_OVERFLOW_Pos 21UL
+#define I2S_INTR_MASKED_RX_OVERFLOW_Msk 0x200000UL
+#define I2S_INTR_MASKED_RX_UNDERFLOW_Pos 22UL
+#define I2S_INTR_MASKED_RX_UNDERFLOW_Msk 0x400000UL
+#define I2S_INTR_MASKED_RX_WD_Pos 24UL
+#define I2S_INTR_MASKED_RX_WD_Msk 0x1000000UL
+
+
+#endif /* _CYIP_I2S_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_ipc.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_ipc.h
new file mode 100644
index 0000000000..c2e5d58e8c
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_ipc.h
@@ -0,0 +1,132 @@
+/***************************************************************************//**
+* \file cyip_ipc.h
+*
+* \brief
+* IPC IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_IPC_H_
+#define _CYIP_IPC_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* IPC
+*******************************************************************************/
+
+#define IPC_STRUCT_SECTION_SIZE 0x00000020UL
+#define IPC_INTR_STRUCT_SECTION_SIZE 0x00000020UL
+#define IPC_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief IPC structure (IPC_STRUCT)
+ */
+typedef struct {
+ __IM uint32_t ACQUIRE; /*!< 0x00000000 IPC acquire */
+ __OM uint32_t RELEASE; /*!< 0x00000004 IPC release */
+ __OM uint32_t NOTIFY; /*!< 0x00000008 IPC notification */
+ __IOM uint32_t DATA; /*!< 0x0000000C IPC data */
+ __IM uint32_t LOCK_STATUS; /*!< 0x00000010 IPC lock status */
+ __IM uint32_t RESERVED[3];
+} IPC_STRUCT_V1_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief IPC interrupt structure (IPC_INTR_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t INTR; /*!< 0x00000000 Interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x00000004 Interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000008 Interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000000C Interrupt masked */
+ __IM uint32_t RESERVED[4];
+} IPC_INTR_STRUCT_V1_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief IPC (IPC)
+ */
+typedef struct {
+ IPC_STRUCT_V1_Type STRUCT[16]; /*!< 0x00000000 IPC structure */
+ __IM uint32_t RESERVED[896];
+ IPC_INTR_STRUCT_V1_Type INTR_STRUCT[16]; /*!< 0x00001000 IPC interrupt structure */
+} IPC_V1_Type; /*!< Size = 4608 (0x1200) */
+
+
+/* IPC_STRUCT.ACQUIRE */
+#define IPC_STRUCT_ACQUIRE_P_Pos 0UL
+#define IPC_STRUCT_ACQUIRE_P_Msk 0x1UL
+#define IPC_STRUCT_ACQUIRE_NS_Pos 1UL
+#define IPC_STRUCT_ACQUIRE_NS_Msk 0x2UL
+#define IPC_STRUCT_ACQUIRE_PC_Pos 4UL
+#define IPC_STRUCT_ACQUIRE_PC_Msk 0xF0UL
+#define IPC_STRUCT_ACQUIRE_MS_Pos 8UL
+#define IPC_STRUCT_ACQUIRE_MS_Msk 0xF00UL
+#define IPC_STRUCT_ACQUIRE_SUCCESS_Pos 31UL
+#define IPC_STRUCT_ACQUIRE_SUCCESS_Msk 0x80000000UL
+/* IPC_STRUCT.RELEASE */
+#define IPC_STRUCT_RELEASE_INTR_RELEASE_Pos 0UL
+#define IPC_STRUCT_RELEASE_INTR_RELEASE_Msk 0xFFFFUL
+/* IPC_STRUCT.NOTIFY */
+#define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Pos 0UL
+#define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk 0xFFFFUL
+/* IPC_STRUCT.DATA */
+#define IPC_STRUCT_DATA_DATA_Pos 0UL
+#define IPC_STRUCT_DATA_DATA_Msk 0xFFFFFFFFUL
+/* IPC_STRUCT.LOCK_STATUS */
+#define IPC_STRUCT_LOCK_STATUS_P_Pos 0UL
+#define IPC_STRUCT_LOCK_STATUS_P_Msk 0x1UL
+#define IPC_STRUCT_LOCK_STATUS_NS_Pos 1UL
+#define IPC_STRUCT_LOCK_STATUS_NS_Msk 0x2UL
+#define IPC_STRUCT_LOCK_STATUS_PC_Pos 4UL
+#define IPC_STRUCT_LOCK_STATUS_PC_Msk 0xF0UL
+#define IPC_STRUCT_LOCK_STATUS_MS_Pos 8UL
+#define IPC_STRUCT_LOCK_STATUS_MS_Msk 0xF00UL
+#define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Pos 31UL
+#define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Msk 0x80000000UL
+
+
+/* IPC_INTR_STRUCT.INTR */
+#define IPC_INTR_STRUCT_INTR_RELEASE_Pos 0UL
+#define IPC_INTR_STRUCT_INTR_RELEASE_Msk 0xFFFFUL
+#define IPC_INTR_STRUCT_INTR_NOTIFY_Pos 16UL
+#define IPC_INTR_STRUCT_INTR_NOTIFY_Msk 0xFFFF0000UL
+/* IPC_INTR_STRUCT.INTR_SET */
+#define IPC_INTR_STRUCT_INTR_SET_RELEASE_Pos 0UL
+#define IPC_INTR_STRUCT_INTR_SET_RELEASE_Msk 0xFFFFUL
+#define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Pos 16UL
+#define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Msk 0xFFFF0000UL
+/* IPC_INTR_STRUCT.INTR_MASK */
+#define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Pos 0UL
+#define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk 0xFFFFUL
+#define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Pos 16UL
+#define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Msk 0xFFFF0000UL
+/* IPC_INTR_STRUCT.INTR_MASKED */
+#define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Pos 0UL
+#define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Msk 0xFFFFUL
+#define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Pos 16UL
+#define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Msk 0xFFFF0000UL
+
+
+#endif /* _CYIP_IPC_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_ipc_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_ipc_v2.h
new file mode 100644
index 0000000000..5869a9c92b
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_ipc_v2.h
@@ -0,0 +1,136 @@
+/***************************************************************************//**
+* \file cyip_ipc_v2.h
+*
+* \brief
+* IPC IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_IPC_V2_H_
+#define _CYIP_IPC_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* IPC
+*******************************************************************************/
+
+#define IPC_STRUCT_V2_SECTION_SIZE 0x00000020UL
+#define IPC_INTR_STRUCT_V2_SECTION_SIZE 0x00000020UL
+#define IPC_V2_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief IPC structure (IPC_STRUCT)
+ */
+typedef struct {
+ __IM uint32_t ACQUIRE; /*!< 0x00000000 IPC acquire */
+ __OM uint32_t RELEASE; /*!< 0x00000004 IPC release */
+ __OM uint32_t NOTIFY; /*!< 0x00000008 IPC notification */
+ __IOM uint32_t DATA0; /*!< 0x0000000C IPC data 0 */
+ __IOM uint32_t DATA1; /*!< 0x00000010 IPC data 1 */
+ __IM uint32_t RESERVED[2];
+ __IM uint32_t LOCK_STATUS; /*!< 0x0000001C IPC lock status */
+} IPC_STRUCT_V2_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief IPC interrupt structure (IPC_INTR_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t INTR; /*!< 0x00000000 Interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x00000004 Interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000008 Interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000000C Interrupt masked */
+ __IM uint32_t RESERVED[4];
+} IPC_INTR_STRUCT_V2_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief IPC (IPC)
+ */
+typedef struct {
+ IPC_STRUCT_V2_Type STRUCT[16]; /*!< 0x00000000 IPC structure */
+ __IM uint32_t RESERVED[896];
+ IPC_INTR_STRUCT_V2_Type INTR_STRUCT[16]; /*!< 0x00001000 IPC interrupt structure */
+} IPC_V2_Type; /*!< Size = 4608 (0x1200) */
+
+
+/* IPC_STRUCT.ACQUIRE */
+#define IPC_STRUCT_V2_ACQUIRE_P_Pos 0UL
+#define IPC_STRUCT_V2_ACQUIRE_P_Msk 0x1UL
+#define IPC_STRUCT_V2_ACQUIRE_NS_Pos 1UL
+#define IPC_STRUCT_V2_ACQUIRE_NS_Msk 0x2UL
+#define IPC_STRUCT_V2_ACQUIRE_PC_Pos 4UL
+#define IPC_STRUCT_V2_ACQUIRE_PC_Msk 0xF0UL
+#define IPC_STRUCT_V2_ACQUIRE_MS_Pos 8UL
+#define IPC_STRUCT_V2_ACQUIRE_MS_Msk 0xF00UL
+#define IPC_STRUCT_V2_ACQUIRE_SUCCESS_Pos 31UL
+#define IPC_STRUCT_V2_ACQUIRE_SUCCESS_Msk 0x80000000UL
+/* IPC_STRUCT.RELEASE */
+#define IPC_STRUCT_V2_RELEASE_INTR_RELEASE_Pos 0UL
+#define IPC_STRUCT_V2_RELEASE_INTR_RELEASE_Msk 0xFFFFUL
+/* IPC_STRUCT.NOTIFY */
+#define IPC_STRUCT_V2_NOTIFY_INTR_NOTIFY_Pos 0UL
+#define IPC_STRUCT_V2_NOTIFY_INTR_NOTIFY_Msk 0xFFFFUL
+/* IPC_STRUCT.DATA0 */
+#define IPC_STRUCT_V2_DATA0_DATA_Pos 0UL
+#define IPC_STRUCT_V2_DATA0_DATA_Msk 0xFFFFFFFFUL
+/* IPC_STRUCT.DATA1 */
+#define IPC_STRUCT_V2_DATA1_DATA_Pos 0UL
+#define IPC_STRUCT_V2_DATA1_DATA_Msk 0xFFFFFFFFUL
+/* IPC_STRUCT.LOCK_STATUS */
+#define IPC_STRUCT_V2_LOCK_STATUS_P_Pos 0UL
+#define IPC_STRUCT_V2_LOCK_STATUS_P_Msk 0x1UL
+#define IPC_STRUCT_V2_LOCK_STATUS_NS_Pos 1UL
+#define IPC_STRUCT_V2_LOCK_STATUS_NS_Msk 0x2UL
+#define IPC_STRUCT_V2_LOCK_STATUS_PC_Pos 4UL
+#define IPC_STRUCT_V2_LOCK_STATUS_PC_Msk 0xF0UL
+#define IPC_STRUCT_V2_LOCK_STATUS_MS_Pos 8UL
+#define IPC_STRUCT_V2_LOCK_STATUS_MS_Msk 0xF00UL
+#define IPC_STRUCT_V2_LOCK_STATUS_ACQUIRED_Pos 31UL
+#define IPC_STRUCT_V2_LOCK_STATUS_ACQUIRED_Msk 0x80000000UL
+
+
+/* IPC_INTR_STRUCT.INTR */
+#define IPC_INTR_STRUCT_V2_INTR_RELEASE_Pos 0UL
+#define IPC_INTR_STRUCT_V2_INTR_RELEASE_Msk 0xFFFFUL
+#define IPC_INTR_STRUCT_V2_INTR_NOTIFY_Pos 16UL
+#define IPC_INTR_STRUCT_V2_INTR_NOTIFY_Msk 0xFFFF0000UL
+/* IPC_INTR_STRUCT.INTR_SET */
+#define IPC_INTR_STRUCT_V2_INTR_SET_RELEASE_Pos 0UL
+#define IPC_INTR_STRUCT_V2_INTR_SET_RELEASE_Msk 0xFFFFUL
+#define IPC_INTR_STRUCT_V2_INTR_SET_NOTIFY_Pos 16UL
+#define IPC_INTR_STRUCT_V2_INTR_SET_NOTIFY_Msk 0xFFFF0000UL
+/* IPC_INTR_STRUCT.INTR_MASK */
+#define IPC_INTR_STRUCT_V2_INTR_MASK_RELEASE_Pos 0UL
+#define IPC_INTR_STRUCT_V2_INTR_MASK_RELEASE_Msk 0xFFFFUL
+#define IPC_INTR_STRUCT_V2_INTR_MASK_NOTIFY_Pos 16UL
+#define IPC_INTR_STRUCT_V2_INTR_MASK_NOTIFY_Msk 0xFFFF0000UL
+/* IPC_INTR_STRUCT.INTR_MASKED */
+#define IPC_INTR_STRUCT_V2_INTR_MASKED_RELEASE_Pos 0UL
+#define IPC_INTR_STRUCT_V2_INTR_MASKED_RELEASE_Msk 0xFFFFUL
+#define IPC_INTR_STRUCT_V2_INTR_MASKED_NOTIFY_Pos 16UL
+#define IPC_INTR_STRUCT_V2_INTR_MASKED_NOTIFY_Msk 0xFFFF0000UL
+
+
+#endif /* _CYIP_IPC_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_lcd.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_lcd.h
new file mode 100644
index 0000000000..241e5b0b58
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_lcd.h
@@ -0,0 +1,101 @@
+/***************************************************************************//**
+* \file cyip_lcd.h
+*
+* \brief
+* LCD IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_LCD_H_
+#define _CYIP_LCD_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* LCD
+*******************************************************************************/
+
+#define LCD_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief LCD Controller Block (LCD)
+ */
+typedef struct {
+ __IM uint32_t ID; /*!< 0x00000000 ID & Revision */
+ __IOM uint32_t DIVIDER; /*!< 0x00000004 LCD Divider Register */
+ __IOM uint32_t CONTROL; /*!< 0x00000008 LCD Configuration Register */
+ __IM uint32_t RESERVED[61];
+ __IOM uint32_t DATA0[8]; /*!< 0x00000100 LCD Pin Data Registers */
+ __IM uint32_t RESERVED1[56];
+ __IOM uint32_t DATA1[8]; /*!< 0x00000200 LCD Pin Data Registers */
+ __IM uint32_t RESERVED2[56];
+ __IOM uint32_t DATA2[8]; /*!< 0x00000300 LCD Pin Data Registers */
+ __IM uint32_t RESERVED3[56];
+ __IOM uint32_t DATA3[8]; /*!< 0x00000400 LCD Pin Data Registers */
+} LCD_V1_Type; /*!< Size = 1056 (0x420) */
+
+
+/* LCD.ID */
+#define LCD_ID_ID_Pos 0UL
+#define LCD_ID_ID_Msk 0xFFFFUL
+#define LCD_ID_REVISION_Pos 16UL
+#define LCD_ID_REVISION_Msk 0xFFFF0000UL
+/* LCD.DIVIDER */
+#define LCD_DIVIDER_SUBFR_DIV_Pos 0UL
+#define LCD_DIVIDER_SUBFR_DIV_Msk 0xFFFFUL
+#define LCD_DIVIDER_DEAD_DIV_Pos 16UL
+#define LCD_DIVIDER_DEAD_DIV_Msk 0xFFFF0000UL
+/* LCD.CONTROL */
+#define LCD_CONTROL_LS_EN_Pos 0UL
+#define LCD_CONTROL_LS_EN_Msk 0x1UL
+#define LCD_CONTROL_HS_EN_Pos 1UL
+#define LCD_CONTROL_HS_EN_Msk 0x2UL
+#define LCD_CONTROL_LCD_MODE_Pos 2UL
+#define LCD_CONTROL_LCD_MODE_Msk 0x4UL
+#define LCD_CONTROL_TYPE_Pos 3UL
+#define LCD_CONTROL_TYPE_Msk 0x8UL
+#define LCD_CONTROL_OP_MODE_Pos 4UL
+#define LCD_CONTROL_OP_MODE_Msk 0x10UL
+#define LCD_CONTROL_BIAS_Pos 5UL
+#define LCD_CONTROL_BIAS_Msk 0x60UL
+#define LCD_CONTROL_COM_NUM_Pos 8UL
+#define LCD_CONTROL_COM_NUM_Msk 0xF00UL
+#define LCD_CONTROL_LS_EN_STAT_Pos 31UL
+#define LCD_CONTROL_LS_EN_STAT_Msk 0x80000000UL
+/* LCD.DATA0 */
+#define LCD_DATA0_DATA_Pos 0UL
+#define LCD_DATA0_DATA_Msk 0xFFFFFFFFUL
+/* LCD.DATA1 */
+#define LCD_DATA1_DATA_Pos 0UL
+#define LCD_DATA1_DATA_Msk 0xFFFFFFFFUL
+/* LCD.DATA2 */
+#define LCD_DATA2_DATA_Pos 0UL
+#define LCD_DATA2_DATA_Msk 0xFFFFFFFFUL
+/* LCD.DATA3 */
+#define LCD_DATA3_DATA_Pos 0UL
+#define LCD_DATA3_DATA_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_LCD_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_lcd_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_lcd_v2.h
new file mode 100644
index 0000000000..e7d5e17402
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_lcd_v2.h
@@ -0,0 +1,103 @@
+/***************************************************************************//**
+* \file cyip_lcd_v2.h
+*
+* \brief
+* LCD IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_LCD_V2_H_
+#define _CYIP_LCD_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* LCD
+*******************************************************************************/
+
+#define LCD_V2_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief LCD Controller Block (LCD)
+ */
+typedef struct {
+ __IM uint32_t ID; /*!< 0x00000000 ID & Revision */
+ __IOM uint32_t DIVIDER; /*!< 0x00000004 LCD Divider Register */
+ __IOM uint32_t CONTROL; /*!< 0x00000008 LCD Configuration Register */
+ __IM uint32_t RESERVED[61];
+ __IOM uint32_t DATA0[8]; /*!< 0x00000100 LCD Pin Data Registers */
+ __IM uint32_t RESERVED1[56];
+ __IOM uint32_t DATA1[8]; /*!< 0x00000200 LCD Pin Data Registers */
+ __IM uint32_t RESERVED2[56];
+ __IOM uint32_t DATA2[8]; /*!< 0x00000300 LCD Pin Data Registers */
+ __IM uint32_t RESERVED3[56];
+ __IOM uint32_t DATA3[8]; /*!< 0x00000400 LCD Pin Data Registers */
+} LCD_V2_Type; /*!< Size = 1056 (0x420) */
+
+
+/* LCD.ID */
+#define LCD_V2_ID_ID_Pos 0UL
+#define LCD_V2_ID_ID_Msk 0xFFFFUL
+#define LCD_V2_ID_REVISION_Pos 16UL
+#define LCD_V2_ID_REVISION_Msk 0xFFFF0000UL
+/* LCD.DIVIDER */
+#define LCD_V2_DIVIDER_SUBFR_DIV_Pos 0UL
+#define LCD_V2_DIVIDER_SUBFR_DIV_Msk 0xFFFFUL
+#define LCD_V2_DIVIDER_DEAD_DIV_Pos 16UL
+#define LCD_V2_DIVIDER_DEAD_DIV_Msk 0xFFFF0000UL
+/* LCD.CONTROL */
+#define LCD_V2_CONTROL_LS_EN_Pos 0UL
+#define LCD_V2_CONTROL_LS_EN_Msk 0x1UL
+#define LCD_V2_CONTROL_HS_EN_Pos 1UL
+#define LCD_V2_CONTROL_HS_EN_Msk 0x2UL
+#define LCD_V2_CONTROL_LCD_MODE_Pos 2UL
+#define LCD_V2_CONTROL_LCD_MODE_Msk 0x4UL
+#define LCD_V2_CONTROL_TYPE_Pos 3UL
+#define LCD_V2_CONTROL_TYPE_Msk 0x8UL
+#define LCD_V2_CONTROL_OP_MODE_Pos 4UL
+#define LCD_V2_CONTROL_OP_MODE_Msk 0x10UL
+#define LCD_V2_CONTROL_BIAS_Pos 5UL
+#define LCD_V2_CONTROL_BIAS_Msk 0x60UL
+#define LCD_V2_CONTROL_CLOCK_LS_SEL_Pos 7UL
+#define LCD_V2_CONTROL_CLOCK_LS_SEL_Msk 0x80UL
+#define LCD_V2_CONTROL_COM_NUM_Pos 8UL
+#define LCD_V2_CONTROL_COM_NUM_Msk 0xF00UL
+#define LCD_V2_CONTROL_LS_EN_STAT_Pos 31UL
+#define LCD_V2_CONTROL_LS_EN_STAT_Msk 0x80000000UL
+/* LCD.DATA0 */
+#define LCD_V2_DATA0_DATA_Pos 0UL
+#define LCD_V2_DATA0_DATA_Msk 0xFFFFFFFFUL
+/* LCD.DATA1 */
+#define LCD_V2_DATA1_DATA_Pos 0UL
+#define LCD_V2_DATA1_DATA_Msk 0xFFFFFFFFUL
+/* LCD.DATA2 */
+#define LCD_V2_DATA2_DATA_Pos 0UL
+#define LCD_V2_DATA2_DATA_Msk 0xFFFFFFFFUL
+/* LCD.DATA3 */
+#define LCD_V2_DATA3_DATA_Pos 0UL
+#define LCD_V2_DATA3_DATA_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_LCD_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_lpcomp.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_lpcomp.h
new file mode 100644
index 0000000000..68b92eab75
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_lpcomp.h
@@ -0,0 +1,180 @@
+/***************************************************************************//**
+* \file cyip_lpcomp.h
+*
+* \brief
+* LPCOMP IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_LPCOMP_H_
+#define _CYIP_LPCOMP_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* LPCOMP
+*******************************************************************************/
+
+#define LPCOMP_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Low Power Comparators (LPCOMP)
+ */
+typedef struct {
+ __IOM uint32_t CONFIG; /*!< 0x00000000 LPCOMP Configuration Register */
+ __IM uint32_t STATUS; /*!< 0x00000004 LPCOMP Status Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t INTR; /*!< 0x00000010 LPCOMP Interrupt request register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000014 LPCOMP Interrupt set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000018 LPCOMP Interrupt request mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000001C LPCOMP Interrupt request masked */
+ __IM uint32_t RESERVED1[8];
+ __IOM uint32_t CMP0_CTRL; /*!< 0x00000040 Comparator 0 control Register */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t CMP0_SW; /*!< 0x00000050 Comparator 0 switch control */
+ __IOM uint32_t CMP0_SW_CLEAR; /*!< 0x00000054 Comparator 0 switch control clear */
+ __IM uint32_t RESERVED3[10];
+ __IOM uint32_t CMP1_CTRL; /*!< 0x00000080 Comparator 1 control Register */
+ __IM uint32_t RESERVED4[3];
+ __IOM uint32_t CMP1_SW; /*!< 0x00000090 Comparator 1 switch control */
+ __IOM uint32_t CMP1_SW_CLEAR; /*!< 0x00000094 Comparator 1 switch control clear */
+} LPCOMP_V1_Type; /*!< Size = 152 (0x98) */
+
+
+/* LPCOMP.CONFIG */
+#define LPCOMP_CONFIG_LPREF_EN_Pos 30UL
+#define LPCOMP_CONFIG_LPREF_EN_Msk 0x40000000UL
+#define LPCOMP_CONFIG_ENABLED_Pos 31UL
+#define LPCOMP_CONFIG_ENABLED_Msk 0x80000000UL
+/* LPCOMP.STATUS */
+#define LPCOMP_STATUS_OUT0_Pos 0UL
+#define LPCOMP_STATUS_OUT0_Msk 0x1UL
+#define LPCOMP_STATUS_OUT1_Pos 16UL
+#define LPCOMP_STATUS_OUT1_Msk 0x10000UL
+/* LPCOMP.INTR */
+#define LPCOMP_INTR_COMP0_Pos 0UL
+#define LPCOMP_INTR_COMP0_Msk 0x1UL
+#define LPCOMP_INTR_COMP1_Pos 1UL
+#define LPCOMP_INTR_COMP1_Msk 0x2UL
+/* LPCOMP.INTR_SET */
+#define LPCOMP_INTR_SET_COMP0_Pos 0UL
+#define LPCOMP_INTR_SET_COMP0_Msk 0x1UL
+#define LPCOMP_INTR_SET_COMP1_Pos 1UL
+#define LPCOMP_INTR_SET_COMP1_Msk 0x2UL
+/* LPCOMP.INTR_MASK */
+#define LPCOMP_INTR_MASK_COMP0_MASK_Pos 0UL
+#define LPCOMP_INTR_MASK_COMP0_MASK_Msk 0x1UL
+#define LPCOMP_INTR_MASK_COMP1_MASK_Pos 1UL
+#define LPCOMP_INTR_MASK_COMP1_MASK_Msk 0x2UL
+/* LPCOMP.INTR_MASKED */
+#define LPCOMP_INTR_MASKED_COMP0_MASKED_Pos 0UL
+#define LPCOMP_INTR_MASKED_COMP0_MASKED_Msk 0x1UL
+#define LPCOMP_INTR_MASKED_COMP1_MASKED_Pos 1UL
+#define LPCOMP_INTR_MASKED_COMP1_MASKED_Msk 0x2UL
+/* LPCOMP.CMP0_CTRL */
+#define LPCOMP_CMP0_CTRL_MODE0_Pos 0UL
+#define LPCOMP_CMP0_CTRL_MODE0_Msk 0x3UL
+#define LPCOMP_CMP0_CTRL_HYST0_Pos 5UL
+#define LPCOMP_CMP0_CTRL_HYST0_Msk 0x20UL
+#define LPCOMP_CMP0_CTRL_INTTYPE0_Pos 6UL
+#define LPCOMP_CMP0_CTRL_INTTYPE0_Msk 0xC0UL
+#define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Pos 10UL
+#define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Msk 0x400UL
+#define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Pos 11UL
+#define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Msk 0x800UL
+/* LPCOMP.CMP0_SW */
+#define LPCOMP_CMP0_SW_CMP0_IP0_Pos 0UL
+#define LPCOMP_CMP0_SW_CMP0_IP0_Msk 0x1UL
+#define LPCOMP_CMP0_SW_CMP0_AP0_Pos 1UL
+#define LPCOMP_CMP0_SW_CMP0_AP0_Msk 0x2UL
+#define LPCOMP_CMP0_SW_CMP0_BP0_Pos 2UL
+#define LPCOMP_CMP0_SW_CMP0_BP0_Msk 0x4UL
+#define LPCOMP_CMP0_SW_CMP0_IN0_Pos 4UL
+#define LPCOMP_CMP0_SW_CMP0_IN0_Msk 0x10UL
+#define LPCOMP_CMP0_SW_CMP0_AN0_Pos 5UL
+#define LPCOMP_CMP0_SW_CMP0_AN0_Msk 0x20UL
+#define LPCOMP_CMP0_SW_CMP0_BN0_Pos 6UL
+#define LPCOMP_CMP0_SW_CMP0_BN0_Msk 0x40UL
+#define LPCOMP_CMP0_SW_CMP0_VN0_Pos 7UL
+#define LPCOMP_CMP0_SW_CMP0_VN0_Msk 0x80UL
+/* LPCOMP.CMP0_SW_CLEAR */
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Pos 0UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Msk 0x1UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Pos 1UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Msk 0x2UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Pos 2UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Msk 0x4UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Pos 4UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Msk 0x10UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Pos 5UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Msk 0x20UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Pos 6UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Msk 0x40UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Pos 7UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Msk 0x80UL
+/* LPCOMP.CMP1_CTRL */
+#define LPCOMP_CMP1_CTRL_MODE1_Pos 0UL
+#define LPCOMP_CMP1_CTRL_MODE1_Msk 0x3UL
+#define LPCOMP_CMP1_CTRL_HYST1_Pos 5UL
+#define LPCOMP_CMP1_CTRL_HYST1_Msk 0x20UL
+#define LPCOMP_CMP1_CTRL_INTTYPE1_Pos 6UL
+#define LPCOMP_CMP1_CTRL_INTTYPE1_Msk 0xC0UL
+#define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Pos 10UL
+#define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Msk 0x400UL
+#define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Pos 11UL
+#define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Msk 0x800UL
+/* LPCOMP.CMP1_SW */
+#define LPCOMP_CMP1_SW_CMP1_IP1_Pos 0UL
+#define LPCOMP_CMP1_SW_CMP1_IP1_Msk 0x1UL
+#define LPCOMP_CMP1_SW_CMP1_AP1_Pos 1UL
+#define LPCOMP_CMP1_SW_CMP1_AP1_Msk 0x2UL
+#define LPCOMP_CMP1_SW_CMP1_BP1_Pos 2UL
+#define LPCOMP_CMP1_SW_CMP1_BP1_Msk 0x4UL
+#define LPCOMP_CMP1_SW_CMP1_IN1_Pos 4UL
+#define LPCOMP_CMP1_SW_CMP1_IN1_Msk 0x10UL
+#define LPCOMP_CMP1_SW_CMP1_AN1_Pos 5UL
+#define LPCOMP_CMP1_SW_CMP1_AN1_Msk 0x20UL
+#define LPCOMP_CMP1_SW_CMP1_BN1_Pos 6UL
+#define LPCOMP_CMP1_SW_CMP1_BN1_Msk 0x40UL
+#define LPCOMP_CMP1_SW_CMP1_VN1_Pos 7UL
+#define LPCOMP_CMP1_SW_CMP1_VN1_Msk 0x80UL
+/* LPCOMP.CMP1_SW_CLEAR */
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Pos 0UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Msk 0x1UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Pos 1UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Msk 0x2UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Pos 2UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Msk 0x4UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Pos 4UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Msk 0x10UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Pos 5UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Msk 0x20UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Pos 6UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Msk 0x40UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Pos 7UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Msk 0x80UL
+
+
+#endif /* _CYIP_LPCOMP_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_pass.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_pass.h
new file mode 100644
index 0000000000..b853d6e640
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_pass.h
@@ -0,0 +1,139 @@
+/***************************************************************************//**
+* \file cyip_pass.h
+*
+* \brief
+* PASS IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_PASS_H_
+#define _CYIP_PASS_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* PASS
+*******************************************************************************/
+
+#define PASS_AREF_SECTION_SIZE 0x00000100UL
+#define PASS_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief AREF configuration (PASS_AREF)
+ */
+typedef struct {
+ __IOM uint32_t AREF_CTRL; /*!< 0x00000000 global AREF control */
+ __IM uint32_t RESERVED[63];
+} PASS_AREF_V1_Type; /*!< Size = 256 (0x100) */
+
+/**
+ * \brief PASS top-level MMIO (DSABv2, INTR) (PASS)
+ */
+typedef struct {
+ __IM uint32_t INTR_CAUSE; /*!< 0x00000000 Interrupt cause register */
+ __IM uint32_t RESERVED[895];
+ PASS_AREF_V1_Type AREF; /*!< 0x00000E00 AREF configuration */
+ __IOM uint32_t VREF_TRIM0; /*!< 0x00000F00 VREF Trim bits */
+ __IOM uint32_t VREF_TRIM1; /*!< 0x00000F04 VREF Trim bits */
+ __IOM uint32_t VREF_TRIM2; /*!< 0x00000F08 VREF Trim bits */
+ __IOM uint32_t VREF_TRIM3; /*!< 0x00000F0C VREF Trim bits */
+ __IOM uint32_t IZTAT_TRIM0; /*!< 0x00000F10 IZTAT Trim bits */
+ __IOM uint32_t IZTAT_TRIM1; /*!< 0x00000F14 IZTAT Trim bits */
+ __IOM uint32_t IPTAT_TRIM0; /*!< 0x00000F18 IPTAT Trim bits */
+ __IOM uint32_t ICTAT_TRIM0; /*!< 0x00000F1C ICTAT Trim bits */
+} PASS_V1_Type; /*!< Size = 3872 (0xF20) */
+
+
+/* PASS_AREF.AREF_CTRL */
+#define PASS_AREF_AREF_CTRL_AREF_MODE_Pos 0UL
+#define PASS_AREF_AREF_CTRL_AREF_MODE_Msk 0x1UL
+#define PASS_AREF_AREF_CTRL_AREF_BIAS_SCALE_Pos 2UL
+#define PASS_AREF_AREF_CTRL_AREF_BIAS_SCALE_Msk 0xCUL
+#define PASS_AREF_AREF_CTRL_AREF_RMB_Pos 4UL
+#define PASS_AREF_AREF_CTRL_AREF_RMB_Msk 0x70UL
+#define PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Pos 7UL
+#define PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Msk 0x80UL
+#define PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Pos 8UL
+#define PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk 0xFF00UL
+#define PASS_AREF_AREF_CTRL_IZTAT_SEL_Pos 16UL
+#define PASS_AREF_AREF_CTRL_IZTAT_SEL_Msk 0x10000UL
+#define PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos 19UL
+#define PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Msk 0x80000UL
+#define PASS_AREF_AREF_CTRL_VREF_SEL_Pos 20UL
+#define PASS_AREF_AREF_CTRL_VREF_SEL_Msk 0x300000UL
+#define PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Pos 28UL
+#define PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Msk 0x30000000UL
+#define PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Pos 30UL
+#define PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL
+#define PASS_AREF_AREF_CTRL_ENABLED_Pos 31UL
+#define PASS_AREF_AREF_CTRL_ENABLED_Msk 0x80000000UL
+
+
+/* PASS.INTR_CAUSE */
+#define PASS_INTR_CAUSE_CTB0_INT_Pos 0UL
+#define PASS_INTR_CAUSE_CTB0_INT_Msk 0x1UL
+#define PASS_INTR_CAUSE_CTB1_INT_Pos 1UL
+#define PASS_INTR_CAUSE_CTB1_INT_Msk 0x2UL
+#define PASS_INTR_CAUSE_CTB2_INT_Pos 2UL
+#define PASS_INTR_CAUSE_CTB2_INT_Msk 0x4UL
+#define PASS_INTR_CAUSE_CTB3_INT_Pos 3UL
+#define PASS_INTR_CAUSE_CTB3_INT_Msk 0x8UL
+#define PASS_INTR_CAUSE_CTDAC0_INT_Pos 4UL
+#define PASS_INTR_CAUSE_CTDAC0_INT_Msk 0x10UL
+#define PASS_INTR_CAUSE_CTDAC1_INT_Pos 5UL
+#define PASS_INTR_CAUSE_CTDAC1_INT_Msk 0x20UL
+#define PASS_INTR_CAUSE_CTDAC2_INT_Pos 6UL
+#define PASS_INTR_CAUSE_CTDAC2_INT_Msk 0x40UL
+#define PASS_INTR_CAUSE_CTDAC3_INT_Pos 7UL
+#define PASS_INTR_CAUSE_CTDAC3_INT_Msk 0x80UL
+/* PASS.VREF_TRIM0 */
+#define PASS_VREF_TRIM0_VREF_ABS_TRIM_Pos 0UL
+#define PASS_VREF_TRIM0_VREF_ABS_TRIM_Msk 0xFFUL
+/* PASS.VREF_TRIM1 */
+#define PASS_VREF_TRIM1_VREF_TEMPCO_TRIM_Pos 0UL
+#define PASS_VREF_TRIM1_VREF_TEMPCO_TRIM_Msk 0xFFUL
+/* PASS.VREF_TRIM2 */
+#define PASS_VREF_TRIM2_VREF_CURV_TRIM_Pos 0UL
+#define PASS_VREF_TRIM2_VREF_CURV_TRIM_Msk 0xFFUL
+/* PASS.VREF_TRIM3 */
+#define PASS_VREF_TRIM3_VREF_ATTEN_TRIM_Pos 0UL
+#define PASS_VREF_TRIM3_VREF_ATTEN_TRIM_Msk 0xFUL
+/* PASS.IZTAT_TRIM0 */
+#define PASS_IZTAT_TRIM0_IZTAT_ABS_TRIM_Pos 0UL
+#define PASS_IZTAT_TRIM0_IZTAT_ABS_TRIM_Msk 0xFFUL
+/* PASS.IZTAT_TRIM1 */
+#define PASS_IZTAT_TRIM1_IZTAT_TC_TRIM_Pos 0UL
+#define PASS_IZTAT_TRIM1_IZTAT_TC_TRIM_Msk 0xFFUL
+/* PASS.IPTAT_TRIM0 */
+#define PASS_IPTAT_TRIM0_IPTAT_CORE_TRIM_Pos 0UL
+#define PASS_IPTAT_TRIM0_IPTAT_CORE_TRIM_Msk 0xFUL
+#define PASS_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Pos 4UL
+#define PASS_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Msk 0xF0UL
+/* PASS.ICTAT_TRIM0 */
+#define PASS_ICTAT_TRIM0_ICTAT_TRIM_Pos 0UL
+#define PASS_ICTAT_TRIM0_ICTAT_TRIM_Msk 0xFUL
+
+
+#endif /* _CYIP_PASS_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_pdm.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_pdm.h
new file mode 100644
index 0000000000..8fdcd7f841
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_pdm.h
@@ -0,0 +1,170 @@
+/***************************************************************************//**
+* \file cyip_pdm.h
+*
+* \brief
+* PDM IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_PDM_H_
+#define _CYIP_PDM_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* PDM
+*******************************************************************************/
+
+#define PDM_SECTION_SIZE 0x00001000UL
+
+/**
+ * \brief PDM registers (PDM)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */
+ __IOM uint32_t MODE_CTL; /*!< 0x00000014 Mode control */
+ __IOM uint32_t DATA_CTL; /*!< 0x00000018 Data control */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t CMD; /*!< 0x00000020 Command */
+ __IM uint32_t RESERVED2[7];
+ __IOM uint32_t TR_CTL; /*!< 0x00000040 Trigger control */
+ __IM uint32_t RESERVED3[175];
+ __IOM uint32_t RX_FIFO_CTL; /*!< 0x00000300 RX FIFO control */
+ __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000304 RX FIFO status */
+ __IM uint32_t RX_FIFO_RD; /*!< 0x00000308 RX FIFO read */
+ __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000030C RX FIFO silent read */
+ __IM uint32_t RESERVED4[764];
+ __IOM uint32_t INTR; /*!< 0x00000F00 Interrupt register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000F04 Interrupt set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000F08 Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x00000F0C Interrupt masked register */
+} PDM_V1_Type; /*!< Size = 3856 (0xF10) */
+
+
+/* PDM.CTL */
+#define PDM_CTL_PGA_R_Pos 0UL
+#define PDM_CTL_PGA_R_Msk 0xFUL
+#define PDM_CTL_PGA_L_Pos 8UL
+#define PDM_CTL_PGA_L_Msk 0xF00UL
+#define PDM_CTL_SOFT_MUTE_Pos 16UL
+#define PDM_CTL_SOFT_MUTE_Msk 0x10000UL
+#define PDM_CTL_STEP_SEL_Pos 17UL
+#define PDM_CTL_STEP_SEL_Msk 0x20000UL
+#define PDM_CTL_ENABLED_Pos 31UL
+#define PDM_CTL_ENABLED_Msk 0x80000000UL
+/* PDM.CLOCK_CTL */
+#define PDM_CLOCK_CTL_CLK_CLOCK_DIV_Pos 0UL
+#define PDM_CLOCK_CTL_CLK_CLOCK_DIV_Msk 0x3UL
+#define PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV_Pos 4UL
+#define PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV_Msk 0x30UL
+#define PDM_CLOCK_CTL_CKO_CLOCK_DIV_Pos 8UL
+#define PDM_CLOCK_CTL_CKO_CLOCK_DIV_Msk 0xF00UL
+#define PDM_CLOCK_CTL_SINC_RATE_Pos 16UL
+#define PDM_CLOCK_CTL_SINC_RATE_Msk 0x7F0000UL
+/* PDM.MODE_CTL */
+#define PDM_MODE_CTL_PCM_CH_SET_Pos 0UL
+#define PDM_MODE_CTL_PCM_CH_SET_Msk 0x3UL
+#define PDM_MODE_CTL_SWAP_LR_Pos 2UL
+#define PDM_MODE_CTL_SWAP_LR_Msk 0x4UL
+#define PDM_MODE_CTL_S_CYCLES_Pos 8UL
+#define PDM_MODE_CTL_S_CYCLES_Msk 0x700UL
+#define PDM_MODE_CTL_CKO_DELAY_Pos 16UL
+#define PDM_MODE_CTL_CKO_DELAY_Msk 0x70000UL
+#define PDM_MODE_CTL_HPF_GAIN_Pos 24UL
+#define PDM_MODE_CTL_HPF_GAIN_Msk 0xF000000UL
+#define PDM_MODE_CTL_HPF_EN_N_Pos 28UL
+#define PDM_MODE_CTL_HPF_EN_N_Msk 0x10000000UL
+/* PDM.DATA_CTL */
+#define PDM_DATA_CTL_WORD_LEN_Pos 0UL
+#define PDM_DATA_CTL_WORD_LEN_Msk 0x3UL
+#define PDM_DATA_CTL_BIT_EXTENSION_Pos 8UL
+#define PDM_DATA_CTL_BIT_EXTENSION_Msk 0x100UL
+/* PDM.CMD */
+#define PDM_CMD_STREAM_EN_Pos 0UL
+#define PDM_CMD_STREAM_EN_Msk 0x1UL
+/* PDM.TR_CTL */
+#define PDM_TR_CTL_RX_REQ_EN_Pos 16UL
+#define PDM_TR_CTL_RX_REQ_EN_Msk 0x10000UL
+/* PDM.RX_FIFO_CTL */
+#define PDM_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
+#define PDM_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
+#define PDM_RX_FIFO_CTL_CLEAR_Pos 16UL
+#define PDM_RX_FIFO_CTL_CLEAR_Msk 0x10000UL
+#define PDM_RX_FIFO_CTL_FREEZE_Pos 17UL
+#define PDM_RX_FIFO_CTL_FREEZE_Msk 0x20000UL
+/* PDM.RX_FIFO_STATUS */
+#define PDM_RX_FIFO_STATUS_USED_Pos 0UL
+#define PDM_RX_FIFO_STATUS_USED_Msk 0xFFUL
+#define PDM_RX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define PDM_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
+#define PDM_RX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define PDM_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
+/* PDM.RX_FIFO_RD */
+#define PDM_RX_FIFO_RD_DATA_Pos 0UL
+#define PDM_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL
+/* PDM.RX_FIFO_RD_SILENT */
+#define PDM_RX_FIFO_RD_SILENT_DATA_Pos 0UL
+#define PDM_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL
+/* PDM.INTR */
+#define PDM_INTR_RX_TRIGGER_Pos 16UL
+#define PDM_INTR_RX_TRIGGER_Msk 0x10000UL
+#define PDM_INTR_RX_NOT_EMPTY_Pos 18UL
+#define PDM_INTR_RX_NOT_EMPTY_Msk 0x40000UL
+#define PDM_INTR_RX_OVERFLOW_Pos 21UL
+#define PDM_INTR_RX_OVERFLOW_Msk 0x200000UL
+#define PDM_INTR_RX_UNDERFLOW_Pos 22UL
+#define PDM_INTR_RX_UNDERFLOW_Msk 0x400000UL
+/* PDM.INTR_SET */
+#define PDM_INTR_SET_RX_TRIGGER_Pos 16UL
+#define PDM_INTR_SET_RX_TRIGGER_Msk 0x10000UL
+#define PDM_INTR_SET_RX_NOT_EMPTY_Pos 18UL
+#define PDM_INTR_SET_RX_NOT_EMPTY_Msk 0x40000UL
+#define PDM_INTR_SET_RX_OVERFLOW_Pos 21UL
+#define PDM_INTR_SET_RX_OVERFLOW_Msk 0x200000UL
+#define PDM_INTR_SET_RX_UNDERFLOW_Pos 22UL
+#define PDM_INTR_SET_RX_UNDERFLOW_Msk 0x400000UL
+/* PDM.INTR_MASK */
+#define PDM_INTR_MASK_RX_TRIGGER_Pos 16UL
+#define PDM_INTR_MASK_RX_TRIGGER_Msk 0x10000UL
+#define PDM_INTR_MASK_RX_NOT_EMPTY_Pos 18UL
+#define PDM_INTR_MASK_RX_NOT_EMPTY_Msk 0x40000UL
+#define PDM_INTR_MASK_RX_OVERFLOW_Pos 21UL
+#define PDM_INTR_MASK_RX_OVERFLOW_Msk 0x200000UL
+#define PDM_INTR_MASK_RX_UNDERFLOW_Pos 22UL
+#define PDM_INTR_MASK_RX_UNDERFLOW_Msk 0x400000UL
+/* PDM.INTR_MASKED */
+#define PDM_INTR_MASKED_RX_TRIGGER_Pos 16UL
+#define PDM_INTR_MASKED_RX_TRIGGER_Msk 0x10000UL
+#define PDM_INTR_MASKED_RX_NOT_EMPTY_Pos 18UL
+#define PDM_INTR_MASKED_RX_NOT_EMPTY_Msk 0x40000UL
+#define PDM_INTR_MASKED_RX_OVERFLOW_Pos 21UL
+#define PDM_INTR_MASKED_RX_OVERFLOW_Msk 0x200000UL
+#define PDM_INTR_MASKED_RX_UNDERFLOW_Pos 22UL
+#define PDM_INTR_MASKED_RX_UNDERFLOW_Msk 0x400000UL
+
+
+#endif /* _CYIP_PDM_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_peri.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_peri.h
new file mode 100644
index 0000000000..cd589cca35
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_peri.h
@@ -0,0 +1,491 @@
+/***************************************************************************//**
+* \file cyip_peri.h
+*
+* \brief
+* PERI IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_PERI_H_
+#define _CYIP_PERI_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* PERI
+*******************************************************************************/
+
+#define PERI_GR_SECTION_SIZE 0x00000040UL
+#define PERI_TR_GR_SECTION_SIZE 0x00000200UL
+#define PERI_PPU_PR_SECTION_SIZE 0x00000040UL
+#define PERI_PPU_GR_SECTION_SIZE 0x00000040UL
+#define PERI_GR_PPU_SL_SECTION_SIZE 0x00000040UL
+#define PERI_GR_PPU_RG_SECTION_SIZE 0x00000040UL
+#define PERI_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Peripheral group structure (PERI_GR)
+ */
+typedef struct {
+ __IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */
+ __IM uint32_t RESERVED[7];
+ __IOM uint32_t SL_CTL; /*!< 0x00000020 Slave control */
+ __IOM uint32_t TIMEOUT_CTL; /*!< 0x00000024 Timeout control */
+ __IM uint32_t RESERVED1[6];
+} PERI_GR_V1_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief Trigger group (PERI_TR_GR)
+ */
+typedef struct {
+ __IOM uint32_t TR_OUT_CTL[128]; /*!< 0x00000000 Trigger control register */
+} PERI_TR_GR_V1_Type; /*!< Size = 512 (0x200) */
+
+/**
+ * \brief PPU structure with programmable address (PERI_PPU_PR)
+ */
+typedef struct {
+ __IOM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */
+ __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */
+ __IM uint32_t RESERVED[6];
+ __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */
+ __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */
+ __IM uint32_t RESERVED1[6];
+} PERI_PPU_PR_V1_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief PPU structure with fixed/constant address for a peripheral group (PERI_PPU_GR)
+ */
+typedef struct {
+ __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */
+ __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */
+ __IM uint32_t RESERVED[6];
+ __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */
+ __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */
+ __IM uint32_t RESERVED1[6];
+} PERI_PPU_GR_V1_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief PPU structure with fixed/constant address for a specific slave (PERI_GR_PPU_SL)
+ */
+typedef struct {
+ __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */
+ __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */
+ __IM uint32_t RESERVED[6];
+ __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */
+ __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */
+ __IM uint32_t RESERVED1[6];
+} PERI_GR_PPU_SL_V1_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief PPU structure with fixed/constant address for a specific region (PERI_GR_PPU_RG)
+ */
+typedef struct {
+ __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */
+ __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */
+ __IM uint32_t RESERVED[6];
+ __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */
+ __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */
+ __IM uint32_t RESERVED1[6];
+} PERI_GR_PPU_RG_V1_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief Peripheral interconnect (PERI)
+ */
+typedef struct {
+ PERI_GR_V1_Type GR[16]; /*!< 0x00000000 Peripheral group structure */
+ __IOM uint32_t DIV_CMD; /*!< 0x00000400 Divider command register */
+ __IM uint32_t RESERVED[255];
+ __IOM uint32_t DIV_8_CTL[64]; /*!< 0x00000800 Divider control register (for 8.0 divider) */
+ __IOM uint32_t DIV_16_CTL[64]; /*!< 0x00000900 Divider control register (for 16.0 divider) */
+ __IOM uint32_t DIV_16_5_CTL[64]; /*!< 0x00000A00 Divider control register (for 16.5 divider) */
+ __IOM uint32_t DIV_24_5_CTL[63]; /*!< 0x00000B00 Divider control register (for 24.5 divider) */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t CLOCK_CTL[128]; /*!< 0x00000C00 Clock control register */
+ __IM uint32_t RESERVED2[128];
+ __IOM uint32_t TR_CMD; /*!< 0x00001000 Trigger command register */
+ __IM uint32_t RESERVED3[1023];
+ PERI_TR_GR_V1_Type TR_GR[16]; /*!< 0x00002000 Trigger group */
+ PERI_PPU_PR_V1_Type PPU_PR[32]; /*!< 0x00004000 PPU structure with programmable address */
+ __IM uint32_t RESERVED4[512];
+ PERI_PPU_GR_V1_Type PPU_GR[16]; /*!< 0x00005000 PPU structure with fixed/constant address for a peripheral
+ group */
+} PERI_V1_Type; /*!< Size = 21504 (0x5400) */
+
+
+/* PERI_GR.CLOCK_CTL */
+#define PERI_GR_CLOCK_CTL_INT8_DIV_Pos 8UL
+#define PERI_GR_CLOCK_CTL_INT8_DIV_Msk 0xFF00UL
+/* PERI_GR.SL_CTL */
+#define PERI_GR_SL_CTL_ENABLED_0_Pos 0UL
+#define PERI_GR_SL_CTL_ENABLED_0_Msk 0x1UL
+#define PERI_GR_SL_CTL_ENABLED_1_Pos 1UL
+#define PERI_GR_SL_CTL_ENABLED_1_Msk 0x2UL
+#define PERI_GR_SL_CTL_ENABLED_2_Pos 2UL
+#define PERI_GR_SL_CTL_ENABLED_2_Msk 0x4UL
+#define PERI_GR_SL_CTL_ENABLED_3_Pos 3UL
+#define PERI_GR_SL_CTL_ENABLED_3_Msk 0x8UL
+#define PERI_GR_SL_CTL_ENABLED_4_Pos 4UL
+#define PERI_GR_SL_CTL_ENABLED_4_Msk 0x10UL
+#define PERI_GR_SL_CTL_ENABLED_5_Pos 5UL
+#define PERI_GR_SL_CTL_ENABLED_5_Msk 0x20UL
+#define PERI_GR_SL_CTL_ENABLED_6_Pos 6UL
+#define PERI_GR_SL_CTL_ENABLED_6_Msk 0x40UL
+#define PERI_GR_SL_CTL_ENABLED_7_Pos 7UL
+#define PERI_GR_SL_CTL_ENABLED_7_Msk 0x80UL
+#define PERI_GR_SL_CTL_ENABLED_8_Pos 8UL
+#define PERI_GR_SL_CTL_ENABLED_8_Msk 0x100UL
+#define PERI_GR_SL_CTL_ENABLED_9_Pos 9UL
+#define PERI_GR_SL_CTL_ENABLED_9_Msk 0x200UL
+#define PERI_GR_SL_CTL_ENABLED_10_Pos 10UL
+#define PERI_GR_SL_CTL_ENABLED_10_Msk 0x400UL
+#define PERI_GR_SL_CTL_ENABLED_11_Pos 11UL
+#define PERI_GR_SL_CTL_ENABLED_11_Msk 0x800UL
+#define PERI_GR_SL_CTL_ENABLED_12_Pos 12UL
+#define PERI_GR_SL_CTL_ENABLED_12_Msk 0x1000UL
+#define PERI_GR_SL_CTL_ENABLED_13_Pos 13UL
+#define PERI_GR_SL_CTL_ENABLED_13_Msk 0x2000UL
+#define PERI_GR_SL_CTL_ENABLED_14_Pos 14UL
+#define PERI_GR_SL_CTL_ENABLED_14_Msk 0x4000UL
+#define PERI_GR_SL_CTL_ENABLED_15_Pos 15UL
+#define PERI_GR_SL_CTL_ENABLED_15_Msk 0x8000UL
+/* PERI_GR.TIMEOUT_CTL */
+#define PERI_GR_TIMEOUT_CTL_TIMEOUT_Pos 0UL
+#define PERI_GR_TIMEOUT_CTL_TIMEOUT_Msk 0xFFFFUL
+
+
+/* PERI_TR_GR.TR_OUT_CTL */
+#define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Pos 0UL
+#define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Msk 0xFFUL
+#define PERI_TR_GR_TR_OUT_CTL_TR_INV_Pos 8UL
+#define PERI_TR_GR_TR_OUT_CTL_TR_INV_Msk 0x100UL
+#define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Pos 9UL
+#define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Msk 0x200UL
+
+
+/* PERI_PPU_PR.ADDR0 */
+#define PERI_PPU_PR_ADDR0_SUBREGION_DISABLE_Pos 0UL
+#define PERI_PPU_PR_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_PPU_PR_ADDR0_ADDR24_Pos 8UL
+#define PERI_PPU_PR_ADDR0_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_PPU_PR.ATT0 */
+#define PERI_PPU_PR_ATT0_UR_Pos 0UL
+#define PERI_PPU_PR_ATT0_UR_Msk 0x1UL
+#define PERI_PPU_PR_ATT0_UW_Pos 1UL
+#define PERI_PPU_PR_ATT0_UW_Msk 0x2UL
+#define PERI_PPU_PR_ATT0_UX_Pos 2UL
+#define PERI_PPU_PR_ATT0_UX_Msk 0x4UL
+#define PERI_PPU_PR_ATT0_PR_Pos 3UL
+#define PERI_PPU_PR_ATT0_PR_Msk 0x8UL
+#define PERI_PPU_PR_ATT0_PW_Pos 4UL
+#define PERI_PPU_PR_ATT0_PW_Msk 0x10UL
+#define PERI_PPU_PR_ATT0_PX_Pos 5UL
+#define PERI_PPU_PR_ATT0_PX_Msk 0x20UL
+#define PERI_PPU_PR_ATT0_NS_Pos 6UL
+#define PERI_PPU_PR_ATT0_NS_Msk 0x40UL
+#define PERI_PPU_PR_ATT0_PC_MASK_0_Pos 8UL
+#define PERI_PPU_PR_ATT0_PC_MASK_0_Msk 0x100UL
+#define PERI_PPU_PR_ATT0_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_PPU_PR_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_PPU_PR_ATT0_REGION_SIZE_Pos 24UL
+#define PERI_PPU_PR_ATT0_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_PPU_PR_ATT0_PC_MATCH_Pos 30UL
+#define PERI_PPU_PR_ATT0_PC_MATCH_Msk 0x40000000UL
+#define PERI_PPU_PR_ATT0_ENABLED_Pos 31UL
+#define PERI_PPU_PR_ATT0_ENABLED_Msk 0x80000000UL
+/* PERI_PPU_PR.ADDR1 */
+#define PERI_PPU_PR_ADDR1_SUBREGION_DISABLE_Pos 0UL
+#define PERI_PPU_PR_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_PPU_PR_ADDR1_ADDR24_Pos 8UL
+#define PERI_PPU_PR_ADDR1_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_PPU_PR.ATT1 */
+#define PERI_PPU_PR_ATT1_UR_Pos 0UL
+#define PERI_PPU_PR_ATT1_UR_Msk 0x1UL
+#define PERI_PPU_PR_ATT1_UW_Pos 1UL
+#define PERI_PPU_PR_ATT1_UW_Msk 0x2UL
+#define PERI_PPU_PR_ATT1_UX_Pos 2UL
+#define PERI_PPU_PR_ATT1_UX_Msk 0x4UL
+#define PERI_PPU_PR_ATT1_PR_Pos 3UL
+#define PERI_PPU_PR_ATT1_PR_Msk 0x8UL
+#define PERI_PPU_PR_ATT1_PW_Pos 4UL
+#define PERI_PPU_PR_ATT1_PW_Msk 0x10UL
+#define PERI_PPU_PR_ATT1_PX_Pos 5UL
+#define PERI_PPU_PR_ATT1_PX_Msk 0x20UL
+#define PERI_PPU_PR_ATT1_NS_Pos 6UL
+#define PERI_PPU_PR_ATT1_NS_Msk 0x40UL
+#define PERI_PPU_PR_ATT1_PC_MASK_0_Pos 8UL
+#define PERI_PPU_PR_ATT1_PC_MASK_0_Msk 0x100UL
+#define PERI_PPU_PR_ATT1_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_PPU_PR_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_PPU_PR_ATT1_REGION_SIZE_Pos 24UL
+#define PERI_PPU_PR_ATT1_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_PPU_PR_ATT1_PC_MATCH_Pos 30UL
+#define PERI_PPU_PR_ATT1_PC_MATCH_Msk 0x40000000UL
+#define PERI_PPU_PR_ATT1_ENABLED_Pos 31UL
+#define PERI_PPU_PR_ATT1_ENABLED_Msk 0x80000000UL
+
+
+/* PERI_PPU_GR.ADDR0 */
+#define PERI_PPU_GR_ADDR0_SUBREGION_DISABLE_Pos 0UL
+#define PERI_PPU_GR_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_PPU_GR_ADDR0_ADDR24_Pos 8UL
+#define PERI_PPU_GR_ADDR0_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_PPU_GR.ATT0 */
+#define PERI_PPU_GR_ATT0_UR_Pos 0UL
+#define PERI_PPU_GR_ATT0_UR_Msk 0x1UL
+#define PERI_PPU_GR_ATT0_UW_Pos 1UL
+#define PERI_PPU_GR_ATT0_UW_Msk 0x2UL
+#define PERI_PPU_GR_ATT0_UX_Pos 2UL
+#define PERI_PPU_GR_ATT0_UX_Msk 0x4UL
+#define PERI_PPU_GR_ATT0_PR_Pos 3UL
+#define PERI_PPU_GR_ATT0_PR_Msk 0x8UL
+#define PERI_PPU_GR_ATT0_PW_Pos 4UL
+#define PERI_PPU_GR_ATT0_PW_Msk 0x10UL
+#define PERI_PPU_GR_ATT0_PX_Pos 5UL
+#define PERI_PPU_GR_ATT0_PX_Msk 0x20UL
+#define PERI_PPU_GR_ATT0_NS_Pos 6UL
+#define PERI_PPU_GR_ATT0_NS_Msk 0x40UL
+#define PERI_PPU_GR_ATT0_PC_MASK_0_Pos 8UL
+#define PERI_PPU_GR_ATT0_PC_MASK_0_Msk 0x100UL
+#define PERI_PPU_GR_ATT0_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_PPU_GR_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_PPU_GR_ATT0_REGION_SIZE_Pos 24UL
+#define PERI_PPU_GR_ATT0_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_PPU_GR_ATT0_PC_MATCH_Pos 30UL
+#define PERI_PPU_GR_ATT0_PC_MATCH_Msk 0x40000000UL
+#define PERI_PPU_GR_ATT0_ENABLED_Pos 31UL
+#define PERI_PPU_GR_ATT0_ENABLED_Msk 0x80000000UL
+/* PERI_PPU_GR.ADDR1 */
+#define PERI_PPU_GR_ADDR1_SUBREGION_DISABLE_Pos 0UL
+#define PERI_PPU_GR_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_PPU_GR_ADDR1_ADDR24_Pos 8UL
+#define PERI_PPU_GR_ADDR1_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_PPU_GR.ATT1 */
+#define PERI_PPU_GR_ATT1_UR_Pos 0UL
+#define PERI_PPU_GR_ATT1_UR_Msk 0x1UL
+#define PERI_PPU_GR_ATT1_UW_Pos 1UL
+#define PERI_PPU_GR_ATT1_UW_Msk 0x2UL
+#define PERI_PPU_GR_ATT1_UX_Pos 2UL
+#define PERI_PPU_GR_ATT1_UX_Msk 0x4UL
+#define PERI_PPU_GR_ATT1_PR_Pos 3UL
+#define PERI_PPU_GR_ATT1_PR_Msk 0x8UL
+#define PERI_PPU_GR_ATT1_PW_Pos 4UL
+#define PERI_PPU_GR_ATT1_PW_Msk 0x10UL
+#define PERI_PPU_GR_ATT1_PX_Pos 5UL
+#define PERI_PPU_GR_ATT1_PX_Msk 0x20UL
+#define PERI_PPU_GR_ATT1_NS_Pos 6UL
+#define PERI_PPU_GR_ATT1_NS_Msk 0x40UL
+#define PERI_PPU_GR_ATT1_PC_MASK_0_Pos 8UL
+#define PERI_PPU_GR_ATT1_PC_MASK_0_Msk 0x100UL
+#define PERI_PPU_GR_ATT1_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_PPU_GR_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_PPU_GR_ATT1_REGION_SIZE_Pos 24UL
+#define PERI_PPU_GR_ATT1_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_PPU_GR_ATT1_PC_MATCH_Pos 30UL
+#define PERI_PPU_GR_ATT1_PC_MATCH_Msk 0x40000000UL
+#define PERI_PPU_GR_ATT1_ENABLED_Pos 31UL
+#define PERI_PPU_GR_ATT1_ENABLED_Msk 0x80000000UL
+
+
+/* PERI_GR_PPU_SL.ADDR0 */
+#define PERI_GR_PPU_SL_ADDR0_SUBREGION_DISABLE_Pos 0UL
+#define PERI_GR_PPU_SL_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_GR_PPU_SL_ADDR0_ADDR24_Pos 8UL
+#define PERI_GR_PPU_SL_ADDR0_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_GR_PPU_SL.ATT0 */
+#define PERI_GR_PPU_SL_ATT0_UR_Pos 0UL
+#define PERI_GR_PPU_SL_ATT0_UR_Msk 0x1UL
+#define PERI_GR_PPU_SL_ATT0_UW_Pos 1UL
+#define PERI_GR_PPU_SL_ATT0_UW_Msk 0x2UL
+#define PERI_GR_PPU_SL_ATT0_UX_Pos 2UL
+#define PERI_GR_PPU_SL_ATT0_UX_Msk 0x4UL
+#define PERI_GR_PPU_SL_ATT0_PR_Pos 3UL
+#define PERI_GR_PPU_SL_ATT0_PR_Msk 0x8UL
+#define PERI_GR_PPU_SL_ATT0_PW_Pos 4UL
+#define PERI_GR_PPU_SL_ATT0_PW_Msk 0x10UL
+#define PERI_GR_PPU_SL_ATT0_PX_Pos 5UL
+#define PERI_GR_PPU_SL_ATT0_PX_Msk 0x20UL
+#define PERI_GR_PPU_SL_ATT0_NS_Pos 6UL
+#define PERI_GR_PPU_SL_ATT0_NS_Msk 0x40UL
+#define PERI_GR_PPU_SL_ATT0_PC_MASK_0_Pos 8UL
+#define PERI_GR_PPU_SL_ATT0_PC_MASK_0_Msk 0x100UL
+#define PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_GR_PPU_SL_ATT0_REGION_SIZE_Pos 24UL
+#define PERI_GR_PPU_SL_ATT0_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_GR_PPU_SL_ATT0_PC_MATCH_Pos 30UL
+#define PERI_GR_PPU_SL_ATT0_PC_MATCH_Msk 0x40000000UL
+#define PERI_GR_PPU_SL_ATT0_ENABLED_Pos 31UL
+#define PERI_GR_PPU_SL_ATT0_ENABLED_Msk 0x80000000UL
+/* PERI_GR_PPU_SL.ADDR1 */
+#define PERI_GR_PPU_SL_ADDR1_SUBREGION_DISABLE_Pos 0UL
+#define PERI_GR_PPU_SL_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_GR_PPU_SL_ADDR1_ADDR24_Pos 8UL
+#define PERI_GR_PPU_SL_ADDR1_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_GR_PPU_SL.ATT1 */
+#define PERI_GR_PPU_SL_ATT1_UR_Pos 0UL
+#define PERI_GR_PPU_SL_ATT1_UR_Msk 0x1UL
+#define PERI_GR_PPU_SL_ATT1_UW_Pos 1UL
+#define PERI_GR_PPU_SL_ATT1_UW_Msk 0x2UL
+#define PERI_GR_PPU_SL_ATT1_UX_Pos 2UL
+#define PERI_GR_PPU_SL_ATT1_UX_Msk 0x4UL
+#define PERI_GR_PPU_SL_ATT1_PR_Pos 3UL
+#define PERI_GR_PPU_SL_ATT1_PR_Msk 0x8UL
+#define PERI_GR_PPU_SL_ATT1_PW_Pos 4UL
+#define PERI_GR_PPU_SL_ATT1_PW_Msk 0x10UL
+#define PERI_GR_PPU_SL_ATT1_PX_Pos 5UL
+#define PERI_GR_PPU_SL_ATT1_PX_Msk 0x20UL
+#define PERI_GR_PPU_SL_ATT1_NS_Pos 6UL
+#define PERI_GR_PPU_SL_ATT1_NS_Msk 0x40UL
+#define PERI_GR_PPU_SL_ATT1_PC_MASK_0_Pos 8UL
+#define PERI_GR_PPU_SL_ATT1_PC_MASK_0_Msk 0x100UL
+#define PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_GR_PPU_SL_ATT1_REGION_SIZE_Pos 24UL
+#define PERI_GR_PPU_SL_ATT1_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_GR_PPU_SL_ATT1_PC_MATCH_Pos 30UL
+#define PERI_GR_PPU_SL_ATT1_PC_MATCH_Msk 0x40000000UL
+#define PERI_GR_PPU_SL_ATT1_ENABLED_Pos 31UL
+#define PERI_GR_PPU_SL_ATT1_ENABLED_Msk 0x80000000UL
+
+
+/* PERI_GR_PPU_RG.ADDR0 */
+#define PERI_GR_PPU_RG_ADDR0_SUBREGION_DISABLE_Pos 0UL
+#define PERI_GR_PPU_RG_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_GR_PPU_RG_ADDR0_ADDR24_Pos 8UL
+#define PERI_GR_PPU_RG_ADDR0_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_GR_PPU_RG.ATT0 */
+#define PERI_GR_PPU_RG_ATT0_UR_Pos 0UL
+#define PERI_GR_PPU_RG_ATT0_UR_Msk 0x1UL
+#define PERI_GR_PPU_RG_ATT0_UW_Pos 1UL
+#define PERI_GR_PPU_RG_ATT0_UW_Msk 0x2UL
+#define PERI_GR_PPU_RG_ATT0_UX_Pos 2UL
+#define PERI_GR_PPU_RG_ATT0_UX_Msk 0x4UL
+#define PERI_GR_PPU_RG_ATT0_PR_Pos 3UL
+#define PERI_GR_PPU_RG_ATT0_PR_Msk 0x8UL
+#define PERI_GR_PPU_RG_ATT0_PW_Pos 4UL
+#define PERI_GR_PPU_RG_ATT0_PW_Msk 0x10UL
+#define PERI_GR_PPU_RG_ATT0_PX_Pos 5UL
+#define PERI_GR_PPU_RG_ATT0_PX_Msk 0x20UL
+#define PERI_GR_PPU_RG_ATT0_NS_Pos 6UL
+#define PERI_GR_PPU_RG_ATT0_NS_Msk 0x40UL
+#define PERI_GR_PPU_RG_ATT0_PC_MASK_0_Pos 8UL
+#define PERI_GR_PPU_RG_ATT0_PC_MASK_0_Msk 0x100UL
+#define PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_GR_PPU_RG_ATT0_REGION_SIZE_Pos 24UL
+#define PERI_GR_PPU_RG_ATT0_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_GR_PPU_RG_ATT0_PC_MATCH_Pos 30UL
+#define PERI_GR_PPU_RG_ATT0_PC_MATCH_Msk 0x40000000UL
+#define PERI_GR_PPU_RG_ATT0_ENABLED_Pos 31UL
+#define PERI_GR_PPU_RG_ATT0_ENABLED_Msk 0x80000000UL
+/* PERI_GR_PPU_RG.ADDR1 */
+#define PERI_GR_PPU_RG_ADDR1_SUBREGION_DISABLE_Pos 0UL
+#define PERI_GR_PPU_RG_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_GR_PPU_RG_ADDR1_ADDR24_Pos 8UL
+#define PERI_GR_PPU_RG_ADDR1_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_GR_PPU_RG.ATT1 */
+#define PERI_GR_PPU_RG_ATT1_UR_Pos 0UL
+#define PERI_GR_PPU_RG_ATT1_UR_Msk 0x1UL
+#define PERI_GR_PPU_RG_ATT1_UW_Pos 1UL
+#define PERI_GR_PPU_RG_ATT1_UW_Msk 0x2UL
+#define PERI_GR_PPU_RG_ATT1_UX_Pos 2UL
+#define PERI_GR_PPU_RG_ATT1_UX_Msk 0x4UL
+#define PERI_GR_PPU_RG_ATT1_PR_Pos 3UL
+#define PERI_GR_PPU_RG_ATT1_PR_Msk 0x8UL
+#define PERI_GR_PPU_RG_ATT1_PW_Pos 4UL
+#define PERI_GR_PPU_RG_ATT1_PW_Msk 0x10UL
+#define PERI_GR_PPU_RG_ATT1_PX_Pos 5UL
+#define PERI_GR_PPU_RG_ATT1_PX_Msk 0x20UL
+#define PERI_GR_PPU_RG_ATT1_NS_Pos 6UL
+#define PERI_GR_PPU_RG_ATT1_NS_Msk 0x40UL
+#define PERI_GR_PPU_RG_ATT1_PC_MASK_0_Pos 8UL
+#define PERI_GR_PPU_RG_ATT1_PC_MASK_0_Msk 0x100UL
+#define PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_GR_PPU_RG_ATT1_REGION_SIZE_Pos 24UL
+#define PERI_GR_PPU_RG_ATT1_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_GR_PPU_RG_ATT1_PC_MATCH_Pos 30UL
+#define PERI_GR_PPU_RG_ATT1_PC_MATCH_Msk 0x40000000UL
+#define PERI_GR_PPU_RG_ATT1_ENABLED_Pos 31UL
+#define PERI_GR_PPU_RG_ATT1_ENABLED_Msk 0x80000000UL
+
+
+/* PERI.DIV_CMD */
+#define PERI_DIV_CMD_DIV_SEL_Pos 0UL
+#define PERI_DIV_CMD_DIV_SEL_Msk 0x3FUL
+#define PERI_DIV_CMD_TYPE_SEL_Pos 6UL
+#define PERI_DIV_CMD_TYPE_SEL_Msk 0xC0UL
+#define PERI_DIV_CMD_PA_DIV_SEL_Pos 8UL
+#define PERI_DIV_CMD_PA_DIV_SEL_Msk 0x3F00UL
+#define PERI_DIV_CMD_PA_TYPE_SEL_Pos 14UL
+#define PERI_DIV_CMD_PA_TYPE_SEL_Msk 0xC000UL
+#define PERI_DIV_CMD_DISABLE_Pos 30UL
+#define PERI_DIV_CMD_DISABLE_Msk 0x40000000UL
+#define PERI_DIV_CMD_ENABLE_Pos 31UL
+#define PERI_DIV_CMD_ENABLE_Msk 0x80000000UL
+/* PERI.DIV_8_CTL */
+#define PERI_DIV_8_CTL_EN_Pos 0UL
+#define PERI_DIV_8_CTL_EN_Msk 0x1UL
+#define PERI_DIV_8_CTL_INT8_DIV_Pos 8UL
+#define PERI_DIV_8_CTL_INT8_DIV_Msk 0xFF00UL
+/* PERI.DIV_16_CTL */
+#define PERI_DIV_16_CTL_EN_Pos 0UL
+#define PERI_DIV_16_CTL_EN_Msk 0x1UL
+#define PERI_DIV_16_CTL_INT16_DIV_Pos 8UL
+#define PERI_DIV_16_CTL_INT16_DIV_Msk 0xFFFF00UL
+/* PERI.DIV_16_5_CTL */
+#define PERI_DIV_16_5_CTL_EN_Pos 0UL
+#define PERI_DIV_16_5_CTL_EN_Msk 0x1UL
+#define PERI_DIV_16_5_CTL_FRAC5_DIV_Pos 3UL
+#define PERI_DIV_16_5_CTL_FRAC5_DIV_Msk 0xF8UL
+#define PERI_DIV_16_5_CTL_INT16_DIV_Pos 8UL
+#define PERI_DIV_16_5_CTL_INT16_DIV_Msk 0xFFFF00UL
+/* PERI.DIV_24_5_CTL */
+#define PERI_DIV_24_5_CTL_EN_Pos 0UL
+#define PERI_DIV_24_5_CTL_EN_Msk 0x1UL
+#define PERI_DIV_24_5_CTL_FRAC5_DIV_Pos 3UL
+#define PERI_DIV_24_5_CTL_FRAC5_DIV_Msk 0xF8UL
+#define PERI_DIV_24_5_CTL_INT24_DIV_Pos 8UL
+#define PERI_DIV_24_5_CTL_INT24_DIV_Msk 0xFFFFFF00UL
+/* PERI.CLOCK_CTL */
+#define PERI_CLOCK_CTL_DIV_SEL_Pos 0UL
+#define PERI_CLOCK_CTL_DIV_SEL_Msk 0x3FUL
+#define PERI_CLOCK_CTL_TYPE_SEL_Pos 6UL
+#define PERI_CLOCK_CTL_TYPE_SEL_Msk 0xC0UL
+/* PERI.TR_CMD */
+#define PERI_TR_CMD_TR_SEL_Pos 0UL
+#define PERI_TR_CMD_TR_SEL_Msk 0xFFUL
+#define PERI_TR_CMD_GROUP_SEL_Pos 8UL
+#define PERI_TR_CMD_GROUP_SEL_Msk 0xF00UL
+#define PERI_TR_CMD_COUNT_Pos 16UL
+#define PERI_TR_CMD_COUNT_Msk 0xFF0000UL
+#define PERI_TR_CMD_OUT_SEL_Pos 30UL
+#define PERI_TR_CMD_OUT_SEL_Msk 0x40000000UL
+#define PERI_TR_CMD_ACTIVATE_Pos 31UL
+#define PERI_TR_CMD_ACTIVATE_Msk 0x80000000UL
+
+
+#endif /* _CYIP_PERI_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_peri_ms_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_peri_ms_v2.h
new file mode 100644
index 0000000000..a2c6c0125f
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_peri_ms_v2.h
@@ -0,0 +1,785 @@
+/***************************************************************************//**
+* \file cyip_peri_ms_v2.h
+*
+* \brief
+* PERI_MS IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_PERI_MS_V2_H_
+#define _CYIP_PERI_MS_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* PERI_MS
+*******************************************************************************/
+
+#define PERI_MS_PPU_PR_V2_SECTION_SIZE 0x00000040UL
+#define PERI_MS_PPU_FX_V2_SECTION_SIZE 0x00000040UL
+#define PERI_MS_V2_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Programmable protection structure pair (PERI_MS_PPU_PR)
+ */
+typedef struct {
+ __IOM uint32_t SL_ADDR; /*!< 0x00000000 Slave region, base address */
+ __IOM uint32_t SL_SIZE; /*!< 0x00000004 Slave region, size */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t SL_ATT0; /*!< 0x00000010 Slave attributes 0 */
+ __IOM uint32_t SL_ATT1; /*!< 0x00000014 Slave attributes 1 */
+ __IOM uint32_t SL_ATT2; /*!< 0x00000018 Slave attributes 2 */
+ __IOM uint32_t SL_ATT3; /*!< 0x0000001C Slave attributes 3 */
+ __IM uint32_t MS_ADDR; /*!< 0x00000020 Master region, base address */
+ __IM uint32_t MS_SIZE; /*!< 0x00000024 Master region, size */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t MS_ATT0; /*!< 0x00000030 Master attributes 0 */
+ __IOM uint32_t MS_ATT1; /*!< 0x00000034 Master attributes 1 */
+ __IOM uint32_t MS_ATT2; /*!< 0x00000038 Master attributes 2 */
+ __IOM uint32_t MS_ATT3; /*!< 0x0000003C Master attributes 3 */
+} PERI_MS_PPU_PR_V2_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief Fixed protection structure pair (PERI_MS_PPU_FX)
+ */
+typedef struct {
+ __IM uint32_t SL_ADDR; /*!< 0x00000000 Slave region, base address */
+ __IM uint32_t SL_SIZE; /*!< 0x00000004 Slave region, size */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t SL_ATT0; /*!< 0x00000010 Slave attributes 0 */
+ __IOM uint32_t SL_ATT1; /*!< 0x00000014 Slave attributes 1 */
+ __IOM uint32_t SL_ATT2; /*!< 0x00000018 Slave attributes 2 */
+ __IOM uint32_t SL_ATT3; /*!< 0x0000001C Slave attributes 3 */
+ __IM uint32_t MS_ADDR; /*!< 0x00000020 Master region, base address */
+ __IM uint32_t MS_SIZE; /*!< 0x00000024 Master region, size */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t MS_ATT0; /*!< 0x00000030 Master attributes 0 */
+ __IOM uint32_t MS_ATT1; /*!< 0x00000034 Master attributes 1 */
+ __IOM uint32_t MS_ATT2; /*!< 0x00000038 Master attributes 2 */
+ __IOM uint32_t MS_ATT3; /*!< 0x0000003C Master attributes 3 */
+} PERI_MS_PPU_FX_V2_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief Peripheral interconnect, master interface (PERI_MS)
+ */
+typedef struct {
+ PERI_MS_PPU_PR_V2_Type PPU_PR[32]; /*!< 0x00000000 Programmable protection structure pair */
+ PERI_MS_PPU_FX_V2_Type PPU_FX[992]; /*!< 0x00000800 Fixed protection structure pair */
+} PERI_MS_V2_Type; /*!< Size = 65536 (0x10000) */
+
+
+/* PERI_MS_PPU_PR.SL_ADDR */
+#define PERI_MS_PPU_PR_V2_SL_ADDR_ADDR30_Pos 2UL
+#define PERI_MS_PPU_PR_V2_SL_ADDR_ADDR30_Msk 0xFFFFFFFCUL
+/* PERI_MS_PPU_PR.SL_SIZE */
+#define PERI_MS_PPU_PR_V2_SL_SIZE_REGION_SIZE_Pos 24UL
+#define PERI_MS_PPU_PR_V2_SL_SIZE_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_MS_PPU_PR_V2_SL_SIZE_VALID_Pos 31UL
+#define PERI_MS_PPU_PR_V2_SL_SIZE_VALID_Msk 0x80000000UL
+/* PERI_MS_PPU_PR.SL_ATT0 */
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_UR_Pos 0UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_UR_Msk 0x1UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_UW_Pos 1UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_UW_Msk 0x2UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_PR_Pos 2UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_PR_Msk 0x4UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_PW_Pos 3UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_PW_Msk 0x8UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_NS_Pos 4UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_NS_Msk 0x10UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_UR_Pos 8UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_UR_Msk 0x100UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_UW_Pos 9UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_UW_Msk 0x200UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_PR_Pos 10UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_PR_Msk 0x400UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_PW_Pos 11UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_PW_Msk 0x800UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_NS_Pos 12UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_NS_Msk 0x1000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_UR_Pos 16UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_UR_Msk 0x10000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_UW_Pos 17UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_UW_Msk 0x20000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_PR_Pos 18UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_PR_Msk 0x40000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_PW_Pos 19UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_PW_Msk 0x80000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_NS_Pos 20UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_NS_Msk 0x100000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_UR_Pos 24UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_UW_Pos 25UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_PR_Pos 26UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_PW_Pos 27UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_NS_Pos 28UL
+#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_PR.SL_ATT1 */
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_UR_Pos 0UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_UR_Msk 0x1UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_UW_Pos 1UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_UW_Msk 0x2UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_PR_Pos 2UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_PR_Msk 0x4UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_PW_Pos 3UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_PW_Msk 0x8UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_NS_Pos 4UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_NS_Msk 0x10UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_UR_Pos 8UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_UR_Msk 0x100UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_UW_Pos 9UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_UW_Msk 0x200UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_PR_Pos 10UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_PR_Msk 0x400UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_PW_Pos 11UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_PW_Msk 0x800UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_NS_Pos 12UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_NS_Msk 0x1000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_UR_Pos 16UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_UR_Msk 0x10000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_UW_Pos 17UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_UW_Msk 0x20000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_PR_Pos 18UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_PR_Msk 0x40000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_PW_Pos 19UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_PW_Msk 0x80000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_NS_Pos 20UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_NS_Msk 0x100000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_UR_Pos 24UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_UW_Pos 25UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_PR_Pos 26UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_PW_Pos 27UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_NS_Pos 28UL
+#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_PR.SL_ATT2 */
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_UR_Pos 0UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_UR_Msk 0x1UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_UW_Pos 1UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_UW_Msk 0x2UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_PR_Pos 2UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_PR_Msk 0x4UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_PW_Pos 3UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_PW_Msk 0x8UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_NS_Pos 4UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_NS_Msk 0x10UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_UR_Pos 8UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_UR_Msk 0x100UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_UW_Pos 9UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_UW_Msk 0x200UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_PR_Pos 10UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_PR_Msk 0x400UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_PW_Pos 11UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_PW_Msk 0x800UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_NS_Pos 12UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_NS_Msk 0x1000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_UR_Pos 16UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_UR_Msk 0x10000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_UW_Pos 17UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_UW_Msk 0x20000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_PR_Pos 18UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_PR_Msk 0x40000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_PW_Pos 19UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_PW_Msk 0x80000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_NS_Pos 20UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_NS_Msk 0x100000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_UR_Pos 24UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_UW_Pos 25UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_PR_Pos 26UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_PW_Pos 27UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_NS_Pos 28UL
+#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_PR.SL_ATT3 */
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_UR_Pos 0UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_UR_Msk 0x1UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_UW_Pos 1UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_UW_Msk 0x2UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_PR_Pos 2UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_PR_Msk 0x4UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_PW_Pos 3UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_PW_Msk 0x8UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_NS_Pos 4UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_NS_Msk 0x10UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_UR_Pos 8UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_UR_Msk 0x100UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_UW_Pos 9UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_UW_Msk 0x200UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_PR_Pos 10UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_PR_Msk 0x400UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_PW_Pos 11UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_PW_Msk 0x800UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_NS_Pos 12UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_NS_Msk 0x1000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_UR_Pos 16UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_UR_Msk 0x10000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_UW_Pos 17UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_UW_Msk 0x20000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_PR_Pos 18UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_PR_Msk 0x40000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_PW_Pos 19UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_PW_Msk 0x80000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_NS_Pos 20UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_NS_Msk 0x100000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_UR_Pos 24UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_UW_Pos 25UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_PR_Pos 26UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_PW_Pos 27UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_NS_Pos 28UL
+#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_PR.MS_ADDR */
+#define PERI_MS_PPU_PR_V2_MS_ADDR_ADDR26_Pos 6UL
+#define PERI_MS_PPU_PR_V2_MS_ADDR_ADDR26_Msk 0xFFFFFFC0UL
+/* PERI_MS_PPU_PR.MS_SIZE */
+#define PERI_MS_PPU_PR_V2_MS_SIZE_REGION_SIZE_Pos 24UL
+#define PERI_MS_PPU_PR_V2_MS_SIZE_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_MS_PPU_PR_V2_MS_SIZE_VALID_Pos 31UL
+#define PERI_MS_PPU_PR_V2_MS_SIZE_VALID_Msk 0x80000000UL
+/* PERI_MS_PPU_PR.MS_ATT0 */
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_UR_Pos 0UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_UR_Msk 0x1UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_UW_Pos 1UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_UW_Msk 0x2UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_PR_Pos 2UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_PR_Msk 0x4UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_PW_Pos 3UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_PW_Msk 0x8UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_NS_Pos 4UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_NS_Msk 0x10UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UR_Pos 8UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UR_Msk 0x100UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UW_Pos 9UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UW_Msk 0x200UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_PR_Pos 10UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_PR_Msk 0x400UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_PW_Pos 11UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_PW_Msk 0x800UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_NS_Pos 12UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_NS_Msk 0x1000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_UR_Pos 16UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_UR_Msk 0x10000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_UW_Pos 17UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_UW_Msk 0x20000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_PR_Pos 18UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_PR_Msk 0x40000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_PW_Pos 19UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_PW_Msk 0x80000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_NS_Pos 20UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_NS_Msk 0x100000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_UR_Pos 24UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_UW_Pos 25UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_PR_Pos 26UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_PW_Pos 27UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_NS_Pos 28UL
+#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_PR.MS_ATT1 */
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_UR_Pos 0UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_UR_Msk 0x1UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_UW_Pos 1UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_UW_Msk 0x2UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_PR_Pos 2UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_PR_Msk 0x4UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_PW_Pos 3UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_PW_Msk 0x8UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_NS_Pos 4UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_NS_Msk 0x10UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_UR_Pos 8UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_UR_Msk 0x100UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_UW_Pos 9UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_UW_Msk 0x200UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_PR_Pos 10UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_PR_Msk 0x400UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_PW_Pos 11UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_PW_Msk 0x800UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_NS_Pos 12UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_NS_Msk 0x1000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_UR_Pos 16UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_UR_Msk 0x10000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_UW_Pos 17UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_UW_Msk 0x20000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_PR_Pos 18UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_PR_Msk 0x40000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_PW_Pos 19UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_PW_Msk 0x80000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_NS_Pos 20UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_NS_Msk 0x100000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_UR_Pos 24UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_UW_Pos 25UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_PR_Pos 26UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_PW_Pos 27UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_NS_Pos 28UL
+#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_PR.MS_ATT2 */
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_UR_Pos 0UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_UR_Msk 0x1UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_UW_Pos 1UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_UW_Msk 0x2UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_PR_Pos 2UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_PR_Msk 0x4UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_PW_Pos 3UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_PW_Msk 0x8UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_NS_Pos 4UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_NS_Msk 0x10UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_UR_Pos 8UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_UR_Msk 0x100UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_UW_Pos 9UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_UW_Msk 0x200UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_PR_Pos 10UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_PR_Msk 0x400UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_PW_Pos 11UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_PW_Msk 0x800UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_NS_Pos 12UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_NS_Msk 0x1000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_UR_Pos 16UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_UR_Msk 0x10000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_UW_Pos 17UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_UW_Msk 0x20000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_PR_Pos 18UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_PR_Msk 0x40000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_PW_Pos 19UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_PW_Msk 0x80000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_NS_Pos 20UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_NS_Msk 0x100000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_UR_Pos 24UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_UW_Pos 25UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_PR_Pos 26UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_PW_Pos 27UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_NS_Pos 28UL
+#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_PR.MS_ATT3 */
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_UR_Pos 0UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_UR_Msk 0x1UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_UW_Pos 1UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_UW_Msk 0x2UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_PR_Pos 2UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_PR_Msk 0x4UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_PW_Pos 3UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_PW_Msk 0x8UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_NS_Pos 4UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_NS_Msk 0x10UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_UR_Pos 8UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_UR_Msk 0x100UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_UW_Pos 9UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_UW_Msk 0x200UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_PR_Pos 10UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_PR_Msk 0x400UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_PW_Pos 11UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_PW_Msk 0x800UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_NS_Pos 12UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_NS_Msk 0x1000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_UR_Pos 16UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_UR_Msk 0x10000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_UW_Pos 17UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_UW_Msk 0x20000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_PR_Pos 18UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_PR_Msk 0x40000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_PW_Pos 19UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_PW_Msk 0x80000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_NS_Pos 20UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_NS_Msk 0x100000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_UR_Pos 24UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_UW_Pos 25UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_PR_Pos 26UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_PW_Pos 27UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_NS_Pos 28UL
+#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_NS_Msk 0x10000000UL
+
+
+/* PERI_MS_PPU_FX.SL_ADDR */
+#define PERI_MS_PPU_FX_V2_SL_ADDR_ADDR30_Pos 2UL
+#define PERI_MS_PPU_FX_V2_SL_ADDR_ADDR30_Msk 0xFFFFFFFCUL
+/* PERI_MS_PPU_FX.SL_SIZE */
+#define PERI_MS_PPU_FX_V2_SL_SIZE_REGION_SIZE_Pos 24UL
+#define PERI_MS_PPU_FX_V2_SL_SIZE_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_MS_PPU_FX_V2_SL_SIZE_VALID_Pos 31UL
+#define PERI_MS_PPU_FX_V2_SL_SIZE_VALID_Msk 0x80000000UL
+/* PERI_MS_PPU_FX.SL_ATT0 */
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_UR_Pos 0UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_UR_Msk 0x1UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_UW_Pos 1UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_UW_Msk 0x2UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_PR_Pos 2UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_PR_Msk 0x4UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_PW_Pos 3UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_PW_Msk 0x8UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_NS_Pos 4UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_NS_Msk 0x10UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_UR_Pos 8UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_UR_Msk 0x100UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_UW_Pos 9UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_UW_Msk 0x200UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_PR_Pos 10UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_PR_Msk 0x400UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_PW_Pos 11UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_PW_Msk 0x800UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_NS_Pos 12UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_NS_Msk 0x1000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_UR_Pos 16UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_UR_Msk 0x10000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_UW_Pos 17UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_UW_Msk 0x20000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_PR_Pos 18UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_PR_Msk 0x40000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_PW_Pos 19UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_PW_Msk 0x80000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_NS_Pos 20UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_NS_Msk 0x100000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_UR_Pos 24UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_UW_Pos 25UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_PR_Pos 26UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_PW_Pos 27UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_NS_Pos 28UL
+#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_FX.SL_ATT1 */
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_UR_Pos 0UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_UR_Msk 0x1UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_UW_Pos 1UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_UW_Msk 0x2UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_PR_Pos 2UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_PR_Msk 0x4UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_PW_Pos 3UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_PW_Msk 0x8UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_NS_Pos 4UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_NS_Msk 0x10UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_UR_Pos 8UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_UR_Msk 0x100UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_UW_Pos 9UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_UW_Msk 0x200UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_PR_Pos 10UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_PR_Msk 0x400UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_PW_Pos 11UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_PW_Msk 0x800UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_NS_Pos 12UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_NS_Msk 0x1000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_UR_Pos 16UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_UR_Msk 0x10000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_UW_Pos 17UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_UW_Msk 0x20000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_PR_Pos 18UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_PR_Msk 0x40000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_PW_Pos 19UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_PW_Msk 0x80000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_NS_Pos 20UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_NS_Msk 0x100000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_UR_Pos 24UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_UW_Pos 25UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_PR_Pos 26UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_PW_Pos 27UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_NS_Pos 28UL
+#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_FX.SL_ATT2 */
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_UR_Pos 0UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_UR_Msk 0x1UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_UW_Pos 1UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_UW_Msk 0x2UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_PR_Pos 2UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_PR_Msk 0x4UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_PW_Pos 3UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_PW_Msk 0x8UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_NS_Pos 4UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_NS_Msk 0x10UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_UR_Pos 8UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_UR_Msk 0x100UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_UW_Pos 9UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_UW_Msk 0x200UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_PR_Pos 10UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_PR_Msk 0x400UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_PW_Pos 11UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_PW_Msk 0x800UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_NS_Pos 12UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_NS_Msk 0x1000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_UR_Pos 16UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_UR_Msk 0x10000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_UW_Pos 17UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_UW_Msk 0x20000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_PR_Pos 18UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_PR_Msk 0x40000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_PW_Pos 19UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_PW_Msk 0x80000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_NS_Pos 20UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_NS_Msk 0x100000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_UR_Pos 24UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_UW_Pos 25UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_PR_Pos 26UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_PW_Pos 27UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_NS_Pos 28UL
+#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_FX.SL_ATT3 */
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_UR_Pos 0UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_UR_Msk 0x1UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_UW_Pos 1UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_UW_Msk 0x2UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_PR_Pos 2UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_PR_Msk 0x4UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_PW_Pos 3UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_PW_Msk 0x8UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_NS_Pos 4UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_NS_Msk 0x10UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_UR_Pos 8UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_UR_Msk 0x100UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_UW_Pos 9UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_UW_Msk 0x200UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_PR_Pos 10UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_PR_Msk 0x400UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_PW_Pos 11UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_PW_Msk 0x800UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_NS_Pos 12UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_NS_Msk 0x1000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_UR_Pos 16UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_UR_Msk 0x10000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_UW_Pos 17UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_UW_Msk 0x20000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_PR_Pos 18UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_PR_Msk 0x40000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_PW_Pos 19UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_PW_Msk 0x80000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_NS_Pos 20UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_NS_Msk 0x100000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_UR_Pos 24UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_UW_Pos 25UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_PR_Pos 26UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_PW_Pos 27UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_NS_Pos 28UL
+#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_FX.MS_ADDR */
+#define PERI_MS_PPU_FX_V2_MS_ADDR_ADDR26_Pos 6UL
+#define PERI_MS_PPU_FX_V2_MS_ADDR_ADDR26_Msk 0xFFFFFFC0UL
+/* PERI_MS_PPU_FX.MS_SIZE */
+#define PERI_MS_PPU_FX_V2_MS_SIZE_REGION_SIZE_Pos 24UL
+#define PERI_MS_PPU_FX_V2_MS_SIZE_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_MS_PPU_FX_V2_MS_SIZE_VALID_Pos 31UL
+#define PERI_MS_PPU_FX_V2_MS_SIZE_VALID_Msk 0x80000000UL
+/* PERI_MS_PPU_FX.MS_ATT0 */
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_UR_Pos 0UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_UR_Msk 0x1UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_UW_Pos 1UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_UW_Msk 0x2UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_PR_Pos 2UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_PR_Msk 0x4UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_PW_Pos 3UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_PW_Msk 0x8UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_NS_Pos 4UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_NS_Msk 0x10UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_UR_Pos 8UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_UR_Msk 0x100UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_UW_Pos 9UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_UW_Msk 0x200UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_PR_Pos 10UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_PR_Msk 0x400UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_PW_Pos 11UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_PW_Msk 0x800UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_NS_Pos 12UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_NS_Msk 0x1000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_UR_Pos 16UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_UR_Msk 0x10000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_UW_Pos 17UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_UW_Msk 0x20000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_PR_Pos 18UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_PR_Msk 0x40000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_PW_Pos 19UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_PW_Msk 0x80000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_NS_Pos 20UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_NS_Msk 0x100000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_UR_Pos 24UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_UW_Pos 25UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_PR_Pos 26UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_PW_Pos 27UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_NS_Pos 28UL
+#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_FX.MS_ATT1 */
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_UR_Pos 0UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_UR_Msk 0x1UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_UW_Pos 1UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_UW_Msk 0x2UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_PR_Pos 2UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_PR_Msk 0x4UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_PW_Pos 3UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_PW_Msk 0x8UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_NS_Pos 4UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_NS_Msk 0x10UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_UR_Pos 8UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_UR_Msk 0x100UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_UW_Pos 9UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_UW_Msk 0x200UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_PR_Pos 10UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_PR_Msk 0x400UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_PW_Pos 11UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_PW_Msk 0x800UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_NS_Pos 12UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_NS_Msk 0x1000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_UR_Pos 16UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_UR_Msk 0x10000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_UW_Pos 17UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_UW_Msk 0x20000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_PR_Pos 18UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_PR_Msk 0x40000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_PW_Pos 19UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_PW_Msk 0x80000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_NS_Pos 20UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_NS_Msk 0x100000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_UR_Pos 24UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_UW_Pos 25UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_PR_Pos 26UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_PW_Pos 27UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_NS_Pos 28UL
+#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_FX.MS_ATT2 */
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_UR_Pos 0UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_UR_Msk 0x1UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_UW_Pos 1UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_UW_Msk 0x2UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_PR_Pos 2UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_PR_Msk 0x4UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_PW_Pos 3UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_PW_Msk 0x8UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_NS_Pos 4UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_NS_Msk 0x10UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_UR_Pos 8UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_UR_Msk 0x100UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_UW_Pos 9UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_UW_Msk 0x200UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_PR_Pos 10UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_PR_Msk 0x400UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_PW_Pos 11UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_PW_Msk 0x800UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_NS_Pos 12UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_NS_Msk 0x1000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_UR_Pos 16UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_UR_Msk 0x10000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_UW_Pos 17UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_UW_Msk 0x20000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_PR_Pos 18UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_PR_Msk 0x40000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_PW_Pos 19UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_PW_Msk 0x80000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_NS_Pos 20UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_NS_Msk 0x100000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_UR_Pos 24UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_UW_Pos 25UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_PR_Pos 26UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_PW_Pos 27UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_NS_Pos 28UL
+#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_NS_Msk 0x10000000UL
+/* PERI_MS_PPU_FX.MS_ATT3 */
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_UR_Pos 0UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_UR_Msk 0x1UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_UW_Pos 1UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_UW_Msk 0x2UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_PR_Pos 2UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_PR_Msk 0x4UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_PW_Pos 3UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_PW_Msk 0x8UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_NS_Pos 4UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_NS_Msk 0x10UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_UR_Pos 8UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_UR_Msk 0x100UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_UW_Pos 9UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_UW_Msk 0x200UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_PR_Pos 10UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_PR_Msk 0x400UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_PW_Pos 11UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_PW_Msk 0x800UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_NS_Pos 12UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_NS_Msk 0x1000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_UR_Pos 16UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_UR_Msk 0x10000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_UW_Pos 17UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_UW_Msk 0x20000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_PR_Pos 18UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_PR_Msk 0x40000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_PW_Pos 19UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_PW_Msk 0x80000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_NS_Pos 20UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_NS_Msk 0x100000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_UR_Pos 24UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_UR_Msk 0x1000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_UW_Pos 25UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_UW_Msk 0x2000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_PR_Pos 26UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_PR_Msk 0x4000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_PW_Pos 27UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_PW_Msk 0x8000000UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_NS_Pos 28UL
+#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_NS_Msk 0x10000000UL
+
+
+#endif /* _CYIP_PERI_MS_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_peri_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_peri_v2.h
new file mode 100644
index 0000000000..1eb63a6c0d
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_peri_v2.h
@@ -0,0 +1,254 @@
+/***************************************************************************//**
+* \file cyip_peri_v2.h
+*
+* \brief
+* PERI IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_PERI_V2_H_
+#define _CYIP_PERI_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* PERI
+*******************************************************************************/
+
+#define PERI_GR_V2_SECTION_SIZE 0x00000020UL
+#define PERI_TR_GR_V2_SECTION_SIZE 0x00000400UL
+#define PERI_TR_1TO1_GR_V2_SECTION_SIZE 0x00000400UL
+#define PERI_V2_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Peripheral group structure (PERI_GR)
+ */
+typedef struct {
+ __IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t SL_CTL; /*!< 0x00000010 Slave control */
+ __IM uint32_t RESERVED1[3];
+} PERI_GR_V2_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief Trigger group (PERI_TR_GR)
+ */
+typedef struct {
+ __IOM uint32_t TR_CTL[256]; /*!< 0x00000000 Trigger control register */
+} PERI_TR_GR_V2_Type; /*!< Size = 1024 (0x400) */
+
+/**
+ * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR)
+ */
+typedef struct {
+ __IOM uint32_t TR_CTL[256]; /*!< 0x00000000 Trigger control register */
+} PERI_TR_1TO1_GR_V2_Type; /*!< Size = 1024 (0x400) */
+
+/**
+ * \brief Peripheral interconnect (PERI)
+ */
+typedef struct {
+ __IM uint32_t RESERVED[128];
+ __IOM uint32_t TIMEOUT_CTL; /*!< 0x00000200 Timeout control */
+ __IM uint32_t RESERVED1[7];
+ __IOM uint32_t TR_CMD; /*!< 0x00000220 Trigger command */
+ __IM uint32_t RESERVED2[119];
+ __IOM uint32_t DIV_CMD; /*!< 0x00000400 Divider command */
+ __IM uint32_t RESERVED3[511];
+ __IOM uint32_t CLOCK_CTL[256]; /*!< 0x00000C00 Clock control */
+ __IOM uint32_t DIV_8_CTL[256]; /*!< 0x00001000 Divider control (for 8.0 divider) */
+ __IOM uint32_t DIV_16_CTL[256]; /*!< 0x00001400 Divider control (for 16.0 divider) */
+ __IOM uint32_t DIV_16_5_CTL[256]; /*!< 0x00001800 Divider control (for 16.5 divider) */
+ __IOM uint32_t DIV_24_5_CTL[255]; /*!< 0x00001C00 Divider control (for 24.5 divider) */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t ECC_CTL; /*!< 0x00002000 ECC control */
+ __IM uint32_t RESERVED5[2047];
+ PERI_GR_V2_Type GR[16]; /*!< 0x00004000 Peripheral group structure */
+ __IM uint32_t RESERVED6[3968];
+ PERI_TR_GR_V2_Type TR_GR[16]; /*!< 0x00008000 Trigger group */
+ PERI_TR_1TO1_GR_V2_Type TR_1TO1_GR[16]; /*!< 0x0000C000 Trigger 1-to-1 group */
+} PERI_V2_Type; /*!< Size = 65536 (0x10000) */
+
+
+/* PERI_GR.CLOCK_CTL */
+#define PERI_GR_V2_CLOCK_CTL_INT8_DIV_Pos 8UL
+#define PERI_GR_V2_CLOCK_CTL_INT8_DIV_Msk 0xFF00UL
+/* PERI_GR.SL_CTL */
+#define PERI_GR_V2_SL_CTL_ENABLED_0_Pos 0UL
+#define PERI_GR_V2_SL_CTL_ENABLED_0_Msk 0x1UL
+#define PERI_GR_V2_SL_CTL_ENABLED_1_Pos 1UL
+#define PERI_GR_V2_SL_CTL_ENABLED_1_Msk 0x2UL
+#define PERI_GR_V2_SL_CTL_ENABLED_2_Pos 2UL
+#define PERI_GR_V2_SL_CTL_ENABLED_2_Msk 0x4UL
+#define PERI_GR_V2_SL_CTL_ENABLED_3_Pos 3UL
+#define PERI_GR_V2_SL_CTL_ENABLED_3_Msk 0x8UL
+#define PERI_GR_V2_SL_CTL_ENABLED_4_Pos 4UL
+#define PERI_GR_V2_SL_CTL_ENABLED_4_Msk 0x10UL
+#define PERI_GR_V2_SL_CTL_ENABLED_5_Pos 5UL
+#define PERI_GR_V2_SL_CTL_ENABLED_5_Msk 0x20UL
+#define PERI_GR_V2_SL_CTL_ENABLED_6_Pos 6UL
+#define PERI_GR_V2_SL_CTL_ENABLED_6_Msk 0x40UL
+#define PERI_GR_V2_SL_CTL_ENABLED_7_Pos 7UL
+#define PERI_GR_V2_SL_CTL_ENABLED_7_Msk 0x80UL
+#define PERI_GR_V2_SL_CTL_ENABLED_8_Pos 8UL
+#define PERI_GR_V2_SL_CTL_ENABLED_8_Msk 0x100UL
+#define PERI_GR_V2_SL_CTL_ENABLED_9_Pos 9UL
+#define PERI_GR_V2_SL_CTL_ENABLED_9_Msk 0x200UL
+#define PERI_GR_V2_SL_CTL_ENABLED_10_Pos 10UL
+#define PERI_GR_V2_SL_CTL_ENABLED_10_Msk 0x400UL
+#define PERI_GR_V2_SL_CTL_ENABLED_11_Pos 11UL
+#define PERI_GR_V2_SL_CTL_ENABLED_11_Msk 0x800UL
+#define PERI_GR_V2_SL_CTL_ENABLED_12_Pos 12UL
+#define PERI_GR_V2_SL_CTL_ENABLED_12_Msk 0x1000UL
+#define PERI_GR_V2_SL_CTL_ENABLED_13_Pos 13UL
+#define PERI_GR_V2_SL_CTL_ENABLED_13_Msk 0x2000UL
+#define PERI_GR_V2_SL_CTL_ENABLED_14_Pos 14UL
+#define PERI_GR_V2_SL_CTL_ENABLED_14_Msk 0x4000UL
+#define PERI_GR_V2_SL_CTL_ENABLED_15_Pos 15UL
+#define PERI_GR_V2_SL_CTL_ENABLED_15_Msk 0x8000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_0_Pos 16UL
+#define PERI_GR_V2_SL_CTL_DISABLED_0_Msk 0x10000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_1_Pos 17UL
+#define PERI_GR_V2_SL_CTL_DISABLED_1_Msk 0x20000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_2_Pos 18UL
+#define PERI_GR_V2_SL_CTL_DISABLED_2_Msk 0x40000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_3_Pos 19UL
+#define PERI_GR_V2_SL_CTL_DISABLED_3_Msk 0x80000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_4_Pos 20UL
+#define PERI_GR_V2_SL_CTL_DISABLED_4_Msk 0x100000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_5_Pos 21UL
+#define PERI_GR_V2_SL_CTL_DISABLED_5_Msk 0x200000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_6_Pos 22UL
+#define PERI_GR_V2_SL_CTL_DISABLED_6_Msk 0x400000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_7_Pos 23UL
+#define PERI_GR_V2_SL_CTL_DISABLED_7_Msk 0x800000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_8_Pos 24UL
+#define PERI_GR_V2_SL_CTL_DISABLED_8_Msk 0x1000000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_9_Pos 25UL
+#define PERI_GR_V2_SL_CTL_DISABLED_9_Msk 0x2000000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_10_Pos 26UL
+#define PERI_GR_V2_SL_CTL_DISABLED_10_Msk 0x4000000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_11_Pos 27UL
+#define PERI_GR_V2_SL_CTL_DISABLED_11_Msk 0x8000000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_12_Pos 28UL
+#define PERI_GR_V2_SL_CTL_DISABLED_12_Msk 0x10000000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_13_Pos 29UL
+#define PERI_GR_V2_SL_CTL_DISABLED_13_Msk 0x20000000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_14_Pos 30UL
+#define PERI_GR_V2_SL_CTL_DISABLED_14_Msk 0x40000000UL
+#define PERI_GR_V2_SL_CTL_DISABLED_15_Pos 31UL
+#define PERI_GR_V2_SL_CTL_DISABLED_15_Msk 0x80000000UL
+
+
+/* PERI_TR_GR.TR_CTL */
+#define PERI_TR_GR_V2_TR_CTL_TR_SEL_Pos 0UL
+#define PERI_TR_GR_V2_TR_CTL_TR_SEL_Msk 0xFFUL
+#define PERI_TR_GR_V2_TR_CTL_TR_INV_Pos 8UL
+#define PERI_TR_GR_V2_TR_CTL_TR_INV_Msk 0x100UL
+#define PERI_TR_GR_V2_TR_CTL_TR_EDGE_Pos 9UL
+#define PERI_TR_GR_V2_TR_CTL_TR_EDGE_Msk 0x200UL
+#define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos 12UL
+#define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk 0x1000UL
+
+
+/* PERI_TR_1TO1_GR.TR_CTL */
+#define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Pos 0UL
+#define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Msk 0x1UL
+#define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Pos 8UL
+#define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Msk 0x100UL
+#define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Pos 9UL
+#define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Msk 0x200UL
+#define PERI_TR_1TO1_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos 12UL
+#define PERI_TR_1TO1_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk 0x1000UL
+
+
+/* PERI.TIMEOUT_CTL */
+#define PERI_V2_TIMEOUT_CTL_TIMEOUT_Pos 0UL
+#define PERI_V2_TIMEOUT_CTL_TIMEOUT_Msk 0xFFFFUL
+/* PERI.TR_CMD */
+#define PERI_V2_TR_CMD_TR_SEL_Pos 0UL
+#define PERI_V2_TR_CMD_TR_SEL_Msk 0xFFUL
+#define PERI_V2_TR_CMD_GROUP_SEL_Pos 8UL
+#define PERI_V2_TR_CMD_GROUP_SEL_Msk 0x1F00UL
+#define PERI_V2_TR_CMD_TR_EDGE_Pos 29UL
+#define PERI_V2_TR_CMD_TR_EDGE_Msk 0x20000000UL
+#define PERI_V2_TR_CMD_OUT_SEL_Pos 30UL
+#define PERI_V2_TR_CMD_OUT_SEL_Msk 0x40000000UL
+#define PERI_V2_TR_CMD_ACTIVATE_Pos 31UL
+#define PERI_V2_TR_CMD_ACTIVATE_Msk 0x80000000UL
+/* PERI.DIV_CMD */
+#define PERI_V2_DIV_CMD_DIV_SEL_Pos 0UL
+#define PERI_V2_DIV_CMD_DIV_SEL_Msk 0xFFUL
+#define PERI_V2_DIV_CMD_TYPE_SEL_Pos 8UL
+#define PERI_V2_DIV_CMD_TYPE_SEL_Msk 0x300UL
+#define PERI_V2_DIV_CMD_PA_DIV_SEL_Pos 16UL
+#define PERI_V2_DIV_CMD_PA_DIV_SEL_Msk 0xFF0000UL
+#define PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos 24UL
+#define PERI_V2_DIV_CMD_PA_TYPE_SEL_Msk 0x3000000UL
+#define PERI_V2_DIV_CMD_DISABLE_Pos 30UL
+#define PERI_V2_DIV_CMD_DISABLE_Msk 0x40000000UL
+#define PERI_V2_DIV_CMD_ENABLE_Pos 31UL
+#define PERI_V2_DIV_CMD_ENABLE_Msk 0x80000000UL
+/* PERI.CLOCK_CTL */
+#define PERI_V2_CLOCK_CTL_DIV_SEL_Pos 0UL
+#define PERI_V2_CLOCK_CTL_DIV_SEL_Msk 0xFFUL
+#define PERI_V2_CLOCK_CTL_TYPE_SEL_Pos 8UL
+#define PERI_V2_CLOCK_CTL_TYPE_SEL_Msk 0x300UL
+/* PERI.DIV_8_CTL */
+#define PERI_V2_DIV_8_CTL_EN_Pos 0UL
+#define PERI_V2_DIV_8_CTL_EN_Msk 0x1UL
+#define PERI_V2_DIV_8_CTL_INT8_DIV_Pos 8UL
+#define PERI_V2_DIV_8_CTL_INT8_DIV_Msk 0xFF00UL
+/* PERI.DIV_16_CTL */
+#define PERI_V2_DIV_16_CTL_EN_Pos 0UL
+#define PERI_V2_DIV_16_CTL_EN_Msk 0x1UL
+#define PERI_V2_DIV_16_CTL_INT16_DIV_Pos 8UL
+#define PERI_V2_DIV_16_CTL_INT16_DIV_Msk 0xFFFF00UL
+/* PERI.DIV_16_5_CTL */
+#define PERI_V2_DIV_16_5_CTL_EN_Pos 0UL
+#define PERI_V2_DIV_16_5_CTL_EN_Msk 0x1UL
+#define PERI_V2_DIV_16_5_CTL_FRAC5_DIV_Pos 3UL
+#define PERI_V2_DIV_16_5_CTL_FRAC5_DIV_Msk 0xF8UL
+#define PERI_V2_DIV_16_5_CTL_INT16_DIV_Pos 8UL
+#define PERI_V2_DIV_16_5_CTL_INT16_DIV_Msk 0xFFFF00UL
+/* PERI.DIV_24_5_CTL */
+#define PERI_V2_DIV_24_5_CTL_EN_Pos 0UL
+#define PERI_V2_DIV_24_5_CTL_EN_Msk 0x1UL
+#define PERI_V2_DIV_24_5_CTL_FRAC5_DIV_Pos 3UL
+#define PERI_V2_DIV_24_5_CTL_FRAC5_DIV_Msk 0xF8UL
+#define PERI_V2_DIV_24_5_CTL_INT24_DIV_Pos 8UL
+#define PERI_V2_DIV_24_5_CTL_INT24_DIV_Msk 0xFFFFFF00UL
+/* PERI.ECC_CTL */
+#define PERI_V2_ECC_CTL_WORD_ADDR_Pos 0UL
+#define PERI_V2_ECC_CTL_WORD_ADDR_Msk 0x7FFUL
+#define PERI_V2_ECC_CTL_ECC_EN_Pos 16UL
+#define PERI_V2_ECC_CTL_ECC_EN_Msk 0x10000UL
+#define PERI_V2_ECC_CTL_ECC_INJ_EN_Pos 18UL
+#define PERI_V2_ECC_CTL_ECC_INJ_EN_Msk 0x40000UL
+#define PERI_V2_ECC_CTL_PARITY_Pos 24UL
+#define PERI_V2_ECC_CTL_PARITY_Msk 0xFF000000UL
+
+
+#endif /* _CYIP_PERI_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_profile.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_profile.h
new file mode 100644
index 0000000000..8c21eb24b5
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_profile.h
@@ -0,0 +1,114 @@
+/***************************************************************************//**
+* \file cyip_profile.h
+*
+* \brief
+* PROFILE IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_PROFILE_H_
+#define _CYIP_PROFILE_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* PROFILE
+*******************************************************************************/
+
+#define PROFILE_CNT_STRUCT_SECTION_SIZE 0x00000010UL
+#define PROFILE_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Profile counter structure (PROFILE_CNT_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Profile counter configuration */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t CNT; /*!< 0x00000008 Profile counter value */
+ __IM uint32_t RESERVED1;
+} PROFILE_CNT_STRUCT_V1_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * \brief Energy Profiler IP (PROFILE)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Profile control */
+ __IM uint32_t STATUS; /*!< 0x00000004 Profile status */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t CMD; /*!< 0x00000010 Profile command */
+ __IM uint32_t RESERVED1[491];
+ __IOM uint32_t INTR; /*!< 0x000007C0 Profile interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x000007C4 Profile interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Profile interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x000007CC Profile interrupt masked */
+ __IM uint32_t RESERVED2[12];
+ PROFILE_CNT_STRUCT_V1_Type CNT_STRUCT[16]; /*!< 0x00000800 Profile counter structure */
+} PROFILE_V1_Type; /*!< Size = 2304 (0x900) */
+
+
+/* PROFILE_CNT_STRUCT.CTL */
+#define PROFILE_CNT_STRUCT_CTL_CNT_DURATION_Pos 0UL
+#define PROFILE_CNT_STRUCT_CTL_CNT_DURATION_Msk 0x1UL
+#define PROFILE_CNT_STRUCT_CTL_REF_CLK_SEL_Pos 4UL
+#define PROFILE_CNT_STRUCT_CTL_REF_CLK_SEL_Msk 0x70UL
+#define PROFILE_CNT_STRUCT_CTL_MON_SEL_Pos 16UL
+#define PROFILE_CNT_STRUCT_CTL_MON_SEL_Msk 0x7F0000UL
+#define PROFILE_CNT_STRUCT_CTL_ENABLED_Pos 31UL
+#define PROFILE_CNT_STRUCT_CTL_ENABLED_Msk 0x80000000UL
+/* PROFILE_CNT_STRUCT.CNT */
+#define PROFILE_CNT_STRUCT_CNT_CNT_Pos 0UL
+#define PROFILE_CNT_STRUCT_CNT_CNT_Msk 0xFFFFFFFFUL
+
+
+/* PROFILE.CTL */
+#define PROFILE_CTL_WIN_MODE_Pos 0UL
+#define PROFILE_CTL_WIN_MODE_Msk 0x1UL
+#define PROFILE_CTL_ENABLED_Pos 31UL
+#define PROFILE_CTL_ENABLED_Msk 0x80000000UL
+/* PROFILE.STATUS */
+#define PROFILE_STATUS_WIN_ACTIVE_Pos 0UL
+#define PROFILE_STATUS_WIN_ACTIVE_Msk 0x1UL
+/* PROFILE.CMD */
+#define PROFILE_CMD_START_TR_Pos 0UL
+#define PROFILE_CMD_START_TR_Msk 0x1UL
+#define PROFILE_CMD_STOP_TR_Pos 1UL
+#define PROFILE_CMD_STOP_TR_Msk 0x2UL
+#define PROFILE_CMD_CLR_ALL_CNT_Pos 8UL
+#define PROFILE_CMD_CLR_ALL_CNT_Msk 0x100UL
+/* PROFILE.INTR */
+#define PROFILE_INTR_CNT_OVFLW_Pos 0UL
+#define PROFILE_INTR_CNT_OVFLW_Msk 0xFFFFFFFFUL
+/* PROFILE.INTR_SET */
+#define PROFILE_INTR_SET_CNT_OVFLW_Pos 0UL
+#define PROFILE_INTR_SET_CNT_OVFLW_Msk 0xFFFFFFFFUL
+/* PROFILE.INTR_MASK */
+#define PROFILE_INTR_MASK_CNT_OVFLW_Pos 0UL
+#define PROFILE_INTR_MASK_CNT_OVFLW_Msk 0xFFFFFFFFUL
+/* PROFILE.INTR_MASKED */
+#define PROFILE_INTR_MASKED_CNT_OVFLW_Pos 0UL
+#define PROFILE_INTR_MASKED_CNT_OVFLW_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_PROFILE_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_prot.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_prot.h
new file mode 100644
index 0000000000..c9832c9410
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_prot.h
@@ -0,0 +1,388 @@
+/***************************************************************************//**
+* \file cyip_prot.h
+*
+* \brief
+* PROT IP definitions
+*
+* \note
+* Generator version: 1.5.0.1287
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_PROT_H_
+#define _CYIP_PROT_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* PROT
+*******************************************************************************/
+
+#define PROT_SMPU_SMPU_STRUCT_SECTION_SIZE 0x00000040UL
+#define PROT_SMPU_SECTION_SIZE 0x00004000UL
+#define PROT_MPU_MPU_STRUCT_SECTION_SIZE 0x00000020UL
+#define PROT_MPU_SECTION_SIZE 0x00000400UL
+#define PROT_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t ADDR0; /*!< 0x00000000 SMPU region address 0 (slave structure) */
+ __IOM uint32_t ATT0; /*!< 0x00000004 SMPU region attributes 0 (slave structure) */
+ __IM uint32_t RESERVED[6];
+ __IM uint32_t ADDR1; /*!< 0x00000020 SMPU region address 1 (master structure) */
+ __IOM uint32_t ATT1; /*!< 0x00000024 SMPU region attributes 1 (master structure) */
+ __IM uint32_t RESERVED1[6];
+} PROT_SMPU_SMPU_STRUCT_V1_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief SMPU (PROT_SMPU)
+ */
+typedef struct {
+ __IOM uint32_t MS0_CTL; /*!< 0x00000000 Master 0 protection context control */
+ __IOM uint32_t MS1_CTL; /*!< 0x00000004 Master 1 protection context control */
+ __IOM uint32_t MS2_CTL; /*!< 0x00000008 Master 2 protection context control */
+ __IOM uint32_t MS3_CTL; /*!< 0x0000000C Master 3 protection context control */
+ __IOM uint32_t MS4_CTL; /*!< 0x00000010 Master 4 protection context control */
+ __IOM uint32_t MS5_CTL; /*!< 0x00000014 Master 5 protection context control */
+ __IOM uint32_t MS6_CTL; /*!< 0x00000018 Master 6 protection context control */
+ __IOM uint32_t MS7_CTL; /*!< 0x0000001C Master 7 protection context control */
+ __IOM uint32_t MS8_CTL; /*!< 0x00000020 Master 8 protection context control */
+ __IOM uint32_t MS9_CTL; /*!< 0x00000024 Master 9 protection context control */
+ __IOM uint32_t MS10_CTL; /*!< 0x00000028 Master 10 protection context control */
+ __IOM uint32_t MS11_CTL; /*!< 0x0000002C Master 11 protection context control */
+ __IOM uint32_t MS12_CTL; /*!< 0x00000030 Master 12 protection context control */
+ __IOM uint32_t MS13_CTL; /*!< 0x00000034 Master 13 protection context control */
+ __IOM uint32_t MS14_CTL; /*!< 0x00000038 Master 14 protection context control */
+ __IOM uint32_t MS15_CTL; /*!< 0x0000003C Master 15 protection context control */
+ __IM uint32_t RESERVED[2032];
+ PROT_SMPU_SMPU_STRUCT_V1_Type SMPU_STRUCT[32]; /*!< 0x00002000 SMPU structure */
+ __IM uint32_t RESERVED1[1536];
+} PROT_SMPU_V1_Type; /*!< Size = 16384 (0x4000) */
+
+/**
+ * \brief MPU structure (PROT_MPU_MPU_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t ADDR; /*!< 0x00000000 MPU region address */
+ __IOM uint32_t ATT; /*!< 0x00000004 MPU region attrributes */
+ __IM uint32_t RESERVED[6];
+} PROT_MPU_MPU_STRUCT_V1_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief MPU (PROT_MPU)
+ */
+typedef struct {
+ __IOM uint32_t MS_CTL; /*!< 0x00000000 Master control */
+ __IM uint32_t MS_CTL_READ_MIR[127]; /*!< 0x00000004 Master control read mirror */
+ PROT_MPU_MPU_STRUCT_V1_Type MPU_STRUCT[16]; /*!< 0x00000200 MPU structure */
+} PROT_MPU_V1_Type; /*!< Size = 1024 (0x400) */
+
+/**
+ * \brief Protection (PROT)
+ */
+typedef struct {
+ PROT_SMPU_V1_Type SMPU; /*!< 0x00000000 SMPU */
+ PROT_MPU_V1_Type CYMPU[16]; /*!< 0x00004000 MPU */
+} PROT_V1_Type; /*!< Size = 32768 (0x8000) */
+
+
+/* PROT_SMPU_SMPU_STRUCT.ADDR0 */
+#define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Pos 0UL
+#define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
+#define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Pos 8UL
+#define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Msk 0xFFFFFF00UL
+/* PROT_SMPU_SMPU_STRUCT.ATT0 */
+#define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Pos 0UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Msk 0x1UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Pos 1UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Msk 0x2UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Pos 2UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Msk 0x4UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Pos 3UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Msk 0x8UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Pos 4UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Msk 0x10UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Pos 5UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Msk 0x20UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Pos 6UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Msk 0x40UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Pos 8UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk 0x100UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Pos 9UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Pos 24UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Msk 0x1F000000UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Pos 30UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Msk 0x40000000UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Pos 31UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Msk 0x80000000UL
+/* PROT_SMPU_SMPU_STRUCT.ADDR1 */
+#define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Pos 0UL
+#define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
+#define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Pos 8UL
+#define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Msk 0xFFFFFF00UL
+/* PROT_SMPU_SMPU_STRUCT.ATT1 */
+#define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Pos 0UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Msk 0x1UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Pos 1UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Msk 0x2UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Pos 2UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk 0x4UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Pos 3UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Msk 0x8UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Pos 4UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Msk 0x10UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Pos 5UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk 0x20UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Pos 6UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Msk 0x40UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Pos 8UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Msk 0x100UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Pos 9UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Pos 24UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Msk 0x1F000000UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Pos 30UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Msk 0x40000000UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Pos 31UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Msk 0x80000000UL
+
+
+/* PROT_SMPU.MS0_CTL */
+#define PROT_SMPU_MS0_CTL_P_Pos 0UL
+#define PROT_SMPU_MS0_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS0_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS0_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS0_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS0_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS0_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS0_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS1_CTL */
+#define PROT_SMPU_MS1_CTL_P_Pos 0UL
+#define PROT_SMPU_MS1_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS1_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS1_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS1_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS1_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS1_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS1_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS2_CTL */
+#define PROT_SMPU_MS2_CTL_P_Pos 0UL
+#define PROT_SMPU_MS2_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS2_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS2_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS2_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS2_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS2_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS2_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS3_CTL */
+#define PROT_SMPU_MS3_CTL_P_Pos 0UL
+#define PROT_SMPU_MS3_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS3_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS3_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS3_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS3_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS3_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS3_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS4_CTL */
+#define PROT_SMPU_MS4_CTL_P_Pos 0UL
+#define PROT_SMPU_MS4_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS4_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS4_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS4_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS4_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS4_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS4_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS5_CTL */
+#define PROT_SMPU_MS5_CTL_P_Pos 0UL
+#define PROT_SMPU_MS5_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS5_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS5_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS5_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS5_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS5_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS5_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS6_CTL */
+#define PROT_SMPU_MS6_CTL_P_Pos 0UL
+#define PROT_SMPU_MS6_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS6_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS6_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS6_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS6_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS6_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS6_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS7_CTL */
+#define PROT_SMPU_MS7_CTL_P_Pos 0UL
+#define PROT_SMPU_MS7_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS7_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS7_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS7_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS7_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS7_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS7_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS8_CTL */
+#define PROT_SMPU_MS8_CTL_P_Pos 0UL
+#define PROT_SMPU_MS8_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS8_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS8_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS8_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS8_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS8_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS8_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS9_CTL */
+#define PROT_SMPU_MS9_CTL_P_Pos 0UL
+#define PROT_SMPU_MS9_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS9_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS9_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS9_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS9_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS9_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS9_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS10_CTL */
+#define PROT_SMPU_MS10_CTL_P_Pos 0UL
+#define PROT_SMPU_MS10_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS10_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS10_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS10_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS10_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS10_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS10_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS11_CTL */
+#define PROT_SMPU_MS11_CTL_P_Pos 0UL
+#define PROT_SMPU_MS11_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS11_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS11_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS11_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS11_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS11_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS11_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS12_CTL */
+#define PROT_SMPU_MS12_CTL_P_Pos 0UL
+#define PROT_SMPU_MS12_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS12_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS12_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS12_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS12_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS12_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS12_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS13_CTL */
+#define PROT_SMPU_MS13_CTL_P_Pos 0UL
+#define PROT_SMPU_MS13_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS13_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS13_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS13_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS13_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS13_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS13_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS14_CTL */
+#define PROT_SMPU_MS14_CTL_P_Pos 0UL
+#define PROT_SMPU_MS14_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS14_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS14_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS14_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS14_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS14_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS14_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS15_CTL */
+#define PROT_SMPU_MS15_CTL_P_Pos 0UL
+#define PROT_SMPU_MS15_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS15_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS15_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS15_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS15_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS15_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS15_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+
+
+/* PROT_MPU_MPU_STRUCT.ADDR */
+#define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Pos 0UL
+#define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Msk 0xFFUL
+#define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Pos 8UL
+#define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Msk 0xFFFFFF00UL
+/* PROT_MPU_MPU_STRUCT.ATT */
+#define PROT_MPU_MPU_STRUCT_ATT_UR_Pos 0UL
+#define PROT_MPU_MPU_STRUCT_ATT_UR_Msk 0x1UL
+#define PROT_MPU_MPU_STRUCT_ATT_UW_Pos 1UL
+#define PROT_MPU_MPU_STRUCT_ATT_UW_Msk 0x2UL
+#define PROT_MPU_MPU_STRUCT_ATT_UX_Pos 2UL
+#define PROT_MPU_MPU_STRUCT_ATT_UX_Msk 0x4UL
+#define PROT_MPU_MPU_STRUCT_ATT_PR_Pos 3UL
+#define PROT_MPU_MPU_STRUCT_ATT_PR_Msk 0x8UL
+#define PROT_MPU_MPU_STRUCT_ATT_PW_Pos 4UL
+#define PROT_MPU_MPU_STRUCT_ATT_PW_Msk 0x10UL
+#define PROT_MPU_MPU_STRUCT_ATT_PX_Pos 5UL
+#define PROT_MPU_MPU_STRUCT_ATT_PX_Msk 0x20UL
+#define PROT_MPU_MPU_STRUCT_ATT_NS_Pos 6UL
+#define PROT_MPU_MPU_STRUCT_ATT_NS_Msk 0x40UL
+#define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Pos 24UL
+#define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Msk 0x1F000000UL
+#define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Pos 31UL
+#define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Msk 0x80000000UL
+
+
+/* PROT_MPU.MS_CTL */
+#define PROT_MPU_MS_CTL_PC_Pos 0UL
+#define PROT_MPU_MS_CTL_PC_Msk 0xFUL
+#define PROT_MPU_MS_CTL_PC_SAVED_Pos 16UL
+#define PROT_MPU_MS_CTL_PC_SAVED_Msk 0xF0000UL
+/* PROT_MPU.MS_CTL_READ_MIR */
+#define PROT_MPU_MS_CTL_READ_MIR_PC_Pos 0UL
+#define PROT_MPU_MS_CTL_READ_MIR_PC_Msk 0xFUL
+#define PROT_MPU_MS_CTL_READ_MIR_PC_SAVED_Pos 16UL
+#define PROT_MPU_MS_CTL_READ_MIR_PC_SAVED_Msk 0xF0000UL
+
+
+#endif /* _CYIP_PROT_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_prot_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_prot_v2.h
new file mode 100644
index 0000000000..194f0ba3b4
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_prot_v2.h
@@ -0,0 +1,388 @@
+/***************************************************************************//**
+* \file cyip_prot_v2.h
+*
+* \brief
+* PROT IP definitions
+*
+* \note
+* Generator version: 1.5.0.1287
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_PROT_V2_H_
+#define _CYIP_PROT_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* PROT
+*******************************************************************************/
+
+#define PROT_SMPU_SMPU_STRUCT_V2_SECTION_SIZE 0x00000040UL
+#define PROT_SMPU_V2_SECTION_SIZE 0x00004000UL
+#define PROT_MPU_MPU_STRUCT_V2_SECTION_SIZE 0x00000020UL
+#define PROT_MPU_V2_SECTION_SIZE 0x00000400UL
+#define PROT_V2_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t ADDR0; /*!< 0x00000000 SMPU region address 0 (slave structure) */
+ __IOM uint32_t ATT0; /*!< 0x00000004 SMPU region attributes 0 (slave structure) */
+ __IM uint32_t RESERVED[6];
+ __IM uint32_t ADDR1; /*!< 0x00000020 SMPU region address 1 (master structure) */
+ __IOM uint32_t ATT1; /*!< 0x00000024 SMPU region attributes 1 (master structure) */
+ __IM uint32_t RESERVED1[6];
+} PROT_SMPU_SMPU_STRUCT_V2_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief SMPU (PROT_SMPU)
+ */
+typedef struct {
+ __IOM uint32_t MS0_CTL; /*!< 0x00000000 Master 0 protection context control */
+ __IOM uint32_t MS1_CTL; /*!< 0x00000004 Master 1 protection context control */
+ __IOM uint32_t MS2_CTL; /*!< 0x00000008 Master 2 protection context control */
+ __IOM uint32_t MS3_CTL; /*!< 0x0000000C Master 3 protection context control */
+ __IOM uint32_t MS4_CTL; /*!< 0x00000010 Master 4 protection context control */
+ __IOM uint32_t MS5_CTL; /*!< 0x00000014 Master 5 protection context control */
+ __IOM uint32_t MS6_CTL; /*!< 0x00000018 Master 6 protection context control */
+ __IOM uint32_t MS7_CTL; /*!< 0x0000001C Master 7 protection context control */
+ __IOM uint32_t MS8_CTL; /*!< 0x00000020 Master 8 protection context control */
+ __IOM uint32_t MS9_CTL; /*!< 0x00000024 Master 9 protection context control */
+ __IOM uint32_t MS10_CTL; /*!< 0x00000028 Master 10 protection context control */
+ __IOM uint32_t MS11_CTL; /*!< 0x0000002C Master 11 protection context control */
+ __IOM uint32_t MS12_CTL; /*!< 0x00000030 Master 12 protection context control */
+ __IOM uint32_t MS13_CTL; /*!< 0x00000034 Master 13 protection context control */
+ __IOM uint32_t MS14_CTL; /*!< 0x00000038 Master 14 protection context control */
+ __IOM uint32_t MS15_CTL; /*!< 0x0000003C Master 15 protection context control */
+ __IM uint32_t RESERVED[2032];
+ PROT_SMPU_SMPU_STRUCT_V2_Type SMPU_STRUCT[32]; /*!< 0x00002000 SMPU structure */
+ __IM uint32_t RESERVED1[1536];
+} PROT_SMPU_V2_Type; /*!< Size = 16384 (0x4000) */
+
+/**
+ * \brief MPU structure (PROT_MPU_MPU_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t ADDR; /*!< 0x00000000 MPU region address */
+ __IOM uint32_t ATT; /*!< 0x00000004 MPU region attrributes */
+ __IM uint32_t RESERVED[6];
+} PROT_MPU_MPU_STRUCT_V2_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief MPU (PROT_MPU)
+ */
+typedef struct {
+ __IOM uint32_t MS_CTL; /*!< 0x00000000 Master control */
+ __IM uint32_t MS_CTL_READ_MIR[127]; /*!< 0x00000004 Master control read mirror */
+ PROT_MPU_MPU_STRUCT_V2_Type MPU_STRUCT[16]; /*!< 0x00000200 MPU structure */
+} PROT_MPU_V2_Type; /*!< Size = 1024 (0x400) */
+
+/**
+ * \brief Protection (PROT)
+ */
+typedef struct {
+ PROT_SMPU_V2_Type SMPU; /*!< 0x00000000 SMPU */
+ PROT_MPU_V2_Type CYMPU[16]; /*!< 0x00004000 MPU */
+} PROT_V2_Type; /*!< Size = 32768 (0x8000) */
+
+
+/* PROT_SMPU_SMPU_STRUCT.ADDR0 */
+#define PROT_SMPU_SMPU_STRUCT_V2_ADDR0_SUBREGION_DISABLE_Pos 0UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
+#define PROT_SMPU_SMPU_STRUCT_V2_ADDR0_ADDR24_Pos 8UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ADDR0_ADDR24_Msk 0xFFFFFF00UL
+/* PROT_SMPU_SMPU_STRUCT.ATT0 */
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UR_Pos 0UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UR_Msk 0x1UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UW_Pos 1UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UW_Msk 0x2UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UX_Pos 2UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UX_Msk 0x4UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PR_Pos 3UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PR_Msk 0x8UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PW_Pos 4UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PW_Msk 0x10UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PX_Pos 5UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PX_Msk 0x20UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_NS_Pos 6UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_NS_Msk 0x40UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_0_Pos 8UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_0_Msk 0x100UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_15_TO_1_Pos 9UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_REGION_SIZE_Pos 24UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_REGION_SIZE_Msk 0x1F000000UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MATCH_Pos 30UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MATCH_Msk 0x40000000UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_ENABLED_Pos 31UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_ENABLED_Msk 0x80000000UL
+/* PROT_SMPU_SMPU_STRUCT.ADDR1 */
+#define PROT_SMPU_SMPU_STRUCT_V2_ADDR1_SUBREGION_DISABLE_Pos 0UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
+#define PROT_SMPU_SMPU_STRUCT_V2_ADDR1_ADDR24_Pos 8UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ADDR1_ADDR24_Msk 0xFFFFFF00UL
+/* PROT_SMPU_SMPU_STRUCT.ATT1 */
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UR_Pos 0UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UR_Msk 0x1UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UW_Pos 1UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UW_Msk 0x2UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UX_Pos 2UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UX_Msk 0x4UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PR_Pos 3UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PR_Msk 0x8UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PW_Pos 4UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PW_Msk 0x10UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PX_Pos 5UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PX_Msk 0x20UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_NS_Pos 6UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_NS_Msk 0x40UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_0_Pos 8UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_0_Msk 0x100UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_15_TO_1_Pos 9UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_REGION_SIZE_Pos 24UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_REGION_SIZE_Msk 0x1F000000UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MATCH_Pos 30UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MATCH_Msk 0x40000000UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_ENABLED_Pos 31UL
+#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_ENABLED_Msk 0x80000000UL
+
+
+/* PROT_SMPU.MS0_CTL */
+#define PROT_SMPU_V2_MS0_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS0_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS0_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS0_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS0_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS0_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS0_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS0_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS0_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS0_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS1_CTL */
+#define PROT_SMPU_V2_MS1_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS1_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS1_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS1_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS1_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS1_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS1_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS1_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS1_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS1_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS2_CTL */
+#define PROT_SMPU_V2_MS2_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS2_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS2_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS2_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS2_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS2_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS2_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS2_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS2_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS2_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS3_CTL */
+#define PROT_SMPU_V2_MS3_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS3_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS3_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS3_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS3_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS3_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS3_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS3_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS3_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS3_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS4_CTL */
+#define PROT_SMPU_V2_MS4_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS4_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS4_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS4_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS4_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS4_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS4_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS4_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS4_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS4_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS5_CTL */
+#define PROT_SMPU_V2_MS5_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS5_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS5_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS5_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS5_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS5_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS5_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS5_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS5_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS5_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS6_CTL */
+#define PROT_SMPU_V2_MS6_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS6_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS6_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS6_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS6_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS6_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS6_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS6_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS6_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS6_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS7_CTL */
+#define PROT_SMPU_V2_MS7_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS7_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS7_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS7_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS7_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS7_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS7_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS7_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS7_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS7_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS8_CTL */
+#define PROT_SMPU_V2_MS8_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS8_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS8_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS8_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS8_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS8_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS8_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS8_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS8_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS8_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS9_CTL */
+#define PROT_SMPU_V2_MS9_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS9_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS9_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS9_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS9_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS9_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS9_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS9_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS9_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS9_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS10_CTL */
+#define PROT_SMPU_V2_MS10_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS10_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS10_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS10_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS10_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS10_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS10_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS10_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS10_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS10_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS11_CTL */
+#define PROT_SMPU_V2_MS11_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS11_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS11_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS11_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS11_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS11_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS11_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS11_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS11_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS11_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS12_CTL */
+#define PROT_SMPU_V2_MS12_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS12_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS12_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS12_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS12_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS12_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS12_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS12_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS12_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS12_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS13_CTL */
+#define PROT_SMPU_V2_MS13_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS13_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS13_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS13_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS13_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS13_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS13_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS13_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS13_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS13_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS14_CTL */
+#define PROT_SMPU_V2_MS14_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS14_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS14_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS14_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS14_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS14_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS14_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS14_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS14_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS14_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS15_CTL */
+#define PROT_SMPU_V2_MS15_CTL_P_Pos 0UL
+#define PROT_SMPU_V2_MS15_CTL_P_Msk 0x1UL
+#define PROT_SMPU_V2_MS15_CTL_NS_Pos 1UL
+#define PROT_SMPU_V2_MS15_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_V2_MS15_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_V2_MS15_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_V2_MS15_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_V2_MS15_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_V2_MS15_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_V2_MS15_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+
+
+/* PROT_MPU_MPU_STRUCT.ADDR */
+#define PROT_MPU_MPU_STRUCT_V2_ADDR_SUBREGION_DISABLE_Pos 0UL
+#define PROT_MPU_MPU_STRUCT_V2_ADDR_SUBREGION_DISABLE_Msk 0xFFUL
+#define PROT_MPU_MPU_STRUCT_V2_ADDR_ADDR24_Pos 8UL
+#define PROT_MPU_MPU_STRUCT_V2_ADDR_ADDR24_Msk 0xFFFFFF00UL
+/* PROT_MPU_MPU_STRUCT.ATT */
+#define PROT_MPU_MPU_STRUCT_V2_ATT_UR_Pos 0UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_UR_Msk 0x1UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_UW_Pos 1UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_UW_Msk 0x2UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_UX_Pos 2UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_UX_Msk 0x4UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_PR_Pos 3UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_PR_Msk 0x8UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_PW_Pos 4UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_PW_Msk 0x10UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_PX_Pos 5UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_PX_Msk 0x20UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_NS_Pos 6UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_NS_Msk 0x40UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_REGION_SIZE_Pos 24UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_REGION_SIZE_Msk 0x1F000000UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_ENABLED_Pos 31UL
+#define PROT_MPU_MPU_STRUCT_V2_ATT_ENABLED_Msk 0x80000000UL
+
+
+/* PROT_MPU.MS_CTL */
+#define PROT_MPU_V2_MS_CTL_PC_Pos 0UL
+#define PROT_MPU_V2_MS_CTL_PC_Msk 0xFUL
+#define PROT_MPU_V2_MS_CTL_PC_SAVED_Pos 16UL
+#define PROT_MPU_V2_MS_CTL_PC_SAVED_Msk 0xF0000UL
+/* PROT_MPU.MS_CTL_READ_MIR */
+#define PROT_MPU_V2_MS_CTL_READ_MIR_PC_Pos 0UL
+#define PROT_MPU_V2_MS_CTL_READ_MIR_PC_Msk 0xFUL
+#define PROT_MPU_V2_MS_CTL_READ_MIR_PC_SAVED_Pos 16UL
+#define PROT_MPU_V2_MS_CTL_READ_MIR_PC_SAVED_Msk 0xF0000UL
+
+
+#endif /* _CYIP_PROT_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_sar.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_sar.h
new file mode 100644
index 0000000000..12294a6942
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_sar.h
@@ -0,0 +1,636 @@
+/***************************************************************************//**
+* \file cyip_sar.h
+*
+* \brief
+* SAR IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_SAR_H_
+#define _CYIP_SAR_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SAR
+*******************************************************************************/
+
+#define SAR_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief SAR ADC with Sequencer (SAR)
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< 0x00000000 Analog control register. */
+ __IOM uint32_t SAMPLE_CTRL; /*!< 0x00000004 Sample control register. */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t SAMPLE_TIME01; /*!< 0x00000010 Sample time specification ST0 and ST1 */
+ __IOM uint32_t SAMPLE_TIME23; /*!< 0x00000014 Sample time specification ST2 and ST3 */
+ __IOM uint32_t RANGE_THRES; /*!< 0x00000018 Global range detect threshold register. */
+ __IOM uint32_t RANGE_COND; /*!< 0x0000001C Global range detect mode register. */
+ __IOM uint32_t CHAN_EN; /*!< 0x00000020 Enable bits for the channels */
+ __IOM uint32_t START_CTRL; /*!< 0x00000024 Start control register (firmware trigger). */
+ __IM uint32_t RESERVED1[22];
+ __IOM uint32_t CHAN_CONFIG[16]; /*!< 0x00000080 Channel configuration register. */
+ __IM uint32_t RESERVED2[16];
+ __IM uint32_t CHAN_WORK[16]; /*!< 0x00000100 Channel working data register */
+ __IM uint32_t RESERVED3[16];
+ __IM uint32_t CHAN_RESULT[16]; /*!< 0x00000180 Channel result data register */
+ __IM uint32_t RESERVED4[16];
+ __IM uint32_t CHAN_WORK_UPDATED; /*!< 0x00000200 Channel working data register 'updated' bits */
+ __IM uint32_t CHAN_RESULT_UPDATED; /*!< 0x00000204 Channel result data register 'updated' bits */
+ __IM uint32_t CHAN_WORK_NEWVALUE; /*!< 0x00000208 Channel working data register 'new value' bits */
+ __IM uint32_t CHAN_RESULT_NEWVALUE; /*!< 0x0000020C Channel result data register 'new value' bits */
+ __IOM uint32_t INTR; /*!< 0x00000210 Interrupt request register. */
+ __IOM uint32_t INTR_SET; /*!< 0x00000214 Interrupt set request register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000218 Interrupt mask register. */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000021C Interrupt masked request register */
+ __IOM uint32_t SATURATE_INTR; /*!< 0x00000220 Saturate interrupt request register. */
+ __IOM uint32_t SATURATE_INTR_SET; /*!< 0x00000224 Saturate interrupt set request register */
+ __IOM uint32_t SATURATE_INTR_MASK; /*!< 0x00000228 Saturate interrupt mask register. */
+ __IM uint32_t SATURATE_INTR_MASKED; /*!< 0x0000022C Saturate interrupt masked request register */
+ __IOM uint32_t RANGE_INTR; /*!< 0x00000230 Range detect interrupt request register. */
+ __IOM uint32_t RANGE_INTR_SET; /*!< 0x00000234 Range detect interrupt set request register */
+ __IOM uint32_t RANGE_INTR_MASK; /*!< 0x00000238 Range detect interrupt mask register. */
+ __IM uint32_t RANGE_INTR_MASKED; /*!< 0x0000023C Range interrupt masked request register */
+ __IM uint32_t INTR_CAUSE; /*!< 0x00000240 Interrupt cause register */
+ __IM uint32_t RESERVED5[15];
+ __IOM uint32_t INJ_CHAN_CONFIG; /*!< 0x00000280 Injection channel configuration register. */
+ __IM uint32_t RESERVED6[3];
+ __IM uint32_t INJ_RESULT; /*!< 0x00000290 Injection channel result register */
+ __IM uint32_t RESERVED7[3];
+ __IM uint32_t STATUS; /*!< 0x000002A0 Current status of internal SAR registers (mostly for debug) */
+ __IM uint32_t AVG_STAT; /*!< 0x000002A4 Current averaging status (for debug) */
+ __IM uint32_t RESERVED8[22];
+ __IOM uint32_t MUX_SWITCH0; /*!< 0x00000300 SARMUX Firmware switch controls */
+ __IOM uint32_t MUX_SWITCH_CLEAR0; /*!< 0x00000304 SARMUX Firmware switch control clear */
+ __IM uint32_t RESERVED9[14];
+ __IOM uint32_t MUX_SWITCH_DS_CTRL; /*!< 0x00000340 SARMUX switch DSI control */
+ __IOM uint32_t MUX_SWITCH_SQ_CTRL; /*!< 0x00000344 SARMUX switch Sar Sequencer control */
+ __IM uint32_t MUX_SWITCH_STATUS; /*!< 0x00000348 SARMUX switch status */
+ __IM uint32_t RESERVED10[749];
+ __IOM uint32_t ANA_TRIM0; /*!< 0x00000F00 Analog trim register. */
+ __IOM uint32_t ANA_TRIM1; /*!< 0x00000F04 Analog trim register. */
+} SAR_V1_Type; /*!< Size = 3848 (0xF08) */
+
+
+/* SAR.CTRL */
+#define SAR_CTRL_PWR_CTRL_VREF_Pos 0UL
+#define SAR_CTRL_PWR_CTRL_VREF_Msk 0x7UL
+#define SAR_CTRL_VREF_SEL_Pos 4UL
+#define SAR_CTRL_VREF_SEL_Msk 0x70UL
+#define SAR_CTRL_VREF_BYP_CAP_EN_Pos 7UL
+#define SAR_CTRL_VREF_BYP_CAP_EN_Msk 0x80UL
+#define SAR_CTRL_NEG_SEL_Pos 9UL
+#define SAR_CTRL_NEG_SEL_Msk 0xE00UL
+#define SAR_CTRL_SAR_HW_CTRL_NEGVREF_Pos 13UL
+#define SAR_CTRL_SAR_HW_CTRL_NEGVREF_Msk 0x2000UL
+#define SAR_CTRL_COMP_DLY_Pos 14UL
+#define SAR_CTRL_COMP_DLY_Msk 0xC000UL
+#define SAR_CTRL_SPARE_Pos 16UL
+#define SAR_CTRL_SPARE_Msk 0xF0000UL
+#define SAR_CTRL_BOOSTPUMP_EN_Pos 20UL
+#define SAR_CTRL_BOOSTPUMP_EN_Msk 0x100000UL
+#define SAR_CTRL_REFBUF_EN_Pos 21UL
+#define SAR_CTRL_REFBUF_EN_Msk 0x200000UL
+#define SAR_CTRL_COMP_PWR_Pos 24UL
+#define SAR_CTRL_COMP_PWR_Msk 0x7000000UL
+#define SAR_CTRL_DEEPSLEEP_ON_Pos 27UL
+#define SAR_CTRL_DEEPSLEEP_ON_Msk 0x8000000UL
+#define SAR_CTRL_DSI_SYNC_CONFIG_Pos 28UL
+#define SAR_CTRL_DSI_SYNC_CONFIG_Msk 0x10000000UL
+#define SAR_CTRL_DSI_MODE_Pos 29UL
+#define SAR_CTRL_DSI_MODE_Msk 0x20000000UL
+#define SAR_CTRL_SWITCH_DISABLE_Pos 30UL
+#define SAR_CTRL_SWITCH_DISABLE_Msk 0x40000000UL
+#define SAR_CTRL_ENABLED_Pos 31UL
+#define SAR_CTRL_ENABLED_Msk 0x80000000UL
+/* SAR.SAMPLE_CTRL */
+#define SAR_SAMPLE_CTRL_LEFT_ALIGN_Pos 1UL
+#define SAR_SAMPLE_CTRL_LEFT_ALIGN_Msk 0x2UL
+#define SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Pos 2UL
+#define SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk 0x4UL
+#define SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Pos 3UL
+#define SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Msk 0x8UL
+#define SAR_SAMPLE_CTRL_AVG_CNT_Pos 4UL
+#define SAR_SAMPLE_CTRL_AVG_CNT_Msk 0x70UL
+#define SAR_SAMPLE_CTRL_AVG_SHIFT_Pos 7UL
+#define SAR_SAMPLE_CTRL_AVG_SHIFT_Msk 0x80UL
+#define SAR_SAMPLE_CTRL_AVG_MODE_Pos 8UL
+#define SAR_SAMPLE_CTRL_AVG_MODE_Msk 0x100UL
+#define SAR_SAMPLE_CTRL_CONTINUOUS_Pos 16UL
+#define SAR_SAMPLE_CTRL_CONTINUOUS_Msk 0x10000UL
+#define SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Pos 17UL
+#define SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk 0x20000UL
+#define SAR_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Pos 18UL
+#define SAR_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Msk 0x40000UL
+#define SAR_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Pos 19UL
+#define SAR_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Msk 0x80000UL
+#define SAR_SAMPLE_CTRL_UAB_SCAN_MODE_Pos 22UL
+#define SAR_SAMPLE_CTRL_UAB_SCAN_MODE_Msk 0x400000UL
+#define SAR_SAMPLE_CTRL_REPEAT_INVALID_Pos 23UL
+#define SAR_SAMPLE_CTRL_REPEAT_INVALID_Msk 0x800000UL
+#define SAR_SAMPLE_CTRL_VALID_SEL_Pos 24UL
+#define SAR_SAMPLE_CTRL_VALID_SEL_Msk 0x7000000UL
+#define SAR_SAMPLE_CTRL_VALID_SEL_EN_Pos 27UL
+#define SAR_SAMPLE_CTRL_VALID_SEL_EN_Msk 0x8000000UL
+#define SAR_SAMPLE_CTRL_VALID_IGNORE_Pos 28UL
+#define SAR_SAMPLE_CTRL_VALID_IGNORE_Msk 0x10000000UL
+#define SAR_SAMPLE_CTRL_TRIGGER_OUT_EN_Pos 30UL
+#define SAR_SAMPLE_CTRL_TRIGGER_OUT_EN_Msk 0x40000000UL
+#define SAR_SAMPLE_CTRL_EOS_DSI_OUT_EN_Pos 31UL
+#define SAR_SAMPLE_CTRL_EOS_DSI_OUT_EN_Msk 0x80000000UL
+/* SAR.SAMPLE_TIME01 */
+#define SAR_SAMPLE_TIME01_SAMPLE_TIME0_Pos 0UL
+#define SAR_SAMPLE_TIME01_SAMPLE_TIME0_Msk 0x3FFUL
+#define SAR_SAMPLE_TIME01_SAMPLE_TIME1_Pos 16UL
+#define SAR_SAMPLE_TIME01_SAMPLE_TIME1_Msk 0x3FF0000UL
+/* SAR.SAMPLE_TIME23 */
+#define SAR_SAMPLE_TIME23_SAMPLE_TIME2_Pos 0UL
+#define SAR_SAMPLE_TIME23_SAMPLE_TIME2_Msk 0x3FFUL
+#define SAR_SAMPLE_TIME23_SAMPLE_TIME3_Pos 16UL
+#define SAR_SAMPLE_TIME23_SAMPLE_TIME3_Msk 0x3FF0000UL
+/* SAR.RANGE_THRES */
+#define SAR_RANGE_THRES_RANGE_LOW_Pos 0UL
+#define SAR_RANGE_THRES_RANGE_LOW_Msk 0xFFFFUL
+#define SAR_RANGE_THRES_RANGE_HIGH_Pos 16UL
+#define SAR_RANGE_THRES_RANGE_HIGH_Msk 0xFFFF0000UL
+/* SAR.RANGE_COND */
+#define SAR_RANGE_COND_RANGE_COND_Pos 30UL
+#define SAR_RANGE_COND_RANGE_COND_Msk 0xC0000000UL
+/* SAR.CHAN_EN */
+#define SAR_CHAN_EN_CHAN_EN_Pos 0UL
+#define SAR_CHAN_EN_CHAN_EN_Msk 0xFFFFUL
+/* SAR.START_CTRL */
+#define SAR_START_CTRL_FW_TRIGGER_Pos 0UL
+#define SAR_START_CTRL_FW_TRIGGER_Msk 0x1UL
+/* SAR.CHAN_CONFIG */
+#define SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos 0UL
+#define SAR_CHAN_CONFIG_POS_PIN_ADDR_Msk 0x7UL
+#define SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos 4UL
+#define SAR_CHAN_CONFIG_POS_PORT_ADDR_Msk 0x70UL
+#define SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Pos 8UL
+#define SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Msk 0x100UL
+#define SAR_CHAN_CONFIG_AVG_EN_Pos 10UL
+#define SAR_CHAN_CONFIG_AVG_EN_Msk 0x400UL
+#define SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos 12UL
+#define SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Msk 0x3000UL
+#define SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos 16UL
+#define SAR_CHAN_CONFIG_NEG_PIN_ADDR_Msk 0x70000UL
+#define SAR_CHAN_CONFIG_NEG_PORT_ADDR_Pos 20UL
+#define SAR_CHAN_CONFIG_NEG_PORT_ADDR_Msk 0x700000UL
+#define SAR_CHAN_CONFIG_NEG_ADDR_EN_Pos 24UL
+#define SAR_CHAN_CONFIG_NEG_ADDR_EN_Msk 0x1000000UL
+#define SAR_CHAN_CONFIG_DSI_OUT_EN_Pos 31UL
+#define SAR_CHAN_CONFIG_DSI_OUT_EN_Msk 0x80000000UL
+/* SAR.CHAN_WORK */
+#define SAR_CHAN_WORK_WORK_Pos 0UL
+#define SAR_CHAN_WORK_WORK_Msk 0xFFFFUL
+#define SAR_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Pos 27UL
+#define SAR_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Msk 0x8000000UL
+#define SAR_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Pos 31UL
+#define SAR_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Msk 0x80000000UL
+/* SAR.CHAN_RESULT */
+#define SAR_CHAN_RESULT_RESULT_Pos 0UL
+#define SAR_CHAN_RESULT_RESULT_Msk 0xFFFFUL
+#define SAR_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Pos 27UL
+#define SAR_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Msk 0x8000000UL
+#define SAR_CHAN_RESULT_SATURATE_INTR_MIR_Pos 29UL
+#define SAR_CHAN_RESULT_SATURATE_INTR_MIR_Msk 0x20000000UL
+#define SAR_CHAN_RESULT_RANGE_INTR_MIR_Pos 30UL
+#define SAR_CHAN_RESULT_RANGE_INTR_MIR_Msk 0x40000000UL
+#define SAR_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Pos 31UL
+#define SAR_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Msk 0x80000000UL
+/* SAR.CHAN_WORK_UPDATED */
+#define SAR_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Pos 0UL
+#define SAR_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Msk 0xFFFFUL
+/* SAR.CHAN_RESULT_UPDATED */
+#define SAR_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Pos 0UL
+#define SAR_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Msk 0xFFFFUL
+/* SAR.CHAN_WORK_NEWVALUE */
+#define SAR_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Pos 0UL
+#define SAR_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Msk 0xFFFFUL
+/* SAR.CHAN_RESULT_NEWVALUE */
+#define SAR_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Pos 0UL
+#define SAR_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Msk 0xFFFFUL
+/* SAR.INTR */
+#define SAR_INTR_EOS_INTR_Pos 0UL
+#define SAR_INTR_EOS_INTR_Msk 0x1UL
+#define SAR_INTR_OVERFLOW_INTR_Pos 1UL
+#define SAR_INTR_OVERFLOW_INTR_Msk 0x2UL
+#define SAR_INTR_FW_COLLISION_INTR_Pos 2UL
+#define SAR_INTR_FW_COLLISION_INTR_Msk 0x4UL
+#define SAR_INTR_DSI_COLLISION_INTR_Pos 3UL
+#define SAR_INTR_DSI_COLLISION_INTR_Msk 0x8UL
+#define SAR_INTR_INJ_EOC_INTR_Pos 4UL
+#define SAR_INTR_INJ_EOC_INTR_Msk 0x10UL
+#define SAR_INTR_INJ_SATURATE_INTR_Pos 5UL
+#define SAR_INTR_INJ_SATURATE_INTR_Msk 0x20UL
+#define SAR_INTR_INJ_RANGE_INTR_Pos 6UL
+#define SAR_INTR_INJ_RANGE_INTR_Msk 0x40UL
+#define SAR_INTR_INJ_COLLISION_INTR_Pos 7UL
+#define SAR_INTR_INJ_COLLISION_INTR_Msk 0x80UL
+/* SAR.INTR_SET */
+#define SAR_INTR_SET_EOS_SET_Pos 0UL
+#define SAR_INTR_SET_EOS_SET_Msk 0x1UL
+#define SAR_INTR_SET_OVERFLOW_SET_Pos 1UL
+#define SAR_INTR_SET_OVERFLOW_SET_Msk 0x2UL
+#define SAR_INTR_SET_FW_COLLISION_SET_Pos 2UL
+#define SAR_INTR_SET_FW_COLLISION_SET_Msk 0x4UL
+#define SAR_INTR_SET_DSI_COLLISION_SET_Pos 3UL
+#define SAR_INTR_SET_DSI_COLLISION_SET_Msk 0x8UL
+#define SAR_INTR_SET_INJ_EOC_SET_Pos 4UL
+#define SAR_INTR_SET_INJ_EOC_SET_Msk 0x10UL
+#define SAR_INTR_SET_INJ_SATURATE_SET_Pos 5UL
+#define SAR_INTR_SET_INJ_SATURATE_SET_Msk 0x20UL
+#define SAR_INTR_SET_INJ_RANGE_SET_Pos 6UL
+#define SAR_INTR_SET_INJ_RANGE_SET_Msk 0x40UL
+#define SAR_INTR_SET_INJ_COLLISION_SET_Pos 7UL
+#define SAR_INTR_SET_INJ_COLLISION_SET_Msk 0x80UL
+/* SAR.INTR_MASK */
+#define SAR_INTR_MASK_EOS_MASK_Pos 0UL
+#define SAR_INTR_MASK_EOS_MASK_Msk 0x1UL
+#define SAR_INTR_MASK_OVERFLOW_MASK_Pos 1UL
+#define SAR_INTR_MASK_OVERFLOW_MASK_Msk 0x2UL
+#define SAR_INTR_MASK_FW_COLLISION_MASK_Pos 2UL
+#define SAR_INTR_MASK_FW_COLLISION_MASK_Msk 0x4UL
+#define SAR_INTR_MASK_DSI_COLLISION_MASK_Pos 3UL
+#define SAR_INTR_MASK_DSI_COLLISION_MASK_Msk 0x8UL
+#define SAR_INTR_MASK_INJ_EOC_MASK_Pos 4UL
+#define SAR_INTR_MASK_INJ_EOC_MASK_Msk 0x10UL
+#define SAR_INTR_MASK_INJ_SATURATE_MASK_Pos 5UL
+#define SAR_INTR_MASK_INJ_SATURATE_MASK_Msk 0x20UL
+#define SAR_INTR_MASK_INJ_RANGE_MASK_Pos 6UL
+#define SAR_INTR_MASK_INJ_RANGE_MASK_Msk 0x40UL
+#define SAR_INTR_MASK_INJ_COLLISION_MASK_Pos 7UL
+#define SAR_INTR_MASK_INJ_COLLISION_MASK_Msk 0x80UL
+/* SAR.INTR_MASKED */
+#define SAR_INTR_MASKED_EOS_MASKED_Pos 0UL
+#define SAR_INTR_MASKED_EOS_MASKED_Msk 0x1UL
+#define SAR_INTR_MASKED_OVERFLOW_MASKED_Pos 1UL
+#define SAR_INTR_MASKED_OVERFLOW_MASKED_Msk 0x2UL
+#define SAR_INTR_MASKED_FW_COLLISION_MASKED_Pos 2UL
+#define SAR_INTR_MASKED_FW_COLLISION_MASKED_Msk 0x4UL
+#define SAR_INTR_MASKED_DSI_COLLISION_MASKED_Pos 3UL
+#define SAR_INTR_MASKED_DSI_COLLISION_MASKED_Msk 0x8UL
+#define SAR_INTR_MASKED_INJ_EOC_MASKED_Pos 4UL
+#define SAR_INTR_MASKED_INJ_EOC_MASKED_Msk 0x10UL
+#define SAR_INTR_MASKED_INJ_SATURATE_MASKED_Pos 5UL
+#define SAR_INTR_MASKED_INJ_SATURATE_MASKED_Msk 0x20UL
+#define SAR_INTR_MASKED_INJ_RANGE_MASKED_Pos 6UL
+#define SAR_INTR_MASKED_INJ_RANGE_MASKED_Msk 0x40UL
+#define SAR_INTR_MASKED_INJ_COLLISION_MASKED_Pos 7UL
+#define SAR_INTR_MASKED_INJ_COLLISION_MASKED_Msk 0x80UL
+/* SAR.SATURATE_INTR */
+#define SAR_SATURATE_INTR_SATURATE_INTR_Pos 0UL
+#define SAR_SATURATE_INTR_SATURATE_INTR_Msk 0xFFFFUL
+/* SAR.SATURATE_INTR_SET */
+#define SAR_SATURATE_INTR_SET_SATURATE_SET_Pos 0UL
+#define SAR_SATURATE_INTR_SET_SATURATE_SET_Msk 0xFFFFUL
+/* SAR.SATURATE_INTR_MASK */
+#define SAR_SATURATE_INTR_MASK_SATURATE_MASK_Pos 0UL
+#define SAR_SATURATE_INTR_MASK_SATURATE_MASK_Msk 0xFFFFUL
+/* SAR.SATURATE_INTR_MASKED */
+#define SAR_SATURATE_INTR_MASKED_SATURATE_MASKED_Pos 0UL
+#define SAR_SATURATE_INTR_MASKED_SATURATE_MASKED_Msk 0xFFFFUL
+/* SAR.RANGE_INTR */
+#define SAR_RANGE_INTR_RANGE_INTR_Pos 0UL
+#define SAR_RANGE_INTR_RANGE_INTR_Msk 0xFFFFUL
+/* SAR.RANGE_INTR_SET */
+#define SAR_RANGE_INTR_SET_RANGE_SET_Pos 0UL
+#define SAR_RANGE_INTR_SET_RANGE_SET_Msk 0xFFFFUL
+/* SAR.RANGE_INTR_MASK */
+#define SAR_RANGE_INTR_MASK_RANGE_MASK_Pos 0UL
+#define SAR_RANGE_INTR_MASK_RANGE_MASK_Msk 0xFFFFUL
+/* SAR.RANGE_INTR_MASKED */
+#define SAR_RANGE_INTR_MASKED_RANGE_MASKED_Pos 0UL
+#define SAR_RANGE_INTR_MASKED_RANGE_MASKED_Msk 0xFFFFUL
+/* SAR.INTR_CAUSE */
+#define SAR_INTR_CAUSE_EOS_MASKED_MIR_Pos 0UL
+#define SAR_INTR_CAUSE_EOS_MASKED_MIR_Msk 0x1UL
+#define SAR_INTR_CAUSE_OVERFLOW_MASKED_MIR_Pos 1UL
+#define SAR_INTR_CAUSE_OVERFLOW_MASKED_MIR_Msk 0x2UL
+#define SAR_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Pos 2UL
+#define SAR_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Msk 0x4UL
+#define SAR_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Pos 3UL
+#define SAR_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Msk 0x8UL
+#define SAR_INTR_CAUSE_INJ_EOC_MASKED_MIR_Pos 4UL
+#define SAR_INTR_CAUSE_INJ_EOC_MASKED_MIR_Msk 0x10UL
+#define SAR_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Pos 5UL
+#define SAR_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Msk 0x20UL
+#define SAR_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Pos 6UL
+#define SAR_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Msk 0x40UL
+#define SAR_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Pos 7UL
+#define SAR_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Msk 0x80UL
+#define SAR_INTR_CAUSE_SATURATE_MASKED_RED_Pos 30UL
+#define SAR_INTR_CAUSE_SATURATE_MASKED_RED_Msk 0x40000000UL
+#define SAR_INTR_CAUSE_RANGE_MASKED_RED_Pos 31UL
+#define SAR_INTR_CAUSE_RANGE_MASKED_RED_Msk 0x80000000UL
+/* SAR.INJ_CHAN_CONFIG */
+#define SAR_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Pos 0UL
+#define SAR_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Msk 0x7UL
+#define SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Pos 4UL
+#define SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Msk 0x70UL
+#define SAR_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Pos 8UL
+#define SAR_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Msk 0x100UL
+#define SAR_INJ_CHAN_CONFIG_INJ_AVG_EN_Pos 10UL
+#define SAR_INJ_CHAN_CONFIG_INJ_AVG_EN_Msk 0x400UL
+#define SAR_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Pos 12UL
+#define SAR_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Msk 0x3000UL
+#define SAR_INJ_CHAN_CONFIG_INJ_TAILGATING_Pos 30UL
+#define SAR_INJ_CHAN_CONFIG_INJ_TAILGATING_Msk 0x40000000UL
+#define SAR_INJ_CHAN_CONFIG_INJ_START_EN_Pos 31UL
+#define SAR_INJ_CHAN_CONFIG_INJ_START_EN_Msk 0x80000000UL
+/* SAR.INJ_RESULT */
+#define SAR_INJ_RESULT_INJ_RESULT_Pos 0UL
+#define SAR_INJ_RESULT_INJ_RESULT_Msk 0xFFFFUL
+#define SAR_INJ_RESULT_INJ_NEWVALUE_Pos 27UL
+#define SAR_INJ_RESULT_INJ_NEWVALUE_Msk 0x8000000UL
+#define SAR_INJ_RESULT_INJ_COLLISION_INTR_MIR_Pos 28UL
+#define SAR_INJ_RESULT_INJ_COLLISION_INTR_MIR_Msk 0x10000000UL
+#define SAR_INJ_RESULT_INJ_SATURATE_INTR_MIR_Pos 29UL
+#define SAR_INJ_RESULT_INJ_SATURATE_INTR_MIR_Msk 0x20000000UL
+#define SAR_INJ_RESULT_INJ_RANGE_INTR_MIR_Pos 30UL
+#define SAR_INJ_RESULT_INJ_RANGE_INTR_MIR_Msk 0x40000000UL
+#define SAR_INJ_RESULT_INJ_EOC_INTR_MIR_Pos 31UL
+#define SAR_INJ_RESULT_INJ_EOC_INTR_MIR_Msk 0x80000000UL
+/* SAR.STATUS */
+#define SAR_STATUS_CUR_CHAN_Pos 0UL
+#define SAR_STATUS_CUR_CHAN_Msk 0x1FUL
+#define SAR_STATUS_SW_VREF_NEG_Pos 30UL
+#define SAR_STATUS_SW_VREF_NEG_Msk 0x40000000UL
+#define SAR_STATUS_BUSY_Pos 31UL
+#define SAR_STATUS_BUSY_Msk 0x80000000UL
+/* SAR.AVG_STAT */
+#define SAR_AVG_STAT_CUR_AVG_ACCU_Pos 0UL
+#define SAR_AVG_STAT_CUR_AVG_ACCU_Msk 0xFFFFFUL
+#define SAR_AVG_STAT_INTRLV_BUSY_Pos 23UL
+#define SAR_AVG_STAT_INTRLV_BUSY_Msk 0x800000UL
+#define SAR_AVG_STAT_CUR_AVG_CNT_Pos 24UL
+#define SAR_AVG_STAT_CUR_AVG_CNT_Msk 0xFF000000UL
+/* SAR.MUX_SWITCH0 */
+#define SAR_MUX_SWITCH0_MUX_FW_P0_VPLUS_Pos 0UL
+#define SAR_MUX_SWITCH0_MUX_FW_P0_VPLUS_Msk 0x1UL
+#define SAR_MUX_SWITCH0_MUX_FW_P1_VPLUS_Pos 1UL
+#define SAR_MUX_SWITCH0_MUX_FW_P1_VPLUS_Msk 0x2UL
+#define SAR_MUX_SWITCH0_MUX_FW_P2_VPLUS_Pos 2UL
+#define SAR_MUX_SWITCH0_MUX_FW_P2_VPLUS_Msk 0x4UL
+#define SAR_MUX_SWITCH0_MUX_FW_P3_VPLUS_Pos 3UL
+#define SAR_MUX_SWITCH0_MUX_FW_P3_VPLUS_Msk 0x8UL
+#define SAR_MUX_SWITCH0_MUX_FW_P4_VPLUS_Pos 4UL
+#define SAR_MUX_SWITCH0_MUX_FW_P4_VPLUS_Msk 0x10UL
+#define SAR_MUX_SWITCH0_MUX_FW_P5_VPLUS_Pos 5UL
+#define SAR_MUX_SWITCH0_MUX_FW_P5_VPLUS_Msk 0x20UL
+#define SAR_MUX_SWITCH0_MUX_FW_P6_VPLUS_Pos 6UL
+#define SAR_MUX_SWITCH0_MUX_FW_P6_VPLUS_Msk 0x40UL
+#define SAR_MUX_SWITCH0_MUX_FW_P7_VPLUS_Pos 7UL
+#define SAR_MUX_SWITCH0_MUX_FW_P7_VPLUS_Msk 0x80UL
+#define SAR_MUX_SWITCH0_MUX_FW_P0_VMINUS_Pos 8UL
+#define SAR_MUX_SWITCH0_MUX_FW_P0_VMINUS_Msk 0x100UL
+#define SAR_MUX_SWITCH0_MUX_FW_P1_VMINUS_Pos 9UL
+#define SAR_MUX_SWITCH0_MUX_FW_P1_VMINUS_Msk 0x200UL
+#define SAR_MUX_SWITCH0_MUX_FW_P2_VMINUS_Pos 10UL
+#define SAR_MUX_SWITCH0_MUX_FW_P2_VMINUS_Msk 0x400UL
+#define SAR_MUX_SWITCH0_MUX_FW_P3_VMINUS_Pos 11UL
+#define SAR_MUX_SWITCH0_MUX_FW_P3_VMINUS_Msk 0x800UL
+#define SAR_MUX_SWITCH0_MUX_FW_P4_VMINUS_Pos 12UL
+#define SAR_MUX_SWITCH0_MUX_FW_P4_VMINUS_Msk 0x1000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P5_VMINUS_Pos 13UL
+#define SAR_MUX_SWITCH0_MUX_FW_P5_VMINUS_Msk 0x2000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P6_VMINUS_Pos 14UL
+#define SAR_MUX_SWITCH0_MUX_FW_P6_VMINUS_Msk 0x4000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P7_VMINUS_Pos 15UL
+#define SAR_MUX_SWITCH0_MUX_FW_P7_VMINUS_Msk 0x8000UL
+#define SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Pos 16UL
+#define SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL
+#define SAR_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Pos 17UL
+#define SAR_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Pos 22UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Pos 23UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Pos 24UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Pos 25UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P4_COREIO0_Pos 26UL
+#define SAR_MUX_SWITCH0_MUX_FW_P4_COREIO0_Msk 0x4000000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P5_COREIO1_Pos 27UL
+#define SAR_MUX_SWITCH0_MUX_FW_P5_COREIO1_Msk 0x8000000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P6_COREIO2_Pos 28UL
+#define SAR_MUX_SWITCH0_MUX_FW_P6_COREIO2_Msk 0x10000000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P7_COREIO3_Pos 29UL
+#define SAR_MUX_SWITCH0_MUX_FW_P7_COREIO3_Msk 0x20000000UL
+/* SAR.MUX_SWITCH_CLEAR0 */
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Pos 0UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Msk 0x1UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Pos 1UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Msk 0x2UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Pos 2UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Msk 0x4UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Pos 3UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Msk 0x8UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Pos 4UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Msk 0x10UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Pos 5UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Msk 0x20UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Pos 6UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Msk 0x40UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Pos 7UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Msk 0x80UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Pos 8UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Msk 0x100UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Pos 9UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Msk 0x200UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Pos 10UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Msk 0x400UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Pos 11UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Msk 0x800UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Pos 12UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Msk 0x1000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Pos 13UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Msk 0x2000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Pos 14UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Msk 0x4000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Pos 15UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Msk 0x8000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Pos 16UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Pos 17UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Pos 22UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Pos 23UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Pos 24UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Pos 25UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Pos 26UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Msk 0x4000000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Pos 27UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Msk 0x8000000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Pos 28UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Msk 0x10000000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Pos 29UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Msk 0x20000000UL
+/* SAR.MUX_SWITCH_DS_CTRL */
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P0_Pos 0UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P0_Msk 0x1UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P1_Pos 1UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P1_Msk 0x2UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P2_Pos 2UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P2_Msk 0x4UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P3_Pos 3UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P3_Msk 0x8UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P4_Pos 4UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P4_Msk 0x10UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P5_Pos 5UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P5_Msk 0x20UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P6_Pos 6UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P6_Msk 0x40UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P7_Pos 7UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P7_Msk 0x80UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_VSSA_Pos 16UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_VSSA_Msk 0x10000UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_TEMP_Pos 17UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_TEMP_Msk 0x20000UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSA_Pos 18UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSA_Msk 0x40000UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSB_Pos 19UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSB_Msk 0x80000UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS0_Pos 22UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS0_Msk 0x400000UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS1_Pos 23UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS1_Msk 0x800000UL
+/* SAR.MUX_SWITCH_SQ_CTRL */
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Pos 0UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Msk 0x1UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Pos 1UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Msk 0x2UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Pos 2UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Msk 0x4UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Pos 3UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Msk 0x8UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Pos 4UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Msk 0x10UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Pos 5UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Msk 0x20UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Pos 6UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Msk 0x40UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Pos 7UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Msk 0x80UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Pos 16UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk 0x10000UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Pos 17UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Msk 0x20000UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Pos 18UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Msk 0x40000UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Pos 19UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Msk 0x80000UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Pos 22UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Msk 0x400000UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Pos 23UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Msk 0x800000UL
+/* SAR.MUX_SWITCH_STATUS */
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Pos 0UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Msk 0x1UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Pos 1UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Msk 0x2UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Pos 2UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Msk 0x4UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Pos 3UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Msk 0x8UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Pos 4UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Msk 0x10UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Pos 5UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Msk 0x20UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Pos 6UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Msk 0x40UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Pos 7UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Msk 0x80UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Pos 8UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Msk 0x100UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Pos 9UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Msk 0x200UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Pos 10UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Msk 0x400UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Pos 11UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Msk 0x800UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Pos 12UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Msk 0x1000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Pos 13UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Msk 0x2000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Pos 14UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Msk 0x4000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Pos 15UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Msk 0x8000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Pos 16UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Msk 0x10000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Pos 17UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Msk 0x20000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Pos 22UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Pos 23UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Pos 24UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Pos 25UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL
+/* SAR.ANA_TRIM0 */
+#define SAR_ANA_TRIM0_CAP_TRIM_Pos 0UL
+#define SAR_ANA_TRIM0_CAP_TRIM_Msk 0x1FUL
+#define SAR_ANA_TRIM0_TRIMUNIT_Pos 5UL
+#define SAR_ANA_TRIM0_TRIMUNIT_Msk 0x20UL
+/* SAR.ANA_TRIM1 */
+#define SAR_ANA_TRIM1_SAR_REF_BUF_TRIM_Pos 0UL
+#define SAR_ANA_TRIM1_SAR_REF_BUF_TRIM_Msk 0x3FUL
+
+
+#endif /* _CYIP_SAR_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_scb.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_scb.h
new file mode 100644
index 0000000000..3dc6186dc0
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_scb.h
@@ -0,0 +1,755 @@
+/***************************************************************************//**
+* \file cyip_scb.h
+*
+* \brief
+* SCB IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_SCB_H_
+#define _CYIP_SCB_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SCB
+*******************************************************************************/
+
+#define SCB_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Serial Communications Block (SPI/UART/I2C) (CySCB)
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< 0x00000000 Generic control */
+ __IM uint32_t STATUS; /*!< 0x00000004 Generic status */
+ __IOM uint32_t CMD_RESP_CTRL; /*!< 0x00000008 Command/response control */
+ __IM uint32_t CMD_RESP_STATUS; /*!< 0x0000000C Command/response status */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t SPI_CTRL; /*!< 0x00000020 SPI control */
+ __IM uint32_t SPI_STATUS; /*!< 0x00000024 SPI status */
+ __IM uint32_t RESERVED1[6];
+ __IOM uint32_t UART_CTRL; /*!< 0x00000040 UART control */
+ __IOM uint32_t UART_TX_CTRL; /*!< 0x00000044 UART transmitter control */
+ __IOM uint32_t UART_RX_CTRL; /*!< 0x00000048 UART receiver control */
+ __IM uint32_t UART_RX_STATUS; /*!< 0x0000004C UART receiver status */
+ __IOM uint32_t UART_FLOW_CTRL; /*!< 0x00000050 UART flow control */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t I2C_CTRL; /*!< 0x00000060 I2C control */
+ __IM uint32_t I2C_STATUS; /*!< 0x00000064 I2C status */
+ __IOM uint32_t I2C_M_CMD; /*!< 0x00000068 I2C master command */
+ __IOM uint32_t I2C_S_CMD; /*!< 0x0000006C I2C slave command */
+ __IOM uint32_t I2C_CFG; /*!< 0x00000070 I2C configuration */
+ __IM uint32_t RESERVED3[99];
+ __IOM uint32_t TX_CTRL; /*!< 0x00000200 Transmitter control */
+ __IOM uint32_t TX_FIFO_CTRL; /*!< 0x00000204 Transmitter FIFO control */
+ __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000208 Transmitter FIFO status */
+ __IM uint32_t RESERVED4[13];
+ __OM uint32_t TX_FIFO_WR; /*!< 0x00000240 Transmitter FIFO write */
+ __IM uint32_t RESERVED5[47];
+ __IOM uint32_t RX_CTRL; /*!< 0x00000300 Receiver control */
+ __IOM uint32_t RX_FIFO_CTRL; /*!< 0x00000304 Receiver FIFO control */
+ __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000308 Receiver FIFO status */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t RX_MATCH; /*!< 0x00000310 Slave address and mask */
+ __IM uint32_t RESERVED7[11];
+ __IM uint32_t RX_FIFO_RD; /*!< 0x00000340 Receiver FIFO read */
+ __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x00000344 Receiver FIFO read silent */
+ __IM uint32_t RESERVED8[46];
+ __IOM uint32_t EZ_DATA[512]; /*!< 0x00000400 Memory buffer */
+ __IM uint32_t RESERVED9[128];
+ __IM uint32_t INTR_CAUSE; /*!< 0x00000E00 Active clocked interrupt signal */
+ __IM uint32_t RESERVED10[31];
+ __IOM uint32_t INTR_I2C_EC; /*!< 0x00000E80 Externally clocked I2C interrupt request */
+ __IM uint32_t RESERVED11;
+ __IOM uint32_t INTR_I2C_EC_MASK; /*!< 0x00000E88 Externally clocked I2C interrupt mask */
+ __IM uint32_t INTR_I2C_EC_MASKED; /*!< 0x00000E8C Externally clocked I2C interrupt masked */
+ __IM uint32_t RESERVED12[12];
+ __IOM uint32_t INTR_SPI_EC; /*!< 0x00000EC0 Externally clocked SPI interrupt request */
+ __IM uint32_t RESERVED13;
+ __IOM uint32_t INTR_SPI_EC_MASK; /*!< 0x00000EC8 Externally clocked SPI interrupt mask */
+ __IM uint32_t INTR_SPI_EC_MASKED; /*!< 0x00000ECC Externally clocked SPI interrupt masked */
+ __IM uint32_t RESERVED14[12];
+ __IOM uint32_t INTR_M; /*!< 0x00000F00 Master interrupt request */
+ __IOM uint32_t INTR_M_SET; /*!< 0x00000F04 Master interrupt set request */
+ __IOM uint32_t INTR_M_MASK; /*!< 0x00000F08 Master interrupt mask */
+ __IM uint32_t INTR_M_MASKED; /*!< 0x00000F0C Master interrupt masked request */
+ __IM uint32_t RESERVED15[12];
+ __IOM uint32_t INTR_S; /*!< 0x00000F40 Slave interrupt request */
+ __IOM uint32_t INTR_S_SET; /*!< 0x00000F44 Slave interrupt set request */
+ __IOM uint32_t INTR_S_MASK; /*!< 0x00000F48 Slave interrupt mask */
+ __IM uint32_t INTR_S_MASKED; /*!< 0x00000F4C Slave interrupt masked request */
+ __IM uint32_t RESERVED16[12];
+ __IOM uint32_t INTR_TX; /*!< 0x00000F80 Transmitter interrupt request */
+ __IOM uint32_t INTR_TX_SET; /*!< 0x00000F84 Transmitter interrupt set request */
+ __IOM uint32_t INTR_TX_MASK; /*!< 0x00000F88 Transmitter interrupt mask */
+ __IM uint32_t INTR_TX_MASKED; /*!< 0x00000F8C Transmitter interrupt masked request */
+ __IM uint32_t RESERVED17[12];
+ __IOM uint32_t INTR_RX; /*!< 0x00000FC0 Receiver interrupt request */
+ __IOM uint32_t INTR_RX_SET; /*!< 0x00000FC4 Receiver interrupt set request */
+ __IOM uint32_t INTR_RX_MASK; /*!< 0x00000FC8 Receiver interrupt mask */
+ __IM uint32_t INTR_RX_MASKED; /*!< 0x00000FCC Receiver interrupt masked request */
+} CySCB_V1_Type; /*!< Size = 4048 (0xFD0) */
+
+
+/* SCB.CTRL */
+#define SCB_CTRL_OVS_Pos 0UL
+#define SCB_CTRL_OVS_Msk 0xFUL
+#define SCB_CTRL_EC_AM_MODE_Pos 8UL
+#define SCB_CTRL_EC_AM_MODE_Msk 0x100UL
+#define SCB_CTRL_EC_OP_MODE_Pos 9UL
+#define SCB_CTRL_EC_OP_MODE_Msk 0x200UL
+#define SCB_CTRL_EZ_MODE_Pos 10UL
+#define SCB_CTRL_EZ_MODE_Msk 0x400UL
+#define SCB_CTRL_BYTE_MODE_Pos 11UL
+#define SCB_CTRL_BYTE_MODE_Msk 0x800UL
+#define SCB_CTRL_CMD_RESP_MODE_Pos 12UL
+#define SCB_CTRL_CMD_RESP_MODE_Msk 0x1000UL
+#define SCB_CTRL_ADDR_ACCEPT_Pos 16UL
+#define SCB_CTRL_ADDR_ACCEPT_Msk 0x10000UL
+#define SCB_CTRL_BLOCK_Pos 17UL
+#define SCB_CTRL_BLOCK_Msk 0x20000UL
+#define SCB_CTRL_MODE_Pos 24UL
+#define SCB_CTRL_MODE_Msk 0x3000000UL
+#define SCB_CTRL_ENABLED_Pos 31UL
+#define SCB_CTRL_ENABLED_Msk 0x80000000UL
+/* SCB.STATUS */
+#define SCB_STATUS_EC_BUSY_Pos 0UL
+#define SCB_STATUS_EC_BUSY_Msk 0x1UL
+/* SCB.CMD_RESP_CTRL */
+#define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Pos 0UL
+#define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Msk 0x1FFUL
+#define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Pos 16UL
+#define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Msk 0x1FF0000UL
+/* SCB.CMD_RESP_STATUS */
+#define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Pos 0UL
+#define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Msk 0x1FFUL
+#define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Pos 16UL
+#define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Msk 0x1FF0000UL
+#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Pos 30UL
+#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Msk 0x40000000UL
+#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Pos 31UL
+#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Msk 0x80000000UL
+/* SCB.SPI_CTRL */
+#define SCB_SPI_CTRL_SSEL_CONTINUOUS_Pos 0UL
+#define SCB_SPI_CTRL_SSEL_CONTINUOUS_Msk 0x1UL
+#define SCB_SPI_CTRL_SELECT_PRECEDE_Pos 1UL
+#define SCB_SPI_CTRL_SELECT_PRECEDE_Msk 0x2UL
+#define SCB_SPI_CTRL_CPHA_Pos 2UL
+#define SCB_SPI_CTRL_CPHA_Msk 0x4UL
+#define SCB_SPI_CTRL_CPOL_Pos 3UL
+#define SCB_SPI_CTRL_CPOL_Msk 0x8UL
+#define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Pos 4UL
+#define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Msk 0x10UL
+#define SCB_SPI_CTRL_SCLK_CONTINUOUS_Pos 5UL
+#define SCB_SPI_CTRL_SCLK_CONTINUOUS_Msk 0x20UL
+#define SCB_SPI_CTRL_SSEL_POLARITY0_Pos 8UL
+#define SCB_SPI_CTRL_SSEL_POLARITY0_Msk 0x100UL
+#define SCB_SPI_CTRL_SSEL_POLARITY1_Pos 9UL
+#define SCB_SPI_CTRL_SSEL_POLARITY1_Msk 0x200UL
+#define SCB_SPI_CTRL_SSEL_POLARITY2_Pos 10UL
+#define SCB_SPI_CTRL_SSEL_POLARITY2_Msk 0x400UL
+#define SCB_SPI_CTRL_SSEL_POLARITY3_Pos 11UL
+#define SCB_SPI_CTRL_SSEL_POLARITY3_Msk 0x800UL
+#define SCB_SPI_CTRL_LOOPBACK_Pos 16UL
+#define SCB_SPI_CTRL_LOOPBACK_Msk 0x10000UL
+#define SCB_SPI_CTRL_MODE_Pos 24UL
+#define SCB_SPI_CTRL_MODE_Msk 0x3000000UL
+#define SCB_SPI_CTRL_SSEL_Pos 26UL
+#define SCB_SPI_CTRL_SSEL_Msk 0xC000000UL
+#define SCB_SPI_CTRL_MASTER_MODE_Pos 31UL
+#define SCB_SPI_CTRL_MASTER_MODE_Msk 0x80000000UL
+/* SCB.SPI_STATUS */
+#define SCB_SPI_STATUS_BUS_BUSY_Pos 0UL
+#define SCB_SPI_STATUS_BUS_BUSY_Msk 0x1UL
+#define SCB_SPI_STATUS_SPI_EC_BUSY_Pos 1UL
+#define SCB_SPI_STATUS_SPI_EC_BUSY_Msk 0x2UL
+#define SCB_SPI_STATUS_CURR_EZ_ADDR_Pos 8UL
+#define SCB_SPI_STATUS_CURR_EZ_ADDR_Msk 0xFF00UL
+#define SCB_SPI_STATUS_BASE_EZ_ADDR_Pos 16UL
+#define SCB_SPI_STATUS_BASE_EZ_ADDR_Msk 0xFF0000UL
+/* SCB.UART_CTRL */
+#define SCB_UART_CTRL_LOOPBACK_Pos 16UL
+#define SCB_UART_CTRL_LOOPBACK_Msk 0x10000UL
+#define SCB_UART_CTRL_MODE_Pos 24UL
+#define SCB_UART_CTRL_MODE_Msk 0x3000000UL
+/* SCB.UART_TX_CTRL */
+#define SCB_UART_TX_CTRL_STOP_BITS_Pos 0UL
+#define SCB_UART_TX_CTRL_STOP_BITS_Msk 0x7UL
+#define SCB_UART_TX_CTRL_PARITY_Pos 4UL
+#define SCB_UART_TX_CTRL_PARITY_Msk 0x10UL
+#define SCB_UART_TX_CTRL_PARITY_ENABLED_Pos 5UL
+#define SCB_UART_TX_CTRL_PARITY_ENABLED_Msk 0x20UL
+#define SCB_UART_TX_CTRL_RETRY_ON_NACK_Pos 8UL
+#define SCB_UART_TX_CTRL_RETRY_ON_NACK_Msk 0x100UL
+/* SCB.UART_RX_CTRL */
+#define SCB_UART_RX_CTRL_STOP_BITS_Pos 0UL
+#define SCB_UART_RX_CTRL_STOP_BITS_Msk 0x7UL
+#define SCB_UART_RX_CTRL_PARITY_Pos 4UL
+#define SCB_UART_RX_CTRL_PARITY_Msk 0x10UL
+#define SCB_UART_RX_CTRL_PARITY_ENABLED_Pos 5UL
+#define SCB_UART_RX_CTRL_PARITY_ENABLED_Msk 0x20UL
+#define SCB_UART_RX_CTRL_POLARITY_Pos 6UL
+#define SCB_UART_RX_CTRL_POLARITY_Msk 0x40UL
+#define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Pos 8UL
+#define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Msk 0x100UL
+#define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Pos 9UL
+#define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Msk 0x200UL
+#define SCB_UART_RX_CTRL_MP_MODE_Pos 10UL
+#define SCB_UART_RX_CTRL_MP_MODE_Msk 0x400UL
+#define SCB_UART_RX_CTRL_LIN_MODE_Pos 12UL
+#define SCB_UART_RX_CTRL_LIN_MODE_Msk 0x1000UL
+#define SCB_UART_RX_CTRL_SKIP_START_Pos 13UL
+#define SCB_UART_RX_CTRL_SKIP_START_Msk 0x2000UL
+#define SCB_UART_RX_CTRL_BREAK_WIDTH_Pos 16UL
+#define SCB_UART_RX_CTRL_BREAK_WIDTH_Msk 0xF0000UL
+/* SCB.UART_RX_STATUS */
+#define SCB_UART_RX_STATUS_BR_COUNTER_Pos 0UL
+#define SCB_UART_RX_STATUS_BR_COUNTER_Msk 0xFFFUL
+/* SCB.UART_FLOW_CTRL */
+#define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Pos 0UL
+#define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Msk 0xFFUL
+#define SCB_UART_FLOW_CTRL_RTS_POLARITY_Pos 16UL
+#define SCB_UART_FLOW_CTRL_RTS_POLARITY_Msk 0x10000UL
+#define SCB_UART_FLOW_CTRL_CTS_POLARITY_Pos 24UL
+#define SCB_UART_FLOW_CTRL_CTS_POLARITY_Msk 0x1000000UL
+#define SCB_UART_FLOW_CTRL_CTS_ENABLED_Pos 25UL
+#define SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk 0x2000000UL
+/* SCB.I2C_CTRL */
+#define SCB_I2C_CTRL_HIGH_PHASE_OVS_Pos 0UL
+#define SCB_I2C_CTRL_HIGH_PHASE_OVS_Msk 0xFUL
+#define SCB_I2C_CTRL_LOW_PHASE_OVS_Pos 4UL
+#define SCB_I2C_CTRL_LOW_PHASE_OVS_Msk 0xF0UL
+#define SCB_I2C_CTRL_M_READY_DATA_ACK_Pos 8UL
+#define SCB_I2C_CTRL_M_READY_DATA_ACK_Msk 0x100UL
+#define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Pos 9UL
+#define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Msk 0x200UL
+#define SCB_I2C_CTRL_S_GENERAL_IGNORE_Pos 11UL
+#define SCB_I2C_CTRL_S_GENERAL_IGNORE_Msk 0x800UL
+#define SCB_I2C_CTRL_S_READY_ADDR_ACK_Pos 12UL
+#define SCB_I2C_CTRL_S_READY_ADDR_ACK_Msk 0x1000UL
+#define SCB_I2C_CTRL_S_READY_DATA_ACK_Pos 13UL
+#define SCB_I2C_CTRL_S_READY_DATA_ACK_Msk 0x2000UL
+#define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Pos 14UL
+#define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Msk 0x4000UL
+#define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Pos 15UL
+#define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk 0x8000UL
+#define SCB_I2C_CTRL_LOOPBACK_Pos 16UL
+#define SCB_I2C_CTRL_LOOPBACK_Msk 0x10000UL
+#define SCB_I2C_CTRL_SLAVE_MODE_Pos 30UL
+#define SCB_I2C_CTRL_SLAVE_MODE_Msk 0x40000000UL
+#define SCB_I2C_CTRL_MASTER_MODE_Pos 31UL
+#define SCB_I2C_CTRL_MASTER_MODE_Msk 0x80000000UL
+/* SCB.I2C_STATUS */
+#define SCB_I2C_STATUS_BUS_BUSY_Pos 0UL
+#define SCB_I2C_STATUS_BUS_BUSY_Msk 0x1UL
+#define SCB_I2C_STATUS_I2C_EC_BUSY_Pos 1UL
+#define SCB_I2C_STATUS_I2C_EC_BUSY_Msk 0x2UL
+#define SCB_I2C_STATUS_S_READ_Pos 4UL
+#define SCB_I2C_STATUS_S_READ_Msk 0x10UL
+#define SCB_I2C_STATUS_M_READ_Pos 5UL
+#define SCB_I2C_STATUS_M_READ_Msk 0x20UL
+#define SCB_I2C_STATUS_CURR_EZ_ADDR_Pos 8UL
+#define SCB_I2C_STATUS_CURR_EZ_ADDR_Msk 0xFF00UL
+#define SCB_I2C_STATUS_BASE_EZ_ADDR_Pos 16UL
+#define SCB_I2C_STATUS_BASE_EZ_ADDR_Msk 0xFF0000UL
+/* SCB.I2C_M_CMD */
+#define SCB_I2C_M_CMD_M_START_Pos 0UL
+#define SCB_I2C_M_CMD_M_START_Msk 0x1UL
+#define SCB_I2C_M_CMD_M_START_ON_IDLE_Pos 1UL
+#define SCB_I2C_M_CMD_M_START_ON_IDLE_Msk 0x2UL
+#define SCB_I2C_M_CMD_M_ACK_Pos 2UL
+#define SCB_I2C_M_CMD_M_ACK_Msk 0x4UL
+#define SCB_I2C_M_CMD_M_NACK_Pos 3UL
+#define SCB_I2C_M_CMD_M_NACK_Msk 0x8UL
+#define SCB_I2C_M_CMD_M_STOP_Pos 4UL
+#define SCB_I2C_M_CMD_M_STOP_Msk 0x10UL
+/* SCB.I2C_S_CMD */
+#define SCB_I2C_S_CMD_S_ACK_Pos 0UL
+#define SCB_I2C_S_CMD_S_ACK_Msk 0x1UL
+#define SCB_I2C_S_CMD_S_NACK_Pos 1UL
+#define SCB_I2C_S_CMD_S_NACK_Msk 0x2UL
+/* SCB.I2C_CFG */
+#define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Pos 0UL
+#define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Msk 0x3UL
+#define SCB_I2C_CFG_SDA_IN_FILT_SEL_Pos 4UL
+#define SCB_I2C_CFG_SDA_IN_FILT_SEL_Msk 0x10UL
+#define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Pos 8UL
+#define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Msk 0x300UL
+#define SCB_I2C_CFG_SCL_IN_FILT_SEL_Pos 12UL
+#define SCB_I2C_CFG_SCL_IN_FILT_SEL_Msk 0x1000UL
+#define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Pos 16UL
+#define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Msk 0x30000UL
+#define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Pos 18UL
+#define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Msk 0xC0000UL
+#define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Pos 20UL
+#define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Msk 0x300000UL
+#define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Pos 28UL
+#define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Msk 0x30000000UL
+/* SCB.TX_CTRL */
+#define SCB_TX_CTRL_DATA_WIDTH_Pos 0UL
+#define SCB_TX_CTRL_DATA_WIDTH_Msk 0xFUL
+#define SCB_TX_CTRL_MSB_FIRST_Pos 8UL
+#define SCB_TX_CTRL_MSB_FIRST_Msk 0x100UL
+#define SCB_TX_CTRL_OPEN_DRAIN_Pos 16UL
+#define SCB_TX_CTRL_OPEN_DRAIN_Msk 0x10000UL
+/* SCB.TX_FIFO_CTRL */
+#define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Pos 0UL
+#define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Msk 0xFFUL
+#define SCB_TX_FIFO_CTRL_CLEAR_Pos 16UL
+#define SCB_TX_FIFO_CTRL_CLEAR_Msk 0x10000UL
+#define SCB_TX_FIFO_CTRL_FREEZE_Pos 17UL
+#define SCB_TX_FIFO_CTRL_FREEZE_Msk 0x20000UL
+/* SCB.TX_FIFO_STATUS */
+#define SCB_TX_FIFO_STATUS_USED_Pos 0UL
+#define SCB_TX_FIFO_STATUS_USED_Msk 0x1FFUL
+#define SCB_TX_FIFO_STATUS_SR_VALID_Pos 15UL
+#define SCB_TX_FIFO_STATUS_SR_VALID_Msk 0x8000UL
+#define SCB_TX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define SCB_TX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
+#define SCB_TX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define SCB_TX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
+/* SCB.TX_FIFO_WR */
+#define SCB_TX_FIFO_WR_DATA_Pos 0UL
+#define SCB_TX_FIFO_WR_DATA_Msk 0xFFFFUL
+/* SCB.RX_CTRL */
+#define SCB_RX_CTRL_DATA_WIDTH_Pos 0UL
+#define SCB_RX_CTRL_DATA_WIDTH_Msk 0xFUL
+#define SCB_RX_CTRL_MSB_FIRST_Pos 8UL
+#define SCB_RX_CTRL_MSB_FIRST_Msk 0x100UL
+#define SCB_RX_CTRL_MEDIAN_Pos 9UL
+#define SCB_RX_CTRL_MEDIAN_Msk 0x200UL
+/* SCB.RX_FIFO_CTRL */
+#define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos 0UL
+#define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk 0xFFUL
+#define SCB_RX_FIFO_CTRL_CLEAR_Pos 16UL
+#define SCB_RX_FIFO_CTRL_CLEAR_Msk 0x10000UL
+#define SCB_RX_FIFO_CTRL_FREEZE_Pos 17UL
+#define SCB_RX_FIFO_CTRL_FREEZE_Msk 0x20000UL
+/* SCB.RX_FIFO_STATUS */
+#define SCB_RX_FIFO_STATUS_USED_Pos 0UL
+#define SCB_RX_FIFO_STATUS_USED_Msk 0x1FFUL
+#define SCB_RX_FIFO_STATUS_SR_VALID_Pos 15UL
+#define SCB_RX_FIFO_STATUS_SR_VALID_Msk 0x8000UL
+#define SCB_RX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define SCB_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
+#define SCB_RX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define SCB_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
+/* SCB.RX_MATCH */
+#define SCB_RX_MATCH_ADDR_Pos 0UL
+#define SCB_RX_MATCH_ADDR_Msk 0xFFUL
+#define SCB_RX_MATCH_MASK_Pos 16UL
+#define SCB_RX_MATCH_MASK_Msk 0xFF0000UL
+/* SCB.RX_FIFO_RD */
+#define SCB_RX_FIFO_RD_DATA_Pos 0UL
+#define SCB_RX_FIFO_RD_DATA_Msk 0xFFFFUL
+/* SCB.RX_FIFO_RD_SILENT */
+#define SCB_RX_FIFO_RD_SILENT_DATA_Pos 0UL
+#define SCB_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFUL
+/* SCB.EZ_DATA */
+#define SCB_EZ_DATA_EZ_DATA_Pos 0UL
+#define SCB_EZ_DATA_EZ_DATA_Msk 0xFFUL
+/* SCB.INTR_CAUSE */
+#define SCB_INTR_CAUSE_M_Pos 0UL
+#define SCB_INTR_CAUSE_M_Msk 0x1UL
+#define SCB_INTR_CAUSE_S_Pos 1UL
+#define SCB_INTR_CAUSE_S_Msk 0x2UL
+#define SCB_INTR_CAUSE_TX_Pos 2UL
+#define SCB_INTR_CAUSE_TX_Msk 0x4UL
+#define SCB_INTR_CAUSE_RX_Pos 3UL
+#define SCB_INTR_CAUSE_RX_Msk 0x8UL
+#define SCB_INTR_CAUSE_I2C_EC_Pos 4UL
+#define SCB_INTR_CAUSE_I2C_EC_Msk 0x10UL
+#define SCB_INTR_CAUSE_SPI_EC_Pos 5UL
+#define SCB_INTR_CAUSE_SPI_EC_Msk 0x20UL
+/* SCB.INTR_I2C_EC */
+#define SCB_INTR_I2C_EC_WAKE_UP_Pos 0UL
+#define SCB_INTR_I2C_EC_WAKE_UP_Msk 0x1UL
+#define SCB_INTR_I2C_EC_EZ_STOP_Pos 1UL
+#define SCB_INTR_I2C_EC_EZ_STOP_Msk 0x2UL
+#define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Pos 2UL
+#define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Msk 0x4UL
+#define SCB_INTR_I2C_EC_EZ_READ_STOP_Pos 3UL
+#define SCB_INTR_I2C_EC_EZ_READ_STOP_Msk 0x8UL
+/* SCB.INTR_I2C_EC_MASK */
+#define SCB_INTR_I2C_EC_MASK_WAKE_UP_Pos 0UL
+#define SCB_INTR_I2C_EC_MASK_WAKE_UP_Msk 0x1UL
+#define SCB_INTR_I2C_EC_MASK_EZ_STOP_Pos 1UL
+#define SCB_INTR_I2C_EC_MASK_EZ_STOP_Msk 0x2UL
+#define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Pos 2UL
+#define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Msk 0x4UL
+#define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Pos 3UL
+#define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Msk 0x8UL
+/* SCB.INTR_I2C_EC_MASKED */
+#define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Pos 0UL
+#define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Msk 0x1UL
+#define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Pos 1UL
+#define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Msk 0x2UL
+#define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Pos 2UL
+#define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Msk 0x4UL
+#define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Pos 3UL
+#define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Msk 0x8UL
+/* SCB.INTR_SPI_EC */
+#define SCB_INTR_SPI_EC_WAKE_UP_Pos 0UL
+#define SCB_INTR_SPI_EC_WAKE_UP_Msk 0x1UL
+#define SCB_INTR_SPI_EC_EZ_STOP_Pos 1UL
+#define SCB_INTR_SPI_EC_EZ_STOP_Msk 0x2UL
+#define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Pos 2UL
+#define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Msk 0x4UL
+#define SCB_INTR_SPI_EC_EZ_READ_STOP_Pos 3UL
+#define SCB_INTR_SPI_EC_EZ_READ_STOP_Msk 0x8UL
+/* SCB.INTR_SPI_EC_MASK */
+#define SCB_INTR_SPI_EC_MASK_WAKE_UP_Pos 0UL
+#define SCB_INTR_SPI_EC_MASK_WAKE_UP_Msk 0x1UL
+#define SCB_INTR_SPI_EC_MASK_EZ_STOP_Pos 1UL
+#define SCB_INTR_SPI_EC_MASK_EZ_STOP_Msk 0x2UL
+#define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Pos 2UL
+#define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Msk 0x4UL
+#define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Pos 3UL
+#define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Msk 0x8UL
+/* SCB.INTR_SPI_EC_MASKED */
+#define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Pos 0UL
+#define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Msk 0x1UL
+#define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Pos 1UL
+#define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Msk 0x2UL
+#define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Pos 2UL
+#define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Msk 0x4UL
+#define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Pos 3UL
+#define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Msk 0x8UL
+/* SCB.INTR_M */
+#define SCB_INTR_M_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_M_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_M_I2C_NACK_Pos 1UL
+#define SCB_INTR_M_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_M_I2C_ACK_Pos 2UL
+#define SCB_INTR_M_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_M_I2C_STOP_Pos 4UL
+#define SCB_INTR_M_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_M_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_M_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_M_SPI_DONE_Pos 9UL
+#define SCB_INTR_M_SPI_DONE_Msk 0x200UL
+/* SCB.INTR_M_SET */
+#define SCB_INTR_M_SET_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_M_SET_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_M_SET_I2C_NACK_Pos 1UL
+#define SCB_INTR_M_SET_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_M_SET_I2C_ACK_Pos 2UL
+#define SCB_INTR_M_SET_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_M_SET_I2C_STOP_Pos 4UL
+#define SCB_INTR_M_SET_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_M_SET_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_M_SET_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_M_SET_SPI_DONE_Pos 9UL
+#define SCB_INTR_M_SET_SPI_DONE_Msk 0x200UL
+/* SCB.INTR_M_MASK */
+#define SCB_INTR_M_MASK_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_M_MASK_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_M_MASK_I2C_NACK_Pos 1UL
+#define SCB_INTR_M_MASK_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_M_MASK_I2C_ACK_Pos 2UL
+#define SCB_INTR_M_MASK_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_M_MASK_I2C_STOP_Pos 4UL
+#define SCB_INTR_M_MASK_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_M_MASK_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_M_MASK_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_M_MASK_SPI_DONE_Pos 9UL
+#define SCB_INTR_M_MASK_SPI_DONE_Msk 0x200UL
+/* SCB.INTR_M_MASKED */
+#define SCB_INTR_M_MASKED_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_M_MASKED_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_M_MASKED_I2C_NACK_Pos 1UL
+#define SCB_INTR_M_MASKED_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_M_MASKED_I2C_ACK_Pos 2UL
+#define SCB_INTR_M_MASKED_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_M_MASKED_I2C_STOP_Pos 4UL
+#define SCB_INTR_M_MASKED_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_M_MASKED_SPI_DONE_Pos 9UL
+#define SCB_INTR_M_MASKED_SPI_DONE_Msk 0x200UL
+/* SCB.INTR_S */
+#define SCB_INTR_S_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_S_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_S_I2C_NACK_Pos 1UL
+#define SCB_INTR_S_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_S_I2C_ACK_Pos 2UL
+#define SCB_INTR_S_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_S_I2C_WRITE_STOP_Pos 3UL
+#define SCB_INTR_S_I2C_WRITE_STOP_Msk 0x8UL
+#define SCB_INTR_S_I2C_STOP_Pos 4UL
+#define SCB_INTR_S_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_S_I2C_START_Pos 5UL
+#define SCB_INTR_S_I2C_START_Msk 0x20UL
+#define SCB_INTR_S_I2C_ADDR_MATCH_Pos 6UL
+#define SCB_INTR_S_I2C_ADDR_MATCH_Msk 0x40UL
+#define SCB_INTR_S_I2C_GENERAL_Pos 7UL
+#define SCB_INTR_S_I2C_GENERAL_Msk 0x80UL
+#define SCB_INTR_S_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_S_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_S_SPI_EZ_WRITE_STOP_Pos 9UL
+#define SCB_INTR_S_SPI_EZ_WRITE_STOP_Msk 0x200UL
+#define SCB_INTR_S_SPI_EZ_STOP_Pos 10UL
+#define SCB_INTR_S_SPI_EZ_STOP_Msk 0x400UL
+#define SCB_INTR_S_SPI_BUS_ERROR_Pos 11UL
+#define SCB_INTR_S_SPI_BUS_ERROR_Msk 0x800UL
+/* SCB.INTR_S_SET */
+#define SCB_INTR_S_SET_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_S_SET_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_S_SET_I2C_NACK_Pos 1UL
+#define SCB_INTR_S_SET_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_S_SET_I2C_ACK_Pos 2UL
+#define SCB_INTR_S_SET_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_S_SET_I2C_WRITE_STOP_Pos 3UL
+#define SCB_INTR_S_SET_I2C_WRITE_STOP_Msk 0x8UL
+#define SCB_INTR_S_SET_I2C_STOP_Pos 4UL
+#define SCB_INTR_S_SET_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_S_SET_I2C_START_Pos 5UL
+#define SCB_INTR_S_SET_I2C_START_Msk 0x20UL
+#define SCB_INTR_S_SET_I2C_ADDR_MATCH_Pos 6UL
+#define SCB_INTR_S_SET_I2C_ADDR_MATCH_Msk 0x40UL
+#define SCB_INTR_S_SET_I2C_GENERAL_Pos 7UL
+#define SCB_INTR_S_SET_I2C_GENERAL_Msk 0x80UL
+#define SCB_INTR_S_SET_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_S_SET_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Pos 9UL
+#define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Msk 0x200UL
+#define SCB_INTR_S_SET_SPI_EZ_STOP_Pos 10UL
+#define SCB_INTR_S_SET_SPI_EZ_STOP_Msk 0x400UL
+#define SCB_INTR_S_SET_SPI_BUS_ERROR_Pos 11UL
+#define SCB_INTR_S_SET_SPI_BUS_ERROR_Msk 0x800UL
+/* SCB.INTR_S_MASK */
+#define SCB_INTR_S_MASK_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_S_MASK_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_S_MASK_I2C_NACK_Pos 1UL
+#define SCB_INTR_S_MASK_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_S_MASK_I2C_ACK_Pos 2UL
+#define SCB_INTR_S_MASK_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_S_MASK_I2C_WRITE_STOP_Pos 3UL
+#define SCB_INTR_S_MASK_I2C_WRITE_STOP_Msk 0x8UL
+#define SCB_INTR_S_MASK_I2C_STOP_Pos 4UL
+#define SCB_INTR_S_MASK_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_S_MASK_I2C_START_Pos 5UL
+#define SCB_INTR_S_MASK_I2C_START_Msk 0x20UL
+#define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Pos 6UL
+#define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Msk 0x40UL
+#define SCB_INTR_S_MASK_I2C_GENERAL_Pos 7UL
+#define SCB_INTR_S_MASK_I2C_GENERAL_Msk 0x80UL
+#define SCB_INTR_S_MASK_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_S_MASK_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Pos 9UL
+#define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Msk 0x200UL
+#define SCB_INTR_S_MASK_SPI_EZ_STOP_Pos 10UL
+#define SCB_INTR_S_MASK_SPI_EZ_STOP_Msk 0x400UL
+#define SCB_INTR_S_MASK_SPI_BUS_ERROR_Pos 11UL
+#define SCB_INTR_S_MASK_SPI_BUS_ERROR_Msk 0x800UL
+/* SCB.INTR_S_MASKED */
+#define SCB_INTR_S_MASKED_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_S_MASKED_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_S_MASKED_I2C_NACK_Pos 1UL
+#define SCB_INTR_S_MASKED_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_S_MASKED_I2C_ACK_Pos 2UL
+#define SCB_INTR_S_MASKED_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Pos 3UL
+#define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Msk 0x8UL
+#define SCB_INTR_S_MASKED_I2C_STOP_Pos 4UL
+#define SCB_INTR_S_MASKED_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_S_MASKED_I2C_START_Pos 5UL
+#define SCB_INTR_S_MASKED_I2C_START_Msk 0x20UL
+#define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Pos 6UL
+#define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Msk 0x40UL
+#define SCB_INTR_S_MASKED_I2C_GENERAL_Pos 7UL
+#define SCB_INTR_S_MASKED_I2C_GENERAL_Msk 0x80UL
+#define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Pos 9UL
+#define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Msk 0x200UL
+#define SCB_INTR_S_MASKED_SPI_EZ_STOP_Pos 10UL
+#define SCB_INTR_S_MASKED_SPI_EZ_STOP_Msk 0x400UL
+#define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Pos 11UL
+#define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Msk 0x800UL
+/* SCB.INTR_TX */
+#define SCB_INTR_TX_TRIGGER_Pos 0UL
+#define SCB_INTR_TX_TRIGGER_Msk 0x1UL
+#define SCB_INTR_TX_NOT_FULL_Pos 1UL
+#define SCB_INTR_TX_NOT_FULL_Msk 0x2UL
+#define SCB_INTR_TX_EMPTY_Pos 4UL
+#define SCB_INTR_TX_EMPTY_Msk 0x10UL
+#define SCB_INTR_TX_OVERFLOW_Pos 5UL
+#define SCB_INTR_TX_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_TX_UNDERFLOW_Pos 6UL
+#define SCB_INTR_TX_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_TX_BLOCKED_Pos 7UL
+#define SCB_INTR_TX_BLOCKED_Msk 0x80UL
+#define SCB_INTR_TX_UART_NACK_Pos 8UL
+#define SCB_INTR_TX_UART_NACK_Msk 0x100UL
+#define SCB_INTR_TX_UART_DONE_Pos 9UL
+#define SCB_INTR_TX_UART_DONE_Msk 0x200UL
+#define SCB_INTR_TX_UART_ARB_LOST_Pos 10UL
+#define SCB_INTR_TX_UART_ARB_LOST_Msk 0x400UL
+/* SCB.INTR_TX_SET */
+#define SCB_INTR_TX_SET_TRIGGER_Pos 0UL
+#define SCB_INTR_TX_SET_TRIGGER_Msk 0x1UL
+#define SCB_INTR_TX_SET_NOT_FULL_Pos 1UL
+#define SCB_INTR_TX_SET_NOT_FULL_Msk 0x2UL
+#define SCB_INTR_TX_SET_EMPTY_Pos 4UL
+#define SCB_INTR_TX_SET_EMPTY_Msk 0x10UL
+#define SCB_INTR_TX_SET_OVERFLOW_Pos 5UL
+#define SCB_INTR_TX_SET_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_TX_SET_UNDERFLOW_Pos 6UL
+#define SCB_INTR_TX_SET_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_TX_SET_BLOCKED_Pos 7UL
+#define SCB_INTR_TX_SET_BLOCKED_Msk 0x80UL
+#define SCB_INTR_TX_SET_UART_NACK_Pos 8UL
+#define SCB_INTR_TX_SET_UART_NACK_Msk 0x100UL
+#define SCB_INTR_TX_SET_UART_DONE_Pos 9UL
+#define SCB_INTR_TX_SET_UART_DONE_Msk 0x200UL
+#define SCB_INTR_TX_SET_UART_ARB_LOST_Pos 10UL
+#define SCB_INTR_TX_SET_UART_ARB_LOST_Msk 0x400UL
+/* SCB.INTR_TX_MASK */
+#define SCB_INTR_TX_MASK_TRIGGER_Pos 0UL
+#define SCB_INTR_TX_MASK_TRIGGER_Msk 0x1UL
+#define SCB_INTR_TX_MASK_NOT_FULL_Pos 1UL
+#define SCB_INTR_TX_MASK_NOT_FULL_Msk 0x2UL
+#define SCB_INTR_TX_MASK_EMPTY_Pos 4UL
+#define SCB_INTR_TX_MASK_EMPTY_Msk 0x10UL
+#define SCB_INTR_TX_MASK_OVERFLOW_Pos 5UL
+#define SCB_INTR_TX_MASK_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_TX_MASK_UNDERFLOW_Pos 6UL
+#define SCB_INTR_TX_MASK_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_TX_MASK_BLOCKED_Pos 7UL
+#define SCB_INTR_TX_MASK_BLOCKED_Msk 0x80UL
+#define SCB_INTR_TX_MASK_UART_NACK_Pos 8UL
+#define SCB_INTR_TX_MASK_UART_NACK_Msk 0x100UL
+#define SCB_INTR_TX_MASK_UART_DONE_Pos 9UL
+#define SCB_INTR_TX_MASK_UART_DONE_Msk 0x200UL
+#define SCB_INTR_TX_MASK_UART_ARB_LOST_Pos 10UL
+#define SCB_INTR_TX_MASK_UART_ARB_LOST_Msk 0x400UL
+/* SCB.INTR_TX_MASKED */
+#define SCB_INTR_TX_MASKED_TRIGGER_Pos 0UL
+#define SCB_INTR_TX_MASKED_TRIGGER_Msk 0x1UL
+#define SCB_INTR_TX_MASKED_NOT_FULL_Pos 1UL
+#define SCB_INTR_TX_MASKED_NOT_FULL_Msk 0x2UL
+#define SCB_INTR_TX_MASKED_EMPTY_Pos 4UL
+#define SCB_INTR_TX_MASKED_EMPTY_Msk 0x10UL
+#define SCB_INTR_TX_MASKED_OVERFLOW_Pos 5UL
+#define SCB_INTR_TX_MASKED_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_TX_MASKED_UNDERFLOW_Pos 6UL
+#define SCB_INTR_TX_MASKED_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_TX_MASKED_BLOCKED_Pos 7UL
+#define SCB_INTR_TX_MASKED_BLOCKED_Msk 0x80UL
+#define SCB_INTR_TX_MASKED_UART_NACK_Pos 8UL
+#define SCB_INTR_TX_MASKED_UART_NACK_Msk 0x100UL
+#define SCB_INTR_TX_MASKED_UART_DONE_Pos 9UL
+#define SCB_INTR_TX_MASKED_UART_DONE_Msk 0x200UL
+#define SCB_INTR_TX_MASKED_UART_ARB_LOST_Pos 10UL
+#define SCB_INTR_TX_MASKED_UART_ARB_LOST_Msk 0x400UL
+/* SCB.INTR_RX */
+#define SCB_INTR_RX_TRIGGER_Pos 0UL
+#define SCB_INTR_RX_TRIGGER_Msk 0x1UL
+#define SCB_INTR_RX_NOT_EMPTY_Pos 2UL
+#define SCB_INTR_RX_NOT_EMPTY_Msk 0x4UL
+#define SCB_INTR_RX_FULL_Pos 3UL
+#define SCB_INTR_RX_FULL_Msk 0x8UL
+#define SCB_INTR_RX_OVERFLOW_Pos 5UL
+#define SCB_INTR_RX_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_RX_UNDERFLOW_Pos 6UL
+#define SCB_INTR_RX_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_RX_BLOCKED_Pos 7UL
+#define SCB_INTR_RX_BLOCKED_Msk 0x80UL
+#define SCB_INTR_RX_FRAME_ERROR_Pos 8UL
+#define SCB_INTR_RX_FRAME_ERROR_Msk 0x100UL
+#define SCB_INTR_RX_PARITY_ERROR_Pos 9UL
+#define SCB_INTR_RX_PARITY_ERROR_Msk 0x200UL
+#define SCB_INTR_RX_BAUD_DETECT_Pos 10UL
+#define SCB_INTR_RX_BAUD_DETECT_Msk 0x400UL
+#define SCB_INTR_RX_BREAK_DETECT_Pos 11UL
+#define SCB_INTR_RX_BREAK_DETECT_Msk 0x800UL
+/* SCB.INTR_RX_SET */
+#define SCB_INTR_RX_SET_TRIGGER_Pos 0UL
+#define SCB_INTR_RX_SET_TRIGGER_Msk 0x1UL
+#define SCB_INTR_RX_SET_NOT_EMPTY_Pos 2UL
+#define SCB_INTR_RX_SET_NOT_EMPTY_Msk 0x4UL
+#define SCB_INTR_RX_SET_FULL_Pos 3UL
+#define SCB_INTR_RX_SET_FULL_Msk 0x8UL
+#define SCB_INTR_RX_SET_OVERFLOW_Pos 5UL
+#define SCB_INTR_RX_SET_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_RX_SET_UNDERFLOW_Pos 6UL
+#define SCB_INTR_RX_SET_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_RX_SET_BLOCKED_Pos 7UL
+#define SCB_INTR_RX_SET_BLOCKED_Msk 0x80UL
+#define SCB_INTR_RX_SET_FRAME_ERROR_Pos 8UL
+#define SCB_INTR_RX_SET_FRAME_ERROR_Msk 0x100UL
+#define SCB_INTR_RX_SET_PARITY_ERROR_Pos 9UL
+#define SCB_INTR_RX_SET_PARITY_ERROR_Msk 0x200UL
+#define SCB_INTR_RX_SET_BAUD_DETECT_Pos 10UL
+#define SCB_INTR_RX_SET_BAUD_DETECT_Msk 0x400UL
+#define SCB_INTR_RX_SET_BREAK_DETECT_Pos 11UL
+#define SCB_INTR_RX_SET_BREAK_DETECT_Msk 0x800UL
+/* SCB.INTR_RX_MASK */
+#define SCB_INTR_RX_MASK_TRIGGER_Pos 0UL
+#define SCB_INTR_RX_MASK_TRIGGER_Msk 0x1UL
+#define SCB_INTR_RX_MASK_NOT_EMPTY_Pos 2UL
+#define SCB_INTR_RX_MASK_NOT_EMPTY_Msk 0x4UL
+#define SCB_INTR_RX_MASK_FULL_Pos 3UL
+#define SCB_INTR_RX_MASK_FULL_Msk 0x8UL
+#define SCB_INTR_RX_MASK_OVERFLOW_Pos 5UL
+#define SCB_INTR_RX_MASK_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_RX_MASK_UNDERFLOW_Pos 6UL
+#define SCB_INTR_RX_MASK_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_RX_MASK_BLOCKED_Pos 7UL
+#define SCB_INTR_RX_MASK_BLOCKED_Msk 0x80UL
+#define SCB_INTR_RX_MASK_FRAME_ERROR_Pos 8UL
+#define SCB_INTR_RX_MASK_FRAME_ERROR_Msk 0x100UL
+#define SCB_INTR_RX_MASK_PARITY_ERROR_Pos 9UL
+#define SCB_INTR_RX_MASK_PARITY_ERROR_Msk 0x200UL
+#define SCB_INTR_RX_MASK_BAUD_DETECT_Pos 10UL
+#define SCB_INTR_RX_MASK_BAUD_DETECT_Msk 0x400UL
+#define SCB_INTR_RX_MASK_BREAK_DETECT_Pos 11UL
+#define SCB_INTR_RX_MASK_BREAK_DETECT_Msk 0x800UL
+/* SCB.INTR_RX_MASKED */
+#define SCB_INTR_RX_MASKED_TRIGGER_Pos 0UL
+#define SCB_INTR_RX_MASKED_TRIGGER_Msk 0x1UL
+#define SCB_INTR_RX_MASKED_NOT_EMPTY_Pos 2UL
+#define SCB_INTR_RX_MASKED_NOT_EMPTY_Msk 0x4UL
+#define SCB_INTR_RX_MASKED_FULL_Pos 3UL
+#define SCB_INTR_RX_MASKED_FULL_Msk 0x8UL
+#define SCB_INTR_RX_MASKED_OVERFLOW_Pos 5UL
+#define SCB_INTR_RX_MASKED_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_RX_MASKED_UNDERFLOW_Pos 6UL
+#define SCB_INTR_RX_MASKED_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_RX_MASKED_BLOCKED_Pos 7UL
+#define SCB_INTR_RX_MASKED_BLOCKED_Msk 0x80UL
+#define SCB_INTR_RX_MASKED_FRAME_ERROR_Pos 8UL
+#define SCB_INTR_RX_MASKED_FRAME_ERROR_Msk 0x100UL
+#define SCB_INTR_RX_MASKED_PARITY_ERROR_Pos 9UL
+#define SCB_INTR_RX_MASKED_PARITY_ERROR_Msk 0x200UL
+#define SCB_INTR_RX_MASKED_BAUD_DETECT_Pos 10UL
+#define SCB_INTR_RX_MASKED_BAUD_DETECT_Msk 0x400UL
+#define SCB_INTR_RX_MASKED_BREAK_DETECT_Pos 11UL
+#define SCB_INTR_RX_MASKED_BREAK_DETECT_Msk 0x800UL
+
+
+#endif /* _CYIP_SCB_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_sdhc.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_sdhc.h
new file mode 100644
index 0000000000..5a84a7d3e5
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_sdhc.h
@@ -0,0 +1,858 @@
+/***************************************************************************//**
+* \file cyip_sdhc.h
+*
+* \brief
+* SDHC IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_SDHC_H_
+#define _CYIP_SDHC_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SDHC
+*******************************************************************************/
+
+#define SDHC_WRAP_SECTION_SIZE 0x00000020UL
+#define SDHC_CORE_SECTION_SIZE 0x00001000UL
+#define SDHC_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief MMIO at SDHC wrapper level (SDHC_WRAP)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Top level wrapper control */
+ __IM uint32_t RESERVED[7];
+} SDHC_WRAP_V1_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief MMIO for Synopsys Mobile Storage Host Controller IP (SDHC_CORE)
+ */
+typedef struct {
+ __IOM uint32_t SDMASA_R; /*!< 0x00000000 SDMA System Address register */
+ __IOM uint16_t BLOCKSIZE_R; /*!< 0x00000004 Block Size register */
+ __IOM uint16_t BLOCKCOUNT_R; /*!< 0x00000006 16-bit Block Count register */
+ __IOM uint32_t ARGUMENT_R; /*!< 0x00000008 Argument register */
+ __IOM uint16_t XFER_MODE_R; /*!< 0x0000000C Transfer Mode register */
+ __IOM uint16_t CMD_R; /*!< 0x0000000E Command register */
+ __IM uint32_t RESP01_R; /*!< 0x00000010 Response Register 0/1 */
+ __IM uint32_t RESP23_R; /*!< 0x00000014 Response Register 2/3 */
+ __IM uint32_t RESP45_R; /*!< 0x00000018 Response Register 4/5 */
+ __IM uint32_t RESP67_R; /*!< 0x0000001C Response Register 6/7 */
+ __IOM uint32_t BUF_DATA_R; /*!< 0x00000020 Buffer Data Port Register */
+ __IM uint32_t PSTATE_REG; /*!< 0x00000024 Present State Register */
+ __IOM uint8_t HOST_CTRL1_R; /*!< 0x00000028 Host Control 1 Register */
+ __IOM uint8_t PWR_CTRL_R; /*!< 0x00000029 Power Control Register */
+ __IOM uint8_t BGAP_CTRL_R; /*!< 0x0000002A Block Gap Control Register */
+ __IOM uint8_t WUP_CTRL_R; /*!< 0x0000002B Wakeup Control Register */
+ __IOM uint16_t CLK_CTRL_R; /*!< 0x0000002C Clock Control Register */
+ __IOM uint8_t TOUT_CTRL_R; /*!< 0x0000002E Timeout Control Register */
+ __IOM uint8_t SW_RST_R; /*!< 0x0000002F Software Reset Register */
+ __IOM uint16_t NORMAL_INT_STAT_R; /*!< 0x00000030 Normal Interrupt Status Register */
+ __IOM uint16_t ERROR_INT_STAT_R; /*!< 0x00000032 Error Interrupt Status Register */
+ __IOM uint16_t NORMAL_INT_STAT_EN_R; /*!< 0x00000034 Normal Interrupt Status Enable Register */
+ __IOM uint16_t ERROR_INT_STAT_EN_R; /*!< 0x00000036 Error Interrupt Status Enable Register */
+ __IOM uint16_t NORMAL_INT_SIGNAL_EN_R; /*!< 0x00000038 Normal Interrupt Signal Enable Register */
+ __IOM uint16_t ERROR_INT_SIGNAL_EN_R; /*!< 0x0000003A Error Interrupt Signal Enable Register */
+ __IM uint16_t AUTO_CMD_STAT_R; /*!< 0x0000003C Auto CMD Status Register */
+ __IOM uint16_t HOST_CTRL2_R; /*!< 0x0000003E Host Control 2 Register */
+ __IM uint32_t CAPABILITIES1_R; /*!< 0x00000040 Capabilities 1 Register - 0 to 31 */
+ __IM uint32_t CAPABILITIES2_R; /*!< 0x00000044 Capabilities Register - 32 to 63 */
+ __IM uint32_t CURR_CAPABILITIES1_R; /*!< 0x00000048 Current Capabilities Register - 0 to 31 */
+ __IM uint32_t CURR_CAPABILITIES2_R; /*!< 0x0000004C Maximum Current Capabilities Register - 32 to 63 */
+ __OM uint16_t FORCE_AUTO_CMD_STAT_R; /*!< 0x00000050 Force Event Register for Auto CMD Error Status register */
+ __IOM uint16_t FORCE_ERROR_INT_STAT_R; /*!< 0x00000052 Force Event Register for Error Interrupt Status */
+ __IM uint8_t ADMA_ERR_STAT_R; /*!< 0x00000054 ADMA Error Status Register */
+ __IM uint8_t RESERVED[3];
+ __IOM uint32_t ADMA_SA_LOW_R; /*!< 0x00000058 ADMA System Address Register - Low */
+ __IM uint32_t RESERVED1[7];
+ __IOM uint32_t ADMA_ID_LOW_R; /*!< 0x00000078 ADMA3 Integrated Descriptor Address Register - Low */
+ __IM uint16_t RESERVED2[65];
+ __IM uint16_t HOST_CNTRL_VERS_R; /*!< 0x000000FE Host Controller Version */
+ __IM uint32_t RESERVED3[32];
+ __IM uint32_t CQVER; /*!< 0x00000180 Command Queuing Version register */
+ __IM uint32_t CQCAP; /*!< 0x00000184 Command Queuing Capabilities register */
+ __IOM uint32_t CQCFG; /*!< 0x00000188 Command Queuing Configuration register */
+ __IOM uint32_t CQCTL; /*!< 0x0000018C Command Queuing Control register */
+ __IOM uint32_t CQIS; /*!< 0x00000190 Command Queuing Interrupt Status register */
+ __IOM uint32_t CQISE; /*!< 0x00000194 Command Queuing Interrupt Status Enable register */
+ __IOM uint32_t CQISGE; /*!< 0x00000198 Command Queuing Interrupt signal enable register */
+ __IOM uint32_t CQIC; /*!< 0x0000019C Command Queuing Interrupt Coalescing register */
+ __IOM uint32_t CQTDLBA; /*!< 0x000001A0 Command Queuing Task Descriptor List Base Address register */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t CQTDBR; /*!< 0x000001A8 Command Queuing DoorBell register */
+ __IOM uint32_t CQTCN; /*!< 0x000001AC Command Queuing TaskClear Notification register */
+ __IM uint32_t CQDQS; /*!< 0x000001B0 Device queue status register */
+ __IM uint32_t CQDPT; /*!< 0x000001B4 Device pending tasks register */
+ __IOM uint32_t CQTCLR; /*!< 0x000001B8 Command Queuing DoorBell register */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t CQSSC1; /*!< 0x000001C0 CQ Send Status Configuration 1 register */
+ __IOM uint32_t CQSSC2; /*!< 0x000001C4 CQ Send Status Configuration 2 register */
+ __IM uint32_t CQCRDCT; /*!< 0x000001C8 Command response for direct command register */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t CQRMEM; /*!< 0x000001D0 Command response mode error mask register */
+ __IM uint32_t CQTERRI; /*!< 0x000001D4 CQ Task Error Information register */
+ __IM uint32_t CQCRI; /*!< 0x000001D8 CQ Command response index */
+ __IM uint32_t CQCRA; /*!< 0x000001DC CQ Command response argument register */
+ __IM uint32_t RESERVED7[200];
+ __IM uint32_t MSHC_VER_ID_R; /*!< 0x00000500 MSHC version */
+ __IM uint32_t MSHC_VER_TYPE_R; /*!< 0x00000504 MSHC version type */
+ __IOM uint8_t MSHC_CTRL_R; /*!< 0x00000508 MSHC Control register */
+ __IM uint8_t RESERVED8[7];
+ __IOM uint8_t MBIU_CTRL_R; /*!< 0x00000510 MBIU Control register */
+ __IM uint8_t RESERVED9[27];
+ __IOM uint16_t EMMC_CTRL_R; /*!< 0x0000052C eMMC Control register */
+ __IOM uint16_t BOOT_CTRL_R; /*!< 0x0000052E eMMC Boot Control register */
+ __IM uint32_t GP_IN_R; /*!< 0x00000530 General Purpose Input register */
+ __IOM uint32_t GP_OUT_R; /*!< 0x00000534 General Purpose Output register */
+ __IM uint32_t RESERVED10[690];
+} SDHC_CORE_V1_Type; /*!< Size = 4096 (0x1000) */
+
+/**
+ * \brief SD/eMMC Host Controller (SDHC)
+ */
+typedef struct {
+ SDHC_WRAP_V1_Type WRAP; /*!< 0x00000000 MMIO at SDHC wrapper level */
+ __IM uint32_t RESERVED[1016];
+ SDHC_CORE_V1_Type CORE; /*!< 0x00001000 MMIO for Synopsys Mobile Storage Host Controller IP */
+} SDHC_V1_Type; /*!< Size = 8192 (0x2000) */
+
+
+/* SDHC_WRAP.CTL */
+#define SDHC_WRAP_CTL_ENABLE_Pos 31UL
+#define SDHC_WRAP_CTL_ENABLE_Msk 0x80000000UL
+
+
+/* SDHC_CORE.SDMASA_R */
+#define SDHC_CORE_SDMASA_R_BLOCKCNT_SDMASA_Pos 0UL
+#define SDHC_CORE_SDMASA_R_BLOCKCNT_SDMASA_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.BLOCKSIZE_R */
+#define SDHC_CORE_BLOCKSIZE_R_XFER_BLOCK_SIZE_Pos 0UL
+#define SDHC_CORE_BLOCKSIZE_R_XFER_BLOCK_SIZE_Msk 0xFFFUL
+#define SDHC_CORE_BLOCKSIZE_R_SDMA_BUF_BDARY_Pos 12UL
+#define SDHC_CORE_BLOCKSIZE_R_SDMA_BUF_BDARY_Msk 0x7000UL
+/* SDHC_CORE.BLOCKCOUNT_R */
+#define SDHC_CORE_BLOCKCOUNT_R_BLOCK_CNT_Pos 0UL
+#define SDHC_CORE_BLOCKCOUNT_R_BLOCK_CNT_Msk 0xFFFFUL
+/* SDHC_CORE.ARGUMENT_R */
+#define SDHC_CORE_ARGUMENT_R_ARGUMENT_Pos 0UL
+#define SDHC_CORE_ARGUMENT_R_ARGUMENT_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.XFER_MODE_R */
+#define SDHC_CORE_XFER_MODE_R_DMA_ENABLE_Pos 0UL
+#define SDHC_CORE_XFER_MODE_R_DMA_ENABLE_Msk 0x1UL
+#define SDHC_CORE_XFER_MODE_R_BLOCK_COUNT_ENABLE_Pos 1UL
+#define SDHC_CORE_XFER_MODE_R_BLOCK_COUNT_ENABLE_Msk 0x2UL
+#define SDHC_CORE_XFER_MODE_R_AUTO_CMD_ENABLE_Pos 2UL
+#define SDHC_CORE_XFER_MODE_R_AUTO_CMD_ENABLE_Msk 0xCUL
+#define SDHC_CORE_XFER_MODE_R_DATA_XFER_DIR_Pos 4UL
+#define SDHC_CORE_XFER_MODE_R_DATA_XFER_DIR_Msk 0x10UL
+#define SDHC_CORE_XFER_MODE_R_MULTI_BLK_SEL_Pos 5UL
+#define SDHC_CORE_XFER_MODE_R_MULTI_BLK_SEL_Msk 0x20UL
+#define SDHC_CORE_XFER_MODE_R_RESP_TYPE_Pos 6UL
+#define SDHC_CORE_XFER_MODE_R_RESP_TYPE_Msk 0x40UL
+#define SDHC_CORE_XFER_MODE_R_RESP_ERR_CHK_ENABLE_Pos 7UL
+#define SDHC_CORE_XFER_MODE_R_RESP_ERR_CHK_ENABLE_Msk 0x80UL
+#define SDHC_CORE_XFER_MODE_R_RESP_INT_DISABLE_Pos 8UL
+#define SDHC_CORE_XFER_MODE_R_RESP_INT_DISABLE_Msk 0x100UL
+/* SDHC_CORE.CMD_R */
+#define SDHC_CORE_CMD_R_RESP_TYPE_SELECT_Pos 0UL
+#define SDHC_CORE_CMD_R_RESP_TYPE_SELECT_Msk 0x3UL
+#define SDHC_CORE_CMD_R_SUB_CMD_FLAG_Pos 2UL
+#define SDHC_CORE_CMD_R_SUB_CMD_FLAG_Msk 0x4UL
+#define SDHC_CORE_CMD_R_CMD_CRC_CHK_ENABLE_Pos 3UL
+#define SDHC_CORE_CMD_R_CMD_CRC_CHK_ENABLE_Msk 0x8UL
+#define SDHC_CORE_CMD_R_CMD_IDX_CHK_ENABLE_Pos 4UL
+#define SDHC_CORE_CMD_R_CMD_IDX_CHK_ENABLE_Msk 0x10UL
+#define SDHC_CORE_CMD_R_DATA_PRESENT_SEL_Pos 5UL
+#define SDHC_CORE_CMD_R_DATA_PRESENT_SEL_Msk 0x20UL
+#define SDHC_CORE_CMD_R_CMD_TYPE_Pos 6UL
+#define SDHC_CORE_CMD_R_CMD_TYPE_Msk 0xC0UL
+#define SDHC_CORE_CMD_R_CMD_INDEX_Pos 8UL
+#define SDHC_CORE_CMD_R_CMD_INDEX_Msk 0x3F00UL
+/* SDHC_CORE.RESP01_R */
+#define SDHC_CORE_RESP01_R_RESP01_Pos 0UL
+#define SDHC_CORE_RESP01_R_RESP01_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.RESP23_R */
+#define SDHC_CORE_RESP23_R_RESP23_Pos 0UL
+#define SDHC_CORE_RESP23_R_RESP23_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.RESP45_R */
+#define SDHC_CORE_RESP45_R_RESP45_Pos 0UL
+#define SDHC_CORE_RESP45_R_RESP45_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.RESP67_R */
+#define SDHC_CORE_RESP67_R_RESP67_Pos 0UL
+#define SDHC_CORE_RESP67_R_RESP67_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.BUF_DATA_R */
+#define SDHC_CORE_BUF_DATA_R_BUF_DATA_Pos 0UL
+#define SDHC_CORE_BUF_DATA_R_BUF_DATA_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.PSTATE_REG */
+#define SDHC_CORE_PSTATE_REG_CMD_INHIBIT_Pos 0UL
+#define SDHC_CORE_PSTATE_REG_CMD_INHIBIT_Msk 0x1UL
+#define SDHC_CORE_PSTATE_REG_CMD_INHIBIT_DAT_Pos 1UL
+#define SDHC_CORE_PSTATE_REG_CMD_INHIBIT_DAT_Msk 0x2UL
+#define SDHC_CORE_PSTATE_REG_DAT_LINE_ACTIVE_Pos 2UL
+#define SDHC_CORE_PSTATE_REG_DAT_LINE_ACTIVE_Msk 0x4UL
+#define SDHC_CORE_PSTATE_REG_DAT_7_4_Pos 4UL
+#define SDHC_CORE_PSTATE_REG_DAT_7_4_Msk 0xF0UL
+#define SDHC_CORE_PSTATE_REG_WR_XFER_ACTIVE_Pos 8UL
+#define SDHC_CORE_PSTATE_REG_WR_XFER_ACTIVE_Msk 0x100UL
+#define SDHC_CORE_PSTATE_REG_RD_XFER_ACTIVE_Pos 9UL
+#define SDHC_CORE_PSTATE_REG_RD_XFER_ACTIVE_Msk 0x200UL
+#define SDHC_CORE_PSTATE_REG_BUF_WR_ENABLE_Pos 10UL
+#define SDHC_CORE_PSTATE_REG_BUF_WR_ENABLE_Msk 0x400UL
+#define SDHC_CORE_PSTATE_REG_BUF_RD_ENABLE_Pos 11UL
+#define SDHC_CORE_PSTATE_REG_BUF_RD_ENABLE_Msk 0x800UL
+#define SDHC_CORE_PSTATE_REG_CARD_INSERTED_Pos 16UL
+#define SDHC_CORE_PSTATE_REG_CARD_INSERTED_Msk 0x10000UL
+#define SDHC_CORE_PSTATE_REG_CARD_STABLE_Pos 17UL
+#define SDHC_CORE_PSTATE_REG_CARD_STABLE_Msk 0x20000UL
+#define SDHC_CORE_PSTATE_REG_CARD_DETECT_PIN_LEVEL_Pos 18UL
+#define SDHC_CORE_PSTATE_REG_CARD_DETECT_PIN_LEVEL_Msk 0x40000UL
+#define SDHC_CORE_PSTATE_REG_WR_PROTECT_SW_LVL_Pos 19UL
+#define SDHC_CORE_PSTATE_REG_WR_PROTECT_SW_LVL_Msk 0x80000UL
+#define SDHC_CORE_PSTATE_REG_DAT_3_0_Pos 20UL
+#define SDHC_CORE_PSTATE_REG_DAT_3_0_Msk 0xF00000UL
+#define SDHC_CORE_PSTATE_REG_CMD_LINE_LVL_Pos 24UL
+#define SDHC_CORE_PSTATE_REG_CMD_LINE_LVL_Msk 0x1000000UL
+#define SDHC_CORE_PSTATE_REG_HOST_REG_VOL_Pos 25UL
+#define SDHC_CORE_PSTATE_REG_HOST_REG_VOL_Msk 0x2000000UL
+#define SDHC_CORE_PSTATE_REG_CMD_ISSU_ERR_Pos 27UL
+#define SDHC_CORE_PSTATE_REG_CMD_ISSU_ERR_Msk 0x8000000UL
+#define SDHC_CORE_PSTATE_REG_SUB_CMD_STAT_Pos 28UL
+#define SDHC_CORE_PSTATE_REG_SUB_CMD_STAT_Msk 0x10000000UL
+/* SDHC_CORE.HOST_CTRL1_R */
+#define SDHC_CORE_HOST_CTRL1_R_LED_CTRL_Pos 0UL
+#define SDHC_CORE_HOST_CTRL1_R_LED_CTRL_Msk 0x1UL
+#define SDHC_CORE_HOST_CTRL1_R_DAT_XFER_WIDTH_Pos 1UL
+#define SDHC_CORE_HOST_CTRL1_R_DAT_XFER_WIDTH_Msk 0x2UL
+#define SDHC_CORE_HOST_CTRL1_R_HIGH_SPEED_EN_Pos 2UL
+#define SDHC_CORE_HOST_CTRL1_R_HIGH_SPEED_EN_Msk 0x4UL
+#define SDHC_CORE_HOST_CTRL1_R_DMA_SEL_Pos 3UL
+#define SDHC_CORE_HOST_CTRL1_R_DMA_SEL_Msk 0x18UL
+#define SDHC_CORE_HOST_CTRL1_R_EXT_DAT_XFER_Pos 5UL
+#define SDHC_CORE_HOST_CTRL1_R_EXT_DAT_XFER_Msk 0x20UL
+#define SDHC_CORE_HOST_CTRL1_R_CARD_DETECT_TEST_LVL_Pos 6UL
+#define SDHC_CORE_HOST_CTRL1_R_CARD_DETECT_TEST_LVL_Msk 0x40UL
+#define SDHC_CORE_HOST_CTRL1_R_CARD_DETECT_SIG_SEL_Pos 7UL
+#define SDHC_CORE_HOST_CTRL1_R_CARD_DETECT_SIG_SEL_Msk 0x80UL
+/* SDHC_CORE.PWR_CTRL_R */
+#define SDHC_CORE_PWR_CTRL_R_SD_BUS_PWR_VDD1_Pos 0UL
+#define SDHC_CORE_PWR_CTRL_R_SD_BUS_PWR_VDD1_Msk 0x1UL
+#define SDHC_CORE_PWR_CTRL_R_SD_BUS_VOL_VDD1_Pos 1UL
+#define SDHC_CORE_PWR_CTRL_R_SD_BUS_VOL_VDD1_Msk 0xEUL
+/* SDHC_CORE.BGAP_CTRL_R */
+#define SDHC_CORE_BGAP_CTRL_R_STOP_BG_REQ_Pos 0UL
+#define SDHC_CORE_BGAP_CTRL_R_STOP_BG_REQ_Msk 0x1UL
+#define SDHC_CORE_BGAP_CTRL_R_CONTINUE_REQ_Pos 1UL
+#define SDHC_CORE_BGAP_CTRL_R_CONTINUE_REQ_Msk 0x2UL
+#define SDHC_CORE_BGAP_CTRL_R_RD_WAIT_CTRL_Pos 2UL
+#define SDHC_CORE_BGAP_CTRL_R_RD_WAIT_CTRL_Msk 0x4UL
+#define SDHC_CORE_BGAP_CTRL_R_INT_AT_BGAP_Pos 3UL
+#define SDHC_CORE_BGAP_CTRL_R_INT_AT_BGAP_Msk 0x8UL
+/* SDHC_CORE.WUP_CTRL_R */
+#define SDHC_CORE_WUP_CTRL_R_WUP_CARD_INT_Pos 0UL
+#define SDHC_CORE_WUP_CTRL_R_WUP_CARD_INT_Msk 0x1UL
+#define SDHC_CORE_WUP_CTRL_R_WUP_CARD_INSERT_Pos 1UL
+#define SDHC_CORE_WUP_CTRL_R_WUP_CARD_INSERT_Msk 0x2UL
+#define SDHC_CORE_WUP_CTRL_R_WUP_CARD_REMOVAL_Pos 2UL
+#define SDHC_CORE_WUP_CTRL_R_WUP_CARD_REMOVAL_Msk 0x4UL
+/* SDHC_CORE.CLK_CTRL_R */
+#define SDHC_CORE_CLK_CTRL_R_INTERNAL_CLK_EN_Pos 0UL
+#define SDHC_CORE_CLK_CTRL_R_INTERNAL_CLK_EN_Msk 0x1UL
+#define SDHC_CORE_CLK_CTRL_R_INTERNAL_CLK_STABLE_Pos 1UL
+#define SDHC_CORE_CLK_CTRL_R_INTERNAL_CLK_STABLE_Msk 0x2UL
+#define SDHC_CORE_CLK_CTRL_R_SD_CLK_EN_Pos 2UL
+#define SDHC_CORE_CLK_CTRL_R_SD_CLK_EN_Msk 0x4UL
+#define SDHC_CORE_CLK_CTRL_R_PLL_ENABLE_Pos 3UL
+#define SDHC_CORE_CLK_CTRL_R_PLL_ENABLE_Msk 0x8UL
+#define SDHC_CORE_CLK_CTRL_R_CLK_GEN_SELECT_Pos 5UL
+#define SDHC_CORE_CLK_CTRL_R_CLK_GEN_SELECT_Msk 0x20UL
+#define SDHC_CORE_CLK_CTRL_R_UPPER_FREQ_SEL_Pos 6UL
+#define SDHC_CORE_CLK_CTRL_R_UPPER_FREQ_SEL_Msk 0xC0UL
+#define SDHC_CORE_CLK_CTRL_R_FREQ_SEL_Pos 8UL
+#define SDHC_CORE_CLK_CTRL_R_FREQ_SEL_Msk 0xFF00UL
+/* SDHC_CORE.TOUT_CTRL_R */
+#define SDHC_CORE_TOUT_CTRL_R_TOUT_CNT_Pos 0UL
+#define SDHC_CORE_TOUT_CTRL_R_TOUT_CNT_Msk 0xFUL
+/* SDHC_CORE.SW_RST_R */
+#define SDHC_CORE_SW_RST_R_SW_RST_ALL_Pos 0UL
+#define SDHC_CORE_SW_RST_R_SW_RST_ALL_Msk 0x1UL
+#define SDHC_CORE_SW_RST_R_SW_RST_CMD_Pos 1UL
+#define SDHC_CORE_SW_RST_R_SW_RST_CMD_Msk 0x2UL
+#define SDHC_CORE_SW_RST_R_SW_RST_DAT_Pos 2UL
+#define SDHC_CORE_SW_RST_R_SW_RST_DAT_Msk 0x4UL
+/* SDHC_CORE.NORMAL_INT_STAT_R */
+#define SDHC_CORE_NORMAL_INT_STAT_R_CMD_COMPLETE_Pos 0UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_CMD_COMPLETE_Msk 0x1UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_XFER_COMPLETE_Pos 1UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_XFER_COMPLETE_Msk 0x2UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_BGAP_EVENT_Pos 2UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_BGAP_EVENT_Msk 0x4UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_DMA_INTERRUPT_Pos 3UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_DMA_INTERRUPT_Msk 0x8UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_BUF_WR_READY_Pos 4UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_BUF_WR_READY_Msk 0x10UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_BUF_RD_READY_Pos 5UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_BUF_RD_READY_Msk 0x20UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_CARD_INSERTION_Pos 6UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_CARD_INSERTION_Msk 0x40UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_CARD_REMOVAL_Pos 7UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_CARD_REMOVAL_Msk 0x80UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_CARD_INTERRUPT_Pos 8UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_CARD_INTERRUPT_Msk 0x100UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_FX_EVENT_Pos 13UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_FX_EVENT_Msk 0x2000UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_CQE_EVENT_Pos 14UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_CQE_EVENT_Msk 0x4000UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_ERR_INTERRUPT_Pos 15UL
+#define SDHC_CORE_NORMAL_INT_STAT_R_ERR_INTERRUPT_Msk 0x8000UL
+/* SDHC_CORE.ERROR_INT_STAT_R */
+#define SDHC_CORE_ERROR_INT_STAT_R_CMD_TOUT_ERR_Pos 0UL
+#define SDHC_CORE_ERROR_INT_STAT_R_CMD_TOUT_ERR_Msk 0x1UL
+#define SDHC_CORE_ERROR_INT_STAT_R_CMD_CRC_ERR_Pos 1UL
+#define SDHC_CORE_ERROR_INT_STAT_R_CMD_CRC_ERR_Msk 0x2UL
+#define SDHC_CORE_ERROR_INT_STAT_R_CMD_END_BIT_ERR_Pos 2UL
+#define SDHC_CORE_ERROR_INT_STAT_R_CMD_END_BIT_ERR_Msk 0x4UL
+#define SDHC_CORE_ERROR_INT_STAT_R_CMD_IDX_ERR_Pos 3UL
+#define SDHC_CORE_ERROR_INT_STAT_R_CMD_IDX_ERR_Msk 0x8UL
+#define SDHC_CORE_ERROR_INT_STAT_R_DATA_TOUT_ERR_Pos 4UL
+#define SDHC_CORE_ERROR_INT_STAT_R_DATA_TOUT_ERR_Msk 0x10UL
+#define SDHC_CORE_ERROR_INT_STAT_R_DATA_CRC_ERR_Pos 5UL
+#define SDHC_CORE_ERROR_INT_STAT_R_DATA_CRC_ERR_Msk 0x20UL
+#define SDHC_CORE_ERROR_INT_STAT_R_DATA_END_BIT_ERR_Pos 6UL
+#define SDHC_CORE_ERROR_INT_STAT_R_DATA_END_BIT_ERR_Msk 0x40UL
+#define SDHC_CORE_ERROR_INT_STAT_R_CUR_LMT_ERR_Pos 7UL
+#define SDHC_CORE_ERROR_INT_STAT_R_CUR_LMT_ERR_Msk 0x80UL
+#define SDHC_CORE_ERROR_INT_STAT_R_AUTO_CMD_ERR_Pos 8UL
+#define SDHC_CORE_ERROR_INT_STAT_R_AUTO_CMD_ERR_Msk 0x100UL
+#define SDHC_CORE_ERROR_INT_STAT_R_ADMA_ERR_Pos 9UL
+#define SDHC_CORE_ERROR_INT_STAT_R_ADMA_ERR_Msk 0x200UL
+#define SDHC_CORE_ERROR_INT_STAT_R_TUNING_ERR_Pos 10UL
+#define SDHC_CORE_ERROR_INT_STAT_R_TUNING_ERR_Msk 0x400UL
+#define SDHC_CORE_ERROR_INT_STAT_R_RESP_ERR_Pos 11UL
+#define SDHC_CORE_ERROR_INT_STAT_R_RESP_ERR_Msk 0x800UL
+#define SDHC_CORE_ERROR_INT_STAT_R_BOOT_ACK_ERR_Pos 12UL
+#define SDHC_CORE_ERROR_INT_STAT_R_BOOT_ACK_ERR_Msk 0x1000UL
+/* SDHC_CORE.NORMAL_INT_STAT_EN_R */
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_CMD_COMPLETE_STAT_EN_Pos 0UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_CMD_COMPLETE_STAT_EN_Msk 0x1UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_XFER_COMPLETE_STAT_EN_Pos 1UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_XFER_COMPLETE_STAT_EN_Msk 0x2UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_BGAP_EVENT_STAT_EN_Pos 2UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_BGAP_EVENT_STAT_EN_Msk 0x4UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_DMA_INTERRUPT_STAT_EN_Pos 3UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_DMA_INTERRUPT_STAT_EN_Msk 0x8UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_BUF_WR_READY_STAT_EN_Pos 4UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_BUF_WR_READY_STAT_EN_Msk 0x10UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_BUF_RD_READY_STAT_EN_Pos 5UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_BUF_RD_READY_STAT_EN_Msk 0x20UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_CARD_INSERTION_STAT_EN_Pos 6UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_CARD_INSERTION_STAT_EN_Msk 0x40UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_CARD_REMOVAL_STAT_EN_Pos 7UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_CARD_REMOVAL_STAT_EN_Msk 0x80UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_CARD_INTERRUPT_STAT_EN_Pos 8UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_CARD_INTERRUPT_STAT_EN_Msk 0x100UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_INT_A_STAT_EN_Pos 9UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_INT_A_STAT_EN_Msk 0x200UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_INT_B_STAT_EN_Pos 10UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_INT_B_STAT_EN_Msk 0x400UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_INT_C_STAT_EN_Pos 11UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_INT_C_STAT_EN_Msk 0x800UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_RE_TUNE_EVENT_STAT_EN_Pos 12UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_RE_TUNE_EVENT_STAT_EN_Msk 0x1000UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_FX_EVENT_STAT_EN_Pos 13UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_FX_EVENT_STAT_EN_Msk 0x2000UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_CQE_EVENT_STAT_EN_Pos 14UL
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R_CQE_EVENT_STAT_EN_Msk 0x4000UL
+/* SDHC_CORE.ERROR_INT_STAT_EN_R */
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_TOUT_ERR_STAT_EN_Pos 0UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_TOUT_ERR_STAT_EN_Msk 0x1UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_CRC_ERR_STAT_EN_Pos 1UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_CRC_ERR_STAT_EN_Msk 0x2UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_END_BIT_ERR_STAT_EN_Pos 2UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_END_BIT_ERR_STAT_EN_Msk 0x4UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_IDX_ERR_STAT_EN_Pos 3UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_IDX_ERR_STAT_EN_Msk 0x8UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_DATA_TOUT_ERR_STAT_EN_Pos 4UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_DATA_TOUT_ERR_STAT_EN_Msk 0x10UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_DATA_CRC_ERR_STAT_EN_Pos 5UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_DATA_CRC_ERR_STAT_EN_Msk 0x20UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_DATA_END_BIT_ERR_STAT_EN_Pos 6UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_DATA_END_BIT_ERR_STAT_EN_Msk 0x40UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_CUR_LMT_ERR_STAT_EN_Pos 7UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_CUR_LMT_ERR_STAT_EN_Msk 0x80UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_AUTO_CMD_ERR_STAT_EN_Pos 8UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_AUTO_CMD_ERR_STAT_EN_Msk 0x100UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_ADMA_ERR_STAT_EN_Pos 9UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_ADMA_ERR_STAT_EN_Msk 0x200UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_TUNING_ERR_STAT_EN_Pos 10UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_TUNING_ERR_STAT_EN_Msk 0x400UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_RESP_ERR_STAT_EN_Pos 11UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_RESP_ERR_STAT_EN_Msk 0x800UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_BOOT_ACK_ERR_STAT_EN_Pos 12UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_BOOT_ACK_ERR_STAT_EN_Msk 0x1000UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_VENDOR_ERR_STAT_EN1_Pos 13UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_VENDOR_ERR_STAT_EN1_Msk 0x2000UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_VENDOR_ERR_STAT_EN2_Pos 14UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_VENDOR_ERR_STAT_EN2_Msk 0x4000UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_VENDOR_ERR_STAT_EN3_Pos 15UL
+#define SDHC_CORE_ERROR_INT_STAT_EN_R_VENDOR_ERR_STAT_EN3_Msk 0x8000UL
+/* SDHC_CORE.NORMAL_INT_SIGNAL_EN_R */
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CMD_COMPLETE_SIGNAL_EN_Pos 0UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CMD_COMPLETE_SIGNAL_EN_Msk 0x1UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_XFER_COMPLETE_SIGNAL_EN_Pos 1UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_XFER_COMPLETE_SIGNAL_EN_Msk 0x2UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_BGAP_EVENT_SIGNAL_EN_Pos 2UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_BGAP_EVENT_SIGNAL_EN_Msk 0x4UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_DMA_INTERRUPT_SIGNAL_EN_Pos 3UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_DMA_INTERRUPT_SIGNAL_EN_Msk 0x8UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_BUF_WR_READY_SIGNAL_EN_Pos 4UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_BUF_WR_READY_SIGNAL_EN_Msk 0x10UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_BUF_RD_READY_SIGNAL_EN_Pos 5UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_BUF_RD_READY_SIGNAL_EN_Msk 0x20UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CARD_INSERTION_SIGNAL_EN_Pos 6UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CARD_INSERTION_SIGNAL_EN_Msk 0x40UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CARD_REMOVAL_SIGNAL_EN_Pos 7UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CARD_REMOVAL_SIGNAL_EN_Msk 0x80UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CARD_INTERRUPT_SIGNAL_EN_Pos 8UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CARD_INTERRUPT_SIGNAL_EN_Msk 0x100UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_INT_A_SIGNAL_EN_Pos 9UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_INT_A_SIGNAL_EN_Msk 0x200UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_INT_B_SIGNAL_EN_Pos 10UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_INT_B_SIGNAL_EN_Msk 0x400UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_INT_C_SIGNAL_EN_Pos 11UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_INT_C_SIGNAL_EN_Msk 0x800UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_RE_TUNE_EVENT_SIGNAL_EN_Pos 12UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_RE_TUNE_EVENT_SIGNAL_EN_Msk 0x1000UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_FX_EVENT_SIGNAL_EN_Pos 13UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_FX_EVENT_SIGNAL_EN_Msk 0x2000UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CQE_EVENT_SIGNAL_EN_Pos 14UL
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CQE_EVENT_SIGNAL_EN_Msk 0x4000UL
+/* SDHC_CORE.ERROR_INT_SIGNAL_EN_R */
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_TOUT_ERR_SIGNAL_EN_Pos 0UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_TOUT_ERR_SIGNAL_EN_Msk 0x1UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_CRC_ERR_SIGNAL_EN_Pos 1UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_CRC_ERR_SIGNAL_EN_Msk 0x2UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_END_BIT_ERR_SIGNAL_EN_Pos 2UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_END_BIT_ERR_SIGNAL_EN_Msk 0x4UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_IDX_ERR_SIGNAL_EN_Pos 3UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_IDX_ERR_SIGNAL_EN_Msk 0x8UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_DATA_TOUT_ERR_SIGNAL_EN_Pos 4UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_DATA_TOUT_ERR_SIGNAL_EN_Msk 0x10UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_DATA_CRC_ERR_SIGNAL_EN_Pos 5UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_DATA_CRC_ERR_SIGNAL_EN_Msk 0x20UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_DATA_END_BIT_ERR_SIGNAL_EN_Pos 6UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_DATA_END_BIT_ERR_SIGNAL_EN_Msk 0x40UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CUR_LMT_ERR_SIGNAL_EN_Pos 7UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CUR_LMT_ERR_SIGNAL_EN_Msk 0x80UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_AUTO_CMD_ERR_SIGNAL_EN_Pos 8UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_AUTO_CMD_ERR_SIGNAL_EN_Msk 0x100UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_ADMA_ERR_SIGNAL_EN_Pos 9UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_ADMA_ERR_SIGNAL_EN_Msk 0x200UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_TUNING_ERR_SIGNAL_EN_Pos 10UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_TUNING_ERR_SIGNAL_EN_Msk 0x400UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_RESP_ERR_SIGNAL_EN_Pos 11UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_RESP_ERR_SIGNAL_EN_Msk 0x800UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_BOOT_ACK_ERR_SIGNAL_EN_Pos 12UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_BOOT_ACK_ERR_SIGNAL_EN_Msk 0x1000UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_VENDOR_ERR_SIGNAL_EN1_Pos 13UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_VENDOR_ERR_SIGNAL_EN1_Msk 0x2000UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_VENDOR_ERR_SIGNAL_EN2_Pos 14UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_VENDOR_ERR_SIGNAL_EN2_Msk 0x4000UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_VENDOR_ERR_SIGNAL_EN3_Pos 15UL
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_VENDOR_ERR_SIGNAL_EN3_Msk 0x8000UL
+/* SDHC_CORE.AUTO_CMD_STAT_R */
+#define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD12_NOT_EXEC_Pos 0UL
+#define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD12_NOT_EXEC_Msk 0x1UL
+#define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_TOUT_ERR_Pos 1UL
+#define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_TOUT_ERR_Msk 0x2UL
+#define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_CRC_ERR_Pos 2UL
+#define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_CRC_ERR_Msk 0x4UL
+#define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_EBIT_ERR_Pos 3UL
+#define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_EBIT_ERR_Msk 0x8UL
+#define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_IDX_ERR_Pos 4UL
+#define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_IDX_ERR_Msk 0x10UL
+#define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_RESP_ERR_Pos 5UL
+#define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_RESP_ERR_Msk 0x20UL
+#define SDHC_CORE_AUTO_CMD_STAT_R_CMD_NOT_ISSUED_AUTO_CMD12_Pos 7UL
+#define SDHC_CORE_AUTO_CMD_STAT_R_CMD_NOT_ISSUED_AUTO_CMD12_Msk 0x80UL
+/* SDHC_CORE.HOST_CTRL2_R */
+#define SDHC_CORE_HOST_CTRL2_R_UHS_MODE_SEL_Pos 0UL
+#define SDHC_CORE_HOST_CTRL2_R_UHS_MODE_SEL_Msk 0x7UL
+#define SDHC_CORE_HOST_CTRL2_R_SIGNALING_EN_Pos 3UL
+#define SDHC_CORE_HOST_CTRL2_R_SIGNALING_EN_Msk 0x8UL
+#define SDHC_CORE_HOST_CTRL2_R_DRV_STRENGTH_SEL_Pos 4UL
+#define SDHC_CORE_HOST_CTRL2_R_DRV_STRENGTH_SEL_Msk 0x30UL
+#define SDHC_CORE_HOST_CTRL2_R_EXEC_TUNING_Pos 6UL
+#define SDHC_CORE_HOST_CTRL2_R_EXEC_TUNING_Msk 0x40UL
+#define SDHC_CORE_HOST_CTRL2_R_SAMPLE_CLK_SEL_Pos 7UL
+#define SDHC_CORE_HOST_CTRL2_R_SAMPLE_CLK_SEL_Msk 0x80UL
+#define SDHC_CORE_HOST_CTRL2_R_UHS2_IF_ENABLE_Pos 8UL
+#define SDHC_CORE_HOST_CTRL2_R_UHS2_IF_ENABLE_Msk 0x100UL
+#define SDHC_CORE_HOST_CTRL2_R_ADMA2_LEN_MODE_Pos 10UL
+#define SDHC_CORE_HOST_CTRL2_R_ADMA2_LEN_MODE_Msk 0x400UL
+#define SDHC_CORE_HOST_CTRL2_R_CMD23_ENABLE_Pos 11UL
+#define SDHC_CORE_HOST_CTRL2_R_CMD23_ENABLE_Msk 0x800UL
+#define SDHC_CORE_HOST_CTRL2_R_HOST_VER4_ENABLE_Pos 12UL
+#define SDHC_CORE_HOST_CTRL2_R_HOST_VER4_ENABLE_Msk 0x1000UL
+#define SDHC_CORE_HOST_CTRL2_R_ADDRESSING_Pos 13UL
+#define SDHC_CORE_HOST_CTRL2_R_ADDRESSING_Msk 0x2000UL
+#define SDHC_CORE_HOST_CTRL2_R_ASYNC_INT_ENABLE_Pos 14UL
+#define SDHC_CORE_HOST_CTRL2_R_ASYNC_INT_ENABLE_Msk 0x4000UL
+#define SDHC_CORE_HOST_CTRL2_R_PRESET_VAL_ENABLE_Pos 15UL
+#define SDHC_CORE_HOST_CTRL2_R_PRESET_VAL_ENABLE_Msk 0x8000UL
+/* SDHC_CORE.CAPABILITIES1_R */
+#define SDHC_CORE_CAPABILITIES1_R_TOUT_CLK_FREQ_Pos 0UL
+#define SDHC_CORE_CAPABILITIES1_R_TOUT_CLK_FREQ_Msk 0x3FUL
+#define SDHC_CORE_CAPABILITIES1_R_TOUT_CLK_UNIT_Pos 7UL
+#define SDHC_CORE_CAPABILITIES1_R_TOUT_CLK_UNIT_Msk 0x80UL
+#define SDHC_CORE_CAPABILITIES1_R_BASE_CLK_FREQ_Pos 8UL
+#define SDHC_CORE_CAPABILITIES1_R_BASE_CLK_FREQ_Msk 0xFF00UL
+#define SDHC_CORE_CAPABILITIES1_R_MAX_BLK_LEN_Pos 16UL
+#define SDHC_CORE_CAPABILITIES1_R_MAX_BLK_LEN_Msk 0x30000UL
+#define SDHC_CORE_CAPABILITIES1_R_EMBEDDED_8_BIT_Pos 18UL
+#define SDHC_CORE_CAPABILITIES1_R_EMBEDDED_8_BIT_Msk 0x40000UL
+#define SDHC_CORE_CAPABILITIES1_R_ADMA2_SUPPORT_Pos 19UL
+#define SDHC_CORE_CAPABILITIES1_R_ADMA2_SUPPORT_Msk 0x80000UL
+#define SDHC_CORE_CAPABILITIES1_R_HIGH_SPEED_SUPPORT_Pos 21UL
+#define SDHC_CORE_CAPABILITIES1_R_HIGH_SPEED_SUPPORT_Msk 0x200000UL
+#define SDHC_CORE_CAPABILITIES1_R_SDMA_SUPPORT_Pos 22UL
+#define SDHC_CORE_CAPABILITIES1_R_SDMA_SUPPORT_Msk 0x400000UL
+#define SDHC_CORE_CAPABILITIES1_R_SUS_RES_SUPPORT_Pos 23UL
+#define SDHC_CORE_CAPABILITIES1_R_SUS_RES_SUPPORT_Msk 0x800000UL
+#define SDHC_CORE_CAPABILITIES1_R_VOLT_33_Pos 24UL
+#define SDHC_CORE_CAPABILITIES1_R_VOLT_33_Msk 0x1000000UL
+#define SDHC_CORE_CAPABILITIES1_R_VOLT_30_Pos 25UL
+#define SDHC_CORE_CAPABILITIES1_R_VOLT_30_Msk 0x2000000UL
+#define SDHC_CORE_CAPABILITIES1_R_VOLT_18_Pos 26UL
+#define SDHC_CORE_CAPABILITIES1_R_VOLT_18_Msk 0x4000000UL
+#define SDHC_CORE_CAPABILITIES1_R_SYS_ADDR_64_V4_Pos 27UL
+#define SDHC_CORE_CAPABILITIES1_R_SYS_ADDR_64_V4_Msk 0x8000000UL
+#define SDHC_CORE_CAPABILITIES1_R_SYS_ADDR_64_V3_Pos 28UL
+#define SDHC_CORE_CAPABILITIES1_R_SYS_ADDR_64_V3_Msk 0x10000000UL
+#define SDHC_CORE_CAPABILITIES1_R_ASYNC_INT_SUPPORT_Pos 29UL
+#define SDHC_CORE_CAPABILITIES1_R_ASYNC_INT_SUPPORT_Msk 0x20000000UL
+#define SDHC_CORE_CAPABILITIES1_R_SLOT_TYPE_R_Pos 30UL
+#define SDHC_CORE_CAPABILITIES1_R_SLOT_TYPE_R_Msk 0xC0000000UL
+/* SDHC_CORE.CAPABILITIES2_R */
+#define SDHC_CORE_CAPABILITIES2_R_SDR50_SUPPORT_Pos 0UL
+#define SDHC_CORE_CAPABILITIES2_R_SDR50_SUPPORT_Msk 0x1UL
+#define SDHC_CORE_CAPABILITIES2_R_SDR104_SUPPORT_Pos 1UL
+#define SDHC_CORE_CAPABILITIES2_R_SDR104_SUPPORT_Msk 0x2UL
+#define SDHC_CORE_CAPABILITIES2_R_DDR50_SUPPORT_Pos 2UL
+#define SDHC_CORE_CAPABILITIES2_R_DDR50_SUPPORT_Msk 0x4UL
+#define SDHC_CORE_CAPABILITIES2_R_UHS2_SUPPORT_Pos 3UL
+#define SDHC_CORE_CAPABILITIES2_R_UHS2_SUPPORT_Msk 0x8UL
+#define SDHC_CORE_CAPABILITIES2_R_DRV_TYPEA_Pos 4UL
+#define SDHC_CORE_CAPABILITIES2_R_DRV_TYPEA_Msk 0x10UL
+#define SDHC_CORE_CAPABILITIES2_R_DRV_TYPEC_Pos 5UL
+#define SDHC_CORE_CAPABILITIES2_R_DRV_TYPEC_Msk 0x20UL
+#define SDHC_CORE_CAPABILITIES2_R_DRV_TYPED_Pos 6UL
+#define SDHC_CORE_CAPABILITIES2_R_DRV_TYPED_Msk 0x40UL
+#define SDHC_CORE_CAPABILITIES2_R_RETUNE_CNT_Pos 8UL
+#define SDHC_CORE_CAPABILITIES2_R_RETUNE_CNT_Msk 0xF00UL
+#define SDHC_CORE_CAPABILITIES2_R_USE_TUNING_SDR50_Pos 13UL
+#define SDHC_CORE_CAPABILITIES2_R_USE_TUNING_SDR50_Msk 0x2000UL
+#define SDHC_CORE_CAPABILITIES2_R_RE_TUNING_MODES_Pos 14UL
+#define SDHC_CORE_CAPABILITIES2_R_RE_TUNING_MODES_Msk 0xC000UL
+#define SDHC_CORE_CAPABILITIES2_R_CLK_MUL_Pos 16UL
+#define SDHC_CORE_CAPABILITIES2_R_CLK_MUL_Msk 0xFF0000UL
+#define SDHC_CORE_CAPABILITIES2_R_ADMA3_SUPPORT_Pos 27UL
+#define SDHC_CORE_CAPABILITIES2_R_ADMA3_SUPPORT_Msk 0x8000000UL
+#define SDHC_CORE_CAPABILITIES2_R_VDD2_18V_SUPPORT_Pos 28UL
+#define SDHC_CORE_CAPABILITIES2_R_VDD2_18V_SUPPORT_Msk 0x10000000UL
+/* SDHC_CORE.CURR_CAPABILITIES1_R */
+#define SDHC_CORE_CURR_CAPABILITIES1_R_MAX_CUR_33V_Pos 0UL
+#define SDHC_CORE_CURR_CAPABILITIES1_R_MAX_CUR_33V_Msk 0xFFUL
+#define SDHC_CORE_CURR_CAPABILITIES1_R_MAX_CUR_30V_Pos 8UL
+#define SDHC_CORE_CURR_CAPABILITIES1_R_MAX_CUR_30V_Msk 0xFF00UL
+#define SDHC_CORE_CURR_CAPABILITIES1_R_MAX_CUR_18V_Pos 16UL
+#define SDHC_CORE_CURR_CAPABILITIES1_R_MAX_CUR_18V_Msk 0xFF0000UL
+/* SDHC_CORE.CURR_CAPABILITIES2_R */
+#define SDHC_CORE_CURR_CAPABILITIES2_R_MAX_CUR_VDD2_18V_Pos 0UL
+#define SDHC_CORE_CURR_CAPABILITIES2_R_MAX_CUR_VDD2_18V_Msk 0xFFUL
+/* SDHC_CORE.FORCE_AUTO_CMD_STAT_R */
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD12_NOT_EXEC_Pos 0UL
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD12_NOT_EXEC_Msk 0x1UL
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_TOUT_ERR_Pos 1UL
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_TOUT_ERR_Msk 0x2UL
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_CRC_ERR_Pos 2UL
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_CRC_ERR_Msk 0x4UL
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_EBIT_ERR_Pos 3UL
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_EBIT_ERR_Msk 0x8UL
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_IDX_ERR_Pos 4UL
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_IDX_ERR_Msk 0x10UL
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_RESP_ERR_Pos 5UL
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_RESP_ERR_Msk 0x20UL
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_Pos 7UL
+#define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_Msk 0x80UL
+/* SDHC_CORE.FORCE_ERROR_INT_STAT_R */
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_TOUT_ERR_Pos 0UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_TOUT_ERR_Msk 0x1UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_CRC_ERR_Pos 1UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_CRC_ERR_Msk 0x2UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_END_BIT_ERR_Pos 2UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_END_BIT_ERR_Msk 0x4UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_IDX_ERR_Pos 3UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_IDX_ERR_Msk 0x8UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_DATA_TOUT_ERR_Pos 4UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_DATA_TOUT_ERR_Msk 0x10UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_DATA_CRC_ERR_Pos 5UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_DATA_CRC_ERR_Msk 0x20UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_DATA_END_BIT_ERR_Pos 6UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_DATA_END_BIT_ERR_Msk 0x40UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CUR_LMT_ERR_Pos 7UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CUR_LMT_ERR_Msk 0x80UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_AUTO_CMD_ERR_Pos 8UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_AUTO_CMD_ERR_Msk 0x100UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_ADMA_ERR_Pos 9UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_ADMA_ERR_Msk 0x200UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_TUNING_ERR_Pos 10UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_TUNING_ERR_Msk 0x400UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_RESP_ERR_Pos 11UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_RESP_ERR_Msk 0x800UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_BOOT_ACK_ERR_Pos 12UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_BOOT_ACK_ERR_Msk 0x1000UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_VENDOR_ERR1_Pos 13UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_VENDOR_ERR1_Msk 0x2000UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_VENDOR_ERR2_Pos 14UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_VENDOR_ERR2_Msk 0x4000UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_VENDOR_ERR3_Pos 15UL
+#define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_VENDOR_ERR3_Msk 0x8000UL
+/* SDHC_CORE.ADMA_ERR_STAT_R */
+#define SDHC_CORE_ADMA_ERR_STAT_R_ADMA_ERR_STATES_Pos 0UL
+#define SDHC_CORE_ADMA_ERR_STAT_R_ADMA_ERR_STATES_Msk 0x3UL
+#define SDHC_CORE_ADMA_ERR_STAT_R_ADMA_LEN_ERR_Pos 2UL
+#define SDHC_CORE_ADMA_ERR_STAT_R_ADMA_LEN_ERR_Msk 0x4UL
+/* SDHC_CORE.ADMA_SA_LOW_R */
+#define SDHC_CORE_ADMA_SA_LOW_R_ADMA_SA_LOW_Pos 0UL
+#define SDHC_CORE_ADMA_SA_LOW_R_ADMA_SA_LOW_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.ADMA_ID_LOW_R */
+#define SDHC_CORE_ADMA_ID_LOW_R_ADMA_ID_LOW_Pos 0UL
+#define SDHC_CORE_ADMA_ID_LOW_R_ADMA_ID_LOW_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.HOST_CNTRL_VERS_R */
+#define SDHC_CORE_HOST_CNTRL_VERS_R_SPEC_VERSION_NUM_Pos 0UL
+#define SDHC_CORE_HOST_CNTRL_VERS_R_SPEC_VERSION_NUM_Msk 0xFFUL
+#define SDHC_CORE_HOST_CNTRL_VERS_R_VENDOR_VERSION_NUM_Pos 8UL
+#define SDHC_CORE_HOST_CNTRL_VERS_R_VENDOR_VERSION_NUM_Msk 0xFF00UL
+/* SDHC_CORE.CQVER */
+#define SDHC_CORE_CQVER_EMMC_VER_SUFFIX_Pos 0UL
+#define SDHC_CORE_CQVER_EMMC_VER_SUFFIX_Msk 0xFUL
+#define SDHC_CORE_CQVER_EMMC_VER_MINOR_Pos 4UL
+#define SDHC_CORE_CQVER_EMMC_VER_MINOR_Msk 0xF0UL
+#define SDHC_CORE_CQVER_EMMC_VER_MAJOR_Pos 8UL
+#define SDHC_CORE_CQVER_EMMC_VER_MAJOR_Msk 0xF00UL
+/* SDHC_CORE.CQCAP */
+#define SDHC_CORE_CQCAP_ITCFVAL_Pos 0UL
+#define SDHC_CORE_CQCAP_ITCFVAL_Msk 0x3FFUL
+#define SDHC_CORE_CQCAP_ITCFMUL_Pos 12UL
+#define SDHC_CORE_CQCAP_ITCFMUL_Msk 0xF000UL
+#define SDHC_CORE_CQCAP_CRYPTO_SUPPORT_Pos 28UL
+#define SDHC_CORE_CQCAP_CRYPTO_SUPPORT_Msk 0x10000000UL
+/* SDHC_CORE.CQCFG */
+#define SDHC_CORE_CQCFG_CQ_EN_Pos 0UL
+#define SDHC_CORE_CQCFG_CQ_EN_Msk 0x1UL
+#define SDHC_CORE_CQCFG_CR_GENERAL_EN_Pos 1UL
+#define SDHC_CORE_CQCFG_CR_GENERAL_EN_Msk 0x2UL
+#define SDHC_CORE_CQCFG_TASK_DESC_SIZE_Pos 8UL
+#define SDHC_CORE_CQCFG_TASK_DESC_SIZE_Msk 0x100UL
+#define SDHC_CORE_CQCFG_DCMD_EN_Pos 12UL
+#define SDHC_CORE_CQCFG_DCMD_EN_Msk 0x1000UL
+/* SDHC_CORE.CQCTL */
+#define SDHC_CORE_CQCTL_HALT_Pos 0UL
+#define SDHC_CORE_CQCTL_HALT_Msk 0x1UL
+#define SDHC_CORE_CQCTL_CLR_ALL_TASKS_Pos 8UL
+#define SDHC_CORE_CQCTL_CLR_ALL_TASKS_Msk 0x100UL
+/* SDHC_CORE.CQIS */
+#define SDHC_CORE_CQIS_HAC_Pos 0UL
+#define SDHC_CORE_CQIS_HAC_Msk 0x1UL
+#define SDHC_CORE_CQIS_TCC_Pos 1UL
+#define SDHC_CORE_CQIS_TCC_Msk 0x2UL
+#define SDHC_CORE_CQIS_RED_Pos 2UL
+#define SDHC_CORE_CQIS_RED_Msk 0x4UL
+#define SDHC_CORE_CQIS_TCL_Pos 3UL
+#define SDHC_CORE_CQIS_TCL_Msk 0x8UL
+#define SDHC_CORE_CQIS_GCE_Pos 4UL
+#define SDHC_CORE_CQIS_GCE_Msk 0x10UL
+#define SDHC_CORE_CQIS_ICCE_Pos 5UL
+#define SDHC_CORE_CQIS_ICCE_Msk 0x20UL
+/* SDHC_CORE.CQISE */
+#define SDHC_CORE_CQISE_HAC_STE_Pos 0UL
+#define SDHC_CORE_CQISE_HAC_STE_Msk 0x1UL
+#define SDHC_CORE_CQISE_TCC_STE_Pos 1UL
+#define SDHC_CORE_CQISE_TCC_STE_Msk 0x2UL
+#define SDHC_CORE_CQISE_RED_STE_Pos 2UL
+#define SDHC_CORE_CQISE_RED_STE_Msk 0x4UL
+#define SDHC_CORE_CQISE_TCL_STE_Pos 3UL
+#define SDHC_CORE_CQISE_TCL_STE_Msk 0x8UL
+#define SDHC_CORE_CQISE_GCE_STE_Pos 4UL
+#define SDHC_CORE_CQISE_GCE_STE_Msk 0x10UL
+#define SDHC_CORE_CQISE_ICCE_STE_Pos 5UL
+#define SDHC_CORE_CQISE_ICCE_STE_Msk 0x20UL
+/* SDHC_CORE.CQISGE */
+#define SDHC_CORE_CQISGE_HAC_SGE_Pos 0UL
+#define SDHC_CORE_CQISGE_HAC_SGE_Msk 0x1UL
+#define SDHC_CORE_CQISGE_TCC_SGE_Pos 1UL
+#define SDHC_CORE_CQISGE_TCC_SGE_Msk 0x2UL
+#define SDHC_CORE_CQISGE_RED_SGE_Pos 2UL
+#define SDHC_CORE_CQISGE_RED_SGE_Msk 0x4UL
+#define SDHC_CORE_CQISGE_TCL_SGE_Pos 3UL
+#define SDHC_CORE_CQISGE_TCL_SGE_Msk 0x8UL
+#define SDHC_CORE_CQISGE_GCE_SGE_Pos 4UL
+#define SDHC_CORE_CQISGE_GCE_SGE_Msk 0x10UL
+#define SDHC_CORE_CQISGE_ICCE_SGE_Pos 5UL
+#define SDHC_CORE_CQISGE_ICCE_SGE_Msk 0x20UL
+/* SDHC_CORE.CQIC */
+#define SDHC_CORE_CQIC_TOUT_VAL_Pos 0UL
+#define SDHC_CORE_CQIC_TOUT_VAL_Msk 0x7FUL
+#define SDHC_CORE_CQIC_TOUT_VAL_WEN_Pos 7UL
+#define SDHC_CORE_CQIC_TOUT_VAL_WEN_Msk 0x80UL
+#define SDHC_CORE_CQIC_INTC_TH_Pos 8UL
+#define SDHC_CORE_CQIC_INTC_TH_Msk 0x1F00UL
+#define SDHC_CORE_CQIC_INTC_TH_WEN_Pos 15UL
+#define SDHC_CORE_CQIC_INTC_TH_WEN_Msk 0x8000UL
+#define SDHC_CORE_CQIC_INTC_RST_Pos 16UL
+#define SDHC_CORE_CQIC_INTC_RST_Msk 0x10000UL
+#define SDHC_CORE_CQIC_INTC_STAT_Pos 20UL
+#define SDHC_CORE_CQIC_INTC_STAT_Msk 0x100000UL
+#define SDHC_CORE_CQIC_INTC_EN_Pos 31UL
+#define SDHC_CORE_CQIC_INTC_EN_Msk 0x80000000UL
+/* SDHC_CORE.CQTDLBA */
+#define SDHC_CORE_CQTDLBA_TDLBA_Pos 0UL
+#define SDHC_CORE_CQTDLBA_TDLBA_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.CQTDBR */
+#define SDHC_CORE_CQTDBR_DBR_Pos 0UL
+#define SDHC_CORE_CQTDBR_DBR_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.CQTCN */
+#define SDHC_CORE_CQTCN_TCN_Pos 0UL
+#define SDHC_CORE_CQTCN_TCN_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.CQDQS */
+#define SDHC_CORE_CQDQS_DQS_Pos 0UL
+#define SDHC_CORE_CQDQS_DQS_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.CQDPT */
+#define SDHC_CORE_CQDPT_DPT_Pos 0UL
+#define SDHC_CORE_CQDPT_DPT_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.CQTCLR */
+#define SDHC_CORE_CQTCLR_TCLR_Pos 0UL
+#define SDHC_CORE_CQTCLR_TCLR_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.CQSSC1 */
+#define SDHC_CORE_CQSSC1_SQSCMD_IDLE_TMR_Pos 0UL
+#define SDHC_CORE_CQSSC1_SQSCMD_IDLE_TMR_Msk 0xFFFFUL
+#define SDHC_CORE_CQSSC1_SQSCMD_BLK_CNT_Pos 16UL
+#define SDHC_CORE_CQSSC1_SQSCMD_BLK_CNT_Msk 0xF0000UL
+/* SDHC_CORE.CQSSC2 */
+#define SDHC_CORE_CQSSC2_SQSCMD_RCA_Pos 0UL
+#define SDHC_CORE_CQSSC2_SQSCMD_RCA_Msk 0xFFFFUL
+/* SDHC_CORE.CQCRDCT */
+#define SDHC_CORE_CQCRDCT_DCMD_RESP_Pos 0UL
+#define SDHC_CORE_CQCRDCT_DCMD_RESP_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.CQRMEM */
+#define SDHC_CORE_CQRMEM_RESP_ERR_MASK_Pos 0UL
+#define SDHC_CORE_CQRMEM_RESP_ERR_MASK_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.CQTERRI */
+#define SDHC_CORE_CQTERRI_RESP_ERR_CMD_INDX_Pos 0UL
+#define SDHC_CORE_CQTERRI_RESP_ERR_CMD_INDX_Msk 0x3FUL
+#define SDHC_CORE_CQTERRI_RESP_ERR_TASKID_Pos 8UL
+#define SDHC_CORE_CQTERRI_RESP_ERR_TASKID_Msk 0x1F00UL
+#define SDHC_CORE_CQTERRI_RESP_ERR_FIELDS_VALID_Pos 15UL
+#define SDHC_CORE_CQTERRI_RESP_ERR_FIELDS_VALID_Msk 0x8000UL
+#define SDHC_CORE_CQTERRI_TRANS_ERR_CMD_INDX_Pos 16UL
+#define SDHC_CORE_CQTERRI_TRANS_ERR_CMD_INDX_Msk 0x3F0000UL
+#define SDHC_CORE_CQTERRI_TRANS_ERR_TASKID_Pos 24UL
+#define SDHC_CORE_CQTERRI_TRANS_ERR_TASKID_Msk 0x1F000000UL
+#define SDHC_CORE_CQTERRI_TRANS_ERR_FIELDS_VALID_Pos 31UL
+#define SDHC_CORE_CQTERRI_TRANS_ERR_FIELDS_VALID_Msk 0x80000000UL
+/* SDHC_CORE.CQCRI */
+#define SDHC_CORE_CQCRI_CMD_RESP_INDX_Pos 0UL
+#define SDHC_CORE_CQCRI_CMD_RESP_INDX_Msk 0x3FUL
+/* SDHC_CORE.CQCRA */
+#define SDHC_CORE_CQCRA_CMD_RESP_ARG_Pos 0UL
+#define SDHC_CORE_CQCRA_CMD_RESP_ARG_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.MSHC_VER_ID_R */
+#define SDHC_CORE_MSHC_VER_ID_R_MSHC_VER_ID_Pos 0UL
+#define SDHC_CORE_MSHC_VER_ID_R_MSHC_VER_ID_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.MSHC_VER_TYPE_R */
+#define SDHC_CORE_MSHC_VER_TYPE_R_MSHC_VER_TYPE_Pos 0UL
+#define SDHC_CORE_MSHC_VER_TYPE_R_MSHC_VER_TYPE_Msk 0xFFFFFFFFUL
+/* SDHC_CORE.MSHC_CTRL_R */
+#define SDHC_CORE_MSHC_CTRL_R_CMD_CONFLICT_CHECK_Pos 0UL
+#define SDHC_CORE_MSHC_CTRL_R_CMD_CONFLICT_CHECK_Msk 0x1UL
+#define SDHC_CORE_MSHC_CTRL_R_SW_CG_DIS_Pos 4UL
+#define SDHC_CORE_MSHC_CTRL_R_SW_CG_DIS_Msk 0x10UL
+/* SDHC_CORE.MBIU_CTRL_R */
+#define SDHC_CORE_MBIU_CTRL_R_UNDEFL_INCR_EN_Pos 0UL
+#define SDHC_CORE_MBIU_CTRL_R_UNDEFL_INCR_EN_Msk 0x1UL
+#define SDHC_CORE_MBIU_CTRL_R_BURST_INCR4_EN_Pos 1UL
+#define SDHC_CORE_MBIU_CTRL_R_BURST_INCR4_EN_Msk 0x2UL
+#define SDHC_CORE_MBIU_CTRL_R_BURST_INCR8_EN_Pos 2UL
+#define SDHC_CORE_MBIU_CTRL_R_BURST_INCR8_EN_Msk 0x4UL
+#define SDHC_CORE_MBIU_CTRL_R_BURST_INCR16_EN_Pos 3UL
+#define SDHC_CORE_MBIU_CTRL_R_BURST_INCR16_EN_Msk 0x8UL
+/* SDHC_CORE.EMMC_CTRL_R */
+#define SDHC_CORE_EMMC_CTRL_R_CARD_IS_EMMC_Pos 0UL
+#define SDHC_CORE_EMMC_CTRL_R_CARD_IS_EMMC_Msk 0x1UL
+#define SDHC_CORE_EMMC_CTRL_R_DISABLE_DATA_CRC_CHK_Pos 1UL
+#define SDHC_CORE_EMMC_CTRL_R_DISABLE_DATA_CRC_CHK_Msk 0x2UL
+#define SDHC_CORE_EMMC_CTRL_R_EMMC_RST_N_Pos 2UL
+#define SDHC_CORE_EMMC_CTRL_R_EMMC_RST_N_Msk 0x4UL
+#define SDHC_CORE_EMMC_CTRL_R_EMMC_RST_N_OE_Pos 3UL
+#define SDHC_CORE_EMMC_CTRL_R_EMMC_RST_N_OE_Msk 0x8UL
+#define SDHC_CORE_EMMC_CTRL_R_CQE_ALGO_SEL_Pos 9UL
+#define SDHC_CORE_EMMC_CTRL_R_CQE_ALGO_SEL_Msk 0x200UL
+#define SDHC_CORE_EMMC_CTRL_R_CQE_PREFETCH_DISABLE_Pos 10UL
+#define SDHC_CORE_EMMC_CTRL_R_CQE_PREFETCH_DISABLE_Msk 0x400UL
+/* SDHC_CORE.BOOT_CTRL_R */
+#define SDHC_CORE_BOOT_CTRL_R_MAN_BOOT_EN_Pos 0UL
+#define SDHC_CORE_BOOT_CTRL_R_MAN_BOOT_EN_Msk 0x1UL
+#define SDHC_CORE_BOOT_CTRL_R_VALIDATE_BOOT_Pos 7UL
+#define SDHC_CORE_BOOT_CTRL_R_VALIDATE_BOOT_Msk 0x80UL
+#define SDHC_CORE_BOOT_CTRL_R_BOOT_ACK_ENABLE_Pos 8UL
+#define SDHC_CORE_BOOT_CTRL_R_BOOT_ACK_ENABLE_Msk 0x100UL
+#define SDHC_CORE_BOOT_CTRL_R_BOOT_TOUT_CNT_Pos 12UL
+#define SDHC_CORE_BOOT_CTRL_R_BOOT_TOUT_CNT_Msk 0xF000UL
+/* SDHC_CORE.GP_IN_R */
+#define SDHC_CORE_GP_IN_R_GP_IN_Pos 0UL
+#define SDHC_CORE_GP_IN_R_GP_IN_Msk 0x1UL
+/* SDHC_CORE.GP_OUT_R */
+#define SDHC_CORE_GP_OUT_R_CARD_DETECT_EN_Pos 0UL
+#define SDHC_CORE_GP_OUT_R_CARD_DETECT_EN_Msk 0x1UL
+#define SDHC_CORE_GP_OUT_R_CARD_MECH_WRITE_PROT_EN_Pos 1UL
+#define SDHC_CORE_GP_OUT_R_CARD_MECH_WRITE_PROT_EN_Msk 0x2UL
+#define SDHC_CORE_GP_OUT_R_LED_CTRL_OE_Pos 2UL
+#define SDHC_CORE_GP_OUT_R_LED_CTRL_OE_Msk 0x4UL
+#define SDHC_CORE_GP_OUT_R_CARD_CLOCK_OE_Pos 3UL
+#define SDHC_CORE_GP_OUT_R_CARD_CLOCK_OE_Msk 0x8UL
+#define SDHC_CORE_GP_OUT_R_CARD_IF_PWR_EN_OE_Pos 4UL
+#define SDHC_CORE_GP_OUT_R_CARD_IF_PWR_EN_OE_Msk 0x10UL
+#define SDHC_CORE_GP_OUT_R_IO_VOLT_SEL_OE_Pos 5UL
+#define SDHC_CORE_GP_OUT_R_IO_VOLT_SEL_OE_Msk 0x20UL
+#define SDHC_CORE_GP_OUT_R_CARD_CLOCK_OUT_DLY_Pos 6UL
+#define SDHC_CORE_GP_OUT_R_CARD_CLOCK_OUT_DLY_Msk 0xC0UL
+#define SDHC_CORE_GP_OUT_R_CARD_CLOCK_IN_DLY_Pos 8UL
+#define SDHC_CORE_GP_OUT_R_CARD_CLOCK_IN_DLY_Msk 0x300UL
+
+
+#endif /* _CYIP_SDHC_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_sflash.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_sflash.h
new file mode 100644
index 0000000000..f824008671
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_sflash.h
@@ -0,0 +1,509 @@
+/***************************************************************************//**
+* \file cyip_sflash.h
+*
+* \brief
+* SFLASH IP definitions
+*
+* \note
+* Generator version: 1.5.0.1287
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_SFLASH_H_
+#define _CYIP_SFLASH_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SFLASH
+*******************************************************************************/
+
+#define SFLASH_SECTION_SIZE 0x00008000UL
+
+/**
+ * \brief FLASH Supervisory Region (SFLASH)
+ */
+typedef struct {
+ __IM uint8_t RESERVED;
+ __IOM uint8_t SI_REVISION_ID; /*!< 0x00000001 Indicates Silicon Revision ID of the device */
+ __IOM uint16_t SILICON_ID; /*!< 0x00000002 Indicates Silicon ID of the device */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint16_t FAMILY_ID; /*!< 0x0000000C Indicates Family ID of the device */
+ __IM uint16_t RESERVED2[3];
+ __IOM uint32_t CPUSS_WOUNDING; /*!< 0x00000014 CPUSS Wounding */
+ __IM uint32_t RESERVED3[378];
+ __IOM uint8_t DIE_LOT[3]; /*!< 0x00000600 Lot Number (3 bytes) */
+ __IOM uint8_t DIE_WAFER; /*!< 0x00000603 Wafer Number */
+ __IOM uint8_t DIE_X; /*!< 0x00000604 X Position on Wafer, CRI Pass/Fail Bin */
+ __IOM uint8_t DIE_Y; /*!< 0x00000605 Y Position on Wafer, CHI Pass/Fail Bin */
+ __IOM uint8_t DIE_SORT; /*!< 0x00000606 Sort1/2/3 Pass/Fail Bin */
+ __IOM uint8_t DIE_MINOR; /*!< 0x00000607 Minor Revision Number */
+ __IOM uint8_t DIE_DAY; /*!< 0x00000608 Day number */
+ __IOM uint8_t DIE_MONTH; /*!< 0x00000609 Month number */
+ __IOM uint8_t DIE_YEAR; /*!< 0x0000060A Year number */
+ __IM uint8_t RESERVED4[61];
+ __IOM uint16_t SAR_TEMP_MULTIPLIER; /*!< 0x00000648 SAR Temperature Sensor Multiplication Factor */
+ __IOM uint16_t SAR_TEMP_OFFSET; /*!< 0x0000064A SAR Temperature Sensor Offset */
+ __IM uint32_t RESERVED5[8];
+ __IOM uint32_t CSP_PANEL_ID; /*!< 0x0000066C CSP Panel Id to record panel ID of CSP die */
+ __IM uint32_t RESERVED6[52];
+ __IOM uint8_t LDO_0P9V_TRIM; /*!< 0x00000740 LDO_0P9V_TRIM */
+ __IOM uint8_t LDO_1P1V_TRIM; /*!< 0x00000741 LDO_1P1V_TRIM */
+ __IM uint16_t RESERVED7[95];
+ __IOM uint32_t BLE_DEVICE_ADDRESS[128]; /*!< 0x00000800 BLE_DEVICE_ADDRESS */
+ __IOM uint32_t USER_FREE_ROW1[128]; /*!< 0x00000A00 USER_FREE_ROW1 */
+ __IOM uint32_t USER_FREE_ROW2[128]; /*!< 0x00000C00 USER_FREE_ROW2 */
+ __IOM uint32_t USER_FREE_ROW3[128]; /*!< 0x00000E00 USER_FREE_ROW3 */
+ __IM uint32_t RESERVED8[302];
+ __IOM uint8_t DEVICE_UID[16]; /*!< 0x000014B8 Unique Identifier Number for each device */
+ __IOM uint8_t MASTER_KEY[16]; /*!< 0x000014C8 Master key to change other keys */
+ __IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ADDR[16]; /*!< 0x000014D8 Standard SMPU STRUCT Slave Address value */
+ __IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ATTR[16]; /*!< 0x00001518 Standard SMPU STRUCT Slave Attribute value */
+ __IOM uint32_t STANDARD_SMPU_STRUCT_MASTER_ATTR[16]; /*!< 0x00001558 Standard SMPU STRUCT Master Attribute value */
+ __IOM uint32_t STANDARD_MPU_STRUCT[16]; /*!< 0x00001598 Standard MPU STRUCT */
+ __IOM uint32_t STANDARD_PPU_STRUCT[16]; /*!< 0x000015D8 Standard PPU STRUCT */
+ __IM uint32_t RESERVED9[122];
+ __IOM uint16_t PILO_FREQ_STEP; /*!< 0x00001800 Resolution step for PILO at class in BCD format */
+ __IM uint16_t RESERVED10;
+ __IOM uint32_t CSDV2_CSD0_ADC_VREF0; /*!< 0x00001804 CSD 1p2 & 1p6 voltage levels for accuracy */
+ __IOM uint32_t CSDV2_CSD0_ADC_VREF1; /*!< 0x00001808 CSD 2p1 & 0p8 voltage levels for accuracy */
+ __IOM uint32_t CSDV2_CSD0_ADC_VREF2; /*!< 0x0000180C CSD calibration spare voltage level for accuracy */
+ __IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00001810 Wakeup delay */
+ __IM uint16_t RESERVED11;
+ __IOM uint16_t RADIO_LDO_TRIMS; /*!< 0x00001816 Radio LDO Trims */
+ __IOM uint32_t CPUSS_TRIM_ROM_CTL_ULP; /*!< 0x00001818 CPUSS TRIM ROM CTL ULP value */
+ __IOM uint32_t CPUSS_TRIM_RAM_CTL_ULP; /*!< 0x0000181C CPUSS TRIM RAM CTL ULP value */
+ __IOM uint32_t CPUSS_TRIM_ROM_CTL_LP; /*!< 0x00001820 CPUSS TRIM ROM CTL LP value */
+ __IOM uint32_t CPUSS_TRIM_RAM_CTL_LP; /*!< 0x00001824 CPUSS TRIM RAM CTL LP value */
+ __IM uint32_t RESERVED12[7];
+ __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_ULP; /*!< 0x00001844 CPUSS TRIM ROM CTL HALF ULP value */
+ __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_ULP; /*!< 0x00001848 CPUSS TRIM RAM CTL HALF ULP value */
+ __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_LP; /*!< 0x0000184C CPUSS TRIM ROM CTL HALF LP value */
+ __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_LP; /*!< 0x00001850 CPUSS TRIM RAM CTL HALF LP value */
+ __IM uint32_t RESERVED13[491];
+ __IOM uint32_t FLASH_BOOT_OBJECT_SIZE; /*!< 0x00002000 Flash Boot - Object Size */
+ __IOM uint32_t FLASH_BOOT_APP_ID; /*!< 0x00002004 Flash Boot - Application ID/Version */
+ __IOM uint32_t FLASH_BOOT_ATTRIBUTE; /*!< 0x00002008 N/A */
+ __IOM uint32_t FLASH_BOOT_N_CORES; /*!< 0x0000200C Flash Boot - Number of Cores(N) */
+ __IOM uint32_t FLASH_BOOT_VT_OFFSET; /*!< 0x00002010 Flash Boot - Core Vector Table offset */
+ __IOM uint32_t FLASH_BOOT_CORE_CPUID; /*!< 0x00002014 Flash Boot - Core CPU ID/Core Index */
+ __IM uint32_t RESERVED14[48];
+ __IOM uint8_t FLASH_BOOT_CODE[14632]; /*!< 0x000020D8 Flash Boot - Code and Data */
+ __IOM uint8_t PUBLIC_KEY[3072]; /*!< 0x00005A00 Public key for signature verification (max RSA key size 4096) */
+ __IOM uint32_t BOOT_PROT_SETTINGS[384]; /*!< 0x00006600 Boot protection settings (not present in PSOC6ABLE2) */
+ __IM uint32_t RESERVED15[768];
+ __IOM uint32_t TOC1_OBJECT_SIZE; /*!< 0x00007800 Object size in bytes for CRC calculation starting from offset
+ 0x00 */
+ __IOM uint32_t TOC1_MAGIC_NUMBER; /*!< 0x00007804 Magic number(0x01211219) */
+ __IOM uint32_t TOC1_FHASH_OBJECTS; /*!< 0x00007808 Number of objects starting from offset 0xC to be verified for
+ FACTORY_HASH */
+ __IOM uint32_t TOC1_GENERAL_TRIM_ADDR_UNUSED; /*!< 0x0000780C Unused (Address is Hardcoded in ROM) */
+ __IOM uint32_t TOC1_UNIQUE_ID_ADDR; /*!< 0x00007810 Address of Unique ID stored in SFLASH */
+ __IOM uint32_t TOC1_FB_OBJECT_ADDR; /*!< 0x00007814 Addresss of FLASH Boot(FB) object that include FLASH patch also */
+ __IOM uint32_t TOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007818 Unused (Address is Hardcoded in ROM) */
+ __IOM uint32_t TOC1_OBJECT_ADDR_UNUSED; /*!< 0x0000781C Unused (Address is Hardcoded in ROM) */
+ __IM uint32_t RESERVED16[119];
+ __IOM uint32_t TOC1_CRC_ADDR; /*!< 0x000079FC Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */
+ __IOM uint32_t RTOC1_OBJECT_SIZE; /*!< 0x00007A00 Redundant Object size in bytes for CRC calculation starting
+ from offset 0x00 */
+ __IOM uint32_t RTOC1_MAGIC_NUMBER; /*!< 0x00007A04 Redundant Magic number(0x01211219) */
+ __IOM uint32_t RTOC1_FHASH_OBJECTS; /*!< 0x00007A08 Redundant Number of objects starting from offset 0xC to be
+ verified for FACTORY_HASH */
+ __IOM uint32_t RTOC1_GENERAL_TRIM_ADDR_UNUSED; /*!< 0x00007A0C Redundant Unused (Address is Hardcoded in ROM) */
+ __IOM uint32_t RTOC1_UNIQUE_ID_ADDR; /*!< 0x00007A10 Redundant Address of Unique ID stored in SFLASH */
+ __IOM uint32_t RTOC1_FB_OBJECT_ADDR; /*!< 0x00007A14 Redundant Addresss of FLASH Boot(FB) object that include FLASH
+ patch also */
+ __IOM uint32_t RTOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007A18 Redundant Unused (Address is Hardcoded in ROM) */
+ __IOM uint32_t RTOC1_OBJECT_ADDR_UNUSED; /*!< 0x00007A1C Redundant Unused (Address is Hardcoded in ROM) */
+ __IM uint32_t RESERVED17[119];
+ __IOM uint32_t RTOC1_CRC_ADDR; /*!< 0x00007BFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2
+ bytes are 0 */
+ __IOM uint32_t TOC2_OBJECT_SIZE; /*!< 0x00007C00 Object size in bytes for CRC calculation starting from offset
+ 0x00 */
+ __IOM uint32_t TOC2_MAGIC_NUMBER; /*!< 0x00007C04 Magic number(0x01211220) */
+ __IOM uint32_t TOC2_KEY_BLOCK_ADDR; /*!< 0x00007C08 Address of Key Storage FLASH blocks */
+ __IOM uint32_t TOC2_SMIF_CFG_STRUCT_ADDR; /*!< 0x00007C0C Null terminated table of pointers representing the SMIF
+ configuration structure */
+ __IOM uint32_t TOC2_FIRST_USER_APP_ADDR; /*!< 0x00007C10 Address of First User Application Object */
+ __IOM uint32_t TOC2_FIRST_USER_APP_FORMAT; /*!< 0x00007C14 Format of First User Application Object. 0 - Basic, 1 - Cypress
+ standard & 2 - Simplified */
+ __IOM uint32_t TOC2_SECOND_USER_APP_ADDR; /*!< 0x00007C18 Address of Second User Application Object */
+ __IOM uint32_t TOC2_SECOND_USER_APP_FORMAT; /*!< 0x00007C1C Format of Second User Application Object. 0 - Basic, 1 -
+ Cypress standard & 2 - Simplified */
+ __IOM uint32_t TOC2_SHASH_OBJECTS; /*!< 0x00007C20 Number of additional objects(in addition to objects covered by
+ FACORY_CAMC) starting from offset 0x24 to be verified for
+ SECURE_HASH(SHASH) */
+ __IOM uint32_t TOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007C24 Address of signature verification key (0 if none).The object is
+ signature specific key. It is the public key in case of RSA */
+ __IM uint32_t RESERVED18[115];
+ __IOM uint32_t TOC2_REVISION; /*!< 0x00007DF4 Indicates TOC2 Revision. It is not used now. */
+ __IOM uint32_t TOC2_FLAGS; /*!< 0x00007DF8 TOC2_FLAGS */
+ __IOM uint32_t TOC2_CRC_ADDR; /*!< 0x00007DFC CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */
+ __IOM uint32_t RTOC2_OBJECT_SIZE; /*!< 0x00007E00 Redundant Object size in bytes for CRC calculation starting
+ from offset 0x00 */
+ __IOM uint32_t RTOC2_MAGIC_NUMBER; /*!< 0x00007E04 Redundant Magic number(0x01211220) */
+ __IOM uint32_t RTOC2_KEY_BLOCK_ADDR; /*!< 0x00007E08 Redundant Address of Key Storage FLASH blocks */
+ __IOM uint32_t RTOC2_SMIF_CFG_STRUCT_ADDR; /*!< 0x00007E0C Redundant Null terminated table of pointers representing the
+ SMIF configuration structure */
+ __IOM uint32_t RTOC2_FIRST_USER_APP_ADDR; /*!< 0x00007E10 Redundant Address of First User Application Object */
+ __IOM uint32_t RTOC2_FIRST_USER_APP_FORMAT; /*!< 0x00007E14 Redundant Format of First User Application Object. 0 - Basic, 1
+ - Cypress standard & 2 - Simplified */
+ __IOM uint32_t RTOC2_SECOND_USER_APP_ADDR; /*!< 0x00007E18 Redundant Address of Second User Application Object */
+ __IOM uint32_t RTOC2_SECOND_USER_APP_FORMAT; /*!< 0x00007E1C Redundant Format of Second User Application Object. 0 - Basic,
+ 1 - Cypress standard & 2 - Simplified */
+ __IOM uint32_t RTOC2_SHASH_OBJECTS; /*!< 0x00007E20 Redundant Number of additional objects(in addition to objects
+ covered by FACORY_CAMC) starting from offset 0x24 to be verified
+ for SECURE_HASH(SHASH) */
+ __IOM uint32_t RTOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007E24 Redundant Address of signature verification key (0 if none).The
+ object is signature specific key. It is the public key in case
+ of RSA */
+ __IM uint32_t RESERVED19[115];
+ __IOM uint32_t RTOC2_REVISION; /*!< 0x00007FF4 Indicates RTOC2 Revision. It is not used now. */
+ __IOM uint32_t RTOC2_FLAGS; /*!< 0x00007FF8 RTOC2_FLAGS */
+ __IOM uint32_t RTOC2_CRC_ADDR; /*!< 0x00007FFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2
+ bytes are 0 */
+} SFLASH_V1_Type; /*!< Size = 32768 (0x8000) */
+
+
+/* SFLASH.SI_REVISION_ID */
+#define SFLASH_SI_REVISION_ID_SI_REVISION_ID_Pos 0UL
+#define SFLASH_SI_REVISION_ID_SI_REVISION_ID_Msk 0xFFUL
+/* SFLASH.SILICON_ID */
+#define SFLASH_SILICON_ID_ID_Pos 0UL
+#define SFLASH_SILICON_ID_ID_Msk 0xFFFFUL
+/* SFLASH.FAMILY_ID */
+#define SFLASH_FAMILY_ID_FAMILY_ID_Pos 0UL
+#define SFLASH_FAMILY_ID_FAMILY_ID_Msk 0xFFFFUL
+/* SFLASH.CPUSS_WOUNDING */
+#define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Pos 0UL
+#define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Msk 0xFFFFFFFFUL
+/* SFLASH.DIE_LOT */
+#define SFLASH_DIE_LOT_LOT_Pos 0UL
+#define SFLASH_DIE_LOT_LOT_Msk 0xFFUL
+/* SFLASH.DIE_WAFER */
+#define SFLASH_DIE_WAFER_WAFER_Pos 0UL
+#define SFLASH_DIE_WAFER_WAFER_Msk 0xFFUL
+/* SFLASH.DIE_X */
+#define SFLASH_DIE_X_X_Pos 0UL
+#define SFLASH_DIE_X_X_Msk 0xFFUL
+/* SFLASH.DIE_Y */
+#define SFLASH_DIE_Y_Y_Pos 0UL
+#define SFLASH_DIE_Y_Y_Msk 0xFFUL
+/* SFLASH.DIE_SORT */
+#define SFLASH_DIE_SORT_S1_PASS_Pos 0UL
+#define SFLASH_DIE_SORT_S1_PASS_Msk 0x1UL
+#define SFLASH_DIE_SORT_S2_PASS_Pos 1UL
+#define SFLASH_DIE_SORT_S2_PASS_Msk 0x2UL
+#define SFLASH_DIE_SORT_S3_PASS_Pos 2UL
+#define SFLASH_DIE_SORT_S3_PASS_Msk 0x4UL
+#define SFLASH_DIE_SORT_CRI_PASS_Pos 3UL
+#define SFLASH_DIE_SORT_CRI_PASS_Msk 0x8UL
+#define SFLASH_DIE_SORT_CHI_PASS_Pos 4UL
+#define SFLASH_DIE_SORT_CHI_PASS_Msk 0x10UL
+#define SFLASH_DIE_SORT_ENG_PASS_Pos 5UL
+#define SFLASH_DIE_SORT_ENG_PASS_Msk 0x20UL
+/* SFLASH.DIE_MINOR */
+#define SFLASH_DIE_MINOR_MINOR_Pos 0UL
+#define SFLASH_DIE_MINOR_MINOR_Msk 0xFFUL
+/* SFLASH.DIE_DAY */
+#define SFLASH_DIE_DAY_MINOR_Pos 0UL
+#define SFLASH_DIE_DAY_MINOR_Msk 0xFFUL
+/* SFLASH.DIE_MONTH */
+#define SFLASH_DIE_MONTH_MINOR_Pos 0UL
+#define SFLASH_DIE_MONTH_MINOR_Msk 0xFFUL
+/* SFLASH.DIE_YEAR */
+#define SFLASH_DIE_YEAR_MINOR_Pos 0UL
+#define SFLASH_DIE_YEAR_MINOR_Msk 0xFFUL
+/* SFLASH.SAR_TEMP_MULTIPLIER */
+#define SFLASH_SAR_TEMP_MULTIPLIER_TEMP_MULTIPLIER_Pos 0UL
+#define SFLASH_SAR_TEMP_MULTIPLIER_TEMP_MULTIPLIER_Msk 0xFFFFUL
+/* SFLASH.SAR_TEMP_OFFSET */
+#define SFLASH_SAR_TEMP_OFFSET_TEMP_OFFSET_Pos 0UL
+#define SFLASH_SAR_TEMP_OFFSET_TEMP_OFFSET_Msk 0xFFFFUL
+/* SFLASH.CSP_PANEL_ID */
+#define SFLASH_CSP_PANEL_ID_DATA32_Pos 0UL
+#define SFLASH_CSP_PANEL_ID_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.LDO_0P9V_TRIM */
+#define SFLASH_LDO_0P9V_TRIM_DATA8_Pos 0UL
+#define SFLASH_LDO_0P9V_TRIM_DATA8_Msk 0xFFUL
+/* SFLASH.LDO_1P1V_TRIM */
+#define SFLASH_LDO_1P1V_TRIM_DATA8_Pos 0UL
+#define SFLASH_LDO_1P1V_TRIM_DATA8_Msk 0xFFUL
+/* SFLASH.BLE_DEVICE_ADDRESS */
+#define SFLASH_BLE_DEVICE_ADDRESS_ADDR_Pos 0UL
+#define SFLASH_BLE_DEVICE_ADDRESS_ADDR_Msk 0xFFFFFFFFUL
+/* SFLASH.USER_FREE_ROW1 */
+#define SFLASH_USER_FREE_ROW1_DATA32_Pos 0UL
+#define SFLASH_USER_FREE_ROW1_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.USER_FREE_ROW2 */
+#define SFLASH_USER_FREE_ROW2_DATA32_Pos 0UL
+#define SFLASH_USER_FREE_ROW2_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.USER_FREE_ROW3 */
+#define SFLASH_USER_FREE_ROW3_DATA32_Pos 0UL
+#define SFLASH_USER_FREE_ROW3_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.DEVICE_UID */
+#define SFLASH_DEVICE_UID_DATA8_Pos 0UL
+#define SFLASH_DEVICE_UID_DATA8_Msk 0xFFUL
+/* SFLASH.MASTER_KEY */
+#define SFLASH_MASTER_KEY_DATA8_Pos 0UL
+#define SFLASH_MASTER_KEY_DATA8_Msk 0xFFUL
+/* SFLASH.STANDARD_SMPU_STRUCT_SLAVE_ADDR */
+#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ADDR_DATA32_Pos 0UL
+#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.STANDARD_SMPU_STRUCT_SLAVE_ATTR */
+#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ATTR_DATA32_Pos 0UL
+#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ATTR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.STANDARD_SMPU_STRUCT_MASTER_ATTR */
+#define SFLASH_STANDARD_SMPU_STRUCT_MASTER_ATTR_DATA32_Pos 0UL
+#define SFLASH_STANDARD_SMPU_STRUCT_MASTER_ATTR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.STANDARD_MPU_STRUCT */
+#define SFLASH_STANDARD_MPU_STRUCT_DATA32_Pos 0UL
+#define SFLASH_STANDARD_MPU_STRUCT_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.STANDARD_PPU_STRUCT */
+#define SFLASH_STANDARD_PPU_STRUCT_DATA32_Pos 0UL
+#define SFLASH_STANDARD_PPU_STRUCT_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.PILO_FREQ_STEP */
+#define SFLASH_PILO_FREQ_STEP_STEP_Pos 0UL
+#define SFLASH_PILO_FREQ_STEP_STEP_Msk 0xFFFFUL
+/* SFLASH.CSDV2_CSD0_ADC_VREF0 */
+#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P2_Pos 0UL
+#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P2_Msk 0xFFFFUL
+#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P6_Pos 16UL
+#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P6_Msk 0xFFFF0000UL
+/* SFLASH.CSDV2_CSD0_ADC_VREF1 */
+#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_2P1_Pos 0UL
+#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_2P1_Msk 0xFFFFUL
+#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_0P8_Pos 16UL
+#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_0P8_Msk 0xFFFF0000UL
+/* SFLASH.CSDV2_CSD0_ADC_VREF2 */
+#define SFLASH_CSDV2_CSD0_ADC_VREF2_VREF_HI_LEVELS_2P6_Pos 0UL
+#define SFLASH_CSDV2_CSD0_ADC_VREF2_VREF_HI_LEVELS_2P6_Msk 0xFFFFUL
+/* SFLASH.PWR_TRIM_WAKE_CTL */
+#define SFLASH_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Pos 0UL
+#define SFLASH_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Msk 0xFFUL
+/* SFLASH.RADIO_LDO_TRIMS */
+#define SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Pos 0UL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Msk 0xFUL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Pos 4UL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Msk 0x30UL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_IF_Pos 6UL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_IF_Msk 0xC0UL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Pos 8UL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Msk 0x300UL
+/* SFLASH.CPUSS_TRIM_ROM_CTL_ULP */
+#define SFLASH_CPUSS_TRIM_ROM_CTL_ULP_DATA32_Pos 0UL
+#define SFLASH_CPUSS_TRIM_ROM_CTL_ULP_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.CPUSS_TRIM_RAM_CTL_ULP */
+#define SFLASH_CPUSS_TRIM_RAM_CTL_ULP_DATA32_Pos 0UL
+#define SFLASH_CPUSS_TRIM_RAM_CTL_ULP_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.CPUSS_TRIM_ROM_CTL_LP */
+#define SFLASH_CPUSS_TRIM_ROM_CTL_LP_DATA32_Pos 0UL
+#define SFLASH_CPUSS_TRIM_ROM_CTL_LP_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.CPUSS_TRIM_RAM_CTL_LP */
+#define SFLASH_CPUSS_TRIM_RAM_CTL_LP_DATA32_Pos 0UL
+#define SFLASH_CPUSS_TRIM_RAM_CTL_LP_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.CPUSS_TRIM_ROM_CTL_HALF_ULP */
+#define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP_DATA32_Pos 0UL
+#define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.CPUSS_TRIM_RAM_CTL_HALF_ULP */
+#define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP_DATA32_Pos 0UL
+#define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.CPUSS_TRIM_ROM_CTL_HALF_LP */
+#define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP_DATA32_Pos 0UL
+#define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.CPUSS_TRIM_RAM_CTL_HALF_LP */
+#define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP_DATA32_Pos 0UL
+#define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.FLASH_BOOT_OBJECT_SIZE */
+#define SFLASH_FLASH_BOOT_OBJECT_SIZE_DATA32_Pos 0UL
+#define SFLASH_FLASH_BOOT_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.FLASH_BOOT_APP_ID */
+#define SFLASH_FLASH_BOOT_APP_ID_APP_ID_Pos 0UL
+#define SFLASH_FLASH_BOOT_APP_ID_APP_ID_Msk 0xFFFFUL
+#define SFLASH_FLASH_BOOT_APP_ID_MINOR_VERSION_Pos 16UL
+#define SFLASH_FLASH_BOOT_APP_ID_MINOR_VERSION_Msk 0xFF0000UL
+#define SFLASH_FLASH_BOOT_APP_ID_MAJOR_VERSION_Pos 24UL
+#define SFLASH_FLASH_BOOT_APP_ID_MAJOR_VERSION_Msk 0xF000000UL
+/* SFLASH.FLASH_BOOT_ATTRIBUTE */
+#define SFLASH_FLASH_BOOT_ATTRIBUTE_DATA32_Pos 0UL
+#define SFLASH_FLASH_BOOT_ATTRIBUTE_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.FLASH_BOOT_N_CORES */
+#define SFLASH_FLASH_BOOT_N_CORES_DATA32_Pos 0UL
+#define SFLASH_FLASH_BOOT_N_CORES_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.FLASH_BOOT_VT_OFFSET */
+#define SFLASH_FLASH_BOOT_VT_OFFSET_DATA32_Pos 0UL
+#define SFLASH_FLASH_BOOT_VT_OFFSET_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.FLASH_BOOT_CORE_CPUID */
+#define SFLASH_FLASH_BOOT_CORE_CPUID_DATA32_Pos 0UL
+#define SFLASH_FLASH_BOOT_CORE_CPUID_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.FLASH_BOOT_CODE */
+#define SFLASH_FLASH_BOOT_CODE_DATA_Pos 0UL
+#define SFLASH_FLASH_BOOT_CODE_DATA_Msk 0xFFUL
+/* SFLASH.PUBLIC_KEY */
+#define SFLASH_PUBLIC_KEY_DATA_Pos 0UL
+#define SFLASH_PUBLIC_KEY_DATA_Msk 0xFFUL
+/* SFLASH.BOOT_PROT_SETTINGS */
+#define SFLASH_BOOT_PROT_SETTINGS_DATA32_Pos 0UL
+#define SFLASH_BOOT_PROT_SETTINGS_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_OBJECT_SIZE */
+#define SFLASH_TOC1_OBJECT_SIZE_DATA32_Pos 0UL
+#define SFLASH_TOC1_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_MAGIC_NUMBER */
+#define SFLASH_TOC1_MAGIC_NUMBER_DATA32_Pos 0UL
+#define SFLASH_TOC1_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_FHASH_OBJECTS */
+#define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Pos 0UL
+#define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_GENERAL_TRIM_ADDR_UNUSED */
+#define SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Pos 0UL
+#define SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_UNIQUE_ID_ADDR */
+#define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_FB_OBJECT_ADDR */
+#define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_SYSCALL_TABLE_ADDR_UNUSED */
+#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Pos 0UL
+#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_OBJECT_ADDR_UNUSED */
+#define SFLASH_TOC1_OBJECT_ADDR_UNUSED_DATA32_Pos 0UL
+#define SFLASH_TOC1_OBJECT_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_CRC_ADDR */
+#define SFLASH_TOC1_CRC_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC1_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_OBJECT_SIZE */
+#define SFLASH_RTOC1_OBJECT_SIZE_DATA32_Pos 0UL
+#define SFLASH_RTOC1_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_MAGIC_NUMBER */
+#define SFLASH_RTOC1_MAGIC_NUMBER_DATA32_Pos 0UL
+#define SFLASH_RTOC1_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_FHASH_OBJECTS */
+#define SFLASH_RTOC1_FHASH_OBJECTS_DATA32_Pos 0UL
+#define SFLASH_RTOC1_FHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_GENERAL_TRIM_ADDR_UNUSED */
+#define SFLASH_RTOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Pos 0UL
+#define SFLASH_RTOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_UNIQUE_ID_ADDR */
+#define SFLASH_RTOC1_UNIQUE_ID_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC1_UNIQUE_ID_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_FB_OBJECT_ADDR */
+#define SFLASH_RTOC1_FB_OBJECT_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC1_FB_OBJECT_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_SYSCALL_TABLE_ADDR_UNUSED */
+#define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Pos 0UL
+#define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_OBJECT_ADDR_UNUSED */
+#define SFLASH_RTOC1_OBJECT_ADDR_UNUSED_DATA32_Pos 0UL
+#define SFLASH_RTOC1_OBJECT_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_CRC_ADDR */
+#define SFLASH_RTOC1_CRC_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC1_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_OBJECT_SIZE */
+#define SFLASH_TOC2_OBJECT_SIZE_DATA32_Pos 0UL
+#define SFLASH_TOC2_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_MAGIC_NUMBER */
+#define SFLASH_TOC2_MAGIC_NUMBER_DATA32_Pos 0UL
+#define SFLASH_TOC2_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_KEY_BLOCK_ADDR */
+#define SFLASH_TOC2_KEY_BLOCK_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC2_KEY_BLOCK_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_SMIF_CFG_STRUCT_ADDR */
+#define SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_FIRST_USER_APP_ADDR */
+#define SFLASH_TOC2_FIRST_USER_APP_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC2_FIRST_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_FIRST_USER_APP_FORMAT */
+#define SFLASH_TOC2_FIRST_USER_APP_FORMAT_DATA32_Pos 0UL
+#define SFLASH_TOC2_FIRST_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_SECOND_USER_APP_ADDR */
+#define SFLASH_TOC2_SECOND_USER_APP_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC2_SECOND_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_SECOND_USER_APP_FORMAT */
+#define SFLASH_TOC2_SECOND_USER_APP_FORMAT_DATA32_Pos 0UL
+#define SFLASH_TOC2_SECOND_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_SHASH_OBJECTS */
+#define SFLASH_TOC2_SHASH_OBJECTS_DATA32_Pos 0UL
+#define SFLASH_TOC2_SHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_SIGNATURE_VERIF_KEY */
+#define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Pos 0UL
+#define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_REVISION */
+#define SFLASH_TOC2_REVISION_DATA32_Pos 0UL
+#define SFLASH_TOC2_REVISION_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_FLAGS */
+#define SFLASH_TOC2_FLAGS_CLOCK_CONFIG_Pos 0UL
+#define SFLASH_TOC2_FLAGS_CLOCK_CONFIG_Msk 0x3UL
+#define SFLASH_TOC2_FLAGS_LISTEN_WINDOW_Pos 2UL
+#define SFLASH_TOC2_FLAGS_LISTEN_WINDOW_Msk 0x1CUL
+#define SFLASH_TOC2_FLAGS_SWJ_PINS_CTL_Pos 5UL
+#define SFLASH_TOC2_FLAGS_SWJ_PINS_CTL_Msk 0x60UL
+#define SFLASH_TOC2_FLAGS_APP_AUTH_CTL_Pos 7UL
+#define SFLASH_TOC2_FLAGS_APP_AUTH_CTL_Msk 0x180UL
+#define SFLASH_TOC2_FLAGS_FB_BOOTLOADER_CTL_Pos 9UL
+#define SFLASH_TOC2_FLAGS_FB_BOOTLOADER_CTL_Msk 0x600UL
+/* SFLASH.TOC2_CRC_ADDR */
+#define SFLASH_TOC2_CRC_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC2_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_OBJECT_SIZE */
+#define SFLASH_RTOC2_OBJECT_SIZE_DATA32_Pos 0UL
+#define SFLASH_RTOC2_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_MAGIC_NUMBER */
+#define SFLASH_RTOC2_MAGIC_NUMBER_DATA32_Pos 0UL
+#define SFLASH_RTOC2_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_KEY_BLOCK_ADDR */
+#define SFLASH_RTOC2_KEY_BLOCK_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC2_KEY_BLOCK_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_SMIF_CFG_STRUCT_ADDR */
+#define SFLASH_RTOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_FIRST_USER_APP_ADDR */
+#define SFLASH_RTOC2_FIRST_USER_APP_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC2_FIRST_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_FIRST_USER_APP_FORMAT */
+#define SFLASH_RTOC2_FIRST_USER_APP_FORMAT_DATA32_Pos 0UL
+#define SFLASH_RTOC2_FIRST_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_SECOND_USER_APP_ADDR */
+#define SFLASH_RTOC2_SECOND_USER_APP_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC2_SECOND_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_SECOND_USER_APP_FORMAT */
+#define SFLASH_RTOC2_SECOND_USER_APP_FORMAT_DATA32_Pos 0UL
+#define SFLASH_RTOC2_SECOND_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_SHASH_OBJECTS */
+#define SFLASH_RTOC2_SHASH_OBJECTS_DATA32_Pos 0UL
+#define SFLASH_RTOC2_SHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_SIGNATURE_VERIF_KEY */
+#define SFLASH_RTOC2_SIGNATURE_VERIF_KEY_DATA32_Pos 0UL
+#define SFLASH_RTOC2_SIGNATURE_VERIF_KEY_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_REVISION */
+#define SFLASH_RTOC2_REVISION_DATA32_Pos 0UL
+#define SFLASH_RTOC2_REVISION_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_FLAGS */
+#define SFLASH_RTOC2_FLAGS_DATA32_Pos 0UL
+#define SFLASH_RTOC2_FLAGS_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_CRC_ADDR */
+#define SFLASH_RTOC2_CRC_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC2_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_SFLASH_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_smartio.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_smartio.h
new file mode 100644
index 0000000000..a3fb95ab98
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_smartio.h
@@ -0,0 +1,118 @@
+/***************************************************************************//**
+* \file cyip_smartio.h
+*
+* \brief
+* SMARTIO IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_SMARTIO_H_
+#define _CYIP_SMARTIO_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SMARTIO
+*******************************************************************************/
+
+#define SMARTIO_PRT_SECTION_SIZE 0x00000100UL
+#define SMARTIO_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Programmable IO port registers (SMARTIO_PRT)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control register */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t SYNC_CTL; /*!< 0x00000010 Synchronization control register */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t LUT_SEL[8]; /*!< 0x00000020 LUT component input selection */
+ __IOM uint32_t LUT_CTL[8]; /*!< 0x00000040 LUT component control register */
+ __IM uint32_t RESERVED2[24];
+ __IOM uint32_t DU_SEL; /*!< 0x000000C0 Data unit component input selection */
+ __IOM uint32_t DU_CTL; /*!< 0x000000C4 Data unit component control register */
+ __IM uint32_t RESERVED3[10];
+ __IOM uint32_t DATA; /*!< 0x000000F0 Data register */
+ __IM uint32_t RESERVED4[3];
+} SMARTIO_PRT_V1_Type; /*!< Size = 256 (0x100) */
+
+/**
+ * \brief Programmable IO configuration (SMARTIO)
+ */
+typedef struct {
+ SMARTIO_PRT_V1_Type PRT[128]; /*!< 0x00000000 Programmable IO port registers */
+} SMARTIO_V1_Type; /*!< Size = 32768 (0x8000) */
+
+
+/* SMARTIO_PRT.CTL */
+#define SMARTIO_PRT_CTL_BYPASS_Pos 0UL
+#define SMARTIO_PRT_CTL_BYPASS_Msk 0xFFUL
+#define SMARTIO_PRT_CTL_CLOCK_SRC_Pos 8UL
+#define SMARTIO_PRT_CTL_CLOCK_SRC_Msk 0x1F00UL
+#define SMARTIO_PRT_CTL_HLD_OVR_Pos 24UL
+#define SMARTIO_PRT_CTL_HLD_OVR_Msk 0x1000000UL
+#define SMARTIO_PRT_CTL_PIPELINE_EN_Pos 25UL
+#define SMARTIO_PRT_CTL_PIPELINE_EN_Msk 0x2000000UL
+#define SMARTIO_PRT_CTL_ENABLED_Pos 31UL
+#define SMARTIO_PRT_CTL_ENABLED_Msk 0x80000000UL
+/* SMARTIO_PRT.SYNC_CTL */
+#define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Pos 0UL
+#define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Msk 0xFFUL
+#define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Pos 8UL
+#define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Msk 0xFF00UL
+/* SMARTIO_PRT.LUT_SEL */
+#define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Pos 0UL
+#define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Msk 0xFUL
+#define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Pos 8UL
+#define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Msk 0xF00UL
+#define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Pos 16UL
+#define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Msk 0xF0000UL
+/* SMARTIO_PRT.LUT_CTL */
+#define SMARTIO_PRT_LUT_CTL_LUT_Pos 0UL
+#define SMARTIO_PRT_LUT_CTL_LUT_Msk 0xFFUL
+#define SMARTIO_PRT_LUT_CTL_LUT_OPC_Pos 8UL
+#define SMARTIO_PRT_LUT_CTL_LUT_OPC_Msk 0x300UL
+/* SMARTIO_PRT.DU_SEL */
+#define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Pos 0UL
+#define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Msk 0xFUL
+#define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Pos 8UL
+#define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Msk 0xF00UL
+#define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Pos 16UL
+#define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Msk 0xF0000UL
+#define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Pos 24UL
+#define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Msk 0x3000000UL
+#define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Pos 28UL
+#define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Msk 0x30000000UL
+/* SMARTIO_PRT.DU_CTL */
+#define SMARTIO_PRT_DU_CTL_DU_SIZE_Pos 0UL
+#define SMARTIO_PRT_DU_CTL_DU_SIZE_Msk 0x7UL
+#define SMARTIO_PRT_DU_CTL_DU_OPC_Pos 8UL
+#define SMARTIO_PRT_DU_CTL_DU_OPC_Msk 0xF00UL
+/* SMARTIO_PRT.DATA */
+#define SMARTIO_PRT_DATA_DATA_Pos 0UL
+#define SMARTIO_PRT_DATA_DATA_Msk 0xFFUL
+
+
+#endif /* _CYIP_SMARTIO_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_smartio_v2.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_smartio_v2.h
new file mode 100644
index 0000000000..a4d5f4be3d
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_smartio_v2.h
@@ -0,0 +1,118 @@
+/***************************************************************************//**
+* \file cyip_smartio_v2.h
+*
+* \brief
+* SMARTIO IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_SMARTIO_V2_H_
+#define _CYIP_SMARTIO_V2_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SMARTIO
+*******************************************************************************/
+
+#define SMARTIO_PRT_V2_SECTION_SIZE 0x00000100UL
+#define SMARTIO_V2_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Programmable IO port registers (SMARTIO_PRT)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control register */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t SYNC_CTL; /*!< 0x00000010 Synchronization control register */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t LUT_SEL[8]; /*!< 0x00000020 LUT component input selection */
+ __IOM uint32_t LUT_CTL[8]; /*!< 0x00000040 LUT component control register */
+ __IM uint32_t RESERVED2[24];
+ __IOM uint32_t DU_SEL; /*!< 0x000000C0 Data unit component input selection */
+ __IOM uint32_t DU_CTL; /*!< 0x000000C4 Data unit component control register */
+ __IM uint32_t RESERVED3[10];
+ __IOM uint32_t DATA; /*!< 0x000000F0 Data register */
+ __IM uint32_t RESERVED4[3];
+} SMARTIO_PRT_V2_Type; /*!< Size = 256 (0x100) */
+
+/**
+ * \brief Programmable IO configuration (SMARTIO)
+ */
+typedef struct {
+ SMARTIO_PRT_V2_Type PRT[128]; /*!< 0x00000000 Programmable IO port registers */
+} SMARTIO_V2_Type; /*!< Size = 32768 (0x8000) */
+
+
+/* SMARTIO_PRT.CTL */
+#define SMARTIO_PRT_V2_CTL_BYPASS_Pos 0UL
+#define SMARTIO_PRT_V2_CTL_BYPASS_Msk 0xFFUL
+#define SMARTIO_PRT_V2_CTL_CLOCK_SRC_Pos 8UL
+#define SMARTIO_PRT_V2_CTL_CLOCK_SRC_Msk 0x1F00UL
+#define SMARTIO_PRT_V2_CTL_HLD_OVR_Pos 24UL
+#define SMARTIO_PRT_V2_CTL_HLD_OVR_Msk 0x1000000UL
+#define SMARTIO_PRT_V2_CTL_PIPELINE_EN_Pos 25UL
+#define SMARTIO_PRT_V2_CTL_PIPELINE_EN_Msk 0x2000000UL
+#define SMARTIO_PRT_V2_CTL_ENABLED_Pos 31UL
+#define SMARTIO_PRT_V2_CTL_ENABLED_Msk 0x80000000UL
+/* SMARTIO_PRT.SYNC_CTL */
+#define SMARTIO_PRT_V2_SYNC_CTL_IO_SYNC_EN_Pos 0UL
+#define SMARTIO_PRT_V2_SYNC_CTL_IO_SYNC_EN_Msk 0xFFUL
+#define SMARTIO_PRT_V2_SYNC_CTL_CHIP_SYNC_EN_Pos 8UL
+#define SMARTIO_PRT_V2_SYNC_CTL_CHIP_SYNC_EN_Msk 0xFF00UL
+/* SMARTIO_PRT.LUT_SEL */
+#define SMARTIO_PRT_V2_LUT_SEL_LUT_TR0_SEL_Pos 0UL
+#define SMARTIO_PRT_V2_LUT_SEL_LUT_TR0_SEL_Msk 0xFUL
+#define SMARTIO_PRT_V2_LUT_SEL_LUT_TR1_SEL_Pos 8UL
+#define SMARTIO_PRT_V2_LUT_SEL_LUT_TR1_SEL_Msk 0xF00UL
+#define SMARTIO_PRT_V2_LUT_SEL_LUT_TR2_SEL_Pos 16UL
+#define SMARTIO_PRT_V2_LUT_SEL_LUT_TR2_SEL_Msk 0xF0000UL
+/* SMARTIO_PRT.LUT_CTL */
+#define SMARTIO_PRT_V2_LUT_CTL_LUT_Pos 0UL
+#define SMARTIO_PRT_V2_LUT_CTL_LUT_Msk 0xFFUL
+#define SMARTIO_PRT_V2_LUT_CTL_LUT_OPC_Pos 8UL
+#define SMARTIO_PRT_V2_LUT_CTL_LUT_OPC_Msk 0x300UL
+/* SMARTIO_PRT.DU_SEL */
+#define SMARTIO_PRT_V2_DU_SEL_DU_TR0_SEL_Pos 0UL
+#define SMARTIO_PRT_V2_DU_SEL_DU_TR0_SEL_Msk 0xFUL
+#define SMARTIO_PRT_V2_DU_SEL_DU_TR1_SEL_Pos 8UL
+#define SMARTIO_PRT_V2_DU_SEL_DU_TR1_SEL_Msk 0xF00UL
+#define SMARTIO_PRT_V2_DU_SEL_DU_TR2_SEL_Pos 16UL
+#define SMARTIO_PRT_V2_DU_SEL_DU_TR2_SEL_Msk 0xF0000UL
+#define SMARTIO_PRT_V2_DU_SEL_DU_DATA0_SEL_Pos 24UL
+#define SMARTIO_PRT_V2_DU_SEL_DU_DATA0_SEL_Msk 0x3000000UL
+#define SMARTIO_PRT_V2_DU_SEL_DU_DATA1_SEL_Pos 28UL
+#define SMARTIO_PRT_V2_DU_SEL_DU_DATA1_SEL_Msk 0x30000000UL
+/* SMARTIO_PRT.DU_CTL */
+#define SMARTIO_PRT_V2_DU_CTL_DU_SIZE_Pos 0UL
+#define SMARTIO_PRT_V2_DU_CTL_DU_SIZE_Msk 0x7UL
+#define SMARTIO_PRT_V2_DU_CTL_DU_OPC_Pos 8UL
+#define SMARTIO_PRT_V2_DU_CTL_DU_OPC_Msk 0xF00UL
+/* SMARTIO_PRT.DATA */
+#define SMARTIO_PRT_V2_DATA_DATA_Pos 0UL
+#define SMARTIO_PRT_V2_DATA_DATA_Msk 0xFFUL
+
+
+#endif /* _CYIP_SMARTIO_V2_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_smif.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_smif.h
new file mode 100644
index 0000000000..ebe1700ce1
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_smif.h
@@ -0,0 +1,387 @@
+/***************************************************************************//**
+* \file cyip_smif.h
+*
+* \brief
+* SMIF IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_SMIF_H_
+#define _CYIP_SMIF_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SMIF
+*******************************************************************************/
+
+#define SMIF_DEVICE_SECTION_SIZE 0x00000080UL
+#define SMIF_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Device (only used in XIP mode) (SMIF_DEVICE)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t ADDR; /*!< 0x00000008 Device region base address */
+ __IOM uint32_t MASK; /*!< 0x0000000C Device region mask */
+ __IM uint32_t RESERVED1[4];
+ __IOM uint32_t ADDR_CTL; /*!< 0x00000020 Address control */
+ __IM uint32_t RESERVED2[7];
+ __IOM uint32_t RD_CMD_CTL; /*!< 0x00000040 Read command control */
+ __IOM uint32_t RD_ADDR_CTL; /*!< 0x00000044 Read address control */
+ __IOM uint32_t RD_MODE_CTL; /*!< 0x00000048 Read mode control */
+ __IOM uint32_t RD_DUMMY_CTL; /*!< 0x0000004C Read dummy control */
+ __IOM uint32_t RD_DATA_CTL; /*!< 0x00000050 Read data control */
+ __IM uint32_t RESERVED3[3];
+ __IOM uint32_t WR_CMD_CTL; /*!< 0x00000060 Write command control */
+ __IOM uint32_t WR_ADDR_CTL; /*!< 0x00000064 Write address control */
+ __IOM uint32_t WR_MODE_CTL; /*!< 0x00000068 Write mode control */
+ __IOM uint32_t WR_DUMMY_CTL; /*!< 0x0000006C Write dummy control */
+ __IOM uint32_t WR_DATA_CTL; /*!< 0x00000070 Write data control */
+ __IM uint32_t RESERVED4[3];
+} SMIF_DEVICE_V1_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * \brief Serial Memory Interface (SMIF)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t STATUS; /*!< 0x00000004 Status */
+ __IM uint32_t RESERVED[15];
+ __IM uint32_t TX_CMD_FIFO_STATUS; /*!< 0x00000044 Transmitter command FIFO status */
+ __IM uint32_t RESERVED1[2];
+ __OM uint32_t TX_CMD_FIFO_WR; /*!< 0x00000050 Transmitter command FIFO write */
+ __IM uint32_t RESERVED2[11];
+ __IOM uint32_t TX_DATA_FIFO_CTL; /*!< 0x00000080 Transmitter data FIFO control */
+ __IM uint32_t TX_DATA_FIFO_STATUS; /*!< 0x00000084 Transmitter data FIFO status */
+ __IM uint32_t RESERVED3[2];
+ __OM uint32_t TX_DATA_FIFO_WR1; /*!< 0x00000090 Transmitter data FIFO write */
+ __OM uint32_t TX_DATA_FIFO_WR2; /*!< 0x00000094 Transmitter data FIFO write */
+ __OM uint32_t TX_DATA_FIFO_WR4; /*!< 0x00000098 Transmitter data FIFO write */
+ __IM uint32_t RESERVED4[9];
+ __IOM uint32_t RX_DATA_FIFO_CTL; /*!< 0x000000C0 Receiver data FIFO control */
+ __IM uint32_t RX_DATA_FIFO_STATUS; /*!< 0x000000C4 Receiver data FIFO status */
+ __IM uint32_t RESERVED5[2];
+ __IM uint32_t RX_DATA_FIFO_RD1; /*!< 0x000000D0 Receiver data FIFO read */
+ __IM uint32_t RX_DATA_FIFO_RD2; /*!< 0x000000D4 Receiver data FIFO read */
+ __IM uint32_t RX_DATA_FIFO_RD4; /*!< 0x000000D8 Receiver data FIFO read */
+ __IM uint32_t RESERVED6;
+ __IM uint32_t RX_DATA_FIFO_RD1_SILENT; /*!< 0x000000E0 Receiver data FIFO silent read */
+ __IM uint32_t RESERVED7[7];
+ __IOM uint32_t SLOW_CA_CTL; /*!< 0x00000100 Slow cache control */
+ __IM uint32_t RESERVED8;
+ __IOM uint32_t SLOW_CA_CMD; /*!< 0x00000108 Slow cache command */
+ __IM uint32_t RESERVED9[29];
+ __IOM uint32_t FAST_CA_CTL; /*!< 0x00000180 Fast cache control */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t FAST_CA_CMD; /*!< 0x00000188 Fast cache command */
+ __IM uint32_t RESERVED11[29];
+ __IOM uint32_t CRYPTO_CMD; /*!< 0x00000200 Cryptography Command */
+ __IM uint32_t RESERVED12[7];
+ __IOM uint32_t CRYPTO_INPUT0; /*!< 0x00000220 Cryptography input 0 */
+ __IOM uint32_t CRYPTO_INPUT1; /*!< 0x00000224 Cryptography input 1 */
+ __IOM uint32_t CRYPTO_INPUT2; /*!< 0x00000228 Cryptography input 2 */
+ __IOM uint32_t CRYPTO_INPUT3; /*!< 0x0000022C Cryptography input 3 */
+ __IM uint32_t RESERVED13[4];
+ __OM uint32_t CRYPTO_KEY0; /*!< 0x00000240 Cryptography key 0 */
+ __OM uint32_t CRYPTO_KEY1; /*!< 0x00000244 Cryptography key 1 */
+ __OM uint32_t CRYPTO_KEY2; /*!< 0x00000248 Cryptography key 2 */
+ __OM uint32_t CRYPTO_KEY3; /*!< 0x0000024C Cryptography key 3 */
+ __IM uint32_t RESERVED14[4];
+ __IOM uint32_t CRYPTO_OUTPUT0; /*!< 0x00000260 Cryptography output 0 */
+ __IOM uint32_t CRYPTO_OUTPUT1; /*!< 0x00000264 Cryptography output 1 */
+ __IOM uint32_t CRYPTO_OUTPUT2; /*!< 0x00000268 Cryptography output 2 */
+ __IOM uint32_t CRYPTO_OUTPUT3; /*!< 0x0000026C Cryptography output 3 */
+ __IM uint32_t RESERVED15[340];
+ __IOM uint32_t INTR; /*!< 0x000007C0 Interrupt register */
+ __IOM uint32_t INTR_SET; /*!< 0x000007C4 Interrupt set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x000007CC Interrupt masked register */
+ __IM uint32_t RESERVED16[12];
+ SMIF_DEVICE_V1_Type DEVICE[4]; /*!< 0x00000800 Device (only used in XIP mode) */
+} SMIF_V1_Type; /*!< Size = 2560 (0xA00) */
+
+
+/* SMIF_DEVICE.CTL */
+#define SMIF_DEVICE_CTL_WR_EN_Pos 0UL
+#define SMIF_DEVICE_CTL_WR_EN_Msk 0x1UL
+#define SMIF_DEVICE_CTL_CRYPTO_EN_Pos 8UL
+#define SMIF_DEVICE_CTL_CRYPTO_EN_Msk 0x100UL
+#define SMIF_DEVICE_CTL_DATA_SEL_Pos 16UL
+#define SMIF_DEVICE_CTL_DATA_SEL_Msk 0x30000UL
+#define SMIF_DEVICE_CTL_ENABLED_Pos 31UL
+#define SMIF_DEVICE_CTL_ENABLED_Msk 0x80000000UL
+/* SMIF_DEVICE.ADDR */
+#define SMIF_DEVICE_ADDR_ADDR_Pos 8UL
+#define SMIF_DEVICE_ADDR_ADDR_Msk 0xFFFFFF00UL
+/* SMIF_DEVICE.MASK */
+#define SMIF_DEVICE_MASK_MASK_Pos 8UL
+#define SMIF_DEVICE_MASK_MASK_Msk 0xFFFFFF00UL
+/* SMIF_DEVICE.ADDR_CTL */
+#define SMIF_DEVICE_ADDR_CTL_SIZE2_Pos 0UL
+#define SMIF_DEVICE_ADDR_CTL_SIZE2_Msk 0x3UL
+#define SMIF_DEVICE_ADDR_CTL_DIV2_Pos 8UL
+#define SMIF_DEVICE_ADDR_CTL_DIV2_Msk 0x100UL
+/* SMIF_DEVICE.RD_CMD_CTL */
+#define SMIF_DEVICE_RD_CMD_CTL_CODE_Pos 0UL
+#define SMIF_DEVICE_RD_CMD_CTL_CODE_Msk 0xFFUL
+#define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Msk 0x30000UL
+#define SMIF_DEVICE_RD_CMD_CTL_PRESENT_Pos 31UL
+#define SMIF_DEVICE_RD_CMD_CTL_PRESENT_Msk 0x80000000UL
+/* SMIF_DEVICE.RD_ADDR_CTL */
+#define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Msk 0x30000UL
+/* SMIF_DEVICE.RD_MODE_CTL */
+#define SMIF_DEVICE_RD_MODE_CTL_CODE_Pos 0UL
+#define SMIF_DEVICE_RD_MODE_CTL_CODE_Msk 0xFFUL
+#define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Msk 0x30000UL
+#define SMIF_DEVICE_RD_MODE_CTL_PRESENT_Pos 31UL
+#define SMIF_DEVICE_RD_MODE_CTL_PRESENT_Msk 0x80000000UL
+/* SMIF_DEVICE.RD_DUMMY_CTL */
+#define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Pos 0UL
+#define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Msk 0x1FUL
+#define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT_Pos 31UL
+#define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT_Msk 0x80000000UL
+/* SMIF_DEVICE.RD_DATA_CTL */
+#define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Msk 0x30000UL
+/* SMIF_DEVICE.WR_CMD_CTL */
+#define SMIF_DEVICE_WR_CMD_CTL_CODE_Pos 0UL
+#define SMIF_DEVICE_WR_CMD_CTL_CODE_Msk 0xFFUL
+#define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Msk 0x30000UL
+#define SMIF_DEVICE_WR_CMD_CTL_PRESENT_Pos 31UL
+#define SMIF_DEVICE_WR_CMD_CTL_PRESENT_Msk 0x80000000UL
+/* SMIF_DEVICE.WR_ADDR_CTL */
+#define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Msk 0x30000UL
+/* SMIF_DEVICE.WR_MODE_CTL */
+#define SMIF_DEVICE_WR_MODE_CTL_CODE_Pos 0UL
+#define SMIF_DEVICE_WR_MODE_CTL_CODE_Msk 0xFFUL
+#define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Msk 0x30000UL
+#define SMIF_DEVICE_WR_MODE_CTL_PRESENT_Pos 31UL
+#define SMIF_DEVICE_WR_MODE_CTL_PRESENT_Msk 0x80000000UL
+/* SMIF_DEVICE.WR_DUMMY_CTL */
+#define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Pos 0UL
+#define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Msk 0x1FUL
+#define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT_Pos 31UL
+#define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT_Msk 0x80000000UL
+/* SMIF_DEVICE.WR_DATA_CTL */
+#define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Msk 0x30000UL
+
+
+/* SMIF.CTL */
+#define SMIF_CTL_XIP_MODE_Pos 0UL
+#define SMIF_CTL_XIP_MODE_Msk 0x1UL
+#define SMIF_CTL_CLOCK_IF_RX_SEL_Pos 12UL
+#define SMIF_CTL_CLOCK_IF_RX_SEL_Msk 0x3000UL
+#define SMIF_CTL_DESELECT_DELAY_Pos 16UL
+#define SMIF_CTL_DESELECT_DELAY_Msk 0x70000UL
+#define SMIF_CTL_BLOCK_Pos 24UL
+#define SMIF_CTL_BLOCK_Msk 0x1000000UL
+#define SMIF_CTL_ENABLED_Pos 31UL
+#define SMIF_CTL_ENABLED_Msk 0x80000000UL
+/* SMIF.STATUS */
+#define SMIF_STATUS_BUSY_Pos 31UL
+#define SMIF_STATUS_BUSY_Msk 0x80000000UL
+/* SMIF.TX_CMD_FIFO_STATUS */
+#define SMIF_TX_CMD_FIFO_STATUS_USED3_Pos 0UL
+#define SMIF_TX_CMD_FIFO_STATUS_USED3_Msk 0x7UL
+/* SMIF.TX_CMD_FIFO_WR */
+#define SMIF_TX_CMD_FIFO_WR_DATA20_Pos 0UL
+#define SMIF_TX_CMD_FIFO_WR_DATA20_Msk 0xFFFFFUL
+/* SMIF.TX_DATA_FIFO_CTL */
+#define SMIF_TX_DATA_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
+#define SMIF_TX_DATA_FIFO_CTL_TRIGGER_LEVEL_Msk 0x7UL
+/* SMIF.TX_DATA_FIFO_STATUS */
+#define SMIF_TX_DATA_FIFO_STATUS_USED4_Pos 0UL
+#define SMIF_TX_DATA_FIFO_STATUS_USED4_Msk 0xFUL
+/* SMIF.TX_DATA_FIFO_WR1 */
+#define SMIF_TX_DATA_FIFO_WR1_DATA0_Pos 0UL
+#define SMIF_TX_DATA_FIFO_WR1_DATA0_Msk 0xFFUL
+/* SMIF.TX_DATA_FIFO_WR2 */
+#define SMIF_TX_DATA_FIFO_WR2_DATA0_Pos 0UL
+#define SMIF_TX_DATA_FIFO_WR2_DATA0_Msk 0xFFUL
+#define SMIF_TX_DATA_FIFO_WR2_DATA1_Pos 8UL
+#define SMIF_TX_DATA_FIFO_WR2_DATA1_Msk 0xFF00UL
+/* SMIF.TX_DATA_FIFO_WR4 */
+#define SMIF_TX_DATA_FIFO_WR4_DATA0_Pos 0UL
+#define SMIF_TX_DATA_FIFO_WR4_DATA0_Msk 0xFFUL
+#define SMIF_TX_DATA_FIFO_WR4_DATA1_Pos 8UL
+#define SMIF_TX_DATA_FIFO_WR4_DATA1_Msk 0xFF00UL
+#define SMIF_TX_DATA_FIFO_WR4_DATA2_Pos 16UL
+#define SMIF_TX_DATA_FIFO_WR4_DATA2_Msk 0xFF0000UL
+#define SMIF_TX_DATA_FIFO_WR4_DATA3_Pos 24UL
+#define SMIF_TX_DATA_FIFO_WR4_DATA3_Msk 0xFF000000UL
+/* SMIF.RX_DATA_FIFO_CTL */
+#define SMIF_RX_DATA_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
+#define SMIF_RX_DATA_FIFO_CTL_TRIGGER_LEVEL_Msk 0x7UL
+/* SMIF.RX_DATA_FIFO_STATUS */
+#define SMIF_RX_DATA_FIFO_STATUS_USED4_Pos 0UL
+#define SMIF_RX_DATA_FIFO_STATUS_USED4_Msk 0xFUL
+/* SMIF.RX_DATA_FIFO_RD1 */
+#define SMIF_RX_DATA_FIFO_RD1_DATA0_Pos 0UL
+#define SMIF_RX_DATA_FIFO_RD1_DATA0_Msk 0xFFUL
+/* SMIF.RX_DATA_FIFO_RD2 */
+#define SMIF_RX_DATA_FIFO_RD2_DATA0_Pos 0UL
+#define SMIF_RX_DATA_FIFO_RD2_DATA0_Msk 0xFFUL
+#define SMIF_RX_DATA_FIFO_RD2_DATA1_Pos 8UL
+#define SMIF_RX_DATA_FIFO_RD2_DATA1_Msk 0xFF00UL
+/* SMIF.RX_DATA_FIFO_RD4 */
+#define SMIF_RX_DATA_FIFO_RD4_DATA0_Pos 0UL
+#define SMIF_RX_DATA_FIFO_RD4_DATA0_Msk 0xFFUL
+#define SMIF_RX_DATA_FIFO_RD4_DATA1_Pos 8UL
+#define SMIF_RX_DATA_FIFO_RD4_DATA1_Msk 0xFF00UL
+#define SMIF_RX_DATA_FIFO_RD4_DATA2_Pos 16UL
+#define SMIF_RX_DATA_FIFO_RD4_DATA2_Msk 0xFF0000UL
+#define SMIF_RX_DATA_FIFO_RD4_DATA3_Pos 24UL
+#define SMIF_RX_DATA_FIFO_RD4_DATA3_Msk 0xFF000000UL
+/* SMIF.RX_DATA_FIFO_RD1_SILENT */
+#define SMIF_RX_DATA_FIFO_RD1_SILENT_DATA0_Pos 0UL
+#define SMIF_RX_DATA_FIFO_RD1_SILENT_DATA0_Msk 0xFFUL
+/* SMIF.SLOW_CA_CTL */
+#define SMIF_SLOW_CA_CTL_WAY_Pos 16UL
+#define SMIF_SLOW_CA_CTL_WAY_Msk 0x30000UL
+#define SMIF_SLOW_CA_CTL_SET_ADDR_Pos 24UL
+#define SMIF_SLOW_CA_CTL_SET_ADDR_Msk 0x3000000UL
+#define SMIF_SLOW_CA_CTL_PREF_EN_Pos 30UL
+#define SMIF_SLOW_CA_CTL_PREF_EN_Msk 0x40000000UL
+#define SMIF_SLOW_CA_CTL_ENABLED_Pos 31UL
+#define SMIF_SLOW_CA_CTL_ENABLED_Msk 0x80000000UL
+/* SMIF.SLOW_CA_CMD */
+#define SMIF_SLOW_CA_CMD_INV_Pos 0UL
+#define SMIF_SLOW_CA_CMD_INV_Msk 0x1UL
+/* SMIF.FAST_CA_CTL */
+#define SMIF_FAST_CA_CTL_WAY_Pos 16UL
+#define SMIF_FAST_CA_CTL_WAY_Msk 0x30000UL
+#define SMIF_FAST_CA_CTL_SET_ADDR_Pos 24UL
+#define SMIF_FAST_CA_CTL_SET_ADDR_Msk 0x3000000UL
+#define SMIF_FAST_CA_CTL_PREF_EN_Pos 30UL
+#define SMIF_FAST_CA_CTL_PREF_EN_Msk 0x40000000UL
+#define SMIF_FAST_CA_CTL_ENABLED_Pos 31UL
+#define SMIF_FAST_CA_CTL_ENABLED_Msk 0x80000000UL
+/* SMIF.FAST_CA_CMD */
+#define SMIF_FAST_CA_CMD_INV_Pos 0UL
+#define SMIF_FAST_CA_CMD_INV_Msk 0x1UL
+/* SMIF.CRYPTO_CMD */
+#define SMIF_CRYPTO_CMD_START_Pos 0UL
+#define SMIF_CRYPTO_CMD_START_Msk 0x1UL
+/* SMIF.CRYPTO_INPUT0 */
+#define SMIF_CRYPTO_INPUT0_INPUT_Pos 0UL
+#define SMIF_CRYPTO_INPUT0_INPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_INPUT1 */
+#define SMIF_CRYPTO_INPUT1_INPUT_Pos 0UL
+#define SMIF_CRYPTO_INPUT1_INPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_INPUT2 */
+#define SMIF_CRYPTO_INPUT2_INPUT_Pos 0UL
+#define SMIF_CRYPTO_INPUT2_INPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_INPUT3 */
+#define SMIF_CRYPTO_INPUT3_INPUT_Pos 0UL
+#define SMIF_CRYPTO_INPUT3_INPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_KEY0 */
+#define SMIF_CRYPTO_KEY0_KEY_Pos 0UL
+#define SMIF_CRYPTO_KEY0_KEY_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_KEY1 */
+#define SMIF_CRYPTO_KEY1_KEY_Pos 0UL
+#define SMIF_CRYPTO_KEY1_KEY_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_KEY2 */
+#define SMIF_CRYPTO_KEY2_KEY_Pos 0UL
+#define SMIF_CRYPTO_KEY2_KEY_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_KEY3 */
+#define SMIF_CRYPTO_KEY3_KEY_Pos 0UL
+#define SMIF_CRYPTO_KEY3_KEY_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_OUTPUT0 */
+#define SMIF_CRYPTO_OUTPUT0_OUTPUT_Pos 0UL
+#define SMIF_CRYPTO_OUTPUT0_OUTPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_OUTPUT1 */
+#define SMIF_CRYPTO_OUTPUT1_OUTPUT_Pos 0UL
+#define SMIF_CRYPTO_OUTPUT1_OUTPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_OUTPUT2 */
+#define SMIF_CRYPTO_OUTPUT2_OUTPUT_Pos 0UL
+#define SMIF_CRYPTO_OUTPUT2_OUTPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_OUTPUT3 */
+#define SMIF_CRYPTO_OUTPUT3_OUTPUT_Pos 0UL
+#define SMIF_CRYPTO_OUTPUT3_OUTPUT_Msk 0xFFFFFFFFUL
+/* SMIF.INTR */
+#define SMIF_INTR_TR_TX_REQ_Pos 0UL
+#define SMIF_INTR_TR_TX_REQ_Msk 0x1UL
+#define SMIF_INTR_TR_RX_REQ_Pos 1UL
+#define SMIF_INTR_TR_RX_REQ_Msk 0x2UL
+#define SMIF_INTR_XIP_ALIGNMENT_ERROR_Pos 2UL
+#define SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk 0x4UL
+#define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Pos 3UL
+#define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
+#define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Pos 4UL
+#define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
+#define SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Pos 5UL
+#define SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL
+/* SMIF.INTR_SET */
+#define SMIF_INTR_SET_TR_TX_REQ_Pos 0UL
+#define SMIF_INTR_SET_TR_TX_REQ_Msk 0x1UL
+#define SMIF_INTR_SET_TR_RX_REQ_Pos 1UL
+#define SMIF_INTR_SET_TR_RX_REQ_Msk 0x2UL
+#define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Pos 2UL
+#define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Msk 0x4UL
+#define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Pos 3UL
+#define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
+#define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Pos 4UL
+#define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
+#define SMIF_INTR_SET_RX_DATA_FIFO_UNDERFLOW_Pos 5UL
+#define SMIF_INTR_SET_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL
+/* SMIF.INTR_MASK */
+#define SMIF_INTR_MASK_TR_TX_REQ_Pos 0UL
+#define SMIF_INTR_MASK_TR_TX_REQ_Msk 0x1UL
+#define SMIF_INTR_MASK_TR_RX_REQ_Pos 1UL
+#define SMIF_INTR_MASK_TR_RX_REQ_Msk 0x2UL
+#define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Pos 2UL
+#define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Msk 0x4UL
+#define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Pos 3UL
+#define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
+#define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Pos 4UL
+#define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
+#define SMIF_INTR_MASK_RX_DATA_FIFO_UNDERFLOW_Pos 5UL
+#define SMIF_INTR_MASK_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL
+/* SMIF.INTR_MASKED */
+#define SMIF_INTR_MASKED_TR_TX_REQ_Pos 0UL
+#define SMIF_INTR_MASKED_TR_TX_REQ_Msk 0x1UL
+#define SMIF_INTR_MASKED_TR_RX_REQ_Pos 1UL
+#define SMIF_INTR_MASKED_TR_RX_REQ_Msk 0x2UL
+#define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Pos 2UL
+#define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Msk 0x4UL
+#define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Pos 3UL
+#define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
+#define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Pos 4UL
+#define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
+#define SMIF_INTR_MASKED_RX_DATA_FIFO_UNDERFLOW_Pos 5UL
+#define SMIF_INTR_MASKED_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL
+
+
+#endif /* _CYIP_SMIF_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_srss.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_srss.h
new file mode 100644
index 0000000000..d8730d5b68
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_srss.h
@@ -0,0 +1,625 @@
+/***************************************************************************//**
+* \file cyip_srss.h
+*
+* \brief
+* SRSS IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_SRSS_H_
+#define _CYIP_SRSS_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SRSS
+*******************************************************************************/
+
+#define MCWDT_STRUCT_SECTION_SIZE 0x00000040UL
+#define SRSS_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Multi-Counter Watchdog Timer (MCWDT_STRUCT)
+ */
+typedef struct {
+ __IM uint32_t RESERVED;
+ __IOM uint32_t MCWDT_CNTLOW; /*!< 0x00000004 Multi-Counter Watchdog Sub-counters 0/1 */
+ __IOM uint32_t MCWDT_CNTHIGH; /*!< 0x00000008 Multi-Counter Watchdog Sub-counter 2 */
+ __IOM uint32_t MCWDT_MATCH; /*!< 0x0000000C Multi-Counter Watchdog Counter Match Register */
+ __IOM uint32_t MCWDT_CONFIG; /*!< 0x00000010 Multi-Counter Watchdog Counter Configuration */
+ __IOM uint32_t MCWDT_CTL; /*!< 0x00000014 Multi-Counter Watchdog Counter Control */
+ __IOM uint32_t MCWDT_INTR; /*!< 0x00000018 Multi-Counter Watchdog Counter Interrupt Register */
+ __IOM uint32_t MCWDT_INTR_SET; /*!< 0x0000001C Multi-Counter Watchdog Counter Interrupt Set Register */
+ __IOM uint32_t MCWDT_INTR_MASK; /*!< 0x00000020 Multi-Counter Watchdog Counter Interrupt Mask Register */
+ __IM uint32_t MCWDT_INTR_MASKED; /*!< 0x00000024 Multi-Counter Watchdog Counter Interrupt Masked Register */
+ __IOM uint32_t MCWDT_LOCK; /*!< 0x00000028 Multi-Counter Watchdog Counter Lock Register */
+ __IM uint32_t RESERVED1[5];
+} MCWDT_STRUCT_V1_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief SRSS Core Registers (SRSS)
+ */
+typedef struct {
+ __IOM uint32_t PWR_CTL; /*!< 0x00000000 Power Mode Control */
+ __IOM uint32_t PWR_HIBERNATE; /*!< 0x00000004 HIBERNATE Mode Register */
+ __IOM uint32_t PWR_LVD_CTL; /*!< 0x00000008 Low Voltage Detector (LVD) Configuration Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t PWR_BUCK_CTL; /*!< 0x00000014 Buck Control Register */
+ __IOM uint32_t PWR_BUCK_CTL2; /*!< 0x00000018 Buck Control Register 2 */
+ __IM uint32_t PWR_LVD_STATUS; /*!< 0x0000001C Low Voltage Detector (LVD) Status Register */
+ __IM uint32_t RESERVED1[24];
+ __IOM uint32_t PWR_HIB_DATA[16]; /*!< 0x00000080 HIBERNATE Data Register */
+ __IM uint32_t RESERVED2[48];
+ __IOM uint32_t WDT_CTL; /*!< 0x00000180 Watchdog Counter Control Register */
+ __IOM uint32_t WDT_CNT; /*!< 0x00000184 Watchdog Counter Count Register */
+ __IOM uint32_t WDT_MATCH; /*!< 0x00000188 Watchdog Counter Match Register */
+ __IM uint32_t RESERVED3[29];
+ MCWDT_STRUCT_V1_Type MCWDT_STRUCT[4]; /*!< 0x00000200 Multi-Counter Watchdog Timer */
+ __IOM uint32_t CLK_DSI_SELECT[16]; /*!< 0x00000300 Clock DSI Select Register */
+ __IOM uint32_t CLK_PATH_SELECT[16]; /*!< 0x00000340 Clock Path Select Register */
+ __IOM uint32_t CLK_ROOT_SELECT[16]; /*!< 0x00000380 Clock Root Select Register */
+ __IM uint32_t RESERVED4[80];
+ __IOM uint32_t CLK_SELECT; /*!< 0x00000500 Clock selection register */
+ __IOM uint32_t CLK_TIMER_CTL; /*!< 0x00000504 Timer Clock Control Register */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t CLK_ILO_CONFIG; /*!< 0x0000050C ILO Configuration */
+ __IOM uint32_t CLK_IMO_CONFIG; /*!< 0x00000510 IMO Configuration */
+ __IOM uint32_t CLK_OUTPUT_FAST; /*!< 0x00000514 Fast Clock Output Select Register */
+ __IOM uint32_t CLK_OUTPUT_SLOW; /*!< 0x00000518 Slow Clock Output Select Register */
+ __IOM uint32_t CLK_CAL_CNT1; /*!< 0x0000051C Clock Calibration Counter 1 */
+ __IM uint32_t CLK_CAL_CNT2; /*!< 0x00000520 Clock Calibration Counter 2 */
+ __IM uint32_t RESERVED6[2];
+ __IOM uint32_t CLK_ECO_CONFIG; /*!< 0x0000052C ECO Configuration Register */
+ __IM uint32_t CLK_ECO_STATUS; /*!< 0x00000530 ECO Status Register */
+ __IM uint32_t RESERVED7[2];
+ __IOM uint32_t CLK_PILO_CONFIG; /*!< 0x0000053C Precision ILO Configuration Register */
+ __IM uint32_t RESERVED8;
+ __IOM uint32_t CLK_MF_SELECT; /*!< 0x00000544 Medium Frequency Clock Select Register */
+ __IOM uint32_t CLK_MFO_CONFIG; /*!< 0x00000548 MFO Configuration Register */
+ __IM uint32_t RESERVED9[13];
+ __IOM uint32_t CLK_FLL_CONFIG; /*!< 0x00000580 FLL Configuration Register */
+ __IOM uint32_t CLK_FLL_CONFIG2; /*!< 0x00000584 FLL Configuration Register 2 */
+ __IOM uint32_t CLK_FLL_CONFIG3; /*!< 0x00000588 FLL Configuration Register 3 */
+ __IOM uint32_t CLK_FLL_CONFIG4; /*!< 0x0000058C FLL Configuration Register 4 */
+ __IOM uint32_t CLK_FLL_STATUS; /*!< 0x00000590 FLL Status Register */
+ __IM uint32_t RESERVED10[27];
+ __IOM uint32_t CLK_PLL_CONFIG[15]; /*!< 0x00000600 PLL Configuration Register */
+ __IM uint32_t RESERVED11;
+ __IOM uint32_t CLK_PLL_STATUS[15]; /*!< 0x00000640 PLL Status Register */
+ __IM uint32_t RESERVED12[33];
+ __IOM uint32_t SRSS_INTR; /*!< 0x00000700 SRSS Interrupt Register */
+ __IOM uint32_t SRSS_INTR_SET; /*!< 0x00000704 SRSS Interrupt Set Register */
+ __IOM uint32_t SRSS_INTR_MASK; /*!< 0x00000708 SRSS Interrupt Mask Register */
+ __IM uint32_t SRSS_INTR_MASKED; /*!< 0x0000070C SRSS Interrupt Masked Register */
+ __IOM uint32_t SRSS_INTR_CFG; /*!< 0x00000710 SRSS Interrupt Configuration Register */
+ __IM uint32_t RESERVED13[59];
+ __IOM uint32_t RES_CAUSE; /*!< 0x00000800 Reset Cause Observation Register */
+ __IOM uint32_t RES_CAUSE2; /*!< 0x00000804 Reset Cause Observation Register 2 */
+ __IM uint32_t RESERVED14[7614];
+ __IOM uint32_t PWR_TRIM_REF_CTL; /*!< 0x00007F00 Reference Trim Register */
+ __IOM uint32_t PWR_TRIM_BODOVP_CTL; /*!< 0x00007F04 BOD/OVP Trim Register */
+ __IOM uint32_t CLK_TRIM_CCO_CTL; /*!< 0x00007F08 CCO Trim Register */
+ __IOM uint32_t CLK_TRIM_CCO_CTL2; /*!< 0x00007F0C CCO Trim Register 2 */
+ __IM uint32_t RESERVED15[8];
+ __IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00007F30 Wakeup Trim Register */
+ __IM uint32_t RESERVED16[8183];
+ __IOM uint32_t PWR_TRIM_LVD_CTL; /*!< 0x0000FF10 LVD Trim Register */
+ __IM uint32_t RESERVED17;
+ __IOM uint32_t CLK_TRIM_ILO_CTL; /*!< 0x0000FF18 ILO Trim Register */
+ __IOM uint32_t PWR_TRIM_PWRSYS_CTL; /*!< 0x0000FF1C Power System Trim Register */
+ __IOM uint32_t CLK_TRIM_ECO_CTL; /*!< 0x0000FF20 ECO Trim Register */
+ __IOM uint32_t CLK_TRIM_PILO_CTL; /*!< 0x0000FF24 PILO Trim Register */
+ __IOM uint32_t CLK_TRIM_PILO_CTL2; /*!< 0x0000FF28 PILO Trim Register 2 */
+ __IOM uint32_t CLK_TRIM_PILO_CTL3; /*!< 0x0000FF2C PILO Trim Register 3 */
+} SRSS_V1_Type; /*!< Size = 65328 (0xFF30) */
+
+
+/* MCWDT_STRUCT.MCWDT_CNTLOW */
+#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk 0xFFFFUL
+#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Pos 16UL
+#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Msk 0xFFFF0000UL
+/* MCWDT_STRUCT.MCWDT_CNTHIGH */
+#define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Msk 0xFFFFFFFFUL
+/* MCWDT_STRUCT.MCWDT_MATCH */
+#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk 0xFFFFUL
+#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Pos 16UL
+#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Msk 0xFFFF0000UL
+/* MCWDT_STRUCT.MCWDT_CONFIG */
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Msk 0x3UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Pos 2UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk 0x4UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Pos 3UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Msk 0x8UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Pos 8UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Msk 0x300UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Pos 10UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk 0x400UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Pos 11UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Msk 0x800UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Pos 16UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Msk 0x10000UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Pos 24UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Msk 0x1F000000UL
+/* MCWDT_STRUCT.MCWDT_CTL */
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk 0x1UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Pos 1UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Msk 0x2UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Pos 3UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk 0x8UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Pos 8UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk 0x100UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Pos 9UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Msk 0x200UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Pos 11UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk 0x800UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Pos 16UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk 0x10000UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Pos 17UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Msk 0x20000UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Pos 19UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk 0x80000UL
+/* MCWDT_STRUCT.MCWDT_INTR */
+#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Msk 0x1UL
+#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Pos 1UL
+#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Msk 0x2UL
+#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Pos 2UL
+#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Msk 0x4UL
+/* MCWDT_STRUCT.MCWDT_INTR_SET */
+#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Msk 0x1UL
+#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Pos 1UL
+#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Msk 0x2UL
+#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Pos 2UL
+#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Msk 0x4UL
+/* MCWDT_STRUCT.MCWDT_INTR_MASK */
+#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Msk 0x1UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Pos 1UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Msk 0x2UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Pos 2UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Msk 0x4UL
+/* MCWDT_STRUCT.MCWDT_INTR_MASKED */
+#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Msk 0x1UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Pos 1UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Msk 0x2UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Pos 2UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Msk 0x4UL
+/* MCWDT_STRUCT.MCWDT_LOCK */
+#define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Pos 30UL
+#define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Msk 0xC0000000UL
+
+
+/* SRSS.PWR_CTL */
+#define SRSS_PWR_CTL_POWER_MODE_Pos 0UL
+#define SRSS_PWR_CTL_POWER_MODE_Msk 0x3UL
+#define SRSS_PWR_CTL_DEBUG_SESSION_Pos 4UL
+#define SRSS_PWR_CTL_DEBUG_SESSION_Msk 0x10UL
+#define SRSS_PWR_CTL_LPM_READY_Pos 5UL
+#define SRSS_PWR_CTL_LPM_READY_Msk 0x20UL
+#define SRSS_PWR_CTL_IREF_LPMODE_Pos 18UL
+#define SRSS_PWR_CTL_IREF_LPMODE_Msk 0x40000UL
+#define SRSS_PWR_CTL_VREFBUF_OK_Pos 19UL
+#define SRSS_PWR_CTL_VREFBUF_OK_Msk 0x80000UL
+#define SRSS_PWR_CTL_DPSLP_REG_DIS_Pos 20UL
+#define SRSS_PWR_CTL_DPSLP_REG_DIS_Msk 0x100000UL
+#define SRSS_PWR_CTL_RET_REG_DIS_Pos 21UL
+#define SRSS_PWR_CTL_RET_REG_DIS_Msk 0x200000UL
+#define SRSS_PWR_CTL_NWELL_REG_DIS_Pos 22UL
+#define SRSS_PWR_CTL_NWELL_REG_DIS_Msk 0x400000UL
+#define SRSS_PWR_CTL_LINREG_DIS_Pos 23UL
+#define SRSS_PWR_CTL_LINREG_DIS_Msk 0x800000UL
+#define SRSS_PWR_CTL_LINREG_LPMODE_Pos 24UL
+#define SRSS_PWR_CTL_LINREG_LPMODE_Msk 0x1000000UL
+#define SRSS_PWR_CTL_PORBOD_LPMODE_Pos 25UL
+#define SRSS_PWR_CTL_PORBOD_LPMODE_Msk 0x2000000UL
+#define SRSS_PWR_CTL_BGREF_LPMODE_Pos 26UL
+#define SRSS_PWR_CTL_BGREF_LPMODE_Msk 0x4000000UL
+#define SRSS_PWR_CTL_PLL_LS_BYPASS_Pos 27UL
+#define SRSS_PWR_CTL_PLL_LS_BYPASS_Msk 0x8000000UL
+#define SRSS_PWR_CTL_VREFBUF_LPMODE_Pos 28UL
+#define SRSS_PWR_CTL_VREFBUF_LPMODE_Msk 0x10000000UL
+#define SRSS_PWR_CTL_VREFBUF_DIS_Pos 29UL
+#define SRSS_PWR_CTL_VREFBUF_DIS_Msk 0x20000000UL
+#define SRSS_PWR_CTL_ACT_REF_DIS_Pos 30UL
+#define SRSS_PWR_CTL_ACT_REF_DIS_Msk 0x40000000UL
+#define SRSS_PWR_CTL_ACT_REF_OK_Pos 31UL
+#define SRSS_PWR_CTL_ACT_REF_OK_Msk 0x80000000UL
+/* SRSS.PWR_HIBERNATE */
+#define SRSS_PWR_HIBERNATE_TOKEN_Pos 0UL
+#define SRSS_PWR_HIBERNATE_TOKEN_Msk 0xFFUL
+#define SRSS_PWR_HIBERNATE_UNLOCK_Pos 8UL
+#define SRSS_PWR_HIBERNATE_UNLOCK_Msk 0xFF00UL
+#define SRSS_PWR_HIBERNATE_FREEZE_Pos 17UL
+#define SRSS_PWR_HIBERNATE_FREEZE_Msk 0x20000UL
+#define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Pos 18UL
+#define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk 0x40000UL
+#define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Pos 19UL
+#define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk 0x80000UL
+#define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos 20UL
+#define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk 0xF00000UL
+#define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos 24UL
+#define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk 0xF000000UL
+#define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Pos 30UL
+#define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Msk 0x40000000UL
+#define SRSS_PWR_HIBERNATE_HIBERNATE_Pos 31UL
+#define SRSS_PWR_HIBERNATE_HIBERNATE_Msk 0x80000000UL
+/* SRSS.PWR_LVD_CTL */
+#define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Pos 0UL
+#define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Msk 0xFUL
+#define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Pos 4UL
+#define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Msk 0x70UL
+#define SRSS_PWR_LVD_CTL_HVLVD1_EN_Pos 7UL
+#define SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk 0x80UL
+/* SRSS.PWR_BUCK_CTL */
+#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Pos 0UL
+#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Msk 0x7UL
+#define SRSS_PWR_BUCK_CTL_BUCK_EN_Pos 30UL
+#define SRSS_PWR_BUCK_CTL_BUCK_EN_Msk 0x40000000UL
+#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Pos 31UL
+#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Msk 0x80000000UL
+/* SRSS.PWR_BUCK_CTL2 */
+#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Pos 0UL
+#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Msk 0x7UL
+#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Pos 30UL
+#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Msk 0x40000000UL
+#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Pos 31UL
+#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Msk 0x80000000UL
+/* SRSS.PWR_LVD_STATUS */
+#define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Pos 0UL
+#define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Msk 0x1UL
+/* SRSS.PWR_HIB_DATA */
+#define SRSS_PWR_HIB_DATA_HIB_DATA_Pos 0UL
+#define SRSS_PWR_HIB_DATA_HIB_DATA_Msk 0xFFFFFFFFUL
+/* SRSS.WDT_CTL */
+#define SRSS_WDT_CTL_WDT_EN_Pos 0UL
+#define SRSS_WDT_CTL_WDT_EN_Msk 0x1UL
+#define SRSS_WDT_CTL_WDT_LOCK_Pos 30UL
+#define SRSS_WDT_CTL_WDT_LOCK_Msk 0xC0000000UL
+/* SRSS.WDT_CNT */
+#define SRSS_WDT_CNT_COUNTER_Pos 0UL
+#define SRSS_WDT_CNT_COUNTER_Msk 0xFFFFUL
+/* SRSS.WDT_MATCH */
+#define SRSS_WDT_MATCH_MATCH_Pos 0UL
+#define SRSS_WDT_MATCH_MATCH_Msk 0xFFFFUL
+#define SRSS_WDT_MATCH_IGNORE_BITS_Pos 16UL
+#define SRSS_WDT_MATCH_IGNORE_BITS_Msk 0xF0000UL
+/* SRSS.CLK_DSI_SELECT */
+#define SRSS_CLK_DSI_SELECT_DSI_MUX_Pos 0UL
+#define SRSS_CLK_DSI_SELECT_DSI_MUX_Msk 0x1FUL
+/* SRSS.CLK_PATH_SELECT */
+#define SRSS_CLK_PATH_SELECT_PATH_MUX_Pos 0UL
+#define SRSS_CLK_PATH_SELECT_PATH_MUX_Msk 0x7UL
+/* SRSS.CLK_ROOT_SELECT */
+#define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Pos 0UL
+#define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk 0xFUL
+#define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Pos 4UL
+#define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk 0x30UL
+#define SRSS_CLK_ROOT_SELECT_ENABLE_Pos 31UL
+#define SRSS_CLK_ROOT_SELECT_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_SELECT */
+#define SRSS_CLK_SELECT_LFCLK_SEL_Pos 0UL
+#define SRSS_CLK_SELECT_LFCLK_SEL_Msk 0x3UL
+#define SRSS_CLK_SELECT_PUMP_SEL_Pos 8UL
+#define SRSS_CLK_SELECT_PUMP_SEL_Msk 0xF00UL
+#define SRSS_CLK_SELECT_PUMP_DIV_Pos 12UL
+#define SRSS_CLK_SELECT_PUMP_DIV_Msk 0x7000UL
+#define SRSS_CLK_SELECT_PUMP_ENABLE_Pos 15UL
+#define SRSS_CLK_SELECT_PUMP_ENABLE_Msk 0x8000UL
+/* SRSS.CLK_TIMER_CTL */
+#define SRSS_CLK_TIMER_CTL_TIMER_SEL_Pos 0UL
+#define SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk 0x1UL
+#define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Pos 8UL
+#define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk 0x300UL
+#define SRSS_CLK_TIMER_CTL_TIMER_DIV_Pos 16UL
+#define SRSS_CLK_TIMER_CTL_TIMER_DIV_Msk 0xFF0000UL
+#define SRSS_CLK_TIMER_CTL_ENABLE_Pos 31UL
+#define SRSS_CLK_TIMER_CTL_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_ILO_CONFIG */
+#define SRSS_CLK_ILO_CONFIG_ILO_BACKUP_Pos 0UL
+#define SRSS_CLK_ILO_CONFIG_ILO_BACKUP_Msk 0x1UL
+#define SRSS_CLK_ILO_CONFIG_ENABLE_Pos 31UL
+#define SRSS_CLK_ILO_CONFIG_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_IMO_CONFIG */
+#define SRSS_CLK_IMO_CONFIG_ENABLE_Pos 31UL
+#define SRSS_CLK_IMO_CONFIG_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_OUTPUT_FAST */
+#define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Pos 0UL
+#define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk 0xFUL
+#define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Pos 4UL
+#define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk 0xF0UL
+#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos 8UL
+#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk 0xF00UL
+#define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Pos 16UL
+#define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk 0xF0000UL
+#define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Pos 20UL
+#define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk 0xF00000UL
+#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos 24UL
+#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk 0xF000000UL
+/* SRSS.CLK_OUTPUT_SLOW */
+#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos 0UL
+#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk 0xFUL
+#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos 4UL
+#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk 0xF0UL
+/* SRSS.CLK_CAL_CNT1 */
+#define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos 0UL
+#define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk 0xFFFFFFUL
+#define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos 31UL
+#define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk 0x80000000UL
+/* SRSS.CLK_CAL_CNT2 */
+#define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Pos 0UL
+#define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Msk 0xFFFFFFUL
+/* SRSS.CLK_ECO_CONFIG */
+#define SRSS_CLK_ECO_CONFIG_AGC_EN_Pos 1UL
+#define SRSS_CLK_ECO_CONFIG_AGC_EN_Msk 0x2UL
+#define SRSS_CLK_ECO_CONFIG_ECO_EN_Pos 31UL
+#define SRSS_CLK_ECO_CONFIG_ECO_EN_Msk 0x80000000UL
+/* SRSS.CLK_ECO_STATUS */
+#define SRSS_CLK_ECO_STATUS_ECO_OK_Pos 0UL
+#define SRSS_CLK_ECO_STATUS_ECO_OK_Msk 0x1UL
+#define SRSS_CLK_ECO_STATUS_ECO_READY_Pos 1UL
+#define SRSS_CLK_ECO_STATUS_ECO_READY_Msk 0x2UL
+/* SRSS.CLK_PILO_CONFIG */
+#define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Pos 0UL
+#define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Msk 0x3FFUL
+#define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Pos 29UL
+#define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk 0x20000000UL
+#define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Pos 30UL
+#define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk 0x40000000UL
+#define SRSS_CLK_PILO_CONFIG_PILO_EN_Pos 31UL
+#define SRSS_CLK_PILO_CONFIG_PILO_EN_Msk 0x80000000UL
+/* SRSS.CLK_MF_SELECT */
+#define SRSS_CLK_MF_SELECT_MFCLK_SEL_Pos 0UL
+#define SRSS_CLK_MF_SELECT_MFCLK_SEL_Msk 0x7UL
+#define SRSS_CLK_MF_SELECT_MFCLK_DIV_Pos 8UL
+#define SRSS_CLK_MF_SELECT_MFCLK_DIV_Msk 0xFF00UL
+#define SRSS_CLK_MF_SELECT_ENABLE_Pos 31UL
+#define SRSS_CLK_MF_SELECT_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_MFO_CONFIG */
+#define SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Pos 30UL
+#define SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Msk 0x40000000UL
+#define SRSS_CLK_MFO_CONFIG_ENABLE_Pos 31UL
+#define SRSS_CLK_MFO_CONFIG_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_FLL_CONFIG */
+#define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos 0UL
+#define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk 0x3FFFFUL
+#define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos 24UL
+#define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk 0x1000000UL
+#define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Pos 31UL
+#define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_FLL_CONFIG2 */
+#define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos 0UL
+#define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk 0x1FFFUL
+#define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos 16UL
+#define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk 0x1FF0000UL
+/* SRSS.CLK_FLL_CONFIG3 */
+#define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos 0UL
+#define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk 0xFUL
+#define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos 4UL
+#define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk 0xF0UL
+#define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos 8UL
+#define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk 0x1FFF00UL
+#define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Pos 28UL
+#define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Msk 0x30000000UL
+/* SRSS.CLK_FLL_CONFIG4 */
+#define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Pos 0UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Msk 0xFFUL
+#define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos 8UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk 0x700UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos 16UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk 0x1FF0000UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Pos 30UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Msk 0x40000000UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Pos 31UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_FLL_STATUS */
+#define SRSS_CLK_FLL_STATUS_LOCKED_Pos 0UL
+#define SRSS_CLK_FLL_STATUS_LOCKED_Msk 0x1UL
+#define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Pos 1UL
+#define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL
+#define SRSS_CLK_FLL_STATUS_CCO_READY_Pos 2UL
+#define SRSS_CLK_FLL_STATUS_CCO_READY_Msk 0x4UL
+/* SRSS.CLK_PLL_CONFIG */
+#define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos 0UL
+#define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk 0x7FUL
+#define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Pos 8UL
+#define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Msk 0x1F00UL
+#define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 16UL
+#define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL
+#define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Pos 27UL
+#define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Msk 0x8000000UL
+#define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos 28UL
+#define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk 0x30000000UL
+#define SRSS_CLK_PLL_CONFIG_ENABLE_Pos 31UL
+#define SRSS_CLK_PLL_CONFIG_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_PLL_STATUS */
+#define SRSS_CLK_PLL_STATUS_LOCKED_Pos 0UL
+#define SRSS_CLK_PLL_STATUS_LOCKED_Msk 0x1UL
+#define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos 1UL
+#define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL
+/* SRSS.SRSS_INTR */
+#define SRSS_SRSS_INTR_WDT_MATCH_Pos 0UL
+#define SRSS_SRSS_INTR_WDT_MATCH_Msk 0x1UL
+#define SRSS_SRSS_INTR_HVLVD1_Pos 1UL
+#define SRSS_SRSS_INTR_HVLVD1_Msk 0x2UL
+#define SRSS_SRSS_INTR_CLK_CAL_Pos 5UL
+#define SRSS_SRSS_INTR_CLK_CAL_Msk 0x20UL
+/* SRSS.SRSS_INTR_SET */
+#define SRSS_SRSS_INTR_SET_WDT_MATCH_Pos 0UL
+#define SRSS_SRSS_INTR_SET_WDT_MATCH_Msk 0x1UL
+#define SRSS_SRSS_INTR_SET_HVLVD1_Pos 1UL
+#define SRSS_SRSS_INTR_SET_HVLVD1_Msk 0x2UL
+#define SRSS_SRSS_INTR_SET_CLK_CAL_Pos 5UL
+#define SRSS_SRSS_INTR_SET_CLK_CAL_Msk 0x20UL
+/* SRSS.SRSS_INTR_MASK */
+#define SRSS_SRSS_INTR_MASK_WDT_MATCH_Pos 0UL
+#define SRSS_SRSS_INTR_MASK_WDT_MATCH_Msk 0x1UL
+#define SRSS_SRSS_INTR_MASK_HVLVD1_Pos 1UL
+#define SRSS_SRSS_INTR_MASK_HVLVD1_Msk 0x2UL
+#define SRSS_SRSS_INTR_MASK_CLK_CAL_Pos 5UL
+#define SRSS_SRSS_INTR_MASK_CLK_CAL_Msk 0x20UL
+/* SRSS.SRSS_INTR_MASKED */
+#define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Pos 0UL
+#define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Msk 0x1UL
+#define SRSS_SRSS_INTR_MASKED_HVLVD1_Pos 1UL
+#define SRSS_SRSS_INTR_MASKED_HVLVD1_Msk 0x2UL
+#define SRSS_SRSS_INTR_MASKED_CLK_CAL_Pos 5UL
+#define SRSS_SRSS_INTR_MASKED_CLK_CAL_Msk 0x20UL
+/* SRSS.SRSS_INTR_CFG */
+#define SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL_Pos 0UL
+#define SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL_Msk 0x3UL
+/* SRSS.RES_CAUSE */
+#define SRSS_RES_CAUSE_RESET_WDT_Pos 0UL
+#define SRSS_RES_CAUSE_RESET_WDT_Msk 0x1UL
+#define SRSS_RES_CAUSE_RESET_ACT_FAULT_Pos 1UL
+#define SRSS_RES_CAUSE_RESET_ACT_FAULT_Msk 0x2UL
+#define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Pos 2UL
+#define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Msk 0x4UL
+#define SRSS_RES_CAUSE_RESET_CSV_WCO_LOSS_Pos 3UL
+#define SRSS_RES_CAUSE_RESET_CSV_WCO_LOSS_Msk 0x8UL
+#define SRSS_RES_CAUSE_RESET_SOFT_Pos 4UL
+#define SRSS_RES_CAUSE_RESET_SOFT_Msk 0x10UL
+#define SRSS_RES_CAUSE_RESET_MCWDT0_Pos 5UL
+#define SRSS_RES_CAUSE_RESET_MCWDT0_Msk 0x20UL
+#define SRSS_RES_CAUSE_RESET_MCWDT1_Pos 6UL
+#define SRSS_RES_CAUSE_RESET_MCWDT1_Msk 0x40UL
+#define SRSS_RES_CAUSE_RESET_MCWDT2_Pos 7UL
+#define SRSS_RES_CAUSE_RESET_MCWDT2_Msk 0x80UL
+#define SRSS_RES_CAUSE_RESET_MCWDT3_Pos 8UL
+#define SRSS_RES_CAUSE_RESET_MCWDT3_Msk 0x100UL
+/* SRSS.RES_CAUSE2 */
+#define SRSS_RES_CAUSE2_RESET_CSV_HF_LOSS_Pos 0UL
+#define SRSS_RES_CAUSE2_RESET_CSV_HF_LOSS_Msk 0xFFFFUL
+#define SRSS_RES_CAUSE2_RESET_CSV_HF_FREQ_Pos 16UL
+#define SRSS_RES_CAUSE2_RESET_CSV_HF_FREQ_Msk 0xFFFF0000UL
+/* SRSS.PWR_TRIM_REF_CTL */
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_TCTRIM_Pos 0UL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_TCTRIM_Msk 0xFUL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ITRIM_Pos 4UL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ITRIM_Msk 0xF0UL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ABSTRIM_Pos 8UL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ABSTRIM_Msk 0x1F00UL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_IBOOST_Pos 14UL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_IBOOST_Msk 0x4000UL
+#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_TCTRIM_Pos 16UL
+#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_TCTRIM_Msk 0xF0000UL
+#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ABSTRIM_Pos 20UL
+#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ABSTRIM_Msk 0x1F00000UL
+#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ITRIM_Pos 28UL
+#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ITRIM_Msk 0xF0000000UL
+/* SRSS.PWR_TRIM_BODOVP_CTL */
+#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_TRIPSEL_Pos 0UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_TRIPSEL_Msk 0x7UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_OFSTRIM_Pos 4UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_OFSTRIM_Msk 0x70UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_ITRIM_Pos 7UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_ITRIM_Msk 0x380UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_TRIPSEL_Pos 10UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_TRIPSEL_Msk 0x1C00UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_OFSTRIM_Pos 14UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_OFSTRIM_Msk 0x1C000UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_ITRIM_Pos 17UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_ITRIM_Msk 0xE0000UL
+/* SRSS.CLK_TRIM_CCO_CTL */
+#define SRSS_CLK_TRIM_CCO_CTL_CCO_RCSTRIM_Pos 0UL
+#define SRSS_CLK_TRIM_CCO_CTL_CCO_RCSTRIM_Msk 0x3FUL
+#define SRSS_CLK_TRIM_CCO_CTL_CCO_STABLE_CNT_Pos 24UL
+#define SRSS_CLK_TRIM_CCO_CTL_CCO_STABLE_CNT_Msk 0x3F000000UL
+#define SRSS_CLK_TRIM_CCO_CTL_ENABLE_CNT_Pos 31UL
+#define SRSS_CLK_TRIM_CCO_CTL_ENABLE_CNT_Msk 0x80000000UL
+/* SRSS.CLK_TRIM_CCO_CTL2 */
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM1_Pos 0UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM1_Msk 0x1FUL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM2_Pos 5UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM2_Msk 0x3E0UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM3_Pos 10UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM3_Msk 0x7C00UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM4_Pos 15UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM4_Msk 0xF8000UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM5_Pos 20UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM5_Msk 0x1F00000UL
+/* SRSS.PWR_TRIM_WAKE_CTL */
+#define SRSS_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Pos 0UL
+#define SRSS_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Msk 0xFFUL
+/* SRSS.PWR_TRIM_LVD_CTL */
+#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_OFSTRIM_Pos 0UL
+#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_OFSTRIM_Msk 0x7UL
+#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_ITRIM_Pos 4UL
+#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_ITRIM_Msk 0x70UL
+/* SRSS.CLK_TRIM_ILO_CTL */
+#define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Pos 0UL
+#define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Msk 0x3FUL
+/* SRSS.PWR_TRIM_PWRSYS_CTL */
+#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Pos 0UL
+#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Msk 0x1FUL
+#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Pos 30UL
+#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Msk 0xC0000000UL
+/* SRSS.CLK_TRIM_ECO_CTL */
+#define SRSS_CLK_TRIM_ECO_CTL_WDTRIM_Pos 0UL
+#define SRSS_CLK_TRIM_ECO_CTL_WDTRIM_Msk 0x7UL
+#define SRSS_CLK_TRIM_ECO_CTL_ATRIM_Pos 4UL
+#define SRSS_CLK_TRIM_ECO_CTL_ATRIM_Msk 0xF0UL
+#define SRSS_CLK_TRIM_ECO_CTL_FTRIM_Pos 8UL
+#define SRSS_CLK_TRIM_ECO_CTL_FTRIM_Msk 0x300UL
+#define SRSS_CLK_TRIM_ECO_CTL_RTRIM_Pos 10UL
+#define SRSS_CLK_TRIM_ECO_CTL_RTRIM_Msk 0xC00UL
+#define SRSS_CLK_TRIM_ECO_CTL_GTRIM_Pos 12UL
+#define SRSS_CLK_TRIM_ECO_CTL_GTRIM_Msk 0x3000UL
+#define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Pos 16UL
+#define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Msk 0x3F0000UL
+/* SRSS.CLK_TRIM_PILO_CTL */
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Pos 0UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Msk 0x3FUL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Pos 12UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Msk 0x7000UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Pos 16UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Msk 0x30000UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Pos 18UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Msk 0xC0000UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Pos 20UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Msk 0x1F00000UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Pos 26UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Msk 0xC000000UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Pos 28UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Msk 0x70000000UL
+/* SRSS.CLK_TRIM_PILO_CTL2 */
+#define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Pos 0UL
+#define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Msk 0xFFUL
+#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Pos 8UL
+#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Msk 0x1F00UL
+#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Pos 16UL
+#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Msk 0xFF0000UL
+/* SRSS.CLK_TRIM_PILO_CTL3 */
+#define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Pos 0UL
+#define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Msk 0xFFFFUL
+
+
+#endif /* _CYIP_SRSS_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_tcpwm.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_tcpwm.h
new file mode 100644
index 0000000000..a728d0c5ff
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_tcpwm.h
@@ -0,0 +1,200 @@
+/***************************************************************************//**
+* \file cyip_tcpwm.h
+*
+* \brief
+* TCPWM IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_TCPWM_H_
+#define _CYIP_TCPWM_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* TCPWM
+*******************************************************************************/
+
+#define TCPWM_CNT_SECTION_SIZE 0x00000040UL
+#define TCPWM_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Timer/Counter/PWM Counter Module (TCPWM_CNT)
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< 0x00000000 Counter control register */
+ __IM uint32_t STATUS; /*!< 0x00000004 Counter status register */
+ __IOM uint32_t COUNTER; /*!< 0x00000008 Counter count register */
+ __IOM uint32_t CC; /*!< 0x0000000C Counter compare/capture register */
+ __IOM uint32_t CC_BUFF; /*!< 0x00000010 Counter buffered compare/capture register */
+ __IOM uint32_t PERIOD; /*!< 0x00000014 Counter period register */
+ __IOM uint32_t PERIOD_BUFF; /*!< 0x00000018 Counter buffered period register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t TR_CTRL0; /*!< 0x00000020 Counter trigger control register 0 */
+ __IOM uint32_t TR_CTRL1; /*!< 0x00000024 Counter trigger control register 1 */
+ __IOM uint32_t TR_CTRL2; /*!< 0x00000028 Counter trigger control register 2 */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t INTR; /*!< 0x00000030 Interrupt request register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000034 Interrupt set request register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000038 Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000003C Interrupt masked request register */
+} TCPWM_CNT_V1_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief Timer/Counter/PWM (TCPWM)
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< 0x00000000 TCPWM control register */
+ __IOM uint32_t CTRL_CLR; /*!< 0x00000004 TCPWM control clear register */
+ __IOM uint32_t CTRL_SET; /*!< 0x00000008 TCPWM control set register */
+ __IOM uint32_t CMD_CAPTURE; /*!< 0x0000000C TCPWM capture command register */
+ __IOM uint32_t CMD_RELOAD; /*!< 0x00000010 TCPWM reload command register */
+ __IOM uint32_t CMD_STOP; /*!< 0x00000014 TCPWM stop command register */
+ __IOM uint32_t CMD_START; /*!< 0x00000018 TCPWM start command register */
+ __IM uint32_t INTR_CAUSE; /*!< 0x0000001C TCPWM Counter interrupt cause register */
+ __IM uint32_t RESERVED[56];
+ TCPWM_CNT_V1_Type CNT[32]; /*!< 0x00000100 Timer/Counter/PWM Counter Module */
+} TCPWM_V1_Type; /*!< Size = 2304 (0x900) */
+
+
+/* TCPWM_CNT.CTRL */
+#define TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Pos 0UL
+#define TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk 0x1UL
+#define TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos 1UL
+#define TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk 0x2UL
+#define TCPWM_CNT_CTRL_PWM_SYNC_KILL_Pos 2UL
+#define TCPWM_CNT_CTRL_PWM_SYNC_KILL_Msk 0x4UL
+#define TCPWM_CNT_CTRL_PWM_STOP_ON_KILL_Pos 3UL
+#define TCPWM_CNT_CTRL_PWM_STOP_ON_KILL_Msk 0x8UL
+#define TCPWM_CNT_CTRL_GENERIC_Pos 8UL
+#define TCPWM_CNT_CTRL_GENERIC_Msk 0xFF00UL
+#define TCPWM_CNT_CTRL_UP_DOWN_MODE_Pos 16UL
+#define TCPWM_CNT_CTRL_UP_DOWN_MODE_Msk 0x30000UL
+#define TCPWM_CNT_CTRL_ONE_SHOT_Pos 18UL
+#define TCPWM_CNT_CTRL_ONE_SHOT_Msk 0x40000UL
+#define TCPWM_CNT_CTRL_QUADRATURE_MODE_Pos 20UL
+#define TCPWM_CNT_CTRL_QUADRATURE_MODE_Msk 0x300000UL
+#define TCPWM_CNT_CTRL_MODE_Pos 24UL
+#define TCPWM_CNT_CTRL_MODE_Msk 0x7000000UL
+/* TCPWM_CNT.STATUS */
+#define TCPWM_CNT_STATUS_DOWN_Pos 0UL
+#define TCPWM_CNT_STATUS_DOWN_Msk 0x1UL
+#define TCPWM_CNT_STATUS_GENERIC_Pos 8UL
+#define TCPWM_CNT_STATUS_GENERIC_Msk 0xFF00UL
+#define TCPWM_CNT_STATUS_RUNNING_Pos 31UL
+#define TCPWM_CNT_STATUS_RUNNING_Msk 0x80000000UL
+/* TCPWM_CNT.COUNTER */
+#define TCPWM_CNT_COUNTER_COUNTER_Pos 0UL
+#define TCPWM_CNT_COUNTER_COUNTER_Msk 0xFFFFFFFFUL
+/* TCPWM_CNT.CC */
+#define TCPWM_CNT_CC_CC_Pos 0UL
+#define TCPWM_CNT_CC_CC_Msk 0xFFFFFFFFUL
+/* TCPWM_CNT.CC_BUFF */
+#define TCPWM_CNT_CC_BUFF_CC_Pos 0UL
+#define TCPWM_CNT_CC_BUFF_CC_Msk 0xFFFFFFFFUL
+/* TCPWM_CNT.PERIOD */
+#define TCPWM_CNT_PERIOD_PERIOD_Pos 0UL
+#define TCPWM_CNT_PERIOD_PERIOD_Msk 0xFFFFFFFFUL
+/* TCPWM_CNT.PERIOD_BUFF */
+#define TCPWM_CNT_PERIOD_BUFF_PERIOD_Pos 0UL
+#define TCPWM_CNT_PERIOD_BUFF_PERIOD_Msk 0xFFFFFFFFUL
+/* TCPWM_CNT.TR_CTRL0 */
+#define TCPWM_CNT_TR_CTRL0_CAPTURE_SEL_Pos 0UL
+#define TCPWM_CNT_TR_CTRL0_CAPTURE_SEL_Msk 0xFUL
+#define TCPWM_CNT_TR_CTRL0_COUNT_SEL_Pos 4UL
+#define TCPWM_CNT_TR_CTRL0_COUNT_SEL_Msk 0xF0UL
+#define TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Pos 8UL
+#define TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Msk 0xF00UL
+#define TCPWM_CNT_TR_CTRL0_STOP_SEL_Pos 12UL
+#define TCPWM_CNT_TR_CTRL0_STOP_SEL_Msk 0xF000UL
+#define TCPWM_CNT_TR_CTRL0_START_SEL_Pos 16UL
+#define TCPWM_CNT_TR_CTRL0_START_SEL_Msk 0xF0000UL
+/* TCPWM_CNT.TR_CTRL1 */
+#define TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE_Pos 0UL
+#define TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE_Msk 0x3UL
+#define TCPWM_CNT_TR_CTRL1_COUNT_EDGE_Pos 2UL
+#define TCPWM_CNT_TR_CTRL1_COUNT_EDGE_Msk 0xCUL
+#define TCPWM_CNT_TR_CTRL1_RELOAD_EDGE_Pos 4UL
+#define TCPWM_CNT_TR_CTRL1_RELOAD_EDGE_Msk 0x30UL
+#define TCPWM_CNT_TR_CTRL1_STOP_EDGE_Pos 6UL
+#define TCPWM_CNT_TR_CTRL1_STOP_EDGE_Msk 0xC0UL
+#define TCPWM_CNT_TR_CTRL1_START_EDGE_Pos 8UL
+#define TCPWM_CNT_TR_CTRL1_START_EDGE_Msk 0x300UL
+/* TCPWM_CNT.TR_CTRL2 */
+#define TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE_Pos 0UL
+#define TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE_Msk 0x3UL
+#define TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE_Pos 2UL
+#define TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE_Msk 0xCUL
+#define TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE_Pos 4UL
+#define TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE_Msk 0x30UL
+/* TCPWM_CNT.INTR */
+#define TCPWM_CNT_INTR_TC_Pos 0UL
+#define TCPWM_CNT_INTR_TC_Msk 0x1UL
+#define TCPWM_CNT_INTR_CC_MATCH_Pos 1UL
+#define TCPWM_CNT_INTR_CC_MATCH_Msk 0x2UL
+/* TCPWM_CNT.INTR_SET */
+#define TCPWM_CNT_INTR_SET_TC_Pos 0UL
+#define TCPWM_CNT_INTR_SET_TC_Msk 0x1UL
+#define TCPWM_CNT_INTR_SET_CC_MATCH_Pos 1UL
+#define TCPWM_CNT_INTR_SET_CC_MATCH_Msk 0x2UL
+/* TCPWM_CNT.INTR_MASK */
+#define TCPWM_CNT_INTR_MASK_TC_Pos 0UL
+#define TCPWM_CNT_INTR_MASK_TC_Msk 0x1UL
+#define TCPWM_CNT_INTR_MASK_CC_MATCH_Pos 1UL
+#define TCPWM_CNT_INTR_MASK_CC_MATCH_Msk 0x2UL
+/* TCPWM_CNT.INTR_MASKED */
+#define TCPWM_CNT_INTR_MASKED_TC_Pos 0UL
+#define TCPWM_CNT_INTR_MASKED_TC_Msk 0x1UL
+#define TCPWM_CNT_INTR_MASKED_CC_MATCH_Pos 1UL
+#define TCPWM_CNT_INTR_MASKED_CC_MATCH_Msk 0x2UL
+
+
+/* TCPWM.CTRL */
+#define TCPWM_CTRL_COUNTER_ENABLED_Pos 0UL
+#define TCPWM_CTRL_COUNTER_ENABLED_Msk 0xFFFFFFFFUL
+/* TCPWM.CTRL_CLR */
+#define TCPWM_CTRL_CLR_COUNTER_ENABLED_Pos 0UL
+#define TCPWM_CTRL_CLR_COUNTER_ENABLED_Msk 0xFFFFFFFFUL
+/* TCPWM.CTRL_SET */
+#define TCPWM_CTRL_SET_COUNTER_ENABLED_Pos 0UL
+#define TCPWM_CTRL_SET_COUNTER_ENABLED_Msk 0xFFFFFFFFUL
+/* TCPWM.CMD_CAPTURE */
+#define TCPWM_CMD_CAPTURE_COUNTER_CAPTURE_Pos 0UL
+#define TCPWM_CMD_CAPTURE_COUNTER_CAPTURE_Msk 0xFFFFFFFFUL
+/* TCPWM.CMD_RELOAD */
+#define TCPWM_CMD_RELOAD_COUNTER_RELOAD_Pos 0UL
+#define TCPWM_CMD_RELOAD_COUNTER_RELOAD_Msk 0xFFFFFFFFUL
+/* TCPWM.CMD_STOP */
+#define TCPWM_CMD_STOP_COUNTER_STOP_Pos 0UL
+#define TCPWM_CMD_STOP_COUNTER_STOP_Msk 0xFFFFFFFFUL
+/* TCPWM.CMD_START */
+#define TCPWM_CMD_START_COUNTER_START_Pos 0UL
+#define TCPWM_CMD_START_COUNTER_START_Msk 0xFFFFFFFFUL
+/* TCPWM.INTR_CAUSE */
+#define TCPWM_INTR_CAUSE_COUNTER_INT_Pos 0UL
+#define TCPWM_INTR_CAUSE_COUNTER_INT_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_TCPWM_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_udb.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_udb.h
new file mode 100644
index 0000000000..6748dd1120
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_udb.h
@@ -0,0 +1,2035 @@
+/***************************************************************************//**
+* \file cyip_udb.h
+*
+* \brief
+* UDB IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_UDB_H_
+#define _CYIP_UDB_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* UDB
+*******************************************************************************/
+
+#define UDB_WRKONE_SECTION_SIZE 0x00000800UL
+#define UDB_WRKMULT_SECTION_SIZE 0x00001000UL
+#define UDB_UDBPAIR_UDBSNG_SECTION_SIZE 0x00000080UL
+#define UDB_UDBPAIR_ROUTE_SECTION_SIZE 0x00000100UL
+#define UDB_UDBPAIR_SECTION_SIZE 0x00000200UL
+#define UDB_DSI_SECTION_SIZE 0x00000080UL
+#define UDB_PA_SECTION_SIZE 0x00000040UL
+#define UDB_BCTL_SECTION_SIZE 0x00000080UL
+#define UDB_UDBIF_SECTION_SIZE 0x00000020UL
+#define UDB_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief UDB Working Registers (2 registers from one UDB at a time) (UDB_WRKONE)
+ */
+typedef struct {
+ __IOM uint32_t A[64]; /*!< 0x00000000 Accumulator Registers {A1,A0} */
+ __IOM uint32_t D[64]; /*!< 0x00000100 Data Registers {D1,D0} */
+ __IOM uint32_t F[64]; /*!< 0x00000200 FIFOs {F1,F0} */
+ __IOM uint32_t CTL_ST[64]; /*!< 0x00000300 Status and Control Registers {CTL,ST} */
+ __IOM uint32_t ACTL_MSK[64]; /*!< 0x00000400 Mask and Auxiliary Control Registers {ACTL,MSK} */
+ __IM uint32_t MC[64]; /*!< 0x00000500 PLD Macrocell Read Registers {00,MC} */
+ __IM uint32_t RESERVED[128];
+} UDB_WRKONE_V1_Type; /*!< Size = 2048 (0x800) */
+
+/**
+ * \brief UDB Working Registers (1 register from multiple UDBs at a time) (UDB_WRKMULT)
+ */
+typedef struct {
+ __IOM uint32_t A0[64]; /*!< 0x00000000 Accumulator 0 */
+ __IOM uint32_t A1[64]; /*!< 0x00000100 Accumulator 1 */
+ __IOM uint32_t D0[64]; /*!< 0x00000200 Data 0 */
+ __IOM uint32_t D1[64]; /*!< 0x00000300 Data 1 */
+ __IOM uint32_t F0[64]; /*!< 0x00000400 FIFO 0 */
+ __IOM uint32_t F1[64]; /*!< 0x00000500 FIFO 1 */
+ __IM uint32_t ST[64]; /*!< 0x00000600 Status Register */
+ __IOM uint32_t CTL[64]; /*!< 0x00000700 Control Register */
+ __IOM uint32_t MSK[64]; /*!< 0x00000800 Interrupt Mask */
+ __IOM uint32_t ACTL[64]; /*!< 0x00000900 Auxiliary Control */
+ __IM uint32_t MC[64]; /*!< 0x00000A00 PLD Macrocell reading */
+ __IM uint32_t RESERVED[320];
+} UDB_WRKMULT_V1_Type; /*!< Size = 4096 (0x1000) */
+
+/**
+ * \brief Single UDB Configuration (UDB_UDBPAIR_UDBSNG)
+ */
+typedef struct {
+ __IOM uint32_t PLD_IT[12]; /*!< 0x00000000 PLD Input Terms */
+ __IOM uint32_t PLD_ORT0; /*!< 0x00000030 PLD OR Terms */
+ __IOM uint32_t PLD_ORT1; /*!< 0x00000034 PLD OR Terms */
+ __IOM uint32_t PLD_CFG0; /*!< 0x00000038 PLD configuration for Carry Enable, Constant, and XOR feedback */
+ __IOM uint32_t PLD_CFG1; /*!< 0x0000003C PLD configuration for Set / Reset selection, and Bypass control */
+ __IOM uint32_t DPATH_CFG0; /*!< 0x00000040 Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD,
+ D0_LD, D1_LD) */
+ __IOM uint32_t DPATH_CFG1; /*!< 0x00000044 Datapath input and output selections (SCI_MUX, SI_MUX, OUT0
+ thru OUT5) */
+ __IOM uint32_t DPATH_CFG2; /*!< 0x00000048 Datapath output synchronization, ALU mask, compare 0 and 1
+ masks */
+ __IOM uint32_t DPATH_CFG3; /*!< 0x0000004C Datapath mask enables, shift in, carry in, compare, chaining,
+ MSB configs; FIFO, shift and parallel input control */
+ __IOM uint32_t DPATH_CFG4; /*!< 0x00000050 Datapath FIFO and register access configuration control */
+ __IOM uint32_t SC_CFG0; /*!< 0x00000054 SC Mode 0 and 1 control registers; status register input mode;
+ general SC configuration */
+ __IOM uint32_t SC_CFG1; /*!< 0x00000058 SC counter control */
+ __IOM uint32_t RC_CFG0; /*!< 0x0000005C PLD0, PLD1, Datatpath, and SC clock and reset control */
+ __IOM uint32_t RC_CFG1; /*!< 0x00000060 PLD0, PLD1, Datatpath, and SC clock selection, general reset
+ control */
+ __IOM uint32_t DPATH_OPC[4]; /*!< 0x00000064 Datapath opcode configuration */
+ __IM uint32_t RESERVED[3];
+} UDB_UDBPAIR_UDBSNG_V1_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * \brief Routing Configuration for one UDB Pair (UDB_UDBPAIR_ROUTE)
+ */
+typedef struct {
+ __IOM uint32_t TOP_V_BOT; /*!< 0x00000000 Top Vertical Input (TVI) vs Bottom Vertical Input (BVI) muxing */
+ __IOM uint32_t LVO1_V_2; /*!< 0x00000004 Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals */
+ __IOM uint32_t RVO1_V_2; /*!< 0x00000008 Right Vertical Ouput (RVO) 1 vs 2 muxing for certain
+ horizontals */
+ __IOM uint32_t TUI_CFG0; /*!< 0x0000000C Top UDB Input (TUI) selection */
+ __IOM uint32_t TUI_CFG1; /*!< 0x00000010 Top UDB Input (TUI) selection */
+ __IOM uint32_t TUI_CFG2; /*!< 0x00000014 Top UDB Input (TUI) selection */
+ __IOM uint32_t TUI_CFG3; /*!< 0x00000018 Top UDB Input (TUI) selection */
+ __IOM uint32_t TUI_CFG4; /*!< 0x0000001C Top UDB Input (TUI) selection */
+ __IOM uint32_t TUI_CFG5; /*!< 0x00000020 Top UDB Input (TUI) selection */
+ __IOM uint32_t BUI_CFG0; /*!< 0x00000024 Bottom UDB Input (BUI) selection */
+ __IOM uint32_t BUI_CFG1; /*!< 0x00000028 Bottom UDB Input (BUI) selection */
+ __IOM uint32_t BUI_CFG2; /*!< 0x0000002C Bottom UDB Input (BUI) selection */
+ __IOM uint32_t BUI_CFG3; /*!< 0x00000030 Bottom UDB Input (BUI) selection */
+ __IOM uint32_t BUI_CFG4; /*!< 0x00000034 Bottom UDB Input (BUI) selection */
+ __IOM uint32_t BUI_CFG5; /*!< 0x00000038 Bottom UDB Input (BUI) selection */
+ __IOM uint32_t RVO_CFG0; /*!< 0x0000003C Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t RVO_CFG1; /*!< 0x00000040 Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t RVO_CFG2; /*!< 0x00000044 Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t RVO_CFG3; /*!< 0x00000048 Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t LVO_CFG0; /*!< 0x0000004C Left Vertical Ouput (LVO) selection */
+ __IOM uint32_t LVO_CFG1; /*!< 0x00000050 Left Vertical Ouput (LVO) selection */
+ __IOM uint32_t RHO_CFG0; /*!< 0x00000054 Right Horizontal Out (RHO) selection */
+ __IOM uint32_t RHO_CFG1; /*!< 0x00000058 Right Horizontal Out (RHO) selection */
+ __IOM uint32_t RHO_CFG2; /*!< 0x0000005C Right Horizontal Out (RHO) selection */
+ __IOM uint32_t LHO_CFG0; /*!< 0x00000060 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG1; /*!< 0x00000064 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG2; /*!< 0x00000068 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG3; /*!< 0x0000006C Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG4; /*!< 0x00000070 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG5; /*!< 0x00000074 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG6; /*!< 0x00000078 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG7; /*!< 0x0000007C Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG8; /*!< 0x00000080 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG9; /*!< 0x00000084 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG10; /*!< 0x00000088 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG11; /*!< 0x0000008C Left Horizontal Out (LHO) selection */
+ __IM uint32_t RESERVED[28];
+} UDB_UDBPAIR_ROUTE_V1_Type; /*!< Size = 256 (0x100) */
+
+/**
+ * \brief UDB Pair Configuration (up to 32 Pairs) (UDB_UDBPAIR)
+ */
+typedef struct {
+ UDB_UDBPAIR_UDBSNG_V1_Type UDBSNG[2]; /*!< 0x00000000 Single UDB Configuration */
+ UDB_UDBPAIR_ROUTE_V1_Type ROUTE; /*!< 0x00000100 Routing Configuration for one UDB Pair */
+} UDB_UDBPAIR_V1_Type; /*!< Size = 512 (0x200) */
+
+/**
+ * \brief DSI Configuration (up to 32 DSI) (UDB_DSI)
+ */
+typedef struct {
+ __IOM uint32_t LVO1_V_2; /*!< 0x00000000 Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals */
+ __IOM uint32_t RVO1_V_2; /*!< 0x00000004 Right Vertical Ouput (RVO) 1 vs 2 muxing for certain
+ horizontals */
+ __IOM uint32_t DOP_CFG0; /*!< 0x00000008 DSI Out Pair (DOP) selection */
+ __IOM uint32_t DOP_CFG1; /*!< 0x0000000C DSI Out Pair (DOP) selection */
+ __IOM uint32_t DOP_CFG2; /*!< 0x00000010 DSI Out Pair (DOP) selection */
+ __IOM uint32_t DOP_CFG3; /*!< 0x00000014 DSI Out Pair (DOP) selection */
+ __IOM uint32_t DOT_CFG0; /*!< 0x00000018 DSI Out Triplet (DOT) selection */
+ __IOM uint32_t DOT_CFG1; /*!< 0x0000001C DSI Out Triplet (DOT) selection */
+ __IOM uint32_t DOT_CFG2; /*!< 0x00000020 DSI Out Triplet (DOT) selection */
+ __IOM uint32_t DOT_CFG3; /*!< 0x00000024 DSI Out Triplet (DOT) selection */
+ __IOM uint32_t RVO_CFG0; /*!< 0x00000028 Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t RVO_CFG1; /*!< 0x0000002C Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t RVO_CFG2; /*!< 0x00000030 Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t RVO_CFG3; /*!< 0x00000034 Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t LVO_CFG0; /*!< 0x00000038 Left Vertical Ouput (LVO) selection */
+ __IOM uint32_t LVO_CFG1; /*!< 0x0000003C Left Vertical Ouput (LVO) selection */
+ __IOM uint32_t RHO_CFG0; /*!< 0x00000040 Right Horizontal Out (RHO) selection */
+ __IOM uint32_t RHO_CFG1; /*!< 0x00000044 Right Horizontal Out (RHO) selection */
+ __IOM uint32_t RHO_CFG2; /*!< 0x00000048 Right Horizontal Out (RHO) selection */
+ __IOM uint32_t LHO_CFG0; /*!< 0x0000004C Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG1; /*!< 0x00000050 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG2; /*!< 0x00000054 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG3; /*!< 0x00000058 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG4; /*!< 0x0000005C Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG5; /*!< 0x00000060 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG6; /*!< 0x00000064 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG7; /*!< 0x00000068 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG8; /*!< 0x0000006C Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG9; /*!< 0x00000070 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG10; /*!< 0x00000074 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG11; /*!< 0x00000078 Left Horizontal Out (LHO) selection */
+ __IM uint32_t RESERVED;
+} UDB_DSI_V1_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * \brief Port Adapter Configuration (up to 32 PA) (UDB_PA)
+ */
+typedef struct {
+ __IOM uint32_t CFG0; /*!< 0x00000000 PA Data In Clock Control Register */
+ __IOM uint32_t CFG1; /*!< 0x00000004 PA Data Out Clock Control Register */
+ __IOM uint32_t CFG2; /*!< 0x00000008 PA Clock Select Register */
+ __IOM uint32_t CFG3; /*!< 0x0000000C PA Reset Select Register */
+ __IOM uint32_t CFG4; /*!< 0x00000010 PA Reset Enable Register */
+ __IOM uint32_t CFG5; /*!< 0x00000014 PA Reset Pin Select Register */
+ __IOM uint32_t CFG6; /*!< 0x00000018 PA Input Data Sync Control Register - Low */
+ __IOM uint32_t CFG7; /*!< 0x0000001C PA Input Data Sync Control Register - High */
+ __IOM uint32_t CFG8; /*!< 0x00000020 PA Output Data Sync Control Register - Low */
+ __IOM uint32_t CFG9; /*!< 0x00000024 PA Output Data Sync Control Register - High */
+ __IOM uint32_t CFG10; /*!< 0x00000028 PA Output Data Select Register - Low */
+ __IOM uint32_t CFG11; /*!< 0x0000002C PA Output Data Select Register - High */
+ __IOM uint32_t CFG12; /*!< 0x00000030 PA OE Select Register - Low */
+ __IOM uint32_t CFG13; /*!< 0x00000034 PA OE Select Register - High */
+ __IOM uint32_t CFG14; /*!< 0x00000038 PA OE Sync Register */
+ __IM uint32_t RESERVED;
+} UDB_PA_V1_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief UDB Array Bank Control (UDB_BCTL)
+ */
+typedef struct {
+ __IOM uint32_t MDCLK_EN; /*!< 0x00000000 Master Digital Clock Enable Register */
+ __IOM uint32_t MBCLK_EN; /*!< 0x00000004 Master clk_peri_app Enable Register */
+ __IOM uint32_t BOTSEL_L; /*!< 0x00000008 Lower Nibble Bottom Digital Clock Select Register */
+ __IOM uint32_t BOTSEL_U; /*!< 0x0000000C Upper Nibble Bottom Digital Clock Select Register */
+ __IOM uint32_t QCLK_EN[16]; /*!< 0x00000010 Quadrant Digital Clock Enable Registers */
+ __IM uint32_t RESERVED[12];
+} UDB_BCTL_V1_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * \brief UDB Subsystem Interface Configuration (UDB_UDBIF)
+ */
+typedef struct {
+ __IOM uint32_t BANK_CTL; /*!< 0x00000000 Bank Control */
+ __IOM uint32_t INT_CLK_CTL; /*!< 0x00000004 Interrupt Clock Control */
+ __IOM uint32_t INT_CFG; /*!< 0x00000008 Interrupt Configuration */
+ __IOM uint32_t TR_CLK_CTL; /*!< 0x0000000C Trigger Clock Control */
+ __IOM uint32_t TR_CFG; /*!< 0x00000010 Trigger Configuration */
+ __IOM uint32_t PRIVATE; /*!< 0x00000014 Internal use only */
+ __IM uint32_t RESERVED[2];
+} UDB_UDBIF_V1_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief Programmable Digital Subsystem (UDB)
+ */
+typedef struct {
+ UDB_WRKONE_V1_Type WRKONE; /*!< 0x00000000 UDB Working Registers (2 registers from one UDB at a time) */
+ __IM uint32_t RESERVED[512];
+ UDB_WRKMULT_V1_Type WRKMULT; /*!< 0x00001000 UDB Working Registers (1 register from multiple UDBs at a time) */
+ UDB_UDBPAIR_V1_Type UDBPAIR[32]; /*!< 0x00002000 UDB Pair Configuration (up to 32 Pairs) */
+ UDB_DSI_V1_Type DSI[32]; /*!< 0x00006000 DSI Configuration (up to 32 DSI) */
+ UDB_PA_V1_Type PA[32]; /*!< 0x00007000 Port Adapter Configuration (up to 32 PA) */
+ UDB_BCTL_V1_Type BCTL; /*!< 0x00007800 UDB Array Bank Control */
+ __IM uint32_t RESERVED1[32];
+ UDB_UDBIF_V1_Type UDBIF; /*!< 0x00007900 UDB Subsystem Interface Configuration */
+} UDB_V1_Type; /*!< Size = 31008 (0x7920) */
+
+
+/* UDB_WRKONE.A */
+#define UDB_WRKONE_A_A0_Pos 0UL
+#define UDB_WRKONE_A_A0_Msk 0xFFUL
+#define UDB_WRKONE_A_A1_Pos 8UL
+#define UDB_WRKONE_A_A1_Msk 0xFF00UL
+/* UDB_WRKONE.D */
+#define UDB_WRKONE_D_D0_Pos 0UL
+#define UDB_WRKONE_D_D0_Msk 0xFFUL
+#define UDB_WRKONE_D_D1_Pos 8UL
+#define UDB_WRKONE_D_D1_Msk 0xFF00UL
+/* UDB_WRKONE.F */
+#define UDB_WRKONE_F_F0_Pos 0UL
+#define UDB_WRKONE_F_F0_Msk 0xFFUL
+#define UDB_WRKONE_F_F1_Pos 8UL
+#define UDB_WRKONE_F_F1_Msk 0xFF00UL
+/* UDB_WRKONE.CTL_ST */
+#define UDB_WRKONE_CTL_ST_ST_Pos 0UL
+#define UDB_WRKONE_CTL_ST_ST_Msk 0xFFUL
+#define UDB_WRKONE_CTL_ST_CTL_Pos 8UL
+#define UDB_WRKONE_CTL_ST_CTL_Msk 0xFF00UL
+/* UDB_WRKONE.ACTL_MSK */
+#define UDB_WRKONE_ACTL_MSK_MSK_Pos 0UL
+#define UDB_WRKONE_ACTL_MSK_MSK_Msk 0x7FUL
+#define UDB_WRKONE_ACTL_MSK_FIFO0_CLR_Pos 8UL
+#define UDB_WRKONE_ACTL_MSK_FIFO0_CLR_Msk 0x100UL
+#define UDB_WRKONE_ACTL_MSK_FIFO1_CLR_Pos 9UL
+#define UDB_WRKONE_ACTL_MSK_FIFO1_CLR_Msk 0x200UL
+#define UDB_WRKONE_ACTL_MSK_FIFO0_LVL_Pos 10UL
+#define UDB_WRKONE_ACTL_MSK_FIFO0_LVL_Msk 0x400UL
+#define UDB_WRKONE_ACTL_MSK_FIFO1_LVL_Pos 11UL
+#define UDB_WRKONE_ACTL_MSK_FIFO1_LVL_Msk 0x800UL
+#define UDB_WRKONE_ACTL_MSK_INT_EN_Pos 12UL
+#define UDB_WRKONE_ACTL_MSK_INT_EN_Msk 0x1000UL
+#define UDB_WRKONE_ACTL_MSK_CNT_START_Pos 13UL
+#define UDB_WRKONE_ACTL_MSK_CNT_START_Msk 0x2000UL
+/* UDB_WRKONE.MC */
+#define UDB_WRKONE_MC_PLD0_MC_Pos 0UL
+#define UDB_WRKONE_MC_PLD0_MC_Msk 0xFUL
+#define UDB_WRKONE_MC_PLD1_MC_Pos 4UL
+#define UDB_WRKONE_MC_PLD1_MC_Msk 0xF0UL
+
+
+/* UDB_WRKMULT.A0 */
+#define UDB_WRKMULT_A0_A0_0_Pos 0UL
+#define UDB_WRKMULT_A0_A0_0_Msk 0xFFUL
+#define UDB_WRKMULT_A0_A0_1_Pos 8UL
+#define UDB_WRKMULT_A0_A0_1_Msk 0xFF00UL
+#define UDB_WRKMULT_A0_A0_2_Pos 16UL
+#define UDB_WRKMULT_A0_A0_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_A0_A0_3_Pos 24UL
+#define UDB_WRKMULT_A0_A0_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.A1 */
+#define UDB_WRKMULT_A1_A1_0_Pos 0UL
+#define UDB_WRKMULT_A1_A1_0_Msk 0xFFUL
+#define UDB_WRKMULT_A1_A1_1_Pos 8UL
+#define UDB_WRKMULT_A1_A1_1_Msk 0xFF00UL
+#define UDB_WRKMULT_A1_A1_2_Pos 16UL
+#define UDB_WRKMULT_A1_A1_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_A1_A1_3_Pos 24UL
+#define UDB_WRKMULT_A1_A1_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.D0 */
+#define UDB_WRKMULT_D0_D0_0_Pos 0UL
+#define UDB_WRKMULT_D0_D0_0_Msk 0xFFUL
+#define UDB_WRKMULT_D0_D0_1_Pos 8UL
+#define UDB_WRKMULT_D0_D0_1_Msk 0xFF00UL
+#define UDB_WRKMULT_D0_D0_2_Pos 16UL
+#define UDB_WRKMULT_D0_D0_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_D0_D0_3_Pos 24UL
+#define UDB_WRKMULT_D0_D0_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.D1 */
+#define UDB_WRKMULT_D1_D1_0_Pos 0UL
+#define UDB_WRKMULT_D1_D1_0_Msk 0xFFUL
+#define UDB_WRKMULT_D1_D1_1_Pos 8UL
+#define UDB_WRKMULT_D1_D1_1_Msk 0xFF00UL
+#define UDB_WRKMULT_D1_D1_2_Pos 16UL
+#define UDB_WRKMULT_D1_D1_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_D1_D1_3_Pos 24UL
+#define UDB_WRKMULT_D1_D1_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.F0 */
+#define UDB_WRKMULT_F0_F0_0_Pos 0UL
+#define UDB_WRKMULT_F0_F0_0_Msk 0xFFUL
+#define UDB_WRKMULT_F0_F0_1_Pos 8UL
+#define UDB_WRKMULT_F0_F0_1_Msk 0xFF00UL
+#define UDB_WRKMULT_F0_F0_2_Pos 16UL
+#define UDB_WRKMULT_F0_F0_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_F0_F0_3_Pos 24UL
+#define UDB_WRKMULT_F0_F0_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.F1 */
+#define UDB_WRKMULT_F1_F1_0_Pos 0UL
+#define UDB_WRKMULT_F1_F1_0_Msk 0xFFUL
+#define UDB_WRKMULT_F1_F1_1_Pos 8UL
+#define UDB_WRKMULT_F1_F1_1_Msk 0xFF00UL
+#define UDB_WRKMULT_F1_F1_2_Pos 16UL
+#define UDB_WRKMULT_F1_F1_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_F1_F1_3_Pos 24UL
+#define UDB_WRKMULT_F1_F1_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.ST */
+#define UDB_WRKMULT_ST_ST_0_Pos 0UL
+#define UDB_WRKMULT_ST_ST_0_Msk 0xFFUL
+#define UDB_WRKMULT_ST_ST_1_Pos 8UL
+#define UDB_WRKMULT_ST_ST_1_Msk 0xFF00UL
+#define UDB_WRKMULT_ST_ST_2_Pos 16UL
+#define UDB_WRKMULT_ST_ST_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_ST_ST_3_Pos 24UL
+#define UDB_WRKMULT_ST_ST_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.CTL */
+#define UDB_WRKMULT_CTL_CTL_0_Pos 0UL
+#define UDB_WRKMULT_CTL_CTL_0_Msk 0xFFUL
+#define UDB_WRKMULT_CTL_CTL_1_Pos 8UL
+#define UDB_WRKMULT_CTL_CTL_1_Msk 0xFF00UL
+#define UDB_WRKMULT_CTL_CTL_2_Pos 16UL
+#define UDB_WRKMULT_CTL_CTL_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_CTL_CTL_3_Pos 24UL
+#define UDB_WRKMULT_CTL_CTL_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.MSK */
+#define UDB_WRKMULT_MSK_MSK_0_Pos 0UL
+#define UDB_WRKMULT_MSK_MSK_0_Msk 0x7FUL
+#define UDB_WRKMULT_MSK_MSK_1_Pos 8UL
+#define UDB_WRKMULT_MSK_MSK_1_Msk 0x7F00UL
+#define UDB_WRKMULT_MSK_MSK_2_Pos 16UL
+#define UDB_WRKMULT_MSK_MSK_2_Msk 0x7F0000UL
+#define UDB_WRKMULT_MSK_MSK_3_Pos 24UL
+#define UDB_WRKMULT_MSK_MSK_3_Msk 0x7F000000UL
+/* UDB_WRKMULT.ACTL */
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_0_Pos 0UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_0_Msk 0x1UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_0_Pos 1UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_0_Msk 0x2UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_0_Pos 2UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_0_Msk 0x4UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_0_Pos 3UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_0_Msk 0x8UL
+#define UDB_WRKMULT_ACTL_INT_EN_0_Pos 4UL
+#define UDB_WRKMULT_ACTL_INT_EN_0_Msk 0x10UL
+#define UDB_WRKMULT_ACTL_CNT_START_0_Pos 5UL
+#define UDB_WRKMULT_ACTL_CNT_START_0_Msk 0x20UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_1_Pos 8UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_1_Msk 0x100UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_1_Pos 9UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_1_Msk 0x200UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_1_Pos 10UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_1_Msk 0x400UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_1_Pos 11UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_1_Msk 0x800UL
+#define UDB_WRKMULT_ACTL_INT_EN_1_Pos 12UL
+#define UDB_WRKMULT_ACTL_INT_EN_1_Msk 0x1000UL
+#define UDB_WRKMULT_ACTL_CNT_START_1_Pos 13UL
+#define UDB_WRKMULT_ACTL_CNT_START_1_Msk 0x2000UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_2_Pos 16UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_2_Msk 0x10000UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_2_Pos 17UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_2_Msk 0x20000UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_2_Pos 18UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_2_Msk 0x40000UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_2_Pos 19UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_2_Msk 0x80000UL
+#define UDB_WRKMULT_ACTL_INT_EN_2_Pos 20UL
+#define UDB_WRKMULT_ACTL_INT_EN_2_Msk 0x100000UL
+#define UDB_WRKMULT_ACTL_CNT_START_2_Pos 21UL
+#define UDB_WRKMULT_ACTL_CNT_START_2_Msk 0x200000UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_3_Pos 24UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_3_Msk 0x1000000UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_3_Pos 25UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_3_Msk 0x2000000UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_3_Pos 26UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_3_Msk 0x4000000UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_3_Pos 27UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_3_Msk 0x8000000UL
+#define UDB_WRKMULT_ACTL_INT_EN_3_Pos 28UL
+#define UDB_WRKMULT_ACTL_INT_EN_3_Msk 0x10000000UL
+#define UDB_WRKMULT_ACTL_CNT_START_3_Pos 29UL
+#define UDB_WRKMULT_ACTL_CNT_START_3_Msk 0x20000000UL
+/* UDB_WRKMULT.MC */
+#define UDB_WRKMULT_MC_PLD0_MC_0_Pos 0UL
+#define UDB_WRKMULT_MC_PLD0_MC_0_Msk 0xFUL
+#define UDB_WRKMULT_MC_PLD1_MC_0_Pos 4UL
+#define UDB_WRKMULT_MC_PLD1_MC_0_Msk 0xF0UL
+#define UDB_WRKMULT_MC_PLD0_MC_1_Pos 8UL
+#define UDB_WRKMULT_MC_PLD0_MC_1_Msk 0xF00UL
+#define UDB_WRKMULT_MC_PLD1_MC_1_Pos 12UL
+#define UDB_WRKMULT_MC_PLD1_MC_1_Msk 0xF000UL
+#define UDB_WRKMULT_MC_PLD0_MC_2_Pos 16UL
+#define UDB_WRKMULT_MC_PLD0_MC_2_Msk 0xF0000UL
+#define UDB_WRKMULT_MC_PLD1_MC_2_Pos 20UL
+#define UDB_WRKMULT_MC_PLD1_MC_2_Msk 0xF00000UL
+#define UDB_WRKMULT_MC_PLD0_MC_3_Pos 24UL
+#define UDB_WRKMULT_MC_PLD0_MC_3_Msk 0xF000000UL
+#define UDB_WRKMULT_MC_PLD1_MC_3_Pos 28UL
+#define UDB_WRKMULT_MC_PLD1_MC_3_Msk 0xF0000000UL
+
+
+/* UDB_UDBPAIR_UDBSNG.PLD_IT */
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT0_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT0_Msk 0x1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT1_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT1_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT2_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT2_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT3_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT3_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT4_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT4_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT5_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT5_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT6_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT6_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT7_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT7_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT0_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT0_Msk 0x100UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT1_Pos 9UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT1_Msk 0x200UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT2_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT2_Msk 0x400UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT3_Pos 11UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT3_Msk 0x800UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT4_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT4_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT5_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT5_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT6_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT6_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT7_Pos 15UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT7_Msk 0x8000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT0_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT0_Msk 0x10000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT1_Pos 17UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT1_Msk 0x20000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT2_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT2_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT3_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT3_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT4_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT4_Msk 0x100000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT5_Pos 21UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT5_Msk 0x200000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT6_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT6_Msk 0x400000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT7_Pos 23UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT7_Msk 0x800000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT0_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT0_Msk 0x1000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT1_Pos 25UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT1_Msk 0x2000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT2_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT2_Msk 0x4000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT3_Pos 27UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT3_Msk 0x8000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT4_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT4_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT5_Pos 29UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT5_Msk 0x20000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT6_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT6_Msk 0x40000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT7_Pos 31UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT7_Msk 0x80000000UL
+/* UDB_UDBPAIR_UDBSNG.PLD_ORT0 */
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT0_T_FOR_OUT0_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT0_T_FOR_OUT0_Msk 0x1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT1_T_FOR_OUT0_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT1_T_FOR_OUT0_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT2_T_FOR_OUT0_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT2_T_FOR_OUT0_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT3_T_FOR_OUT0_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT3_T_FOR_OUT0_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT4_T_FOR_OUT0_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT4_T_FOR_OUT0_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT5_T_FOR_OUT0_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT5_T_FOR_OUT0_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT6_T_FOR_OUT0_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT6_T_FOR_OUT0_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT7_T_FOR_OUT0_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT7_T_FOR_OUT0_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT0_T_FOR_OUT0_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT0_T_FOR_OUT0_Msk 0x100UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT1_T_FOR_OUT0_Pos 9UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT1_T_FOR_OUT0_Msk 0x200UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT2_T_FOR_OUT0_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT2_T_FOR_OUT0_Msk 0x400UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT3_T_FOR_OUT0_Pos 11UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT3_T_FOR_OUT0_Msk 0x800UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT4_T_FOR_OUT0_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT4_T_FOR_OUT0_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT5_T_FOR_OUT0_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT5_T_FOR_OUT0_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT6_T_FOR_OUT0_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT6_T_FOR_OUT0_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT7_T_FOR_OUT0_Pos 15UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT7_T_FOR_OUT0_Msk 0x8000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT0_T_FOR_OUT1_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT0_T_FOR_OUT1_Msk 0x10000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT1_T_FOR_OUT1_Pos 17UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT1_T_FOR_OUT1_Msk 0x20000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT2_T_FOR_OUT1_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT2_T_FOR_OUT1_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT3_T_FOR_OUT1_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT3_T_FOR_OUT1_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT4_T_FOR_OUT1_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT4_T_FOR_OUT1_Msk 0x100000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT5_T_FOR_OUT1_Pos 21UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT5_T_FOR_OUT1_Msk 0x200000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT6_T_FOR_OUT1_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT6_T_FOR_OUT1_Msk 0x400000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT7_T_FOR_OUT1_Pos 23UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT7_T_FOR_OUT1_Msk 0x800000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT0_T_FOR_OUT1_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT0_T_FOR_OUT1_Msk 0x1000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT1_T_FOR_OUT1_Pos 25UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT1_T_FOR_OUT1_Msk 0x2000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT2_T_FOR_OUT1_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT2_T_FOR_OUT1_Msk 0x4000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT3_T_FOR_OUT1_Pos 27UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT3_T_FOR_OUT1_Msk 0x8000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT4_T_FOR_OUT1_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT4_T_FOR_OUT1_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT5_T_FOR_OUT1_Pos 29UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT5_T_FOR_OUT1_Msk 0x20000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT6_T_FOR_OUT1_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT6_T_FOR_OUT1_Msk 0x40000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT7_T_FOR_OUT1_Pos 31UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT7_T_FOR_OUT1_Msk 0x80000000UL
+/* UDB_UDBPAIR_UDBSNG.PLD_ORT1 */
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT0_T_FOR_OUT2_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT0_T_FOR_OUT2_Msk 0x1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT1_T_FOR_OUT2_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT1_T_FOR_OUT2_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT2_T_FOR_OUT2_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT2_T_FOR_OUT2_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT3_T_FOR_OUT2_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT3_T_FOR_OUT2_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT4_T_FOR_OUT2_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT4_T_FOR_OUT2_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT5_T_FOR_OUT2_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT5_T_FOR_OUT2_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT6_T_FOR_OUT2_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT6_T_FOR_OUT2_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT7_T_FOR_OUT2_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT7_T_FOR_OUT2_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT0_T_FOR_OUT2_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT0_T_FOR_OUT2_Msk 0x100UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT1_T_FOR_OUT2_Pos 9UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT1_T_FOR_OUT2_Msk 0x200UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT2_T_FOR_OUT2_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT2_T_FOR_OUT2_Msk 0x400UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT3_T_FOR_OUT2_Pos 11UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT3_T_FOR_OUT2_Msk 0x800UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT4_T_FOR_OUT2_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT4_T_FOR_OUT2_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT5_T_FOR_OUT2_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT5_T_FOR_OUT2_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT6_T_FOR_OUT2_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT6_T_FOR_OUT2_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT7_T_FOR_OUT2_Pos 15UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT7_T_FOR_OUT2_Msk 0x8000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT0_T_FOR_OUT3_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT0_T_FOR_OUT3_Msk 0x10000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT1_T_FOR_OUT3_Pos 17UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT1_T_FOR_OUT3_Msk 0x20000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT2_T_FOR_OUT3_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT2_T_FOR_OUT3_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT3_T_FOR_OUT3_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT3_T_FOR_OUT3_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT4_T_FOR_OUT3_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT4_T_FOR_OUT3_Msk 0x100000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT5_T_FOR_OUT3_Pos 21UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT5_T_FOR_OUT3_Msk 0x200000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT6_T_FOR_OUT3_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT6_T_FOR_OUT3_Msk 0x400000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT7_T_FOR_OUT3_Pos 23UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT7_T_FOR_OUT3_Msk 0x800000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT0_T_FOR_OUT3_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT0_T_FOR_OUT3_Msk 0x1000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT1_T_FOR_OUT3_Pos 25UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT1_T_FOR_OUT3_Msk 0x2000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT2_T_FOR_OUT3_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT2_T_FOR_OUT3_Msk 0x4000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT3_T_FOR_OUT3_Pos 27UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT3_T_FOR_OUT3_Msk 0x8000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT4_T_FOR_OUT3_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT4_T_FOR_OUT3_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT5_T_FOR_OUT3_Pos 29UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT5_T_FOR_OUT3_Msk 0x20000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT6_T_FOR_OUT3_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT6_T_FOR_OUT3_Msk 0x40000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT7_T_FOR_OUT3_Pos 31UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT7_T_FOR_OUT3_Msk 0x80000000UL
+/* UDB_UDBPAIR_UDBSNG.PLD_CFG0 */
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_CEN_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_CEN_Msk 0x1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_DFF_C_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_DFF_C_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_CEN_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_CEN_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_DFF_C_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_DFF_C_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_CEN_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_CEN_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_DFF_C_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_DFF_C_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_CEN_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_CEN_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_DFF_C_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_DFF_C_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_CEN_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_CEN_Msk 0x100UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_DFF_C_Pos 9UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_DFF_C_Msk 0x200UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_CEN_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_CEN_Msk 0x400UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_DFF_C_Pos 11UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_DFF_C_Msk 0x800UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_CEN_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_CEN_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_DFF_C_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_DFF_C_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_CEN_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_CEN_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_DFF_C_Pos 15UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_DFF_C_Msk 0x8000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_XORFB_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_XORFB_Msk 0x30000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_XORFB_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_XORFB_Msk 0xC0000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_XORFB_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_XORFB_Msk 0x300000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_XORFB_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_XORFB_Msk 0xC00000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_XORFB_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_XORFB_Msk 0x3000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_XORFB_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_XORFB_Msk 0xC000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_XORFB_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_XORFB_Msk 0x30000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_XORFB_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_XORFB_Msk 0xC0000000UL
+/* UDB_UDBPAIR_UDBSNG.PLD_CFG1 */
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_SET_SEL_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_SET_SEL_Msk 0x1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_RESET_SEL_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_RESET_SEL_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_SET_SEL_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_SET_SEL_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_RESET_SEL_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_RESET_SEL_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_SET_SEL_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_SET_SEL_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_RESET_SEL_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_RESET_SEL_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_SET_SEL_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_SET_SEL_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_RESET_SEL_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_RESET_SEL_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_SET_SEL_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_SET_SEL_Msk 0x100UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_RESET_SEL_Pos 9UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_RESET_SEL_Msk 0x200UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_SET_SEL_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_SET_SEL_Msk 0x400UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_RESET_SEL_Pos 11UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_RESET_SEL_Msk 0x800UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_SET_SEL_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_SET_SEL_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_RESET_SEL_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_RESET_SEL_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_SET_SEL_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_SET_SEL_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_RESET_SEL_Pos 15UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_RESET_SEL_Msk 0x8000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_BYPASS_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_BYPASS_Msk 0x10000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_BYPASS_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_BYPASS_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_BYPASS_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_BYPASS_Msk 0x100000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_BYPASS_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_BYPASS_Msk 0x400000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_BYPASS_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_BYPASS_Msk 0x1000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_BYPASS_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_BYPASS_Msk 0x4000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_BYPASS_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_BYPASS_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_BYPASS_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_BYPASS_Msk 0x40000000UL
+/* UDB_UDBPAIR_UDBSNG.DPATH_CFG0 */
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD0_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD0_Msk 0x7UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD1_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD1_Msk 0x70UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD2_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD2_Msk 0x700UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS0_Pos 11UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS0_Msk 0x800UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS1_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS1_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS2_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS2_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS3_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS3_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS4_Pos 15UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS4_Msk 0x8000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_F0_LD_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_F0_LD_Msk 0x70000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS5_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS5_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_F1_LD_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_F1_LD_Msk 0x700000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_D0_LD_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_D0_LD_Msk 0x7000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_D1_LD_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_D1_LD_Msk 0x70000000UL
+/* UDB_UDBPAIR_UDBSNG.DPATH_CFG1 */
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_SI_MUX_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_SI_MUX_Msk 0x7UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_CI_MUX_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_CI_MUX_Msk 0x70UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT0_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT0_Msk 0xF00UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT1_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT1_Msk 0xF000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT2_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT2_Msk 0xF0000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT3_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT3_Msk 0xF00000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT4_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT4_Msk 0xF000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT5_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT5_Msk 0xF0000000UL
+/* UDB_UDBPAIR_UDBSNG.DPATH_CFG2 */
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_OUT_SYNC_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_OUT_SYNC_Msk 0x3FUL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_AMASK_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_AMASK_Msk 0xFF00UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_CMASK0_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_CMASK0_Msk 0xFF0000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_CMASK1_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_CMASK1_Msk 0xFF000000UL
+/* UDB_UDBPAIR_UDBSNG.DPATH_CFG3 */
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SI_SELA_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SI_SELA_Msk 0x3UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SI_SELB_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SI_SELB_Msk 0xCUL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_DEF_SI_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_DEF_SI_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_AMASK_EN_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_AMASK_EN_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMASK0_EN_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMASK0_EN_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMASK1_EN_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMASK1_EN_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CI_SELA_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CI_SELA_Msk 0x300UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CI_SELB_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CI_SELB_Msk 0xC00UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMP_SELA_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMP_SELA_Msk 0x3000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMP_SELB_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMP_SELB_Msk 0xC000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN0_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN0_Msk 0x10000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN1_Pos 17UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN1_Msk 0x20000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN_FB_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN_FB_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN_CMSB_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN_CMSB_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_SEL_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_SEL_Msk 0x700000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_EN_Pos 23UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_EN_Msk 0x800000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_F0_INSEL_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_F0_INSEL_Msk 0x3000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_F1_INSEL_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_F1_INSEL_Msk 0xC000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_SI_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_SI_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_PI_DYN_Pos 29UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_PI_DYN_Msk 0x20000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SHIFT_SEL_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SHIFT_SEL_Msk 0x40000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_PI_SEL_Pos 31UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_PI_SEL_Msk 0x80000000UL
+/* UDB_UDBPAIR_UDBSNG.DPATH_CFG4 */
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_EXT_CRCPRS_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_EXT_CRCPRS_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_ASYNC_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_ASYNC_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_EDGE_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_EDGE_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_CAP_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_CAP_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_FAST_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_FAST_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F0_CK_INV_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F0_CK_INV_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F1_CK_INV_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F1_CK_INV_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F0_DYN_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F0_DYN_Msk 0x100UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F1_DYN_Pos 9UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F1_DYN_Msk 0x200UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_ADD_SYNC_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_ADD_SYNC_Msk 0x1000UL
+/* UDB_UDBPAIR_UDBSNG.SC_CFG0 */
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_CTL_MD0_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_CTL_MD0_Msk 0xFFUL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_CTL_MD1_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_CTL_MD1_Msk 0xFF00UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_STAT_MD_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_STAT_MD_Msk 0xFF0000UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_OUT_CTL_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_OUT_CTL_Msk 0x3000000UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_INT_MD_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_INT_MD_Msk 0x4000000UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_SYNC_MD_Pos 27UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_SYNC_MD_Msk 0x8000000UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_EXT_RES_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_EXT_RES_Msk 0x10000000UL
+/* UDB_UDBPAIR_UDBSNG.SC_CFG1 */
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_CNT_LD_SEL_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_CNT_LD_SEL_Msk 0x3UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_CNT_EN_SEL_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_CNT_EN_SEL_Msk 0xCUL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ROUTE_LD_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ROUTE_LD_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ROUTE_EN_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ROUTE_EN_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ALT_CNT_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ALT_CNT_Msk 0x40UL
+/* UDB_UDBPAIR_UDBSNG.RC_CFG0 */
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_SEL_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_SEL_Msk 0x3UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_MODE_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_MODE_Msk 0xCUL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_INV_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_INV_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_INV_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_INV_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_RES_SEL0_OR_FRES_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_RES_SEL0_OR_FRES_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_RES_SEL1_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_RES_SEL1_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_SEL_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_SEL_Msk 0x300UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_MODE_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_MODE_Msk 0xC00UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_INV_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_INV_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_INV_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_INV_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_RES_SEL0_OR_FRES_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_RES_SEL0_OR_FRES_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_SEL_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_SEL_Msk 0x30000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_MODE_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_MODE_Msk 0xC0000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_INV_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_INV_Msk 0x100000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_INV_Pos 21UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_INV_Msk 0x200000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_RES_SEL0_OR_FRES_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_RES_SEL0_OR_FRES_Msk 0x400000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_RES_SEL1_Pos 23UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_RES_SEL1_Msk 0x800000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_SEL_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_SEL_Msk 0x3000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_MODE_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_MODE_Msk 0xC000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_INV_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_INV_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_INV_Pos 29UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_INV_Msk 0x20000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_RES_SEL0_OR_FRES_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_RES_SEL0_OR_FRES_Msk 0x40000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_RES_SEL1_Pos 31UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_RES_SEL1_Msk 0x80000000UL
+/* UDB_UDBPAIR_UDBSNG.RC_CFG1 */
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD0_CK_SEL_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD0_CK_SEL_Msk 0xFUL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD1_CK_SEL_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD1_CK_SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_DP_CK_SEL_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_DP_CK_SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_SC_CK_SEL_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_SC_CK_SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_RES_SEL_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_RES_SEL_Msk 0x30000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_RES_POL_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_RES_POL_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_CNTCTL_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_CNTCTL_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_DP_RES_POL_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_DP_RES_POL_Msk 0x400000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_SC_RES_POL_Pos 23UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_SC_RES_POL_Msk 0x800000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_ALT_RES_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_ALT_RES_Msk 0x1000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EXT_SYNC_Pos 25UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EXT_SYNC_Msk 0x2000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_STAT_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_STAT_Msk 0x4000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_DP_Pos 27UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_DP_Msk 0x8000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EXT_CK_SEL_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EXT_CK_SEL_Msk 0x30000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD0_RES_POL_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD0_RES_POL_Msk 0x40000000UL
+/* UDB_UDBPAIR_UDBSNG.DPATH_OPC */
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CMP_SEL_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CMP_SEL_Msk 0x1UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SI_SEL_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SI_SEL_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CI_SEL_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CI_SEL_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CFB_EN_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CFB_EN_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_A1_WR_SRC_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_A1_WR_SRC_Msk 0x30UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_A0_WR_SRC_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_A0_WR_SRC_Msk 0xC0UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SHIFT_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SHIFT_Msk 0x300UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SRC_B_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SRC_B_Msk 0xC00UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SRC_A_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SRC_A_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_FUNC_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_FUNC_Msk 0xE000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CMP_SEL_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CMP_SEL_Msk 0x10000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SI_SEL_Pos 17UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SI_SEL_Msk 0x20000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CI_SEL_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CI_SEL_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CFB_EN_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CFB_EN_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_A1_WR_SRC_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_A1_WR_SRC_Msk 0x300000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_A0_WR_SRC_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_A0_WR_SRC_Msk 0xC00000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SHIFT_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SHIFT_Msk 0x3000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SRC_B_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SRC_B_Msk 0xC000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SRC_A_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SRC_A_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_FUNC_Pos 29UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_FUNC_Msk 0xE0000000UL
+
+
+/* UDB_UDBPAIR_ROUTE.TOP_V_BOT */
+#define UDB_UDBPAIR_ROUTE_TOP_V_BOT_TOP_V_BOT_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TOP_V_BOT_TOP_V_BOT_Msk 0xFFFFFFFFUL
+/* UDB_UDBPAIR_ROUTE.LVO1_V_2 */
+#define UDB_UDBPAIR_ROUTE_LVO1_V_2_LVO1_V_2_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LVO1_V_2_LVO1_V_2_Msk 0xFFFFFFFFUL
+/* UDB_UDBPAIR_ROUTE.RVO1_V_2 */
+#define UDB_UDBPAIR_ROUTE_RVO1_V_2_RVO1_V_2_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RVO1_V_2_RVO1_V_2_Msk 0xFFFFFFFFUL
+/* UDB_UDBPAIR_ROUTE.TUI_CFG0 */
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI0SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI0SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI1SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI1SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI2SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI2SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI3SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI3SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI4SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI4SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI5SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI5SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI6SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI6SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI7SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI7SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.TUI_CFG1 */
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI8SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI8SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI9SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI9SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI10SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI10SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI11SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI11SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI12SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI12SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI13SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI13SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI14SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI14SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI15SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI15SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.TUI_CFG2 */
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI16SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI16SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI17SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI17SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI18SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI18SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI19SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI19SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI20SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI20SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI21SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI21SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI22SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI22SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI23SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI23SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.TUI_CFG3 */
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI24SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI24SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI25SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI25SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI26SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI26SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI27SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI27SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI28SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI28SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI29SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI29SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI30SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI30SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI31SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI31SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.TUI_CFG4 */
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI32SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI32SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI33SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI33SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI34SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI34SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI35SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI35SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI36SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI36SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI37SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI37SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI38SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI38SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI39SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI39SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.TUI_CFG5 */
+#define UDB_UDBPAIR_ROUTE_TUI_CFG5_TUI40SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG5_TUI40SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG5_TUI41SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG5_TUI41SEL_Msk 0xF0UL
+/* UDB_UDBPAIR_ROUTE.BUI_CFG0 */
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI0SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI0SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI1SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI1SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI2SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI2SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI3SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI3SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI4SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI4SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI5SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI5SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI6SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI6SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI7SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI7SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.BUI_CFG1 */
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI8SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI8SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI9SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI9SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI10SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI10SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI11SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI11SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI12SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI12SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI13SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI13SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI14SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI14SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI15SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI15SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.BUI_CFG2 */
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI16SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI16SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI17SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI17SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI18SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI18SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI19SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI19SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI20SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI20SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI21SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI21SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI22SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI22SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI23SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI23SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.BUI_CFG3 */
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI24SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI24SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI25SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI25SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI26SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI26SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI27SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI27SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI28SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI28SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI29SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI29SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI30SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI30SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI31SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI31SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.BUI_CFG4 */
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI32SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI32SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI33SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI33SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI34SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI34SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI35SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI35SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI36SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI36SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI37SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI37SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI38SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI38SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI39SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI39SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.BUI_CFG5 */
+#define UDB_UDBPAIR_ROUTE_BUI_CFG5_BUI40SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG5_BUI40SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG5_BUI41SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG5_BUI41SEL_Msk 0xF0UL
+/* UDB_UDBPAIR_ROUTE.RVO_CFG0 */
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO0SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO0SEL_Msk 0x1FUL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO1SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO1SEL_Msk 0x1F00UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO2SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO2SEL_Msk 0x1F0000UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO3SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO3SEL_Msk 0x1F000000UL
+/* UDB_UDBPAIR_ROUTE.RVO_CFG1 */
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO4SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO4SEL_Msk 0x1FUL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO5SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO5SEL_Msk 0x1F00UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO6SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO6SEL_Msk 0x1F0000UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO7SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO7SEL_Msk 0x1F000000UL
+/* UDB_UDBPAIR_ROUTE.RVO_CFG2 */
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO8SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO8SEL_Msk 0x1FUL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO9SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO9SEL_Msk 0x1F00UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO10SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO10SEL_Msk 0x1F0000UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO11SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO11SEL_Msk 0x1F000000UL
+/* UDB_UDBPAIR_ROUTE.RVO_CFG3 */
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO12SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO12SEL_Msk 0x1FUL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO13SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO13SEL_Msk 0x1F00UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO14SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO14SEL_Msk 0x1F0000UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO15SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO15SEL_Msk 0x1F000000UL
+/* UDB_UDBPAIR_ROUTE.LVO_CFG0 */
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO0SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO0SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO1SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO1SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO2SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO2SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO3SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO3SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO4SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO4SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO5SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO5SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO6SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO6SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO7SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO7SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LVO_CFG1 */
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO8SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO8SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO9SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO9SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO10SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO10SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO11SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO11SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO12SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO12SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO13SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO13SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO14SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO14SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO15SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO15SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.RHO_CFG0 */
+#define UDB_UDBPAIR_ROUTE_RHO_CFG0_RHOSEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RHO_CFG0_RHOSEL_Msk 0xFFFFFFFFUL
+/* UDB_UDBPAIR_ROUTE.RHO_CFG1 */
+#define UDB_UDBPAIR_ROUTE_RHO_CFG1_RHOSEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RHO_CFG1_RHOSEL_Msk 0xFFFFFFFFUL
+/* UDB_UDBPAIR_ROUTE.RHO_CFG2 */
+#define UDB_UDBPAIR_ROUTE_RHO_CFG2_RHOSEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RHO_CFG2_RHOSEL_Msk 0xFFFFFFFFUL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG0 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO0SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO0SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO1SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO1SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO2SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO2SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO3SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO3SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO4SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO4SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO5SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO5SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO6SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO6SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO7SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO7SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG1 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO8SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO8SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO9SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO9SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO10SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO10SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO11SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO11SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO12SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO12SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO13SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO13SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO14SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO14SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO15SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO15SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG2 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO16SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO16SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO17SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO17SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO18SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO18SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO19SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO19SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO20SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO20SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO21SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO21SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO22SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO22SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO23SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO23SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG3 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO24SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO24SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO25SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO25SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO26SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO26SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO27SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO27SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO28SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO28SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO29SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO29SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO30SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO30SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO31SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO31SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG4 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO32SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO32SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO33SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO33SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO34SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO34SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO35SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO35SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO36SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO36SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO37SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO37SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO38SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO38SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO39SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO39SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG5 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO40SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO40SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO41SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO41SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO42SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO42SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO43SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO43SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO44SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO44SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO45SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO45SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO46SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO46SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO47SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO47SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG6 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO48SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO48SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO49SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO49SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO50SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO50SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO51SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO51SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO52SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO52SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO53SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO53SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO54SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO54SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO55SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO55SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG7 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO56SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO56SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO57SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO57SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO58SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO58SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO59SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO59SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO60SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO60SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO61SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO61SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO62SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO62SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO63SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO63SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG8 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO64SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO64SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO65SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO65SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO66SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO66SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO67SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO67SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO68SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO68SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO69SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO69SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO70SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO70SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO71SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO71SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG9 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO72SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO72SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO73SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO73SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO74SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO74SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO75SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO75SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO76SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO76SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO77SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO77SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO78SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO78SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO79SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO79SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG10 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO80SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO80SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO81SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO81SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO82SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO82SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO83SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO83SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO84SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO84SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO85SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO85SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO86SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO86SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO87SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO87SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG11 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO88SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO88SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO89SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO89SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO90SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO90SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO91SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO91SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO92SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO92SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO93SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO93SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO94SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO94SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO95SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO95SEL_Msk 0xF0000000UL
+
+
+/* UDB_DSI.LVO1_V_2 */
+#define UDB_DSI_LVO1_V_2_LVO1_V_2_Pos 0UL
+#define UDB_DSI_LVO1_V_2_LVO1_V_2_Msk 0xFFFFFFFFUL
+/* UDB_DSI.RVO1_V_2 */
+#define UDB_DSI_RVO1_V_2_RVO1_V_2_Pos 0UL
+#define UDB_DSI_RVO1_V_2_RVO1_V_2_Msk 0xFFFFFFFFUL
+/* UDB_DSI.DOP_CFG0 */
+#define UDB_DSI_DOP_CFG0_DOP0SEL_Pos 0UL
+#define UDB_DSI_DOP_CFG0_DOP0SEL_Msk 0x1FUL
+#define UDB_DSI_DOP_CFG0_DOP1SEL_Pos 8UL
+#define UDB_DSI_DOP_CFG0_DOP1SEL_Msk 0x1F00UL
+#define UDB_DSI_DOP_CFG0_DOP2SEL_Pos 16UL
+#define UDB_DSI_DOP_CFG0_DOP2SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOP_CFG0_DOP3SEL_Pos 24UL
+#define UDB_DSI_DOP_CFG0_DOP3SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOP_CFG1 */
+#define UDB_DSI_DOP_CFG1_DOP4SEL_Pos 0UL
+#define UDB_DSI_DOP_CFG1_DOP4SEL_Msk 0x1FUL
+#define UDB_DSI_DOP_CFG1_DOP5SEL_Pos 8UL
+#define UDB_DSI_DOP_CFG1_DOP5SEL_Msk 0x1F00UL
+#define UDB_DSI_DOP_CFG1_DOP6SEL_Pos 16UL
+#define UDB_DSI_DOP_CFG1_DOP6SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOP_CFG1_DOP7SEL_Pos 24UL
+#define UDB_DSI_DOP_CFG1_DOP7SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOP_CFG2 */
+#define UDB_DSI_DOP_CFG2_DOP8SEL_Pos 0UL
+#define UDB_DSI_DOP_CFG2_DOP8SEL_Msk 0x1FUL
+#define UDB_DSI_DOP_CFG2_DOP9SEL_Pos 8UL
+#define UDB_DSI_DOP_CFG2_DOP9SEL_Msk 0x1F00UL
+#define UDB_DSI_DOP_CFG2_DOP10SEL_Pos 16UL
+#define UDB_DSI_DOP_CFG2_DOP10SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOP_CFG2_DOP11SEL_Pos 24UL
+#define UDB_DSI_DOP_CFG2_DOP11SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOP_CFG3 */
+#define UDB_DSI_DOP_CFG3_DOP12SEL_Pos 0UL
+#define UDB_DSI_DOP_CFG3_DOP12SEL_Msk 0x1FUL
+#define UDB_DSI_DOP_CFG3_DOP13SEL_Pos 8UL
+#define UDB_DSI_DOP_CFG3_DOP13SEL_Msk 0x1F00UL
+#define UDB_DSI_DOP_CFG3_DOP14SEL_Pos 16UL
+#define UDB_DSI_DOP_CFG3_DOP14SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOP_CFG3_DOP15SEL_Pos 24UL
+#define UDB_DSI_DOP_CFG3_DOP15SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOT_CFG0 */
+#define UDB_DSI_DOT_CFG0_DOT0SEL_Pos 0UL
+#define UDB_DSI_DOT_CFG0_DOT0SEL_Msk 0x1FUL
+#define UDB_DSI_DOT_CFG0_DOT1SEL_Pos 8UL
+#define UDB_DSI_DOT_CFG0_DOT1SEL_Msk 0x1F00UL
+#define UDB_DSI_DOT_CFG0_DOT2SEL_Pos 16UL
+#define UDB_DSI_DOT_CFG0_DOT2SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOT_CFG0_DOT3SEL_Pos 24UL
+#define UDB_DSI_DOT_CFG0_DOT3SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOT_CFG1 */
+#define UDB_DSI_DOT_CFG1_DOT4SEL_Pos 0UL
+#define UDB_DSI_DOT_CFG1_DOT4SEL_Msk 0x1FUL
+#define UDB_DSI_DOT_CFG1_DOT5SEL_Pos 8UL
+#define UDB_DSI_DOT_CFG1_DOT5SEL_Msk 0x1F00UL
+#define UDB_DSI_DOT_CFG1_DOT6SEL_Pos 16UL
+#define UDB_DSI_DOT_CFG1_DOT6SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOT_CFG1_DOT7SEL_Pos 24UL
+#define UDB_DSI_DOT_CFG1_DOT7SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOT_CFG2 */
+#define UDB_DSI_DOT_CFG2_DOT8SEL_Pos 0UL
+#define UDB_DSI_DOT_CFG2_DOT8SEL_Msk 0x1FUL
+#define UDB_DSI_DOT_CFG2_DOT9SEL_Pos 8UL
+#define UDB_DSI_DOT_CFG2_DOT9SEL_Msk 0x1F00UL
+#define UDB_DSI_DOT_CFG2_DOT10SEL_Pos 16UL
+#define UDB_DSI_DOT_CFG2_DOT10SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOT_CFG2_DOT11SEL_Pos 24UL
+#define UDB_DSI_DOT_CFG2_DOT11SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOT_CFG3 */
+#define UDB_DSI_DOT_CFG3_DOT12SEL_Pos 0UL
+#define UDB_DSI_DOT_CFG3_DOT12SEL_Msk 0x1FUL
+#define UDB_DSI_DOT_CFG3_DOT13SEL_Pos 8UL
+#define UDB_DSI_DOT_CFG3_DOT13SEL_Msk 0x1F00UL
+#define UDB_DSI_DOT_CFG3_DOT14SEL_Pos 16UL
+#define UDB_DSI_DOT_CFG3_DOT14SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOT_CFG3_DOT15SEL_Pos 24UL
+#define UDB_DSI_DOT_CFG3_DOT15SEL_Msk 0x1F000000UL
+/* UDB_DSI.RVO_CFG0 */
+#define UDB_DSI_RVO_CFG0_RVO0SEL_Pos 0UL
+#define UDB_DSI_RVO_CFG0_RVO0SEL_Msk 0x1FUL
+#define UDB_DSI_RVO_CFG0_RVO1SEL_Pos 8UL
+#define UDB_DSI_RVO_CFG0_RVO1SEL_Msk 0x1F00UL
+#define UDB_DSI_RVO_CFG0_RVO2SEL_Pos 16UL
+#define UDB_DSI_RVO_CFG0_RVO2SEL_Msk 0x1F0000UL
+#define UDB_DSI_RVO_CFG0_RVO3SEL_Pos 24UL
+#define UDB_DSI_RVO_CFG0_RVO3SEL_Msk 0x1F000000UL
+/* UDB_DSI.RVO_CFG1 */
+#define UDB_DSI_RVO_CFG1_RVO4SEL_Pos 0UL
+#define UDB_DSI_RVO_CFG1_RVO4SEL_Msk 0x1FUL
+#define UDB_DSI_RVO_CFG1_RVO5SEL_Pos 8UL
+#define UDB_DSI_RVO_CFG1_RVO5SEL_Msk 0x1F00UL
+#define UDB_DSI_RVO_CFG1_RVO6SEL_Pos 16UL
+#define UDB_DSI_RVO_CFG1_RVO6SEL_Msk 0x1F0000UL
+#define UDB_DSI_RVO_CFG1_RVO7SEL_Pos 24UL
+#define UDB_DSI_RVO_CFG1_RVO7SEL_Msk 0x1F000000UL
+/* UDB_DSI.RVO_CFG2 */
+#define UDB_DSI_RVO_CFG2_RVO8SEL_Pos 0UL
+#define UDB_DSI_RVO_CFG2_RVO8SEL_Msk 0x1FUL
+#define UDB_DSI_RVO_CFG2_RVO9SEL_Pos 8UL
+#define UDB_DSI_RVO_CFG2_RVO9SEL_Msk 0x1F00UL
+#define UDB_DSI_RVO_CFG2_RVO10SEL_Pos 16UL
+#define UDB_DSI_RVO_CFG2_RVO10SEL_Msk 0x1F0000UL
+#define UDB_DSI_RVO_CFG2_RVO11SEL_Pos 24UL
+#define UDB_DSI_RVO_CFG2_RVO11SEL_Msk 0x1F000000UL
+/* UDB_DSI.RVO_CFG3 */
+#define UDB_DSI_RVO_CFG3_RVO12SEL_Pos 0UL
+#define UDB_DSI_RVO_CFG3_RVO12SEL_Msk 0x1FUL
+#define UDB_DSI_RVO_CFG3_RVO13SEL_Pos 8UL
+#define UDB_DSI_RVO_CFG3_RVO13SEL_Msk 0x1F00UL
+#define UDB_DSI_RVO_CFG3_RVO14SEL_Pos 16UL
+#define UDB_DSI_RVO_CFG3_RVO14SEL_Msk 0x1F0000UL
+#define UDB_DSI_RVO_CFG3_RVO15SEL_Pos 24UL
+#define UDB_DSI_RVO_CFG3_RVO15SEL_Msk 0x1F000000UL
+/* UDB_DSI.LVO_CFG0 */
+#define UDB_DSI_LVO_CFG0_LVO0SEL_Pos 0UL
+#define UDB_DSI_LVO_CFG0_LVO0SEL_Msk 0xFUL
+#define UDB_DSI_LVO_CFG0_LVO1SEL_Pos 4UL
+#define UDB_DSI_LVO_CFG0_LVO1SEL_Msk 0xF0UL
+#define UDB_DSI_LVO_CFG0_LVO2SEL_Pos 8UL
+#define UDB_DSI_LVO_CFG0_LVO2SEL_Msk 0xF00UL
+#define UDB_DSI_LVO_CFG0_LVO3SEL_Pos 12UL
+#define UDB_DSI_LVO_CFG0_LVO3SEL_Msk 0xF000UL
+#define UDB_DSI_LVO_CFG0_LVO4SEL_Pos 16UL
+#define UDB_DSI_LVO_CFG0_LVO4SEL_Msk 0xF0000UL
+#define UDB_DSI_LVO_CFG0_LVO5SEL_Pos 20UL
+#define UDB_DSI_LVO_CFG0_LVO5SEL_Msk 0xF00000UL
+#define UDB_DSI_LVO_CFG0_LVO6SEL_Pos 24UL
+#define UDB_DSI_LVO_CFG0_LVO6SEL_Msk 0xF000000UL
+#define UDB_DSI_LVO_CFG0_LVO7SEL_Pos 28UL
+#define UDB_DSI_LVO_CFG0_LVO7SEL_Msk 0xF0000000UL
+/* UDB_DSI.LVO_CFG1 */
+#define UDB_DSI_LVO_CFG1_LVO8SEL_Pos 0UL
+#define UDB_DSI_LVO_CFG1_LVO8SEL_Msk 0xFUL
+#define UDB_DSI_LVO_CFG1_LVO9SEL_Pos 4UL
+#define UDB_DSI_LVO_CFG1_LVO9SEL_Msk 0xF0UL
+#define UDB_DSI_LVO_CFG1_LVO10SEL_Pos 8UL
+#define UDB_DSI_LVO_CFG1_LVO10SEL_Msk 0xF00UL
+#define UDB_DSI_LVO_CFG1_LVO11SEL_Pos 12UL
+#define UDB_DSI_LVO_CFG1_LVO11SEL_Msk 0xF000UL
+#define UDB_DSI_LVO_CFG1_LVO12SEL_Pos 16UL
+#define UDB_DSI_LVO_CFG1_LVO12SEL_Msk 0xF0000UL
+#define UDB_DSI_LVO_CFG1_LVO13SEL_Pos 20UL
+#define UDB_DSI_LVO_CFG1_LVO13SEL_Msk 0xF00000UL
+#define UDB_DSI_LVO_CFG1_LVO14SEL_Pos 24UL
+#define UDB_DSI_LVO_CFG1_LVO14SEL_Msk 0xF000000UL
+#define UDB_DSI_LVO_CFG1_LVO15SEL_Pos 28UL
+#define UDB_DSI_LVO_CFG1_LVO15SEL_Msk 0xF0000000UL
+/* UDB_DSI.RHO_CFG0 */
+#define UDB_DSI_RHO_CFG0_RHOSEL_Pos 0UL
+#define UDB_DSI_RHO_CFG0_RHOSEL_Msk 0xFFFFFFFFUL
+/* UDB_DSI.RHO_CFG1 */
+#define UDB_DSI_RHO_CFG1_RHOSEL_Pos 0UL
+#define UDB_DSI_RHO_CFG1_RHOSEL_Msk 0xFFFFFFFFUL
+/* UDB_DSI.RHO_CFG2 */
+#define UDB_DSI_RHO_CFG2_RHOSEL_Pos 0UL
+#define UDB_DSI_RHO_CFG2_RHOSEL_Msk 0xFFFFFFFFUL
+/* UDB_DSI.LHO_CFG0 */
+#define UDB_DSI_LHO_CFG0_LHO0SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG0_LHO0SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG0_LHO1SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG0_LHO1SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG0_LHO2SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG0_LHO2SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG0_LHO3SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG0_LHO3SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG0_LHO4SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG0_LHO4SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG0_LHO5SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG0_LHO5SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG0_LHO6SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG0_LHO6SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG0_LHO7SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG0_LHO7SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG1 */
+#define UDB_DSI_LHO_CFG1_LHO8SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG1_LHO8SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG1_LHO9SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG1_LHO9SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG1_LHO10SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG1_LHO10SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG1_LHO11SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG1_LHO11SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG1_LHO12SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG1_LHO12SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG1_LHO13SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG1_LHO13SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG1_LHO14SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG1_LHO14SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG1_LHO15SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG1_LHO15SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG2 */
+#define UDB_DSI_LHO_CFG2_LHO16SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG2_LHO16SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG2_LHO17SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG2_LHO17SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG2_LHO18SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG2_LHO18SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG2_LHO19SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG2_LHO19SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG2_LHO20SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG2_LHO20SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG2_LHO21SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG2_LHO21SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG2_LHO22SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG2_LHO22SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG2_LHO23SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG2_LHO23SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG3 */
+#define UDB_DSI_LHO_CFG3_LHO24SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG3_LHO24SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG3_LHO25SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG3_LHO25SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG3_LHO26SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG3_LHO26SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG3_LHO27SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG3_LHO27SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG3_LHO28SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG3_LHO28SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG3_LHO29SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG3_LHO29SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG3_LHO30SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG3_LHO30SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG3_LHO31SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG3_LHO31SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG4 */
+#define UDB_DSI_LHO_CFG4_LHO32SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG4_LHO32SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG4_LHO33SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG4_LHO33SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG4_LHO34SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG4_LHO34SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG4_LHO35SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG4_LHO35SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG4_LHO36SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG4_LHO36SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG4_LHO37SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG4_LHO37SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG4_LHO38SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG4_LHO38SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG4_LHO39SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG4_LHO39SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG5 */
+#define UDB_DSI_LHO_CFG5_LHO40SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG5_LHO40SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG5_LHO41SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG5_LHO41SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG5_LHO42SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG5_LHO42SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG5_LHO43SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG5_LHO43SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG5_LHO44SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG5_LHO44SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG5_LHO45SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG5_LHO45SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG5_LHO46SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG5_LHO46SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG5_LHO47SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG5_LHO47SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG6 */
+#define UDB_DSI_LHO_CFG6_LHO48SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG6_LHO48SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG6_LHO49SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG6_LHO49SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG6_LHO50SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG6_LHO50SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG6_LHO51SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG6_LHO51SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG6_LHO52SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG6_LHO52SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG6_LHO53SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG6_LHO53SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG6_LHO54SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG6_LHO54SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG6_LHO55SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG6_LHO55SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG7 */
+#define UDB_DSI_LHO_CFG7_LHO56SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG7_LHO56SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG7_LHO57SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG7_LHO57SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG7_LHO58SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG7_LHO58SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG7_LHO59SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG7_LHO59SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG7_LHO60SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG7_LHO60SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG7_LHO61SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG7_LHO61SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG7_LHO62SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG7_LHO62SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG7_LHO63SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG7_LHO63SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG8 */
+#define UDB_DSI_LHO_CFG8_LHO64SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG8_LHO64SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG8_LHO65SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG8_LHO65SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG8_LHO66SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG8_LHO66SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG8_LHO67SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG8_LHO67SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG8_LHO68SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG8_LHO68SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG8_LHO69SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG8_LHO69SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG8_LHO70SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG8_LHO70SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG8_LHO71SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG8_LHO71SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG9 */
+#define UDB_DSI_LHO_CFG9_LHO72SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG9_LHO72SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG9_LHO73SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG9_LHO73SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG9_LHO74SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG9_LHO74SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG9_LHO75SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG9_LHO75SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG9_LHO76SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG9_LHO76SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG9_LHO77SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG9_LHO77SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG9_LHO78SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG9_LHO78SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG9_LHO79SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG9_LHO79SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG10 */
+#define UDB_DSI_LHO_CFG10_LHO80SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG10_LHO80SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG10_LHO81SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG10_LHO81SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG10_LHO82SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG10_LHO82SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG10_LHO83SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG10_LHO83SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG10_LHO84SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG10_LHO84SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG10_LHO85SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG10_LHO85SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG10_LHO86SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG10_LHO86SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG10_LHO87SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG10_LHO87SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG11 */
+#define UDB_DSI_LHO_CFG11_LHO88SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG11_LHO88SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG11_LHO89SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG11_LHO89SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG11_LHO90SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG11_LHO90SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG11_LHO91SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG11_LHO91SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG11_LHO92SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG11_LHO92SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG11_LHO93SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG11_LHO93SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG11_LHO94SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG11_LHO94SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG11_LHO95SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG11_LHO95SEL_Msk 0xF0000000UL
+
+
+/* UDB_PA.CFG0 */
+#define UDB_PA_CFG0_CLKIN_EN_SEL_Pos 0UL
+#define UDB_PA_CFG0_CLKIN_EN_SEL_Msk 0x3UL
+#define UDB_PA_CFG0_CLKIN_EN_MODE_Pos 2UL
+#define UDB_PA_CFG0_CLKIN_EN_MODE_Msk 0xCUL
+#define UDB_PA_CFG0_CLKIN_EN_INV_Pos 4UL
+#define UDB_PA_CFG0_CLKIN_EN_INV_Msk 0x10UL
+#define UDB_PA_CFG0_CLKIN_INV_Pos 5UL
+#define UDB_PA_CFG0_CLKIN_INV_Msk 0x20UL
+/* UDB_PA.CFG1 */
+#define UDB_PA_CFG1_CLKOUT_EN_SEL_Pos 0UL
+#define UDB_PA_CFG1_CLKOUT_EN_SEL_Msk 0x3UL
+#define UDB_PA_CFG1_CLKOUT_EN_MODE_Pos 2UL
+#define UDB_PA_CFG1_CLKOUT_EN_MODE_Msk 0xCUL
+#define UDB_PA_CFG1_CLKOUT_EN_INV_Pos 4UL
+#define UDB_PA_CFG1_CLKOUT_EN_INV_Msk 0x10UL
+#define UDB_PA_CFG1_CLKOUT_INV_Pos 5UL
+#define UDB_PA_CFG1_CLKOUT_INV_Msk 0x20UL
+/* UDB_PA.CFG2 */
+#define UDB_PA_CFG2_CLKIN_SEL_Pos 0UL
+#define UDB_PA_CFG2_CLKIN_SEL_Msk 0xFUL
+#define UDB_PA_CFG2_CLKOUT_SEL_Pos 4UL
+#define UDB_PA_CFG2_CLKOUT_SEL_Msk 0xF0UL
+/* UDB_PA.CFG3 */
+#define UDB_PA_CFG3_RES_IN_SEL_Pos 0UL
+#define UDB_PA_CFG3_RES_IN_SEL_Msk 0x3UL
+#define UDB_PA_CFG3_RES_IN_INV_Pos 2UL
+#define UDB_PA_CFG3_RES_IN_INV_Msk 0x4UL
+#define UDB_PA_CFG3_RES_OUT_SEL_Pos 4UL
+#define UDB_PA_CFG3_RES_OUT_SEL_Msk 0x30UL
+#define UDB_PA_CFG3_RES_OUT_INV_Pos 6UL
+#define UDB_PA_CFG3_RES_OUT_INV_Msk 0x40UL
+/* UDB_PA.CFG4 */
+#define UDB_PA_CFG4_RES_IN_EN_Pos 0UL
+#define UDB_PA_CFG4_RES_IN_EN_Msk 0x1UL
+#define UDB_PA_CFG4_RES_OUT_EN_Pos 1UL
+#define UDB_PA_CFG4_RES_OUT_EN_Msk 0x2UL
+#define UDB_PA_CFG4_RES_OE_EN_Pos 2UL
+#define UDB_PA_CFG4_RES_OE_EN_Msk 0x4UL
+/* UDB_PA.CFG5 */
+#define UDB_PA_CFG5_PIN_SEL_Pos 0UL
+#define UDB_PA_CFG5_PIN_SEL_Msk 0x7UL
+/* UDB_PA.CFG6 */
+#define UDB_PA_CFG6_IN_SYNC0_Pos 0UL
+#define UDB_PA_CFG6_IN_SYNC0_Msk 0x3UL
+#define UDB_PA_CFG6_IN_SYNC1_Pos 2UL
+#define UDB_PA_CFG6_IN_SYNC1_Msk 0xCUL
+#define UDB_PA_CFG6_IN_SYNC2_Pos 4UL
+#define UDB_PA_CFG6_IN_SYNC2_Msk 0x30UL
+#define UDB_PA_CFG6_IN_SYNC3_Pos 6UL
+#define UDB_PA_CFG6_IN_SYNC3_Msk 0xC0UL
+/* UDB_PA.CFG7 */
+#define UDB_PA_CFG7_IN_SYNC4_Pos 0UL
+#define UDB_PA_CFG7_IN_SYNC4_Msk 0x3UL
+#define UDB_PA_CFG7_IN_SYNC5_Pos 2UL
+#define UDB_PA_CFG7_IN_SYNC5_Msk 0xCUL
+#define UDB_PA_CFG7_IN_SYNC6_Pos 4UL
+#define UDB_PA_CFG7_IN_SYNC6_Msk 0x30UL
+#define UDB_PA_CFG7_IN_SYNC7_Pos 6UL
+#define UDB_PA_CFG7_IN_SYNC7_Msk 0xC0UL
+/* UDB_PA.CFG8 */
+#define UDB_PA_CFG8_OUT_SYNC0_Pos 0UL
+#define UDB_PA_CFG8_OUT_SYNC0_Msk 0x3UL
+#define UDB_PA_CFG8_OUT_SYNC1_Pos 2UL
+#define UDB_PA_CFG8_OUT_SYNC1_Msk 0xCUL
+#define UDB_PA_CFG8_OUT_SYNC2_Pos 4UL
+#define UDB_PA_CFG8_OUT_SYNC2_Msk 0x30UL
+#define UDB_PA_CFG8_OUT_SYNC3_Pos 6UL
+#define UDB_PA_CFG8_OUT_SYNC3_Msk 0xC0UL
+/* UDB_PA.CFG9 */
+#define UDB_PA_CFG9_OUT_SYNC4_Pos 0UL
+#define UDB_PA_CFG9_OUT_SYNC4_Msk 0x3UL
+#define UDB_PA_CFG9_OUT_SYNC5_Pos 2UL
+#define UDB_PA_CFG9_OUT_SYNC5_Msk 0xCUL
+#define UDB_PA_CFG9_OUT_SYNC6_Pos 4UL
+#define UDB_PA_CFG9_OUT_SYNC6_Msk 0x30UL
+#define UDB_PA_CFG9_OUT_SYNC7_Pos 6UL
+#define UDB_PA_CFG9_OUT_SYNC7_Msk 0xC0UL
+/* UDB_PA.CFG10 */
+#define UDB_PA_CFG10_DATA_SEL0_Pos 0UL
+#define UDB_PA_CFG10_DATA_SEL0_Msk 0x3UL
+#define UDB_PA_CFG10_DATA_SEL1_Pos 2UL
+#define UDB_PA_CFG10_DATA_SEL1_Msk 0xCUL
+#define UDB_PA_CFG10_DATA_SEL2_Pos 4UL
+#define UDB_PA_CFG10_DATA_SEL2_Msk 0x30UL
+#define UDB_PA_CFG10_DATA_SEL3_Pos 6UL
+#define UDB_PA_CFG10_DATA_SEL3_Msk 0xC0UL
+/* UDB_PA.CFG11 */
+#define UDB_PA_CFG11_DATA_SEL4_Pos 0UL
+#define UDB_PA_CFG11_DATA_SEL4_Msk 0x3UL
+#define UDB_PA_CFG11_DATA_SEL5_Pos 2UL
+#define UDB_PA_CFG11_DATA_SEL5_Msk 0xCUL
+#define UDB_PA_CFG11_DATA_SEL6_Pos 4UL
+#define UDB_PA_CFG11_DATA_SEL6_Msk 0x30UL
+#define UDB_PA_CFG11_DATA_SEL7_Pos 6UL
+#define UDB_PA_CFG11_DATA_SEL7_Msk 0xC0UL
+/* UDB_PA.CFG12 */
+#define UDB_PA_CFG12_OE_SEL0_Pos 0UL
+#define UDB_PA_CFG12_OE_SEL0_Msk 0x3UL
+#define UDB_PA_CFG12_OE_SEL1_Pos 2UL
+#define UDB_PA_CFG12_OE_SEL1_Msk 0xCUL
+#define UDB_PA_CFG12_OE_SEL2_Pos 4UL
+#define UDB_PA_CFG12_OE_SEL2_Msk 0x30UL
+#define UDB_PA_CFG12_OE_SEL3_Pos 6UL
+#define UDB_PA_CFG12_OE_SEL3_Msk 0xC0UL
+/* UDB_PA.CFG13 */
+#define UDB_PA_CFG13_OE_SEL4_Pos 0UL
+#define UDB_PA_CFG13_OE_SEL4_Msk 0x3UL
+#define UDB_PA_CFG13_OE_SEL5_Pos 2UL
+#define UDB_PA_CFG13_OE_SEL5_Msk 0xCUL
+#define UDB_PA_CFG13_OE_SEL6_Pos 4UL
+#define UDB_PA_CFG13_OE_SEL6_Msk 0x30UL
+#define UDB_PA_CFG13_OE_SEL7_Pos 6UL
+#define UDB_PA_CFG13_OE_SEL7_Msk 0xC0UL
+/* UDB_PA.CFG14 */
+#define UDB_PA_CFG14_OE_SYNC0_Pos 0UL
+#define UDB_PA_CFG14_OE_SYNC0_Msk 0x3UL
+#define UDB_PA_CFG14_OE_SYNC1_Pos 2UL
+#define UDB_PA_CFG14_OE_SYNC1_Msk 0xCUL
+#define UDB_PA_CFG14_OE_SYNC2_Pos 4UL
+#define UDB_PA_CFG14_OE_SYNC2_Msk 0x30UL
+#define UDB_PA_CFG14_OE_SYNC3_Pos 6UL
+#define UDB_PA_CFG14_OE_SYNC3_Msk 0xC0UL
+
+
+/* UDB_BCTL.MDCLK_EN */
+#define UDB_BCTL_MDCLK_EN_DCEN_Pos 0UL
+#define UDB_BCTL_MDCLK_EN_DCEN_Msk 0xFFUL
+/* UDB_BCTL.MBCLK_EN */
+#define UDB_BCTL_MBCLK_EN_BCEN_Pos 0UL
+#define UDB_BCTL_MBCLK_EN_BCEN_Msk 0x1UL
+/* UDB_BCTL.BOTSEL_L */
+#define UDB_BCTL_BOTSEL_L_CLK_SEL0_Pos 0UL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL0_Msk 0x3UL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL1_Pos 2UL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL1_Msk 0xCUL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL2_Pos 4UL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL2_Msk 0x30UL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL3_Pos 6UL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL3_Msk 0xC0UL
+/* UDB_BCTL.BOTSEL_U */
+#define UDB_BCTL_BOTSEL_U_CLK_SEL4_Pos 0UL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL4_Msk 0x3UL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL5_Pos 2UL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL5_Msk 0xCUL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL6_Pos 4UL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL6_Msk 0x30UL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL7_Pos 6UL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL7_Msk 0xC0UL
+/* UDB_BCTL.QCLK_EN */
+#define UDB_BCTL_QCLK_EN_DCEN_Q_Pos 0UL
+#define UDB_BCTL_QCLK_EN_DCEN_Q_Msk 0xFFUL
+#define UDB_BCTL_QCLK_EN_BCEN_Q_Pos 8UL
+#define UDB_BCTL_QCLK_EN_BCEN_Q_Msk 0x100UL
+#define UDB_BCTL_QCLK_EN_DISABLE_ROUTE_Pos 11UL
+#define UDB_BCTL_QCLK_EN_DISABLE_ROUTE_Msk 0x800UL
+
+
+/* UDB_UDBIF.BANK_CTL */
+#define UDB_UDBIF_BANK_CTL_DIS_COR_Pos 0UL
+#define UDB_UDBIF_BANK_CTL_DIS_COR_Msk 0x1UL
+#define UDB_UDBIF_BANK_CTL_ROUTE_EN_Pos 1UL
+#define UDB_UDBIF_BANK_CTL_ROUTE_EN_Msk 0x2UL
+#define UDB_UDBIF_BANK_CTL_BANK_EN_Pos 2UL
+#define UDB_UDBIF_BANK_CTL_BANK_EN_Msk 0x4UL
+#define UDB_UDBIF_BANK_CTL_READ_WAIT_Pos 8UL
+#define UDB_UDBIF_BANK_CTL_READ_WAIT_Msk 0x100UL
+/* UDB_UDBIF.INT_CLK_CTL */
+#define UDB_UDBIF_INT_CLK_CTL_INT_CLK_ENABLE_Pos 0UL
+#define UDB_UDBIF_INT_CLK_CTL_INT_CLK_ENABLE_Msk 0x1UL
+/* UDB_UDBIF.INT_CFG */
+#define UDB_UDBIF_INT_CFG_INT_MODE_CFG_Pos 0UL
+#define UDB_UDBIF_INT_CFG_INT_MODE_CFG_Msk 0xFFFFFFFFUL
+/* UDB_UDBIF.TR_CLK_CTL */
+#define UDB_UDBIF_TR_CLK_CTL_TR_CLOCK_ENABLE_Pos 0UL
+#define UDB_UDBIF_TR_CLK_CTL_TR_CLOCK_ENABLE_Msk 0x1UL
+/* UDB_UDBIF.TR_CFG */
+#define UDB_UDBIF_TR_CFG_TR_MODE_CFG_Pos 0UL
+#define UDB_UDBIF_TR_CFG_TR_MODE_CFG_Msk 0xFFFFFFFFUL
+/* UDB_UDBIF.PRIVATE */
+#define UDB_UDBIF_PRIVATE_PIPELINE_MD_Pos 0UL
+#define UDB_UDBIF_PRIVATE_PIPELINE_MD_Msk 0x1UL
+
+
+#endif /* _CYIP_UDB_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/ip/cyip_usbfs.h b/platform/ext/target/psoc64/Device/Include/ip/cyip_usbfs.h
new file mode 100644
index 0000000000..2c2d5df640
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/ip/cyip_usbfs.h
@@ -0,0 +1,1779 @@
+/***************************************************************************//**
+* \file cyip_usbfs.h
+*
+* \brief
+* USBFS IP definitions
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYIP_USBFS_H_
+#define _CYIP_USBFS_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* USBFS
+*******************************************************************************/
+
+#define USBFS_USBDEV_SECTION_SIZE 0x00002000UL
+#define USBFS_USBLPM_SECTION_SIZE 0x00001000UL
+#define USBFS_USBHOST_SECTION_SIZE 0x00002000UL
+#define USBFS_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief USB Device (USBFS_USBDEV)
+ */
+typedef struct {
+ __IOM uint32_t EP0_DR[8]; /*!< 0x00000000 Control End point EP0 Data Register */
+ __IOM uint32_t CR0; /*!< 0x00000020 USB control 0 Register */
+ __IOM uint32_t CR1; /*!< 0x00000024 USB control 1 Register */
+ __IOM uint32_t SIE_EP_INT_EN; /*!< 0x00000028 USB SIE Data Endpoints Interrupt Enable Register */
+ __IOM uint32_t SIE_EP_INT_SR; /*!< 0x0000002C USB SIE Data Endpoint Interrupt Status */
+ __IOM uint32_t SIE_EP1_CNT0; /*!< 0x00000030 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP1_CNT1; /*!< 0x00000034 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP1_CR0; /*!< 0x00000038 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t USBIO_CR0; /*!< 0x00000040 USBIO Control 0 Register */
+ __IOM uint32_t USBIO_CR2; /*!< 0x00000044 USBIO control 2 Register */
+ __IOM uint32_t USBIO_CR1; /*!< 0x00000048 USBIO control 1 Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t DYN_RECONFIG; /*!< 0x00000050 USB Dynamic reconfiguration register */
+ __IM uint32_t RESERVED2[3];
+ __IM uint32_t SOF0; /*!< 0x00000060 Start Of Frame Register */
+ __IM uint32_t SOF1; /*!< 0x00000064 Start Of Frame Register */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t SIE_EP2_CNT0; /*!< 0x00000070 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP2_CNT1; /*!< 0x00000074 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP2_CR0; /*!< 0x00000078 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED4;
+ __IM uint32_t OSCLK_DR0; /*!< 0x00000080 Oscillator lock data register 0 */
+ __IM uint32_t OSCLK_DR1; /*!< 0x00000084 Oscillator lock data register 1 */
+ __IM uint32_t RESERVED5[6];
+ __IOM uint32_t EP0_CR; /*!< 0x000000A0 Endpoint0 control Register */
+ __IOM uint32_t EP0_CNT; /*!< 0x000000A4 Endpoint0 count Register */
+ __IM uint32_t RESERVED6[2];
+ __IOM uint32_t SIE_EP3_CNT0; /*!< 0x000000B0 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP3_CNT1; /*!< 0x000000B4 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP3_CR0; /*!< 0x000000B8 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED7[13];
+ __IOM uint32_t SIE_EP4_CNT0; /*!< 0x000000F0 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP4_CNT1; /*!< 0x000000F4 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP4_CR0; /*!< 0x000000F8 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED8[13];
+ __IOM uint32_t SIE_EP5_CNT0; /*!< 0x00000130 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP5_CNT1; /*!< 0x00000134 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP5_CR0; /*!< 0x00000138 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED9[13];
+ __IOM uint32_t SIE_EP6_CNT0; /*!< 0x00000170 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP6_CNT1; /*!< 0x00000174 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP6_CR0; /*!< 0x00000178 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED10[13];
+ __IOM uint32_t SIE_EP7_CNT0; /*!< 0x000001B0 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP7_CNT1; /*!< 0x000001B4 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP7_CR0; /*!< 0x000001B8 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED11[13];
+ __IOM uint32_t SIE_EP8_CNT0; /*!< 0x000001F0 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP8_CNT1; /*!< 0x000001F4 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP8_CR0; /*!< 0x000001F8 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t ARB_EP1_CFG; /*!< 0x00000200 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP1_INT_EN; /*!< 0x00000204 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP1_SR; /*!< 0x00000208 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED13;
+ __IOM uint32_t ARB_RW1_WA; /*!< 0x00000210 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW1_WA_MSB; /*!< 0x00000214 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW1_RA; /*!< 0x00000218 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW1_RA_MSB; /*!< 0x0000021C Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW1_DR; /*!< 0x00000220 Endpoint Data Register */
+ __IM uint32_t RESERVED14[3];
+ __IOM uint32_t BUF_SIZE; /*!< 0x00000230 Dedicated Endpoint Buffer Size Register *1 */
+ __IM uint32_t RESERVED15;
+ __IOM uint32_t EP_ACTIVE; /*!< 0x00000238 Endpoint Active Indication Register *1 */
+ __IOM uint32_t EP_TYPE; /*!< 0x0000023C Endpoint Type (IN/OUT) Indication *1 */
+ __IOM uint32_t ARB_EP2_CFG; /*!< 0x00000240 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP2_INT_EN; /*!< 0x00000244 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP2_SR; /*!< 0x00000248 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED16;
+ __IOM uint32_t ARB_RW2_WA; /*!< 0x00000250 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW2_WA_MSB; /*!< 0x00000254 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW2_RA; /*!< 0x00000258 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW2_RA_MSB; /*!< 0x0000025C Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW2_DR; /*!< 0x00000260 Endpoint Data Register */
+ __IM uint32_t RESERVED17[3];
+ __IOM uint32_t ARB_CFG; /*!< 0x00000270 Arbiter Configuration Register *1 */
+ __IOM uint32_t USB_CLK_EN; /*!< 0x00000274 USB Block Clock Enable Register */
+ __IOM uint32_t ARB_INT_EN; /*!< 0x00000278 Arbiter Interrupt Enable *1 */
+ __IM uint32_t ARB_INT_SR; /*!< 0x0000027C Arbiter Interrupt Status *1 */
+ __IOM uint32_t ARB_EP3_CFG; /*!< 0x00000280 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP3_INT_EN; /*!< 0x00000284 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP3_SR; /*!< 0x00000288 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED18;
+ __IOM uint32_t ARB_RW3_WA; /*!< 0x00000290 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW3_WA_MSB; /*!< 0x00000294 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW3_RA; /*!< 0x00000298 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW3_RA_MSB; /*!< 0x0000029C Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW3_DR; /*!< 0x000002A0 Endpoint Data Register */
+ __IM uint32_t RESERVED19[3];
+ __IOM uint32_t CWA; /*!< 0x000002B0 Common Area Write Address *1 */
+ __IOM uint32_t CWA_MSB; /*!< 0x000002B4 Endpoint Read Address value *1 */
+ __IM uint32_t RESERVED20[2];
+ __IOM uint32_t ARB_EP4_CFG; /*!< 0x000002C0 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP4_INT_EN; /*!< 0x000002C4 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP4_SR; /*!< 0x000002C8 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED21;
+ __IOM uint32_t ARB_RW4_WA; /*!< 0x000002D0 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW4_WA_MSB; /*!< 0x000002D4 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW4_RA; /*!< 0x000002D8 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW4_RA_MSB; /*!< 0x000002DC Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW4_DR; /*!< 0x000002E0 Endpoint Data Register */
+ __IM uint32_t RESERVED22[3];
+ __IOM uint32_t DMA_THRES; /*!< 0x000002F0 DMA Burst / Threshold Configuration */
+ __IOM uint32_t DMA_THRES_MSB; /*!< 0x000002F4 DMA Burst / Threshold Configuration */
+ __IM uint32_t RESERVED23[2];
+ __IOM uint32_t ARB_EP5_CFG; /*!< 0x00000300 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP5_INT_EN; /*!< 0x00000304 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP5_SR; /*!< 0x00000308 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED24;
+ __IOM uint32_t ARB_RW5_WA; /*!< 0x00000310 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW5_WA_MSB; /*!< 0x00000314 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW5_RA; /*!< 0x00000318 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW5_RA_MSB; /*!< 0x0000031C Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW5_DR; /*!< 0x00000320 Endpoint Data Register */
+ __IM uint32_t RESERVED25[3];
+ __IOM uint32_t BUS_RST_CNT; /*!< 0x00000330 Bus Reset Count Register */
+ __IM uint32_t RESERVED26[3];
+ __IOM uint32_t ARB_EP6_CFG; /*!< 0x00000340 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP6_INT_EN; /*!< 0x00000344 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP6_SR; /*!< 0x00000348 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED27;
+ __IOM uint32_t ARB_RW6_WA; /*!< 0x00000350 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW6_WA_MSB; /*!< 0x00000354 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW6_RA; /*!< 0x00000358 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW6_RA_MSB; /*!< 0x0000035C Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW6_DR; /*!< 0x00000360 Endpoint Data Register */
+ __IM uint32_t RESERVED28[7];
+ __IOM uint32_t ARB_EP7_CFG; /*!< 0x00000380 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP7_INT_EN; /*!< 0x00000384 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP7_SR; /*!< 0x00000388 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED29;
+ __IOM uint32_t ARB_RW7_WA; /*!< 0x00000390 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW7_WA_MSB; /*!< 0x00000394 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW7_RA; /*!< 0x00000398 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW7_RA_MSB; /*!< 0x0000039C Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW7_DR; /*!< 0x000003A0 Endpoint Data Register */
+ __IM uint32_t RESERVED30[7];
+ __IOM uint32_t ARB_EP8_CFG; /*!< 0x000003C0 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP8_INT_EN; /*!< 0x000003C4 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP8_SR; /*!< 0x000003C8 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED31;
+ __IOM uint32_t ARB_RW8_WA; /*!< 0x000003D0 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW8_WA_MSB; /*!< 0x000003D4 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW8_RA; /*!< 0x000003D8 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW8_RA_MSB; /*!< 0x000003DC Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW8_DR; /*!< 0x000003E0 Endpoint Data Register */
+ __IM uint32_t RESERVED32[7];
+ __IOM uint32_t MEM_DATA[512]; /*!< 0x00000400 DATA */
+ __IM uint32_t RESERVED33[280];
+ __IM uint32_t SOF16; /*!< 0x00001060 Start Of Frame Register */
+ __IM uint32_t RESERVED34[7];
+ __IM uint32_t OSCLK_DR16; /*!< 0x00001080 Oscillator lock data register */
+ __IM uint32_t RESERVED35[99];
+ __IOM uint32_t ARB_RW1_WA16; /*!< 0x00001210 Endpoint Write Address value */
+ __IM uint32_t RESERVED36;
+ __IOM uint32_t ARB_RW1_RA16; /*!< 0x00001218 Endpoint Read Address value */
+ __IM uint32_t RESERVED37;
+ __IOM uint32_t ARB_RW1_DR16; /*!< 0x00001220 Endpoint Data Register */
+ __IM uint32_t RESERVED38[11];
+ __IOM uint32_t ARB_RW2_WA16; /*!< 0x00001250 Endpoint Write Address value */
+ __IM uint32_t RESERVED39;
+ __IOM uint32_t ARB_RW2_RA16; /*!< 0x00001258 Endpoint Read Address value */
+ __IM uint32_t RESERVED40;
+ __IOM uint32_t ARB_RW2_DR16; /*!< 0x00001260 Endpoint Data Register */
+ __IM uint32_t RESERVED41[11];
+ __IOM uint32_t ARB_RW3_WA16; /*!< 0x00001290 Endpoint Write Address value */
+ __IM uint32_t RESERVED42;
+ __IOM uint32_t ARB_RW3_RA16; /*!< 0x00001298 Endpoint Read Address value */
+ __IM uint32_t RESERVED43;
+ __IOM uint32_t ARB_RW3_DR16; /*!< 0x000012A0 Endpoint Data Register */
+ __IM uint32_t RESERVED44[3];
+ __IOM uint32_t CWA16; /*!< 0x000012B0 Common Area Write Address */
+ __IM uint32_t RESERVED45[7];
+ __IOM uint32_t ARB_RW4_WA16; /*!< 0x000012D0 Endpoint Write Address value */
+ __IM uint32_t RESERVED46;
+ __IOM uint32_t ARB_RW4_RA16; /*!< 0x000012D8 Endpoint Read Address value */
+ __IM uint32_t RESERVED47;
+ __IOM uint32_t ARB_RW4_DR16; /*!< 0x000012E0 Endpoint Data Register */
+ __IM uint32_t RESERVED48[3];
+ __IOM uint32_t DMA_THRES16; /*!< 0x000012F0 DMA Burst / Threshold Configuration */
+ __IM uint32_t RESERVED49[7];
+ __IOM uint32_t ARB_RW5_WA16; /*!< 0x00001310 Endpoint Write Address value */
+ __IM uint32_t RESERVED50;
+ __IOM uint32_t ARB_RW5_RA16; /*!< 0x00001318 Endpoint Read Address value */
+ __IM uint32_t RESERVED51;
+ __IOM uint32_t ARB_RW5_DR16; /*!< 0x00001320 Endpoint Data Register */
+ __IM uint32_t RESERVED52[11];
+ __IOM uint32_t ARB_RW6_WA16; /*!< 0x00001350 Endpoint Write Address value */
+ __IM uint32_t RESERVED53;
+ __IOM uint32_t ARB_RW6_RA16; /*!< 0x00001358 Endpoint Read Address value */
+ __IM uint32_t RESERVED54;
+ __IOM uint32_t ARB_RW6_DR16; /*!< 0x00001360 Endpoint Data Register */
+ __IM uint32_t RESERVED55[11];
+ __IOM uint32_t ARB_RW7_WA16; /*!< 0x00001390 Endpoint Write Address value */
+ __IM uint32_t RESERVED56;
+ __IOM uint32_t ARB_RW7_RA16; /*!< 0x00001398 Endpoint Read Address value */
+ __IM uint32_t RESERVED57;
+ __IOM uint32_t ARB_RW7_DR16; /*!< 0x000013A0 Endpoint Data Register */
+ __IM uint32_t RESERVED58[11];
+ __IOM uint32_t ARB_RW8_WA16; /*!< 0x000013D0 Endpoint Write Address value */
+ __IM uint32_t RESERVED59;
+ __IOM uint32_t ARB_RW8_RA16; /*!< 0x000013D8 Endpoint Read Address value */
+ __IM uint32_t RESERVED60;
+ __IOM uint32_t ARB_RW8_DR16; /*!< 0x000013E0 Endpoint Data Register */
+ __IM uint32_t RESERVED61[775];
+} USBFS_USBDEV_V1_Type; /*!< Size = 8192 (0x2000) */
+
+/**
+ * \brief USB Device LPM and PHY Test (USBFS_USBLPM)
+ */
+typedef struct {
+ __IOM uint32_t POWER_CTL; /*!< 0x00000000 Power Control Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t USBIO_CTL; /*!< 0x00000008 USB IO Control Register */
+ __IOM uint32_t FLOW_CTL; /*!< 0x0000000C Flow Control Register */
+ __IOM uint32_t LPM_CTL; /*!< 0x00000010 LPM Control Register */
+ __IM uint32_t LPM_STAT; /*!< 0x00000014 LPM Status register */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t INTR_SIE; /*!< 0x00000020 USB SOF, BUS RESET and EP0 Interrupt Status */
+ __IOM uint32_t INTR_SIE_SET; /*!< 0x00000024 USB SOF, BUS RESET and EP0 Interrupt Set */
+ __IOM uint32_t INTR_SIE_MASK; /*!< 0x00000028 USB SOF, BUS RESET and EP0 Interrupt Mask */
+ __IM uint32_t INTR_SIE_MASKED; /*!< 0x0000002C USB SOF, BUS RESET and EP0 Interrupt Masked */
+ __IOM uint32_t INTR_LVL_SEL; /*!< 0x00000030 Select interrupt level for each interrupt source */
+ __IM uint32_t INTR_CAUSE_HI; /*!< 0x00000034 High priority interrupt Cause register */
+ __IM uint32_t INTR_CAUSE_MED; /*!< 0x00000038 Medium priority interrupt Cause register */
+ __IM uint32_t INTR_CAUSE_LO; /*!< 0x0000003C Low priority interrupt Cause register */
+ __IM uint32_t RESERVED2[12];
+ __IOM uint32_t DFT_CTL; /*!< 0x00000070 DFT control */
+ __IM uint32_t RESERVED3[995];
+} USBFS_USBLPM_V1_Type; /*!< Size = 4096 (0x1000) */
+
+/**
+ * \brief USB Host Controller (USBFS_USBHOST)
+ */
+typedef struct {
+ __IOM uint32_t HOST_CTL0; /*!< 0x00000000 Host Control 0 Register. */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t HOST_CTL1; /*!< 0x00000010 Host Control 1 Register. */
+ __IM uint32_t RESERVED1[59];
+ __IOM uint32_t HOST_CTL2; /*!< 0x00000100 Host Control 2 Register. */
+ __IOM uint32_t HOST_ERR; /*!< 0x00000104 Host Error Status Register. */
+ __IOM uint32_t HOST_STATUS; /*!< 0x00000108 Host Status Register. */
+ __IOM uint32_t HOST_FCOMP; /*!< 0x0000010C Host SOF Interrupt Frame Compare Register */
+ __IOM uint32_t HOST_RTIMER; /*!< 0x00000110 Host Retry Timer Setup Register */
+ __IOM uint32_t HOST_ADDR; /*!< 0x00000114 Host Address Register */
+ __IOM uint32_t HOST_EOF; /*!< 0x00000118 Host EOF Setup Register */
+ __IOM uint32_t HOST_FRAME; /*!< 0x0000011C Host Frame Setup Register */
+ __IOM uint32_t HOST_TOKEN; /*!< 0x00000120 Host Token Endpoint Register */
+ __IM uint32_t RESERVED2[183];
+ __IOM uint32_t HOST_EP1_CTL; /*!< 0x00000400 Host Endpoint 1 Control Register */
+ __IM uint32_t HOST_EP1_STATUS; /*!< 0x00000404 Host Endpoint 1 Status Register */
+ __IOM uint32_t HOST_EP1_RW1_DR; /*!< 0x00000408 Host Endpoint 1 Data 1-Byte Register */
+ __IOM uint32_t HOST_EP1_RW2_DR; /*!< 0x0000040C Host Endpoint 1 Data 2-Byte Register */
+ __IM uint32_t RESERVED3[60];
+ __IOM uint32_t HOST_EP2_CTL; /*!< 0x00000500 Host Endpoint 2 Control Register */
+ __IM uint32_t HOST_EP2_STATUS; /*!< 0x00000504 Host Endpoint 2 Status Register */
+ __IOM uint32_t HOST_EP2_RW1_DR; /*!< 0x00000508 Host Endpoint 2 Data 1-Byte Register */
+ __IOM uint32_t HOST_EP2_RW2_DR; /*!< 0x0000050C Host Endpoint 2 Data 2-Byte Register */
+ __IM uint32_t RESERVED4[188];
+ __IOM uint32_t HOST_LVL1_SEL; /*!< 0x00000800 Host Interrupt Level 1 Selection Register */
+ __IOM uint32_t HOST_LVL2_SEL; /*!< 0x00000804 Host Interrupt Level 2 Selection Register */
+ __IM uint32_t RESERVED5[62];
+ __IM uint32_t INTR_USBHOST_CAUSE_HI; /*!< 0x00000900 Interrupt USB Host Cause High Register */
+ __IM uint32_t INTR_USBHOST_CAUSE_MED; /*!< 0x00000904 Interrupt USB Host Cause Medium Register */
+ __IM uint32_t INTR_USBHOST_CAUSE_LO; /*!< 0x00000908 Interrupt USB Host Cause Low Register */
+ __IM uint32_t RESERVED6[5];
+ __IM uint32_t INTR_HOST_EP_CAUSE_HI; /*!< 0x00000920 Interrupt USB Host Endpoint Cause High Register */
+ __IM uint32_t INTR_HOST_EP_CAUSE_MED; /*!< 0x00000924 Interrupt USB Host Endpoint Cause Medium Register */
+ __IM uint32_t INTR_HOST_EP_CAUSE_LO; /*!< 0x00000928 Interrupt USB Host Endpoint Cause Low Register */
+ __IM uint32_t RESERVED7[5];
+ __IOM uint32_t INTR_USBHOST; /*!< 0x00000940 Interrupt USB Host Register */
+ __IOM uint32_t INTR_USBHOST_SET; /*!< 0x00000944 Interrupt USB Host Set Register */
+ __IOM uint32_t INTR_USBHOST_MASK; /*!< 0x00000948 Interrupt USB Host Mask Register */
+ __IM uint32_t INTR_USBHOST_MASKED; /*!< 0x0000094C Interrupt USB Host Masked Register */
+ __IM uint32_t RESERVED8[44];
+ __IOM uint32_t INTR_HOST_EP; /*!< 0x00000A00 Interrupt USB Host Endpoint Register */
+ __IOM uint32_t INTR_HOST_EP_SET; /*!< 0x00000A04 Interrupt USB Host Endpoint Set Register */
+ __IOM uint32_t INTR_HOST_EP_MASK; /*!< 0x00000A08 Interrupt USB Host Endpoint Mask Register */
+ __IM uint32_t INTR_HOST_EP_MASKED; /*!< 0x00000A0C Interrupt USB Host Endpoint Masked Register */
+ __IM uint32_t RESERVED9[60];
+ __IOM uint32_t HOST_DMA_ENBL; /*!< 0x00000B00 Host DMA Enable Register */
+ __IM uint32_t RESERVED10[7];
+ __IOM uint32_t HOST_EP1_BLK; /*!< 0x00000B20 Host Endpoint 1 Block Register */
+ __IM uint32_t RESERVED11[3];
+ __IOM uint32_t HOST_EP2_BLK; /*!< 0x00000B30 Host Endpoint 2 Block Register */
+ __IM uint32_t RESERVED12[1331];
+} USBFS_USBHOST_V1_Type; /*!< Size = 8192 (0x2000) */
+
+/**
+ * \brief USB Host and Device Controller (USBFS)
+ */
+typedef struct {
+ USBFS_USBDEV_V1_Type USBDEV; /*!< 0x00000000 USB Device */
+ USBFS_USBLPM_V1_Type USBLPM; /*!< 0x00002000 USB Device LPM and PHY Test */
+ __IM uint32_t RESERVED[1024];
+ USBFS_USBHOST_V1_Type USBHOST; /*!< 0x00004000 USB Host Controller */
+} USBFS_V1_Type; /*!< Size = 24576 (0x6000) */
+
+
+/* USBFS_USBDEV.EP0_DR */
+#define USBFS_USBDEV_EP0_DR_DATA_BYTE_Pos 0UL
+#define USBFS_USBDEV_EP0_DR_DATA_BYTE_Msk 0xFFUL
+/* USBFS_USBDEV.CR0 */
+#define USBFS_USBDEV_CR0_DEVICE_ADDRESS_Pos 0UL
+#define USBFS_USBDEV_CR0_DEVICE_ADDRESS_Msk 0x7FUL
+#define USBFS_USBDEV_CR0_USB_ENABLE_Pos 7UL
+#define USBFS_USBDEV_CR0_USB_ENABLE_Msk 0x80UL
+/* USBFS_USBDEV.CR1 */
+#define USBFS_USBDEV_CR1_REG_ENABLE_Pos 0UL
+#define USBFS_USBDEV_CR1_REG_ENABLE_Msk 0x1UL
+#define USBFS_USBDEV_CR1_ENABLE_LOCK_Pos 1UL
+#define USBFS_USBDEV_CR1_ENABLE_LOCK_Msk 0x2UL
+#define USBFS_USBDEV_CR1_BUS_ACTIVITY_Pos 2UL
+#define USBFS_USBDEV_CR1_BUS_ACTIVITY_Msk 0x4UL
+#define USBFS_USBDEV_CR1_RESERVED_3_Pos 3UL
+#define USBFS_USBDEV_CR1_RESERVED_3_Msk 0x8UL
+/* USBFS_USBDEV.SIE_EP_INT_EN */
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP1_INTR_EN_Pos 0UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP1_INTR_EN_Msk 0x1UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP2_INTR_EN_Pos 1UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP2_INTR_EN_Msk 0x2UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP3_INTR_EN_Pos 2UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP3_INTR_EN_Msk 0x4UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP4_INTR_EN_Pos 3UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP4_INTR_EN_Msk 0x8UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP5_INTR_EN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP5_INTR_EN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP6_INTR_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP6_INTR_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP7_INTR_EN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP7_INTR_EN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP8_INTR_EN_Pos 7UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP8_INTR_EN_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP_INT_SR */
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP1_INTR_Pos 0UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP1_INTR_Msk 0x1UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP2_INTR_Pos 1UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP2_INTR_Msk 0x2UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP3_INTR_Pos 2UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP3_INTR_Msk 0x4UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP4_INTR_Pos 3UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP4_INTR_Msk 0x8UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP5_INTR_Pos 4UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP5_INTR_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP6_INTR_Pos 5UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP6_INTR_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP7_INTR_Pos 6UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP7_INTR_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP8_INTR_Pos 7UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP8_INTR_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP1_CNT0 */
+#define USBFS_USBDEV_SIE_EP1_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP1_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP1_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP1_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP1_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP1_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP1_CNT1 */
+#define USBFS_USBDEV_SIE_EP1_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP1_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP1_CR0 */
+#define USBFS_USBDEV_SIE_EP1_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP1_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP1_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP1_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP1_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP1_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP1_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP1_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP1_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP1_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.USBIO_CR0 */
+#define USBFS_USBDEV_USBIO_CR0_RD_Pos 0UL
+#define USBFS_USBDEV_USBIO_CR0_RD_Msk 0x1UL
+#define USBFS_USBDEV_USBIO_CR0_TD_Pos 5UL
+#define USBFS_USBDEV_USBIO_CR0_TD_Msk 0x20UL
+#define USBFS_USBDEV_USBIO_CR0_TSE0_Pos 6UL
+#define USBFS_USBDEV_USBIO_CR0_TSE0_Msk 0x40UL
+#define USBFS_USBDEV_USBIO_CR0_TEN_Pos 7UL
+#define USBFS_USBDEV_USBIO_CR0_TEN_Msk 0x80UL
+/* USBFS_USBDEV.USBIO_CR2 */
+#define USBFS_USBDEV_USBIO_CR2_RESERVED_5_0_Pos 0UL
+#define USBFS_USBDEV_USBIO_CR2_RESERVED_5_0_Msk 0x3FUL
+#define USBFS_USBDEV_USBIO_CR2_TEST_PKT_Pos 6UL
+#define USBFS_USBDEV_USBIO_CR2_TEST_PKT_Msk 0x40UL
+#define USBFS_USBDEV_USBIO_CR2_RESERVED_7_Pos 7UL
+#define USBFS_USBDEV_USBIO_CR2_RESERVED_7_Msk 0x80UL
+/* USBFS_USBDEV.USBIO_CR1 */
+#define USBFS_USBDEV_USBIO_CR1_DMO_Pos 0UL
+#define USBFS_USBDEV_USBIO_CR1_DMO_Msk 0x1UL
+#define USBFS_USBDEV_USBIO_CR1_DPO_Pos 1UL
+#define USBFS_USBDEV_USBIO_CR1_DPO_Msk 0x2UL
+#define USBFS_USBDEV_USBIO_CR1_RESERVED_2_Pos 2UL
+#define USBFS_USBDEV_USBIO_CR1_RESERVED_2_Msk 0x4UL
+#define USBFS_USBDEV_USBIO_CR1_IOMODE_Pos 5UL
+#define USBFS_USBDEV_USBIO_CR1_IOMODE_Msk 0x20UL
+/* USBFS_USBDEV.DYN_RECONFIG */
+#define USBFS_USBDEV_DYN_RECONFIG_DYN_CONFIG_EN_Pos 0UL
+#define USBFS_USBDEV_DYN_RECONFIG_DYN_CONFIG_EN_Msk 0x1UL
+#define USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_EPNO_Pos 1UL
+#define USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_EPNO_Msk 0xEUL
+#define USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_RDY_STS_Pos 4UL
+#define USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_RDY_STS_Msk 0x10UL
+/* USBFS_USBDEV.SOF0 */
+#define USBFS_USBDEV_SOF0_FRAME_NUMBER_Pos 0UL
+#define USBFS_USBDEV_SOF0_FRAME_NUMBER_Msk 0xFFUL
+/* USBFS_USBDEV.SOF1 */
+#define USBFS_USBDEV_SOF1_FRAME_NUMBER_MSB_Pos 0UL
+#define USBFS_USBDEV_SOF1_FRAME_NUMBER_MSB_Msk 0x7UL
+/* USBFS_USBDEV.SIE_EP2_CNT0 */
+#define USBFS_USBDEV_SIE_EP2_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP2_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP2_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP2_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP2_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP2_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP2_CNT1 */
+#define USBFS_USBDEV_SIE_EP2_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP2_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP2_CR0 */
+#define USBFS_USBDEV_SIE_EP2_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP2_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP2_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP2_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP2_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP2_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP2_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP2_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP2_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP2_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.OSCLK_DR0 */
+#define USBFS_USBDEV_OSCLK_DR0_ADDER_Pos 0UL
+#define USBFS_USBDEV_OSCLK_DR0_ADDER_Msk 0xFFUL
+/* USBFS_USBDEV.OSCLK_DR1 */
+#define USBFS_USBDEV_OSCLK_DR1_ADDER_MSB_Pos 0UL
+#define USBFS_USBDEV_OSCLK_DR1_ADDER_MSB_Msk 0x7FUL
+/* USBFS_USBDEV.EP0_CR */
+#define USBFS_USBDEV_EP0_CR_MODE_Pos 0UL
+#define USBFS_USBDEV_EP0_CR_MODE_Msk 0xFUL
+#define USBFS_USBDEV_EP0_CR_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_EP0_CR_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_EP0_CR_OUT_RCVD_Pos 5UL
+#define USBFS_USBDEV_EP0_CR_OUT_RCVD_Msk 0x20UL
+#define USBFS_USBDEV_EP0_CR_IN_RCVD_Pos 6UL
+#define USBFS_USBDEV_EP0_CR_IN_RCVD_Msk 0x40UL
+#define USBFS_USBDEV_EP0_CR_SETUP_RCVD_Pos 7UL
+#define USBFS_USBDEV_EP0_CR_SETUP_RCVD_Msk 0x80UL
+/* USBFS_USBDEV.EP0_CNT */
+#define USBFS_USBDEV_EP0_CNT_BYTE_COUNT_Pos 0UL
+#define USBFS_USBDEV_EP0_CNT_BYTE_COUNT_Msk 0xFUL
+#define USBFS_USBDEV_EP0_CNT_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_EP0_CNT_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP3_CNT0 */
+#define USBFS_USBDEV_SIE_EP3_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP3_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP3_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP3_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP3_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP3_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP3_CNT1 */
+#define USBFS_USBDEV_SIE_EP3_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP3_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP3_CR0 */
+#define USBFS_USBDEV_SIE_EP3_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP3_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP3_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP3_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP3_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP3_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP3_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP3_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP3_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP3_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP4_CNT0 */
+#define USBFS_USBDEV_SIE_EP4_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP4_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP4_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP4_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP4_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP4_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP4_CNT1 */
+#define USBFS_USBDEV_SIE_EP4_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP4_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP4_CR0 */
+#define USBFS_USBDEV_SIE_EP4_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP4_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP4_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP4_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP4_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP4_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP4_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP4_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP4_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP4_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP5_CNT0 */
+#define USBFS_USBDEV_SIE_EP5_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP5_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP5_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP5_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP5_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP5_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP5_CNT1 */
+#define USBFS_USBDEV_SIE_EP5_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP5_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP5_CR0 */
+#define USBFS_USBDEV_SIE_EP5_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP5_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP5_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP5_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP5_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP5_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP5_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP5_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP5_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP5_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP6_CNT0 */
+#define USBFS_USBDEV_SIE_EP6_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP6_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP6_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP6_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP6_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP6_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP6_CNT1 */
+#define USBFS_USBDEV_SIE_EP6_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP6_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP6_CR0 */
+#define USBFS_USBDEV_SIE_EP6_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP6_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP6_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP6_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP6_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP6_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP6_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP6_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP6_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP6_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP7_CNT0 */
+#define USBFS_USBDEV_SIE_EP7_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP7_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP7_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP7_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP7_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP7_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP7_CNT1 */
+#define USBFS_USBDEV_SIE_EP7_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP7_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP7_CR0 */
+#define USBFS_USBDEV_SIE_EP7_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP7_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP7_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP7_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP7_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP7_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP7_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP7_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP7_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP7_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP8_CNT0 */
+#define USBFS_USBDEV_SIE_EP8_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP8_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP8_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP8_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP8_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP8_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP8_CNT1 */
+#define USBFS_USBDEV_SIE_EP8_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP8_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP8_CR0 */
+#define USBFS_USBDEV_SIE_EP8_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP8_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP8_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP8_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP8_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP8_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP8_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP8_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP8_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP8_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.ARB_EP1_CFG */
+#define USBFS_USBDEV_ARB_EP1_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP1_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP1_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP1_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP1_INT_EN */
+#define USBFS_USBDEV_ARB_EP1_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP1_SR */
+#define USBFS_USBDEV_ARB_EP1_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP1_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP1_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP1_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP1_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP1_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP1_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP1_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP1_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP1_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW1_WA */
+#define USBFS_USBDEV_ARB_RW1_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW1_WA_MSB */
+#define USBFS_USBDEV_ARB_RW1_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW1_RA */
+#define USBFS_USBDEV_ARB_RW1_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW1_RA_MSB */
+#define USBFS_USBDEV_ARB_RW1_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW1_DR */
+#define USBFS_USBDEV_ARB_RW1_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.BUF_SIZE */
+#define USBFS_USBDEV_BUF_SIZE_IN_BUF_Pos 0UL
+#define USBFS_USBDEV_BUF_SIZE_IN_BUF_Msk 0xFUL
+#define USBFS_USBDEV_BUF_SIZE_OUT_BUF_Pos 4UL
+#define USBFS_USBDEV_BUF_SIZE_OUT_BUF_Msk 0xF0UL
+/* USBFS_USBDEV.EP_ACTIVE */
+#define USBFS_USBDEV_EP_ACTIVE_EP1_ACT_Pos 0UL
+#define USBFS_USBDEV_EP_ACTIVE_EP1_ACT_Msk 0x1UL
+#define USBFS_USBDEV_EP_ACTIVE_EP2_ACT_Pos 1UL
+#define USBFS_USBDEV_EP_ACTIVE_EP2_ACT_Msk 0x2UL
+#define USBFS_USBDEV_EP_ACTIVE_EP3_ACT_Pos 2UL
+#define USBFS_USBDEV_EP_ACTIVE_EP3_ACT_Msk 0x4UL
+#define USBFS_USBDEV_EP_ACTIVE_EP4_ACT_Pos 3UL
+#define USBFS_USBDEV_EP_ACTIVE_EP4_ACT_Msk 0x8UL
+#define USBFS_USBDEV_EP_ACTIVE_EP5_ACT_Pos 4UL
+#define USBFS_USBDEV_EP_ACTIVE_EP5_ACT_Msk 0x10UL
+#define USBFS_USBDEV_EP_ACTIVE_EP6_ACT_Pos 5UL
+#define USBFS_USBDEV_EP_ACTIVE_EP6_ACT_Msk 0x20UL
+#define USBFS_USBDEV_EP_ACTIVE_EP7_ACT_Pos 6UL
+#define USBFS_USBDEV_EP_ACTIVE_EP7_ACT_Msk 0x40UL
+#define USBFS_USBDEV_EP_ACTIVE_EP8_ACT_Pos 7UL
+#define USBFS_USBDEV_EP_ACTIVE_EP8_ACT_Msk 0x80UL
+/* USBFS_USBDEV.EP_TYPE */
+#define USBFS_USBDEV_EP_TYPE_EP1_TYP_Pos 0UL
+#define USBFS_USBDEV_EP_TYPE_EP1_TYP_Msk 0x1UL
+#define USBFS_USBDEV_EP_TYPE_EP2_TYP_Pos 1UL
+#define USBFS_USBDEV_EP_TYPE_EP2_TYP_Msk 0x2UL
+#define USBFS_USBDEV_EP_TYPE_EP3_TYP_Pos 2UL
+#define USBFS_USBDEV_EP_TYPE_EP3_TYP_Msk 0x4UL
+#define USBFS_USBDEV_EP_TYPE_EP4_TYP_Pos 3UL
+#define USBFS_USBDEV_EP_TYPE_EP4_TYP_Msk 0x8UL
+#define USBFS_USBDEV_EP_TYPE_EP5_TYP_Pos 4UL
+#define USBFS_USBDEV_EP_TYPE_EP5_TYP_Msk 0x10UL
+#define USBFS_USBDEV_EP_TYPE_EP6_TYP_Pos 5UL
+#define USBFS_USBDEV_EP_TYPE_EP6_TYP_Msk 0x20UL
+#define USBFS_USBDEV_EP_TYPE_EP7_TYP_Pos 6UL
+#define USBFS_USBDEV_EP_TYPE_EP7_TYP_Msk 0x40UL
+#define USBFS_USBDEV_EP_TYPE_EP8_TYP_Pos 7UL
+#define USBFS_USBDEV_EP_TYPE_EP8_TYP_Msk 0x80UL
+/* USBFS_USBDEV.ARB_EP2_CFG */
+#define USBFS_USBDEV_ARB_EP2_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP2_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP2_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP2_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP2_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP2_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP2_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP2_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP2_INT_EN */
+#define USBFS_USBDEV_ARB_EP2_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP2_SR */
+#define USBFS_USBDEV_ARB_EP2_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP2_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP2_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP2_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP2_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP2_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP2_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP2_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP2_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP2_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW2_WA */
+#define USBFS_USBDEV_ARB_RW2_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW2_WA_MSB */
+#define USBFS_USBDEV_ARB_RW2_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW2_RA */
+#define USBFS_USBDEV_ARB_RW2_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW2_RA_MSB */
+#define USBFS_USBDEV_ARB_RW2_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW2_DR */
+#define USBFS_USBDEV_ARB_RW2_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_CFG */
+#define USBFS_USBDEV_ARB_CFG_AUTO_MEM_Pos 4UL
+#define USBFS_USBDEV_ARB_CFG_AUTO_MEM_Msk 0x10UL
+#define USBFS_USBDEV_ARB_CFG_DMA_CFG_Pos 5UL
+#define USBFS_USBDEV_ARB_CFG_DMA_CFG_Msk 0x60UL
+#define USBFS_USBDEV_ARB_CFG_CFG_CMP_Pos 7UL
+#define USBFS_USBDEV_ARB_CFG_CFG_CMP_Msk 0x80UL
+/* USBFS_USBDEV.USB_CLK_EN */
+#define USBFS_USBDEV_USB_CLK_EN_CSR_CLK_EN_Pos 0UL
+#define USBFS_USBDEV_USB_CLK_EN_CSR_CLK_EN_Msk 0x1UL
+/* USBFS_USBDEV.ARB_INT_EN */
+#define USBFS_USBDEV_ARB_INT_EN_EP1_INTR_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_INT_EN_EP1_INTR_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_INT_EN_EP2_INTR_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_INT_EN_EP2_INTR_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_INT_EN_EP3_INTR_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_INT_EN_EP3_INTR_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_INT_EN_EP4_INTR_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_INT_EN_EP4_INTR_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_INT_EN_EP5_INTR_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_INT_EN_EP5_INTR_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_INT_EN_EP6_INTR_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_INT_EN_EP6_INTR_EN_Msk 0x20UL
+#define USBFS_USBDEV_ARB_INT_EN_EP7_INTR_EN_Pos 6UL
+#define USBFS_USBDEV_ARB_INT_EN_EP7_INTR_EN_Msk 0x40UL
+#define USBFS_USBDEV_ARB_INT_EN_EP8_INTR_EN_Pos 7UL
+#define USBFS_USBDEV_ARB_INT_EN_EP8_INTR_EN_Msk 0x80UL
+/* USBFS_USBDEV.ARB_INT_SR */
+#define USBFS_USBDEV_ARB_INT_SR_EP1_INTR_Pos 0UL
+#define USBFS_USBDEV_ARB_INT_SR_EP1_INTR_Msk 0x1UL
+#define USBFS_USBDEV_ARB_INT_SR_EP2_INTR_Pos 1UL
+#define USBFS_USBDEV_ARB_INT_SR_EP2_INTR_Msk 0x2UL
+#define USBFS_USBDEV_ARB_INT_SR_EP3_INTR_Pos 2UL
+#define USBFS_USBDEV_ARB_INT_SR_EP3_INTR_Msk 0x4UL
+#define USBFS_USBDEV_ARB_INT_SR_EP4_INTR_Pos 3UL
+#define USBFS_USBDEV_ARB_INT_SR_EP4_INTR_Msk 0x8UL
+#define USBFS_USBDEV_ARB_INT_SR_EP5_INTR_Pos 4UL
+#define USBFS_USBDEV_ARB_INT_SR_EP5_INTR_Msk 0x10UL
+#define USBFS_USBDEV_ARB_INT_SR_EP6_INTR_Pos 5UL
+#define USBFS_USBDEV_ARB_INT_SR_EP6_INTR_Msk 0x20UL
+#define USBFS_USBDEV_ARB_INT_SR_EP7_INTR_Pos 6UL
+#define USBFS_USBDEV_ARB_INT_SR_EP7_INTR_Msk 0x40UL
+#define USBFS_USBDEV_ARB_INT_SR_EP8_INTR_Pos 7UL
+#define USBFS_USBDEV_ARB_INT_SR_EP8_INTR_Msk 0x80UL
+/* USBFS_USBDEV.ARB_EP3_CFG */
+#define USBFS_USBDEV_ARB_EP3_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP3_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP3_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP3_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP3_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP3_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP3_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP3_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP3_INT_EN */
+#define USBFS_USBDEV_ARB_EP3_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP3_SR */
+#define USBFS_USBDEV_ARB_EP3_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP3_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP3_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP3_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP3_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP3_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP3_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP3_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP3_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP3_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW3_WA */
+#define USBFS_USBDEV_ARB_RW3_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW3_WA_MSB */
+#define USBFS_USBDEV_ARB_RW3_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW3_RA */
+#define USBFS_USBDEV_ARB_RW3_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW3_RA_MSB */
+#define USBFS_USBDEV_ARB_RW3_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW3_DR */
+#define USBFS_USBDEV_ARB_RW3_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.CWA */
+#define USBFS_USBDEV_CWA_CWA_Pos 0UL
+#define USBFS_USBDEV_CWA_CWA_Msk 0xFFUL
+/* USBFS_USBDEV.CWA_MSB */
+#define USBFS_USBDEV_CWA_MSB_CWA_MSB_Pos 0UL
+#define USBFS_USBDEV_CWA_MSB_CWA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_EP4_CFG */
+#define USBFS_USBDEV_ARB_EP4_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP4_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP4_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP4_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP4_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP4_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP4_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP4_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP4_INT_EN */
+#define USBFS_USBDEV_ARB_EP4_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP4_SR */
+#define USBFS_USBDEV_ARB_EP4_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP4_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP4_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP4_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP4_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP4_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP4_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP4_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP4_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP4_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW4_WA */
+#define USBFS_USBDEV_ARB_RW4_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW4_WA_MSB */
+#define USBFS_USBDEV_ARB_RW4_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW4_RA */
+#define USBFS_USBDEV_ARB_RW4_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW4_RA_MSB */
+#define USBFS_USBDEV_ARB_RW4_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW4_DR */
+#define USBFS_USBDEV_ARB_RW4_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.DMA_THRES */
+#define USBFS_USBDEV_DMA_THRES_DMA_THS_Pos 0UL
+#define USBFS_USBDEV_DMA_THRES_DMA_THS_Msk 0xFFUL
+/* USBFS_USBDEV.DMA_THRES_MSB */
+#define USBFS_USBDEV_DMA_THRES_MSB_DMA_THS_MSB_Pos 0UL
+#define USBFS_USBDEV_DMA_THRES_MSB_DMA_THS_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_EP5_CFG */
+#define USBFS_USBDEV_ARB_EP5_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP5_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP5_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP5_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP5_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP5_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP5_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP5_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP5_INT_EN */
+#define USBFS_USBDEV_ARB_EP5_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP5_SR */
+#define USBFS_USBDEV_ARB_EP5_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP5_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP5_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP5_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP5_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP5_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP5_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP5_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP5_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP5_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW5_WA */
+#define USBFS_USBDEV_ARB_RW5_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW5_WA_MSB */
+#define USBFS_USBDEV_ARB_RW5_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW5_RA */
+#define USBFS_USBDEV_ARB_RW5_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW5_RA_MSB */
+#define USBFS_USBDEV_ARB_RW5_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW5_DR */
+#define USBFS_USBDEV_ARB_RW5_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.BUS_RST_CNT */
+#define USBFS_USBDEV_BUS_RST_CNT_BUS_RST_CNT_Pos 0UL
+#define USBFS_USBDEV_BUS_RST_CNT_BUS_RST_CNT_Msk 0xFUL
+/* USBFS_USBDEV.ARB_EP6_CFG */
+#define USBFS_USBDEV_ARB_EP6_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP6_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP6_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP6_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP6_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP6_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP6_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP6_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP6_INT_EN */
+#define USBFS_USBDEV_ARB_EP6_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP6_SR */
+#define USBFS_USBDEV_ARB_EP6_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP6_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP6_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP6_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP6_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP6_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP6_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP6_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP6_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP6_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW6_WA */
+#define USBFS_USBDEV_ARB_RW6_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW6_WA_MSB */
+#define USBFS_USBDEV_ARB_RW6_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW6_RA */
+#define USBFS_USBDEV_ARB_RW6_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW6_RA_MSB */
+#define USBFS_USBDEV_ARB_RW6_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW6_DR */
+#define USBFS_USBDEV_ARB_RW6_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_EP7_CFG */
+#define USBFS_USBDEV_ARB_EP7_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP7_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP7_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP7_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP7_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP7_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP7_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP7_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP7_INT_EN */
+#define USBFS_USBDEV_ARB_EP7_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP7_SR */
+#define USBFS_USBDEV_ARB_EP7_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP7_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP7_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP7_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP7_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP7_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP7_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP7_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP7_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP7_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW7_WA */
+#define USBFS_USBDEV_ARB_RW7_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW7_WA_MSB */
+#define USBFS_USBDEV_ARB_RW7_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW7_RA */
+#define USBFS_USBDEV_ARB_RW7_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW7_RA_MSB */
+#define USBFS_USBDEV_ARB_RW7_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW7_DR */
+#define USBFS_USBDEV_ARB_RW7_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_EP8_CFG */
+#define USBFS_USBDEV_ARB_EP8_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP8_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP8_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP8_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP8_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP8_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP8_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP8_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP8_INT_EN */
+#define USBFS_USBDEV_ARB_EP8_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP8_SR */
+#define USBFS_USBDEV_ARB_EP8_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP8_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP8_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP8_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP8_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP8_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP8_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP8_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP8_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP8_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW8_WA */
+#define USBFS_USBDEV_ARB_RW8_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW8_WA_MSB */
+#define USBFS_USBDEV_ARB_RW8_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW8_RA */
+#define USBFS_USBDEV_ARB_RW8_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW8_RA_MSB */
+#define USBFS_USBDEV_ARB_RW8_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW8_DR */
+#define USBFS_USBDEV_ARB_RW8_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.MEM_DATA */
+#define USBFS_USBDEV_MEM_DATA_DR_Pos 0UL
+#define USBFS_USBDEV_MEM_DATA_DR_Msk 0xFFUL
+/* USBFS_USBDEV.SOF16 */
+#define USBFS_USBDEV_SOF16_FRAME_NUMBER16_Pos 0UL
+#define USBFS_USBDEV_SOF16_FRAME_NUMBER16_Msk 0x7FFUL
+/* USBFS_USBDEV.OSCLK_DR16 */
+#define USBFS_USBDEV_OSCLK_DR16_ADDER16_Pos 0UL
+#define USBFS_USBDEV_OSCLK_DR16_ADDER16_Msk 0x7FFFUL
+/* USBFS_USBDEV.ARB_RW1_WA16 */
+#define USBFS_USBDEV_ARB_RW1_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW1_RA16 */
+#define USBFS_USBDEV_ARB_RW1_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW1_DR16 */
+#define USBFS_USBDEV_ARB_RW1_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.ARB_RW2_WA16 */
+#define USBFS_USBDEV_ARB_RW2_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW2_RA16 */
+#define USBFS_USBDEV_ARB_RW2_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW2_DR16 */
+#define USBFS_USBDEV_ARB_RW2_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.ARB_RW3_WA16 */
+#define USBFS_USBDEV_ARB_RW3_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW3_RA16 */
+#define USBFS_USBDEV_ARB_RW3_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW3_DR16 */
+#define USBFS_USBDEV_ARB_RW3_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.CWA16 */
+#define USBFS_USBDEV_CWA16_CWA16_Pos 0UL
+#define USBFS_USBDEV_CWA16_CWA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW4_WA16 */
+#define USBFS_USBDEV_ARB_RW4_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW4_RA16 */
+#define USBFS_USBDEV_ARB_RW4_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW4_DR16 */
+#define USBFS_USBDEV_ARB_RW4_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.DMA_THRES16 */
+#define USBFS_USBDEV_DMA_THRES16_DMA_THS16_Pos 0UL
+#define USBFS_USBDEV_DMA_THRES16_DMA_THS16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW5_WA16 */
+#define USBFS_USBDEV_ARB_RW5_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW5_RA16 */
+#define USBFS_USBDEV_ARB_RW5_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW5_DR16 */
+#define USBFS_USBDEV_ARB_RW5_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.ARB_RW6_WA16 */
+#define USBFS_USBDEV_ARB_RW6_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW6_RA16 */
+#define USBFS_USBDEV_ARB_RW6_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW6_DR16 */
+#define USBFS_USBDEV_ARB_RW6_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.ARB_RW7_WA16 */
+#define USBFS_USBDEV_ARB_RW7_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW7_RA16 */
+#define USBFS_USBDEV_ARB_RW7_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW7_DR16 */
+#define USBFS_USBDEV_ARB_RW7_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.ARB_RW8_WA16 */
+#define USBFS_USBDEV_ARB_RW8_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW8_RA16 */
+#define USBFS_USBDEV_ARB_RW8_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW8_DR16 */
+#define USBFS_USBDEV_ARB_RW8_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_DR16_DR16_Msk 0xFFFFUL
+
+
+/* USBFS_USBLPM.POWER_CTL */
+#define USBFS_USBLPM_POWER_CTL_SUSPEND_Pos 2UL
+#define USBFS_USBLPM_POWER_CTL_SUSPEND_Msk 0x4UL
+#define USBFS_USBLPM_POWER_CTL_DP_UP_EN_Pos 16UL
+#define USBFS_USBLPM_POWER_CTL_DP_UP_EN_Msk 0x10000UL
+#define USBFS_USBLPM_POWER_CTL_DP_BIG_Pos 17UL
+#define USBFS_USBLPM_POWER_CTL_DP_BIG_Msk 0x20000UL
+#define USBFS_USBLPM_POWER_CTL_DP_DOWN_EN_Pos 18UL
+#define USBFS_USBLPM_POWER_CTL_DP_DOWN_EN_Msk 0x40000UL
+#define USBFS_USBLPM_POWER_CTL_DM_UP_EN_Pos 19UL
+#define USBFS_USBLPM_POWER_CTL_DM_UP_EN_Msk 0x80000UL
+#define USBFS_USBLPM_POWER_CTL_DM_BIG_Pos 20UL
+#define USBFS_USBLPM_POWER_CTL_DM_BIG_Msk 0x100000UL
+#define USBFS_USBLPM_POWER_CTL_DM_DOWN_EN_Pos 21UL
+#define USBFS_USBLPM_POWER_CTL_DM_DOWN_EN_Msk 0x200000UL
+#define USBFS_USBLPM_POWER_CTL_ENABLE_DPO_Pos 28UL
+#define USBFS_USBLPM_POWER_CTL_ENABLE_DPO_Msk 0x10000000UL
+#define USBFS_USBLPM_POWER_CTL_ENABLE_DMO_Pos 29UL
+#define USBFS_USBLPM_POWER_CTL_ENABLE_DMO_Msk 0x20000000UL
+/* USBFS_USBLPM.USBIO_CTL */
+#define USBFS_USBLPM_USBIO_CTL_DM_P_Pos 0UL
+#define USBFS_USBLPM_USBIO_CTL_DM_P_Msk 0x7UL
+#define USBFS_USBLPM_USBIO_CTL_DM_M_Pos 3UL
+#define USBFS_USBLPM_USBIO_CTL_DM_M_Msk 0x38UL
+/* USBFS_USBLPM.FLOW_CTL */
+#define USBFS_USBLPM_FLOW_CTL_EP1_ERR_RESP_Pos 0UL
+#define USBFS_USBLPM_FLOW_CTL_EP1_ERR_RESP_Msk 0x1UL
+#define USBFS_USBLPM_FLOW_CTL_EP2_ERR_RESP_Pos 1UL
+#define USBFS_USBLPM_FLOW_CTL_EP2_ERR_RESP_Msk 0x2UL
+#define USBFS_USBLPM_FLOW_CTL_EP3_ERR_RESP_Pos 2UL
+#define USBFS_USBLPM_FLOW_CTL_EP3_ERR_RESP_Msk 0x4UL
+#define USBFS_USBLPM_FLOW_CTL_EP4_ERR_RESP_Pos 3UL
+#define USBFS_USBLPM_FLOW_CTL_EP4_ERR_RESP_Msk 0x8UL
+#define USBFS_USBLPM_FLOW_CTL_EP5_ERR_RESP_Pos 4UL
+#define USBFS_USBLPM_FLOW_CTL_EP5_ERR_RESP_Msk 0x10UL
+#define USBFS_USBLPM_FLOW_CTL_EP6_ERR_RESP_Pos 5UL
+#define USBFS_USBLPM_FLOW_CTL_EP6_ERR_RESP_Msk 0x20UL
+#define USBFS_USBLPM_FLOW_CTL_EP7_ERR_RESP_Pos 6UL
+#define USBFS_USBLPM_FLOW_CTL_EP7_ERR_RESP_Msk 0x40UL
+#define USBFS_USBLPM_FLOW_CTL_EP8_ERR_RESP_Pos 7UL
+#define USBFS_USBLPM_FLOW_CTL_EP8_ERR_RESP_Msk 0x80UL
+/* USBFS_USBLPM.LPM_CTL */
+#define USBFS_USBLPM_LPM_CTL_LPM_EN_Pos 0UL
+#define USBFS_USBLPM_LPM_CTL_LPM_EN_Msk 0x1UL
+#define USBFS_USBLPM_LPM_CTL_LPM_ACK_RESP_Pos 1UL
+#define USBFS_USBLPM_LPM_CTL_LPM_ACK_RESP_Msk 0x2UL
+#define USBFS_USBLPM_LPM_CTL_NYET_EN_Pos 2UL
+#define USBFS_USBLPM_LPM_CTL_NYET_EN_Msk 0x4UL
+#define USBFS_USBLPM_LPM_CTL_SUB_RESP_Pos 4UL
+#define USBFS_USBLPM_LPM_CTL_SUB_RESP_Msk 0x10UL
+/* USBFS_USBLPM.LPM_STAT */
+#define USBFS_USBLPM_LPM_STAT_LPM_BESL_Pos 0UL
+#define USBFS_USBLPM_LPM_STAT_LPM_BESL_Msk 0xFUL
+#define USBFS_USBLPM_LPM_STAT_LPM_REMOTEWAKE_Pos 4UL
+#define USBFS_USBLPM_LPM_STAT_LPM_REMOTEWAKE_Msk 0x10UL
+/* USBFS_USBLPM.INTR_SIE */
+#define USBFS_USBLPM_INTR_SIE_SOF_INTR_Pos 0UL
+#define USBFS_USBLPM_INTR_SIE_SOF_INTR_Msk 0x1UL
+#define USBFS_USBLPM_INTR_SIE_BUS_RESET_INTR_Pos 1UL
+#define USBFS_USBLPM_INTR_SIE_BUS_RESET_INTR_Msk 0x2UL
+#define USBFS_USBLPM_INTR_SIE_EP0_INTR_Pos 2UL
+#define USBFS_USBLPM_INTR_SIE_EP0_INTR_Msk 0x4UL
+#define USBFS_USBLPM_INTR_SIE_LPM_INTR_Pos 3UL
+#define USBFS_USBLPM_INTR_SIE_LPM_INTR_Msk 0x8UL
+#define USBFS_USBLPM_INTR_SIE_RESUME_INTR_Pos 4UL
+#define USBFS_USBLPM_INTR_SIE_RESUME_INTR_Msk 0x10UL
+/* USBFS_USBLPM.INTR_SIE_SET */
+#define USBFS_USBLPM_INTR_SIE_SET_SOF_INTR_SET_Pos 0UL
+#define USBFS_USBLPM_INTR_SIE_SET_SOF_INTR_SET_Msk 0x1UL
+#define USBFS_USBLPM_INTR_SIE_SET_BUS_RESET_INTR_SET_Pos 1UL
+#define USBFS_USBLPM_INTR_SIE_SET_BUS_RESET_INTR_SET_Msk 0x2UL
+#define USBFS_USBLPM_INTR_SIE_SET_EP0_INTR_SET_Pos 2UL
+#define USBFS_USBLPM_INTR_SIE_SET_EP0_INTR_SET_Msk 0x4UL
+#define USBFS_USBLPM_INTR_SIE_SET_LPM_INTR_SET_Pos 3UL
+#define USBFS_USBLPM_INTR_SIE_SET_LPM_INTR_SET_Msk 0x8UL
+#define USBFS_USBLPM_INTR_SIE_SET_RESUME_INTR_SET_Pos 4UL
+#define USBFS_USBLPM_INTR_SIE_SET_RESUME_INTR_SET_Msk 0x10UL
+/* USBFS_USBLPM.INTR_SIE_MASK */
+#define USBFS_USBLPM_INTR_SIE_MASK_SOF_INTR_MASK_Pos 0UL
+#define USBFS_USBLPM_INTR_SIE_MASK_SOF_INTR_MASK_Msk 0x1UL
+#define USBFS_USBLPM_INTR_SIE_MASK_BUS_RESET_INTR_MASK_Pos 1UL
+#define USBFS_USBLPM_INTR_SIE_MASK_BUS_RESET_INTR_MASK_Msk 0x2UL
+#define USBFS_USBLPM_INTR_SIE_MASK_EP0_INTR_MASK_Pos 2UL
+#define USBFS_USBLPM_INTR_SIE_MASK_EP0_INTR_MASK_Msk 0x4UL
+#define USBFS_USBLPM_INTR_SIE_MASK_LPM_INTR_MASK_Pos 3UL
+#define USBFS_USBLPM_INTR_SIE_MASK_LPM_INTR_MASK_Msk 0x8UL
+#define USBFS_USBLPM_INTR_SIE_MASK_RESUME_INTR_MASK_Pos 4UL
+#define USBFS_USBLPM_INTR_SIE_MASK_RESUME_INTR_MASK_Msk 0x10UL
+/* USBFS_USBLPM.INTR_SIE_MASKED */
+#define USBFS_USBLPM_INTR_SIE_MASKED_SOF_INTR_MASKED_Pos 0UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_SOF_INTR_MASKED_Msk 0x1UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_BUS_RESET_INTR_MASKED_Pos 1UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_BUS_RESET_INTR_MASKED_Msk 0x2UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_EP0_INTR_MASKED_Pos 2UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_EP0_INTR_MASKED_Msk 0x4UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_LPM_INTR_MASKED_Pos 3UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_LPM_INTR_MASKED_Msk 0x8UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_RESUME_INTR_MASKED_Pos 4UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_RESUME_INTR_MASKED_Msk 0x10UL
+/* USBFS_USBLPM.INTR_LVL_SEL */
+#define USBFS_USBLPM_INTR_LVL_SEL_SOF_LVL_SEL_Pos 0UL
+#define USBFS_USBLPM_INTR_LVL_SEL_SOF_LVL_SEL_Msk 0x3UL
+#define USBFS_USBLPM_INTR_LVL_SEL_BUS_RESET_LVL_SEL_Pos 2UL
+#define USBFS_USBLPM_INTR_LVL_SEL_BUS_RESET_LVL_SEL_Msk 0xCUL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP0_LVL_SEL_Pos 4UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP0_LVL_SEL_Msk 0x30UL
+#define USBFS_USBLPM_INTR_LVL_SEL_LPM_LVL_SEL_Pos 6UL
+#define USBFS_USBLPM_INTR_LVL_SEL_LPM_LVL_SEL_Msk 0xC0UL
+#define USBFS_USBLPM_INTR_LVL_SEL_RESUME_LVL_SEL_Pos 8UL
+#define USBFS_USBLPM_INTR_LVL_SEL_RESUME_LVL_SEL_Msk 0x300UL
+#define USBFS_USBLPM_INTR_LVL_SEL_ARB_EP_LVL_SEL_Pos 14UL
+#define USBFS_USBLPM_INTR_LVL_SEL_ARB_EP_LVL_SEL_Msk 0xC000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP1_LVL_SEL_Pos 16UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP1_LVL_SEL_Msk 0x30000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP2_LVL_SEL_Pos 18UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP2_LVL_SEL_Msk 0xC0000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP3_LVL_SEL_Pos 20UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP3_LVL_SEL_Msk 0x300000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP4_LVL_SEL_Pos 22UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP4_LVL_SEL_Msk 0xC00000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP5_LVL_SEL_Pos 24UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP5_LVL_SEL_Msk 0x3000000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP6_LVL_SEL_Pos 26UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP6_LVL_SEL_Msk 0xC000000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP7_LVL_SEL_Pos 28UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP7_LVL_SEL_Msk 0x30000000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP8_LVL_SEL_Pos 30UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP8_LVL_SEL_Msk 0xC0000000UL
+/* USBFS_USBLPM.INTR_CAUSE_HI */
+#define USBFS_USBLPM_INTR_CAUSE_HI_SOF_INTR_Pos 0UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_SOF_INTR_Msk 0x1UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_BUS_RESET_INTR_Pos 1UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_BUS_RESET_INTR_Msk 0x2UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP0_INTR_Pos 2UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP0_INTR_Msk 0x4UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_LPM_INTR_Pos 3UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_LPM_INTR_Msk 0x8UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_RESUME_INTR_Pos 4UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_RESUME_INTR_Msk 0x10UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_ARB_EP_INTR_Pos 7UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_ARB_EP_INTR_Msk 0x80UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP1_INTR_Pos 8UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP1_INTR_Msk 0x100UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP2_INTR_Pos 9UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP2_INTR_Msk 0x200UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP3_INTR_Pos 10UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP3_INTR_Msk 0x400UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP4_INTR_Pos 11UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP4_INTR_Msk 0x800UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP5_INTR_Pos 12UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP5_INTR_Msk 0x1000UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP6_INTR_Pos 13UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP6_INTR_Msk 0x2000UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP7_INTR_Pos 14UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP7_INTR_Msk 0x4000UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP8_INTR_Pos 15UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP8_INTR_Msk 0x8000UL
+/* USBFS_USBLPM.INTR_CAUSE_MED */
+#define USBFS_USBLPM_INTR_CAUSE_MED_SOF_INTR_Pos 0UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_SOF_INTR_Msk 0x1UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_BUS_RESET_INTR_Pos 1UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_BUS_RESET_INTR_Msk 0x2UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP0_INTR_Pos 2UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP0_INTR_Msk 0x4UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_LPM_INTR_Pos 3UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_LPM_INTR_Msk 0x8UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_RESUME_INTR_Pos 4UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_RESUME_INTR_Msk 0x10UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_ARB_EP_INTR_Pos 7UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_ARB_EP_INTR_Msk 0x80UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP1_INTR_Pos 8UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP1_INTR_Msk 0x100UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP2_INTR_Pos 9UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP2_INTR_Msk 0x200UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP3_INTR_Pos 10UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP3_INTR_Msk 0x400UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP4_INTR_Pos 11UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP4_INTR_Msk 0x800UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP5_INTR_Pos 12UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP5_INTR_Msk 0x1000UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP6_INTR_Pos 13UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP6_INTR_Msk 0x2000UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP7_INTR_Pos 14UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP7_INTR_Msk 0x4000UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP8_INTR_Pos 15UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP8_INTR_Msk 0x8000UL
+/* USBFS_USBLPM.INTR_CAUSE_LO */
+#define USBFS_USBLPM_INTR_CAUSE_LO_SOF_INTR_Pos 0UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_SOF_INTR_Msk 0x1UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_BUS_RESET_INTR_Pos 1UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_BUS_RESET_INTR_Msk 0x2UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP0_INTR_Pos 2UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP0_INTR_Msk 0x4UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_LPM_INTR_Pos 3UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_LPM_INTR_Msk 0x8UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_RESUME_INTR_Pos 4UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_RESUME_INTR_Msk 0x10UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_ARB_EP_INTR_Pos 7UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_ARB_EP_INTR_Msk 0x80UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP1_INTR_Pos 8UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP1_INTR_Msk 0x100UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP2_INTR_Pos 9UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP2_INTR_Msk 0x200UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP3_INTR_Pos 10UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP3_INTR_Msk 0x400UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP4_INTR_Pos 11UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP4_INTR_Msk 0x800UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP5_INTR_Pos 12UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP5_INTR_Msk 0x1000UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP6_INTR_Pos 13UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP6_INTR_Msk 0x2000UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP7_INTR_Pos 14UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP7_INTR_Msk 0x4000UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP8_INTR_Pos 15UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP8_INTR_Msk 0x8000UL
+/* USBFS_USBLPM.DFT_CTL */
+#define USBFS_USBLPM_DFT_CTL_DDFT_OUT_SEL_Pos 0UL
+#define USBFS_USBLPM_DFT_CTL_DDFT_OUT_SEL_Msk 0x7UL
+#define USBFS_USBLPM_DFT_CTL_DDFT_IN_SEL_Pos 3UL
+#define USBFS_USBLPM_DFT_CTL_DDFT_IN_SEL_Msk 0x18UL
+
+
+/* USBFS_USBHOST.HOST_CTL0 */
+#define USBFS_USBHOST_HOST_CTL0_HOST_Pos 0UL
+#define USBFS_USBHOST_HOST_CTL0_HOST_Msk 0x1UL
+#define USBFS_USBHOST_HOST_CTL0_ENABLE_Pos 31UL
+#define USBFS_USBHOST_HOST_CTL0_ENABLE_Msk 0x80000000UL
+/* USBFS_USBHOST.HOST_CTL1 */
+#define USBFS_USBHOST_HOST_CTL1_CLKSEL_Pos 0UL
+#define USBFS_USBHOST_HOST_CTL1_CLKSEL_Msk 0x1UL
+#define USBFS_USBHOST_HOST_CTL1_USTP_Pos 1UL
+#define USBFS_USBHOST_HOST_CTL1_USTP_Msk 0x2UL
+#define USBFS_USBHOST_HOST_CTL1_RST_Pos 7UL
+#define USBFS_USBHOST_HOST_CTL1_RST_Msk 0x80UL
+/* USBFS_USBHOST.HOST_CTL2 */
+#define USBFS_USBHOST_HOST_CTL2_RETRY_Pos 0UL
+#define USBFS_USBHOST_HOST_CTL2_RETRY_Msk 0x1UL
+#define USBFS_USBHOST_HOST_CTL2_CANCEL_Pos 1UL
+#define USBFS_USBHOST_HOST_CTL2_CANCEL_Msk 0x2UL
+#define USBFS_USBHOST_HOST_CTL2_SOFSTEP_Pos 2UL
+#define USBFS_USBHOST_HOST_CTL2_SOFSTEP_Msk 0x4UL
+#define USBFS_USBHOST_HOST_CTL2_ALIVE_Pos 3UL
+#define USBFS_USBHOST_HOST_CTL2_ALIVE_Msk 0x8UL
+#define USBFS_USBHOST_HOST_CTL2_RESERVED_4_Pos 4UL
+#define USBFS_USBHOST_HOST_CTL2_RESERVED_4_Msk 0x10UL
+#define USBFS_USBHOST_HOST_CTL2_RESERVED_5_Pos 5UL
+#define USBFS_USBHOST_HOST_CTL2_RESERVED_5_Msk 0x20UL
+#define USBFS_USBHOST_HOST_CTL2_TTEST_Pos 6UL
+#define USBFS_USBHOST_HOST_CTL2_TTEST_Msk 0xC0UL
+/* USBFS_USBHOST.HOST_ERR */
+#define USBFS_USBHOST_HOST_ERR_HS_Pos 0UL
+#define USBFS_USBHOST_HOST_ERR_HS_Msk 0x3UL
+#define USBFS_USBHOST_HOST_ERR_STUFF_Pos 2UL
+#define USBFS_USBHOST_HOST_ERR_STUFF_Msk 0x4UL
+#define USBFS_USBHOST_HOST_ERR_TGERR_Pos 3UL
+#define USBFS_USBHOST_HOST_ERR_TGERR_Msk 0x8UL
+#define USBFS_USBHOST_HOST_ERR_CRC_Pos 4UL
+#define USBFS_USBHOST_HOST_ERR_CRC_Msk 0x10UL
+#define USBFS_USBHOST_HOST_ERR_TOUT_Pos 5UL
+#define USBFS_USBHOST_HOST_ERR_TOUT_Msk 0x20UL
+#define USBFS_USBHOST_HOST_ERR_RERR_Pos 6UL
+#define USBFS_USBHOST_HOST_ERR_RERR_Msk 0x40UL
+#define USBFS_USBHOST_HOST_ERR_LSTSOF_Pos 7UL
+#define USBFS_USBHOST_HOST_ERR_LSTSOF_Msk 0x80UL
+/* USBFS_USBHOST.HOST_STATUS */
+#define USBFS_USBHOST_HOST_STATUS_CSTAT_Pos 0UL
+#define USBFS_USBHOST_HOST_STATUS_CSTAT_Msk 0x1UL
+#define USBFS_USBHOST_HOST_STATUS_TMODE_Pos 1UL
+#define USBFS_USBHOST_HOST_STATUS_TMODE_Msk 0x2UL
+#define USBFS_USBHOST_HOST_STATUS_SUSP_Pos 2UL
+#define USBFS_USBHOST_HOST_STATUS_SUSP_Msk 0x4UL
+#define USBFS_USBHOST_HOST_STATUS_SOFBUSY_Pos 3UL
+#define USBFS_USBHOST_HOST_STATUS_SOFBUSY_Msk 0x8UL
+#define USBFS_USBHOST_HOST_STATUS_URST_Pos 4UL
+#define USBFS_USBHOST_HOST_STATUS_URST_Msk 0x10UL
+#define USBFS_USBHOST_HOST_STATUS_RESERVED_5_Pos 5UL
+#define USBFS_USBHOST_HOST_STATUS_RESERVED_5_Msk 0x20UL
+#define USBFS_USBHOST_HOST_STATUS_RSTBUSY_Pos 6UL
+#define USBFS_USBHOST_HOST_STATUS_RSTBUSY_Msk 0x40UL
+#define USBFS_USBHOST_HOST_STATUS_CLKSEL_ST_Pos 7UL
+#define USBFS_USBHOST_HOST_STATUS_CLKSEL_ST_Msk 0x80UL
+#define USBFS_USBHOST_HOST_STATUS_HOST_ST_Pos 8UL
+#define USBFS_USBHOST_HOST_STATUS_HOST_ST_Msk 0x100UL
+/* USBFS_USBHOST.HOST_FCOMP */
+#define USBFS_USBHOST_HOST_FCOMP_FRAMECOMP_Pos 0UL
+#define USBFS_USBHOST_HOST_FCOMP_FRAMECOMP_Msk 0xFFUL
+/* USBFS_USBHOST.HOST_RTIMER */
+#define USBFS_USBHOST_HOST_RTIMER_RTIMER_Pos 0UL
+#define USBFS_USBHOST_HOST_RTIMER_RTIMER_Msk 0x3FFFFUL
+/* USBFS_USBHOST.HOST_ADDR */
+#define USBFS_USBHOST_HOST_ADDR_ADDRESS_Pos 0UL
+#define USBFS_USBHOST_HOST_ADDR_ADDRESS_Msk 0x7FUL
+/* USBFS_USBHOST.HOST_EOF */
+#define USBFS_USBHOST_HOST_EOF_EOF_Pos 0UL
+#define USBFS_USBHOST_HOST_EOF_EOF_Msk 0x3FFFUL
+/* USBFS_USBHOST.HOST_FRAME */
+#define USBFS_USBHOST_HOST_FRAME_FRAME_Pos 0UL
+#define USBFS_USBHOST_HOST_FRAME_FRAME_Msk 0x7FFUL
+/* USBFS_USBHOST.HOST_TOKEN */
+#define USBFS_USBHOST_HOST_TOKEN_ENDPT_Pos 0UL
+#define USBFS_USBHOST_HOST_TOKEN_ENDPT_Msk 0xFUL
+#define USBFS_USBHOST_HOST_TOKEN_TKNEN_Pos 4UL
+#define USBFS_USBHOST_HOST_TOKEN_TKNEN_Msk 0x70UL
+#define USBFS_USBHOST_HOST_TOKEN_TGGL_Pos 8UL
+#define USBFS_USBHOST_HOST_TOKEN_TGGL_Msk 0x100UL
+/* USBFS_USBHOST.HOST_EP1_CTL */
+#define USBFS_USBHOST_HOST_EP1_CTL_PKS1_Pos 0UL
+#define USBFS_USBHOST_HOST_EP1_CTL_PKS1_Msk 0x1FFUL
+#define USBFS_USBHOST_HOST_EP1_CTL_NULLE_Pos 10UL
+#define USBFS_USBHOST_HOST_EP1_CTL_NULLE_Msk 0x400UL
+#define USBFS_USBHOST_HOST_EP1_CTL_DMAE_Pos 11UL
+#define USBFS_USBHOST_HOST_EP1_CTL_DMAE_Msk 0x800UL
+#define USBFS_USBHOST_HOST_EP1_CTL_DIR_Pos 12UL
+#define USBFS_USBHOST_HOST_EP1_CTL_DIR_Msk 0x1000UL
+#define USBFS_USBHOST_HOST_EP1_CTL_BFINI_Pos 15UL
+#define USBFS_USBHOST_HOST_EP1_CTL_BFINI_Msk 0x8000UL
+/* USBFS_USBHOST.HOST_EP1_STATUS */
+#define USBFS_USBHOST_HOST_EP1_STATUS_SIZE1_Pos 0UL
+#define USBFS_USBHOST_HOST_EP1_STATUS_SIZE1_Msk 0x1FFUL
+#define USBFS_USBHOST_HOST_EP1_STATUS_VAL_DATA_Pos 16UL
+#define USBFS_USBHOST_HOST_EP1_STATUS_VAL_DATA_Msk 0x10000UL
+#define USBFS_USBHOST_HOST_EP1_STATUS_INI_ST_Pos 17UL
+#define USBFS_USBHOST_HOST_EP1_STATUS_INI_ST_Msk 0x20000UL
+#define USBFS_USBHOST_HOST_EP1_STATUS_RESERVED_18_Pos 18UL
+#define USBFS_USBHOST_HOST_EP1_STATUS_RESERVED_18_Msk 0x40000UL
+/* USBFS_USBHOST.HOST_EP1_RW1_DR */
+#define USBFS_USBHOST_HOST_EP1_RW1_DR_BFDT8_Pos 0UL
+#define USBFS_USBHOST_HOST_EP1_RW1_DR_BFDT8_Msk 0xFFUL
+/* USBFS_USBHOST.HOST_EP1_RW2_DR */
+#define USBFS_USBHOST_HOST_EP1_RW2_DR_BFDT16_Pos 0UL
+#define USBFS_USBHOST_HOST_EP1_RW2_DR_BFDT16_Msk 0xFFFFUL
+/* USBFS_USBHOST.HOST_EP2_CTL */
+#define USBFS_USBHOST_HOST_EP2_CTL_PKS2_Pos 0UL
+#define USBFS_USBHOST_HOST_EP2_CTL_PKS2_Msk 0x7FUL
+#define USBFS_USBHOST_HOST_EP2_CTL_NULLE_Pos 10UL
+#define USBFS_USBHOST_HOST_EP2_CTL_NULLE_Msk 0x400UL
+#define USBFS_USBHOST_HOST_EP2_CTL_DMAE_Pos 11UL
+#define USBFS_USBHOST_HOST_EP2_CTL_DMAE_Msk 0x800UL
+#define USBFS_USBHOST_HOST_EP2_CTL_DIR_Pos 12UL
+#define USBFS_USBHOST_HOST_EP2_CTL_DIR_Msk 0x1000UL
+#define USBFS_USBHOST_HOST_EP2_CTL_BFINI_Pos 15UL
+#define USBFS_USBHOST_HOST_EP2_CTL_BFINI_Msk 0x8000UL
+/* USBFS_USBHOST.HOST_EP2_STATUS */
+#define USBFS_USBHOST_HOST_EP2_STATUS_SIZE2_Pos 0UL
+#define USBFS_USBHOST_HOST_EP2_STATUS_SIZE2_Msk 0x7FUL
+#define USBFS_USBHOST_HOST_EP2_STATUS_VAL_DATA_Pos 16UL
+#define USBFS_USBHOST_HOST_EP2_STATUS_VAL_DATA_Msk 0x10000UL
+#define USBFS_USBHOST_HOST_EP2_STATUS_INI_ST_Pos 17UL
+#define USBFS_USBHOST_HOST_EP2_STATUS_INI_ST_Msk 0x20000UL
+#define USBFS_USBHOST_HOST_EP2_STATUS_RESERVED_18_Pos 18UL
+#define USBFS_USBHOST_HOST_EP2_STATUS_RESERVED_18_Msk 0x40000UL
+/* USBFS_USBHOST.HOST_EP2_RW1_DR */
+#define USBFS_USBHOST_HOST_EP2_RW1_DR_BFDT8_Pos 0UL
+#define USBFS_USBHOST_HOST_EP2_RW1_DR_BFDT8_Msk 0xFFUL
+/* USBFS_USBHOST.HOST_EP2_RW2_DR */
+#define USBFS_USBHOST_HOST_EP2_RW2_DR_BFDT16_Pos 0UL
+#define USBFS_USBHOST_HOST_EP2_RW2_DR_BFDT16_Msk 0xFFFFUL
+/* USBFS_USBHOST.HOST_LVL1_SEL */
+#define USBFS_USBHOST_HOST_LVL1_SEL_SOFIRQ_SEL_Pos 0UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_SOFIRQ_SEL_Msk 0x3UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_DIRQ_SEL_Pos 2UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_DIRQ_SEL_Msk 0xCUL
+#define USBFS_USBHOST_HOST_LVL1_SEL_CNNIRQ_SEL_Pos 4UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_CNNIRQ_SEL_Msk 0x30UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_CMPIRQ_SEL_Pos 6UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_CMPIRQ_SEL_Msk 0xC0UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_URIRQ_SEL_Pos 8UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_URIRQ_SEL_Msk 0x300UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_RWKIRQ_SEL_Pos 10UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_RWKIRQ_SEL_Msk 0xC00UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_RESERVED_13_12_Pos 12UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_RESERVED_13_12_Msk 0x3000UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_TCAN_SEL_Pos 14UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_TCAN_SEL_Msk 0xC000UL
+/* USBFS_USBHOST.HOST_LVL2_SEL */
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP1_DRQ_SEL_Pos 4UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP1_DRQ_SEL_Msk 0x30UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP1_SPK_SEL_Pos 6UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP1_SPK_SEL_Msk 0xC0UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP2_DRQ_SEL_Pos 8UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP2_DRQ_SEL_Msk 0x300UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP2_SPK_SEL_Pos 10UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP2_SPK_SEL_Msk 0xC00UL
+/* USBFS_USBHOST.INTR_USBHOST_CAUSE_HI */
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_SOFIRQ_INT_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_SOFIRQ_INT_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_DIRQ_INT_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_DIRQ_INT_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_CNNIRQ_INT_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_CNNIRQ_INT_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_CMPIRQ_INT_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_CMPIRQ_INT_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_URIRQ_INT_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_URIRQ_INT_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_RWKIRQ_INT_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_RWKIRQ_INT_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_TCAN_INT_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_TCAN_INT_Msk 0x80UL
+/* USBFS_USBHOST.INTR_USBHOST_CAUSE_MED */
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_SOFIRQ_INT_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_SOFIRQ_INT_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_DIRQ_INT_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_DIRQ_INT_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_CNNIRQ_INT_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_CNNIRQ_INT_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_CMPIRQ_INT_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_CMPIRQ_INT_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_URIRQ_INT_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_URIRQ_INT_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_RWKIRQ_INT_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_RWKIRQ_INT_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_TCAN_INT_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_TCAN_INT_Msk 0x80UL
+/* USBFS_USBHOST.INTR_USBHOST_CAUSE_LO */
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_SOFIRQ_INT_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_SOFIRQ_INT_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_DIRQ_INT_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_DIRQ_INT_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_CNNIRQ_INT_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_CNNIRQ_INT_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_CMPIRQ_INT_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_CMPIRQ_INT_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_URIRQ_INT_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_URIRQ_INT_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_RWKIRQ_INT_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_RWKIRQ_INT_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_TCAN_INT_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_TCAN_INT_Msk 0x80UL
+/* USBFS_USBHOST.INTR_HOST_EP_CAUSE_HI */
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP1DRQ_INT_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP1DRQ_INT_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP1SPK_INT_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP1SPK_INT_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP2DRQ_INT_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP2DRQ_INT_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP2SPK_INT_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP2SPK_INT_Msk 0x20UL
+/* USBFS_USBHOST.INTR_HOST_EP_CAUSE_MED */
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP1DRQ_INT_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP1DRQ_INT_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP1SPK_INT_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP1SPK_INT_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP2DRQ_INT_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP2DRQ_INT_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP2SPK_INT_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP2SPK_INT_Msk 0x20UL
+/* USBFS_USBHOST.INTR_HOST_EP_CAUSE_LO */
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP1DRQ_INT_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP1DRQ_INT_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP1SPK_INT_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP1SPK_INT_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP2DRQ_INT_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP2DRQ_INT_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP2SPK_INT_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP2SPK_INT_Msk 0x20UL
+/* USBFS_USBHOST.INTR_USBHOST */
+#define USBFS_USBHOST_INTR_USBHOST_SOFIRQ_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_SOFIRQ_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_DIRQ_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_DIRQ_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_CNNIRQ_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_CNNIRQ_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_CMPIRQ_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_CMPIRQ_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_URIRQ_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_URIRQ_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_RWKIRQ_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_RWKIRQ_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_TCAN_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_TCAN_Msk 0x80UL
+/* USBFS_USBHOST.INTR_USBHOST_SET */
+#define USBFS_USBHOST_INTR_USBHOST_SET_SOFIRQS_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_SOFIRQS_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_DIRQS_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_DIRQS_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_CNNIRQS_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_CNNIRQS_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_CMPIRQS_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_CMPIRQS_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_URIRQS_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_URIRQS_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_RWKIRQS_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_RWKIRQS_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_TCANS_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_TCANS_Msk 0x80UL
+/* USBFS_USBHOST.INTR_USBHOST_MASK */
+#define USBFS_USBHOST_INTR_USBHOST_MASK_SOFIRQM_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_SOFIRQM_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_DIRQM_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_DIRQM_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_CNNIRQM_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_CNNIRQM_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_CMPIRQM_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_CMPIRQM_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_URIRQM_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_URIRQM_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_RWKIRQM_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_RWKIRQM_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_TCANM_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_TCANM_Msk 0x80UL
+/* USBFS_USBHOST.INTR_USBHOST_MASKED */
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_SOFIRQED_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_SOFIRQED_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_DIRQED_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_DIRQED_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_CNNIRQED_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_CNNIRQED_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_CMPIRQED_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_CMPIRQED_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_URIRQED_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_URIRQED_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_RWKIRQED_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_RWKIRQED_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_TCANED_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_TCANED_Msk 0x80UL
+/* USBFS_USBHOST.INTR_HOST_EP */
+#define USBFS_USBHOST_INTR_HOST_EP_EP1DRQ_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP1DRQ_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP1SPK_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP1SPK_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP2DRQ_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP2DRQ_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP2SPK_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP2SPK_Msk 0x20UL
+/* USBFS_USBHOST.INTR_HOST_EP_SET */
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP1DRQS_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP1DRQS_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP1SPKS_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP1SPKS_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP2DRQS_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP2DRQS_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP2SPKS_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP2SPKS_Msk 0x20UL
+/* USBFS_USBHOST.INTR_HOST_EP_MASK */
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP1DRQM_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP1DRQM_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP1SPKM_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP1SPKM_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP2DRQM_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP2DRQM_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP2SPKM_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP2SPKM_Msk 0x20UL
+/* USBFS_USBHOST.INTR_HOST_EP_MASKED */
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP1DRQED_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP1DRQED_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP1SPKED_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP1SPKED_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP2DRQED_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP2DRQED_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP2SPKED_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP2SPKED_Msk 0x20UL
+/* USBFS_USBHOST.HOST_DMA_ENBL */
+#define USBFS_USBHOST_HOST_DMA_ENBL_DM_EP1DRQE_Pos 2UL
+#define USBFS_USBHOST_HOST_DMA_ENBL_DM_EP1DRQE_Msk 0x4UL
+#define USBFS_USBHOST_HOST_DMA_ENBL_DM_EP2DRQE_Pos 3UL
+#define USBFS_USBHOST_HOST_DMA_ENBL_DM_EP2DRQE_Msk 0x8UL
+/* USBFS_USBHOST.HOST_EP1_BLK */
+#define USBFS_USBHOST_HOST_EP1_BLK_BLK_NUM_Pos 16UL
+#define USBFS_USBHOST_HOST_EP1_BLK_BLK_NUM_Msk 0xFFFF0000UL
+/* USBFS_USBHOST.HOST_EP2_BLK */
+#define USBFS_USBHOST_HOST_EP2_BLK_BLK_NUM_Pos 16UL
+#define USBFS_USBHOST_HOST_EP2_BLK_BLK_NUM_Msk 0xFFFF0000UL
+
+
+#endif /* _CYIP_USBFS_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/platform_base_address.h b/platform/ext/target/psoc64/Device/Include/platform_base_address.h
new file mode 100644
index 0000000000..f90be772d9
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/platform_base_address.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.01 Device\_Template_Vendor\Vendor\Device\Include\Device.h
+ */
+
+#ifndef __PLATFORM_BASE_ADDRESS_H__
+#define __PLATFORM_BASE_ADDRESS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+/* Non-Secure Peripheral and SRAM base address */
+/* Secure Peripheral and SRAM base address */
+
+/* SRAM MPC ranges and limits */
+/* Internal memory */
+
+/* Code SRAM memory */
+
+/* QSPI Flash memory */
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLATFORM_BASE_ADDRESS_H__ */
diff --git a/platform/ext/target/psoc64/Device/Include/platform_description.h b/platform/ext/target/psoc64/Device/Include/platform_description.h
new file mode 100644
index 0000000000..e5760c76f6
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/platform_description.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __PLATFORM_DESCRIPTION_H__
+#define __PLATFORM_DESCRIPTION_H__
+
+#include "platform_base_address.h"
+#include "platform_pins.h"
+#include "platform_regs.h"
+#include "cmsis.h"
+
+#endif /* __PLATFORM_DESCRIPTION_H__ */
diff --git a/platform/ext/target/psoc64/Device/Include/platform_pins.h b/platform/ext/target/psoc64/Device/Include/platform_pins.h
new file mode 100644
index 0000000000..d883093135
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/platform_pins.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_pins.h
+ * \brief This file defines all the pins for this platform.
+ */
+
+#ifndef __PLATFORM_PINS__
+#define __PLATFORM_PINS__
+
+#endif /* __PLATFORM_PINS__ */
diff --git a/platform/ext/target/psoc64/Device/Include/platform_regs.h b/platform/ext/target/psoc64/Device/Include/platform_regs.h
new file mode 100644
index 0000000000..1fddeae88b
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/platform_regs.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2016-2018 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __PLATFORM_REGS_H__
+#define __PLATFORM_REGS_H__
+
+/* ARM APB PPCEXP1 peripherals definition */
+/* End of ARM AHB PPC0 peripherals definition */
+
+#endif /* __PLATFORM_REGS_H__ */
diff --git a/platform/ext/target/psoc64/Device/Include/psoc6_01_config.h b/platform/ext/target/psoc64/Device/Include/psoc6_01_config.h
new file mode 100644
index 0000000000..321f0398b4
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/psoc6_01_config.h
@@ -0,0 +1,3097 @@
+/***************************************************************************//**
+* \file psoc6_01_config.h
+*
+* \brief
+* PSoC6_01 device configuration header
+*
+* \note
+* Generator version: 1.5.0.1286
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _PSOC6_01_CONFIG_H_
+#define _PSOC6_01_CONFIG_H_
+
+/* Clock Connections */
+typedef enum
+{
+ PCLK_SCB0_CLOCK = 0x0000u, /* scb[0].clock */
+ PCLK_SCB1_CLOCK = 0x0001u, /* scb[1].clock */
+ PCLK_SCB2_CLOCK = 0x0002u, /* scb[2].clock */
+ PCLK_SCB3_CLOCK = 0x0003u, /* scb[3].clock */
+ PCLK_SCB4_CLOCK = 0x0004u, /* scb[4].clock */
+ PCLK_SCB5_CLOCK = 0x0005u, /* scb[5].clock */
+ PCLK_SCB6_CLOCK = 0x0006u, /* scb[6].clock */
+ PCLK_SCB7_CLOCK = 0x0007u, /* scb[7].clock */
+ PCLK_SCB8_CLOCK = 0x0008u, /* scb[8].clock */
+ PCLK_UDB_CLOCKS0 = 0x0009u, /* udb.clocks[0] */
+ PCLK_UDB_CLOCKS1 = 0x000Au, /* udb.clocks[1] */
+ PCLK_UDB_CLOCKS2 = 0x000Bu, /* udb.clocks[2] */
+ PCLK_UDB_CLOCKS3 = 0x000Cu, /* udb.clocks[3] */
+ PCLK_UDB_CLOCKS4 = 0x000Du, /* udb.clocks[4] */
+ PCLK_UDB_CLOCKS5 = 0x000Eu, /* udb.clocks[5] */
+ PCLK_UDB_CLOCKS6 = 0x000Fu, /* udb.clocks[6] */
+ PCLK_UDB_CLOCKS7 = 0x0010u, /* udb.clocks[7] */
+ PCLK_SMARTIO8_CLOCK = 0x0011u, /* smartio[8].clock */
+ PCLK_SMARTIO9_CLOCK = 0x0012u, /* smartio[9].clock */
+ PCLK_TCPWM0_CLOCKS0 = 0x0013u, /* tcpwm[0].clocks[0] */
+ PCLK_TCPWM0_CLOCKS1 = 0x0014u, /* tcpwm[0].clocks[1] */
+ PCLK_TCPWM0_CLOCKS2 = 0x0015u, /* tcpwm[0].clocks[2] */
+ PCLK_TCPWM0_CLOCKS3 = 0x0016u, /* tcpwm[0].clocks[3] */
+ PCLK_TCPWM0_CLOCKS4 = 0x0017u, /* tcpwm[0].clocks[4] */
+ PCLK_TCPWM0_CLOCKS5 = 0x0018u, /* tcpwm[0].clocks[5] */
+ PCLK_TCPWM0_CLOCKS6 = 0x0019u, /* tcpwm[0].clocks[6] */
+ PCLK_TCPWM0_CLOCKS7 = 0x001Au, /* tcpwm[0].clocks[7] */
+ PCLK_TCPWM1_CLOCKS0 = 0x001Bu, /* tcpwm[1].clocks[0] */
+ PCLK_TCPWM1_CLOCKS1 = 0x001Cu, /* tcpwm[1].clocks[1] */
+ PCLK_TCPWM1_CLOCKS2 = 0x001Du, /* tcpwm[1].clocks[2] */
+ PCLK_TCPWM1_CLOCKS3 = 0x001Eu, /* tcpwm[1].clocks[3] */
+ PCLK_TCPWM1_CLOCKS4 = 0x001Fu, /* tcpwm[1].clocks[4] */
+ PCLK_TCPWM1_CLOCKS5 = 0x0020u, /* tcpwm[1].clocks[5] */
+ PCLK_TCPWM1_CLOCKS6 = 0x0021u, /* tcpwm[1].clocks[6] */
+ PCLK_TCPWM1_CLOCKS7 = 0x0022u, /* tcpwm[1].clocks[7] */
+ PCLK_TCPWM1_CLOCKS8 = 0x0023u, /* tcpwm[1].clocks[8] */
+ PCLK_TCPWM1_CLOCKS9 = 0x0024u, /* tcpwm[1].clocks[9] */
+ PCLK_TCPWM1_CLOCKS10 = 0x0025u, /* tcpwm[1].clocks[10] */
+ PCLK_TCPWM1_CLOCKS11 = 0x0026u, /* tcpwm[1].clocks[11] */
+ PCLK_TCPWM1_CLOCKS12 = 0x0027u, /* tcpwm[1].clocks[12] */
+ PCLK_TCPWM1_CLOCKS13 = 0x0028u, /* tcpwm[1].clocks[13] */
+ PCLK_TCPWM1_CLOCKS14 = 0x0029u, /* tcpwm[1].clocks[14] */
+ PCLK_TCPWM1_CLOCKS15 = 0x002Au, /* tcpwm[1].clocks[15] */
+ PCLK_TCPWM1_CLOCKS16 = 0x002Bu, /* tcpwm[1].clocks[16] */
+ PCLK_TCPWM1_CLOCKS17 = 0x002Cu, /* tcpwm[1].clocks[17] */
+ PCLK_TCPWM1_CLOCKS18 = 0x002Du, /* tcpwm[1].clocks[18] */
+ PCLK_TCPWM1_CLOCKS19 = 0x002Eu, /* tcpwm[1].clocks[19] */
+ PCLK_TCPWM1_CLOCKS20 = 0x002Fu, /* tcpwm[1].clocks[20] */
+ PCLK_TCPWM1_CLOCKS21 = 0x0030u, /* tcpwm[1].clocks[21] */
+ PCLK_TCPWM1_CLOCKS22 = 0x0031u, /* tcpwm[1].clocks[22] */
+ PCLK_TCPWM1_CLOCKS23 = 0x0032u, /* tcpwm[1].clocks[23] */
+ PCLK_CSD_CLOCK = 0x0033u, /* csd.clock */
+ PCLK_LCD_CLOCK = 0x0034u, /* lcd.clock */
+ PCLK_PROFILE_CLOCK_PROFILE = 0x0035u, /* profile.clock_profile */
+ PCLK_CPUSS_CLOCK_TRACE_IN = 0x0036u, /* cpuss.clock_trace_in */
+ PCLK_PASS_CLOCK_CTDAC = 0x0037u, /* pass.clock_ctdac */
+ PCLK_PASS_CLOCK_PUMP_PERI = 0x0038u, /* pass.clock_pump_peri */
+ PCLK_PASS_CLOCK_SAR = 0x0039u, /* pass.clock_sar */
+ PCLK_USB_CLOCK_DEV_BRS = 0x003Au /* usb.clock_dev_brs */
+} en_clk_dst_t;
+
+/* Trigger Group */
+/* This section contains the enums related to the Trigger multiplexer (TrigMux) driver.
+* Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details.
+*/
+/* Trigger Group Inputs */
+/* Trigger Input Group 0 - DMA Request Assignments */
+typedef enum
+{
+ TRIG0_IN_CPUSS_ZERO = 0x00000000u, /* cpuss.zero */
+ TRIG0_IN_TR_GROUP10_OUTPUT0 = 0x00000001u, /* tr_group[10].output[0] */
+ TRIG0_IN_TR_GROUP10_OUTPUT1 = 0x00000002u, /* tr_group[10].output[1] */
+ TRIG0_IN_TR_GROUP10_OUTPUT2 = 0x00000003u, /* tr_group[10].output[2] */
+ TRIG0_IN_TR_GROUP10_OUTPUT3 = 0x00000004u, /* tr_group[10].output[3] */
+ TRIG0_IN_TR_GROUP10_OUTPUT4 = 0x00000005u, /* tr_group[10].output[4] */
+ TRIG0_IN_TR_GROUP10_OUTPUT5 = 0x00000006u, /* tr_group[10].output[5] */
+ TRIG0_IN_TR_GROUP10_OUTPUT6 = 0x00000007u, /* tr_group[10].output[6] */
+ TRIG0_IN_TR_GROUP10_OUTPUT7 = 0x00000008u, /* tr_group[10].output[7] */
+ TRIG0_IN_TR_GROUP11_OUTPUT0 = 0x00000009u, /* tr_group[11].output[0] */
+ TRIG0_IN_TR_GROUP11_OUTPUT1 = 0x0000000Au, /* tr_group[11].output[1] */
+ TRIG0_IN_TR_GROUP11_OUTPUT2 = 0x0000000Bu, /* tr_group[11].output[2] */
+ TRIG0_IN_TR_GROUP11_OUTPUT3 = 0x0000000Cu, /* tr_group[11].output[3] */
+ TRIG0_IN_TR_GROUP11_OUTPUT4 = 0x0000000Du, /* tr_group[11].output[4] */
+ TRIG0_IN_TR_GROUP11_OUTPUT5 = 0x0000000Eu, /* tr_group[11].output[5] */
+ TRIG0_IN_TR_GROUP11_OUTPUT6 = 0x0000000Fu, /* tr_group[11].output[6] */
+ TRIG0_IN_TR_GROUP11_OUTPUT7 = 0x00000010u, /* tr_group[11].output[7] */
+ TRIG0_IN_TR_GROUP11_OUTPUT8 = 0x00000011u, /* tr_group[11].output[8] */
+ TRIG0_IN_TR_GROUP11_OUTPUT9 = 0x00000012u, /* tr_group[11].output[9] */
+ TRIG0_IN_TR_GROUP11_OUTPUT10 = 0x00000013u, /* tr_group[11].output[10] */
+ TRIG0_IN_TR_GROUP11_OUTPUT11 = 0x00000014u, /* tr_group[11].output[11] */
+ TRIG0_IN_TR_GROUP11_OUTPUT12 = 0x00000015u, /* tr_group[11].output[12] */
+ TRIG0_IN_TR_GROUP11_OUTPUT13 = 0x00000016u, /* tr_group[11].output[13] */
+ TRIG0_IN_TR_GROUP11_OUTPUT14 = 0x00000017u, /* tr_group[11].output[14] */
+ TRIG0_IN_TR_GROUP11_OUTPUT15 = 0x00000018u, /* tr_group[11].output[15] */
+ TRIG0_IN_TR_GROUP12_OUTPUT8 = 0x00000019u, /* tr_group[12].output[8] */
+ TRIG0_IN_TR_GROUP12_OUTPUT9 = 0x0000001Au, /* tr_group[12].output[9] */
+ TRIG0_IN_TR_GROUP13_OUTPUT0 = 0x0000001Bu, /* tr_group[13].output[0] */
+ TRIG0_IN_TR_GROUP13_OUTPUT1 = 0x0000001Cu, /* tr_group[13].output[1] */
+ TRIG0_IN_TR_GROUP13_OUTPUT2 = 0x0000001Du, /* tr_group[13].output[2] */
+ TRIG0_IN_TR_GROUP13_OUTPUT3 = 0x0000001Eu, /* tr_group[13].output[3] */
+ TRIG0_IN_TR_GROUP13_OUTPUT4 = 0x0000001Fu, /* tr_group[13].output[4] */
+ TRIG0_IN_TR_GROUP13_OUTPUT5 = 0x00000020u, /* tr_group[13].output[5] */
+ TRIG0_IN_TR_GROUP13_OUTPUT6 = 0x00000021u, /* tr_group[13].output[6] */
+ TRIG0_IN_TR_GROUP13_OUTPUT7 = 0x00000022u, /* tr_group[13].output[7] */
+ TRIG0_IN_TR_GROUP13_OUTPUT8 = 0x00000023u, /* tr_group[13].output[8] */
+ TRIG0_IN_TR_GROUP13_OUTPUT9 = 0x00000024u, /* tr_group[13].output[9] */
+ TRIG0_IN_TR_GROUP13_OUTPUT10 = 0x00000025u, /* tr_group[13].output[10] */
+ TRIG0_IN_TR_GROUP13_OUTPUT11 = 0x00000026u, /* tr_group[13].output[11] */
+ TRIG0_IN_TR_GROUP13_OUTPUT12 = 0x00000027u, /* tr_group[13].output[12] */
+ TRIG0_IN_TR_GROUP13_OUTPUT13 = 0x00000028u, /* tr_group[13].output[13] */
+ TRIG0_IN_TR_GROUP13_OUTPUT14 = 0x00000029u, /* tr_group[13].output[14] */
+ TRIG0_IN_TR_GROUP13_OUTPUT15 = 0x0000002Au, /* tr_group[13].output[15] */
+ TRIG0_IN_TR_GROUP14_OUTPUT0 = 0x0000002Bu, /* tr_group[14].output[0] */
+ TRIG0_IN_TR_GROUP14_OUTPUT1 = 0x0000002Cu, /* tr_group[14].output[1] */
+ TRIG0_IN_TR_GROUP14_OUTPUT2 = 0x0000002Du, /* tr_group[14].output[2] */
+ TRIG0_IN_TR_GROUP14_OUTPUT3 = 0x0000002Eu, /* tr_group[14].output[3] */
+ TRIG0_IN_TR_GROUP14_OUTPUT4 = 0x0000002Fu, /* tr_group[14].output[4] */
+ TRIG0_IN_TR_GROUP14_OUTPUT5 = 0x00000030u, /* tr_group[14].output[5] */
+ TRIG0_IN_TR_GROUP14_OUTPUT6 = 0x00000031u, /* tr_group[14].output[6] */
+ TRIG0_IN_TR_GROUP14_OUTPUT7 = 0x00000032u /* tr_group[14].output[7] */
+} en_trig_input_grp0_t;
+
+/* Trigger Input Group 1 - DMA Request Assignments */
+typedef enum
+{
+ TRIG1_IN_CPUSS_ZERO = 0x00000100u, /* cpuss.zero */
+ TRIG1_IN_TR_GROUP10_OUTPUT0 = 0x00000101u, /* tr_group[10].output[0] */
+ TRIG1_IN_TR_GROUP10_OUTPUT1 = 0x00000102u, /* tr_group[10].output[1] */
+ TRIG1_IN_TR_GROUP10_OUTPUT2 = 0x00000103u, /* tr_group[10].output[2] */
+ TRIG1_IN_TR_GROUP10_OUTPUT3 = 0x00000104u, /* tr_group[10].output[3] */
+ TRIG1_IN_TR_GROUP10_OUTPUT4 = 0x00000105u, /* tr_group[10].output[4] */
+ TRIG1_IN_TR_GROUP10_OUTPUT5 = 0x00000106u, /* tr_group[10].output[5] */
+ TRIG1_IN_TR_GROUP10_OUTPUT6 = 0x00000107u, /* tr_group[10].output[6] */
+ TRIG1_IN_TR_GROUP10_OUTPUT7 = 0x00000108u, /* tr_group[10].output[7] */
+ TRIG1_IN_TR_GROUP11_OUTPUT0 = 0x00000109u, /* tr_group[11].output[0] */
+ TRIG1_IN_TR_GROUP11_OUTPUT1 = 0x0000010Au, /* tr_group[11].output[1] */
+ TRIG1_IN_TR_GROUP11_OUTPUT2 = 0x0000010Bu, /* tr_group[11].output[2] */
+ TRIG1_IN_TR_GROUP11_OUTPUT3 = 0x0000010Cu, /* tr_group[11].output[3] */
+ TRIG1_IN_TR_GROUP11_OUTPUT4 = 0x0000010Du, /* tr_group[11].output[4] */
+ TRIG1_IN_TR_GROUP11_OUTPUT5 = 0x0000010Eu, /* tr_group[11].output[5] */
+ TRIG1_IN_TR_GROUP11_OUTPUT6 = 0x0000010Fu, /* tr_group[11].output[6] */
+ TRIG1_IN_TR_GROUP11_OUTPUT7 = 0x00000110u, /* tr_group[11].output[7] */
+ TRIG1_IN_TR_GROUP11_OUTPUT8 = 0x00000111u, /* tr_group[11].output[8] */
+ TRIG1_IN_TR_GROUP11_OUTPUT9 = 0x00000112u, /* tr_group[11].output[9] */
+ TRIG1_IN_TR_GROUP11_OUTPUT10 = 0x00000113u, /* tr_group[11].output[10] */
+ TRIG1_IN_TR_GROUP11_OUTPUT11 = 0x00000114u, /* tr_group[11].output[11] */
+ TRIG1_IN_TR_GROUP11_OUTPUT12 = 0x00000115u, /* tr_group[11].output[12] */
+ TRIG1_IN_TR_GROUP11_OUTPUT13 = 0x00000116u, /* tr_group[11].output[13] */
+ TRIG1_IN_TR_GROUP11_OUTPUT14 = 0x00000117u, /* tr_group[11].output[14] */
+ TRIG1_IN_TR_GROUP11_OUTPUT15 = 0x00000118u, /* tr_group[11].output[15] */
+ TRIG1_IN_TR_GROUP12_OUTPUT8 = 0x00000119u, /* tr_group[12].output[8] */
+ TRIG1_IN_TR_GROUP12_OUTPUT9 = 0x0000011Au, /* tr_group[12].output[9] */
+ TRIG1_IN_TR_GROUP13_OUTPUT0 = 0x0000011Bu, /* tr_group[13].output[0] */
+ TRIG1_IN_TR_GROUP13_OUTPUT1 = 0x0000011Cu, /* tr_group[13].output[1] */
+ TRIG1_IN_TR_GROUP13_OUTPUT2 = 0x0000011Du, /* tr_group[13].output[2] */
+ TRIG1_IN_TR_GROUP13_OUTPUT3 = 0x0000011Eu, /* tr_group[13].output[3] */
+ TRIG1_IN_TR_GROUP13_OUTPUT4 = 0x0000011Fu, /* tr_group[13].output[4] */
+ TRIG1_IN_TR_GROUP13_OUTPUT5 = 0x00000120u, /* tr_group[13].output[5] */
+ TRIG1_IN_TR_GROUP13_OUTPUT6 = 0x00000121u, /* tr_group[13].output[6] */
+ TRIG1_IN_TR_GROUP13_OUTPUT7 = 0x00000122u, /* tr_group[13].output[7] */
+ TRIG1_IN_TR_GROUP13_OUTPUT8 = 0x00000123u, /* tr_group[13].output[8] */
+ TRIG1_IN_TR_GROUP13_OUTPUT9 = 0x00000124u, /* tr_group[13].output[9] */
+ TRIG1_IN_TR_GROUP13_OUTPUT10 = 0x00000125u, /* tr_group[13].output[10] */
+ TRIG1_IN_TR_GROUP13_OUTPUT11 = 0x00000126u, /* tr_group[13].output[11] */
+ TRIG1_IN_TR_GROUP13_OUTPUT12 = 0x00000127u, /* tr_group[13].output[12] */
+ TRIG1_IN_TR_GROUP13_OUTPUT13 = 0x00000128u, /* tr_group[13].output[13] */
+ TRIG1_IN_TR_GROUP13_OUTPUT14 = 0x00000129u, /* tr_group[13].output[14] */
+ TRIG1_IN_TR_GROUP13_OUTPUT15 = 0x0000012Au, /* tr_group[13].output[15] */
+ TRIG1_IN_TR_GROUP14_OUTPUT0 = 0x0000012Bu, /* tr_group[14].output[0] */
+ TRIG1_IN_TR_GROUP14_OUTPUT1 = 0x0000012Cu, /* tr_group[14].output[1] */
+ TRIG1_IN_TR_GROUP14_OUTPUT2 = 0x0000012Du, /* tr_group[14].output[2] */
+ TRIG1_IN_TR_GROUP14_OUTPUT3 = 0x0000012Eu, /* tr_group[14].output[3] */
+ TRIG1_IN_TR_GROUP14_OUTPUT4 = 0x0000012Fu, /* tr_group[14].output[4] */
+ TRIG1_IN_TR_GROUP14_OUTPUT5 = 0x00000130u, /* tr_group[14].output[5] */
+ TRIG1_IN_TR_GROUP14_OUTPUT6 = 0x00000131u, /* tr_group[14].output[6] */
+ TRIG1_IN_TR_GROUP14_OUTPUT7 = 0x00000132u /* tr_group[14].output[7] */
+} en_trig_input_grp1_t;
+
+/* Trigger Input Group 2 - TCPWM trigger inputs */
+typedef enum
+{
+ TRIG2_IN_CPUSS_ZERO = 0x00000200u, /* cpuss.zero */
+ TRIG2_IN_TR_GROUP10_OUTPUT0 = 0x00000201u, /* tr_group[10].output[0] */
+ TRIG2_IN_TR_GROUP10_OUTPUT1 = 0x00000202u, /* tr_group[10].output[1] */
+ TRIG2_IN_TR_GROUP10_OUTPUT2 = 0x00000203u, /* tr_group[10].output[2] */
+ TRIG2_IN_TR_GROUP10_OUTPUT3 = 0x00000204u, /* tr_group[10].output[3] */
+ TRIG2_IN_TR_GROUP10_OUTPUT4 = 0x00000205u, /* tr_group[10].output[4] */
+ TRIG2_IN_TR_GROUP10_OUTPUT5 = 0x00000206u, /* tr_group[10].output[5] */
+ TRIG2_IN_TR_GROUP10_OUTPUT6 = 0x00000207u, /* tr_group[10].output[6] */
+ TRIG2_IN_TR_GROUP10_OUTPUT7 = 0x00000208u, /* tr_group[10].output[7] */
+ TRIG2_IN_TR_GROUP11_OUTPUT0 = 0x00000209u, /* tr_group[11].output[0] */
+ TRIG2_IN_TR_GROUP11_OUTPUT1 = 0x0000020Au, /* tr_group[11].output[1] */
+ TRIG2_IN_TR_GROUP11_OUTPUT2 = 0x0000020Bu, /* tr_group[11].output[2] */
+ TRIG2_IN_TR_GROUP11_OUTPUT3 = 0x0000020Cu, /* tr_group[11].output[3] */
+ TRIG2_IN_TR_GROUP11_OUTPUT4 = 0x0000020Du, /* tr_group[11].output[4] */
+ TRIG2_IN_TR_GROUP11_OUTPUT5 = 0x0000020Eu, /* tr_group[11].output[5] */
+ TRIG2_IN_TR_GROUP11_OUTPUT6 = 0x0000020Fu, /* tr_group[11].output[6] */
+ TRIG2_IN_TR_GROUP11_OUTPUT7 = 0x00000210u, /* tr_group[11].output[7] */
+ TRIG2_IN_TR_GROUP11_OUTPUT8 = 0x00000211u, /* tr_group[11].output[8] */
+ TRIG2_IN_TR_GROUP11_OUTPUT9 = 0x00000212u, /* tr_group[11].output[9] */
+ TRIG2_IN_TR_GROUP11_OUTPUT10 = 0x00000213u, /* tr_group[11].output[10] */
+ TRIG2_IN_TR_GROUP11_OUTPUT11 = 0x00000214u, /* tr_group[11].output[11] */
+ TRIG2_IN_TR_GROUP11_OUTPUT12 = 0x00000215u, /* tr_group[11].output[12] */
+ TRIG2_IN_TR_GROUP11_OUTPUT13 = 0x00000216u, /* tr_group[11].output[13] */
+ TRIG2_IN_TR_GROUP11_OUTPUT14 = 0x00000217u, /* tr_group[11].output[14] */
+ TRIG2_IN_TR_GROUP11_OUTPUT15 = 0x00000218u, /* tr_group[11].output[15] */
+ TRIG2_IN_TR_GROUP12_OUTPUT0 = 0x00000219u, /* tr_group[12].output[0] */
+ TRIG2_IN_TR_GROUP12_OUTPUT1 = 0x0000021Au, /* tr_group[12].output[1] */
+ TRIG2_IN_TR_GROUP12_OUTPUT2 = 0x0000021Bu, /* tr_group[12].output[2] */
+ TRIG2_IN_TR_GROUP12_OUTPUT3 = 0x0000021Cu, /* tr_group[12].output[3] */
+ TRIG2_IN_TR_GROUP12_OUTPUT4 = 0x0000021Du, /* tr_group[12].output[4] */
+ TRIG2_IN_TR_GROUP12_OUTPUT5 = 0x0000021Eu, /* tr_group[12].output[5] */
+ TRIG2_IN_TR_GROUP12_OUTPUT6 = 0x0000021Fu, /* tr_group[12].output[6] */
+ TRIG2_IN_TR_GROUP12_OUTPUT7 = 0x00000220u, /* tr_group[12].output[7] */
+ TRIG2_IN_TR_GROUP13_OUTPUT16 = 0x00000221u, /* tr_group[13].output[16] */
+ TRIG2_IN_TR_GROUP13_OUTPUT17 = 0x00000222u, /* tr_group[13].output[17] */
+ TRIG2_IN_TR_GROUP14_OUTPUT8 = 0x00000223u, /* tr_group[14].output[8] */
+ TRIG2_IN_TR_GROUP14_OUTPUT9 = 0x00000224u, /* tr_group[14].output[9] */
+ TRIG2_IN_TR_GROUP14_OUTPUT10 = 0x00000225u, /* tr_group[14].output[10] */
+ TRIG2_IN_TR_GROUP14_OUTPUT11 = 0x00000226u, /* tr_group[14].output[11] */
+ TRIG2_IN_TR_GROUP14_OUTPUT12 = 0x00000227u, /* tr_group[14].output[12] */
+ TRIG2_IN_TR_GROUP14_OUTPUT13 = 0x00000228u, /* tr_group[14].output[13] */
+ TRIG2_IN_TR_GROUP14_OUTPUT14 = 0x00000229u, /* tr_group[14].output[14] */
+ TRIG2_IN_TR_GROUP14_OUTPUT15 = 0x0000022Au /* tr_group[14].output[15] */
+} en_trig_input_grp2_t;
+
+/* Trigger Input Group 3 - TCPWM trigger inputs */
+typedef enum
+{
+ TRIG3_IN_CPUSS_ZERO = 0x00000300u, /* cpuss.zero */
+ TRIG3_IN_TR_GROUP10_OUTPUT0 = 0x00000301u, /* tr_group[10].output[0] */
+ TRIG3_IN_TR_GROUP10_OUTPUT1 = 0x00000302u, /* tr_group[10].output[1] */
+ TRIG3_IN_TR_GROUP10_OUTPUT2 = 0x00000303u, /* tr_group[10].output[2] */
+ TRIG3_IN_TR_GROUP10_OUTPUT3 = 0x00000304u, /* tr_group[10].output[3] */
+ TRIG3_IN_TR_GROUP10_OUTPUT4 = 0x00000305u, /* tr_group[10].output[4] */
+ TRIG3_IN_TR_GROUP10_OUTPUT5 = 0x00000306u, /* tr_group[10].output[5] */
+ TRIG3_IN_TR_GROUP10_OUTPUT6 = 0x00000307u, /* tr_group[10].output[6] */
+ TRIG3_IN_TR_GROUP10_OUTPUT7 = 0x00000308u, /* tr_group[10].output[7] */
+ TRIG3_IN_TR_GROUP11_OUTPUT0 = 0x00000309u, /* tr_group[11].output[0] */
+ TRIG3_IN_TR_GROUP11_OUTPUT1 = 0x0000030Au, /* tr_group[11].output[1] */
+ TRIG3_IN_TR_GROUP11_OUTPUT2 = 0x0000030Bu, /* tr_group[11].output[2] */
+ TRIG3_IN_TR_GROUP11_OUTPUT3 = 0x0000030Cu, /* tr_group[11].output[3] */
+ TRIG3_IN_TR_GROUP11_OUTPUT4 = 0x0000030Du, /* tr_group[11].output[4] */
+ TRIG3_IN_TR_GROUP11_OUTPUT5 = 0x0000030Eu, /* tr_group[11].output[5] */
+ TRIG3_IN_TR_GROUP11_OUTPUT6 = 0x0000030Fu, /* tr_group[11].output[6] */
+ TRIG3_IN_TR_GROUP11_OUTPUT7 = 0x00000310u, /* tr_group[11].output[7] */
+ TRIG3_IN_TR_GROUP11_OUTPUT8 = 0x00000311u, /* tr_group[11].output[8] */
+ TRIG3_IN_TR_GROUP11_OUTPUT9 = 0x00000312u, /* tr_group[11].output[9] */
+ TRIG3_IN_TR_GROUP11_OUTPUT10 = 0x00000313u, /* tr_group[11].output[10] */
+ TRIG3_IN_TR_GROUP11_OUTPUT11 = 0x00000314u, /* tr_group[11].output[11] */
+ TRIG3_IN_TR_GROUP11_OUTPUT12 = 0x00000315u, /* tr_group[11].output[12] */
+ TRIG3_IN_TR_GROUP11_OUTPUT13 = 0x00000316u, /* tr_group[11].output[13] */
+ TRIG3_IN_TR_GROUP11_OUTPUT14 = 0x00000317u, /* tr_group[11].output[14] */
+ TRIG3_IN_TR_GROUP11_OUTPUT15 = 0x00000318u, /* tr_group[11].output[15] */
+ TRIG3_IN_TR_GROUP12_OUTPUT0 = 0x00000319u, /* tr_group[12].output[0] */
+ TRIG3_IN_TR_GROUP12_OUTPUT1 = 0x0000031Au, /* tr_group[12].output[1] */
+ TRIG3_IN_TR_GROUP12_OUTPUT2 = 0x0000031Bu, /* tr_group[12].output[2] */
+ TRIG3_IN_TR_GROUP12_OUTPUT3 = 0x0000031Cu, /* tr_group[12].output[3] */
+ TRIG3_IN_TR_GROUP12_OUTPUT4 = 0x0000031Du, /* tr_group[12].output[4] */
+ TRIG3_IN_TR_GROUP12_OUTPUT5 = 0x0000031Eu, /* tr_group[12].output[5] */
+ TRIG3_IN_TR_GROUP12_OUTPUT6 = 0x0000031Fu, /* tr_group[12].output[6] */
+ TRIG3_IN_TR_GROUP12_OUTPUT7 = 0x00000320u, /* tr_group[12].output[7] */
+ TRIG3_IN_TR_GROUP13_OUTPUT16 = 0x00000321u, /* tr_group[13].output[16] */
+ TRIG3_IN_TR_GROUP13_OUTPUT17 = 0x00000322u, /* tr_group[13].output[17] */
+ TRIG3_IN_TR_GROUP14_OUTPUT8 = 0x00000323u, /* tr_group[14].output[8] */
+ TRIG3_IN_TR_GROUP14_OUTPUT9 = 0x00000324u, /* tr_group[14].output[9] */
+ TRIG3_IN_TR_GROUP14_OUTPUT10 = 0x00000325u, /* tr_group[14].output[10] */
+ TRIG3_IN_TR_GROUP14_OUTPUT11 = 0x00000326u, /* tr_group[14].output[11] */
+ TRIG3_IN_TR_GROUP14_OUTPUT12 = 0x00000327u, /* tr_group[14].output[12] */
+ TRIG3_IN_TR_GROUP14_OUTPUT13 = 0x00000328u, /* tr_group[14].output[13] */
+ TRIG3_IN_TR_GROUP14_OUTPUT14 = 0x00000329u, /* tr_group[14].output[14] */
+ TRIG3_IN_TR_GROUP14_OUTPUT15 = 0x0000032Au /* tr_group[14].output[15] */
+} en_trig_input_grp3_t;
+
+/* Trigger Input Group 4 - PROFILE trigger multiplexer */
+typedef enum
+{
+ TRIG4_IN_CPUSS_ZERO = 0x00000400u, /* cpuss.zero */
+ TRIG4_IN_TR_GROUP10_OUTPUT0 = 0x00000401u, /* tr_group[10].output[0] */
+ TRIG4_IN_TR_GROUP10_OUTPUT1 = 0x00000402u, /* tr_group[10].output[1] */
+ TRIG4_IN_TR_GROUP10_OUTPUT2 = 0x00000403u, /* tr_group[10].output[2] */
+ TRIG4_IN_TR_GROUP10_OUTPUT3 = 0x00000404u, /* tr_group[10].output[3] */
+ TRIG4_IN_TR_GROUP10_OUTPUT4 = 0x00000405u, /* tr_group[10].output[4] */
+ TRIG4_IN_TR_GROUP10_OUTPUT5 = 0x00000406u, /* tr_group[10].output[5] */
+ TRIG4_IN_TR_GROUP10_OUTPUT6 = 0x00000407u, /* tr_group[10].output[6] */
+ TRIG4_IN_TR_GROUP10_OUTPUT7 = 0x00000408u, /* tr_group[10].output[7] */
+ TRIG4_IN_TR_GROUP11_OUTPUT0 = 0x00000409u, /* tr_group[11].output[0] */
+ TRIG4_IN_TR_GROUP11_OUTPUT1 = 0x0000040Au, /* tr_group[11].output[1] */
+ TRIG4_IN_TR_GROUP11_OUTPUT2 = 0x0000040Bu, /* tr_group[11].output[2] */
+ TRIG4_IN_TR_GROUP11_OUTPUT3 = 0x0000040Cu, /* tr_group[11].output[3] */
+ TRIG4_IN_TR_GROUP11_OUTPUT4 = 0x0000040Du, /* tr_group[11].output[4] */
+ TRIG4_IN_TR_GROUP11_OUTPUT5 = 0x0000040Eu, /* tr_group[11].output[5] */
+ TRIG4_IN_TR_GROUP11_OUTPUT6 = 0x0000040Fu, /* tr_group[11].output[6] */
+ TRIG4_IN_TR_GROUP11_OUTPUT7 = 0x00000410u, /* tr_group[11].output[7] */
+ TRIG4_IN_TR_GROUP11_OUTPUT8 = 0x00000411u, /* tr_group[11].output[8] */
+ TRIG4_IN_TR_GROUP11_OUTPUT9 = 0x00000412u, /* tr_group[11].output[9] */
+ TRIG4_IN_TR_GROUP11_OUTPUT10 = 0x00000413u, /* tr_group[11].output[10] */
+ TRIG4_IN_TR_GROUP11_OUTPUT11 = 0x00000414u, /* tr_group[11].output[11] */
+ TRIG4_IN_TR_GROUP11_OUTPUT12 = 0x00000415u, /* tr_group[11].output[12] */
+ TRIG4_IN_TR_GROUP11_OUTPUT13 = 0x00000416u, /* tr_group[11].output[13] */
+ TRIG4_IN_TR_GROUP11_OUTPUT14 = 0x00000417u, /* tr_group[11].output[14] */
+ TRIG4_IN_TR_GROUP11_OUTPUT15 = 0x00000418u, /* tr_group[11].output[15] */
+ TRIG4_IN_TR_GROUP12_OUTPUT0 = 0x00000419u, /* tr_group[12].output[0] */
+ TRIG4_IN_TR_GROUP12_OUTPUT1 = 0x0000041Au, /* tr_group[12].output[1] */
+ TRIG4_IN_TR_GROUP12_OUTPUT2 = 0x0000041Bu, /* tr_group[12].output[2] */
+ TRIG4_IN_TR_GROUP12_OUTPUT3 = 0x0000041Cu, /* tr_group[12].output[3] */
+ TRIG4_IN_TR_GROUP12_OUTPUT4 = 0x0000041Du, /* tr_group[12].output[4] */
+ TRIG4_IN_TR_GROUP12_OUTPUT5 = 0x0000041Eu, /* tr_group[12].output[5] */
+ TRIG4_IN_TR_GROUP12_OUTPUT6 = 0x0000041Fu, /* tr_group[12].output[6] */
+ TRIG4_IN_TR_GROUP12_OUTPUT7 = 0x00000420u, /* tr_group[12].output[7] */
+ TRIG4_IN_TR_GROUP13_OUTPUT16 = 0x00000421u, /* tr_group[13].output[16] */
+ TRIG4_IN_TR_GROUP13_OUTPUT17 = 0x00000422u, /* tr_group[13].output[17] */
+ TRIG4_IN_TR_GROUP14_OUTPUT8 = 0x00000423u, /* tr_group[14].output[8] */
+ TRIG4_IN_TR_GROUP14_OUTPUT9 = 0x00000424u, /* tr_group[14].output[9] */
+ TRIG4_IN_TR_GROUP14_OUTPUT10 = 0x00000425u, /* tr_group[14].output[10] */
+ TRIG4_IN_TR_GROUP14_OUTPUT11 = 0x00000426u, /* tr_group[14].output[11] */
+ TRIG4_IN_TR_GROUP14_OUTPUT12 = 0x00000427u, /* tr_group[14].output[12] */
+ TRIG4_IN_TR_GROUP14_OUTPUT13 = 0x00000428u, /* tr_group[14].output[13] */
+ TRIG4_IN_TR_GROUP14_OUTPUT14 = 0x00000429u, /* tr_group[14].output[14] */
+ TRIG4_IN_TR_GROUP14_OUTPUT15 = 0x0000042Au /* tr_group[14].output[15] */
+} en_trig_input_grp4_t;
+
+/* Trigger Input Group 5 - CPUSS.CTI trigger multiplexer */
+typedef enum
+{
+ TRIG5_IN_CPUSS_ZERO = 0x00000500u, /* cpuss.zero */
+ TRIG5_IN_TR_GROUP10_OUTPUT0 = 0x00000501u, /* tr_group[10].output[0] */
+ TRIG5_IN_TR_GROUP10_OUTPUT1 = 0x00000502u, /* tr_group[10].output[1] */
+ TRIG5_IN_TR_GROUP10_OUTPUT2 = 0x00000503u, /* tr_group[10].output[2] */
+ TRIG5_IN_TR_GROUP10_OUTPUT3 = 0x00000504u, /* tr_group[10].output[3] */
+ TRIG5_IN_TR_GROUP10_OUTPUT4 = 0x00000505u, /* tr_group[10].output[4] */
+ TRIG5_IN_TR_GROUP10_OUTPUT5 = 0x00000506u, /* tr_group[10].output[5] */
+ TRIG5_IN_TR_GROUP10_OUTPUT6 = 0x00000507u, /* tr_group[10].output[6] */
+ TRIG5_IN_TR_GROUP10_OUTPUT7 = 0x00000508u, /* tr_group[10].output[7] */
+ TRIG5_IN_TR_GROUP11_OUTPUT0 = 0x00000509u, /* tr_group[11].output[0] */
+ TRIG5_IN_TR_GROUP11_OUTPUT1 = 0x0000050Au, /* tr_group[11].output[1] */
+ TRIG5_IN_TR_GROUP11_OUTPUT2 = 0x0000050Bu, /* tr_group[11].output[2] */
+ TRIG5_IN_TR_GROUP11_OUTPUT3 = 0x0000050Cu, /* tr_group[11].output[3] */
+ TRIG5_IN_TR_GROUP11_OUTPUT4 = 0x0000050Du, /* tr_group[11].output[4] */
+ TRIG5_IN_TR_GROUP11_OUTPUT5 = 0x0000050Eu, /* tr_group[11].output[5] */
+ TRIG5_IN_TR_GROUP11_OUTPUT6 = 0x0000050Fu, /* tr_group[11].output[6] */
+ TRIG5_IN_TR_GROUP11_OUTPUT7 = 0x00000510u, /* tr_group[11].output[7] */
+ TRIG5_IN_TR_GROUP11_OUTPUT8 = 0x00000511u, /* tr_group[11].output[8] */
+ TRIG5_IN_TR_GROUP11_OUTPUT9 = 0x00000512u, /* tr_group[11].output[9] */
+ TRIG5_IN_TR_GROUP11_OUTPUT10 = 0x00000513u, /* tr_group[11].output[10] */
+ TRIG5_IN_TR_GROUP11_OUTPUT11 = 0x00000514u, /* tr_group[11].output[11] */
+ TRIG5_IN_TR_GROUP11_OUTPUT12 = 0x00000515u, /* tr_group[11].output[12] */
+ TRIG5_IN_TR_GROUP11_OUTPUT13 = 0x00000516u, /* tr_group[11].output[13] */
+ TRIG5_IN_TR_GROUP11_OUTPUT14 = 0x00000517u, /* tr_group[11].output[14] */
+ TRIG5_IN_TR_GROUP11_OUTPUT15 = 0x00000518u, /* tr_group[11].output[15] */
+ TRIG5_IN_TR_GROUP12_OUTPUT0 = 0x00000519u, /* tr_group[12].output[0] */
+ TRIG5_IN_TR_GROUP12_OUTPUT1 = 0x0000051Au, /* tr_group[12].output[1] */
+ TRIG5_IN_TR_GROUP12_OUTPUT2 = 0x0000051Bu, /* tr_group[12].output[2] */
+ TRIG5_IN_TR_GROUP12_OUTPUT3 = 0x0000051Cu, /* tr_group[12].output[3] */
+ TRIG5_IN_TR_GROUP12_OUTPUT4 = 0x0000051Du, /* tr_group[12].output[4] */
+ TRIG5_IN_TR_GROUP12_OUTPUT5 = 0x0000051Eu, /* tr_group[12].output[5] */
+ TRIG5_IN_TR_GROUP12_OUTPUT6 = 0x0000051Fu, /* tr_group[12].output[6] */
+ TRIG5_IN_TR_GROUP12_OUTPUT7 = 0x00000520u, /* tr_group[12].output[7] */
+ TRIG5_IN_TR_GROUP13_OUTPUT16 = 0x00000521u, /* tr_group[13].output[16] */
+ TRIG5_IN_TR_GROUP13_OUTPUT17 = 0x00000522u, /* tr_group[13].output[17] */
+ TRIG5_IN_TR_GROUP14_OUTPUT8 = 0x00000523u, /* tr_group[14].output[8] */
+ TRIG5_IN_TR_GROUP14_OUTPUT9 = 0x00000524u, /* tr_group[14].output[9] */
+ TRIG5_IN_TR_GROUP14_OUTPUT10 = 0x00000525u, /* tr_group[14].output[10] */
+ TRIG5_IN_TR_GROUP14_OUTPUT11 = 0x00000526u, /* tr_group[14].output[11] */
+ TRIG5_IN_TR_GROUP14_OUTPUT12 = 0x00000527u, /* tr_group[14].output[12] */
+ TRIG5_IN_TR_GROUP14_OUTPUT13 = 0x00000528u, /* tr_group[14].output[13] */
+ TRIG5_IN_TR_GROUP14_OUTPUT14 = 0x00000529u, /* tr_group[14].output[14] */
+ TRIG5_IN_TR_GROUP14_OUTPUT15 = 0x0000052Au /* tr_group[14].output[15] */
+} en_trig_input_grp5_t;
+
+/* Trigger Input Group 6 - PASS trigger multiplexer */
+typedef enum
+{
+ TRIG6_IN_CPUSS_ZERO = 0x00000600u, /* cpuss.zero */
+ TRIG6_IN_TR_GROUP10_OUTPUT0 = 0x00000601u, /* tr_group[10].output[0] */
+ TRIG6_IN_TR_GROUP10_OUTPUT1 = 0x00000602u, /* tr_group[10].output[1] */
+ TRIG6_IN_TR_GROUP10_OUTPUT2 = 0x00000603u, /* tr_group[10].output[2] */
+ TRIG6_IN_TR_GROUP10_OUTPUT3 = 0x00000604u, /* tr_group[10].output[3] */
+ TRIG6_IN_TR_GROUP10_OUTPUT4 = 0x00000605u, /* tr_group[10].output[4] */
+ TRIG6_IN_TR_GROUP10_OUTPUT5 = 0x00000606u, /* tr_group[10].output[5] */
+ TRIG6_IN_TR_GROUP10_OUTPUT6 = 0x00000607u, /* tr_group[10].output[6] */
+ TRIG6_IN_TR_GROUP10_OUTPUT7 = 0x00000608u, /* tr_group[10].output[7] */
+ TRIG6_IN_TR_GROUP11_OUTPUT0 = 0x00000609u, /* tr_group[11].output[0] */
+ TRIG6_IN_TR_GROUP11_OUTPUT1 = 0x0000060Au, /* tr_group[11].output[1] */
+ TRIG6_IN_TR_GROUP11_OUTPUT2 = 0x0000060Bu, /* tr_group[11].output[2] */
+ TRIG6_IN_TR_GROUP11_OUTPUT3 = 0x0000060Cu, /* tr_group[11].output[3] */
+ TRIG6_IN_TR_GROUP11_OUTPUT4 = 0x0000060Du, /* tr_group[11].output[4] */
+ TRIG6_IN_TR_GROUP11_OUTPUT5 = 0x0000060Eu, /* tr_group[11].output[5] */
+ TRIG6_IN_TR_GROUP11_OUTPUT6 = 0x0000060Fu, /* tr_group[11].output[6] */
+ TRIG6_IN_TR_GROUP11_OUTPUT7 = 0x00000610u, /* tr_group[11].output[7] */
+ TRIG6_IN_TR_GROUP11_OUTPUT8 = 0x00000611u, /* tr_group[11].output[8] */
+ TRIG6_IN_TR_GROUP11_OUTPUT9 = 0x00000612u, /* tr_group[11].output[9] */
+ TRIG6_IN_TR_GROUP11_OUTPUT10 = 0x00000613u, /* tr_group[11].output[10] */
+ TRIG6_IN_TR_GROUP11_OUTPUT11 = 0x00000614u, /* tr_group[11].output[11] */
+ TRIG6_IN_TR_GROUP11_OUTPUT12 = 0x00000615u, /* tr_group[11].output[12] */
+ TRIG6_IN_TR_GROUP11_OUTPUT13 = 0x00000616u, /* tr_group[11].output[13] */
+ TRIG6_IN_TR_GROUP11_OUTPUT14 = 0x00000617u, /* tr_group[11].output[14] */
+ TRIG6_IN_TR_GROUP11_OUTPUT15 = 0x00000618u, /* tr_group[11].output[15] */
+ TRIG6_IN_TR_GROUP12_OUTPUT0 = 0x00000619u, /* tr_group[12].output[0] */
+ TRIG6_IN_TR_GROUP12_OUTPUT1 = 0x0000061Au, /* tr_group[12].output[1] */
+ TRIG6_IN_TR_GROUP12_OUTPUT2 = 0x0000061Bu, /* tr_group[12].output[2] */
+ TRIG6_IN_TR_GROUP12_OUTPUT3 = 0x0000061Cu, /* tr_group[12].output[3] */
+ TRIG6_IN_TR_GROUP12_OUTPUT4 = 0x0000061Du, /* tr_group[12].output[4] */
+ TRIG6_IN_TR_GROUP12_OUTPUT5 = 0x0000061Eu, /* tr_group[12].output[5] */
+ TRIG6_IN_TR_GROUP12_OUTPUT6 = 0x0000061Fu, /* tr_group[12].output[6] */
+ TRIG6_IN_TR_GROUP12_OUTPUT7 = 0x00000620u, /* tr_group[12].output[7] */
+ TRIG6_IN_TR_GROUP13_OUTPUT16 = 0x00000621u, /* tr_group[13].output[16] */
+ TRIG6_IN_TR_GROUP13_OUTPUT17 = 0x00000622u, /* tr_group[13].output[17] */
+ TRIG6_IN_TR_GROUP14_OUTPUT8 = 0x00000623u, /* tr_group[14].output[8] */
+ TRIG6_IN_TR_GROUP14_OUTPUT9 = 0x00000624u, /* tr_group[14].output[9] */
+ TRIG6_IN_TR_GROUP14_OUTPUT10 = 0x00000625u, /* tr_group[14].output[10] */
+ TRIG6_IN_TR_GROUP14_OUTPUT11 = 0x00000626u, /* tr_group[14].output[11] */
+ TRIG6_IN_TR_GROUP14_OUTPUT12 = 0x00000627u, /* tr_group[14].output[12] */
+ TRIG6_IN_TR_GROUP14_OUTPUT13 = 0x00000628u, /* tr_group[14].output[13] */
+ TRIG6_IN_TR_GROUP14_OUTPUT14 = 0x00000629u, /* tr_group[14].output[14] */
+ TRIG6_IN_TR_GROUP14_OUTPUT15 = 0x0000062Au /* tr_group[14].output[15] */
+} en_trig_input_grp6_t;
+
+/* Trigger Input Group 7 - UDB general purpose trigger multiplexer */
+typedef enum
+{
+ TRIG7_IN_CPUSS_ZERO = 0x00000700u, /* cpuss.zero */
+ TRIG7_IN_TR_GROUP10_OUTPUT0 = 0x00000701u, /* tr_group[10].output[0] */
+ TRIG7_IN_TR_GROUP10_OUTPUT1 = 0x00000702u, /* tr_group[10].output[1] */
+ TRIG7_IN_TR_GROUP10_OUTPUT2 = 0x00000703u, /* tr_group[10].output[2] */
+ TRIG7_IN_TR_GROUP10_OUTPUT3 = 0x00000704u, /* tr_group[10].output[3] */
+ TRIG7_IN_TR_GROUP10_OUTPUT4 = 0x00000705u, /* tr_group[10].output[4] */
+ TRIG7_IN_TR_GROUP10_OUTPUT5 = 0x00000706u, /* tr_group[10].output[5] */
+ TRIG7_IN_TR_GROUP10_OUTPUT6 = 0x00000707u, /* tr_group[10].output[6] */
+ TRIG7_IN_TR_GROUP10_OUTPUT7 = 0x00000708u, /* tr_group[10].output[7] */
+ TRIG7_IN_TR_GROUP11_OUTPUT0 = 0x00000709u, /* tr_group[11].output[0] */
+ TRIG7_IN_TR_GROUP11_OUTPUT1 = 0x0000070Au, /* tr_group[11].output[1] */
+ TRIG7_IN_TR_GROUP11_OUTPUT2 = 0x0000070Bu, /* tr_group[11].output[2] */
+ TRIG7_IN_TR_GROUP11_OUTPUT3 = 0x0000070Cu, /* tr_group[11].output[3] */
+ TRIG7_IN_TR_GROUP11_OUTPUT4 = 0x0000070Du, /* tr_group[11].output[4] */
+ TRIG7_IN_TR_GROUP11_OUTPUT5 = 0x0000070Eu, /* tr_group[11].output[5] */
+ TRIG7_IN_TR_GROUP11_OUTPUT6 = 0x0000070Fu, /* tr_group[11].output[6] */
+ TRIG7_IN_TR_GROUP11_OUTPUT7 = 0x00000710u, /* tr_group[11].output[7] */
+ TRIG7_IN_TR_GROUP11_OUTPUT8 = 0x00000711u, /* tr_group[11].output[8] */
+ TRIG7_IN_TR_GROUP11_OUTPUT9 = 0x00000712u, /* tr_group[11].output[9] */
+ TRIG7_IN_TR_GROUP11_OUTPUT10 = 0x00000713u, /* tr_group[11].output[10] */
+ TRIG7_IN_TR_GROUP11_OUTPUT11 = 0x00000714u, /* tr_group[11].output[11] */
+ TRIG7_IN_TR_GROUP11_OUTPUT12 = 0x00000715u, /* tr_group[11].output[12] */
+ TRIG7_IN_TR_GROUP11_OUTPUT13 = 0x00000716u, /* tr_group[11].output[13] */
+ TRIG7_IN_TR_GROUP11_OUTPUT14 = 0x00000717u, /* tr_group[11].output[14] */
+ TRIG7_IN_TR_GROUP11_OUTPUT15 = 0x00000718u, /* tr_group[11].output[15] */
+ TRIG7_IN_TR_GROUP12_OUTPUT0 = 0x00000719u, /* tr_group[12].output[0] */
+ TRIG7_IN_TR_GROUP12_OUTPUT1 = 0x0000071Au, /* tr_group[12].output[1] */
+ TRIG7_IN_TR_GROUP12_OUTPUT2 = 0x0000071Bu, /* tr_group[12].output[2] */
+ TRIG7_IN_TR_GROUP12_OUTPUT3 = 0x0000071Cu, /* tr_group[12].output[3] */
+ TRIG7_IN_TR_GROUP12_OUTPUT4 = 0x0000071Du, /* tr_group[12].output[4] */
+ TRIG7_IN_TR_GROUP12_OUTPUT5 = 0x0000071Eu, /* tr_group[12].output[5] */
+ TRIG7_IN_TR_GROUP12_OUTPUT6 = 0x0000071Fu, /* tr_group[12].output[6] */
+ TRIG7_IN_TR_GROUP12_OUTPUT7 = 0x00000720u, /* tr_group[12].output[7] */
+ TRIG7_IN_TR_GROUP13_OUTPUT16 = 0x00000721u, /* tr_group[13].output[16] */
+ TRIG7_IN_TR_GROUP13_OUTPUT17 = 0x00000722u, /* tr_group[13].output[17] */
+ TRIG7_IN_TR_GROUP14_OUTPUT8 = 0x00000723u, /* tr_group[14].output[8] */
+ TRIG7_IN_TR_GROUP14_OUTPUT9 = 0x00000724u, /* tr_group[14].output[9] */
+ TRIG7_IN_TR_GROUP14_OUTPUT10 = 0x00000725u, /* tr_group[14].output[10] */
+ TRIG7_IN_TR_GROUP14_OUTPUT11 = 0x00000726u, /* tr_group[14].output[11] */
+ TRIG7_IN_TR_GROUP14_OUTPUT12 = 0x00000727u, /* tr_group[14].output[12] */
+ TRIG7_IN_TR_GROUP14_OUTPUT13 = 0x00000728u, /* tr_group[14].output[13] */
+ TRIG7_IN_TR_GROUP14_OUTPUT14 = 0x00000729u, /* tr_group[14].output[14] */
+ TRIG7_IN_TR_GROUP14_OUTPUT15 = 0x0000072Au /* tr_group[14].output[15] */
+} en_trig_input_grp7_t;
+
+/* Trigger Input Group 8 - Trigger multiplexer to pins */
+typedef enum
+{
+ TRIG8_IN_CPUSS_ZERO = 0x00000800u, /* cpuss.zero */
+ TRIG8_IN_TR_GROUP10_OUTPUT0 = 0x00000801u, /* tr_group[10].output[0] */
+ TRIG8_IN_TR_GROUP10_OUTPUT1 = 0x00000802u, /* tr_group[10].output[1] */
+ TRIG8_IN_TR_GROUP10_OUTPUT2 = 0x00000803u, /* tr_group[10].output[2] */
+ TRIG8_IN_TR_GROUP10_OUTPUT3 = 0x00000804u, /* tr_group[10].output[3] */
+ TRIG8_IN_TR_GROUP10_OUTPUT4 = 0x00000805u, /* tr_group[10].output[4] */
+ TRIG8_IN_TR_GROUP10_OUTPUT5 = 0x00000806u, /* tr_group[10].output[5] */
+ TRIG8_IN_TR_GROUP10_OUTPUT6 = 0x00000807u, /* tr_group[10].output[6] */
+ TRIG8_IN_TR_GROUP10_OUTPUT7 = 0x00000808u, /* tr_group[10].output[7] */
+ TRIG8_IN_TR_GROUP11_OUTPUT0 = 0x00000809u, /* tr_group[11].output[0] */
+ TRIG8_IN_TR_GROUP11_OUTPUT1 = 0x0000080Au, /* tr_group[11].output[1] */
+ TRIG8_IN_TR_GROUP11_OUTPUT2 = 0x0000080Bu, /* tr_group[11].output[2] */
+ TRIG8_IN_TR_GROUP11_OUTPUT3 = 0x0000080Cu, /* tr_group[11].output[3] */
+ TRIG8_IN_TR_GROUP11_OUTPUT4 = 0x0000080Du, /* tr_group[11].output[4] */
+ TRIG8_IN_TR_GROUP11_OUTPUT5 = 0x0000080Eu, /* tr_group[11].output[5] */
+ TRIG8_IN_TR_GROUP11_OUTPUT6 = 0x0000080Fu, /* tr_group[11].output[6] */
+ TRIG8_IN_TR_GROUP11_OUTPUT7 = 0x00000810u, /* tr_group[11].output[7] */
+ TRIG8_IN_TR_GROUP11_OUTPUT8 = 0x00000811u, /* tr_group[11].output[8] */
+ TRIG8_IN_TR_GROUP11_OUTPUT9 = 0x00000812u, /* tr_group[11].output[9] */
+ TRIG8_IN_TR_GROUP11_OUTPUT10 = 0x00000813u, /* tr_group[11].output[10] */
+ TRIG8_IN_TR_GROUP11_OUTPUT11 = 0x00000814u, /* tr_group[11].output[11] */
+ TRIG8_IN_TR_GROUP11_OUTPUT12 = 0x00000815u, /* tr_group[11].output[12] */
+ TRIG8_IN_TR_GROUP11_OUTPUT13 = 0x00000816u, /* tr_group[11].output[13] */
+ TRIG8_IN_TR_GROUP11_OUTPUT14 = 0x00000817u, /* tr_group[11].output[14] */
+ TRIG8_IN_TR_GROUP11_OUTPUT15 = 0x00000818u, /* tr_group[11].output[15] */
+ TRIG8_IN_TR_GROUP12_OUTPUT0 = 0x00000819u, /* tr_group[12].output[0] */
+ TRIG8_IN_TR_GROUP12_OUTPUT1 = 0x0000081Au, /* tr_group[12].output[1] */
+ TRIG8_IN_TR_GROUP12_OUTPUT2 = 0x0000081Bu, /* tr_group[12].output[2] */
+ TRIG8_IN_TR_GROUP12_OUTPUT3 = 0x0000081Cu, /* tr_group[12].output[3] */
+ TRIG8_IN_TR_GROUP12_OUTPUT4 = 0x0000081Du, /* tr_group[12].output[4] */
+ TRIG8_IN_TR_GROUP12_OUTPUT5 = 0x0000081Eu, /* tr_group[12].output[5] */
+ TRIG8_IN_TR_GROUP12_OUTPUT6 = 0x0000081Fu, /* tr_group[12].output[6] */
+ TRIG8_IN_TR_GROUP12_OUTPUT7 = 0x00000820u, /* tr_group[12].output[7] */
+ TRIG8_IN_TR_GROUP13_OUTPUT16 = 0x00000821u, /* tr_group[13].output[16] */
+ TRIG8_IN_TR_GROUP13_OUTPUT17 = 0x00000822u, /* tr_group[13].output[17] */
+ TRIG8_IN_TR_GROUP14_OUTPUT8 = 0x00000823u, /* tr_group[14].output[8] */
+ TRIG8_IN_TR_GROUP14_OUTPUT9 = 0x00000824u, /* tr_group[14].output[9] */
+ TRIG8_IN_TR_GROUP14_OUTPUT10 = 0x00000825u, /* tr_group[14].output[10] */
+ TRIG8_IN_TR_GROUP14_OUTPUT11 = 0x00000826u, /* tr_group[14].output[11] */
+ TRIG8_IN_TR_GROUP14_OUTPUT12 = 0x00000827u, /* tr_group[14].output[12] */
+ TRIG8_IN_TR_GROUP14_OUTPUT13 = 0x00000828u, /* tr_group[14].output[13] */
+ TRIG8_IN_TR_GROUP14_OUTPUT14 = 0x00000829u, /* tr_group[14].output[14] */
+ TRIG8_IN_TR_GROUP14_OUTPUT15 = 0x0000082Au /* tr_group[14].output[15] */
+} en_trig_input_grp8_t;
+
+/* Trigger Input Group 9 - Feedback mux to USB DMA interface */
+typedef enum
+{
+ TRIG9_IN_CPUSS_ZERO = 0x00000900u, /* cpuss.zero */
+ TRIG9_IN_CPUSS_DW0_TR_OUT0 = 0x00000901u, /* cpuss.dw0_tr_out[0] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT1 = 0x00000902u, /* cpuss.dw0_tr_out[1] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT2 = 0x00000903u, /* cpuss.dw0_tr_out[2] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT3 = 0x00000904u, /* cpuss.dw0_tr_out[3] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT4 = 0x00000905u, /* cpuss.dw0_tr_out[4] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT5 = 0x00000906u, /* cpuss.dw0_tr_out[5] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT6 = 0x00000907u, /* cpuss.dw0_tr_out[6] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT7 = 0x00000908u, /* cpuss.dw0_tr_out[7] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT8 = 0x00000909u, /* cpuss.dw0_tr_out[8] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT9 = 0x0000090Au, /* cpuss.dw0_tr_out[9] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT10 = 0x0000090Bu, /* cpuss.dw0_tr_out[10] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT11 = 0x0000090Cu, /* cpuss.dw0_tr_out[11] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT12 = 0x0000090Du, /* cpuss.dw0_tr_out[12] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT13 = 0x0000090Eu, /* cpuss.dw0_tr_out[13] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT14 = 0x0000090Fu, /* cpuss.dw0_tr_out[14] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT15 = 0x00000910u, /* cpuss.dw0_tr_out[15] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT0 = 0x00000911u, /* cpuss.dw1_tr_out[0] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT1 = 0x00000912u, /* cpuss.dw1_tr_out[1] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT2 = 0x00000913u, /* cpuss.dw1_tr_out[2] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT3 = 0x00000914u, /* cpuss.dw1_tr_out[3] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT4 = 0x00000915u, /* cpuss.dw1_tr_out[4] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT5 = 0x00000916u, /* cpuss.dw1_tr_out[5] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT6 = 0x00000917u, /* cpuss.dw1_tr_out[6] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT7 = 0x00000918u, /* cpuss.dw1_tr_out[7] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT8 = 0x00000919u, /* cpuss.dw1_tr_out[8] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT9 = 0x0000091Au, /* cpuss.dw1_tr_out[9] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT10 = 0x0000091Bu, /* cpuss.dw1_tr_out[10] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT11 = 0x0000091Cu, /* cpuss.dw1_tr_out[11] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT12 = 0x0000091Du, /* cpuss.dw1_tr_out[12] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT13 = 0x0000091Eu, /* cpuss.dw1_tr_out[13] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT14 = 0x0000091Fu, /* cpuss.dw1_tr_out[14] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT15 = 0x00000920u /* cpuss.dw1_tr_out[15] */
+} en_trig_input_grp9_t;
+
+/* Trigger Input Group 10 - Reduces 32 datawire output triggers to 8 signals, used by all except USB */
+typedef enum
+{
+ TRIG10_IN_CPUSS_ZERO = 0x00000A00u, /* cpuss.zero */
+ TRIG10_IN_CPUSS_DW0_TR_OUT0 = 0x00000A01u, /* cpuss.dw0_tr_out[0] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT1 = 0x00000A02u, /* cpuss.dw0_tr_out[1] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT2 = 0x00000A03u, /* cpuss.dw0_tr_out[2] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT3 = 0x00000A04u, /* cpuss.dw0_tr_out[3] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT4 = 0x00000A05u, /* cpuss.dw0_tr_out[4] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT5 = 0x00000A06u, /* cpuss.dw0_tr_out[5] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT6 = 0x00000A07u, /* cpuss.dw0_tr_out[6] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT7 = 0x00000A08u, /* cpuss.dw0_tr_out[7] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT8 = 0x00000A09u, /* cpuss.dw0_tr_out[8] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT9 = 0x00000A0Au, /* cpuss.dw0_tr_out[9] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT10 = 0x00000A0Bu, /* cpuss.dw0_tr_out[10] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT11 = 0x00000A0Cu, /* cpuss.dw0_tr_out[11] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT12 = 0x00000A0Du, /* cpuss.dw0_tr_out[12] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT13 = 0x00000A0Eu, /* cpuss.dw0_tr_out[13] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT14 = 0x00000A0Fu, /* cpuss.dw0_tr_out[14] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT15 = 0x00000A10u, /* cpuss.dw0_tr_out[15] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT0 = 0x00000A11u, /* cpuss.dw1_tr_out[0] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT1 = 0x00000A12u, /* cpuss.dw1_tr_out[1] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT2 = 0x00000A13u, /* cpuss.dw1_tr_out[2] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT3 = 0x00000A14u, /* cpuss.dw1_tr_out[3] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT4 = 0x00000A15u, /* cpuss.dw1_tr_out[4] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT5 = 0x00000A16u, /* cpuss.dw1_tr_out[5] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT6 = 0x00000A17u, /* cpuss.dw1_tr_out[6] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT7 = 0x00000A18u, /* cpuss.dw1_tr_out[7] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT8 = 0x00000A19u, /* cpuss.dw1_tr_out[8] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT9 = 0x00000A1Au, /* cpuss.dw1_tr_out[9] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT10 = 0x00000A1Bu, /* cpuss.dw1_tr_out[10] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT11 = 0x00000A1Cu, /* cpuss.dw1_tr_out[11] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT12 = 0x00000A1Du, /* cpuss.dw1_tr_out[12] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT13 = 0x00000A1Eu, /* cpuss.dw1_tr_out[13] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT14 = 0x00000A1Fu, /* cpuss.dw1_tr_out[14] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT15 = 0x00000A20u /* cpuss.dw1_tr_out[15] */
+} en_trig_input_grp10_t;
+
+/* Trigger Input Group 11 - Reduces 96 tcpwm output triggers to 16 signals, used by all sinks */
+typedef enum
+{
+ TRIG11_IN_CPUSS_ZERO = 0x00000B00u, /* cpuss.zero */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW0 = 0x00000B01u, /* tcpwm[0].tr_overflow[0] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW1 = 0x00000B02u, /* tcpwm[0].tr_overflow[1] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW2 = 0x00000B03u, /* tcpwm[0].tr_overflow[2] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW3 = 0x00000B04u, /* tcpwm[0].tr_overflow[3] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW4 = 0x00000B05u, /* tcpwm[0].tr_overflow[4] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW5 = 0x00000B06u, /* tcpwm[0].tr_overflow[5] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW6 = 0x00000B07u, /* tcpwm[0].tr_overflow[6] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW7 = 0x00000B08u, /* tcpwm[0].tr_overflow[7] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH0 = 0x00000B09u, /* tcpwm[0].tr_compare_match[0] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH1 = 0x00000B0Au, /* tcpwm[0].tr_compare_match[1] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH2 = 0x00000B0Bu, /* tcpwm[0].tr_compare_match[2] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH3 = 0x00000B0Cu, /* tcpwm[0].tr_compare_match[3] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH4 = 0x00000B0Du, /* tcpwm[0].tr_compare_match[4] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH5 = 0x00000B0Eu, /* tcpwm[0].tr_compare_match[5] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH6 = 0x00000B0Fu, /* tcpwm[0].tr_compare_match[6] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH7 = 0x00000B10u, /* tcpwm[0].tr_compare_match[7] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW0 = 0x00000B11u, /* tcpwm[0].tr_underflow[0] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW1 = 0x00000B12u, /* tcpwm[0].tr_underflow[1] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW2 = 0x00000B13u, /* tcpwm[0].tr_underflow[2] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW3 = 0x00000B14u, /* tcpwm[0].tr_underflow[3] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW4 = 0x00000B15u, /* tcpwm[0].tr_underflow[4] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW5 = 0x00000B16u, /* tcpwm[0].tr_underflow[5] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW6 = 0x00000B17u, /* tcpwm[0].tr_underflow[6] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW7 = 0x00000B18u, /* tcpwm[0].tr_underflow[7] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW0 = 0x00000B19u, /* tcpwm[1].tr_overflow[0] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW1 = 0x00000B1Au, /* tcpwm[1].tr_overflow[1] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW2 = 0x00000B1Bu, /* tcpwm[1].tr_overflow[2] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW3 = 0x00000B1Cu, /* tcpwm[1].tr_overflow[3] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW4 = 0x00000B1Du, /* tcpwm[1].tr_overflow[4] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW5 = 0x00000B1Eu, /* tcpwm[1].tr_overflow[5] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW6 = 0x00000B1Fu, /* tcpwm[1].tr_overflow[6] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW7 = 0x00000B20u, /* tcpwm[1].tr_overflow[7] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW8 = 0x00000B21u, /* tcpwm[1].tr_overflow[8] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW9 = 0x00000B22u, /* tcpwm[1].tr_overflow[9] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW10 = 0x00000B23u, /* tcpwm[1].tr_overflow[10] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW11 = 0x00000B24u, /* tcpwm[1].tr_overflow[11] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW12 = 0x00000B25u, /* tcpwm[1].tr_overflow[12] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW13 = 0x00000B26u, /* tcpwm[1].tr_overflow[13] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW14 = 0x00000B27u, /* tcpwm[1].tr_overflow[14] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW15 = 0x00000B28u, /* tcpwm[1].tr_overflow[15] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW16 = 0x00000B29u, /* tcpwm[1].tr_overflow[16] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW17 = 0x00000B2Au, /* tcpwm[1].tr_overflow[17] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW18 = 0x00000B2Bu, /* tcpwm[1].tr_overflow[18] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW19 = 0x00000B2Cu, /* tcpwm[1].tr_overflow[19] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW20 = 0x00000B2Du, /* tcpwm[1].tr_overflow[20] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW21 = 0x00000B2Eu, /* tcpwm[1].tr_overflow[21] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW22 = 0x00000B2Fu, /* tcpwm[1].tr_overflow[22] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW23 = 0x00000B30u, /* tcpwm[1].tr_overflow[23] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH0 = 0x00000B31u, /* tcpwm[1].tr_compare_match[0] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH1 = 0x00000B32u, /* tcpwm[1].tr_compare_match[1] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH2 = 0x00000B33u, /* tcpwm[1].tr_compare_match[2] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH3 = 0x00000B34u, /* tcpwm[1].tr_compare_match[3] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH4 = 0x00000B35u, /* tcpwm[1].tr_compare_match[4] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH5 = 0x00000B36u, /* tcpwm[1].tr_compare_match[5] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH6 = 0x00000B37u, /* tcpwm[1].tr_compare_match[6] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH7 = 0x00000B38u, /* tcpwm[1].tr_compare_match[7] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH8 = 0x00000B39u, /* tcpwm[1].tr_compare_match[8] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH9 = 0x00000B3Au, /* tcpwm[1].tr_compare_match[9] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH10 = 0x00000B3Bu, /* tcpwm[1].tr_compare_match[10] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH11 = 0x00000B3Cu, /* tcpwm[1].tr_compare_match[11] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH12 = 0x00000B3Du, /* tcpwm[1].tr_compare_match[12] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH13 = 0x00000B3Eu, /* tcpwm[1].tr_compare_match[13] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH14 = 0x00000B3Fu, /* tcpwm[1].tr_compare_match[14] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH15 = 0x00000B40u, /* tcpwm[1].tr_compare_match[15] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH16 = 0x00000B41u, /* tcpwm[1].tr_compare_match[16] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH17 = 0x00000B42u, /* tcpwm[1].tr_compare_match[17] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH18 = 0x00000B43u, /* tcpwm[1].tr_compare_match[18] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH19 = 0x00000B44u, /* tcpwm[1].tr_compare_match[19] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH20 = 0x00000B45u, /* tcpwm[1].tr_compare_match[20] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH21 = 0x00000B46u, /* tcpwm[1].tr_compare_match[21] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH22 = 0x00000B47u, /* tcpwm[1].tr_compare_match[22] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH23 = 0x00000B48u, /* tcpwm[1].tr_compare_match[23] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW0 = 0x00000B49u, /* tcpwm[1].tr_underflow[0] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW1 = 0x00000B4Au, /* tcpwm[1].tr_underflow[1] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW2 = 0x00000B4Bu, /* tcpwm[1].tr_underflow[2] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW3 = 0x00000B4Cu, /* tcpwm[1].tr_underflow[3] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW4 = 0x00000B4Du, /* tcpwm[1].tr_underflow[4] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW5 = 0x00000B4Eu, /* tcpwm[1].tr_underflow[5] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW6 = 0x00000B4Fu, /* tcpwm[1].tr_underflow[6] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW7 = 0x00000B50u, /* tcpwm[1].tr_underflow[7] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW8 = 0x00000B51u, /* tcpwm[1].tr_underflow[8] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW9 = 0x00000B52u, /* tcpwm[1].tr_underflow[9] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW10 = 0x00000B53u, /* tcpwm[1].tr_underflow[10] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW11 = 0x00000B54u, /* tcpwm[1].tr_underflow[11] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW12 = 0x00000B55u, /* tcpwm[1].tr_underflow[12] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW13 = 0x00000B56u, /* tcpwm[1].tr_underflow[13] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW14 = 0x00000B57u, /* tcpwm[1].tr_underflow[14] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW15 = 0x00000B58u, /* tcpwm[1].tr_underflow[15] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW16 = 0x00000B59u, /* tcpwm[1].tr_underflow[16] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW17 = 0x00000B5Au, /* tcpwm[1].tr_underflow[17] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW18 = 0x00000B5Bu, /* tcpwm[1].tr_underflow[18] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW19 = 0x00000B5Cu, /* tcpwm[1].tr_underflow[19] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW20 = 0x00000B5Du, /* tcpwm[1].tr_underflow[20] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW21 = 0x00000B5Eu, /* tcpwm[1].tr_underflow[21] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW22 = 0x00000B5Fu, /* tcpwm[1].tr_underflow[22] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW23 = 0x00000B60u /* tcpwm[1].tr_underflow[23] */
+} en_trig_input_grp11_t;
+
+/* Trigger Input Group 12 - Reduces 28 pin input signals to 10 triggers used by all sinks */
+typedef enum
+{
+ TRIG12_IN_CPUSS_ZERO = 0x00000C00u, /* cpuss.zero */
+ TRIG12_IN_PERI_TR_IO_INPUT0 = 0x00000C01u, /* peri.tr_io_input[0] */
+ TRIG12_IN_PERI_TR_IO_INPUT1 = 0x00000C02u, /* peri.tr_io_input[1] */
+ TRIG12_IN_PERI_TR_IO_INPUT2 = 0x00000C03u, /* peri.tr_io_input[2] */
+ TRIG12_IN_PERI_TR_IO_INPUT3 = 0x00000C04u, /* peri.tr_io_input[3] */
+ TRIG12_IN_PERI_TR_IO_INPUT4 = 0x00000C05u, /* peri.tr_io_input[4] */
+ TRIG12_IN_PERI_TR_IO_INPUT5 = 0x00000C06u, /* peri.tr_io_input[5] */
+ TRIG12_IN_PERI_TR_IO_INPUT6 = 0x00000C07u, /* peri.tr_io_input[6] */
+ TRIG12_IN_PERI_TR_IO_INPUT7 = 0x00000C08u, /* peri.tr_io_input[7] */
+ TRIG12_IN_PERI_TR_IO_INPUT8 = 0x00000C09u, /* peri.tr_io_input[8] */
+ TRIG12_IN_PERI_TR_IO_INPUT9 = 0x00000C0Au, /* peri.tr_io_input[9] */
+ TRIG12_IN_PERI_TR_IO_INPUT10 = 0x00000C0Bu, /* peri.tr_io_input[10] */
+ TRIG12_IN_PERI_TR_IO_INPUT11 = 0x00000C0Cu, /* peri.tr_io_input[11] */
+ TRIG12_IN_PERI_TR_IO_INPUT12 = 0x00000C0Du, /* peri.tr_io_input[12] */
+ TRIG12_IN_PERI_TR_IO_INPUT13 = 0x00000C0Eu, /* peri.tr_io_input[13] */
+ TRIG12_IN_PERI_TR_IO_INPUT14 = 0x00000C0Fu, /* peri.tr_io_input[14] */
+ TRIG12_IN_PERI_TR_IO_INPUT15 = 0x00000C10u, /* peri.tr_io_input[15] */
+ TRIG12_IN_PERI_TR_IO_INPUT16 = 0x00000C11u, /* peri.tr_io_input[16] */
+ TRIG12_IN_PERI_TR_IO_INPUT17 = 0x00000C12u, /* peri.tr_io_input[17] */
+ TRIG12_IN_PERI_TR_IO_INPUT18 = 0x00000C13u, /* peri.tr_io_input[18] */
+ TRIG12_IN_PERI_TR_IO_INPUT19 = 0x00000C14u, /* peri.tr_io_input[19] */
+ TRIG12_IN_PERI_TR_IO_INPUT20 = 0x00000C15u, /* peri.tr_io_input[20] */
+ TRIG12_IN_PERI_TR_IO_INPUT21 = 0x00000C16u, /* peri.tr_io_input[21] */
+ TRIG12_IN_PERI_TR_IO_INPUT22 = 0x00000C17u, /* peri.tr_io_input[22] */
+ TRIG12_IN_PERI_TR_IO_INPUT23 = 0x00000C18u, /* peri.tr_io_input[23] */
+ TRIG12_IN_PERI_TR_IO_INPUT24 = 0x00000C19u, /* peri.tr_io_input[24] */
+ TRIG12_IN_PERI_TR_IO_INPUT25 = 0x00000C1Au, /* peri.tr_io_input[25] */
+ TRIG12_IN_PERI_TR_IO_INPUT26 = 0x00000C1Bu, /* peri.tr_io_input[26] */
+ TRIG12_IN_PERI_TR_IO_INPUT27 = 0x00000C1Cu /* peri.tr_io_input[27] */
+} en_trig_input_grp12_t;
+
+/* Trigger Input Group 13 - Reduces DMA requests to 16+2 outputs used by all sinks */
+typedef enum
+{
+ TRIG13_IN_CPUSS_ZERO = 0x00000D00u, /* cpuss.zero */
+ TRIG13_IN_SCB0_TR_TX_REQ = 0x00000D01u, /* scb[0].tr_tx_req */
+ TRIG13_IN_SCB0_TR_RX_REQ = 0x00000D02u, /* scb[0].tr_rx_req */
+ TRIG13_IN_SCB1_TR_TX_REQ = 0x00000D03u, /* scb[1].tr_tx_req */
+ TRIG13_IN_SCB1_TR_RX_REQ = 0x00000D04u, /* scb[1].tr_rx_req */
+ TRIG13_IN_SCB2_TR_TX_REQ = 0x00000D05u, /* scb[2].tr_tx_req */
+ TRIG13_IN_SCB2_TR_RX_REQ = 0x00000D06u, /* scb[2].tr_rx_req */
+ TRIG13_IN_SCB3_TR_TX_REQ = 0x00000D07u, /* scb[3].tr_tx_req */
+ TRIG13_IN_SCB3_TR_RX_REQ = 0x00000D08u, /* scb[3].tr_rx_req */
+ TRIG13_IN_SCB4_TR_TX_REQ = 0x00000D09u, /* scb[4].tr_tx_req */
+ TRIG13_IN_SCB4_TR_RX_REQ = 0x00000D0Au, /* scb[4].tr_rx_req */
+ TRIG13_IN_SCB5_TR_TX_REQ = 0x00000D0Bu, /* scb[5].tr_tx_req */
+ TRIG13_IN_SCB5_TR_RX_REQ = 0x00000D0Cu, /* scb[5].tr_rx_req */
+ TRIG13_IN_SCB6_TR_TX_REQ = 0x00000D0Du, /* scb[6].tr_tx_req */
+ TRIG13_IN_SCB6_TR_RX_REQ = 0x00000D0Eu, /* scb[6].tr_rx_req */
+ TRIG13_IN_SCB7_TR_TX_REQ = 0x00000D0Fu, /* scb[7].tr_tx_req */
+ TRIG13_IN_SCB7_TR_RX_REQ = 0x00000D10u, /* scb[7].tr_rx_req */
+ TRIG13_IN_SCB8_TR_TX_REQ = 0x00000D11u, /* scb[8].tr_tx_req */
+ TRIG13_IN_SCB8_TR_RX_REQ = 0x00000D12u, /* scb[8].tr_rx_req */
+ TRIG13_IN_AUDIOSS_TR_PDM_RX_REQ = 0x00000D13u, /* audioss.tr_pdm_rx_req */
+ TRIG13_IN_AUDIOSS_TR_I2S_TX_REQ = 0x00000D14u, /* audioss.tr_i2s_tx_req */
+ TRIG13_IN_AUDIOSS_TR_I2S_RX_REQ = 0x00000D15u, /* audioss.tr_i2s_rx_req */
+ TRIG13_IN_SMIF_TR_TX_REQ = 0x00000D16u, /* smif.tr_tx_req */
+ TRIG13_IN_SMIF_TR_RX_REQ = 0x00000D17u, /* smif.tr_rx_req */
+ TRIG13_IN_USB_DMA_REQ0 = 0x00000D18u, /* usb.dma_req[0] */
+ TRIG13_IN_USB_DMA_REQ1 = 0x00000D19u, /* usb.dma_req[1] */
+ TRIG13_IN_USB_DMA_REQ2 = 0x00000D1Au, /* usb.dma_req[2] */
+ TRIG13_IN_USB_DMA_REQ3 = 0x00000D1Bu, /* usb.dma_req[3] */
+ TRIG13_IN_USB_DMA_REQ4 = 0x00000D1Cu, /* usb.dma_req[4] */
+ TRIG13_IN_USB_DMA_REQ5 = 0x00000D1Du, /* usb.dma_req[5] */
+ TRIG13_IN_USB_DMA_REQ6 = 0x00000D1Eu, /* usb.dma_req[6] */
+ TRIG13_IN_USB_DMA_REQ7 = 0x00000D1Fu, /* usb.dma_req[7] */
+ TRIG13_IN_CSD_TR_ADC_DONE = 0x00000D20u, /* csd.tr_adc_done */
+ TRIG13_IN_CSD_DSI_SENSE_OUT = 0x00000D21u /* csd.dsi_sense_out */
+} en_trig_input_grp13_t;
+
+/* Trigger Input Group 14 - Reduces general purpose trigger inputs to 8+8 outputs used by all sinks */
+typedef enum
+{
+ TRIG14_IN_CPUSS_ZERO = 0x00000E00u, /* cpuss.zero */
+ TRIG14_IN_UDB_TR_UDB0 = 0x00000E01u, /* udb.tr_udb[0] */
+ TRIG14_IN_UDB_TR_UDB1 = 0x00000E02u, /* udb.tr_udb[1] */
+ TRIG14_IN_UDB_TR_UDB2 = 0x00000E03u, /* udb.tr_udb[2] */
+ TRIG14_IN_UDB_TR_UDB3 = 0x00000E04u, /* udb.tr_udb[3] */
+ TRIG14_IN_UDB_TR_UDB4 = 0x00000E05u, /* udb.tr_udb[4] */
+ TRIG14_IN_UDB_TR_UDB5 = 0x00000E06u, /* udb.tr_udb[5] */
+ TRIG14_IN_UDB_TR_UDB6 = 0x00000E07u, /* udb.tr_udb[6] */
+ TRIG14_IN_UDB_TR_UDB7 = 0x00000E08u, /* udb.tr_udb[7] */
+ TRIG14_IN_UDB_TR_UDB8 = 0x00000E09u, /* udb.tr_udb[8] */
+ TRIG14_IN_UDB_TR_UDB9 = 0x00000E0Au, /* udb.tr_udb[9] */
+ TRIG14_IN_UDB_TR_UDB10 = 0x00000E0Bu, /* udb.tr_udb[10] */
+ TRIG14_IN_UDB_TR_UDB11 = 0x00000E0Cu, /* udb.tr_udb[11] */
+ TRIG14_IN_UDB_TR_UDB12 = 0x00000E0Du, /* udb.tr_udb[12] */
+ TRIG14_IN_UDB_TR_UDB13 = 0x00000E0Eu, /* udb.tr_udb[13] */
+ TRIG14_IN_UDB_TR_UDB14 = 0x00000E0Fu, /* udb.tr_udb[14] */
+ TRIG14_IN_UDB_TR_UDB15 = 0x00000E10u, /* udb.tr_udb[15] */
+ TRIG14_IN_UDB_DSI_OUT_TR0 = 0x00000E11u, /* udb.dsi_out_tr[0] */
+ TRIG14_IN_UDB_DSI_OUT_TR1 = 0x00000E12u, /* udb.dsi_out_tr[1] */
+ TRIG14_IN_CPUSS_CTI_TR_OUT0 = 0x00000E13u, /* cpuss.cti_tr_out[0] */
+ TRIG14_IN_CPUSS_CTI_TR_OUT1 = 0x00000E14u, /* cpuss.cti_tr_out[1] */
+ TRIG14_IN_PASS_TR_SAR_OUT = 0x00000E15u, /* pass.tr_sar_out */
+ TRIG14_IN_PASS_TR_CTDAC_EMPTY = 0x00000E16u, /* pass.tr_ctdac_empty */
+ TRIG14_IN_PASS_DSI_CTB_CMP0 = 0x00000E17u, /* pass.dsi_ctb_cmp0 */
+ TRIG14_IN_PASS_DSI_CTB_CMP1 = 0x00000E18u, /* pass.dsi_ctb_cmp1 */
+ TRIG14_IN_LPCOMP_DSI_COMP0 = 0x00000E19u, /* lpcomp.dsi_comp0 */
+ TRIG14_IN_LPCOMP_DSI_COMP1 = 0x00000E1Au, /* lpcomp.dsi_comp1 */
+ TRIG14_IN_SCB0_TR_I2C_SCL_FILTERED = 0x00000E1Bu, /* scb[0].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB1_TR_I2C_SCL_FILTERED = 0x00000E1Cu, /* scb[1].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB2_TR_I2C_SCL_FILTERED = 0x00000E1Du, /* scb[2].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB3_TR_I2C_SCL_FILTERED = 0x00000E1Eu, /* scb[3].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB4_TR_I2C_SCL_FILTERED = 0x00000E1Fu, /* scb[4].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB5_TR_I2C_SCL_FILTERED = 0x00000E20u, /* scb[5].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB6_TR_I2C_SCL_FILTERED = 0x00000E21u, /* scb[6].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB7_TR_I2C_SCL_FILTERED = 0x00000E22u, /* scb[7].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB8_TR_I2C_SCL_FILTERED = 0x00000E23u, /* scb[8].tr_i2c_scl_filtered */
+ TRIG14_IN_CPUSS_TR_FAULT0 = 0x00000E24u, /* cpuss.tr_fault[0] */
+ TRIG14_IN_CPUSS_TR_FAULT1 = 0x00000E25u /* cpuss.tr_fault[1] */
+} en_trig_input_grp14_t;
+
+/* Trigger Group Outputs */
+/* Trigger Output Group 0 - DMA Request Assignments */
+typedef enum
+{
+ TRIG0_OUT_CPUSS_DW0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN7 = 0x40000007u, /* cpuss.dw0_tr_in[7] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN8 = 0x40000008u, /* cpuss.dw0_tr_in[8] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN9 = 0x40000009u, /* cpuss.dw0_tr_in[9] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN10 = 0x4000000Au, /* cpuss.dw0_tr_in[10] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN11 = 0x4000000Bu, /* cpuss.dw0_tr_in[11] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN12 = 0x4000000Cu, /* cpuss.dw0_tr_in[12] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN13 = 0x4000000Du, /* cpuss.dw0_tr_in[13] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN14 = 0x4000000Eu, /* cpuss.dw0_tr_in[14] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN15 = 0x4000000Fu /* cpuss.dw0_tr_in[15] */
+} en_trig_output_grp0_t;
+
+/* Trigger Output Group 1 - DMA Request Assignments */
+typedef enum
+{
+ TRIG1_OUT_CPUSS_DW1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN7 = 0x40000107u, /* cpuss.dw1_tr_in[7] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN8 = 0x40000108u, /* cpuss.dw1_tr_in[8] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN9 = 0x40000109u, /* cpuss.dw1_tr_in[9] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN10 = 0x4000010Au, /* cpuss.dw1_tr_in[10] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN11 = 0x4000010Bu, /* cpuss.dw1_tr_in[11] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN12 = 0x4000010Cu, /* cpuss.dw1_tr_in[12] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN13 = 0x4000010Du, /* cpuss.dw1_tr_in[13] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN14 = 0x4000010Eu, /* cpuss.dw1_tr_in[14] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN15 = 0x4000010Fu /* cpuss.dw1_tr_in[15] */
+} en_trig_output_grp1_t;
+
+/* Trigger Output Group 2 - TCPWM trigger inputs */
+typedef enum
+{
+ TRIG2_OUT_TCPWM0_TR_IN0 = 0x40000200u, /* tcpwm[0].tr_in[0] */
+ TRIG2_OUT_TCPWM0_TR_IN1 = 0x40000201u, /* tcpwm[0].tr_in[1] */
+ TRIG2_OUT_TCPWM0_TR_IN2 = 0x40000202u, /* tcpwm[0].tr_in[2] */
+ TRIG2_OUT_TCPWM0_TR_IN3 = 0x40000203u, /* tcpwm[0].tr_in[3] */
+ TRIG2_OUT_TCPWM0_TR_IN4 = 0x40000204u, /* tcpwm[0].tr_in[4] */
+ TRIG2_OUT_TCPWM0_TR_IN5 = 0x40000205u, /* tcpwm[0].tr_in[5] */
+ TRIG2_OUT_TCPWM0_TR_IN6 = 0x40000206u, /* tcpwm[0].tr_in[6] */
+ TRIG2_OUT_TCPWM0_TR_IN7 = 0x40000207u, /* tcpwm[0].tr_in[7] */
+ TRIG2_OUT_TCPWM0_TR_IN8 = 0x40000208u, /* tcpwm[0].tr_in[8] */
+ TRIG2_OUT_TCPWM0_TR_IN9 = 0x40000209u, /* tcpwm[0].tr_in[9] */
+ TRIG2_OUT_TCPWM0_TR_IN10 = 0x4000020Au, /* tcpwm[0].tr_in[10] */
+ TRIG2_OUT_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_in[11] */
+ TRIG2_OUT_TCPWM0_TR_IN12 = 0x4000020Cu, /* tcpwm[0].tr_in[12] */
+ TRIG2_OUT_TCPWM0_TR_IN13 = 0x4000020Du /* tcpwm[0].tr_in[13] */
+} en_trig_output_grp2_t;
+
+/* Trigger Output Group 3 - TCPWM trigger inputs */
+typedef enum
+{
+ TRIG3_OUT_TCPWM1_TR_IN0 = 0x40000300u, /* tcpwm[1].tr_in[0] */
+ TRIG3_OUT_TCPWM1_TR_IN1 = 0x40000301u, /* tcpwm[1].tr_in[1] */
+ TRIG3_OUT_TCPWM1_TR_IN2 = 0x40000302u, /* tcpwm[1].tr_in[2] */
+ TRIG3_OUT_TCPWM1_TR_IN3 = 0x40000303u, /* tcpwm[1].tr_in[3] */
+ TRIG3_OUT_TCPWM1_TR_IN4 = 0x40000304u, /* tcpwm[1].tr_in[4] */
+ TRIG3_OUT_TCPWM1_TR_IN5 = 0x40000305u, /* tcpwm[1].tr_in[5] */
+ TRIG3_OUT_TCPWM1_TR_IN6 = 0x40000306u, /* tcpwm[1].tr_in[6] */
+ TRIG3_OUT_TCPWM1_TR_IN7 = 0x40000307u, /* tcpwm[1].tr_in[7] */
+ TRIG3_OUT_TCPWM1_TR_IN8 = 0x40000308u, /* tcpwm[1].tr_in[8] */
+ TRIG3_OUT_TCPWM1_TR_IN9 = 0x40000309u, /* tcpwm[1].tr_in[9] */
+ TRIG3_OUT_TCPWM1_TR_IN10 = 0x4000030Au, /* tcpwm[1].tr_in[10] */
+ TRIG3_OUT_TCPWM1_TR_IN11 = 0x4000030Bu, /* tcpwm[1].tr_in[11] */
+ TRIG3_OUT_TCPWM1_TR_IN12 = 0x4000030Cu, /* tcpwm[1].tr_in[12] */
+ TRIG3_OUT_TCPWM1_TR_IN13 = 0x4000030Du /* tcpwm[1].tr_in[13] */
+} en_trig_output_grp3_t;
+
+/* Trigger Output Group 4 - PROFILE trigger multiplexer */
+typedef enum
+{
+ TRIG4_OUT_PROFILE_TR_START = 0x40000400u, /* profile.tr_start */
+ TRIG4_OUT_PROFILE_TR_STOP = 0x40000401u /* profile.tr_stop */
+} en_trig_output_grp4_t;
+
+/* Trigger Output Group 5 - CPUSS.CTI trigger multiplexer */
+typedef enum
+{
+ TRIG5_OUT_CPUSS_CTI_TR_IN0 = 0x40000500u, /* cpuss.cti_tr_in[0] */
+ TRIG5_OUT_CPUSS_CTI_TR_IN1 = 0x40000501u /* cpuss.cti_tr_in[1] */
+} en_trig_output_grp5_t;
+
+/* Trigger Output Group 6 - PASS trigger multiplexer */
+typedef enum
+{
+ TRIG6_OUT_PASS_TR_SAR_IN = 0x40000600u /* pass.tr_sar_in */
+} en_trig_output_grp6_t;
+
+/* Trigger Output Group 7 - UDB general purpose trigger multiplexer */
+typedef enum
+{
+ TRIG7_OUT_UDB_TR_IN0 = 0x40000700u, /* udb.tr_in[0] */
+ TRIG7_OUT_UDB_TR_IN1 = 0x40000701u /* udb.tr_in[1] */
+} en_trig_output_grp7_t;
+
+/* Trigger Output Group 8 - Trigger multiplexer to pins */
+typedef enum
+{
+ TRIG8_OUT_PERI_TR_IO_OUTPUT0 = 0x40000800u, /* peri.tr_io_output[0] */
+ TRIG8_OUT_PERI_TR_IO_OUTPUT1 = 0x40000801u /* peri.tr_io_output[1] */
+} en_trig_output_grp8_t;
+
+/* Trigger Output Group 9 - Feedback mux to USB DMA interface */
+typedef enum
+{
+ TRIG9_OUT_USB_DMA_BURSTEND0 = 0x40000900u, /* usb.dma_burstend[0] */
+ TRIG9_OUT_USB_DMA_BURSTEND1 = 0x40000901u, /* usb.dma_burstend[1] */
+ TRIG9_OUT_USB_DMA_BURSTEND2 = 0x40000902u, /* usb.dma_burstend[2] */
+ TRIG9_OUT_USB_DMA_BURSTEND3 = 0x40000903u, /* usb.dma_burstend[3] */
+ TRIG9_OUT_USB_DMA_BURSTEND4 = 0x40000904u, /* usb.dma_burstend[4] */
+ TRIG9_OUT_USB_DMA_BURSTEND5 = 0x40000905u, /* usb.dma_burstend[5] */
+ TRIG9_OUT_USB_DMA_BURSTEND6 = 0x40000906u, /* usb.dma_burstend[6] */
+ TRIG9_OUT_USB_DMA_BURSTEND7 = 0x40000907u /* usb.dma_burstend[7] */
+} en_trig_output_grp9_t;
+
+/* Trigger Output Group 10 - Reduces 32 datawire output triggers to 8 signals, used by all except USB */
+typedef enum
+{
+ TRIG10_OUT_UDB_TR_DW_ACK0 = 0x40000A00u, /* udb.tr_dw_ack[0] */
+ TRIG10_OUT_TR_GROUP0_INPUT1 = 0x40000A00u, /* tr_group[0].input[1] */
+ TRIG10_OUT_TR_GROUP1_INPUT1 = 0x40000A00u, /* tr_group[1].input[1] */
+ TRIG10_OUT_TR_GROUP2_INPUT1 = 0x40000A00u, /* tr_group[2].input[1] */
+ TRIG10_OUT_TR_GROUP3_INPUT1 = 0x40000A00u, /* tr_group[3].input[1] */
+ TRIG10_OUT_TR_GROUP4_INPUT1 = 0x40000A00u, /* tr_group[4].input[1] */
+ TRIG10_OUT_TR_GROUP5_INPUT1 = 0x40000A00u, /* tr_group[5].input[1] */
+ TRIG10_OUT_TR_GROUP6_INPUT1 = 0x40000A00u, /* tr_group[6].input[1] */
+ TRIG10_OUT_TR_GROUP7_INPUT1 = 0x40000A00u, /* tr_group[7].input[1] */
+ TRIG10_OUT_TR_GROUP8_INPUT1 = 0x40000A00u, /* tr_group[8].input[1] */
+ TRIG10_OUT_UDB_TR_DW_ACK1 = 0x40000A01u, /* udb.tr_dw_ack[1] */
+ TRIG10_OUT_TR_GROUP0_INPUT2 = 0x40000A01u, /* tr_group[0].input[2] */
+ TRIG10_OUT_TR_GROUP1_INPUT2 = 0x40000A01u, /* tr_group[1].input[2] */
+ TRIG10_OUT_TR_GROUP2_INPUT2 = 0x40000A01u, /* tr_group[2].input[2] */
+ TRIG10_OUT_TR_GROUP3_INPUT2 = 0x40000A01u, /* tr_group[3].input[2] */
+ TRIG10_OUT_TR_GROUP4_INPUT2 = 0x40000A01u, /* tr_group[4].input[2] */
+ TRIG10_OUT_TR_GROUP5_INPUT2 = 0x40000A01u, /* tr_group[5].input[2] */
+ TRIG10_OUT_TR_GROUP6_INPUT2 = 0x40000A01u, /* tr_group[6].input[2] */
+ TRIG10_OUT_TR_GROUP7_INPUT2 = 0x40000A01u, /* tr_group[7].input[2] */
+ TRIG10_OUT_TR_GROUP8_INPUT2 = 0x40000A01u, /* tr_group[8].input[2] */
+ TRIG10_OUT_UDB_TR_DW_ACK2 = 0x40000A02u, /* udb.tr_dw_ack[2] */
+ TRIG10_OUT_TR_GROUP0_INPUT3 = 0x40000A02u, /* tr_group[0].input[3] */
+ TRIG10_OUT_TR_GROUP1_INPUT3 = 0x40000A02u, /* tr_group[1].input[3] */
+ TRIG10_OUT_TR_GROUP2_INPUT3 = 0x40000A02u, /* tr_group[2].input[3] */
+ TRIG10_OUT_TR_GROUP3_INPUT3 = 0x40000A02u, /* tr_group[3].input[3] */
+ TRIG10_OUT_TR_GROUP4_INPUT3 = 0x40000A02u, /* tr_group[4].input[3] */
+ TRIG10_OUT_TR_GROUP5_INPUT3 = 0x40000A02u, /* tr_group[5].input[3] */
+ TRIG10_OUT_TR_GROUP6_INPUT3 = 0x40000A02u, /* tr_group[6].input[3] */
+ TRIG10_OUT_TR_GROUP7_INPUT3 = 0x40000A02u, /* tr_group[7].input[3] */
+ TRIG10_OUT_TR_GROUP8_INPUT3 = 0x40000A02u, /* tr_group[8].input[3] */
+ TRIG10_OUT_UDB_TR_DW_ACK3 = 0x40000A03u, /* udb.tr_dw_ack[3] */
+ TRIG10_OUT_TR_GROUP0_INPUT4 = 0x40000A03u, /* tr_group[0].input[4] */
+ TRIG10_OUT_TR_GROUP1_INPUT4 = 0x40000A03u, /* tr_group[1].input[4] */
+ TRIG10_OUT_TR_GROUP2_INPUT4 = 0x40000A03u, /* tr_group[2].input[4] */
+ TRIG10_OUT_TR_GROUP3_INPUT4 = 0x40000A03u, /* tr_group[3].input[4] */
+ TRIG10_OUT_TR_GROUP4_INPUT4 = 0x40000A03u, /* tr_group[4].input[4] */
+ TRIG10_OUT_TR_GROUP5_INPUT4 = 0x40000A03u, /* tr_group[5].input[4] */
+ TRIG10_OUT_TR_GROUP6_INPUT4 = 0x40000A03u, /* tr_group[6].input[4] */
+ TRIG10_OUT_TR_GROUP7_INPUT4 = 0x40000A03u, /* tr_group[7].input[4] */
+ TRIG10_OUT_TR_GROUP8_INPUT4 = 0x40000A03u, /* tr_group[8].input[4] */
+ TRIG10_OUT_UDB_TR_DW_ACK4 = 0x40000A04u, /* udb.tr_dw_ack[4] */
+ TRIG10_OUT_TR_GROUP0_INPUT5 = 0x40000A04u, /* tr_group[0].input[5] */
+ TRIG10_OUT_TR_GROUP1_INPUT5 = 0x40000A04u, /* tr_group[1].input[5] */
+ TRIG10_OUT_TR_GROUP2_INPUT5 = 0x40000A04u, /* tr_group[2].input[5] */
+ TRIG10_OUT_TR_GROUP3_INPUT5 = 0x40000A04u, /* tr_group[3].input[5] */
+ TRIG10_OUT_TR_GROUP4_INPUT5 = 0x40000A04u, /* tr_group[4].input[5] */
+ TRIG10_OUT_TR_GROUP5_INPUT5 = 0x40000A04u, /* tr_group[5].input[5] */
+ TRIG10_OUT_TR_GROUP6_INPUT5 = 0x40000A04u, /* tr_group[6].input[5] */
+ TRIG10_OUT_TR_GROUP7_INPUT5 = 0x40000A04u, /* tr_group[7].input[5] */
+ TRIG10_OUT_TR_GROUP8_INPUT5 = 0x40000A04u, /* tr_group[8].input[5] */
+ TRIG10_OUT_UDB_TR_DW_ACK5 = 0x40000A05u, /* udb.tr_dw_ack[5] */
+ TRIG10_OUT_TR_GROUP0_INPUT6 = 0x40000A05u, /* tr_group[0].input[6] */
+ TRIG10_OUT_TR_GROUP1_INPUT6 = 0x40000A05u, /* tr_group[1].input[6] */
+ TRIG10_OUT_TR_GROUP2_INPUT6 = 0x40000A05u, /* tr_group[2].input[6] */
+ TRIG10_OUT_TR_GROUP3_INPUT6 = 0x40000A05u, /* tr_group[3].input[6] */
+ TRIG10_OUT_TR_GROUP4_INPUT6 = 0x40000A05u, /* tr_group[4].input[6] */
+ TRIG10_OUT_TR_GROUP5_INPUT6 = 0x40000A05u, /* tr_group[5].input[6] */
+ TRIG10_OUT_TR_GROUP6_INPUT6 = 0x40000A05u, /* tr_group[6].input[6] */
+ TRIG10_OUT_TR_GROUP7_INPUT6 = 0x40000A05u, /* tr_group[7].input[6] */
+ TRIG10_OUT_TR_GROUP8_INPUT6 = 0x40000A05u, /* tr_group[8].input[6] */
+ TRIG10_OUT_UDB_TR_DW_ACK6 = 0x40000A06u, /* udb.tr_dw_ack[6] */
+ TRIG10_OUT_TR_GROUP0_INPUT7 = 0x40000A06u, /* tr_group[0].input[7] */
+ TRIG10_OUT_TR_GROUP1_INPUT7 = 0x40000A06u, /* tr_group[1].input[7] */
+ TRIG10_OUT_TR_GROUP2_INPUT7 = 0x40000A06u, /* tr_group[2].input[7] */
+ TRIG10_OUT_TR_GROUP3_INPUT7 = 0x40000A06u, /* tr_group[3].input[7] */
+ TRIG10_OUT_TR_GROUP4_INPUT7 = 0x40000A06u, /* tr_group[4].input[7] */
+ TRIG10_OUT_TR_GROUP5_INPUT7 = 0x40000A06u, /* tr_group[5].input[7] */
+ TRIG10_OUT_TR_GROUP6_INPUT7 = 0x40000A06u, /* tr_group[6].input[7] */
+ TRIG10_OUT_TR_GROUP7_INPUT7 = 0x40000A06u, /* tr_group[7].input[7] */
+ TRIG10_OUT_TR_GROUP8_INPUT7 = 0x40000A06u, /* tr_group[8].input[7] */
+ TRIG10_OUT_UDB_TR_DW_ACK7 = 0x40000A07u, /* udb.tr_dw_ack[7] */
+ TRIG10_OUT_TR_GROUP0_INPUT8 = 0x40000A07u, /* tr_group[0].input[8] */
+ TRIG10_OUT_TR_GROUP1_INPUT8 = 0x40000A07u, /* tr_group[1].input[8] */
+ TRIG10_OUT_TR_GROUP2_INPUT8 = 0x40000A07u, /* tr_group[2].input[8] */
+ TRIG10_OUT_TR_GROUP3_INPUT8 = 0x40000A07u, /* tr_group[3].input[8] */
+ TRIG10_OUT_TR_GROUP4_INPUT8 = 0x40000A07u, /* tr_group[4].input[8] */
+ TRIG10_OUT_TR_GROUP5_INPUT8 = 0x40000A07u, /* tr_group[5].input[8] */
+ TRIG10_OUT_TR_GROUP6_INPUT8 = 0x40000A07u, /* tr_group[6].input[8] */
+ TRIG10_OUT_TR_GROUP7_INPUT8 = 0x40000A07u, /* tr_group[7].input[8] */
+ TRIG10_OUT_TR_GROUP8_INPUT8 = 0x40000A07u /* tr_group[8].input[8] */
+} en_trig_output_grp10_t;
+
+/* Trigger Output Group 11 - Reduces 96 tcpwm output triggers to 16 signals, used by all sinks */
+typedef enum
+{
+ TRIG11_OUT_TR_GROUP0_INPUT9 = 0x40000B00u, /* tr_group[0].input[9] */
+ TRIG11_OUT_TR_GROUP1_INPUT9 = 0x40000B00u, /* tr_group[1].input[9] */
+ TRIG11_OUT_TR_GROUP2_INPUT9 = 0x40000B00u, /* tr_group[2].input[9] */
+ TRIG11_OUT_TR_GROUP3_INPUT9 = 0x40000B00u, /* tr_group[3].input[9] */
+ TRIG11_OUT_TR_GROUP4_INPUT9 = 0x40000B00u, /* tr_group[4].input[9] */
+ TRIG11_OUT_TR_GROUP5_INPUT9 = 0x40000B00u, /* tr_group[5].input[9] */
+ TRIG11_OUT_TR_GROUP6_INPUT9 = 0x40000B00u, /* tr_group[6].input[9] */
+ TRIG11_OUT_TR_GROUP7_INPUT9 = 0x40000B00u, /* tr_group[7].input[9] */
+ TRIG11_OUT_TR_GROUP8_INPUT9 = 0x40000B00u, /* tr_group[8].input[9] */
+ TRIG11_OUT_TR_GROUP0_INPUT10 = 0x40000B01u, /* tr_group[0].input[10] */
+ TRIG11_OUT_TR_GROUP1_INPUT10 = 0x40000B01u, /* tr_group[1].input[10] */
+ TRIG11_OUT_TR_GROUP2_INPUT10 = 0x40000B01u, /* tr_group[2].input[10] */
+ TRIG11_OUT_TR_GROUP3_INPUT10 = 0x40000B01u, /* tr_group[3].input[10] */
+ TRIG11_OUT_TR_GROUP4_INPUT10 = 0x40000B01u, /* tr_group[4].input[10] */
+ TRIG11_OUT_TR_GROUP5_INPUT10 = 0x40000B01u, /* tr_group[5].input[10] */
+ TRIG11_OUT_TR_GROUP6_INPUT10 = 0x40000B01u, /* tr_group[6].input[10] */
+ TRIG11_OUT_TR_GROUP7_INPUT10 = 0x40000B01u, /* tr_group[7].input[10] */
+ TRIG11_OUT_TR_GROUP8_INPUT10 = 0x40000B01u, /* tr_group[8].input[10] */
+ TRIG11_OUT_TR_GROUP0_INPUT11 = 0x40000B02u, /* tr_group[0].input[11] */
+ TRIG11_OUT_TR_GROUP1_INPUT11 = 0x40000B02u, /* tr_group[1].input[11] */
+ TRIG11_OUT_TR_GROUP2_INPUT11 = 0x40000B02u, /* tr_group[2].input[11] */
+ TRIG11_OUT_TR_GROUP3_INPUT11 = 0x40000B02u, /* tr_group[3].input[11] */
+ TRIG11_OUT_TR_GROUP4_INPUT11 = 0x40000B02u, /* tr_group[4].input[11] */
+ TRIG11_OUT_TR_GROUP5_INPUT11 = 0x40000B02u, /* tr_group[5].input[11] */
+ TRIG11_OUT_TR_GROUP6_INPUT11 = 0x40000B02u, /* tr_group[6].input[11] */
+ TRIG11_OUT_TR_GROUP7_INPUT11 = 0x40000B02u, /* tr_group[7].input[11] */
+ TRIG11_OUT_TR_GROUP8_INPUT11 = 0x40000B02u, /* tr_group[8].input[11] */
+ TRIG11_OUT_TR_GROUP0_INPUT12 = 0x40000B03u, /* tr_group[0].input[12] */
+ TRIG11_OUT_TR_GROUP1_INPUT12 = 0x40000B03u, /* tr_group[1].input[12] */
+ TRIG11_OUT_TR_GROUP2_INPUT12 = 0x40000B03u, /* tr_group[2].input[12] */
+ TRIG11_OUT_TR_GROUP3_INPUT12 = 0x40000B03u, /* tr_group[3].input[12] */
+ TRIG11_OUT_TR_GROUP4_INPUT12 = 0x40000B03u, /* tr_group[4].input[12] */
+ TRIG11_OUT_TR_GROUP5_INPUT12 = 0x40000B03u, /* tr_group[5].input[12] */
+ TRIG11_OUT_TR_GROUP6_INPUT12 = 0x40000B03u, /* tr_group[6].input[12] */
+ TRIG11_OUT_TR_GROUP7_INPUT12 = 0x40000B03u, /* tr_group[7].input[12] */
+ TRIG11_OUT_TR_GROUP8_INPUT12 = 0x40000B03u, /* tr_group[8].input[12] */
+ TRIG11_OUT_TR_GROUP0_INPUT13 = 0x40000B04u, /* tr_group[0].input[13] */
+ TRIG11_OUT_TR_GROUP1_INPUT13 = 0x40000B04u, /* tr_group[1].input[13] */
+ TRIG11_OUT_TR_GROUP2_INPUT13 = 0x40000B04u, /* tr_group[2].input[13] */
+ TRIG11_OUT_TR_GROUP3_INPUT13 = 0x40000B04u, /* tr_group[3].input[13] */
+ TRIG11_OUT_TR_GROUP4_INPUT13 = 0x40000B04u, /* tr_group[4].input[13] */
+ TRIG11_OUT_TR_GROUP5_INPUT13 = 0x40000B04u, /* tr_group[5].input[13] */
+ TRIG11_OUT_TR_GROUP6_INPUT13 = 0x40000B04u, /* tr_group[6].input[13] */
+ TRIG11_OUT_TR_GROUP7_INPUT13 = 0x40000B04u, /* tr_group[7].input[13] */
+ TRIG11_OUT_TR_GROUP8_INPUT13 = 0x40000B04u, /* tr_group[8].input[13] */
+ TRIG11_OUT_TR_GROUP0_INPUT14 = 0x40000B05u, /* tr_group[0].input[14] */
+ TRIG11_OUT_TR_GROUP1_INPUT14 = 0x40000B05u, /* tr_group[1].input[14] */
+ TRIG11_OUT_TR_GROUP2_INPUT14 = 0x40000B05u, /* tr_group[2].input[14] */
+ TRIG11_OUT_TR_GROUP3_INPUT14 = 0x40000B05u, /* tr_group[3].input[14] */
+ TRIG11_OUT_TR_GROUP4_INPUT14 = 0x40000B05u, /* tr_group[4].input[14] */
+ TRIG11_OUT_TR_GROUP5_INPUT14 = 0x40000B05u, /* tr_group[5].input[14] */
+ TRIG11_OUT_TR_GROUP6_INPUT14 = 0x40000B05u, /* tr_group[6].input[14] */
+ TRIG11_OUT_TR_GROUP7_INPUT14 = 0x40000B05u, /* tr_group[7].input[14] */
+ TRIG11_OUT_TR_GROUP8_INPUT14 = 0x40000B05u, /* tr_group[8].input[14] */
+ TRIG11_OUT_TR_GROUP0_INPUT15 = 0x40000B06u, /* tr_group[0].input[15] */
+ TRIG11_OUT_TR_GROUP1_INPUT15 = 0x40000B06u, /* tr_group[1].input[15] */
+ TRIG11_OUT_TR_GROUP2_INPUT15 = 0x40000B06u, /* tr_group[2].input[15] */
+ TRIG11_OUT_TR_GROUP3_INPUT15 = 0x40000B06u, /* tr_group[3].input[15] */
+ TRIG11_OUT_TR_GROUP4_INPUT15 = 0x40000B06u, /* tr_group[4].input[15] */
+ TRIG11_OUT_TR_GROUP5_INPUT15 = 0x40000B06u, /* tr_group[5].input[15] */
+ TRIG11_OUT_TR_GROUP6_INPUT15 = 0x40000B06u, /* tr_group[6].input[15] */
+ TRIG11_OUT_TR_GROUP7_INPUT15 = 0x40000B06u, /* tr_group[7].input[15] */
+ TRIG11_OUT_TR_GROUP8_INPUT15 = 0x40000B06u, /* tr_group[8].input[15] */
+ TRIG11_OUT_TR_GROUP0_INPUT16 = 0x40000B07u, /* tr_group[0].input[16] */
+ TRIG11_OUT_TR_GROUP1_INPUT16 = 0x40000B07u, /* tr_group[1].input[16] */
+ TRIG11_OUT_TR_GROUP2_INPUT16 = 0x40000B07u, /* tr_group[2].input[16] */
+ TRIG11_OUT_TR_GROUP3_INPUT16 = 0x40000B07u, /* tr_group[3].input[16] */
+ TRIG11_OUT_TR_GROUP4_INPUT16 = 0x40000B07u, /* tr_group[4].input[16] */
+ TRIG11_OUT_TR_GROUP5_INPUT16 = 0x40000B07u, /* tr_group[5].input[16] */
+ TRIG11_OUT_TR_GROUP6_INPUT16 = 0x40000B07u, /* tr_group[6].input[16] */
+ TRIG11_OUT_TR_GROUP7_INPUT16 = 0x40000B07u, /* tr_group[7].input[16] */
+ TRIG11_OUT_TR_GROUP8_INPUT16 = 0x40000B07u, /* tr_group[8].input[16] */
+ TRIG11_OUT_TR_GROUP0_INPUT17 = 0x40000B08u, /* tr_group[0].input[17] */
+ TRIG11_OUT_TR_GROUP1_INPUT17 = 0x40000B08u, /* tr_group[1].input[17] */
+ TRIG11_OUT_TR_GROUP2_INPUT17 = 0x40000B08u, /* tr_group[2].input[17] */
+ TRIG11_OUT_TR_GROUP3_INPUT17 = 0x40000B08u, /* tr_group[3].input[17] */
+ TRIG11_OUT_TR_GROUP4_INPUT17 = 0x40000B08u, /* tr_group[4].input[17] */
+ TRIG11_OUT_TR_GROUP5_INPUT17 = 0x40000B08u, /* tr_group[5].input[17] */
+ TRIG11_OUT_TR_GROUP6_INPUT17 = 0x40000B08u, /* tr_group[6].input[17] */
+ TRIG11_OUT_TR_GROUP7_INPUT17 = 0x40000B08u, /* tr_group[7].input[17] */
+ TRIG11_OUT_TR_GROUP8_INPUT17 = 0x40000B08u, /* tr_group[8].input[17] */
+ TRIG11_OUT_TR_GROUP0_INPUT18 = 0x40000B09u, /* tr_group[0].input[18] */
+ TRIG11_OUT_TR_GROUP1_INPUT18 = 0x40000B09u, /* tr_group[1].input[18] */
+ TRIG11_OUT_TR_GROUP2_INPUT18 = 0x40000B09u, /* tr_group[2].input[18] */
+ TRIG11_OUT_TR_GROUP3_INPUT18 = 0x40000B09u, /* tr_group[3].input[18] */
+ TRIG11_OUT_TR_GROUP4_INPUT18 = 0x40000B09u, /* tr_group[4].input[18] */
+ TRIG11_OUT_TR_GROUP5_INPUT18 = 0x40000B09u, /* tr_group[5].input[18] */
+ TRIG11_OUT_TR_GROUP6_INPUT18 = 0x40000B09u, /* tr_group[6].input[18] */
+ TRIG11_OUT_TR_GROUP7_INPUT18 = 0x40000B09u, /* tr_group[7].input[18] */
+ TRIG11_OUT_TR_GROUP8_INPUT18 = 0x40000B09u, /* tr_group[8].input[18] */
+ TRIG11_OUT_TR_GROUP0_INPUT19 = 0x40000B0Au, /* tr_group[0].input[19] */
+ TRIG11_OUT_TR_GROUP1_INPUT19 = 0x40000B0Au, /* tr_group[1].input[19] */
+ TRIG11_OUT_TR_GROUP2_INPUT19 = 0x40000B0Au, /* tr_group[2].input[19] */
+ TRIG11_OUT_TR_GROUP3_INPUT19 = 0x40000B0Au, /* tr_group[3].input[19] */
+ TRIG11_OUT_TR_GROUP4_INPUT19 = 0x40000B0Au, /* tr_group[4].input[19] */
+ TRIG11_OUT_TR_GROUP5_INPUT19 = 0x40000B0Au, /* tr_group[5].input[19] */
+ TRIG11_OUT_TR_GROUP6_INPUT19 = 0x40000B0Au, /* tr_group[6].input[19] */
+ TRIG11_OUT_TR_GROUP7_INPUT19 = 0x40000B0Au, /* tr_group[7].input[19] */
+ TRIG11_OUT_TR_GROUP8_INPUT19 = 0x40000B0Au, /* tr_group[8].input[19] */
+ TRIG11_OUT_TR_GROUP0_INPUT20 = 0x40000B0Bu, /* tr_group[0].input[20] */
+ TRIG11_OUT_TR_GROUP1_INPUT20 = 0x40000B0Bu, /* tr_group[1].input[20] */
+ TRIG11_OUT_TR_GROUP2_INPUT20 = 0x40000B0Bu, /* tr_group[2].input[20] */
+ TRIG11_OUT_TR_GROUP3_INPUT20 = 0x40000B0Bu, /* tr_group[3].input[20] */
+ TRIG11_OUT_TR_GROUP4_INPUT20 = 0x40000B0Bu, /* tr_group[4].input[20] */
+ TRIG11_OUT_TR_GROUP5_INPUT20 = 0x40000B0Bu, /* tr_group[5].input[20] */
+ TRIG11_OUT_TR_GROUP6_INPUT20 = 0x40000B0Bu, /* tr_group[6].input[20] */
+ TRIG11_OUT_TR_GROUP7_INPUT20 = 0x40000B0Bu, /* tr_group[7].input[20] */
+ TRIG11_OUT_TR_GROUP8_INPUT20 = 0x40000B0Bu, /* tr_group[8].input[20] */
+ TRIG11_OUT_TR_GROUP0_INPUT21 = 0x40000B0Cu, /* tr_group[0].input[21] */
+ TRIG11_OUT_TR_GROUP1_INPUT21 = 0x40000B0Cu, /* tr_group[1].input[21] */
+ TRIG11_OUT_TR_GROUP2_INPUT21 = 0x40000B0Cu, /* tr_group[2].input[21] */
+ TRIG11_OUT_TR_GROUP3_INPUT21 = 0x40000B0Cu, /* tr_group[3].input[21] */
+ TRIG11_OUT_TR_GROUP4_INPUT21 = 0x40000B0Cu, /* tr_group[4].input[21] */
+ TRIG11_OUT_TR_GROUP5_INPUT21 = 0x40000B0Cu, /* tr_group[5].input[21] */
+ TRIG11_OUT_TR_GROUP6_INPUT21 = 0x40000B0Cu, /* tr_group[6].input[21] */
+ TRIG11_OUT_TR_GROUP7_INPUT21 = 0x40000B0Cu, /* tr_group[7].input[21] */
+ TRIG11_OUT_TR_GROUP8_INPUT21 = 0x40000B0Cu, /* tr_group[8].input[21] */
+ TRIG11_OUT_TR_GROUP0_INPUT22 = 0x40000B0Du, /* tr_group[0].input[22] */
+ TRIG11_OUT_TR_GROUP1_INPUT22 = 0x40000B0Du, /* tr_group[1].input[22] */
+ TRIG11_OUT_TR_GROUP2_INPUT22 = 0x40000B0Du, /* tr_group[2].input[22] */
+ TRIG11_OUT_TR_GROUP3_INPUT22 = 0x40000B0Du, /* tr_group[3].input[22] */
+ TRIG11_OUT_TR_GROUP4_INPUT22 = 0x40000B0Du, /* tr_group[4].input[22] */
+ TRIG11_OUT_TR_GROUP5_INPUT22 = 0x40000B0Du, /* tr_group[5].input[22] */
+ TRIG11_OUT_TR_GROUP6_INPUT22 = 0x40000B0Du, /* tr_group[6].input[22] */
+ TRIG11_OUT_TR_GROUP7_INPUT22 = 0x40000B0Du, /* tr_group[7].input[22] */
+ TRIG11_OUT_TR_GROUP8_INPUT22 = 0x40000B0Du, /* tr_group[8].input[22] */
+ TRIG11_OUT_TR_GROUP0_INPUT23 = 0x40000B0Eu, /* tr_group[0].input[23] */
+ TRIG11_OUT_TR_GROUP1_INPUT23 = 0x40000B0Eu, /* tr_group[1].input[23] */
+ TRIG11_OUT_TR_GROUP2_INPUT23 = 0x40000B0Eu, /* tr_group[2].input[23] */
+ TRIG11_OUT_TR_GROUP3_INPUT23 = 0x40000B0Eu, /* tr_group[3].input[23] */
+ TRIG11_OUT_TR_GROUP4_INPUT23 = 0x40000B0Eu, /* tr_group[4].input[23] */
+ TRIG11_OUT_TR_GROUP5_INPUT23 = 0x40000B0Eu, /* tr_group[5].input[23] */
+ TRIG11_OUT_TR_GROUP6_INPUT23 = 0x40000B0Eu, /* tr_group[6].input[23] */
+ TRIG11_OUT_TR_GROUP7_INPUT23 = 0x40000B0Eu, /* tr_group[7].input[23] */
+ TRIG11_OUT_TR_GROUP8_INPUT23 = 0x40000B0Eu, /* tr_group[8].input[23] */
+ TRIG11_OUT_TR_GROUP0_INPUT24 = 0x40000B0Fu, /* tr_group[0].input[24] */
+ TRIG11_OUT_TR_GROUP1_INPUT24 = 0x40000B0Fu, /* tr_group[1].input[24] */
+ TRIG11_OUT_TR_GROUP2_INPUT24 = 0x40000B0Fu, /* tr_group[2].input[24] */
+ TRIG11_OUT_TR_GROUP3_INPUT24 = 0x40000B0Fu, /* tr_group[3].input[24] */
+ TRIG11_OUT_TR_GROUP4_INPUT24 = 0x40000B0Fu, /* tr_group[4].input[24] */
+ TRIG11_OUT_TR_GROUP5_INPUT24 = 0x40000B0Fu, /* tr_group[5].input[24] */
+ TRIG11_OUT_TR_GROUP6_INPUT24 = 0x40000B0Fu, /* tr_group[6].input[24] */
+ TRIG11_OUT_TR_GROUP7_INPUT24 = 0x40000B0Fu, /* tr_group[7].input[24] */
+ TRIG11_OUT_TR_GROUP8_INPUT24 = 0x40000B0Fu /* tr_group[8].input[24] */
+} en_trig_output_grp11_t;
+
+/* Trigger Output Group 12 - Reduces 28 pin input signals to 10 triggers used by all sinks */
+typedef enum
+{
+ TRIG12_OUT_TR_GROUP2_INPUT25 = 0x40000C00u, /* tr_group[2].input[25] */
+ TRIG12_OUT_TR_GROUP3_INPUT25 = 0x40000C00u, /* tr_group[3].input[25] */
+ TRIG12_OUT_TR_GROUP4_INPUT25 = 0x40000C00u, /* tr_group[4].input[25] */
+ TRIG12_OUT_TR_GROUP5_INPUT25 = 0x40000C00u, /* tr_group[5].input[25] */
+ TRIG12_OUT_TR_GROUP6_INPUT25 = 0x40000C00u, /* tr_group[6].input[25] */
+ TRIG12_OUT_TR_GROUP7_INPUT25 = 0x40000C00u, /* tr_group[7].input[25] */
+ TRIG12_OUT_TR_GROUP8_INPUT25 = 0x40000C00u, /* tr_group[8].input[25] */
+ TRIG12_OUT_TR_GROUP2_INPUT26 = 0x40000C01u, /* tr_group[2].input[26] */
+ TRIG12_OUT_TR_GROUP3_INPUT26 = 0x40000C01u, /* tr_group[3].input[26] */
+ TRIG12_OUT_TR_GROUP4_INPUT26 = 0x40000C01u, /* tr_group[4].input[26] */
+ TRIG12_OUT_TR_GROUP5_INPUT26 = 0x40000C01u, /* tr_group[5].input[26] */
+ TRIG12_OUT_TR_GROUP6_INPUT26 = 0x40000C01u, /* tr_group[6].input[26] */
+ TRIG12_OUT_TR_GROUP7_INPUT26 = 0x40000C01u, /* tr_group[7].input[26] */
+ TRIG12_OUT_TR_GROUP8_INPUT26 = 0x40000C01u, /* tr_group[8].input[26] */
+ TRIG12_OUT_TR_GROUP2_INPUT27 = 0x40000C02u, /* tr_group[2].input[27] */
+ TRIG12_OUT_TR_GROUP3_INPUT27 = 0x40000C02u, /* tr_group[3].input[27] */
+ TRIG12_OUT_TR_GROUP4_INPUT27 = 0x40000C02u, /* tr_group[4].input[27] */
+ TRIG12_OUT_TR_GROUP5_INPUT27 = 0x40000C02u, /* tr_group[5].input[27] */
+ TRIG12_OUT_TR_GROUP6_INPUT27 = 0x40000C02u, /* tr_group[6].input[27] */
+ TRIG12_OUT_TR_GROUP7_INPUT27 = 0x40000C02u, /* tr_group[7].input[27] */
+ TRIG12_OUT_TR_GROUP8_INPUT27 = 0x40000C02u, /* tr_group[8].input[27] */
+ TRIG12_OUT_TR_GROUP2_INPUT28 = 0x40000C03u, /* tr_group[2].input[28] */
+ TRIG12_OUT_TR_GROUP3_INPUT28 = 0x40000C03u, /* tr_group[3].input[28] */
+ TRIG12_OUT_TR_GROUP4_INPUT28 = 0x40000C03u, /* tr_group[4].input[28] */
+ TRIG12_OUT_TR_GROUP5_INPUT28 = 0x40000C03u, /* tr_group[5].input[28] */
+ TRIG12_OUT_TR_GROUP6_INPUT28 = 0x40000C03u, /* tr_group[6].input[28] */
+ TRIG12_OUT_TR_GROUP7_INPUT28 = 0x40000C03u, /* tr_group[7].input[28] */
+ TRIG12_OUT_TR_GROUP8_INPUT28 = 0x40000C03u, /* tr_group[8].input[28] */
+ TRIG12_OUT_TR_GROUP2_INPUT29 = 0x40000C04u, /* tr_group[2].input[29] */
+ TRIG12_OUT_TR_GROUP3_INPUT29 = 0x40000C04u, /* tr_group[3].input[29] */
+ TRIG12_OUT_TR_GROUP4_INPUT29 = 0x40000C04u, /* tr_group[4].input[29] */
+ TRIG12_OUT_TR_GROUP5_INPUT29 = 0x40000C04u, /* tr_group[5].input[29] */
+ TRIG12_OUT_TR_GROUP6_INPUT29 = 0x40000C04u, /* tr_group[6].input[29] */
+ TRIG12_OUT_TR_GROUP7_INPUT29 = 0x40000C04u, /* tr_group[7].input[29] */
+ TRIG12_OUT_TR_GROUP8_INPUT29 = 0x40000C04u, /* tr_group[8].input[29] */
+ TRIG12_OUT_TR_GROUP2_INPUT30 = 0x40000C05u, /* tr_group[2].input[30] */
+ TRIG12_OUT_TR_GROUP3_INPUT30 = 0x40000C05u, /* tr_group[3].input[30] */
+ TRIG12_OUT_TR_GROUP4_INPUT30 = 0x40000C05u, /* tr_group[4].input[30] */
+ TRIG12_OUT_TR_GROUP5_INPUT30 = 0x40000C05u, /* tr_group[5].input[30] */
+ TRIG12_OUT_TR_GROUP6_INPUT30 = 0x40000C05u, /* tr_group[6].input[30] */
+ TRIG12_OUT_TR_GROUP7_INPUT30 = 0x40000C05u, /* tr_group[7].input[30] */
+ TRIG12_OUT_TR_GROUP8_INPUT30 = 0x40000C05u, /* tr_group[8].input[30] */
+ TRIG12_OUT_TR_GROUP2_INPUT31 = 0x40000C06u, /* tr_group[2].input[31] */
+ TRIG12_OUT_TR_GROUP3_INPUT31 = 0x40000C06u, /* tr_group[3].input[31] */
+ TRIG12_OUT_TR_GROUP4_INPUT31 = 0x40000C06u, /* tr_group[4].input[31] */
+ TRIG12_OUT_TR_GROUP5_INPUT31 = 0x40000C06u, /* tr_group[5].input[31] */
+ TRIG12_OUT_TR_GROUP6_INPUT31 = 0x40000C06u, /* tr_group[6].input[31] */
+ TRIG12_OUT_TR_GROUP7_INPUT31 = 0x40000C06u, /* tr_group[7].input[31] */
+ TRIG12_OUT_TR_GROUP8_INPUT31 = 0x40000C06u, /* tr_group[8].input[31] */
+ TRIG12_OUT_TR_GROUP2_INPUT32 = 0x40000C07u, /* tr_group[2].input[32] */
+ TRIG12_OUT_TR_GROUP3_INPUT32 = 0x40000C07u, /* tr_group[3].input[32] */
+ TRIG12_OUT_TR_GROUP4_INPUT32 = 0x40000C07u, /* tr_group[4].input[32] */
+ TRIG12_OUT_TR_GROUP5_INPUT32 = 0x40000C07u, /* tr_group[5].input[32] */
+ TRIG12_OUT_TR_GROUP6_INPUT32 = 0x40000C07u, /* tr_group[6].input[32] */
+ TRIG12_OUT_TR_GROUP7_INPUT32 = 0x40000C07u, /* tr_group[7].input[32] */
+ TRIG12_OUT_TR_GROUP8_INPUT32 = 0x40000C07u, /* tr_group[8].input[32] */
+ TRIG12_OUT_TR_GROUP0_INPUT25 = 0x40000C08u, /* tr_group[0].input[25] */
+ TRIG12_OUT_TR_GROUP1_INPUT25 = 0x40000C08u, /* tr_group[1].input[25] */
+ TRIG12_OUT_TR_GROUP0_INPUT26 = 0x40000C09u, /* tr_group[0].input[26] */
+ TRIG12_OUT_TR_GROUP1_INPUT26 = 0x40000C09u /* tr_group[1].input[26] */
+} en_trig_output_grp12_t;
+
+/* Trigger Output Group 13 - Reduces DMA requests to 16+2 outputs used by all sinks */
+typedef enum
+{
+ TRIG13_OUT_TR_GROUP0_INPUT27 = 0x40000D00u, /* tr_group[0].input[27] */
+ TRIG13_OUT_TR_GROUP1_INPUT27 = 0x40000D00u, /* tr_group[1].input[27] */
+ TRIG13_OUT_TR_GROUP0_INPUT28 = 0x40000D01u, /* tr_group[0].input[28] */
+ TRIG13_OUT_TR_GROUP1_INPUT28 = 0x40000D01u, /* tr_group[1].input[28] */
+ TRIG13_OUT_TR_GROUP0_INPUT29 = 0x40000D02u, /* tr_group[0].input[29] */
+ TRIG13_OUT_TR_GROUP1_INPUT29 = 0x40000D02u, /* tr_group[1].input[29] */
+ TRIG13_OUT_TR_GROUP0_INPUT30 = 0x40000D03u, /* tr_group[0].input[30] */
+ TRIG13_OUT_TR_GROUP1_INPUT30 = 0x40000D03u, /* tr_group[1].input[30] */
+ TRIG13_OUT_TR_GROUP0_INPUT31 = 0x40000D04u, /* tr_group[0].input[31] */
+ TRIG13_OUT_TR_GROUP1_INPUT31 = 0x40000D04u, /* tr_group[1].input[31] */
+ TRIG13_OUT_TR_GROUP0_INPUT32 = 0x40000D05u, /* tr_group[0].input[32] */
+ TRIG13_OUT_TR_GROUP1_INPUT32 = 0x40000D05u, /* tr_group[1].input[32] */
+ TRIG13_OUT_TR_GROUP0_INPUT33 = 0x40000D06u, /* tr_group[0].input[33] */
+ TRIG13_OUT_TR_GROUP1_INPUT33 = 0x40000D06u, /* tr_group[1].input[33] */
+ TRIG13_OUT_TR_GROUP0_INPUT34 = 0x40000D07u, /* tr_group[0].input[34] */
+ TRIG13_OUT_TR_GROUP1_INPUT34 = 0x40000D07u, /* tr_group[1].input[34] */
+ TRIG13_OUT_TR_GROUP0_INPUT35 = 0x40000D08u, /* tr_group[0].input[35] */
+ TRIG13_OUT_TR_GROUP1_INPUT35 = 0x40000D08u, /* tr_group[1].input[35] */
+ TRIG13_OUT_TR_GROUP0_INPUT36 = 0x40000D09u, /* tr_group[0].input[36] */
+ TRIG13_OUT_TR_GROUP1_INPUT36 = 0x40000D09u, /* tr_group[1].input[36] */
+ TRIG13_OUT_TR_GROUP0_INPUT37 = 0x40000D0Au, /* tr_group[0].input[37] */
+ TRIG13_OUT_TR_GROUP1_INPUT37 = 0x40000D0Au, /* tr_group[1].input[37] */
+ TRIG13_OUT_TR_GROUP0_INPUT38 = 0x40000D0Bu, /* tr_group[0].input[38] */
+ TRIG13_OUT_TR_GROUP1_INPUT38 = 0x40000D0Bu, /* tr_group[1].input[38] */
+ TRIG13_OUT_TR_GROUP0_INPUT39 = 0x40000D0Cu, /* tr_group[0].input[39] */
+ TRIG13_OUT_TR_GROUP1_INPUT39 = 0x40000D0Cu, /* tr_group[1].input[39] */
+ TRIG13_OUT_TR_GROUP0_INPUT40 = 0x40000D0Du, /* tr_group[0].input[40] */
+ TRIG13_OUT_TR_GROUP1_INPUT40 = 0x40000D0Du, /* tr_group[1].input[40] */
+ TRIG13_OUT_TR_GROUP0_INPUT41 = 0x40000D0Eu, /* tr_group[0].input[41] */
+ TRIG13_OUT_TR_GROUP1_INPUT41 = 0x40000D0Eu, /* tr_group[1].input[41] */
+ TRIG13_OUT_TR_GROUP0_INPUT42 = 0x40000D0Fu, /* tr_group[0].input[42] */
+ TRIG13_OUT_TR_GROUP1_INPUT42 = 0x40000D0Fu, /* tr_group[1].input[42] */
+ TRIG13_OUT_TR_GROUP2_INPUT33 = 0x40000D10u, /* tr_group[2].input[33] */
+ TRIG13_OUT_TR_GROUP3_INPUT33 = 0x40000D10u, /* tr_group[3].input[33] */
+ TRIG13_OUT_TR_GROUP4_INPUT33 = 0x40000D10u, /* tr_group[4].input[33] */
+ TRIG13_OUT_TR_GROUP5_INPUT33 = 0x40000D10u, /* tr_group[5].input[33] */
+ TRIG13_OUT_TR_GROUP6_INPUT33 = 0x40000D10u, /* tr_group[6].input[33] */
+ TRIG13_OUT_TR_GROUP7_INPUT33 = 0x40000D10u, /* tr_group[7].input[33] */
+ TRIG13_OUT_TR_GROUP8_INPUT33 = 0x40000D10u, /* tr_group[8].input[33] */
+ TRIG13_OUT_TR_GROUP2_INPUT34 = 0x40000D11u, /* tr_group[2].input[34] */
+ TRIG13_OUT_TR_GROUP3_INPUT34 = 0x40000D11u, /* tr_group[3].input[34] */
+ TRIG13_OUT_TR_GROUP4_INPUT34 = 0x40000D11u, /* tr_group[4].input[34] */
+ TRIG13_OUT_TR_GROUP5_INPUT34 = 0x40000D11u, /* tr_group[5].input[34] */
+ TRIG13_OUT_TR_GROUP6_INPUT34 = 0x40000D11u, /* tr_group[6].input[34] */
+ TRIG13_OUT_TR_GROUP7_INPUT34 = 0x40000D11u, /* tr_group[7].input[34] */
+ TRIG13_OUT_TR_GROUP8_INPUT34 = 0x40000D11u /* tr_group[8].input[34] */
+} en_trig_output_grp13_t;
+
+/* Trigger Output Group 14 - Reduces general purpose trigger inputs to 8+8 outputs used by all sinks */
+typedef enum
+{
+ TRIG14_OUT_TR_GROUP0_INPUT43 = 0x40000E00u, /* tr_group[0].input[43] */
+ TRIG14_OUT_TR_GROUP1_INPUT43 = 0x40000E00u, /* tr_group[1].input[43] */
+ TRIG14_OUT_TR_GROUP0_INPUT44 = 0x40000E01u, /* tr_group[0].input[44] */
+ TRIG14_OUT_TR_GROUP1_INPUT44 = 0x40000E01u, /* tr_group[1].input[44] */
+ TRIG14_OUT_TR_GROUP0_INPUT45 = 0x40000E02u, /* tr_group[0].input[45] */
+ TRIG14_OUT_TR_GROUP1_INPUT45 = 0x40000E02u, /* tr_group[1].input[45] */
+ TRIG14_OUT_TR_GROUP0_INPUT46 = 0x40000E03u, /* tr_group[0].input[46] */
+ TRIG14_OUT_TR_GROUP1_INPUT46 = 0x40000E03u, /* tr_group[1].input[46] */
+ TRIG14_OUT_TR_GROUP0_INPUT47 = 0x40000E04u, /* tr_group[0].input[47] */
+ TRIG14_OUT_TR_GROUP1_INPUT47 = 0x40000E04u, /* tr_group[1].input[47] */
+ TRIG14_OUT_TR_GROUP0_INPUT48 = 0x40000E05u, /* tr_group[0].input[48] */
+ TRIG14_OUT_TR_GROUP1_INPUT48 = 0x40000E05u, /* tr_group[1].input[48] */
+ TRIG14_OUT_TR_GROUP0_INPUT49 = 0x40000E06u, /* tr_group[0].input[49] */
+ TRIG14_OUT_TR_GROUP1_INPUT49 = 0x40000E06u, /* tr_group[1].input[49] */
+ TRIG14_OUT_TR_GROUP0_INPUT50 = 0x40000E07u, /* tr_group[0].input[50] */
+ TRIG14_OUT_TR_GROUP1_INPUT50 = 0x40000E07u, /* tr_group[1].input[50] */
+ TRIG14_OUT_TR_GROUP2_INPUT35 = 0x40000E08u, /* tr_group[2].input[35] */
+ TRIG14_OUT_TR_GROUP3_INPUT35 = 0x40000E08u, /* tr_group[3].input[35] */
+ TRIG14_OUT_TR_GROUP4_INPUT35 = 0x40000E08u, /* tr_group[4].input[35] */
+ TRIG14_OUT_TR_GROUP5_INPUT35 = 0x40000E08u, /* tr_group[5].input[35] */
+ TRIG14_OUT_TR_GROUP6_INPUT35 = 0x40000E08u, /* tr_group[6].input[35] */
+ TRIG14_OUT_TR_GROUP7_INPUT35 = 0x40000E08u, /* tr_group[7].input[35] */
+ TRIG14_OUT_TR_GROUP8_INPUT35 = 0x40000E08u, /* tr_group[8].input[35] */
+ TRIG14_OUT_TR_GROUP2_INPUT36 = 0x40000E09u, /* tr_group[2].input[36] */
+ TRIG14_OUT_TR_GROUP3_INPUT36 = 0x40000E09u, /* tr_group[3].input[36] */
+ TRIG14_OUT_TR_GROUP4_INPUT36 = 0x40000E09u, /* tr_group[4].input[36] */
+ TRIG14_OUT_TR_GROUP5_INPUT36 = 0x40000E09u, /* tr_group[5].input[36] */
+ TRIG14_OUT_TR_GROUP6_INPUT36 = 0x40000E09u, /* tr_group[6].input[36] */
+ TRIG14_OUT_TR_GROUP7_INPUT36 = 0x40000E09u, /* tr_group[7].input[36] */
+ TRIG14_OUT_TR_GROUP8_INPUT36 = 0x40000E09u, /* tr_group[8].input[36] */
+ TRIG14_OUT_TR_GROUP2_INPUT37 = 0x40000E0Au, /* tr_group[2].input[37] */
+ TRIG14_OUT_TR_GROUP3_INPUT37 = 0x40000E0Au, /* tr_group[3].input[37] */
+ TRIG14_OUT_TR_GROUP4_INPUT37 = 0x40000E0Au, /* tr_group[4].input[37] */
+ TRIG14_OUT_TR_GROUP5_INPUT37 = 0x40000E0Au, /* tr_group[5].input[37] */
+ TRIG14_OUT_TR_GROUP6_INPUT37 = 0x40000E0Au, /* tr_group[6].input[37] */
+ TRIG14_OUT_TR_GROUP7_INPUT37 = 0x40000E0Au, /* tr_group[7].input[37] */
+ TRIG14_OUT_TR_GROUP8_INPUT37 = 0x40000E0Au, /* tr_group[8].input[37] */
+ TRIG14_OUT_TR_GROUP2_INPUT38 = 0x40000E0Bu, /* tr_group[2].input[38] */
+ TRIG14_OUT_TR_GROUP3_INPUT38 = 0x40000E0Bu, /* tr_group[3].input[38] */
+ TRIG14_OUT_TR_GROUP4_INPUT38 = 0x40000E0Bu, /* tr_group[4].input[38] */
+ TRIG14_OUT_TR_GROUP5_INPUT38 = 0x40000E0Bu, /* tr_group[5].input[38] */
+ TRIG14_OUT_TR_GROUP6_INPUT38 = 0x40000E0Bu, /* tr_group[6].input[38] */
+ TRIG14_OUT_TR_GROUP7_INPUT38 = 0x40000E0Bu, /* tr_group[7].input[38] */
+ TRIG14_OUT_TR_GROUP8_INPUT38 = 0x40000E0Bu, /* tr_group[8].input[38] */
+ TRIG14_OUT_TR_GROUP2_INPUT39 = 0x40000E0Cu, /* tr_group[2].input[39] */
+ TRIG14_OUT_TR_GROUP3_INPUT39 = 0x40000E0Cu, /* tr_group[3].input[39] */
+ TRIG14_OUT_TR_GROUP4_INPUT39 = 0x40000E0Cu, /* tr_group[4].input[39] */
+ TRIG14_OUT_TR_GROUP5_INPUT39 = 0x40000E0Cu, /* tr_group[5].input[39] */
+ TRIG14_OUT_TR_GROUP6_INPUT39 = 0x40000E0Cu, /* tr_group[6].input[39] */
+ TRIG14_OUT_TR_GROUP7_INPUT39 = 0x40000E0Cu, /* tr_group[7].input[39] */
+ TRIG14_OUT_TR_GROUP8_INPUT39 = 0x40000E0Cu, /* tr_group[8].input[39] */
+ TRIG14_OUT_TR_GROUP2_INPUT40 = 0x40000E0Du, /* tr_group[2].input[40] */
+ TRIG14_OUT_TR_GROUP3_INPUT40 = 0x40000E0Du, /* tr_group[3].input[40] */
+ TRIG14_OUT_TR_GROUP4_INPUT40 = 0x40000E0Du, /* tr_group[4].input[40] */
+ TRIG14_OUT_TR_GROUP5_INPUT40 = 0x40000E0Du, /* tr_group[5].input[40] */
+ TRIG14_OUT_TR_GROUP6_INPUT40 = 0x40000E0Du, /* tr_group[6].input[40] */
+ TRIG14_OUT_TR_GROUP7_INPUT40 = 0x40000E0Du, /* tr_group[7].input[40] */
+ TRIG14_OUT_TR_GROUP8_INPUT40 = 0x40000E0Du, /* tr_group[8].input[40] */
+ TRIG14_OUT_TR_GROUP2_INPUT41 = 0x40000E0Eu, /* tr_group[2].input[41] */
+ TRIG14_OUT_TR_GROUP3_INPUT41 = 0x40000E0Eu, /* tr_group[3].input[41] */
+ TRIG14_OUT_TR_GROUP4_INPUT41 = 0x40000E0Eu, /* tr_group[4].input[41] */
+ TRIG14_OUT_TR_GROUP5_INPUT41 = 0x40000E0Eu, /* tr_group[5].input[41] */
+ TRIG14_OUT_TR_GROUP6_INPUT41 = 0x40000E0Eu, /* tr_group[6].input[41] */
+ TRIG14_OUT_TR_GROUP7_INPUT41 = 0x40000E0Eu, /* tr_group[7].input[41] */
+ TRIG14_OUT_TR_GROUP8_INPUT41 = 0x40000E0Eu, /* tr_group[8].input[41] */
+ TRIG14_OUT_TR_GROUP2_INPUT42 = 0x40000E0Fu, /* tr_group[2].input[42] */
+ TRIG14_OUT_TR_GROUP3_INPUT42 = 0x40000E0Fu, /* tr_group[3].input[42] */
+ TRIG14_OUT_TR_GROUP4_INPUT42 = 0x40000E0Fu, /* tr_group[4].input[42] */
+ TRIG14_OUT_TR_GROUP5_INPUT42 = 0x40000E0Fu, /* tr_group[5].input[42] */
+ TRIG14_OUT_TR_GROUP6_INPUT42 = 0x40000E0Fu, /* tr_group[6].input[42] */
+ TRIG14_OUT_TR_GROUP7_INPUT42 = 0x40000E0Fu, /* tr_group[7].input[42] */
+ TRIG14_OUT_TR_GROUP8_INPUT42 = 0x40000E0Fu /* tr_group[8].input[42] */
+} en_trig_output_grp14_t;
+
+/* Level or edge detection setting for a trigger mux */
+typedef enum
+{
+ /* The trigger is a simple level output */
+ TRIGGER_TYPE_LEVEL = 0u,
+ /* The trigger is synchronized to the consumer blocks clock
+ and a two cycle pulse is generated on this clock */
+ TRIGGER_TYPE_EDGE = 1u
+} en_trig_type_t;
+
+/* Trigger Type Defines */
+/* TCPWM Trigger Types */
+#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE
+/* CSD Trigger Types */
+#define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE
+/* SCB Trigger Types */
+#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL
+/* PERI Trigger Types */
+#define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE
+/* CPUSS Trigger Types */
+#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE
+/* AUDIOSS Trigger Types */
+#define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL
+/* LPCOMP Trigger Types */
+#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL
+/* PASS Trigger Types */
+#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY TRIGGER_TYPE_EDGE
+/* SMIF Trigger Types */
+#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL
+/* USB Trigger Types */
+#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE
+/* UDB Trigger Types */
+#define TRIGGER_TYPE_UDB_TR_IN__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_UDB_TR_IN__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_UDB_TR_DW_ACK__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_UDB_TR_DW_ACK__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_UDB_TR_UDB__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_UDB_TR_UDB__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_UDB_DSI_OUT_TR__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_UDB_DSI_OUT_TR__EDGE TRIGGER_TYPE_EDGE
+/* PROFILE Trigger Types */
+#define TRIGGER_TYPE_PROFILE_TR_START TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_PROFILE_TR_STOP TRIGGER_TYPE_EDGE
+/* TR_GROUP Trigger Types */
+#define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_TR_GROUP_INPUT__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_TR_GROUP_INPUT__EDGE TRIGGER_TYPE_EDGE
+
+/* Monitor Signal Defines */
+typedef enum
+{
+ PROFILE_ONE = 0, /* profile.one */
+ CPUSS_MONITOR_CM0 = 1, /* cpuss.monitor_cm0 */
+ CPUSS_MONITOR_CM4 = 2, /* cpuss.monitor_cm4 */
+ CPUSS_MONITOR_FLASH = 3, /* cpuss.monitor_flash */
+ CPUSS_MONITOR_DW0_AHB = 4, /* cpuss.monitor_dw0_ahb */
+ CPUSS_MONITOR_DW1_AHB = 5, /* cpuss.monitor_dw1_ahb */
+ CPUSS_MONITOR_CRYPTO = 6, /* cpuss.monitor_crypto */
+ USB_MONITOR_AHB = 7, /* usb.monitor_ahb */
+ SCB0_MONITOR_AHB = 8, /* scb[0].monitor_ahb */
+ SCB1_MONITOR_AHB = 9, /* scb[1].monitor_ahb */
+ SCB2_MONITOR_AHB = 10, /* scb[2].monitor_ahb */
+ SCB3_MONITOR_AHB = 11, /* scb[3].monitor_ahb */
+ SCB4_MONITOR_AHB = 12, /* scb[4].monitor_ahb */
+ SCB5_MONITOR_AHB = 13, /* scb[5].monitor_ahb */
+ SCB6_MONITOR_AHB = 14, /* scb[6].monitor_ahb */
+ SCB7_MONITOR_AHB = 15, /* scb[7].monitor_ahb */
+ SCB8_MONITOR_AHB = 16, /* scb[8].monitor_ahb */
+ UDB_MONITOR_UDB0 = 17, /* udb.monitor_udb[0] */
+ UDB_MONITOR_UDB1 = 18, /* udb.monitor_udb[1] */
+ UDB_MONITOR_UDB2 = 19, /* udb.monitor_udb[2] */
+ UDB_MONITOR_UDB3 = 20, /* udb.monitor_udb[3] */
+ SMIF_MONITOR_SMIF_SPI_SELECT0 = 21, /* smif.monitor_smif_spi_select[0] */
+ SMIF_MONITOR_SMIF_SPI_SELECT1 = 22, /* smif.monitor_smif_spi_select[1] */
+ SMIF_MONITOR_SMIF_SPI_SELECT2 = 23, /* smif.monitor_smif_spi_select[2] */
+ SMIF_MONITOR_SMIF_SPI_SELECT3 = 24, /* smif.monitor_smif_spi_select[3] */
+ SMIF_MONITOR_SMIF_SPI_SELECT_ANY = 25, /* smif.monitor_smif_spi_select_any */
+ BLESS_EXT_LNA_RX_CTL_OUT = 26, /* bless.ext_lna_rx_ctl_out */
+ BLESS_EXT_PA_TX_CTL_OUT = 27 /* bless.ext_pa_tx_ctl_out */
+} en_ep_mon_sel_t;
+
+/* Total count of Energy Profiler monitor signal connections */
+#define EP_MONITOR_COUNT 28u
+
+/* Bus masters */
+typedef enum
+{
+ CPUSS_MS_ID_CM0 = 0,
+ CPUSS_MS_ID_CRYPTO = 1,
+ CPUSS_MS_ID_DW0 = 2,
+ CPUSS_MS_ID_DW1 = 3,
+ CPUSS_MS_ID_CM4 = 14,
+ CPUSS_MS_ID_TC = 15
+} en_prot_master_t;
+
+/* Pointer to device configuration structure */
+#define CY_DEVICE_CFG (&cy_deviceIpBlockCfgPSoC6_01)
+
+/* Include IP definitions */
+#include "ip/cyip_sflash.h"
+#include "ip/cyip_peri.h"
+#include "ip/cyip_crypto.h"
+#include "ip/cyip_cpuss.h"
+#include "ip/cyip_fault.h"
+#include "ip/cyip_ipc.h"
+#include "ip/cyip_prot.h"
+#include "ip/cyip_flashc.h"
+#include "ip/cyip_srss.h"
+#include "ip/cyip_backup.h"
+#include "ip/cyip_dw.h"
+#include "ip/cyip_efuse.h"
+#include "ip/cyip_efuse_data_psoc6_01.h"
+#include "ip/cyip_profile.h"
+#include "ip/cyip_hsiom.h"
+#include "ip/cyip_gpio.h"
+#include "ip/cyip_smartio.h"
+#include "ip/cyip_udb.h"
+#include "ip/cyip_lpcomp.h"
+#include "ip/cyip_csd.h"
+#include "ip/cyip_tcpwm.h"
+#include "ip/cyip_lcd.h"
+#include "ip/cyip_ble.h"
+#include "ip/cyip_usbfs.h"
+#include "ip/cyip_smif.h"
+#include "ip/cyip_scb.h"
+#include "ip/cyip_ctbm.h"
+#include "ip/cyip_ctdac.h"
+#include "ip/cyip_sar.h"
+#include "ip/cyip_pass.h"
+#include "ip/cyip_i2s.h"
+#include "ip/cyip_pdm.h"
+
+/* IP type definitions */
+typedef SFLASH_V1_Type SFLASH_Type;
+typedef PERI_GR_V1_Type PERI_GR_Type;
+typedef PERI_TR_GR_V1_Type PERI_TR_GR_Type;
+typedef PERI_PPU_PR_V1_Type PERI_PPU_PR_Type;
+typedef PERI_PPU_GR_V1_Type PERI_PPU_GR_Type;
+typedef PERI_GR_PPU_SL_V1_Type PERI_GR_PPU_SL_Type;
+typedef PERI_GR_PPU_RG_V1_Type PERI_GR_PPU_RG_Type;
+typedef PERI_V1_Type PERI_Type;
+typedef CRYPTO_V1_Type CRYPTO_Type;
+typedef CPUSS_V1_Type CPUSS_Type;
+typedef FAULT_STRUCT_V1_Type FAULT_STRUCT_Type;
+typedef FAULT_V1_Type FAULT_Type;
+typedef IPC_STRUCT_V1_Type IPC_STRUCT_Type;
+typedef IPC_INTR_STRUCT_V1_Type IPC_INTR_STRUCT_Type;
+typedef IPC_V1_Type IPC_Type;
+typedef PROT_SMPU_SMPU_STRUCT_V1_Type PROT_SMPU_SMPU_STRUCT_Type;
+typedef PROT_SMPU_V1_Type PROT_SMPU_Type;
+typedef PROT_MPU_MPU_STRUCT_V1_Type PROT_MPU_MPU_STRUCT_Type;
+typedef PROT_MPU_V1_Type PROT_MPU_Type;
+typedef PROT_V1_Type PROT_Type;
+typedef FLASHC_FM_CTL_V1_Type FLASHC_FM_CTL_Type;
+typedef FLASHC_V1_Type FLASHC_Type;
+typedef MCWDT_STRUCT_V1_Type MCWDT_STRUCT_Type;
+typedef SRSS_V1_Type SRSS_Type;
+typedef BACKUP_V1_Type BACKUP_Type;
+typedef DW_CH_STRUCT_V1_Type DW_CH_STRUCT_Type;
+typedef DW_V1_Type DW_Type;
+typedef EFUSE_V1_Type EFUSE_Type;
+typedef PROFILE_CNT_STRUCT_V1_Type PROFILE_CNT_STRUCT_Type;
+typedef PROFILE_V1_Type PROFILE_Type;
+typedef HSIOM_PRT_V1_Type HSIOM_PRT_Type;
+typedef HSIOM_V1_Type HSIOM_Type;
+typedef GPIO_PRT_V1_Type GPIO_PRT_Type;
+typedef GPIO_V1_Type GPIO_Type;
+typedef SMARTIO_PRT_V1_Type SMARTIO_PRT_Type;
+typedef SMARTIO_V1_Type SMARTIO_Type;
+typedef UDB_WRKONE_V1_Type UDB_WRKONE_Type;
+typedef UDB_WRKMULT_V1_Type UDB_WRKMULT_Type;
+typedef UDB_UDBPAIR_UDBSNG_V1_Type UDB_UDBPAIR_UDBSNG_Type;
+typedef UDB_UDBPAIR_ROUTE_V1_Type UDB_UDBPAIR_ROUTE_Type;
+typedef UDB_UDBPAIR_V1_Type UDB_UDBPAIR_Type;
+typedef UDB_DSI_V1_Type UDB_DSI_Type;
+typedef UDB_PA_V1_Type UDB_PA_Type;
+typedef UDB_BCTL_V1_Type UDB_BCTL_Type;
+typedef UDB_UDBIF_V1_Type UDB_UDBIF_Type;
+typedef UDB_V1_Type UDB_Type;
+typedef LPCOMP_V1_Type LPCOMP_Type;
+typedef CSD_V1_Type CSD_Type;
+typedef TCPWM_CNT_V1_Type TCPWM_CNT_Type;
+typedef TCPWM_V1_Type TCPWM_Type;
+typedef LCD_V1_Type LCD_Type;
+typedef BLE_RCB_RCBLL_V1_Type BLE_RCB_RCBLL_Type;
+typedef BLE_RCB_V1_Type BLE_RCB_Type;
+typedef BLE_BLELL_V1_Type BLE_BLELL_Type;
+typedef BLE_BLESS_V1_Type BLE_BLESS_Type;
+typedef BLE_V1_Type BLE_Type;
+typedef USBFS_USBDEV_V1_Type USBFS_USBDEV_Type;
+typedef USBFS_USBLPM_V1_Type USBFS_USBLPM_Type;
+typedef USBFS_USBHOST_V1_Type USBFS_USBHOST_Type;
+typedef USBFS_V1_Type USBFS_Type;
+typedef SMIF_DEVICE_V1_Type SMIF_DEVICE_Type;
+typedef SMIF_V1_Type SMIF_Type;
+typedef CySCB_V1_Type CySCB_Type;
+typedef CTBM_V1_Type CTBM_Type;
+typedef CTDAC_V1_Type CTDAC_Type;
+typedef SAR_V1_Type SAR_Type;
+typedef PASS_AREF_V1_Type PASS_AREF_Type;
+typedef PASS_V1_Type PASS_Type;
+typedef I2S_V1_Type I2S_Type;
+typedef PDM_V1_Type PDM_Type;
+
+/* Parameter Defines */
+/* Number of regulator modules instantiated within SRSS */
+#define SRSS_NUM_ACTREG_PWRMOD 2u
+/* Number of shorting switches between vccd and vccact */
+#define SRSS_NUM_ACTIVE_SWITCH 3u
+/* ULP linear regulator system is present */
+#define SRSS_ULPLINREG_PRESENT 1u
+/* HT linear regulator system is present */
+#define SRSS_HTLINREG_PRESENT 0u
+/* SIMO buck core regulator is present. Only compatible with ULP linear regulator
+ system (ULPLINREG_PRESENT==1). */
+#define SRSS_SIMOBUCK_PRESENT 1u
+/* Precision ILO (PILO) is present */
+#define SRSS_PILO_PRESENT 1u
+/* External Crystal Oscillator is present (high frequency) */
+#define SRSS_ECO_PRESENT 1u
+/* System Buck-Boost is present */
+#define SRSS_SYSBB_PRESENT 0u
+/* Number of clock paths. Must be > 0 */
+#define SRSS_NUM_CLKPATH 5u
+/* Number of PLLs present. Must be <= NUM_CLKPATH */
+#define SRSS_NUM_PLL 1u
+/* Number of HFCLK roots present. Must be > 0 */
+#define SRSS_NUM_HFROOT 5u
+/* Number of PWR_HIB_DATA registers */
+#define SRSS_NUM_HIBDATA 1u
+/* Backup domain is present */
+#define SRSS_BACKUP_PRESENT 1u
+/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of
+ mask indicates presence of a CSV. */
+#define SRSS_MASK_HFCSV 0u
+/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */
+#define SRSS_WCOCSV_PRESENT 0u
+/* Number of software watchdog timers. */
+#define SRSS_NUM_MCWDT 2u
+/* Number of DSI inputs into clock muxes. This is used for logic optimization. */
+#define SRSS_NUM_DSI 2u
+/* Alternate high-frequency clock is present. This is used for logic optimization. */
+#define SRSS_ALTHF_PRESENT 1u
+/* Alternate low-frequency clock is present. This is used for logic optimization. */
+#define SRSS_ALTLF_PRESENT 0u
+/* Use the hardened clkactfllmux block */
+#define SRSS_USE_HARD_CLKACTFLLMUX 1u
+/* Number of clock paths, including direct paths in hardened clkactfllmux block
+ (Must be >= NUM_CLKPATH) */
+#define SRSS_HARD_CLKPATH 6u
+/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >=
+ NUM_PLL+1) */
+#define SRSS_HARD_CLKPATHMUX 6u
+/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */
+#define SRSS_HARD_HFROOT 6u
+/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */
+#define SRSS_HARD_ECOMUX_PRESENT 1u
+/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */
+#define SRSS_HARD_ALTHFMUX_PRESENT 1u
+/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT
+ or SIMOBUCK_PRESENT. */
+#define SRSS_BUCKCTL_PRESENT 1u
+/* Low-current SISO buck core regulator is present. Only compatible with ULP
+ linear regulator system (ULPLINREG_PRESENT==1). */
+#define SRSS_S40S_SISOBUCKLC_PRESENT 0u
+/* Backup memory is present (only used when BACKUP_PRESENT==1) */
+#define SRSS_BACKUP_BMEM_PRESENT 0u
+/* Number of Backup registers to include (each is 32b). Only used when
+ BACKUP_PRESENT==1. */
+#define SRSS_BACKUP_NUM_BREG 16u
+/* Number of AMUX splitter cells */
+#define IOSS_HSIOM_AMUX_SPLIT_NR 9u
+/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */
+#define IOSS_HSIOM_HSIOM_PORT_NR 15u
+/* Number of GPIO ports in range 0..31 */
+#define IOSS_GPIO_GPIO_PORT_NR_0_31 15u
+/* Number of GPIO ports in range 32..63 */
+#define IOSS_GPIO_GPIO_PORT_NR_32_63 0u
+/* Number of GPIO ports in range 64..95 */
+#define IOSS_GPIO_GPIO_PORT_NR_64_95 0u
+/* Number of GPIO ports in range 96..127 */
+#define IOSS_GPIO_GPIO_PORT_NR_96_127 0u
+/* Number of ports in device */
+#define IOSS_GPIO_GPIO_PORT_NR 15u
+/* Mask of SMARTIO instances presence */
+#define IOSS_SMARTIO_SMARTIO_MASK 768u
+/* The number of protection contexts ([2, 16]). */
+#define PERI_PC_NR 8u
+/* Master interface presence mask (4 bits) */
+#define PERI_MS_PRESENT 15u
+/* Master interface PPU combinatorial (1) or registerd (0) */
+#define PERI_MS_PPU_COMBINATORIAL 1u
+/* The number of programmable PPU structures for PERI (all peripherals) */
+#define PERI_MS_PPU_PROG_STRUCT_NR 16u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Number of programmable clocks (outputs) */
+#define PERI_CLOCK_NR 59u
+/* Number of 8.0 dividers */
+#define PERI_DIV_8_NR 8u
+/* Number of 16.0 dividers */
+#define PERI_DIV_16_NR 16u
+/* Number of 16.5 (fractional) dividers */
+#define PERI_DIV_16_5_NR 4u
+/* Number of 24.5 (fractional) dividers */
+#define PERI_DIV_24_5_NR 1u
+/* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */
+#define PERI_DIV_ADDR_WIDTH 4u
+/* Trigger module present (0=No, 1=Yes) */
+#define PERI_TR 1u
+/* Number of trigger groups */
+#define PERI_TR_GROUP_NR 15u
+/* The number of protection contexts minus 1 ([1, 15]). */
+#define PERI_PPU_FIXED_STRUCT_PC_NR_MINUS1 7u
+/* The number of protection contexts minus 1 ([1, 15]). */
+#define PERI_PPU_PROG_STRUCT_PC_NR_MINUS1 7u
+/* UDB present or not ('0': no, '1': yes) */
+#define CPUSS_UDB_PRESENT 1u
+/* System RAM 0 size in kilobytes */
+#define CPUSS_SRAM0_SIZE 288u
+/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System
+ SRAM0 is implemented with 8 32KB macros. */
+#define CPUSS_RAMC0_MACRO_NR 9u
+/* System RAM 1 present or not (0=No, 1=Yes) */
+#define CPUSS_RAMC1_PRESENT 0u
+/* System RAM 1 size in kilobytes */
+#define CPUSS_SRAM1_SIZE 32u
+/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System
+ RAM 1 is implemented with 8 32KB macros. */
+#define CPUSS_RAMC1_MACRO_NR 1u
+/* System RAM 2 present or not (0=No, 1=Yes) */
+#define CPUSS_RAMC2_PRESENT 0u
+/* System RAM 2 size in kilobytes */
+#define CPUSS_SRAM2_SIZE 256u
+/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System
+ RAM 2 is implemented with 8 32KB macros. */
+#define CPUSS_RAMC2_MACRO_NR 16u
+/* System ROM size in KB */
+#define CPUSS_ROM_SIZE 128u
+/* Flash main region size in KB */
+#define CPUSS_FLASH_SIZE 1024u
+/* Flash work region size in KB (EEPROM emulation, data) */
+#define CPUSS_WFLASH_SIZE 32u
+/* Flash supervisory region size in KB */
+#define CPUSS_SFLASH_SIZE 32u
+/* Flash data output size (in Bytes) */
+#define CPUSS_FLASHC_WORD_SIZE 16u
+/* Flash row address width */
+#define CPUSS_FLASHC_ROW_ADDR_WIDTH 12u
+/* Flash column address width */
+#define CPUSS_FLASHC_COL_ADDR_WIDTH 5u
+/* Number of external slaves directly connected to slow AHB-Lite infrastructure.
+ Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits.
+ 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave
+ 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK
+ parameters (for the slaves present) should be derived from the Memory Map. */
+#define CPUSS_SLOW_SL_PRESENT 1u
+/* Number of external slaves directly connected to fast AHB-Lite infrastructure.
+ Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits.
+ 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave
+ 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK
+ parameters (for the slaves present) should be derived from the Memory Map. */
+#define CPUSS_FAST_SL_PRESENT 1u
+/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum
+ number of masters supported is 2. Width of this parameter is 2-bits. 1-bit
+ mask for each master indicating present or not. Example: 2'b01 - master 0 is
+ present. */
+#define CPUSS_SLOW_MS_PRESENT 0u
+/* Number of total interrupt request inputs to CPUSS */
+#define CPUSS_IRQ_NR 147u
+/* Number of DeepSleep wakeup interrupt inputs to CPUSS */
+#define CPUSS_DPSLP_IRQ_NR 41u
+/* Number of DeepSleep wakeup interrupt inputs to CM0+ (product configuration) */
+#define CPUSS_CM0_DPSLP_IRQ_NR 8u
+/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8
+ levels of priority 8 = 256 levels of priority */
+#define CPUSS_CM4_LVL_WIDTH 3u
+/* CM4 Floating point unit present or not (0=No, 1=Yes) */
+#define CPUSS_CM4_FPU_PRESENT 1u
+/* Debug level. Legal range [0,3] */
+#define CPUSS_DEBUG_LVL 3u
+/* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3
+ for trace level is not supported in CPUSS. */
+#define CPUSS_TRACE_LVL 2u
+/* Embedded Trace Buffer present or not (0=No, 1=Yes) */
+#define CPUSS_ETB_PRESENT 0u
+/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */
+#define CPUSS_MTB_SRAM_SIZE 4u
+/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */
+#define CPUSS_ETB_SRAM_SIZE 16u
+/* PTM interface present (0=No, 1=Yes) */
+#define CPUSS_PTM_PRESENT 1u
+/* Width of the PTM interface in bits ([2,32]) */
+#define CPUSS_PTM_WIDTH 8u
+/* Width of the TPIU interface in bits ([1,32]) */
+#define CPUSS_TPIU_WIDTH 4u
+/* CoreSight Part Identification Number */
+#define CPUSS_JEPID 52u
+/* CoreSight Part Identification Number */
+#define CPUSS_JEPCONTINUATION 0u
+/* CoreSight Part Identification Number */
+#define CPUSS_FAMILYID 256u
+/* Cryptography IP present or not (0=No, 1=Yes) */
+#define CPUSS_CRYPTO_PRESENT 1u
+/* DataWire 0 present or not (0=No, 1=Yes) */
+#define CPUSS_DW0_PRESENT 1u
+/* Number of DataWire 0 channels (8, 16 or 32) */
+#define CPUSS_DW0_CH_NR 16u
+/* DataWire 1 present or not (0=No, 1=Yes) */
+#define CPUSS_DW1_PRESENT 1u
+/* Number of DataWire 1 channels (8, 16 or 32) */
+#define CPUSS_DW1_CH_NR 16u
+/* Number of Flash BIST_DATA registers */
+#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u
+/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */
+#define CPUSS_FLASHC_PA_SIZE 128u
+/* AES cipher support (0 = no support, 1 = support */
+#define CPUSS_CRYPTO_AES 1u
+/* (Tripple) DES cipher support (0 = no support, 1 = support */
+#define CPUSS_CRYPTO_DES 1u
+/* Pseudo random number generation support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_PR 1u
+/* SHA support included */
+#define CPUSS_CRYPTO_SHA 1u
+/* SHA1 hash support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_SHA1 1u
+/* SHA256 hash support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_SHA256 1u
+/* SHA512 hash support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_SHA512 1u
+/* Cyclic Redundancy Check support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_CRC 1u
+/* Vector unit support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_VU 1u
+/* True random number generation support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_TR 1u
+/* String support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_STR 1u
+/* AHB-Lite master interface support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_MASTER_IF 1u
+/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128,
+ 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8
+ kB and 16 kB memory buffer) */
+#define CPUSS_CRYPTO_BUFF_SIZE 1024u
+/* Number of fault structures. Legal range [1, 4] */
+#define CPUSS_FAULT_FAULT_NR 2u
+/* Number of IPC structures. Legal range [1, 16] */
+#define CPUSS_IPC_IPC_NR 16u
+/* Number of IPC interrupt structures. Legal range [1, 16] */
+#define CPUSS_IPC_IPC_IRQ_NR 16u
+/* Master 0 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u
+/* Master 1 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 7u
+/* Master 2 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u
+/* Master 3 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u
+/* Master 4 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u
+/* Master 5 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u
+/* Master 6 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u
+/* Master 7 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u
+/* Master 8 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u
+/* Master 9 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u
+/* Master 10 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u
+/* Master 11 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u
+/* Master 12 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u
+/* Master 13 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u
+/* Master 14 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u
+/* Master 15 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u
+/* Number of SMPU protection structures */
+#define CPUSS_PROT_SMPU_STRUCT_NR 16u
+/* Number of protection contexts supported minus 1. Legal range [1,16] */
+#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u
+/* Number of DataWire controllers present (max 2) */
+#define CPUSS_DW_NR 2u
+/* Number of channels in each DataWire controller (must be the same for now) */
+#define CPUSS_DW_CH_NR 16u
+/* Number of profiling counters. Legal range [1, 32] */
+#define PROFILE_PRFL_CNT_NR 8u
+/* Number of monitor event signals. Legal range [1, 128] */
+#define PROFILE_PRFL_MONITOR_NR 128u
+/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */
+#define EFUSE_EFUSE_NR 4u
+/* SONOS Flash is used or not ('0': no, '1': yes) */
+#define SFLASH_FLASHC_IS_SONOS 1u
+/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */
+#define SFLASH_CPUSS_WOUNDING_PRESENT 1u
+/* Number of UDB Interrupts */
+#define UDB_NUMINT 16u
+/* Number of triggers */
+#define UDB_NUMTR 16u
+/* Number of UDB array rows (must be multiple of 2) */
+#define UDB_NUMROW 2u
+/* Number of UDB array columns */
+#define UDB_NUMCOL 6u
+/* DSI on bottom (1) or on bottom and top (2) of UDB array */
+#define UDB_DSISIDES 2u
+/* Number of UDBs = NUMROW * NUMCOL */
+#define UDB_NUMUDB 12u
+/* Number of UDB pairs = NUMUDB / 2 */
+#define UDB_NUMUDBPAIR 6u
+/* Number of DSIs = NUMCOL * DSISIDES */
+#define UDB_NUMDSI 12u
+/* Number of quad clocks */
+#define UDB_NUMQCLK 3u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB0_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB0_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB0_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB0_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB0_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB0_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB0_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB0_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB0_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB0_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB0_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB0_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB0_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB0_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB0_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB0_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB0_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB0_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB0_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB0_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB0_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB0_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB0_I2C_FAST_PLUS 1u
+/* Number of used spi_select signals (max 4) */
+#define SCB0_CHIP_TOP_SPI_SEL_NR 3u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB1_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB1_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB1_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB1_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB1_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB1_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB1_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB1_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB1_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB1_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB1_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB1_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB1_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB1_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB1_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB1_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB1_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB1_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB1_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB1_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB1_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB1_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB1_I2C_FAST_PLUS 1u
+/* Number of used spi_select signals (max 4) */
+#define SCB1_CHIP_TOP_SPI_SEL_NR 3u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB2_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB2_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB2_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB2_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB2_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB2_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB2_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB2_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB2_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB2_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB2_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB2_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB2_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB2_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB2_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB2_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB2_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB2_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB2_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB2_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB2_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB2_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB2_I2C_FAST_PLUS 1u
+/* Number of used spi_select signals (max 4) */
+#define SCB2_CHIP_TOP_SPI_SEL_NR 3u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB3_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB3_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB3_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB3_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB3_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB3_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB3_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB3_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB3_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB3_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB3_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB3_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB3_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB3_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB3_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB3_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB3_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB3_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB3_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB3_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB3_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB3_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB3_I2C_FAST_PLUS 1u
+/* Number of used spi_select signals (max 4) */
+#define SCB3_CHIP_TOP_SPI_SEL_NR 3u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB4_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB4_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB4_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB4_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB4_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB4_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB4_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB4_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB4_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB4_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB4_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB4_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB4_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB4_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB4_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB4_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB4_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB4_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB4_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB4_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB4_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB4_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB4_I2C_FAST_PLUS 1u
+/* Number of used spi_select signals (max 4) */
+#define SCB4_CHIP_TOP_SPI_SEL_NR 3u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB5_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB5_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB5_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB5_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB5_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB5_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB5_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB5_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB5_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB5_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB5_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB5_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB5_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB5_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB5_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB5_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB5_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB5_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB5_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB5_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB5_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB5_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB5_I2C_FAST_PLUS 1u
+/* Number of used spi_select signals (max 4) */
+#define SCB5_CHIP_TOP_SPI_SEL_NR 3u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB6_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB6_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB6_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB6_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB6_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB6_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB6_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB6_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB6_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB6_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB6_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB6_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB6_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB6_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB6_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB6_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB6_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB6_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB6_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB6_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB6_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB6_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB6_I2C_FAST_PLUS 1u
+/* Number of used spi_select signals (max 4) */
+#define SCB6_CHIP_TOP_SPI_SEL_NR 3u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB7_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB7_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB7_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB7_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB7_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB7_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB7_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB7_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB7_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB7_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB7_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB7_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB7_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB7_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB7_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB7_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB7_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB7_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB7_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB7_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB7_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB7_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB7_I2C_FAST_PLUS 1u
+/* Number of used spi_select signals (max 4) */
+#define SCB7_CHIP_TOP_SPI_SEL_NR 3u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB8_DEEPSLEEP 1u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB8_EC 1u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB8_I2C_M 0u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB8_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB8_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB8_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB8_I2C_EC 1u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB8_I2C_M_S 0u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB8_I2C_S_EC 1u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB8_SPI_M 0u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB8_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB8_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB8_SPI_EC 1u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB8_SPI_S_EC 1u
+/* UART support? ('0': no, '1': yes) */
+#define SCB8_UART 0u
+/* SPI or UART (SPI | UART) */
+#define SCB8_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB8_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB8_CMD_RESP 1u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB8_EZ 1u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB8_EZ_CMD_RESP 1u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB8_I2C_S_EZ 1u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB8_SPI_S_EZ 1u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB8_I2C_FAST_PLUS 1u
+/* Number of used spi_select signals (max 4) */
+#define SCB8_CHIP_TOP_SPI_SEL_NR 1u
+/* Number of counters per IP (1..8) */
+#define TCPWM0_CNT_NR 8u
+/* Counter width (in number of bits) */
+#define TCPWM0_CNT_CNT_WIDTH 32u
+/* Number of counters per IP (1..8) */
+#define TCPWM1_CNT_NR 24u
+/* Counter width (in number of bits) */
+#define TCPWM1_CNT_CNT_WIDTH 16u
+/* Number of ports supoprting up to 4 COMs */
+#define LCD_NUMPORTS 8u
+/* Number of ports supporting up to 8 COMs */
+#define LCD_NUMPORTS8 8u
+/* Number of ports supporting up to 16 COMs */
+#define LCD_NUMPORTS16 0u
+/* Max number of LCD commons supported */
+#define LCD_CHIP_TOP_COM_NR 8u
+/* Max number of LCD pins (total) supported */
+#define LCD_CHIP_TOP_PIN_NR 62u
+/* Number of IREF outputs from AREF */
+#define PASS_NR_IREFS 4u
+/* Number of CTBs in the Subsystem */
+#define PASS_NR_CTBS 1u
+/* Number of CTDACs in the Subsystem */
+#define PASS_NR_CTDACS 1u
+/* CTB0 Exists */
+#define PASS_CTB0_EXISTS 1u
+/* CTB1 Exists */
+#define PASS_CTB1_EXISTS 0u
+/* CTB2 Exists */
+#define PASS_CTB2_EXISTS 0u
+/* CTB3 Exists */
+#define PASS_CTB3_EXISTS 0u
+/* CTDAC0 Exists */
+#define PASS_CTDAC0_EXISTS 1u
+/* CTDAC1 Exists */
+#define PASS_CTDAC1_EXISTS 0u
+/* CTDAC2 Exists */
+#define PASS_CTDAC2_EXISTS 0u
+/* CTDAC3 Exists */
+#define PASS_CTDAC3_EXISTS 0u
+/* Number of SAR channels */
+#define PASS_SAR_SAR_CHANNELS 16u
+/* Averaging logic present in SAR */
+#define PASS_SAR_SAR_AVERAGE 1u
+/* Range detect logic present in SAR */
+#define PASS_SAR_SAR_RANGEDET 1u
+/* Support for UAB sampling */
+#define PASS_SAR_SAR_UAB 0u
+#define PASS_CTBM_CTDAC_PRESENT 1u
+/* Number of AHB-Lite "hmaster[]" bits ([1, 8]) */
+#define SMIF_MASTER_WIDTH 8u
+/* Base address of the SMIF XIP memory region. This address must be a multiple of
+ the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This
+ address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP
+ memory region should NOT overlap with other memory regions. */
+#define SMIF_SMIF_XIP_ADDR 402653184u
+/* Capacity of the SMIF XIP memory region. The more significant bits of this
+ parameter must be '1' and the lesser significant bits of this paramter must
+ be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are
+ {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000,
+ 0xffe0:0000, ..., 0xe000:0000}. */
+#define SMIF_SMIF_XIP_MASK 4160749568u
+/* Cryptography (AES) support ('0' = no support, '1' = support) */
+#define SMIF_CRYPTO 1u
+/* Number of external devices supported ([1,4]) */
+#define SMIF_DEVICE_NR 4u
+/* External device write support. This is a 4-bit field. Each external device has
+ a dedicated bit. E.g., if bit 2 is '1', external device 2 has write support. */
+#define SMIF_DEVICE_WR_EN 15u
+/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data
+ pins) */
+#define SMIF_CHIP_TOP_DATA8_PRESENT 1u
+/* Number of used spi_select signals (max 4) */
+#define SMIF_CHIP_TOP_SPI_SEL_NR 4u
+/* I2S capable? (0=No,1=Yes) */
+#define AUDIOSS_I2S 1u
+/* PDM capable? (0=No,1=Yes) */
+#define AUDIOSS_PDM 1u
+
+/* MMIO Targets Defines */
+#define CY_MMIO_CRYPTO_GROUP_NR 1u
+#define CY_MMIO_CRYPTO_SLAVE_NR 1u
+#define CY_MMIO_CPUSS_GROUP_NR 2u
+#define CY_MMIO_CPUSS_SLAVE_NR 1u
+#define CY_MMIO_FAULT_GROUP_NR 2u
+#define CY_MMIO_FAULT_SLAVE_NR 2u
+#define CY_MMIO_IPC_GROUP_NR 2u
+#define CY_MMIO_IPC_SLAVE_NR 3u
+#define CY_MMIO_PROT_GROUP_NR 2u
+#define CY_MMIO_PROT_SLAVE_NR 4u
+#define CY_MMIO_FLASHC_GROUP_NR 2u
+#define CY_MMIO_FLASHC_SLAVE_NR 5u
+#define CY_MMIO_SRSS_GROUP_NR 2u
+#define CY_MMIO_SRSS_SLAVE_NR 6u
+#define CY_MMIO_BACKUP_GROUP_NR 2u
+#define CY_MMIO_BACKUP_SLAVE_NR 7u
+#define CY_MMIO_DW_GROUP_NR 2u
+#define CY_MMIO_DW_SLAVE_NR 8u
+#define CY_MMIO_EFUSE_GROUP_NR 2u
+#define CY_MMIO_EFUSE_SLAVE_NR 12u
+#define CY_MMIO_PROFILE_GROUP_NR 2u
+#define CY_MMIO_PROFILE_SLAVE_NR 13u
+#define CY_MMIO_HSIOM_GROUP_NR 3u
+#define CY_MMIO_HSIOM_SLAVE_NR 1u
+#define CY_MMIO_GPIO_GROUP_NR 3u
+#define CY_MMIO_GPIO_SLAVE_NR 2u
+#define CY_MMIO_SMARTIO_GROUP_NR 3u
+#define CY_MMIO_SMARTIO_SLAVE_NR 3u
+#define CY_MMIO_UDB_GROUP_NR 3u
+#define CY_MMIO_UDB_SLAVE_NR 4u
+#define CY_MMIO_LPCOMP_GROUP_NR 3u
+#define CY_MMIO_LPCOMP_SLAVE_NR 5u
+#define CY_MMIO_CSD0_GROUP_NR 3u
+#define CY_MMIO_CSD0_SLAVE_NR 6u
+#define CY_MMIO_TCPWM0_GROUP_NR 3u
+#define CY_MMIO_TCPWM0_SLAVE_NR 8u
+#define CY_MMIO_TCPWM1_GROUP_NR 3u
+#define CY_MMIO_TCPWM1_SLAVE_NR 9u
+#define CY_MMIO_LCD0_GROUP_NR 3u
+#define CY_MMIO_LCD0_SLAVE_NR 10u
+#define CY_MMIO_BLE_GROUP_NR 3u
+#define CY_MMIO_BLE_SLAVE_NR 11u
+#define CY_MMIO_USBFS0_GROUP_NR 3u
+#define CY_MMIO_USBFS0_SLAVE_NR 12u
+#define CY_MMIO_SMIF0_GROUP_NR 4u
+#define CY_MMIO_SMIF0_SLAVE_NR 2u
+#define CY_MMIO_SCB0_GROUP_NR 6u
+#define CY_MMIO_SCB0_SLAVE_NR 1u
+#define CY_MMIO_SCB1_GROUP_NR 6u
+#define CY_MMIO_SCB1_SLAVE_NR 2u
+#define CY_MMIO_SCB2_GROUP_NR 6u
+#define CY_MMIO_SCB2_SLAVE_NR 3u
+#define CY_MMIO_SCB3_GROUP_NR 6u
+#define CY_MMIO_SCB3_SLAVE_NR 4u
+#define CY_MMIO_SCB4_GROUP_NR 6u
+#define CY_MMIO_SCB4_SLAVE_NR 5u
+#define CY_MMIO_SCB5_GROUP_NR 6u
+#define CY_MMIO_SCB5_SLAVE_NR 6u
+#define CY_MMIO_SCB6_GROUP_NR 6u
+#define CY_MMIO_SCB6_SLAVE_NR 7u
+#define CY_MMIO_SCB7_GROUP_NR 6u
+#define CY_MMIO_SCB7_SLAVE_NR 8u
+#define CY_MMIO_SCB8_GROUP_NR 6u
+#define CY_MMIO_SCB8_SLAVE_NR 9u
+#define CY_MMIO_PASS_GROUP_NR 9u
+#define CY_MMIO_PASS_SLAVE_NR 1u
+#define CY_MMIO_I2S0_GROUP_NR 10u
+#define CY_MMIO_I2S0_SLAVE_NR 1u
+#define CY_MMIO_PDM0_GROUP_NR 10u
+#define CY_MMIO_PDM0_SLAVE_NR 2u
+
+/* Backward compatibility definitions */
+#define CPUSS_SYSTEM_INT_NR CPUSS_IRQ_NR
+#define CPUSS_SYSTEM_DPSLP_INT_NR CPUSS_DPSLP_IRQ_NR
+
+#endif /* _PSOC6_01_CONFIG_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Include/system_psoc6.h b/platform/ext/target/psoc64/Device/Include/system_psoc6.h
new file mode 100644
index 0000000000..d95d171ee5
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Include/system_psoc6.h
@@ -0,0 +1,665 @@
+/***************************************************************************//**
+* \file system_psoc6.h
+* \version 2.30
+*
+* \brief Device system header file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+
+#ifndef _SYSTEM_PSOC6_H_
+#define _SYSTEM_PSOC6_H_
+
+/**
+* \addtogroup group_system_config
+* \{
+* Provides device startup, system configuration, and linker script files.
+* The system startup provides the followings features:
+* - See \ref group_system_config_device_initialization for the:
+* * \ref group_system_config_dual_core_device_initialization
+* * \ref group_system_config_single_core_device_initialization
+* - \ref group_system_config_device_memory_definition
+* - \ref group_system_config_heap_stack_config
+* - \ref group_system_config_merge_apps
+* - \ref group_system_config_default_handlers
+* - \ref group_system_config_device_vector_table
+* - \ref group_system_config_cm4_functions
+*
+* \section group_system_config_configuration Configuration Considerations
+*
+* \subsection group_system_config_device_memory_definition Device Memory Definition
+* The flash and RAM allocation for each CPU is defined by the linker scripts.
+* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores.
+* 2 KB of RAM (allocated at the end of RAM) are reserved for system use.
+* For Single-Core devices the system reserves additional 80 bytes of RAM.
+* Using the reserved memory area for other purposes will lead to unexpected behavior.
+*
+* \note The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see warnings during the build process. To eliminate build
+* warnings in your project, you can simply comment out or remove the relevant
+* code in the linker file.
+*
+* <b>ARM GCC</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
+* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
+* \note If the start of the Cortex-M4 application image is changed, the value
+* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
+* Cy_SysEnableCM4() function call.
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_cm0plus.ld', where 'xx' is the device group:
+* \code
+* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
+* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
+* \endcode
+* - 'xx_cm4_dual.ld', where 'xx' is the device group:
+* \code
+* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
+* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
+* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
+* by either:
+* - Passing the following commands to the compiler:\n
+* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
+* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
+*
+* <b>ARM MDK</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
+* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
+* \note If the start of the Cortex-M4 application image is changed, the value
+* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
+* Cy_SysEnableCM4() function call.
+*
+* \note The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see the warnings during the build process:
+* L6314W (no section matches pattern) and/or L6329W
+* (pattern only matches removed unused sections). In your project, you can
+* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+* the linker. You can also comment out or remove the relevant code in the linker
+* file.
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_cm0plus.scat', where 'xx' is the device group:
+* \code
+* #define FLASH_START 0x10000000
+* #define FLASH_SIZE 0x00080000
+* #define RAM_START 0x08000000
+* #define RAM_SIZE 0x00024000
+* \endcode
+* - 'xx_cm4_dual.scat', where 'xx' is the device group:
+* \code
+* #define FLASH_START 0x10080000
+* #define FLASH_SIZE 0x00080000
+* #define RAM_START 0x08024000
+* #define RAM_SIZE 0x00023800
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
+* value in the 'xx_cm4_dual.scat' file,
+* where 'xx' is the device group. Do this by either:
+* - Passing the following commands to the compiler:\n
+* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
+* 'xx' is device family:\n
+* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
+*
+* <b>IAR</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example,
+* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
+* \note If the start of the Cortex-M4 application image is changed, the value
+* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
+* Cy_SysEnableCM4() function call.
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_cm0plus.icf', where 'xx' is the device group:
+* \code
+* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
+* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
+* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
+* \endcode
+* - 'xx_cm4_dual.icf', where 'xx' is the device group:
+* \code
+* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
+* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
+* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
+* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
+* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
+* is the device group. Do this by either:
+* - Passing the following commands to the compiler:\n
+* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
+* 'xx' is device family:\n
+* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
+*
+* \subsection group_system_config_device_initialization Device Initialization
+* After a power-on-reset (POR), the boot process is handled by the boot code
+* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot
+* code passes the control to the Cortex-M0+ startup code located in flash.
+*
+* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices
+* The Cortex-M0+ startup code performs the device initialization by a call to
+* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled
+* by default. Enable the core using the \ref Cy_SysEnableCM4() function.
+* See \ref group_system_config_cm4_functions for more details.
+* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores.
+* The function has a separate implementation on each core.
+* Both function implementations unlock and disable the WDT.
+* Therefore enable the WDT after both cores have been initialized.
+*
+* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices
+* The Cortex-M0+ core is not user-accessible on these devices. In this case the
+* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
+*
+* \subsection group_system_config_heap_stack_config Heap and Stack Configuration
+* There are two ways to adjust heap and stack configurations:
+* -# Editing source code files
+* -# Specifying via command line
+*
+* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.
+*
+* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
+* - <b>Editing source code files</b>\n
+* The heap and stack sizes are defined in the assembler startup files
+* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
+* Change the heap and stack sizes by modifying the following lines:\n
+* \code .equ Stack_Size, 0x00001000 \endcode
+* \code .equ Heap_Size, 0x00000400 \endcode
+*
+* - <b>Specifying via command line</b>\n
+* Change the heap and stack sizes passing the following commands to the compiler:\n
+* \code -D __STACK_SIZE=0x000000400 \endcode
+* \code -D __HEAP_SIZE=0x000000100 \endcode
+*
+* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
+* - <b>Editing source code files</b>\n
+* The heap and stack sizes are defined in the assembler startup files
+* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
+* Change the heap and stack sizes by modifying the following lines:\n
+* \code Stack_Size EQU 0x00001000 \endcode
+* \code Heap_Size EQU 0x00000400 \endcode
+*
+* - <b>Specifying via command line</b>\n
+* Change the heap and stack sizes passing the following commands to the assembler:\n
+* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
+* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
+*
+* \subsubsection group_system_config_heap_stack_config_iar IAR
+* - <b>Editing source code files</b>\n
+* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
+* where 'xx' is the device family, and 'yy' is the target CPU; for example,
+* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
+* Change the heap and stack sizes by modifying the following lines:\n
+* \code Stack_Size EQU 0x00001000 \endcode
+* \code Heap_Size EQU 0x00000400 \endcode
+*
+* - <b>Specifying via command line</b>\n
+* Change the heap and stack sizes passing the following commands to the
+* linker (including quotation marks):\n
+* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
+* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
+*
+* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
+* The CM0+ project and linker script build the CM0+ application image. Similarly,
+* the CM4 linker script builds the CM4 application image. Each specifies
+* locations, sizes, and contents of sections in memory. See
+* \ref group_system_config_device_memory_definition for the symbols and default
+* values.
+*
+* The cymcuelftool is invoked by a post-build command. The precise project
+* setting is IDE-specific.
+*
+* The cymcuelftool combines the two executables. The tool examines the
+* executables to ensure that memory regions either do not overlap, or contain
+* identical bytes (shared). If there are no problems, it creates a new ELF file
+* with the merged image, without changing any of the addresses or data.
+*
+* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
+* The default interrupt handler functions are defined as weak functions to a dummy
+* handler in the startup file. The naming convention for the interrupt handler names
+* is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
+* user code by defining the handler function using the same name. For example:
+* \code
+* void scb_0_interrupt_IRQHandler(void)
+*{
+* ...
+*}
+* \endcode
+*
+* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM
+* This process uses memory sections defined in the linker script. The startup
+* code actually defines the contents of the vector table and performs the copy.
+* \subsubsection group_system_config_device_vector_table_gcc ARM GCC
+* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and
+* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
+* It defines sections and locations in memory.\n
+* Copy interrupt vectors from flash to RAM: \n
+* From: \code LONG (__Vectors) \endcode
+* To: \code LONG (__ram_vectors_start__) \endcode
+* Size: \code LONG (__Vectors_End - __Vectors) \endcode
+* The vector table address (and the vector table itself) are defined in the
+* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
+* The code in these files copies the vector table from Flash to RAM.
+* \subsubsection group_system_config_device_vector_table_mdk ARM MDK
+* The linker script file is 'xx_yy.scat', where 'xx' is the device family,
+* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
+* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
+* (RESET_RAM) shall be first in the RAM section.\n
+* RESET_RAM represents the vector table. It is defined in the assembler startup
+* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
+* The code in these files copies the vector table from Flash to RAM.
+*
+* \subsubsection group_system_config_device_vector_table_iar IAR
+* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and
+* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
+* This file defines the .intvec_ram section and its location.
+* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode
+* The vector table address (and the vector table itself) are defined in the
+* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
+* The code in these files copies the vector table from Flash to RAM.
+*
+* \section group_system_config_more_information More Information
+* Refer to the <a href="..\..\pdl_user_guide.pdf">PDL User Guide</a> for the
+* more details.
+*
+* \section group_system_config_MISRA MISRA Compliance
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>2.3</td>
+* <td>R</td>
+* <td>The character sequence // shall not be used within a comment.</td>
+* <td>The comments provide a useful WEB link to the documentation.</td>
+* </tr>
+* </table>
+*
+* \section group_system_config_changelog Changelog
+* <table class="doxtable">
+* <tr>
+* <th>Version</th>
+* <th>Changes</th>
+* <th>Reason for Change</th>
+* </tr>
+* <tr>
+* <td rowspan="2">2.30</td>
+* <td>Added assembler files, linker skripts for Mbed OS.</td>
+* <td>Added Arm Mbed OS embedded operating system support.</td>
+* </tr>
+* <tr>
+* <td>Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.</td>
+* <td>Enhanced PDL usability.</td>
+* </tr>
+* <tr>
+* <td>2.20</td>
+* <td>Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.</td>
+* <td>Changed the IPC driver configuration method from compile time to run time.</td>
+* </tr>
+* <tr>
+* <td rowspan="2"> 2.10</td>
+* <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n
+* Removed $Sub$$main symbol for ARM MDK compiler.
+* </td>
+* <td>uVision Debugger support.</td>
+* </tr>
+* <tr>
+* <td>Updated description of the Startup behavior for Single-Core Devices. \n
+* Added note about WDT disabling by SystemInit() function.
+* </td>
+* <td>Documentation improvement.</td>
+* </tr>
+* <tr>
+* <td rowspan="4"> 2.0</td>
+* <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices.
+* Single core device support.
+* </td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n
+* Renamed 'wflash' memory region to 'em_eeprom'.
+* </td>
+* <td>Linker scripts usability improvement.</td>
+* </tr>
+* <tr>
+* <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td>
+* <td>Reserved system resources for internal operations.</td>
+* </tr>
+* <tr>
+* <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td>
+* <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+*
+* \defgroup group_system_config_macro Macro
+* \{
+* \defgroup group_system_config_system_macro System
+* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status
+* \defgroup group_system_config_user_settings_macro User Settings
+* \}
+* \defgroup group_system_config_functions Functions
+* \{
+* \defgroup group_system_config_system_functions System
+* \defgroup group_system_config_cm4_functions Cortex-M4 Control
+* \}
+* \defgroup group_system_config_globals Global Variables
+*
+* \}
+*/
+
+/**
+* \addtogroup group_system_config_system_functions
+* \{
+* \details
+* The following system functions implement CMSIS Core functions.
+* Refer to the [CMSIS documentation]
+* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
+* for more details.
+* \}
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Include files
+*******************************************************************************/
+#include <stdint.h>
+
+
+/*******************************************************************************
+* Global preprocessor symbols/macros ('define')
+*******************************************************************************/
+#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+ (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__ARMCC_VERSION) && ((__TARGET_ARCH_THUMB == 3) || (__ARM_ARCH_6M__ == 1))))
+ #define CY_SYSTEM_CPU_CM0P 1UL
+#else
+ #define CY_SYSTEM_CPU_CM0P 0UL
+#endif
+
+#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
+ #include "cyfitter.h"
+#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
+
+
+
+
+/*******************************************************************************
+*
+* START OF USER SETTINGS HERE
+* ===========================
+*
+* All lines with '<<<' can be set by user.
+*
+*******************************************************************************/
+
+/**
+* \addtogroup group_system_config_user_settings_macro
+* \{
+*/
+
+#if defined (CYDEV_CLK_EXTCLK__HZ)
+ #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
+#else
+ /***************************************************************************//**
+ * External Clock Frequency (in Hz, [value]UL). If compiled within
+ * PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
+ * Otherwise, edit the value below.
+ * <i>(USER SETTING)</i>
+ *******************************************************************************/
+ #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
+#endif /* (CYDEV_CLK_EXTCLK__HZ) */
+
+
+#if defined (CYDEV_CLK_ECO__HZ)
+ #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
+#else
+ /***************************************************************************//**
+ * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
+ * within PSoC Creator and the clock is enabled in the DWR, the value from DWR
+ * used.
+ * <i>(USER SETTING)</i>
+ *******************************************************************************/
+ #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
+#endif /* (CYDEV_CLK_ECO__HZ) */
+
+
+#if defined (CYDEV_CLK_ALTHF__HZ)
+ #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
+#else
+ /***************************************************************************//**
+ * \brief Alternate high frequency (in Hz, [value]UL). If compiled within
+ * PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
+ * Otherwise, edit the value below.
+ * <i>(USER SETTING)</i>
+ *******************************************************************************/
+ #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
+#endif /* (CYDEV_CLK_ALTHF__HZ) */
+
+
+/***************************************************************************//**
+* \brief Start address of the Cortex-M4 application ([address]UL)
+* <i>(USER SETTING)</i>
+*******************************************************************************/
+#if !defined (CY_CORTEX_M4_APPL_ADDR)
+ #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */
+#endif /* (CY_CORTEX_M4_APPL_ADDR) */
+
+
+/***************************************************************************//**
+* \brief IPC Semaphores allocation ([value]UL).
+* <i>(USER SETTING)</i>
+*******************************************************************************/
+#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */
+
+
+/***************************************************************************//**
+* \brief IPC Pipe definitions ([value]UL).
+* <i>(USER SETTING)</i>
+*******************************************************************************/
+#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */
+
+
+/*******************************************************************************
+*
+* END OF USER SETTINGS HERE
+* =========================
+*
+*******************************************************************************/
+
+/** \} group_system_config_user_settings_macro */
+
+
+/**
+* \addtogroup group_system_config_system_macro
+* \{
+*/
+
+#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
+ /** The Cortex-M0+ startup driver identifier */
+ #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U))
+#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
+
+#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN)
+ /** The Cortex-M4 startup driver identifier */
+ #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U))
+#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */
+
+/** \} group_system_config_system_macro */
+
+
+/**
+* \addtogroup group_system_config_system_functions
+* \{
+*/
+extern void SystemInit(void);
+
+extern void SystemCoreClockUpdate(void);
+/** \} group_system_config_system_functions */
+
+
+/**
+* \addtogroup group_system_config_cm4_functions
+* \{
+*/
+extern uint32_t Cy_SysGetCM4Status(void);
+extern void Cy_SysEnableCM4(uint32_t vectorTableOffset);
+extern void Cy_SysDisableCM4(void);
+extern void Cy_SysRetainCM4(void);
+extern void Cy_SysResetCM4(void);
+/** \} group_system_config_cm4_functions */
+
+
+/** \cond */
+extern void Default_Handler (void);
+
+void Cy_SysIpcPipeIsrCm0(void);
+void Cy_SysIpcPipeIsrCm4(void);
+
+extern void Cy_SystemInit(void);
+extern void Cy_SystemInitFpuEnable(void);
+
+extern uint32_t cy_delayFreqHz;
+extern uint32_t cy_delayFreqKhz;
+extern uint8_t cy_delayFreqMhz;
+extern uint32_t cy_delay32kMs;
+/** \endcond */
+
+
+#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
+/**
+* \addtogroup group_system_config_cm4_status_macro
+* \{
+*/
+#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */
+#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */
+#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */
+#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */
+/** \} group_system_config_cm4_status_macro */
+
+#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
+
+
+/*******************************************************************************
+* IPC Configuration
+* =========================
+*******************************************************************************/
+/* IPC CY_PIPE default configuration */
+#define CY_SYS_CYPIPE_CLIENT_CNT (8UL)
+
+#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */
+#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */
+#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */
+
+#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0)
+#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1)
+
+
+/******************************************************************************/
+/*
+ * The System pipe configuration defines the IPC channel number, interrupt
+ * number, and the pipe interrupt mask for the endpoint.
+ *
+ * The format of the endPoint configuration
+ * Bits[31:16] Interrupt Mask
+ * Bits[15:8 ] IPC interrupt
+ * Bits[ 7:0 ] IPC channel
+ */
+
+/* System Pipe addresses */
+/* CyPipe defines */
+
+#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
+
+#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
+ | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
+ | CY_IPC_CHAN_CYPIPE_EP0)
+#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
+ | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
+ | CY_IPC_CHAN_CYPIPE_EP1)
+
+/******************************************************************************/
+
+
+/** \addtogroup group_system_config_globals
+* \{
+*/
+
+extern uint32_t SystemCoreClock;
+extern uint32_t cy_BleEcoClockFreqHz;
+extern uint32_t cy_Hfclk0FreqHz;
+extern uint32_t cy_PeriClkFreqHz;
+
+/** \} group_system_config_globals */
+
+
+
+/** \cond INTERNAL */
+/*******************************************************************************
+* Backward compatibility macro. The following code is DEPRECATED and must
+* not be used in new projects
+*******************************************************************************/
+
+/* BWC defines for functions related to enter/exit critical section */
+#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection
+#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
+#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
+#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
+
+/** \endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_PSOC6_H_ */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Source/armclang/cy_syslib_mdk.s b/platform/ext/target/psoc64/Device/Source/armclang/cy_syslib_mdk.s
new file mode 100644
index 0000000000..50483219a2
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/armclang/cy_syslib_mdk.s
@@ -0,0 +1,109 @@
+;-------------------------------------------------------------------------------
+; \file cy_syslib_mdk.s
+; \version 2.20
+;
+; \brief Assembly routines for ARMCC.
+;
+;-------------------------------------------------------------------------------
+; Copyright 2016-2019 Cypress Semiconductor Corporation
+; SPDX-License-Identifier: Apache-2.0
+;
+; Licensed under the Apache License, Version 2.0 (the "License");
+; you may not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+; http://www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;-------------------------------------------------------------------------------
+
+ AREA |.text|,CODE,ALIGN=3
+ THUMB
+ EXTERN Reset
+
+;-------------------------------------------------------------------------------
+; Function Name: Cy_SysLib_DelayCycles
+;-------------------------------------------------------------------------------
+;
+; Summary:
+; Delays for the specified number of cycles.
+;
+; Parameters:
+; uint32_t cycles: The number of cycles to delay.
+;
+;-------------------------------------------------------------------------------
+; void Cy_SysLib_DelayCycles(uint32_t cycles)
+ ALIGN 8
+Cy_SysLib_DelayCycles FUNCTION
+ EXPORT Cy_SysLib_DelayCycles
+ ; cycles bytes
+ ADDS r0, r0, #2 ; 1 2 Round to the nearest multiple of 4.
+ LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags.
+ BEQ Cy_DelayCycles_done ; 2 2 Skip if 0.
+Cy_DelayCycles_loop
+ ADDS r0, r0, #1 ; 1 2 Increment the counter.
+ SUBS r0, r0, #2 ; 1 2 Decrement the counter by 2.
+ BNE Cy_DelayCycles_loop ; (1)2 2 2 CPU cycles (if branch is taken).
+ NOP ; 1 2 Loop alignment padding.
+Cy_DelayCycles_done
+ BX lr ; 3 2
+ ENDFUNC
+
+
+;-------------------------------------------------------------------------------
+; Function Name: Cy_SysLib_EnterCriticalSection
+;-------------------------------------------------------------------------------
+;
+; Summary:
+; Cy_SysLib_EnterCriticalSection disables interrupts and returns a value
+; indicating whether interrupts were previously enabled.
+;
+; Note Implementation of Cy_SysLib_EnterCriticalSection manipulates the IRQ
+; enable bit with interrupts still enabled. The test and set of the interrupt
+; bits are not atomic. Therefore, to avoid a corrupting processor state, it must
+; be the policy that all interrupt routines restore the interrupt enable bits as
+; they were found on entry.
+;
+; Return:
+; uint8_t
+; Returns 0 if interrupts were previously enabled or 1 if interrupts
+; were previously disabled.
+;
+;-------------------------------------------------------------------------------
+; uint8_t Cy_SysLib_EnterCriticalSection(void)
+Cy_SysLib_EnterCriticalSection FUNCTION
+ EXPORT Cy_SysLib_EnterCriticalSection
+ MRS r0, PRIMASK ; Save and return an interrupt state.
+ CPSID I ; Disable the interrupts.
+ BX lr
+ ENDFUNC
+
+;-------------------------------------------------------------------------------
+; Function Name: Cy_SysLib_ExitCriticalSection
+;-------------------------------------------------------------------------------
+;
+; Summary:
+; Cy_SysLib_ExitCriticalSection re-enables interrupts if they were enabled
+; before Cy_SysLib_EnterCriticalSection was called. The argument should be the
+; value returned from Cy_SysLib_EnterCriticalSection.
+;
+; Parameters:
+; uint8_t savedIntrStatus:
+; The saved interrupt status returned by the Cy_SysLib_EnterCriticalSection
+; function.
+;
+;-------------------------------------------------------------------------------
+; void Cy_SysLib_ExitCriticalSection(uint8_t savedIntrStatus)
+Cy_SysLib_ExitCriticalSection FUNCTION
+ EXPORT Cy_SysLib_ExitCriticalSection
+ MSR PRIMASK, r0 ; Restore the interrupt state.
+ BX lr
+ ENDFUNC
+
+ END
+
+; [] END OF FILE
diff --git a/platform/ext/target/psoc64/Device/Source/armclang/psoc6_bl2.sct b/platform/ext/target/psoc64/Device/Source/armclang/psoc6_bl2.sct
new file mode 100644
index 0000000000..baaf0ed9cd
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/armclang/psoc6_bl2.sct
@@ -0,0 +1,49 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "region_defs.h"
+
+LR_CODE BL2_CODE_START {
+ ER_CODE BL2_CODE_START {
+ startup_psoc6_bl2.o (RESET +First)
+ startup_psoc6_bl2.o (+RO)
+ system_psoc6_cm0plus.o (+RO) ; SystemInit
+ *(InRoot$$Sections) ; ARM library sections
+ .ANY (+RO) ; app code that gets copied from Flash to SRAM
+ }
+
+
+ TFM_SHARED_DATA BL2_DATA_START ALIGN 32 EMPTY BOOT_TFM_SHARED_DATA_SIZE {
+ }
+
+ ER_DATA +0 BL2_DATA_SIZE {
+ .ANY (+ZI +RW)
+ }
+
+ /* MSP */
+ ARM_LIB_STACK +0 ALIGN 32 EMPTY BL2_MSP_STACK_SIZE {
+ }
+
+ ARM_LIB_HEAP +0 ALIGN 8 EMPTY BL2_HEAP_SIZE {
+ }
+
+ /* Executable code allocated in RAM */
+ TFM_RAM_CODE +0 ALIGN 32 {
+ * (.ramfunc)
+ }
+}
diff --git a/platform/ext/target/psoc64/Device/Source/armclang/psoc6_ns.sct b/platform/ext/target/psoc64/Device/Source/armclang/psoc6_ns.sct
new file mode 100644
index 0000000000..c9c71d6c8d
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/armclang/psoc6_ns.sct
@@ -0,0 +1,53 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "region_defs.h"
+
+LR_CODE NS_CODE_START {
+ ER_CODE NS_CODE_START NS_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+ ER_DATA NS_DATA_START NS_DATA_SIZE {
+ .ANY (+ZI +RW)
+ }
+
+ /* MSP */
+ ARM_LIB_STACK_MSP +0 ALIGN 32 EMPTY NS_MSP_STACK_SIZE {
+ }
+
+ /* PSP */
+ ARM_LIB_STACK +0 ALIGN 32 EMPTY NS_PSP_STACK_SIZE {
+ }
+
+ ARM_LIB_HEAP +0 ALIGN 8 EMPTY NS_HEAP_SIZE {
+ }
+
+ /* Executable code allocated in RAM */
+ TFM_RAM_CODE +0 ALIGN 32 {
+ * (.ramfunc)
+ }
+
+#if defined (NS_DATA_SHARED_START)
+ /* Shared memory data */
+ TFM_SHARED_MEM NS_DATA_SHARED_START EMPTY NS_DATA_SHARED_SIZE {
+ }
+#endif
+}
+
diff --git a/platform/ext/target/psoc64/Device/Source/armclang/startup_psoc6_bl2.s b/platform/ext/target/psoc64/Device/Source/armclang/startup_psoc6_bl2.s
new file mode 100644
index 0000000000..e7e8bffbb5
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/armclang/startup_psoc6_bl2.s
@@ -0,0 +1,169 @@
+;/*
+; * Copyright (c) 2017-2018 ARM Limited
+; * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
+; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+; Address of the NMI handler in ROM
+CY_NMI_HANLDER_ADDR EQU 0x0000000D
+
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+ EXPORT __ramVectors
+
+ IMPORT Cy_SysIpcPipeIsrCm0
+
+__Vectors ;Core Interrupts
+ DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD CY_NMI_HANLDER_ADDR ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External interrupts Description
+ DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0
+ DCD Cy_SysIpcPipeIsrCm0
+ DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2
+ DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3
+ DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4
+ DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5
+ DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6
+ DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7
+ DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8
+ DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9
+ DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10
+ DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11
+ DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12
+ DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13
+ DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14
+ DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15
+ DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16
+ DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17
+ DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18
+ DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19
+ DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20
+ DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21
+ DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22
+ DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23
+ DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24
+ DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25
+ DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26
+ DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27
+ DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28
+ DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29
+ DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30
+ DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA RESET_RAM, READWRITE, NOINIT
+__ramVectors
+ SPACE __Vectors_Size
+
+
+; Reset Handler
+ AREA |.text|, CODE, READONLY
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+End_Of_Main
+ B .
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+ MACRO
+ Default_Handler $handler_name
+$handler_name PROC
+ EXPORT $handler_name [WEAK]
+ B .
+ ENDP
+ MEND
+
+ Default_Handler HardFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+ Default_Handler NvicMux0_IRQHandler
+ Default_Handler NvicMux2_IRQHandler
+ Default_Handler NvicMux3_IRQHandler
+ Default_Handler NvicMux4_IRQHandler
+ Default_Handler NvicMux5_IRQHandler
+ Default_Handler NvicMux6_IRQHandler
+ Default_Handler NvicMux7_IRQHandler
+ Default_Handler NvicMux8_IRQHandler
+ Default_Handler NvicMux9_IRQHandler
+ Default_Handler NvicMux10_IRQHandler
+ Default_Handler NvicMux11_IRQHandler
+ Default_Handler NvicMux12_IRQHandler
+ Default_Handler NvicMux13_IRQHandler
+ Default_Handler NvicMux14_IRQHandler
+ Default_Handler NvicMux15_IRQHandler
+ Default_Handler NvicMux16_IRQHandler
+ Default_Handler NvicMux17_IRQHandler
+ Default_Handler NvicMux18_IRQHandler
+ Default_Handler NvicMux19_IRQHandler
+ Default_Handler NvicMux20_IRQHandler
+ Default_Handler NvicMux21_IRQHandler
+ Default_Handler NvicMux22_IRQHandler
+ Default_Handler NvicMux23_IRQHandler
+ Default_Handler NvicMux24_IRQHandler
+ Default_Handler NvicMux25_IRQHandler
+ Default_Handler NvicMux26_IRQHandler
+ Default_Handler NvicMux27_IRQHandler
+ Default_Handler NvicMux28_IRQHandler
+ Default_Handler NvicMux29_IRQHandler
+ Default_Handler NvicMux30_IRQHandler
+ Default_Handler NvicMux31_IRQHandler
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/psoc64/Device/Source/armclang/startup_psoc6_ns.s b/platform/ext/target/psoc64/Device/Source/armclang/startup_psoc6_ns.s
new file mode 100644
index 0000000000..623655c6a0
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/armclang/startup_psoc6_ns.s
@@ -0,0 +1,643 @@
+;/*
+; * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+; * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of mbed-os startup_psoc6_01_cm4.S
+; TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/
+; Git SHA: 101ae73b87e7082502915c5a4c6f3971fac270bb
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+ EXPORT __ramVectors
+ IMPORT Cy_SysIpcPipeIsrCm4
+ IMPORT Cy_Flash_ResumeIrqHandler
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External interrupts Description
+ DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0
+ DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1
+ DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2
+ DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3
+ DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4
+ DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5
+ DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6
+ DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7
+ DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8
+ DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9
+ DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10
+ DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11
+ DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12
+ DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13
+ DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14
+ DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports
+ DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt
+ DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt
+ DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable)
+ DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
+ DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
+ DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
+ DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)
+ DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms)
+ DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt
+ DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0
+ DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1
+ DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2
+ DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3
+ DCD Cy_SysIpcPipeIsrCm4
+ DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5
+ DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6
+ DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7
+ DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8
+ DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9
+ DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10
+ DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11
+ DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12
+ DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13
+ DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14
+ DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15
+ DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0
+ DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1
+ DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2
+ DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3
+ DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4
+ DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5
+ DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6
+ DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7
+ DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
+ DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0
+ DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1
+ DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2
+ DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3
+ DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4
+ DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5
+ DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6
+ DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7
+ DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8
+ DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9
+ DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10
+ DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11
+ DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12
+ DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13
+ DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14
+ DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15
+ DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0
+ DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1
+ DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2
+ DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3
+ DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4
+ DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5
+ DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6
+ DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7
+ DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8
+ DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9
+ DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10
+ DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11
+ DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12
+ DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13
+ DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14
+ DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15
+ DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0
+ DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1
+ DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt
+ DCD Cy_Flash_ResumeIrqHandler
+ DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0
+ DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1
+ DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0
+ DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1
+ DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
+ DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
+ DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
+ DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
+ DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
+ DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
+ DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
+ DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
+ DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
+ DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
+ DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2
+ DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3
+ DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4
+ DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5
+ DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6
+ DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7
+ DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8
+ DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9
+ DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10
+ DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11
+ DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12
+ DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13
+ DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14
+ DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15
+ DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16
+ DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17
+ DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18
+ DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19
+ DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20
+ DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21
+ DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22
+ DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23
+ DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0
+ DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1
+ DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2
+ DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3
+ DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4
+ DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5
+ DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6
+ DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7
+ DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8
+ DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9
+ DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10
+ DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11
+ DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12
+ DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13
+ DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14
+ DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15
+ DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
+ DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt
+ DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt
+ DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
+ DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
+ DCD usb_interrupt_hi_IRQHandler ; USB Interrupt
+ DCD usb_interrupt_med_IRQHandler ; USB Interrupt
+ DCD usb_interrupt_lo_IRQHandler ; USB Interrupt
+ DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA RESET_RAM, READWRITE, NOINIT
+__ramVectors
+ SPACE __Vectors_Size
+
+ AREA |.text|, CODE, READONLY
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+ EXPORT Cy_SysLib_FaultHandler [WEAK]
+ AREA |.text|, CODE, READONLY
+Cy_SysLib_FaultHandler
+ B .
+
+ EXPORT HardFault_Handler [WEAK]
+ AREA |.text|, CODE, READONLY
+HardFault_Handler
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq L_MSP
+ mrs r0, PSP
+ b L_API_call
+L_MSP
+ mrs r0, MSP
+L_API_call
+ ; Storing LR content for Creator call stack trace
+ push {LR}
+ bl Cy_SysLib_FaultHandler
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+
+Default_Handler PROC
+ EXPORT Default_Handler [WEAK]
+ EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK]
+ EXPORT ioss_interrupt_gpio_IRQHandler [WEAK]
+ EXPORT ioss_interrupt_vdd_IRQHandler [WEAK]
+ EXPORT lpcomp_interrupt_IRQHandler [WEAK]
+ EXPORT scb_8_interrupt_IRQHandler [WEAK]
+ EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK]
+ EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK]
+ EXPORT srss_interrupt_backup_IRQHandler [WEAK]
+ EXPORT srss_interrupt_IRQHandler [WEAK]
+ EXPORT pass_interrupt_ctbs_IRQHandler [WEAK]
+ EXPORT bless_interrupt_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK]
+ EXPORT scb_0_interrupt_IRQHandler [WEAK]
+ EXPORT scb_1_interrupt_IRQHandler [WEAK]
+ EXPORT scb_2_interrupt_IRQHandler [WEAK]
+ EXPORT scb_3_interrupt_IRQHandler [WEAK]
+ EXPORT scb_4_interrupt_IRQHandler [WEAK]
+ EXPORT scb_5_interrupt_IRQHandler [WEAK]
+ EXPORT scb_6_interrupt_IRQHandler [WEAK]
+ EXPORT scb_7_interrupt_IRQHandler [WEAK]
+ EXPORT csd_interrupt_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK]
+ EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK]
+ EXPORT udb_interrupts_0_IRQHandler [WEAK]
+ EXPORT udb_interrupts_1_IRQHandler [WEAK]
+ EXPORT udb_interrupts_2_IRQHandler [WEAK]
+ EXPORT udb_interrupts_3_IRQHandler [WEAK]
+ EXPORT udb_interrupts_4_IRQHandler [WEAK]
+ EXPORT udb_interrupts_5_IRQHandler [WEAK]
+ EXPORT udb_interrupts_6_IRQHandler [WEAK]
+ EXPORT udb_interrupts_7_IRQHandler [WEAK]
+ EXPORT udb_interrupts_8_IRQHandler [WEAK]
+ EXPORT udb_interrupts_9_IRQHandler [WEAK]
+ EXPORT udb_interrupts_10_IRQHandler [WEAK]
+ EXPORT udb_interrupts_11_IRQHandler [WEAK]
+ EXPORT udb_interrupts_12_IRQHandler [WEAK]
+ EXPORT udb_interrupts_13_IRQHandler [WEAK]
+ EXPORT udb_interrupts_14_IRQHandler [WEAK]
+ EXPORT udb_interrupts_15_IRQHandler [WEAK]
+ EXPORT pass_interrupt_sar_IRQHandler [WEAK]
+ EXPORT audioss_interrupt_i2s_IRQHandler [WEAK]
+ EXPORT audioss_interrupt_pdm_IRQHandler [WEAK]
+ EXPORT profile_interrupt_IRQHandler [WEAK]
+ EXPORT smif_interrupt_IRQHandler [WEAK]
+ EXPORT usb_interrupt_hi_IRQHandler [WEAK]
+ EXPORT usb_interrupt_med_IRQHandler [WEAK]
+ EXPORT usb_interrupt_lo_IRQHandler [WEAK]
+ EXPORT pass_interrupt_dacs_IRQHandler [WEAK]
+
+ioss_interrupts_gpio_0_IRQHandler
+ioss_interrupts_gpio_1_IRQHandler
+ioss_interrupts_gpio_2_IRQHandler
+ioss_interrupts_gpio_3_IRQHandler
+ioss_interrupts_gpio_4_IRQHandler
+ioss_interrupts_gpio_5_IRQHandler
+ioss_interrupts_gpio_6_IRQHandler
+ioss_interrupts_gpio_7_IRQHandler
+ioss_interrupts_gpio_8_IRQHandler
+ioss_interrupts_gpio_9_IRQHandler
+ioss_interrupts_gpio_10_IRQHandler
+ioss_interrupts_gpio_11_IRQHandler
+ioss_interrupts_gpio_12_IRQHandler
+ioss_interrupts_gpio_13_IRQHandler
+ioss_interrupts_gpio_14_IRQHandler
+ioss_interrupt_gpio_IRQHandler
+ioss_interrupt_vdd_IRQHandler
+lpcomp_interrupt_IRQHandler
+scb_8_interrupt_IRQHandler
+srss_interrupt_mcwdt_0_IRQHandler
+srss_interrupt_mcwdt_1_IRQHandler
+srss_interrupt_backup_IRQHandler
+srss_interrupt_IRQHandler
+pass_interrupt_ctbs_IRQHandler
+bless_interrupt_IRQHandler
+cpuss_interrupts_ipc_0_IRQHandler
+cpuss_interrupts_ipc_1_IRQHandler
+cpuss_interrupts_ipc_2_IRQHandler
+cpuss_interrupts_ipc_3_IRQHandler
+cpuss_interrupts_ipc_5_IRQHandler
+cpuss_interrupts_ipc_6_IRQHandler
+cpuss_interrupts_ipc_7_IRQHandler
+cpuss_interrupts_ipc_8_IRQHandler
+cpuss_interrupts_ipc_9_IRQHandler
+cpuss_interrupts_ipc_10_IRQHandler
+cpuss_interrupts_ipc_11_IRQHandler
+cpuss_interrupts_ipc_12_IRQHandler
+cpuss_interrupts_ipc_13_IRQHandler
+cpuss_interrupts_ipc_14_IRQHandler
+cpuss_interrupts_ipc_15_IRQHandler
+scb_0_interrupt_IRQHandler
+scb_1_interrupt_IRQHandler
+scb_2_interrupt_IRQHandler
+scb_3_interrupt_IRQHandler
+scb_4_interrupt_IRQHandler
+scb_5_interrupt_IRQHandler
+scb_6_interrupt_IRQHandler
+scb_7_interrupt_IRQHandler
+csd_interrupt_IRQHandler
+cpuss_interrupts_dw0_0_IRQHandler
+cpuss_interrupts_dw0_1_IRQHandler
+cpuss_interrupts_dw0_2_IRQHandler
+cpuss_interrupts_dw0_3_IRQHandler
+cpuss_interrupts_dw0_4_IRQHandler
+cpuss_interrupts_dw0_5_IRQHandler
+cpuss_interrupts_dw0_6_IRQHandler
+cpuss_interrupts_dw0_7_IRQHandler
+cpuss_interrupts_dw0_8_IRQHandler
+cpuss_interrupts_dw0_9_IRQHandler
+cpuss_interrupts_dw0_10_IRQHandler
+cpuss_interrupts_dw0_11_IRQHandler
+cpuss_interrupts_dw0_12_IRQHandler
+cpuss_interrupts_dw0_13_IRQHandler
+cpuss_interrupts_dw0_14_IRQHandler
+cpuss_interrupts_dw0_15_IRQHandler
+cpuss_interrupts_dw1_0_IRQHandler
+cpuss_interrupts_dw1_1_IRQHandler
+cpuss_interrupts_dw1_2_IRQHandler
+cpuss_interrupts_dw1_3_IRQHandler
+cpuss_interrupts_dw1_4_IRQHandler
+cpuss_interrupts_dw1_5_IRQHandler
+cpuss_interrupts_dw1_6_IRQHandler
+cpuss_interrupts_dw1_7_IRQHandler
+cpuss_interrupts_dw1_8_IRQHandler
+cpuss_interrupts_dw1_9_IRQHandler
+cpuss_interrupts_dw1_10_IRQHandler
+cpuss_interrupts_dw1_11_IRQHandler
+cpuss_interrupts_dw1_12_IRQHandler
+cpuss_interrupts_dw1_13_IRQHandler
+cpuss_interrupts_dw1_14_IRQHandler
+cpuss_interrupts_dw1_15_IRQHandler
+cpuss_interrupts_fault_0_IRQHandler
+cpuss_interrupts_fault_1_IRQHandler
+cpuss_interrupt_crypto_IRQHandler
+cpuss_interrupts_cm0_cti_0_IRQHandler
+cpuss_interrupts_cm0_cti_1_IRQHandler
+cpuss_interrupts_cm4_cti_0_IRQHandler
+cpuss_interrupts_cm4_cti_1_IRQHandler
+tcpwm_0_interrupts_0_IRQHandler
+tcpwm_0_interrupts_1_IRQHandler
+tcpwm_0_interrupts_2_IRQHandler
+tcpwm_0_interrupts_3_IRQHandler
+tcpwm_0_interrupts_4_IRQHandler
+tcpwm_0_interrupts_5_IRQHandler
+tcpwm_0_interrupts_6_IRQHandler
+tcpwm_0_interrupts_7_IRQHandler
+tcpwm_1_interrupts_0_IRQHandler
+tcpwm_1_interrupts_1_IRQHandler
+tcpwm_1_interrupts_2_IRQHandler
+tcpwm_1_interrupts_3_IRQHandler
+tcpwm_1_interrupts_4_IRQHandler
+tcpwm_1_interrupts_5_IRQHandler
+tcpwm_1_interrupts_6_IRQHandler
+tcpwm_1_interrupts_7_IRQHandler
+tcpwm_1_interrupts_8_IRQHandler
+tcpwm_1_interrupts_9_IRQHandler
+tcpwm_1_interrupts_10_IRQHandler
+tcpwm_1_interrupts_11_IRQHandler
+tcpwm_1_interrupts_12_IRQHandler
+tcpwm_1_interrupts_13_IRQHandler
+tcpwm_1_interrupts_14_IRQHandler
+tcpwm_1_interrupts_15_IRQHandler
+tcpwm_1_interrupts_16_IRQHandler
+tcpwm_1_interrupts_17_IRQHandler
+tcpwm_1_interrupts_18_IRQHandler
+tcpwm_1_interrupts_19_IRQHandler
+tcpwm_1_interrupts_20_IRQHandler
+tcpwm_1_interrupts_21_IRQHandler
+tcpwm_1_interrupts_22_IRQHandler
+tcpwm_1_interrupts_23_IRQHandler
+udb_interrupts_0_IRQHandler
+udb_interrupts_1_IRQHandler
+udb_interrupts_2_IRQHandler
+udb_interrupts_3_IRQHandler
+udb_interrupts_4_IRQHandler
+udb_interrupts_5_IRQHandler
+udb_interrupts_6_IRQHandler
+udb_interrupts_7_IRQHandler
+udb_interrupts_8_IRQHandler
+udb_interrupts_9_IRQHandler
+udb_interrupts_10_IRQHandler
+udb_interrupts_11_IRQHandler
+udb_interrupts_12_IRQHandler
+udb_interrupts_13_IRQHandler
+udb_interrupts_14_IRQHandler
+udb_interrupts_15_IRQHandler
+pass_interrupt_sar_IRQHandler
+audioss_interrupt_i2s_IRQHandler
+audioss_interrupt_pdm_IRQHandler
+profile_interrupt_IRQHandler
+smif_interrupt_IRQHandler
+usb_interrupt_hi_IRQHandler
+usb_interrupt_med_IRQHandler
+usb_interrupt_lo_IRQHandler
+pass_interrupt_dacs_IRQHandler
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/platform/ext/target/psoc64/Device/Source/armclang/startup_psoc6_s.s b/platform/ext/target/psoc64/Device/Source/armclang/startup_psoc6_s.s
new file mode 100644
index 0000000000..22ac8d3748
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/armclang/startup_psoc6_s.s
@@ -0,0 +1,177 @@
+;/*
+; * Copyright (c) 2017-2018 ARM Limited
+; * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
+; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+; Address of the NMI handler in ROM
+CY_NMI_HANLDER_ADDR EQU 0x0000000D
+
+ PRESERVE8
+
+ IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+ EXPORT __ramVectors
+
+ IMPORT HardFault_Handler
+ IMPORT SVC_Handler
+ IMPORT PendSV_Handler
+ IMPORT NvicMux9_IRQHandler
+ IMPORT Cy_SysIpcPipeIsrCm0
+
+__Vectors ;Core Interrupts
+ DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD CY_NMI_HANLDER_ADDR ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External interrupts Description
+ DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0
+ DCD Cy_SysIpcPipeIsrCm0
+ DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2
+ DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3
+ DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4
+ DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5
+ DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6
+ DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7
+ DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8
+ DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9
+ DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10
+ DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11
+ DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12
+ DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13
+ DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14
+ DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15
+ DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16
+ DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17
+ DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18
+ DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19
+ DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20
+ DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21
+ DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22
+ DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23
+ DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24
+ DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25
+ DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26
+ DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27
+ DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28
+ DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29
+ DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30
+ DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA RESET_RAM, READWRITE, NOINIT
+__ramVectors
+ SPACE __Vectors_Size
+
+; Reset Handler
+ AREA |.text|, CODE, READONLY
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ CPSID i ; Disable IRQs
+ LDR R0, =SystemInit
+ BLX R0
+ MOV R3, SP
+ MRS R0, control ; Get control value
+ MOVS R1, #2
+ ORRS R0, R0, R1 ; Select switch to PSP
+
+ MSR control, R0
+ MOV SP, R3
+ LDR R0, =__main
+ BX R0
+ ENDP
+End_Of_Main
+ B .
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+ MACRO
+ Default_Handler $handler_name
+$handler_name PROC
+ EXPORT $handler_name [WEAK]
+ B .
+ ENDP
+ MEND
+
+ Default_Handler SysTick_Handler
+ Default_Handler NvicMux0_IRQHandler
+ Default_Handler NvicMux2_IRQHandler
+ Default_Handler NvicMux3_IRQHandler
+ Default_Handler NvicMux4_IRQHandler
+ Default_Handler NvicMux5_IRQHandler
+ Default_Handler NvicMux6_IRQHandler
+ Default_Handler NvicMux7_IRQHandler
+ Default_Handler NvicMux8_IRQHandler
+ Default_Handler NvicMux10_IRQHandler
+ Default_Handler NvicMux11_IRQHandler
+ Default_Handler NvicMux12_IRQHandler
+ Default_Handler NvicMux13_IRQHandler
+ Default_Handler NvicMux14_IRQHandler
+ Default_Handler NvicMux15_IRQHandler
+ Default_Handler NvicMux16_IRQHandler
+ Default_Handler NvicMux17_IRQHandler
+ Default_Handler NvicMux18_IRQHandler
+ Default_Handler NvicMux19_IRQHandler
+ Default_Handler NvicMux20_IRQHandler
+ Default_Handler NvicMux21_IRQHandler
+ Default_Handler NvicMux22_IRQHandler
+ Default_Handler NvicMux23_IRQHandler
+ Default_Handler NvicMux24_IRQHandler
+ Default_Handler NvicMux25_IRQHandler
+ Default_Handler NvicMux26_IRQHandler
+ Default_Handler NvicMux27_IRQHandler
+ Default_Handler NvicMux28_IRQHandler
+ Default_Handler NvicMux29_IRQHandler
+ Default_Handler NvicMux30_IRQHandler
+ Default_Handler NvicMux31_IRQHandler
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/psoc64/Device/Source/device_definition.c b/platform/ext/target/psoc64/Device/Source/device_definition.c
new file mode 100644
index 0000000000..b11f5b2a26
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/device_definition.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file device_definition.c
+ * \brief This file defines exports the structures based on the peripheral
+ * definitions from device_cfg.h.
+ * This retarget file is meant to be used as a helper for baremetal
+ * applications and/or as an example of how to configure the generic
+ * driver structures.
+ */
+
+#include "device_definition.h"
+#include "platform_base_address.h"
+
+/* CMSDK Timer driver structures */
+#ifdef CMSDK_TIMER0_S
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S = {
+ .base = CMSDK_TIMER0_BASE_S};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_S = {
+ .is_initialized = 0};
+struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S = {&(CMSDK_TIMER0_DEV_CFG_S),
+ &(CMSDK_TIMER0_DEV_DATA_S)};
+#endif
+#ifdef CMSDK_TIMER0_NS
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_NS = {
+ .base = CMSDK_TIMER0_BASE_NS};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_NS = {
+ .is_initialized = 0};
+struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS = {&(CMSDK_TIMER0_DEV_CFG_NS),
+ &(CMSDK_TIMER0_DEV_DATA_NS)};
+#endif
+
+#ifdef CMSDK_TIMER1_S
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_S = {
+ .base = CMSDK_TIMER1_BASE_S};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_S = {
+ .is_initialized = 0};
+struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S = {&(CMSDK_TIMER1_DEV_CFG_S),
+ &(CMSDK_TIMER1_DEV_DATA_S)};
+#endif
+#ifdef CMSDK_TIMER1_NS
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_NS = {
+ .base = CMSDK_TIMER1_BASE_NS};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_NS = {
+ .is_initialized = 0};
+struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS = {&(CMSDK_TIMER1_DEV_CFG_NS),
+ &(CMSDK_TIMER1_DEV_DATA_NS)};
+#endif
+
diff --git a/platform/ext/target/psoc64/Device/Source/gcc/cy_syslib_gcc.S b/platform/ext/target/psoc64/Device/Source/gcc/cy_syslib_gcc.S
new file mode 100644
index 0000000000..25d8b6a6f6
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/gcc/cy_syslib_gcc.S
@@ -0,0 +1,150 @@
+/***************************************************************************//**
+* \file cy_syslib_gcc.S
+* \version 2.20
+*
+* \brief Assembly routines for GNU GCC.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+.syntax unified
+.text
+.thumb
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_DelayCycles
+****************************************************************************//**
+*
+* Delays for the specified number of cycles.
+*
+* \param uint32_t cycles: The number of cycles to delay.
+*
+*******************************************************************************/
+/* void Cy_SysLib_DelayCycles(uint32_t cycles) */
+.align 3 /* Align to 8 byte boundary (2^n) */
+#ifndef __clang__
+.global Cy_SysLib_DelayCycles
+.func Cy_SysLib_DelayCycles, Cy_SysLib_DelayCycles
+.type Cy_SysLib_DelayCycles, %function
+.thumb_func
+Cy_SysLib_DelayCycles: /* cycles bytes */
+
+#else
+.global _Cy_SysLib_DelayCycles
+.thumb_func
+
+_Cy_SysLib_DelayCycles: /* cycles bytes */
+#endif
+
+ ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */
+ LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */
+ BEQ Cy_DelayCycles_done /* 2 2 Skip if 0 */
+#ifdef __clang__
+ .align 2 /* Align to 8 byte boundary (2^n) */
+#endif
+Cy_DelayCycles_loop:
+ ADDS r0, r0, #1 /* 1 2 Increment counter */
+ SUBS r0, r0, #2 /* 1 2 Decrement counter by 2 */
+ BNE Cy_DelayCycles_loop /* (1)2 2 2 CPU cycles (if branch is taken) */
+ NOP /* 1 2 Loop alignment padding */
+#ifdef __clang__
+ .align 2 /* Align to 8 byte boundary (2^n) */
+#endif
+Cy_DelayCycles_done:
+ NOP /* 1 2 Loop alignment padding */
+ BX lr /* 3 2 */
+
+#ifndef __clang__
+.endfunc
+#endif
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_EnterCriticalSection
+****************************************************************************//**
+*
+* Cy_SysLib_EnterCriticalSection disables interrupts and returns a value
+* indicating whether interrupts were previously enabled.
+*
+* Note Implementation of Cy_SysLib_EnterCriticalSection manipulates the IRQ
+* enable bit with interrupts still enabled.
+*
+* \return Returns 0 if interrupts were previously enabled or 1 if interrupts
+* were previously disabled.
+*
+*******************************************************************************/
+/* uint8_t Cy_SysLib_EnterCriticalSection(void) */
+#ifndef __clang__
+.global Cy_SysLib_EnterCriticalSection
+.func Cy_SysLib_EnterCriticalSection, Cy_SysLib_EnterCriticalSection
+.type Cy_SysLib_EnterCriticalSection, %function
+.thumb_func
+
+Cy_SysLib_EnterCriticalSection:
+#else
+.global _Cy_SysLib_EnterCriticalSection
+.thumb_func
+
+_Cy_SysLib_EnterCriticalSection:
+#endif
+
+ MRS r0, PRIMASK /* Save and return interrupt state */
+ cpsid i /* Disable interrupts */
+ BX lr
+
+#ifndef __clang__
+.endfunc
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_ExitCriticalSection
+****************************************************************************//**
+*
+* Re-enables interrupts if they were enabled before
+* Cy_SysLib_EnterCriticalSection() was called. The argument should be the value
+* returned from \ref Cy_SysLib_EnterCriticalSection().
+*
+* \param uint8_t savedIntrStatus:
+* Saved interrupt status returned by the \ref Cy_SysLib_EnterCriticalSection().
+*
+*******************************************************************************/
+/* void Cy_SysLib_ExitCriticalSection(uint8_t savedIntrStatus) */
+#ifndef __clang__
+.global Cy_SysLib_ExitCriticalSection
+.func Cy_SysLib_ExitCriticalSection, Cy_SysLib_ExitCriticalSection
+.type Cy_SysLib_ExitCriticalSection, %function
+.thumb_func
+Cy_SysLib_ExitCriticalSection:
+#else
+.global _Cy_SysLib_ExitCriticalSection
+.thumb_func
+
+_Cy_SysLib_ExitCriticalSection:
+#endif
+
+ MSR PRIMASK, r0 /* Restore interrupt state */
+ BX lr
+
+#ifndef __clang__
+.endfunc
+#endif
+
+.end
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Source/gcc/psoc6_bl2.ld b/platform/ext/target/psoc64/Device/Source/gcc/psoc6_bl2.ld
new file mode 100644
index 0000000000..e389ab39ba
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/gcc/psoc6_bl2.ld
@@ -0,0 +1,396 @@
+/*
+ * Copyright (c) 2018-2019 ARM Limited
+ * Copyright 2016-2018 Cypress Semiconductor Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of Cypress PDL 3.0 cy8c6xx7_cm0plus.ld
+ */
+
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+#include "region_defs.h"
+
+__heap_size__ = BL2_HEAP_SIZE;
+__msp_stack_size__ = BL2_MSP_STACK_SIZE;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
+ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+ */
+ ram (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE
+ flash (rx) : ORIGIN = BL2_CODE_START, LENGTH = BL2_CODE_SIZE
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
+ sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
+ sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ .cy_app_header :
+ {
+ KEEP(*(.cy_app_header))
+ } > flash
+
+ .text :
+ {
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+#endif
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+ } > flash
+
+ __etext = . ;
+
+ .tfm_bl2_shared_data BOOT_TFM_SHARED_DATA_BASE : ALIGN(32)
+ {
+ . += BOOT_TFM_SHARED_DATA_SIZE;
+ } > ram
+ Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data);
+ Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data);
+
+#ifdef RAM_VECTORS_SUPPORT
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+ .data __ram_vectors_end__ : AT (__etext)
+#else
+ .data : AT (__etext)
+#endif
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.ramfunc))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+ bss_size = __bss_end__ - __bss_start__;
+
+ .msp_stack (NOLOAD): ALIGN(32)
+ {
+ . += __msp_stack_size__;
+ } > ram
+
+ Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+ .heap (NOLOAD): ALIGN(8)
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += __heap_size__;
+ __HeapLimit = .;
+ } > ram
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+
+ /* Supervisory Flash: Table of Content # 2 Copy */
+ .cy_rtoc_part2 :
+ {
+ KEEP(*(.cy_rtoc_part2))
+ } > sflash_rtoc_2
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ .cy_xip :
+ {
+ KEEP(*(.cy_xip))
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+
+ /* These sections are used for additional metadata (silicon revision,
+ * Silicon/JTAG ID, etc.) storage.
+ */
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start = 0x10000000;
+__cy_memory_0_length = 0x00100000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start = 0x14000000;
+__cy_memory_1_length = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start = 0x16000000;
+__cy_memory_2_length = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start = 0x18000000;
+__cy_memory_3_length = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start = 0x90700000;
+__cy_memory_4_length = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/platform/ext/target/psoc64/Device/Source/gcc/psoc6_ns.ld b/platform/ext/target/psoc64/Device/Source/gcc/psoc6_ns.ld
new file mode 100644
index 0000000000..77a436a0b3
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/gcc/psoc6_ns.ld
@@ -0,0 +1,421 @@
+/*
+ * Copyright (c) 2018-2019 ARM Limited
+ * Copyright 2016-2018 Cypress Semiconductor Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of Cypress PDL 3.0 cy8c6xx7_cm4_dual.ld
+ */
+
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+#include "region_defs.h"
+
+__heap_size__ = NS_HEAP_SIZE;
+__psp_stack_size__ = NS_PSP_STACK_SIZE;
+__msp_stack_size__ = NS_MSP_STACK_SIZE;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+ */
+ ram (rwx) : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE
+ flash (rx) : ORIGIN = NS_CODE_START, LENGTH = NS_CODE_SIZE
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
+ sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
+ sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+#endif
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+ } > flash
+
+ __etext = . ;
+
+
+#ifdef RAM_VECTORS_SUPPORT
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+ .data __ram_vectors_end__ : AT (__etext)
+#else
+ .data : AT (__etext)
+#endif
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.ramfunc))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ PROVIDE(end = .);
+ end = __end__;
+ . += __heap_size__;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > ram
+
+ .msp_stack : ALIGN(32)
+ {
+ . += __msp_stack_size__;
+ } > ram
+ Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+ .psp_stack : ALIGN(32)
+ {
+ . += __psp_stack_size__;
+ } > ram
+
+ Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack);
+ Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);
+
+ PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);
+
+ Image$$ER_TFM_DATA$$RW$$Base = ADDR(.data);
+ Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.data) + SIZEOF(.data);
+
+ Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.bss);
+ Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.bss) + SIZEOF(.bss);
+
+ Image$$ER_TFM_DATA$$Base = ADDR(.data);
+ Image$$ER_TFM_DATA$$Limit = ADDR(.data) + SIZEOF(.data) + SIZEOF(.bss);
+
+#if defined (NS_DATA_SHARED_START)
+ .TFM_SHARED NS_DATA_SHARED_START (NOLOAD) :
+ {
+ . = ALIGN(4);
+ . += NS_DATA_SHARED_SIZE;
+ } > ram
+#endif
+
+ /* Used for the digital signature of the secure application and the Bootloader SDK appication.
+ * The size of the section depends on the required data size. */
+ .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
+ {
+ KEEP(*(.cy_app_signature))
+ } > flash
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+
+ /* Supervisory Flash: Table of Content # 2 Copy */
+ .cy_rtoc_part2 :
+ {
+ KEEP(*(.cy_rtoc_part2))
+ } > sflash_rtoc_2
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ .cy_xip :
+ {
+ KEEP(*(.cy_xip))
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+
+ /* These sections are used for additional metadata (silicon revision,
+ * Silicon/JTAG ID, etc.) storage.
+ */
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start = 0x10000000;
+__cy_memory_0_length = 0x00100000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start = 0x14000000;
+__cy_memory_1_length = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start = 0x16000000;
+__cy_memory_2_length = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start = 0x18000000;
+__cy_memory_3_length = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start = 0x90700000;
+__cy_memory_4_length = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/platform/ext/target/psoc64/Device/Source/gcc/startup_psoc6_bl2.S b/platform/ext/target/psoc64/Device/Source/gcc/startup_psoc6_bl2.S
new file mode 100644
index 0000000000..40b4aa9754
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/gcc/startup_psoc6_bl2.S
@@ -0,0 +1,385 @@
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* adapted from Cypress-Peripheral-Driver-Library-v3.0.1 startup_psoc63_cm0plus.S*/
+
+#include "region_defs.h"
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */
+ .long Cy_SysIpcPipeIsrCm0
+ .long NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */
+ .long NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */
+ .long NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */
+ .long NvicMux5_IRQHandler /* CM0 + NVIC Mux input 5 */
+ .long NvicMux6_IRQHandler /* CM0 + NVIC Mux input 6 */
+ .long NvicMux7_IRQHandler /* CM0 + NVIC Mux input 7 */
+ .long NvicMux8_IRQHandler /* CM0 + NVIC Mux input 8 */
+ .long NvicMux9_IRQHandler /* CM0 + NVIC Mux input 9 */
+ .long NvicMux10_IRQHandler /* CM0 + NVIC Mux input 10 */
+ .long NvicMux11_IRQHandler /* CM0 + NVIC Mux input 11 */
+ .long NvicMux12_IRQHandler /* CM0 + NVIC Mux input 12 */
+ .long NvicMux13_IRQHandler /* CM0 + NVIC Mux input 13 */
+ .long NvicMux14_IRQHandler /* CM0 + NVIC Mux input 14 */
+ .long NvicMux15_IRQHandler /* CM0 + NVIC Mux input 15 */
+ .long NvicMux16_IRQHandler /* CM0 + NVIC Mux input 16 */
+ .long NvicMux17_IRQHandler /* CM0 + NVIC Mux input 17 */
+ .long NvicMux18_IRQHandler /* CM0 + NVIC Mux input 18 */
+ .long NvicMux19_IRQHandler /* CM0 + NVIC Mux input 19 */
+ .long NvicMux20_IRQHandler /* CM0 + NVIC Mux input 20 */
+ .long NvicMux21_IRQHandler /* CM0 + NVIC Mux input 21 */
+ .long NvicMux22_IRQHandler /* CM0 + NVIC Mux input 22 */
+ .long NvicMux23_IRQHandler /* CM0 + NVIC Mux input 23 */
+ .long NvicMux24_IRQHandler /* CM0 + NVIC Mux input 24 */
+ .long NvicMux25_IRQHandler /* CM0 + NVIC Mux input 25 */
+ .long NvicMux26_IRQHandler /* CM0 + NVIC Mux input 26 */
+ .long NvicMux27_IRQHandler /* CM0 + NVIC Mux input 27 */
+ .long NvicMux28_IRQHandler /* CM0 + NVIC Mux input 28 */
+ .long NvicMux29_IRQHandler /* CM0 + NVIC Mux input 29 */
+ .long NvicMux30_IRQHandler /* CM0 + NVIC Mux input 30 */
+ .long NvicMux31_IRQHandler /* CM0 + NVIC Mux input 31 */
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+#ifdef RAM_VECTORS_SUPPORT
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+#else
+ /* vectors relocation is not supported,
+ but allocate __ramVectors for PDL code */
+ .globl __ramVectors
+ .equ __ramVectors, 0
+#endif
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /* Device startup customization */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+Cy_OnResetUser:
+
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Saves and disables the interrupts */
+ .global Cy_SaveIRQ
+ .func Cy_SaveIRQ, Cy_SaveIRQ
+ .type Cy_SaveIRQ, %function
+Cy_SaveIRQ:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+ .size Cy_SaveIRQ, . - Cy_SaveIRQ
+ .endfunc
+
+ /* Restores the interrupts */
+ .global Cy_RestoreIRQ
+ .func Cy_RestoreIRQ, Cy_RestoreIRQ
+ .type Cy_RestoreIRQ, %function
+Cy_RestoreIRQ:
+ msr PRIMASK, r0
+ bx lr
+ .size Cy_RestoreIRQ, . - Cy_RestoreIRQ
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ bl main
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+
+
+ .type Fault_Handler, %function
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+.L_API_call:
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_fault_Handler HardFault_Handler
+
+ def_irq_handler SVC_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */
+ def_irq_handler NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */
+ def_irq_handler NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */
+ def_irq_handler NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */
+ def_irq_handler NvicMux5_IRQHandler /* CM0 + NVIC Mux input 5 */
+ def_irq_handler NvicMux6_IRQHandler /* CM0 + NVIC Mux input 6 */
+ def_irq_handler NvicMux7_IRQHandler /* CM0 + NVIC Mux input 7 */
+ def_irq_handler NvicMux8_IRQHandler /* CM0 + NVIC Mux input 8 */
+ def_irq_handler NvicMux9_IRQHandler /* CM0 + NVIC Mux input 9 */
+ def_irq_handler NvicMux10_IRQHandler /* CM0 + NVIC Mux input 10 */
+ def_irq_handler NvicMux11_IRQHandler /* CM0 + NVIC Mux input 11 */
+ def_irq_handler NvicMux12_IRQHandler /* CM0 + NVIC Mux input 12 */
+ def_irq_handler NvicMux13_IRQHandler /* CM0 + NVIC Mux input 13 */
+ def_irq_handler NvicMux14_IRQHandler /* CM0 + NVIC Mux input 14 */
+ def_irq_handler NvicMux15_IRQHandler /* CM0 + NVIC Mux input 15 */
+ def_irq_handler NvicMux16_IRQHandler /* CM0 + NVIC Mux input 16 */
+ def_irq_handler NvicMux17_IRQHandler /* CM0 + NVIC Mux input 17 */
+ def_irq_handler NvicMux18_IRQHandler /* CM0 + NVIC Mux input 18 */
+ def_irq_handler NvicMux19_IRQHandler /* CM0 + NVIC Mux input 19 */
+ def_irq_handler NvicMux20_IRQHandler /* CM0 + NVIC Mux input 20 */
+ def_irq_handler NvicMux21_IRQHandler /* CM0 + NVIC Mux input 21 */
+ def_irq_handler NvicMux22_IRQHandler /* CM0 + NVIC Mux input 22 */
+ def_irq_handler NvicMux23_IRQHandler /* CM0 + NVIC Mux input 23 */
+ def_irq_handler NvicMux24_IRQHandler /* CM0 + NVIC Mux input 24 */
+ def_irq_handler NvicMux25_IRQHandler /* CM0 + NVIC Mux input 25 */
+ def_irq_handler NvicMux26_IRQHandler /* CM0 + NVIC Mux input 26 */
+ def_irq_handler NvicMux27_IRQHandler /* CM0 + NVIC Mux input 27 */
+ def_irq_handler NvicMux28_IRQHandler /* CM0 + NVIC Mux input 28 */
+ def_irq_handler NvicMux29_IRQHandler /* CM0 + NVIC Mux input 29 */
+ def_irq_handler NvicMux30_IRQHandler /* CM0 + NVIC Mux input 30 */
+ def_irq_handler NvicMux31_IRQHandler /* CM0 + NVIC Mux input 31 */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Source/gcc/startup_psoc6_ns.S b/platform/ext/target/psoc64/Device/Source/gcc/startup_psoc6_ns.S
new file mode 100644
index 0000000000..68011103d0
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/gcc/startup_psoc6_ns.S
@@ -0,0 +1,616 @@
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* adapted from Cypress-Peripheral-Driver-Library-v3.0.1 startup_psoc63_cm4.S*/
+
+#include "region_defs.h"
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
+ .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
+ .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ .long Cy_SysIpcPipeIsrCm4
+ .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ .long Cy_Flash_ResumeIrqHandler
+ .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
+ .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
+ .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
+ .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
+ .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
+ .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
+ .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
+ .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
+ .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
+ .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
+ .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
+ .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
+ .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
+ .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
+ .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
+ .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
+ .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
+ .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
+ .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ .long usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_med_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
+
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+#ifdef RAM_VECTORS_SUPPORT
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+#else
+ /* vectors relocation is not supported,
+ but allocate __ramVectors for PDL code */
+ .globl __ramVectors
+ .equ __ramVectors, 0
+#endif
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /* Device startup customization */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+Cy_OnResetUser:
+
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Saves and disables the interrupts */
+ .global Cy_SaveIRQ
+ .func Cy_SaveIRQ, Cy_SaveIRQ
+ .type Cy_SaveIRQ, %function
+Cy_SaveIRQ:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+ .size Cy_SaveIRQ, . - Cy_SaveIRQ
+ .endfunc
+
+ /* Restores the interrupts */
+ .global Cy_RestoreIRQ
+ .func Cy_RestoreIRQ, Cy_RestoreIRQ
+ .type Cy_RestoreIRQ, %function
+Cy_RestoreIRQ:
+ msr PRIMASK, r0
+ bx lr
+ .size Cy_RestoreIRQ, . - Cy_RestoreIRQ
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+#endif
+
+#if defined (__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ /* temp workaround: this file is built as a part of sc built too */
+ /* Enable the FPU if used */
+ bl Cy_SystemInitFpuEnable
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ cpsie i
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+
+ .type Fault_Handler, %function
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+.L_API_call:
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+
+ def_fault_Handler HardFault_Handler
+ def_fault_Handler MemManage_Handler
+ def_fault_Handler BusFault_Handler
+ def_fault_Handler UsageFault_Handler
+
+ def_irq_handler DebugMon_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
+ def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
+ def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
+ def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
+ def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
+ def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
+ def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
+ def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
+ def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
+ def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
+ def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
+ def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
+ def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
+ def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
+ def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
+ def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
+ def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
+ def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
+ def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
+ def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
+ def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Source/gcc/startup_psoc6_s.S b/platform/ext/target/psoc64/Device/Source/gcc/startup_psoc6_s.S
new file mode 100644
index 0000000000..887f692cad
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/gcc/startup_psoc6_s.S
@@ -0,0 +1,387 @@
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* adapted from Cypress-Peripheral-Driver-Library-v3.0.1 startup_psoc63_cm0plus.S*/
+
+#include "region_defs.h"
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */
+ .long Cy_SysIpcPipeIsrCm0
+ .long NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */
+ .long NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */
+ .long NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */
+ .long NvicMux5_IRQHandler /* CM0 + NVIC Mux input 5 */
+ .long NvicMux6_IRQHandler /* CM0 + NVIC Mux input 6 */
+ .long NvicMux7_IRQHandler /* CM0 + NVIC Mux input 7 */
+ .long NvicMux8_IRQHandler /* CM0 + NVIC Mux input 8 */
+ .long NvicMux9_IRQHandler /* CM0 + NVIC Mux input 9 */
+ .long NvicMux10_IRQHandler /* CM0 + NVIC Mux input 10 */
+ .long NvicMux11_IRQHandler /* CM0 + NVIC Mux input 11 */
+ .long NvicMux12_IRQHandler /* CM0 + NVIC Mux input 12 */
+ .long NvicMux13_IRQHandler /* CM0 + NVIC Mux input 13 */
+ .long NvicMux14_IRQHandler /* CM0 + NVIC Mux input 14 */
+ .long NvicMux15_IRQHandler /* CM0 + NVIC Mux input 15 */
+ .long NvicMux16_IRQHandler /* CM0 + NVIC Mux input 16 */
+ .long NvicMux17_IRQHandler /* CM0 + NVIC Mux input 17 */
+ .long NvicMux18_IRQHandler /* CM0 + NVIC Mux input 18 */
+ .long NvicMux19_IRQHandler /* CM0 + NVIC Mux input 19 */
+ .long NvicMux20_IRQHandler /* CM0 + NVIC Mux input 20 */
+ .long NvicMux21_IRQHandler /* CM0 + NVIC Mux input 21 */
+ .long NvicMux22_IRQHandler /* CM0 + NVIC Mux input 22 */
+ .long NvicMux23_IRQHandler /* CM0 + NVIC Mux input 23 */
+ .long NvicMux24_IRQHandler /* CM0 + NVIC Mux input 24 */
+ .long NvicMux25_IRQHandler /* CM0 + NVIC Mux input 25 */
+ .long NvicMux26_IRQHandler /* CM0 + NVIC Mux input 26 */
+ .long NvicMux27_IRQHandler /* CM0 + NVIC Mux input 27 */
+ .long NvicMux28_IRQHandler /* CM0 + NVIC Mux input 28 */
+ .long NvicMux29_IRQHandler /* CM0 + NVIC Mux input 29 */
+ .long NvicMux30_IRQHandler /* CM0 + NVIC Mux input 30 */
+ .long NvicMux31_IRQHandler /* CM0 + NVIC Mux input 31 */
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+#ifdef RAM_VECTORS_SUPPORT
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+#else
+ /* vectors relocation is not supported,
+ but allocate __ramVectors for PDL code */
+ .globl __ramVectors
+ .equ __ramVectors, 0
+#endif
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /* Device startup customization */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+Cy_OnResetUser:
+
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Saves and disables the interrupts */
+ .global Cy_SaveIRQ
+ .func Cy_SaveIRQ, Cy_SaveIRQ
+ .type Cy_SaveIRQ, %function
+Cy_SaveIRQ:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+ .size Cy_SaveIRQ, . - Cy_SaveIRQ
+ .endfunc
+
+ /* Restores the interrupts */
+ .global Cy_RestoreIRQ
+ .func Cy_RestoreIRQ, Cy_RestoreIRQ
+ .type Cy_RestoreIRQ, %function
+Cy_RestoreIRQ:
+ msr PRIMASK, r0
+ bx lr
+ .size Cy_RestoreIRQ, . - Cy_RestoreIRQ
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ mrs r0, control /* Get control value */
+ movs r1, #2
+ orrs r0, r0, r1 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+ msr psp, r0
+
+ bl main
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+
+ .type Fault_Handler, %function
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+.L_API_call:
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */
+ def_irq_handler NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */
+ def_irq_handler NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */
+ def_irq_handler NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */
+ def_irq_handler NvicMux5_IRQHandler /* CM0 + NVIC Mux input 5 */
+ def_irq_handler NvicMux6_IRQHandler /* CM0 + NVIC Mux input 6 */
+ def_irq_handler NvicMux7_IRQHandler /* CM0 + NVIC Mux input 7 */
+ def_irq_handler NvicMux8_IRQHandler /* CM0 + NVIC Mux input 8 */
+ def_irq_handler NvicMux9_IRQHandler /* CM0 + NVIC Mux input 9 */
+ def_irq_handler NvicMux10_IRQHandler /* CM0 + NVIC Mux input 10 */
+ def_irq_handler NvicMux11_IRQHandler /* CM0 + NVIC Mux input 11 */
+ def_irq_handler NvicMux12_IRQHandler /* CM0 + NVIC Mux input 12 */
+ def_irq_handler NvicMux13_IRQHandler /* CM0 + NVIC Mux input 13 */
+ def_irq_handler NvicMux14_IRQHandler /* CM0 + NVIC Mux input 14 */
+ def_irq_handler NvicMux15_IRQHandler /* CM0 + NVIC Mux input 15 */
+ def_irq_handler NvicMux16_IRQHandler /* CM0 + NVIC Mux input 16 */
+ def_irq_handler NvicMux17_IRQHandler /* CM0 + NVIC Mux input 17 */
+ def_irq_handler NvicMux18_IRQHandler /* CM0 + NVIC Mux input 18 */
+ def_irq_handler NvicMux19_IRQHandler /* CM0 + NVIC Mux input 19 */
+ def_irq_handler NvicMux20_IRQHandler /* CM0 + NVIC Mux input 20 */
+ def_irq_handler NvicMux21_IRQHandler /* CM0 + NVIC Mux input 21 */
+ def_irq_handler NvicMux22_IRQHandler /* CM0 + NVIC Mux input 22 */
+ def_irq_handler NvicMux23_IRQHandler /* CM0 + NVIC Mux input 23 */
+ def_irq_handler NvicMux24_IRQHandler /* CM0 + NVIC Mux input 24 */
+ def_irq_handler NvicMux25_IRQHandler /* CM0 + NVIC Mux input 25 */
+ def_irq_handler NvicMux26_IRQHandler /* CM0 + NVIC Mux input 26 */
+ def_irq_handler NvicMux27_IRQHandler /* CM0 + NVIC Mux input 27 */
+ def_irq_handler NvicMux28_IRQHandler /* CM0 + NVIC Mux input 28 */
+ def_irq_handler NvicMux29_IRQHandler /* CM0 + NVIC Mux input 29 */
+ def_irq_handler NvicMux30_IRQHandler /* CM0 + NVIC Mux input 30 */
+ def_irq_handler NvicMux31_IRQHandler /* CM0 + NVIC Mux input 31 */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Source/system_psoc6_cm0plus.c b/platform/ext/target/psoc64/Device/Source/system_psoc6_cm0plus.c
new file mode 100644
index 0000000000..45dc6be4b0
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/system_psoc6_cm0plus.c
@@ -0,0 +1,751 @@
+/***************************************************************************//**
+* \file system_psoc6_cm0plus.c
+* \version 2.60
+*
+* The device system-source file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdbool.h>
+#include "system_psoc6.h"
+#include "cycfg.h"
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include "cy_wdt.h"
+#include "Driver_Flash.h"
+#include "flash_layout.h"
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ #include "cy_ipc_sema.h"
+ #include "cy_ipc_pipe.h"
+ #include "cy_ipc_drv.h"
+
+ #if defined(CY_DEVICE_PSOC6ABLE2)
+ #include "cy_flash.h"
+ #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
+
+/** Default SlowClk system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
+
+/** IMO frequency in Hz */
+#define CY_CLK_IMO_FREQ_HZ (8000000UL)
+
+/** HVILO frequency in Hz */
+#define CY_CLK_HVILO_FREQ_HZ (32000UL)
+
+/** PILO frequency in Hz */
+#define CY_CLK_PILO_FREQ_HZ (32768UL)
+
+/** WCO frequency in Hz */
+#define CY_CLK_WCO_FREQ_HZ (32768UL)
+
+/** ALTLF frequency in Hz */
+#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
+
+
+/**
+* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
+* which is the system clock frequency supplied to the SysTick timer and the
+* processor core clock.
+* This variable implements CMSIS Core global variable.
+* Refer to the [CMSIS documentation]
+* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
+* for more details.
+* This variable can be used by debuggers to query the frequency
+* of the debug timer or to configure the trace clock speed.
+*
+* \attention Compilers must be configured to avoid removing this variable in case
+* the application program is not using it. Debugging systems require the variable
+* to be physically present in memory so that it can be examined to configure the debugger. */
+uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
+
+/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
+#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
+ uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
+#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
+
+
+/*******************************************************************************
+* SystemInit()
+*******************************************************************************/
+
+/* CLK_FLL_CONFIG default values */
+#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
+#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
+#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
+#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
+#define CY_DELAY_1K_THRESHOLD (1000u)
+#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
+#define CY_DELAY_1M_THRESHOLD (1000000u)
+#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
+uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
+ CY_DELAY_1K_THRESHOLD;
+
+uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
+ CY_DELAY_1M_THRESHOLD);
+
+uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
+ ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
+
+#define CY_ROOT_PATH_SRC_IMO (0UL)
+#define CY_ROOT_PATH_SRC_EXT (1UL)
+#if (SRSS_ECO_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_ECO (2UL)
+#endif /* (SRSS_ECO_PRESENT == 1U) */
+#if (SRSS_ALTHF_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_ALTHF (3UL)
+#endif /* (SRSS_ALTHF_PRESENT == 1U) */
+#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
+#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
+#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
+#if (SRSS_ALTLF_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
+#endif /* (SRSS_ALTLF_PRESENT == 1U) */
+#if (SRSS_PILO_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
+#endif /* (SRSS_PILO_PRESENT == 1U) */
+
+
+/*******************************************************************************
+* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
+*******************************************************************************/
+#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL)
+#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
+#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL)
+
+void Cy_Platform_Init(void);
+
+/*******************************************************************************
+* Function Name: SystemInit
+****************************************************************************//**
+*
+* Initializes the system:
+* - Restores FLL registers to the default state.
+* - Unlocks and disables WDT.
+* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref SystemCoreClockUpdate().
+*
+*******************************************************************************/
+void SystemInit(void)
+{
+ Cy_PDL_Init(CY_DEVICE_CFG);
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern const cy_israddress __Vectors[]; /* Vector Table in flash */;
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+ /* Restore FLL registers to the default state as they are not restored by the ROM code */
+ uint32_t copy = SRSS->CLK_FLL_CONFIG;
+ copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
+ SRSS->CLK_FLL_CONFIG = copy;
+
+ copy = SRSS->CLK_ROOT_SELECT[0u];
+ copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
+ SRSS->CLK_ROOT_SELECT[0u] = copy;
+
+ SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
+ SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
+ SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
+ SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
+
+ /* Unlock and disable WDT */
+ Cy_WDT_Unlock();
+ Cy_WDT_Disable();
+
+ Cy_SystemInit();
+ SystemCoreClockUpdate();
+
+#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
+ if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
+ {
+ /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
+ IPC_STRUCT7->DATA = 0UL;
+ /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
+ IPC_STRUCT7->RELEASE = 0UL;
+ }
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup. Once project compiled as part of
+* the PSoC Creator project, the Cy_SystemInit() function is generated by the
+* PSoC Creator.
+*
+* The function generated by PSoC Creator performs all of the necessary device
+* configuration based on the design settings. This includes settings from the
+* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
+* configuration that is necessary.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+ /* Empty weak function. The actual implementation to be in the PSoC Creator
+ * generated strong function.
+ */
+}
+
+
+/*******************************************************************************
+* Function Name: SystemCoreClockUpdate
+****************************************************************************//**
+*
+* Gets core clock frequency and updates \ref SystemCoreClock, \ref
+* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
+*
+* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
+* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
+*
+*******************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+ uint32_t srcFreqHz;
+ uint32_t pathFreqHz;
+ uint32_t slowClkDiv;
+ uint32_t periClkDiv;
+ uint32_t rootPath;
+ uint32_t srcClk;
+
+ /* Get root path clock for the high-frequency clock # 0 */
+ rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
+
+ /* Get source of the root path clock */
+ srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
+
+ /* Get frequency of the source */
+ switch (srcClk)
+ {
+ case CY_ROOT_PATH_SRC_IMO:
+ srcFreqHz = CY_CLK_IMO_FREQ_HZ;
+ break;
+
+ case CY_ROOT_PATH_SRC_EXT:
+ srcFreqHz = CY_CLK_EXT_FREQ_HZ;
+ break;
+
+ #if (SRSS_ECO_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_ECO:
+ srcFreqHz = CY_CLK_ECO_FREQ_HZ;
+ break;
+ #endif /* (SRSS_ECO_PRESENT == 1U) */
+
+#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_ALTHF:
+ srcFreqHz = cy_BleEcoClockFreqHz;
+ break;
+#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
+
+ case CY_ROOT_PATH_SRC_DSI_MUX:
+ {
+ uint32_t dsi_src;
+ dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
+ switch (dsi_src)
+ {
+ case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
+ srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
+ break;
+
+ case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
+ srcFreqHz = CY_CLK_WCO_FREQ_HZ;
+ break;
+
+ #if (SRSS_ALTLF_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
+ srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
+ break;
+ #endif /* (SRSS_ALTLF_PRESENT == 1U) */
+
+ #if (SRSS_PILO_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
+ srcFreqHz = CY_CLK_PILO_FREQ_HZ;
+ break;
+ #endif /* (SRSS_PILO_PRESENT == 1U) */
+
+ default:
+ srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
+ break;
+ }
+ }
+ break;
+
+ default:
+ srcFreqHz = CY_CLK_EXT_FREQ_HZ;
+ break;
+ }
+
+ if (rootPath == 0UL)
+ {
+ /* FLL */
+ bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
+ bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
+ bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
+ (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
+ if ((fllOutputAuto && fllLocked) || fllOutputOutput)
+ {
+ uint32_t fllMult;
+ uint32_t refDiv;
+ uint32_t outputDiv;
+
+ fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
+ refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
+ outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
+
+ pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
+ }
+ else
+ {
+ pathFreqHz = srcFreqHz;
+ }
+ }
+ else if ((rootPath == 1UL) || (rootPath == 2UL))
+ {
+ /* PLL */
+ bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
+ bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
+ bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
+ (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
+ if ((pllOutputAuto && pllLocked) || pllOutputOutput)
+ {
+ uint32_t feedbackDiv;
+ uint32_t referenceDiv;
+ uint32_t outputDiv;
+
+ feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
+ referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
+ outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
+
+ pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
+
+ }
+ else
+ {
+ pathFreqHz = srcFreqHz;
+ }
+ }
+ else
+ {
+ /* Direct */
+ pathFreqHz = srcFreqHz;
+ }
+
+ /* Get frequency after hf_clk pre-divider */
+ pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
+ cy_Hfclk0FreqHz = pathFreqHz;
+
+ /* Slow Clock Divider */
+ slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL);
+
+ /* Peripheral Clock Divider */
+ periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
+
+ pathFreqHz = pathFreqHz / periClkDiv;
+ cy_PeriClkFreqHz = pathFreqHz;
+ pathFreqHz = pathFreqHz / slowClkDiv;
+ SystemCoreClock = pathFreqHz;
+
+ /* Sets clock frequency for Delay API */
+ cy_delayFreqHz = SystemCoreClock;
+ cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
+ cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
+ cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
+}
+
+
+#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Function Name: Cy_SysGetCM4Status
+****************************************************************************//**
+*
+* Returns the Cortex-M4 core power mode.
+*
+* \return \ref group_system_config_cm4_status_macro
+*
+*******************************************************************************/
+uint32_t Cy_SysGetCM4Status(void)
+{
+ uint32_t regValue;
+
+ /* Get current power mode */
+ regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
+
+ return (regValue);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysEnableCM4
+****************************************************************************//**
+*
+* Sets vector table base address and enables the Cortex-M4 core.
+*
+* \note If the CPU is already enabled, it is reset and then enabled.
+*
+* \param vectorTableOffset The offset of the vector table base address from
+* memory address 0x00000000. The offset should be multiple to 1024 bytes.
+*
+*******************************************************************************/
+void Cy_SysEnableCM4(uint32_t vectorTableOffset)
+{
+ uint32_t regValue;
+ uint32_t interruptState;
+ uint32_t cpuState;
+
+ CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ cpuState = Cy_SysGetCM4Status();
+ if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
+ {
+ Cy_SysResetCM4();
+ }
+
+ CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_ENABLED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysDisableCM4
+****************************************************************************//**
+*
+* Disables the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
+* CPU.
+*
+*******************************************************************************/
+void Cy_SysDisableCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_DISABLED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysRetainCM4
+****************************************************************************//**
+*
+* Retains the Cortex-M4 core and exists without waiting for the mode to take
+* effect.
+*
+* \note The retained mode can be entered only from the enabled mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysRetainCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_RETAINED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysResetCM4
+****************************************************************************//**
+*
+* Resets the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \note The reset mode can not be entered from the retained mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysResetCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_RESET;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
+
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) && !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+/*******************************************************************************
+* Function Name: Cy_SysIpcPipeIsrCm0
+****************************************************************************//**
+*
+* This is the interrupt service routine for the system pipe.
+*
+*******************************************************************************/
+void Cy_SysIpcPipeIsrCm0(void)
+{
+ Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR);
+}
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_MemorySymbols
+****************************************************************************//**
+*
+* The intention of the function is to declare boundaries of the memories for the
+* MDK compilers. For the rest of the supported compilers, this is done using
+* linker configuration files. The following symbols used by the cymcuelftool.
+*
+*******************************************************************************/
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
+__asm void Cy_MemorySymbols(void)
+{
+ /* Flash */
+ EXPORT __cy_memory_0_start
+ EXPORT __cy_memory_0_length
+ EXPORT __cy_memory_0_row_size
+
+ /* Working Flash */
+ EXPORT __cy_memory_1_start
+ EXPORT __cy_memory_1_length
+ EXPORT __cy_memory_1_row_size
+
+ /* Supervisory Flash */
+ EXPORT __cy_memory_2_start
+ EXPORT __cy_memory_2_length
+ EXPORT __cy_memory_2_row_size
+
+ /* XIP */
+ EXPORT __cy_memory_3_start
+ EXPORT __cy_memory_3_length
+ EXPORT __cy_memory_3_row_size
+
+ /* eFuse */
+ EXPORT __cy_memory_4_start
+ EXPORT __cy_memory_4_length
+ EXPORT __cy_memory_4_row_size
+
+ /* Flash */
+__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
+__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
+__cy_memory_0_row_size EQU 0x200
+
+ /* Flash region for EEPROM emulation */
+__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
+__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
+__cy_memory_1_row_size EQU 0x200
+
+ /* Supervisory Flash */
+__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
+__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
+__cy_memory_2_row_size EQU 0x200
+
+ /* XIP */
+__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
+__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
+__cy_memory_3_row_size EQU 0x200
+
+ /* eFuse */
+__cy_memory_4_start EQU __cpp(0x90700000)
+__cy_memory_4_length EQU __cpp(0x100000)
+__cy_memory_4_row_size EQU __cpp(1)
+}
+#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
+
+
+/*******************************************************************************
+* Function Name: Cy_Platform_Init
+****************************************************************************//**
+*
+* CM0 custom HW initialization
+*
+*******************************************************************************/
+void Cy_Platform_Init(void)
+{
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ /* Initialize semaphores for the system operations.*/
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ /********************************************************************************
+ *
+ * Initializes the system pipes. The system pipes are used by BLE and Flash.
+ *
+ * If the default startup file is not used, or SystemInit() is not called in your
+ * project, call the following three functions prior to executing any flash or
+ * EmEEPROM write or erase operation:
+ * -# Cy_IPC_Sema_Init()
+ * -# Cy_IPC_Pipe_Config()
+ * -# Cy_IPC_Pipe_Init()
+ * -# Cy_Flash_Init()
+ *
+ *******************************************************************************/
+
+ /* Create an array of endpoint structures */
+ static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
+
+ Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
+
+ static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
+
+ static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
+ {
+ /* .ep0ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
+ /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
+ },
+ /* .ep1ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
+ /* .ipcNotifierMuxNumber */ 0u,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
+ },
+ /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
+ /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
+ /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
+ };
+
+ if (cy_device->flashPipeRequired != 0u)
+ {
+ Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
+ }
+
+#if defined(CY_DEVICE_PSOC6ABLE2)
+ Cy_Flash_Init();
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+
+ return;
+}
+
+#ifdef BL2
+/* Flash device name must be specified by target */
+extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
+
+uint32_t bl2_platform_init(void)
+{
+ Cy_PDL_Init(CY_DEVICE_CFG);
+
+ init_cycfg_all();
+ Cy_Platform_Init();
+
+ /* make sure CM4 is disabled */
+ if (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status()) {
+ Cy_SysDisableCM4();
+ }
+
+ return FLASH_DEV_NAME.Initialize(NULL);
+}
+#endif
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Device/Source/system_psoc6_cm4.c b/platform/ext/target/psoc64/Device/Source/system_psoc6_cm4.c
new file mode 100644
index 0000000000..b56bd5630e
--- /dev/null
+++ b/platform/ext/target/psoc64/Device/Source/system_psoc6_cm4.c
@@ -0,0 +1,587 @@
+/***************************************************************************//**
+* \file system_psoc6_cm4.c
+* \version 2.60
+*
+* The device system-source file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdbool.h>
+#include "system_psoc6.h"
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include "cy_wdt.h"
+#include "cycfg.h"
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ #include "cy_ipc_sema.h"
+ #include "cy_ipc_pipe.h"
+ #include "cy_ipc_drv.h"
+
+ #if defined(CY_DEVICE_PSOC6ABLE2)
+ #include "cy_flash.h"
+ #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#include "target_cfg.h"
+#include "Driver_USART.h"
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
+
+/** Default SlowClk system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
+
+/** IMO frequency in Hz */
+#define CY_CLK_IMO_FREQ_HZ (8000000UL)
+
+/** HVILO frequency in Hz */
+#define CY_CLK_HVILO_FREQ_HZ (32000UL)
+
+/** PILO frequency in Hz */
+#define CY_CLK_PILO_FREQ_HZ (32768UL)
+
+/** WCO frequency in Hz */
+#define CY_CLK_WCO_FREQ_HZ (32768UL)
+
+/** ALTLF frequency in Hz */
+#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
+
+
+/**
+* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
+* which is the system clock frequency supplied to the SysTick timer and the
+* processor core clock.
+* This variable implements CMSIS Core global variable.
+* Refer to the [CMSIS documentation]
+* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
+* for more details.
+* This variable can be used by debuggers to query the frequency
+* of the debug timer or to configure the trace clock speed.
+*
+* \attention Compilers must be configured to avoid removing this variable in case
+* the application program is not using it. Debugging systems require the variable
+* to be physically present in memory so that it can be examined to configure the debugger. */
+uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
+
+/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
+#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
+ uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
+#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
+
+/* SCB->CPACR */
+#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
+
+
+/*******************************************************************************
+* SystemInit()
+*******************************************************************************/
+
+/* CLK_FLL_CONFIG default values */
+#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
+#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
+#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
+#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
+#define CY_DELAY_1K_THRESHOLD (1000u)
+#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
+#define CY_DELAY_1M_THRESHOLD (1000000u)
+#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
+uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
+ CY_DELAY_1K_THRESHOLD;
+
+uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
+ CY_DELAY_1M_THRESHOLD);
+
+uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
+ ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
+
+#define CY_ROOT_PATH_SRC_IMO (0UL)
+#define CY_ROOT_PATH_SRC_EXT (1UL)
+#if (SRSS_ECO_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_ECO (2UL)
+#endif /* (SRSS_ECO_PRESENT == 1U) */
+#if (SRSS_ALTHF_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_ALTHF (3UL)
+#endif /* (SRSS_ALTHF_PRESENT == 1U) */
+#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
+#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
+#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
+#if (SRSS_ALTLF_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
+#endif /* (SRSS_ALTLF_PRESENT == 1U) */
+#if (SRSS_PILO_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
+#endif /* (SRSS_PILO_PRESENT == 1U) */
+
+
+/*******************************************************************************
+* Function Name: SystemInit
+****************************************************************************//**
+* \cond
+* Initializes the system:
+* - Restores FLL registers to the default state for single core devices.
+* - Unlocks and disables WDT.
+* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref SystemCoreClockUpdate().
+* \endcond
+*******************************************************************************/
+void SystemInit(void)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern const cy_israddress __Vectors[]; /* Vector Table in flash */
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+ /*
+ * FIXME:
+ * Even if __FPU_USED is undefined or cleared, FP registers are still
+ * accessed inside armclang library. Not sure about why armclang doesn't
+ * care about the __FPU_USED.
+ */
+ SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
+
+#ifdef __CM0P_PRESENT
+ #if (__CM0P_PRESENT == 0)
+ /* Restore FLL registers to the default state as they are not restored by the ROM code */
+ uint32_t copy = SRSS->CLK_FLL_CONFIG;
+ copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
+ SRSS->CLK_FLL_CONFIG = copy;
+
+ copy = SRSS->CLK_ROOT_SELECT[0u];
+ copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
+ SRSS->CLK_ROOT_SELECT[0u] = copy;
+
+ SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
+ SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
+ SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
+ SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
+
+ /* Unlock and disable WDT */
+ Cy_WDT_Unlock();
+ Cy_WDT_Disable();
+ #endif /* (__CM0P_PRESENT == 0) */
+#endif /* __CM0P_PRESENT */
+
+ Cy_SystemInit();
+ SystemCoreClockUpdate();
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup. Once project compiled as part of
+* the PSoC Creator project, the Cy_SystemInit() function is generated by the
+* PSoC Creator.
+*
+* The function generated by PSoC Creator performs all of the necessary device
+* configuration based on the design settings. This includes settings from the
+* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
+* configuration that is necessary.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+ /* Empty weak function. The actual implementation to be in the PSoC Creator
+ * generated strong function.
+ */
+}
+
+
+/*******************************************************************************
+* Function Name: SystemCoreClockUpdate
+****************************************************************************//**
+*
+* Gets core clock frequency and updates \ref SystemCoreClock, \ref
+* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
+*
+* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
+* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
+*
+*******************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+ uint32_t srcFreqHz;
+ uint32_t pathFreqHz;
+ uint32_t fastClkDiv;
+ uint32_t periClkDiv;
+ uint32_t rootPath;
+ uint32_t srcClk;
+
+ /* Get root path clock for the high-frequency clock # 0 */
+ rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
+
+ /* Get source of the root path clock */
+ srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
+
+ /* Get frequency of the source */
+ switch (srcClk)
+ {
+ case CY_ROOT_PATH_SRC_IMO:
+ srcFreqHz = CY_CLK_IMO_FREQ_HZ;
+ break;
+
+ case CY_ROOT_PATH_SRC_EXT:
+ srcFreqHz = CY_CLK_EXT_FREQ_HZ;
+ break;
+
+ #if (SRSS_ECO_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_ECO:
+ srcFreqHz = CY_CLK_ECO_FREQ_HZ;
+ break;
+ #endif /* (SRSS_ECO_PRESENT == 1U) */
+
+#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_ALTHF:
+ srcFreqHz = cy_BleEcoClockFreqHz;
+ break;
+#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
+
+ case CY_ROOT_PATH_SRC_DSI_MUX:
+ {
+ uint32_t dsi_src;
+ dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
+ switch (dsi_src)
+ {
+ case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
+ srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
+ break;
+
+ case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
+ srcFreqHz = CY_CLK_WCO_FREQ_HZ;
+ break;
+
+ #if (SRSS_ALTLF_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
+ srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
+ break;
+ #endif /* (SRSS_ALTLF_PRESENT == 1U) */
+
+ #if (SRSS_PILO_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
+ srcFreqHz = CY_CLK_PILO_FREQ_HZ;
+ break;
+ #endif /* (SRSS_PILO_PRESENT == 1U) */
+
+ default:
+ srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
+ break;
+ }
+ }
+ break;
+
+ default:
+ srcFreqHz = CY_CLK_EXT_FREQ_HZ;
+ break;
+ }
+
+ if (rootPath == 0UL)
+ {
+ /* FLL */
+ bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
+ bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
+ bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
+ (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
+ if ((fllOutputAuto && fllLocked) || fllOutputOutput)
+ {
+ uint32_t fllMult;
+ uint32_t refDiv;
+ uint32_t outputDiv;
+
+ fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
+ refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
+ outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
+
+ pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
+ }
+ else
+ {
+ pathFreqHz = srcFreqHz;
+ }
+ }
+ else if ((rootPath == 1UL) || (rootPath == 2UL))
+ {
+ /* PLL */
+ bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
+ bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
+ bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
+ (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
+ if ((pllOutputAuto && pllLocked) || pllOutputOutput)
+ {
+ uint32_t feedbackDiv;
+ uint32_t referenceDiv;
+ uint32_t outputDiv;
+
+ feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
+ referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
+ outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
+
+ pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
+
+ }
+ else
+ {
+ pathFreqHz = srcFreqHz;
+ }
+ }
+ else
+ {
+ /* Direct */
+ pathFreqHz = srcFreqHz;
+ }
+
+ /* Get frequency after hf_clk pre-divider */
+ pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
+ cy_Hfclk0FreqHz = pathFreqHz;
+
+ /* Fast Clock Divider */
+ fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
+
+ /* Peripheral Clock Divider */
+ periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
+ cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
+
+ pathFreqHz = pathFreqHz / fastClkDiv;
+ SystemCoreClock = pathFreqHz;
+
+ /* Sets clock frequency for Delay API */
+ cy_delayFreqHz = SystemCoreClock;
+ cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
+ cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
+ cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInitFpuEnable
+****************************************************************************//**
+*
+* Enables the FPU if it is used. The function is called from the startup file.
+*
+*******************************************************************************/
+void Cy_SystemInitFpuEnable(void)
+{
+ #if defined (__FPU_USED) && (__FPU_USED == 1U)
+ uint32_t interruptState;
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
+ __DSB();
+ __ISB();
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ #endif /* (__FPU_USED) && (__FPU_USED == 1U) */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MemorySymbols
+****************************************************************************//**
+*
+* The intention of the function is to declare boundaries of the memories for the
+* MDK compilers. For the rest of the supported compilers, this is done using
+* linker configuration files. The following symbols used by the cymcuelftool.
+*
+*******************************************************************************/
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
+__asm void Cy_MemorySymbols(void)
+{
+ /* Flash */
+ EXPORT __cy_memory_0_start
+ EXPORT __cy_memory_0_length
+ EXPORT __cy_memory_0_row_size
+
+ /* Working Flash */
+ EXPORT __cy_memory_1_start
+ EXPORT __cy_memory_1_length
+ EXPORT __cy_memory_1_row_size
+
+ /* Supervisory Flash */
+ EXPORT __cy_memory_2_start
+ EXPORT __cy_memory_2_length
+ EXPORT __cy_memory_2_row_size
+
+ /* XIP */
+ EXPORT __cy_memory_3_start
+ EXPORT __cy_memory_3_length
+ EXPORT __cy_memory_3_row_size
+
+ /* eFuse */
+ EXPORT __cy_memory_4_start
+ EXPORT __cy_memory_4_length
+ EXPORT __cy_memory_4_row_size
+
+ /* Flash */
+__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
+__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
+__cy_memory_0_row_size EQU 0x200
+
+ /* Flash region for EEPROM emulation */
+__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
+__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
+__cy_memory_1_row_size EQU 0x200
+
+ /* Supervisory Flash */
+__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
+__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
+__cy_memory_2_row_size EQU 0x200
+
+ /* XIP */
+__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
+__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
+__cy_memory_3_row_size EQU 0x200
+
+ /* eFuse */
+__cy_memory_4_start EQU __cpp(0x90700000)
+__cy_memory_4_length EQU __cpp(0x100000)
+__cy_memory_4_row_size EQU __cpp(1)
+}
+#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
+
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) && !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+/*******************************************************************************
+* Function Name: Cy_SysIpcPipeIsrCm4
+****************************************************************************//**
+*
+* This is the interrupt service routine for the system pipe.
+*
+*******************************************************************************/
+void Cy_SysIpcPipeIsrCm4(void)
+{
+ Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR);
+}
+#endif
+
+
+/* For UART the CMSIS driver is used */
+extern ARM_DRIVER_USART NS_DRIVER_STDIO;
+
+/*******************************************************************************
+* Function Name: Cy_Platform_Init
+****************************************************************************//**
+*
+* CM4 custom HW initialization
+*
+*******************************************************************************/
+void Cy_Platform_Init(void)
+{
+ Cy_PDL_Init(CY_DEVICE_CFG);
+
+ (void)NS_DRIVER_STDIO.Initialize(NULL);
+ NS_DRIVER_STDIO.Control(ARM_USART_MODE_ASYNCHRONOUS, 115200);
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+#ifdef __CM0P_PRESENT
+ /* Allocate and initialize semaphores for the system operations. */
+ static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
+#else
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
+#endif /* __CM0P_PRESENT */
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ /********************************************************************************
+ *
+ * Initializes the system pipes. The system pipes are used by BLE and Flash.
+ *
+ * If the default startup file is not used, or SystemInit() is not called in your
+ * project, call the following three functions prior to executing any flash or
+ * EmEEPROM write or erase operation:
+ * -# Cy_IPC_Sema_Init()
+ * -# Cy_IPC_Pipe_Config()
+ * -# Cy_IPC_Pipe_Init()
+ * -# Cy_Flash_Init()
+ *
+ *******************************************************************************/
+ /* Create an array of endpoint structures */
+ static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
+
+ Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
+
+ static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
+
+ static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 =
+ {
+ /* .ep0ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
+ /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
+
+ },
+ /* .ep1ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
+ /* .ipcNotifierMuxNumber */ 0u,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
+ },
+ /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
+ /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
+ /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
+ };
+
+ if (cy_device->flashPipeRequired != 0u)
+ {
+ Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
+ }
+
+#if defined(CY_DEVICE_PSOC6ABLE2)
+ Cy_Flash_Init();
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+ return;
+}
+
+
+int32_t tfm_ns_platform_init (void)
+{
+ Cy_Platform_Init();
+ return ARM_DRIVER_OK;
+}
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg.c b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg.c
new file mode 100644
index 0000000000..74c28aba2c
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg.c
@@ -0,0 +1,34 @@
+/*******************************************************************************
+* File Name: cycfg.c
+*
+* Description:
+* Wrapper function to initialize all generated code.
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg.h"
+
+void init_cycfg_all(void)
+{
+ init_cycfg_clocks();
+ init_cycfg_peripherals();
+ init_cycfg_pins();
+ init_cycfg_platform();
+ init_cycfg_routing();
+}
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg.h b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg.h
new file mode 100644
index 0000000000..1709481df2
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg.h
@@ -0,0 +1,48 @@
+/*******************************************************************************
+* File Name: cycfg.h
+*
+* Description:
+* Simple wrapper header containing all generated files.
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_H)
+#define CYCFG_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+#include "cycfg_clocks.h"
+#include "cycfg_dmas.h"
+#include "cycfg_peripherals.h"
+#include "cycfg_pins.h"
+#include "cycfg_platform.h"
+#include "cycfg_routing.h"
+
+void init_cycfg_all(void);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_H */
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_clocks.c b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_clocks.c
new file mode 100644
index 0000000000..5249f7d3a0
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_clocks.c
@@ -0,0 +1,53 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.c
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_clocks.h"
+
+
+void init_cycfg_clocks(void)
+{
+ Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+
+ Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+
+ Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+
+ Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
+
+ Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 1U);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
+
+ Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 255U);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
+}
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_clocks.h b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_clocks.h
new file mode 100644
index 0000000000..0da97983ce
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_clocks.h
@@ -0,0 +1,55 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.h
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CLOCKS_H)
+#define CYCFG_CLOCKS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define peri_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT
+#define peri_0_div_16_0_NUM 0U
+#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT
+#define peri_0_div_8_0_NUM 0U
+#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT
+#define peri_0_div_8_1_NUM 1U
+#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT
+#define peri_0_div_8_2_NUM 2U
+#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
+#define peri_0_div_8_3_NUM 3U
+#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT
+#define peri_0_div_8_4_NUM 4U
+
+void init_cycfg_clocks(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CLOCKS_H */
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_dmas.c b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_dmas.c
new file mode 100644
index 0000000000..a8e9de3e06
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_dmas.c
@@ -0,0 +1,179 @@
+/*******************************************************************************
+* File Name: cycfg_dmas.c
+*
+* Description:
+* DMA configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_dmas.h"
+
+const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config =
+{
+ .retrigger = CY_DMA_RETRIG_IM,
+ .interruptType = CY_DMA_1ELEMENT,
+ .triggerOutType = CY_DMA_1ELEMENT,
+ .channelState = CY_DMA_CHANNEL_DISABLED,
+ .triggerInType = CY_DMA_1ELEMENT,
+ .dataSize = CY_DMA_BYTE,
+ .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+ .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+ .descriptorType = CY_DMA_1D_TRANSFER,
+ .srcAddress = NULL,
+ .dstAddress = NULL,
+ .srcXincrement = 0,
+ .dstXincrement = 1,
+ .xCount = 6,
+ .srcYincrement = 0,
+ .dstYincrement = 0,
+ .yCount = 1,
+ .nextDescriptor = NULL,
+};
+cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0 =
+{
+ .ctl = 0UL,
+ .src = 0UL,
+ .dst = 0UL,
+ .xCtl = 0UL,
+ .yCtl = 0UL,
+ .nextPtr = 0UL,
+};
+const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig =
+{
+ .descriptor = &cpuss_0_dw0_0_chan_0_Descriptor_0,
+ .preemptable = true,
+ .priority = 1,
+ .enable = false,
+ .bufferable = false,
+};
+const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config =
+{
+ .retrigger = CY_DMA_RETRIG_16CYC,
+ .interruptType = CY_DMA_1ELEMENT,
+ .triggerOutType = CY_DMA_1ELEMENT,
+ .channelState = CY_DMA_CHANNEL_DISABLED,
+ .triggerInType = CY_DMA_1ELEMENT,
+ .dataSize = CY_DMA_BYTE,
+ .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+ .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+ .descriptorType = CY_DMA_1D_TRANSFER,
+ .srcAddress = NULL,
+ .dstAddress = NULL,
+ .srcXincrement = 1,
+ .dstXincrement = 0,
+ .xCount = 5,
+ .srcYincrement = 0,
+ .dstYincrement = 0,
+ .yCount = 1,
+ .nextDescriptor = NULL,
+};
+cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0 =
+{
+ .ctl = 0UL,
+ .src = 0UL,
+ .dst = 0UL,
+ .xCtl = 0UL,
+ .yCtl = 0UL,
+ .nextPtr = 0UL,
+};
+const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig =
+{
+ .descriptor = &cpuss_0_dw0_0_chan_1_Descriptor_0,
+ .preemptable = true,
+ .priority = 1,
+ .enable = false,
+ .bufferable = false,
+};
+const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config =
+{
+ .retrigger = CY_DMA_RETRIG_4CYC,
+ .interruptType = CY_DMA_DESCR,
+ .triggerOutType = CY_DMA_1ELEMENT,
+ .channelState = CY_DMA_CHANNEL_DISABLED,
+ .triggerInType = CY_DMA_X_LOOP,
+ .dataSize = CY_DMA_HALFWORD,
+ .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+ .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+ .descriptorType = CY_DMA_2D_TRANSFER,
+ .srcAddress = NULL,
+ .dstAddress = NULL,
+ .srcXincrement = 2,
+ .dstXincrement = 0,
+ .xCount = 10,
+ .srcYincrement = 10,
+ .dstYincrement = 0,
+ .yCount = 2,
+ .nextDescriptor = NULL,
+};
+cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0 =
+{
+ .ctl = 0UL,
+ .src = 0UL,
+ .dst = 0UL,
+ .xCtl = 0UL,
+ .yCtl = 0UL,
+ .nextPtr = 0UL,
+};
+const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig =
+{
+ .descriptor = &cpuss_0_dw1_0_chan_1_Descriptor_0,
+ .preemptable = false,
+ .priority = 0,
+ .enable = false,
+ .bufferable = false,
+};
+const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config =
+{
+ .retrigger = CY_DMA_RETRIG_IM,
+ .interruptType = CY_DMA_DESCR,
+ .triggerOutType = CY_DMA_1ELEMENT,
+ .channelState = CY_DMA_CHANNEL_DISABLED,
+ .triggerInType = CY_DMA_X_LOOP,
+ .dataSize = CY_DMA_HALFWORD,
+ .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+ .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+ .descriptorType = CY_DMA_2D_TRANSFER,
+ .srcAddress = NULL,
+ .dstAddress = NULL,
+ .srcXincrement = 0,
+ .dstXincrement = 2,
+ .xCount = 10,
+ .srcYincrement = 0,
+ .dstYincrement = 10,
+ .yCount = 2,
+ .nextDescriptor = NULL,
+};
+cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0 =
+{
+ .ctl = 0UL,
+ .src = 0UL,
+ .dst = 0UL,
+ .xCtl = 0UL,
+ .yCtl = 0UL,
+ .nextPtr = 0UL,
+};
+const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig =
+{
+ .descriptor = &cpuss_0_dw1_0_chan_3_Descriptor_0,
+ .preemptable = false,
+ .priority = 0,
+ .enable = false,
+ .bufferable = false,
+};
+
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_dmas.h b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_dmas.h
new file mode 100644
index 0000000000..c68d4b9ec8
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_dmas.h
@@ -0,0 +1,67 @@
+/*******************************************************************************
+* File Name: cycfg_dmas.h
+*
+* Description:
+* DMA configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_DMAS_H)
+#define CYCFG_DMAS_H
+
+#include "cycfg_notices.h"
+#include "cy_dma.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define cpuss_0_dw0_0_chan_0_HW DW0
+#define cpuss_0_dw0_0_chan_0_CHANNEL 0
+#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
+#define cpuss_0_dw0_0_chan_1_HW DW0
+#define cpuss_0_dw0_0_chan_1_CHANNEL 1
+#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
+#define cpuss_0_dw1_0_chan_1_HW DW1
+#define cpuss_0_dw1_0_chan_1_CHANNEL 1
+#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
+#define cpuss_0_dw1_0_chan_3_HW DW1
+#define cpuss_0_dw1_0_chan_3_CHANNEL 3
+#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
+
+extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config;
+extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0;
+extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig;
+extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config;
+extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0;
+extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig;
+extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config;
+extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0;
+extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig;
+extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config;
+extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0;
+extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig;
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_DMAS_H */
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_notices.h b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_notices.h
new file mode 100644
index 0000000000..90f1013f8a
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_notices.h
@@ -0,0 +1,30 @@
+/*******************************************************************************
+* File Name: cycfg_notices.h
+*
+* Description:
+* Contains warnings and errors that occurred while generating code for the
+* design.
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_NOTICES_H)
+#define CYCFG_NOTICES_H
+
+
+#endif /* CYCFG_NOTICES_H */
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_peripherals.c b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_peripherals.c
new file mode 100644
index 0000000000..67b745f805
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_peripherals.c
@@ -0,0 +1,204 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.c
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_peripherals.h"
+
+#define PWM_INPUT_DISABLED 0x7U
+#define USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x2U) | \
+ CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
+ CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
+ CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
+ CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
+ CY_USBFS_DEV_DRV_SET_EP1_LVL(0x2U) | \
+ CY_USBFS_DEV_DRV_SET_EP2_LVL(0x2U) | \
+ CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
+ CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
+ CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
+ CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
+ CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
+ CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
+
+cy_stc_csd_context_t cy_csd_0_context =
+{
+ .lockKey = CY_CSD_NONE_KEY,
+};
+const cy_stc_scb_uart_config_t BT_UART_config =
+{
+ .uartMode = CY_SCB_UART_STANDARD,
+ .enableMutliProcessorMode = false,
+ .smartCardRetryOnNack = false,
+ .irdaInvertRx = false,
+ .irdaEnableLowPowerReceiver = false,
+ .oversample = 8,
+ .enableMsbFirst = false,
+ .dataWidth = 8UL,
+ .parity = CY_SCB_UART_PARITY_NONE,
+ .stopBits = CY_SCB_UART_STOP_BITS_1,
+ .enableInputFilter = false,
+ .breakWidth = 11UL,
+ .dropOnFrameError = false,
+ .dropOnParityError = false,
+ .receiverAddress = 0x0UL,
+ .receiverAddressMask = 0x0UL,
+ .acceptAddrInFifo = false,
+ .enableCts = true,
+ .ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rtsRxFifoLevel = 63,
+ .rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rxFifoTriggerLevel = 1UL,
+ .rxFifoIntEnableMask = 0UL,
+ .txFifoTriggerLevel = 63UL,
+ .txFifoIntEnableMask = 0UL,
+};
+const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
+{
+ .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
+ .slaveAddress1 = 8U,
+ .slaveAddress2 = 0U,
+ .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
+ .enableWakeFromSleep = false,
+};
+const cy_stc_scb_uart_config_t KITPROG_UART_config =
+{
+ .uartMode = CY_SCB_UART_STANDARD,
+ .enableMutliProcessorMode = false,
+ .smartCardRetryOnNack = false,
+ .irdaInvertRx = false,
+ .irdaEnableLowPowerReceiver = false,
+ .oversample = 8,
+ .enableMsbFirst = false,
+ .dataWidth = 8UL,
+ .parity = CY_SCB_UART_PARITY_NONE,
+ .stopBits = CY_SCB_UART_STOP_BITS_1,
+ .enableInputFilter = false,
+ .breakWidth = 11UL,
+ .dropOnFrameError = false,
+ .dropOnParityError = false,
+ .receiverAddress = 0x0UL,
+ .receiverAddressMask = 0x0UL,
+ .acceptAddrInFifo = false,
+ .enableCts = false,
+ .ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rtsRxFifoLevel = 0UL,
+ .rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rxFifoTriggerLevel = 63UL,
+ .rxFifoIntEnableMask = 0UL,
+ .txFifoTriggerLevel = 63UL,
+ .txFifoIntEnableMask = 0UL,
+};
+const cy_stc_smif_config_t QSPI_config =
+{
+ .mode = (uint32_t)CY_SMIF_NORMAL,
+ .deselectDelay = QSPI_DESELECT_DELAY,
+ .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
+ .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
+};
+const cy_stc_mcwdt_config_t MCWDT0_config =
+{
+ .c0Match = 32768U,
+ .c1Match = 32768U,
+ .c0Mode = CY_MCWDT_MODE_NONE,
+ .c1Mode = CY_MCWDT_MODE_NONE,
+ .c2ToggleBit = 16U,
+ .c2Mode = CY_MCWDT_MODE_NONE,
+ .c0ClearOnMatch = false,
+ .c1ClearOnMatch = false,
+ .c0c1Cascade = true,
+ .c1c2Cascade = false,
+};
+const cy_stc_rtc_config_t RTC_config =
+{
+ .sec = 0U,
+ .min = 0U,
+ .hour = 12U,
+ .amPm = CY_RTC_AM,
+ .hrFormat = CY_RTC_24_HOURS,
+ .dayOfWeek = CY_RTC_SUNDAY,
+ .date = 1U,
+ .month = CY_RTC_JANUARY,
+ .year = 0U,
+};
+const cy_stc_tcpwm_pwm_config_t PWM_config =
+{
+ .pwmMode = CY_TCPWM_PWM_MODE_PWM,
+ .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1,
+ .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN,
+ .deadTimeClocks = 0,
+ .runMode = CY_TCPWM_PWM_CONTINUOUS,
+ .period0 = 32000,
+ .period1 = 32768,
+ .enablePeriodSwap = false,
+ .compare0 = 16384,
+ .compare1 = 16384,
+ .enableCompareSwap = false,
+ .interruptSources = CY_TCPWM_INT_NONE,
+ .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE,
+ .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE,
+ .killMode = CY_TCPWM_PWM_STOP_ON_KILL,
+ .swapInputMode = PWM_INPUT_DISABLED & 0x3U,
+ .swapInput = CY_TCPWM_INPUT_0,
+ .reloadInputMode = PWM_INPUT_DISABLED & 0x3U,
+ .reloadInput = CY_TCPWM_INPUT_0,
+ .startInputMode = PWM_INPUT_DISABLED & 0x3U,
+ .startInput = CY_TCPWM_INPUT_0,
+ .killInputMode = PWM_INPUT_DISABLED & 0x3U,
+ .killInput = CY_TCPWM_INPUT_0,
+ .countInputMode = PWM_INPUT_DISABLED & 0x3U,
+ .countInput = CY_TCPWM_INPUT_1,
+};
+const cy_stc_usbfs_dev_drv_config_t USBUART_config =
+{
+ .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
+ .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
+ .epBuffer = NULL,
+ .epBufferSize = 0U,
+ .dmaConfig[0] = NULL,
+ .dmaConfig[1] = NULL,
+ .dmaConfig[2] = NULL,
+ .dmaConfig[3] = NULL,
+ .dmaConfig[4] = NULL,
+ .dmaConfig[5] = NULL,
+ .dmaConfig[6] = NULL,
+ .dmaConfig[7] = NULL,
+ .enableLpm = false,
+ .intrLevelSel = USBUART_INTR_LVL_SEL,
+};
+
+
+void init_cycfg_peripherals(void)
+{
+ Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
+
+ Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
+
+ Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
+
+ Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
+
+ Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM1_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 3U);
+
+ Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u);
+
+ Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
+}
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_peripherals.h b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_peripherals.h
new file mode 100644
index 0000000000..beadadac39
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_peripherals.h
@@ -0,0 +1,140 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.h
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PERIPHERALS_H)
+#define CYCFG_PERIPHERALS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_csd.h"
+#include "cy_scb_uart.h"
+#include "cy_scb_ezi2c.h"
+#include "cy_smif.h"
+#include "cy_mcwdt.h"
+#include "cy_rtc.h"
+#include "cy_tcpwm_pwm.h"
+#include "cycfg_routing.h"
+#include "cy_usbfs_dev_drv.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CY_CAPSENSE_CORE 4u
+#define CY_CAPSENSE_CPU_CLK 100000000u
+#define CY_CAPSENSE_PERI_CLK 100000000u
+#define CY_CAPSENSE_VDDA_MV 3300u
+#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
+#define CY_CAPSENSE_PERI_DIV_INDEX 4u
+#define Cmod_PORT GPIO_PRT7
+#define CintA_PORT GPIO_PRT7
+#define CintB_PORT GPIO_PRT7
+#define Button0_Rx0_PORT GPIO_PRT8
+#define Button0_Tx_PORT GPIO_PRT1
+#define Button1_Rx0_PORT GPIO_PRT8
+#define Button1_Tx_PORT GPIO_PRT1
+#define LinearSlider0_Sns0_PORT GPIO_PRT8
+#define LinearSlider0_Sns1_PORT GPIO_PRT8
+#define LinearSlider0_Sns2_PORT GPIO_PRT8
+#define LinearSlider0_Sns3_PORT GPIO_PRT8
+#define LinearSlider0_Sns4_PORT GPIO_PRT8
+#define Cmod_PIN 7u
+#define CintA_PIN 1u
+#define CintB_PIN 2u
+#define Button0_Rx0_PIN 1u
+#define Button0_Tx_PIN 0u
+#define Button1_Rx0_PIN 2u
+#define Button1_Tx_PIN 0u
+#define LinearSlider0_Sns0_PIN 3u
+#define LinearSlider0_Sns1_PIN 4u
+#define LinearSlider0_Sns2_PIN 5u
+#define LinearSlider0_Sns3_PIN 6u
+#define LinearSlider0_Sns4_PIN 7u
+#define Cmod_PORT_NUM 7u
+#define CintA_PORT_NUM 7u
+#define CintB_PORT_NUM 7u
+#define CapSense_HW CSD0
+#define CapSense_IRQ csd_interrupt_IRQn
+#define BT_UART_HW SCB2
+#define BT_UART_IRQ scb_2_interrupt_IRQn
+#define CSD_COMM_HW SCB3
+#define CSD_COMM_IRQ scb_3_interrupt_IRQn
+#define KITPROG_UART_HW SCB5
+#define KITPROG_UART_IRQ scb_5_interrupt_IRQn
+#define QSPI_HW SMIF0
+#define QSPI_IRQ smif_interrupt_IRQn
+#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
+#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
+#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
+#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
+#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
+#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
+#define QSPI_DATALINES0_1 (1UL)
+#define QSPI_DATALINES2_3 (1UL)
+#define QSPI_DATALINES4_5 (0UL)
+#define QSPI_DATALINES6_7 (0UL)
+#define QSPI_SS0 (1UL)
+#define QSPI_SS1 (0UL)
+#define QSPI_SS2 (0UL)
+#define QSPI_SS3 (0UL)
+#define QSPI_DESELECT_DELAY 7
+#define MCWDT0_HW MCWDT_STRUCT0
+#define RTC_10_MONTH_OFFSET (28U)
+#define RTC_MONTH_OFFSET (24U)
+#define RTC_10_DAY_OFFSET (20U)
+#define RTC_DAY_OFFSET (16U)
+#define RTC_1000_YEAR_OFFSET (12U)
+#define RTC_100_YEAR_OFFSET (8U)
+#define RTC_10_YEAR_OFFSET (4U)
+#define RTC_YEAR_OFFSET (0U)
+#define PWM_HW TCPWM1
+#define PWM_NUM 1UL
+#define PWM_MASK (1UL << 1)
+#define USBUART_ACTIVE_ENDPOINTS_MASK 7U
+#define USBUART_ENDPOINTS_BUFFER_SIZE 140U
+#define USBUART_ENDPOINTS_ACCESS_TYPE 0U
+#define USBUART_USB_CORE 4U
+#define USBUART_HW USBFS0
+#define USBUART_HI_IRQ usb_interrupt_hi_IRQn
+#define USBUART_MED_IRQ usb_interrupt_med_IRQn
+#define USBUART_LO_IRQ usb_interrupt_lo_IRQn
+
+extern cy_stc_csd_context_t cy_csd_0_context;
+extern const cy_stc_scb_uart_config_t BT_UART_config;
+extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config;
+extern const cy_stc_scb_uart_config_t KITPROG_UART_config;
+extern const cy_stc_smif_config_t QSPI_config;
+extern const cy_stc_mcwdt_config_t MCWDT0_config;
+extern const cy_stc_rtc_config_t RTC_config;
+extern const cy_stc_tcpwm_pwm_config_t PWM_config;
+extern const cy_stc_usbfs_dev_drv_config_t USBUART_config;
+
+void init_cycfg_peripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PERIPHERALS_H */
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_pins.c b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_pins.c
new file mode 100644
index 0000000000..8fed53e210
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_pins.c
@@ -0,0 +1,883 @@
+/*******************************************************************************
+* File Name: cycfg_pins.c
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_pins.h"
+
+const cy_stc_gpio_pin_config_t WCO_IN_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = WCO_IN_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t WCO_OUT_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = WCO_OUT_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t LED_RED_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = LED_RED_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t SW2_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_PULLUP,
+ .hsiom = SW2_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t LED_BLUE_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = LED_BLUE_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t QSPI_SS0_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = QSPI_SS0_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t QSPI_DATA3_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = QSPI_DATA3_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t QSPI_DATA2_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = QSPI_DATA2_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t QSPI_DATA1_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = QSPI_DATA1_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t QSPI_DATA0_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = QSPI_DATA0_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = QSPI_SPI_CLOCK_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t LED9_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = LED9_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = ioss_0_port_14_pin_0_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = ioss_0_port_14_pin_1_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CSD_TX_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CSD_TX_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t LED_GREEN_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = LED_GREEN_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t LED8_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = LED8_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t SDHC0_DAT0_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = SDHC0_DAT0_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t SDHC0_DAT1_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = SDHC0_DAT1_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t SDHC0_DAT2_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = SDHC0_DAT2_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t SDHC0_DAT3_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = SDHC0_DAT3_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t SDHC0_CMD_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = SDHC0_CMD_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t SDHC0_CLK_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = SDHC0_CLK_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t ENABLE_WIFI_config =
+{
+ .outVal = 0,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = ENABLE_WIFI_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t BT_UART_RX_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_HIGHZ,
+ .hsiom = BT_UART_RX_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t BT_UART_TX_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = BT_UART_TX_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t BT_UART_RTS_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = BT_UART_RTS_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t BT_UART_CTS_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_HIGHZ,
+ .hsiom = BT_UART_CTS_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t BT_POWER_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF,
+ .hsiom = BT_POWER_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config =
+{
+ .outVal = 0,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = BT_HOST_WAKE_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config =
+{
+ .outVal = 0,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = BT_DEVICE_WAKE_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t UART_RX_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_HIGHZ,
+ .hsiom = UART_RX_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t UART_TX_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = UART_TX_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t EZI2C_SCL_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_OD_DRIVESLOW,
+ .hsiom = EZI2C_SCL_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t EZI2C_SDA_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_OD_DRIVESLOW,
+ .hsiom = EZI2C_SDA_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t SWO_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = SWO_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t SWDIO_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_PULLUP,
+ .hsiom = SWDIO_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t SWDCK_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_PULLDOWN,
+ .hsiom = SWDCK_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CINA_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CINA_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CINB_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CINB_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CMOD_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CMOD_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CSD_BTN0_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CSD_BTN0_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CSD_BTN1_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CSD_BTN1_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CSD_SLD0_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CSD_SLD0_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CSD_SLD1_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CSD_SLD1_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CSD_SLD2_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CSD_SLD2_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CSD_SLD3_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CSD_SLD3_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CSD_SLD4_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CSD_SLD4_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+
+
+void init_cycfg_pins(void)
+{
+ Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config);
+
+ Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config);
+
+ Cy_GPIO_Pin_Init(LED_RED_PORT, LED_RED_PIN, &LED_RED_config);
+
+ Cy_GPIO_Pin_Init(SW2_PORT, SW2_PIN, &SW2_config);
+
+ Cy_GPIO_Pin_Init(LED_BLUE_PORT, LED_BLUE_PIN, &LED_BLUE_config);
+
+ Cy_GPIO_Pin_Init(QSPI_SS0_PORT, QSPI_SS0_PIN, &QSPI_SS0_config);
+
+ Cy_GPIO_Pin_Init(QSPI_DATA3_PORT, QSPI_DATA3_PIN, &QSPI_DATA3_config);
+
+ Cy_GPIO_Pin_Init(QSPI_DATA2_PORT, QSPI_DATA2_PIN, &QSPI_DATA2_config);
+
+ Cy_GPIO_Pin_Init(QSPI_DATA1_PORT, QSPI_DATA1_PIN, &QSPI_DATA1_config);
+
+ Cy_GPIO_Pin_Init(QSPI_DATA0_PORT, QSPI_DATA0_PIN, &QSPI_DATA0_config);
+
+ Cy_GPIO_Pin_Init(QSPI_SPI_CLOCK_PORT, QSPI_SPI_CLOCK_PIN, &QSPI_SPI_CLOCK_config);
+
+ Cy_GPIO_Pin_Init(LED9_PORT, LED9_PIN, &LED9_config);
+
+ Cy_GPIO_Pin_Init(ioss_0_port_14_pin_0_PORT, ioss_0_port_14_pin_0_PIN, &ioss_0_port_14_pin_0_config);
+
+ Cy_GPIO_Pin_Init(ioss_0_port_14_pin_1_PORT, ioss_0_port_14_pin_1_PIN, &ioss_0_port_14_pin_1_config);
+
+
+ Cy_GPIO_Pin_Init(LED_GREEN_PORT, LED_GREEN_PIN, &LED_GREEN_config);
+
+ Cy_GPIO_Pin_Init(LED8_PORT, LED8_PIN, &LED8_config);
+
+ Cy_GPIO_Pin_Init(SDHC0_DAT0_PORT, SDHC0_DAT0_PIN, &SDHC0_DAT0_config);
+
+ Cy_GPIO_Pin_Init(SDHC0_DAT1_PORT, SDHC0_DAT1_PIN, &SDHC0_DAT1_config);
+
+ Cy_GPIO_Pin_Init(SDHC0_DAT2_PORT, SDHC0_DAT2_PIN, &SDHC0_DAT2_config);
+
+ Cy_GPIO_Pin_Init(SDHC0_DAT3_PORT, SDHC0_DAT3_PIN, &SDHC0_DAT3_config);
+
+ Cy_GPIO_Pin_Init(SDHC0_CMD_PORT, SDHC0_CMD_PIN, &SDHC0_CMD_config);
+
+ Cy_GPIO_Pin_Init(SDHC0_CLK_PORT, SDHC0_CLK_PIN, &SDHC0_CLK_config);
+
+ Cy_GPIO_Pin_Init(ENABLE_WIFI_PORT, ENABLE_WIFI_PIN, &ENABLE_WIFI_config);
+
+ Cy_GPIO_Pin_Init(BT_UART_RX_PORT, BT_UART_RX_PIN, &BT_UART_RX_config);
+
+ Cy_GPIO_Pin_Init(BT_UART_TX_PORT, BT_UART_TX_PIN, &BT_UART_TX_config);
+
+ Cy_GPIO_Pin_Init(BT_UART_RTS_PORT, BT_UART_RTS_PIN, &BT_UART_RTS_config);
+
+ Cy_GPIO_Pin_Init(BT_UART_CTS_PORT, BT_UART_CTS_PIN, &BT_UART_CTS_config);
+
+ Cy_GPIO_Pin_Init(BT_POWER_PORT, BT_POWER_PIN, &BT_POWER_config);
+
+ Cy_GPIO_Pin_Init(BT_HOST_WAKE_PORT, BT_HOST_WAKE_PIN, &BT_HOST_WAKE_config);
+
+ Cy_GPIO_Pin_Init(BT_DEVICE_WAKE_PORT, BT_DEVICE_WAKE_PIN, &BT_DEVICE_WAKE_config);
+
+ Cy_GPIO_Pin_Init(UART_RX_PORT, UART_RX_PIN, &UART_RX_config);
+
+ Cy_GPIO_Pin_Init(UART_TX_PORT, UART_TX_PIN, &UART_TX_config);
+
+ Cy_GPIO_Pin_Init(EZI2C_SCL_PORT, EZI2C_SCL_PIN, &EZI2C_SCL_config);
+
+ Cy_GPIO_Pin_Init(EZI2C_SDA_PORT, EZI2C_SDA_PIN, &EZI2C_SDA_config);
+
+ Cy_GPIO_Pin_Init(SWO_PORT, SWO_PIN, &SWO_config);
+
+ Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config);
+
+ Cy_GPIO_Pin_Init(SWDCK_PORT, SWDCK_PIN, &SWDCK_config);
+
+
+
+
+
+
+
+
+
+
+}
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_pins.h b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_pins.h
new file mode 100644
index 0000000000..7496d6069e
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_pins.h
@@ -0,0 +1,571 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cycfg_notices.h"
+#include "cy_gpio.h"
+#include "cycfg_routing.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define WCO_IN_PORT GPIO_PRT0
+#define WCO_IN_PIN 0U
+#define WCO_IN_NUM 0U
+#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define WCO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_0_HSIOM
+ #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#define WCO_OUT_PORT GPIO_PRT0
+#define WCO_OUT_PIN 1U
+#define WCO_OUT_NUM 1U
+#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define WCO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_1_HSIOM
+ #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#define LED_RED_PORT GPIO_PRT0
+#define LED_RED_PIN 3U
+#define LED_RED_NUM 3U
+#define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define LED_RED_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_3_HSIOM
+ #define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
+#define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
+#define SW2_PORT GPIO_PRT0
+#define SW2_PIN 4U
+#define SW2_NUM 4U
+#define SW2_DRIVEMODE CY_GPIO_DM_PULLUP
+#define SW2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_4_HSIOM
+ #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define SW2_HSIOM ioss_0_port_0_pin_4_HSIOM
+#define SW2_IRQ ioss_interrupts_gpio_0_IRQn
+#define LED_BLUE_PORT GPIO_PRT11
+#define LED_BLUE_PIN 1U
+#define LED_BLUE_NUM 1U
+#define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define LED_BLUE_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_1_HSIOM
+ #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
+#define LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
+#define QSPI_SS0_PORT GPIO_PRT11
+#define QSPI_SS0_PIN 2U
+#define QSPI_SS0_NUM 2U
+#define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define QSPI_SS0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_2_HSIOM
+ #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
+#define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
+#define QSPI_DATA3_PORT GPIO_PRT11
+#define QSPI_DATA3_PIN 3U
+#define QSPI_DATA3_NUM 3U
+#define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
+#define QSPI_DATA3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_3_HSIOM
+ #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
+#define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
+#define QSPI_DATA2_PORT GPIO_PRT11
+#define QSPI_DATA2_PIN 4U
+#define QSPI_DATA2_NUM 4U
+#define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
+#define QSPI_DATA2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_4_HSIOM
+ #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
+#define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
+#define QSPI_DATA1_PORT GPIO_PRT11
+#define QSPI_DATA1_PIN 5U
+#define QSPI_DATA1_NUM 5U
+#define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
+#define QSPI_DATA1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_5_HSIOM
+ #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
+#define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
+#define QSPI_DATA0_PORT GPIO_PRT11
+#define QSPI_DATA0_PIN 6U
+#define QSPI_DATA0_NUM 6U
+#define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
+#define QSPI_DATA0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_6_HSIOM
+ #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
+#define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
+#define QSPI_SPI_CLOCK_PORT GPIO_PRT11
+#define QSPI_SPI_CLOCK_PIN 7U
+#define QSPI_SPI_CLOCK_NUM 7U
+#define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_7_HSIOM
+ #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
+#define LED9_PORT GPIO_PRT13
+#define LED9_PIN 7U
+#define LED9_NUM 7U
+#define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define LED9_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_13_pin_7_HSIOM
+ #define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
+#define LED9_IRQ ioss_interrupts_gpio_13_IRQn
+#define ioss_0_port_14_pin_0_PORT GPIO_PRT14
+#define ioss_0_port_14_pin_0_PIN 0U
+#define ioss_0_port_14_pin_0_NUM 0U
+#define ioss_0_port_14_pin_0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define ioss_0_port_14_pin_0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_14_pin_0_HSIOM
+ #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn
+#define ioss_0_port_14_pin_1_PORT GPIO_PRT14
+#define ioss_0_port_14_pin_1_PIN 1U
+#define ioss_0_port_14_pin_1_NUM 1U
+#define ioss_0_port_14_pin_1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define ioss_0_port_14_pin_1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_14_pin_1_HSIOM
+ #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn
+#define CSD_TX_PORT GPIO_PRT1
+#define CSD_TX_PIN 0U
+#define CSD_TX_NUM 0U
+#define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CSD_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_0_HSIOM
+ #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
+#define LED_GREEN_PORT GPIO_PRT1
+#define LED_GREEN_PIN 1U
+#define LED_GREEN_NUM 1U
+#define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define LED_GREEN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_1_HSIOM
+ #define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
+#define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
+#define LED8_PORT GPIO_PRT1
+#define LED8_PIN 5U
+#define LED8_NUM 5U
+#define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define LED8_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_5_HSIOM
+ #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
+#define LED8_IRQ ioss_interrupts_gpio_1_IRQn
+#define SDHC0_DAT0_PORT GPIO_PRT2
+#define SDHC0_DAT0_PIN 0U
+#define SDHC0_DAT0_NUM 0U
+#define SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG
+#define SDHC0_DAT0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_2_pin_0_HSIOM
+ #define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM
+#define SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn
+#define SDHC0_DAT1_PORT GPIO_PRT2
+#define SDHC0_DAT1_PIN 1U
+#define SDHC0_DAT1_NUM 1U
+#define SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG
+#define SDHC0_DAT1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_2_pin_1_HSIOM
+ #define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM
+#define SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn
+#define SDHC0_DAT2_PORT GPIO_PRT2
+#define SDHC0_DAT2_PIN 2U
+#define SDHC0_DAT2_NUM 2U
+#define SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG
+#define SDHC0_DAT2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_2_pin_2_HSIOM
+ #define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM
+#define SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn
+#define SDHC0_DAT3_PORT GPIO_PRT2
+#define SDHC0_DAT3_PIN 3U
+#define SDHC0_DAT3_NUM 3U
+#define SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG
+#define SDHC0_DAT3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_2_pin_3_HSIOM
+ #define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM
+#define SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn
+#define SDHC0_CMD_PORT GPIO_PRT2
+#define SDHC0_CMD_PIN 4U
+#define SDHC0_CMD_NUM 4U
+#define SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG
+#define SDHC0_CMD_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_2_pin_4_HSIOM
+ #define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
+#define SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn
+#define SDHC0_CLK_PORT GPIO_PRT2
+#define SDHC0_CLK_PIN 5U
+#define SDHC0_CLK_NUM 5U
+#define SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define SDHC0_CLK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_2_pin_5_HSIOM
+ #define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
+#define SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn
+#define ENABLE_WIFI_PORT GPIO_PRT2
+#define ENABLE_WIFI_PIN 6U
+#define ENABLE_WIFI_NUM 6U
+#define ENABLE_WIFI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define ENABLE_WIFI_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_2_pin_6_HSIOM
+ #define ioss_0_port_2_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define ENABLE_WIFI_HSIOM ioss_0_port_2_pin_6_HSIOM
+#define ENABLE_WIFI_IRQ ioss_interrupts_gpio_2_IRQn
+#define BT_UART_RX_PORT GPIO_PRT3
+#define BT_UART_RX_PIN 0U
+#define BT_UART_RX_NUM 0U
+#define BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define BT_UART_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_0_HSIOM
+ #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
+#define BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
+#define BT_UART_TX_PORT GPIO_PRT3
+#define BT_UART_TX_PIN 1U
+#define BT_UART_TX_NUM 1U
+#define BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define BT_UART_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_1_HSIOM
+ #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
+#define BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
+#define BT_UART_RTS_PORT GPIO_PRT3
+#define BT_UART_RTS_PIN 2U
+#define BT_UART_RTS_NUM 2U
+#define BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define BT_UART_RTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_2_HSIOM
+ #define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
+#define BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
+#define BT_UART_CTS_PORT GPIO_PRT3
+#define BT_UART_CTS_PIN 3U
+#define BT_UART_CTS_NUM 3U
+#define BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define BT_UART_CTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_3_HSIOM
+ #define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
+#define BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
+#define BT_POWER_PORT GPIO_PRT3
+#define BT_POWER_PIN 4U
+#define BT_POWER_NUM 4U
+#define BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
+#define BT_POWER_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_4_HSIOM
+ #define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
+#define BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
+#define BT_HOST_WAKE_PORT GPIO_PRT3
+#define BT_HOST_WAKE_PIN 5U
+#define BT_HOST_WAKE_NUM 5U
+#define BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
+#define BT_HOST_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_3_pin_5_HSIOM
+ #define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
+#define BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
+#define BT_DEVICE_WAKE_PORT GPIO_PRT4
+#define BT_DEVICE_WAKE_PIN 0U
+#define BT_DEVICE_WAKE_NUM 0U
+#define BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define BT_DEVICE_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_4_pin_0_HSIOM
+ #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
+#define BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
+#define UART_RX_PORT GPIO_PRT5
+#define UART_RX_PIN 0U
+#define UART_RX_NUM 0U
+#define UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define UART_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_5_pin_0_HSIOM
+ #define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
+#define UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
+#define UART_TX_PORT GPIO_PRT5
+#define UART_TX_PIN 1U
+#define UART_TX_NUM 1U
+#define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define UART_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_5_pin_1_HSIOM
+ #define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
+#define UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
+#define EZI2C_SCL_PORT GPIO_PRT6
+#define EZI2C_SCL_PIN 0U
+#define EZI2C_SCL_NUM 0U
+#define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define EZI2C_SCL_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_0_HSIOM
+ #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
+#define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#define EZI2C_SDA_PORT GPIO_PRT6
+#define EZI2C_SDA_PIN 1U
+#define EZI2C_SDA_NUM 1U
+#define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define EZI2C_SDA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_1_HSIOM
+ #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
+#define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#define SWO_PORT GPIO_PRT6
+#define SWO_PIN 4U
+#define SWO_NUM 4U
+#define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define SWO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_4_HSIOM
+ #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#define SWDIO_PORT GPIO_PRT6
+#define SWDIO_PIN 6U
+#define SWDIO_NUM 6U
+#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define SWDIO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_6_HSIOM
+ #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#define SWDCK_PORT GPIO_PRT6
+#define SWDCK_PIN 7U
+#define SWDCK_NUM 7U
+#define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define SWDCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_7_HSIOM
+ #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
+#define CINA_PORT GPIO_PRT7
+#define CINA_PIN 1U
+#define CINA_NUM 1U
+#define CINA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CINA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_1_HSIOM
+ #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CINA_IRQ ioss_interrupts_gpio_7_IRQn
+#define CINB_PORT GPIO_PRT7
+#define CINB_PIN 2U
+#define CINB_NUM 2U
+#define CINB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CINB_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_2_HSIOM
+ #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CINB_IRQ ioss_interrupts_gpio_7_IRQn
+#define CMOD_PORT GPIO_PRT7
+#define CMOD_PIN 7U
+#define CMOD_NUM 7U
+#define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CMOD_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_7_HSIOM
+ #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#define CSD_BTN0_PORT GPIO_PRT8
+#define CSD_BTN0_PIN 1U
+#define CSD_BTN0_NUM 1U
+#define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CSD_BTN0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_1_HSIOM
+ #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#define CSD_BTN1_PORT GPIO_PRT8
+#define CSD_BTN1_PIN 2U
+#define CSD_BTN1_NUM 2U
+#define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CSD_BTN1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_2_HSIOM
+ #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#define CSD_SLD0_PORT GPIO_PRT8
+#define CSD_SLD0_PIN 3U
+#define CSD_SLD0_NUM 3U
+#define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CSD_SLD0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_3_HSIOM
+ #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#define CSD_SLD1_PORT GPIO_PRT8
+#define CSD_SLD1_PIN 4U
+#define CSD_SLD1_NUM 4U
+#define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CSD_SLD1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_4_HSIOM
+ #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#define CSD_SLD2_PORT GPIO_PRT8
+#define CSD_SLD2_PIN 5U
+#define CSD_SLD2_NUM 5U
+#define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CSD_SLD2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_5_HSIOM
+ #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#define CSD_SLD3_PORT GPIO_PRT8
+#define CSD_SLD3_PIN 6U
+#define CSD_SLD3_NUM 6U
+#define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CSD_SLD3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_6_HSIOM
+ #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#define CSD_SLD4_PORT GPIO_PRT8
+#define CSD_SLD4_PIN 7U
+#define CSD_SLD4_NUM 7U
+#define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CSD_SLD4_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_7_HSIOM
+ #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+
+extern const cy_stc_gpio_pin_config_t WCO_IN_config;
+extern const cy_stc_gpio_pin_config_t WCO_OUT_config;
+extern const cy_stc_gpio_pin_config_t LED_RED_config;
+extern const cy_stc_gpio_pin_config_t SW2_config;
+extern const cy_stc_gpio_pin_config_t LED_BLUE_config;
+extern const cy_stc_gpio_pin_config_t QSPI_SS0_config;
+extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config;
+extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config;
+extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config;
+extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config;
+extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config;
+extern const cy_stc_gpio_pin_config_t LED9_config;
+extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config;
+extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config;
+extern const cy_stc_gpio_pin_config_t CSD_TX_config;
+extern const cy_stc_gpio_pin_config_t LED_GREEN_config;
+extern const cy_stc_gpio_pin_config_t LED8_config;
+extern const cy_stc_gpio_pin_config_t SDHC0_DAT0_config;
+extern const cy_stc_gpio_pin_config_t SDHC0_DAT1_config;
+extern const cy_stc_gpio_pin_config_t SDHC0_DAT2_config;
+extern const cy_stc_gpio_pin_config_t SDHC0_DAT3_config;
+extern const cy_stc_gpio_pin_config_t SDHC0_CMD_config;
+extern const cy_stc_gpio_pin_config_t SDHC0_CLK_config;
+extern const cy_stc_gpio_pin_config_t ENABLE_WIFI_config;
+extern const cy_stc_gpio_pin_config_t BT_UART_RX_config;
+extern const cy_stc_gpio_pin_config_t BT_UART_TX_config;
+extern const cy_stc_gpio_pin_config_t BT_UART_RTS_config;
+extern const cy_stc_gpio_pin_config_t BT_UART_CTS_config;
+extern const cy_stc_gpio_pin_config_t BT_POWER_config;
+extern const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config;
+extern const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config;
+extern const cy_stc_gpio_pin_config_t UART_RX_config;
+extern const cy_stc_gpio_pin_config_t UART_TX_config;
+extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config;
+extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config;
+extern const cy_stc_gpio_pin_config_t SWO_config;
+extern const cy_stc_gpio_pin_config_t SWDIO_config;
+extern const cy_stc_gpio_pin_config_t SWDCK_config;
+extern const cy_stc_gpio_pin_config_t CINA_config;
+extern const cy_stc_gpio_pin_config_t CINB_config;
+extern const cy_stc_gpio_pin_config_t CMOD_config;
+extern const cy_stc_gpio_pin_config_t CSD_BTN0_config;
+extern const cy_stc_gpio_pin_config_t CSD_BTN1_config;
+extern const cy_stc_gpio_pin_config_t CSD_SLD0_config;
+extern const cy_stc_gpio_pin_config_t CSD_SLD1_config;
+extern const cy_stc_gpio_pin_config_t CSD_SLD2_config;
+extern const cy_stc_gpio_pin_config_t CSD_SLD3_config;
+extern const cy_stc_gpio_pin_config_t CSD_SLD4_config;
+
+void init_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_platform.c b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_platform.c
new file mode 100644
index 0000000000..306a16a389
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_platform.c
@@ -0,0 +1,557 @@
+/*******************************************************************************
+* File Name: cycfg_platform.c
+*
+* Description:
+* Platform configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_platform.h"
+
+#define CY_CFG_SYSCLK_ECO_ERROR 1
+#define CY_CFG_SYSCLK_ALTHF_ERROR 2
+#define CY_CFG_SYSCLK_PLL_ERROR 3
+#define CY_CFG_SYSCLK_FLL_ERROR 4
+#define CY_CFG_SYSCLK_WCO_ERROR 5
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
+#define CY_CFG_SYSCLK_FLL_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 48UL
+#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
+#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
+#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
+#define CY_CFG_SYSCLK_ILO_ENABLED 1
+#define CY_CFG_SYSCLK_IMO_ENABLED 1
+#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
+#define CY_CFG_SYSCLK_PLL0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
+#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
+#define CY_CFG_SYSCLK_WCO_ENABLED 1
+#define CY_CFG_PWR_ENABLED 1
+#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_USING_PMIC 0
+#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD
+#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V
+#define CY_CFG_PWR_USING_ULP 0
+
+static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
+{
+ .fllMult = 500U,
+ .refDiv = 20U,
+ .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
+ .enableOutputDiv = true,
+ .lockTolerance = 4U,
+ .igain = 9U,
+ .pgain = 5U,
+ .settlingCount = 8U,
+ .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
+ .cco_Freq = 355U,
+};
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
+{
+ .feedbackDiv = 30,
+ .referenceDiv = 1,
+ .outputDiv = 5,
+ .lfMode = false,
+ .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
+
+__WEAK void cycfg_ClockStartupError(uint32_t error)
+{
+ (void)error; /* Suppress the compiler warning */
+ while(1);
+}
+__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
+{
+ Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
+}
+__STATIC_INLINE void Cy_SysClk_ClkBakInit()
+{
+ Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
+}
+__STATIC_INLINE void Cy_SysClk_ClkFastInit()
+{
+ Cy_SysClk_ClkFastSetDivider(0U);
+}
+__STATIC_INLINE void Cy_SysClk_FllInit()
+{
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+ }
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+ }
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
+{
+ Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf1Init()
+{
+ Cy_SysClk_ClkHfSetSource(1U, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(1U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(1U);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
+{
+ Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
+ Cy_SysClk_ClkHfEnable(2U);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
+{
+ Cy_SysClk_ClkHfSetSource(3U, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(3U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(3U);
+}
+__STATIC_INLINE void Cy_SysClk_IloInit()
+{
+ /* The WDT is unlocked in the default startup code */
+ Cy_SysClk_IloEnable();
+ Cy_SysClk_IloHibernateOn(true);
+}
+__STATIC_INLINE void Cy_SysClk_ClkLfInit()
+{
+ /* The WDT is unlocked in the default startup code */
+ Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
+{
+ Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
+{
+ Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
+{
+ Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath3Init()
+{
+ Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath4Init()
+{
+ Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
+{
+ Cy_SysClk_ClkPeriSetDivider(0U);
+}
+__STATIC_INLINE void Cy_SysClk_Pll0Init()
+{
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+ }
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+ }
+}
+__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
+{
+ Cy_SysClk_ClkSlowSetDivider(0U);
+}
+__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
+{
+ Cy_SysClk_ClkTimerDisable();
+ Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
+ Cy_SysClk_ClkTimerSetDivider(0U);
+ Cy_SysClk_ClkTimerEnable();
+}
+__STATIC_INLINE void Cy_SysClk_WcoInit()
+{
+ (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+ (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
+ }
+}
+
+
+void init_cycfg_platform(void)
+{
+ /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
+ Cy_SysLib_SetWaitStates(false, 150UL);
+ #if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD)
+ if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
+ {
+ Cy_SysLib_ResetBackupDomain();
+ Cy_SysClk_IloDisable();
+ Cy_SysClk_IloInit();
+ }
+ #endif
+ #ifdef CY_CFG_PWR_ENABLED
+ /* Configure power mode */
+ #if CY_CFG_PWR_USING_LDO
+ Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE);
+ #else
+ Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE);
+ #endif
+ /* Configure PMIC */
+ Cy_SysPm_UnlockPmic();
+ #if CY_CFG_PWR_USING_PMIC
+ Cy_SysPm_PmicEnableOutput();
+ #else
+ Cy_SysPm_PmicDisableOutput();
+ #endif
+ #endif
+
+ /* Reset the core clock path to default and disable all the FLLs/PLLs */
+ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkFastSetDivider(0U);
+ Cy_SysClk_ClkPeriSetDivider(1U);
+ Cy_SysClk_ClkSlowSetDivider(0U);
+ Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
+
+ if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
+ (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
+ {
+ Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ }
+
+ Cy_SysClk_FllDisable();
+ Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
+ Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
+ #ifdef CY_IP_MXBLESS
+ (void)Cy_BLE_EcoReset();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3);
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4);
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5);
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6);
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7);
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8);
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9);
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10);
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11);
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12);
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13);
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14);
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE
+ (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15);
+ #endif
+
+ /* Enable all source clocks */
+ #ifdef CY_CFG_SYSCLK_PILO_ENABLED
+ Cy_SysClk_PiloInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_WCO_ENABLED
+ Cy_SysClk_WcoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+ Cy_SysClk_ClkLfInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
+ Cy_SysClk_AltHfInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_ECO_ENABLED
+ Cy_SysClk_EcoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+ Cy_SysClk_ExtClkInit();
+ #endif
+
+ /* Configure CPU clock dividers */
+ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
+ Cy_SysClk_ClkFastInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
+ Cy_SysClk_ClkPeriInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
+ Cy_SysClk_ClkSlowInit();
+ #endif
+
+ #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
+ /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
+ Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
+ Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ #else
+ #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+ Cy_SysClk_ClkPath1Init();
+ #endif
+ #endif
+
+ /* Configure Path Clocks */
+ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+ Cy_SysClk_ClkPath0Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
+ Cy_SysClk_ClkPath2Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
+ Cy_SysClk_ClkPath3Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
+ Cy_SysClk_ClkPath4Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
+ Cy_SysClk_ClkPath5Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
+ Cy_SysClk_ClkPath6Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
+ Cy_SysClk_ClkPath7Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
+ Cy_SysClk_ClkPath8Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
+ Cy_SysClk_ClkPath9Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
+ Cy_SysClk_ClkPath10Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
+ Cy_SysClk_ClkPath11Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
+ Cy_SysClk_ClkPath12Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
+ Cy_SysClk_ClkPath13Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
+ Cy_SysClk_ClkPath14Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
+ Cy_SysClk_ClkPath15Init();
+ #endif
+
+ /* Configure and enable FLL */
+ #ifdef CY_CFG_SYSCLK_FLL_ENABLED
+ Cy_SysClk_FllInit();
+ #endif
+
+ Cy_SysClk_ClkHf0Init();
+
+ #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
+ #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+ /* Apply the ClkPath1 user setting */
+ Cy_SysClk_ClkPath1Init();
+ #endif
+ #endif
+
+ /* Configure and enable PLLs */
+ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
+ Cy_SysClk_Pll0Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
+ Cy_SysClk_Pll1Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL2_ENABLED
+ Cy_SysClk_Pll2Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL3_ENABLED
+ Cy_SysClk_Pll3Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL4_ENABLED
+ Cy_SysClk_Pll4Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL5_ENABLED
+ Cy_SysClk_Pll5Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL6_ENABLED
+ Cy_SysClk_Pll6Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL7_ENABLED
+ Cy_SysClk_Pll7Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL8_ENABLED
+ Cy_SysClk_Pll8Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL9_ENABLED
+ Cy_SysClk_Pll9Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL10_ENABLED
+ Cy_SysClk_Pll10Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL11_ENABLED
+ Cy_SysClk_Pll11Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL12_ENABLED
+ Cy_SysClk_Pll12Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL13_ENABLED
+ Cy_SysClk_Pll13Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL14_ENABLED
+ Cy_SysClk_Pll14Init();
+ #endif
+
+ /* Configure HF clocks */
+ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
+ Cy_SysClk_ClkHf1Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
+ Cy_SysClk_ClkHf2Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
+ Cy_SysClk_ClkHf3Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
+ Cy_SysClk_ClkHf4Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
+ Cy_SysClk_ClkHf5Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
+ Cy_SysClk_ClkHf6Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
+ Cy_SysClk_ClkHf7Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
+ Cy_SysClk_ClkHf8Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
+ Cy_SysClk_ClkHf9Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
+ Cy_SysClk_ClkHf10Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
+ Cy_SysClk_ClkHf11Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
+ Cy_SysClk_ClkHf12Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
+ Cy_SysClk_ClkHf13Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
+ Cy_SysClk_ClkHf14Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
+ Cy_SysClk_ClkHf15Init();
+ #endif
+
+ /* Configure miscellaneous clocks */
+ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
+ Cy_SysClk_ClkTimerInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+ Cy_SysClk_ClkAltSysTickInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
+ Cy_SysClk_ClkPumpInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
+ Cy_SysClk_ClkBakInit();
+ #endif
+
+ /* Configure default enabled clocks */
+ #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+ Cy_SysClk_IloInit();
+ #else
+ Cy_SysClk_IloDisable();
+ #endif
+
+ #ifndef CY_CFG_SYSCLK_IMO_ENABLED
+ #error the IMO must be enabled for proper chip operation
+ #endif
+
+ /* Set accurate flash wait states */
+ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
+ Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
+ #endif
+
+ /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
+ SystemCoreClockUpdate();
+}
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_platform.h b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_platform.h
new file mode 100644
index 0000000000..76dfbef7bc
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_platform.h
@@ -0,0 +1,53 @@
+/*******************************************************************************
+* File Name: cycfg_platform.h
+*
+* Description:
+* Platform configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PLATFORM_H)
+#define CYCFG_PLATFORM_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_systick.h"
+#include "cy_gpio.h"
+#include "cy_syspm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VBACKUP_MV 3300
+#define CY_CFG_PWR_VDD_NS_MV 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
+
+void init_cycfg_platform(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PLATFORM_H */
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_routing.c b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_routing.c
new file mode 100644
index 0000000000..8a1e655157
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_routing.c
@@ -0,0 +1,51 @@
+/*******************************************************************************
+* File Name: cycfg_routing.c
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_routing.h"
+
+#include "cy_trigmux.h"
+
+#include "stdbool.h"
+
+#include "cy_device_headers.h"
+
+void init_cycfg_routing(void)
+{
+ Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT44, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT1, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
+ HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+ HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+}
diff --git a/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_routing.h b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_routing.h
new file mode 100644
index 0000000000..9d9b019eae
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/generated_source/cycfg_routing.h
@@ -0,0 +1,89 @@
+/*******************************************************************************
+* File Name: cycfg_routing.h
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_ROUTING_H)
+#define CYCFG_ROUTING_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+void init_cycfg_routing(void);
+#define init_cycfg_connectivity() init_cycfg_routing()
+#define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM1_LINE_COMPL1
+#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
+#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
+#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
+#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
+#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
+#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
+#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_2_pin_0_HSIOM P2_0_DSI_DSI
+#define ioss_0_port_2_pin_1_HSIOM P2_1_DSI_DSI
+#define ioss_0_port_2_pin_2_HSIOM P2_2_DSI_DSI
+#define ioss_0_port_2_pin_3_HSIOM P2_3_DSI_DSI
+#define ioss_0_port_2_pin_4_HSIOM P2_4_DSI_DSI
+#define ioss_0_port_2_pin_5_HSIOM P2_5_DSI_GPIO
+#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
+#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
+#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
+#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
+#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
+#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
+#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
+#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
+#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
+#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
+#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
+#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
+
+#define cpuss_0_dw0_0_chan_0_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN0
+#define cpuss_0_dw0_0_chan_1_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN1
+#define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1
+#define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3
+#define udb_0_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
+#define udb_0_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT1
+#define udb_0_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT4
+#define udb_0_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
+#define udb_0_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3
+#define udb_0_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
+#define udb_0_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
+#define udb_0_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_ROUTING_H */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_csd.h b/platform/ext/target/psoc64/Native_Driver/include/cy_csd.h
new file mode 100644
index 0000000000..f88605b284
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_csd.h
@@ -0,0 +1,863 @@
+/***************************************************************************//**
+* \file cy_csd.h
+* \version 1.10
+*
+* The header file of the CSD driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either expressed or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_csd
+*/
+
+/**
+********************************************************************************
+* \addtogroup group_csd
+********************************************************************************
+* \{
+*
+* The CSD HW block enables multiple sensing capabilities on PSoC devices,
+* including self-cap and mutual-cap capacitive touch sensing solutions,
+* a 10-bit ADC, IDAC, and Comparator.
+*
+* The CapSense solution includes:
+* * The CapSense Configurator tool, which is a configuration wizard to create
+* and configure CapSense widgets. It can be launched in ModusToolbox
+* from the CSD personality as well as in standalone mode.
+* It contains separate documentation on how to create and
+* configure widgets, parameters, and algorithm descriptions.
+* * An API to control the design from the application program. This documentation
+* describes the API with code snippets about how to use them.
+* * The CapSense Tuner tool for real-time tuning, testing, and debugging,
+* for easy and smooth design of human interfaces on customer products.
+* The Tuner tool communicates with a device through a HW bridge and
+* communication drivers (EzI2C, UART, etc.) and allows monitoring of
+* widget statuses, sensor signals, detected touch positions, gestures, etc.
+* The application program does not need to interact with the CSD driver
+* and/or other drivers such as GPIO or SysClk directly. All of that is
+* configured and managed by middleware.
+*
+* \image html capsense_solution.png "CapSense Solution" width=800px
+* \image latex capsense_solution.png
+*
+* This section describes only the CSD driver. Refer to the corresponding sections
+* for documentation of middleware supported by the CSD HW block.
+*
+* The CSD driver is a low-level peripheral driver that provides an interface to
+* a complex mixed signal of the CSD HW block.
+*
+* The CSD driver alone does not provide system-level functions. Instead, it is
+* used by upper-level middleware to configure the CSD HW block required by
+* an application.
+*
+* The CSD HW block can support only one function at a time. To allow seamless
+* time-multiplex implementation of functionality and to avoid conflicting access
+* to hardware from the upper level, the CSD driver also implements a lock
+* semaphore mechanism.
+*
+* The CSD driver supports re-entrance. If a device contains several
+* CSD HW blocks, the same CSD driver is used to configure any HW block. For
+* that, each function of the CSD driver contains a base address to define
+* the CSD HW block to which the CSD driver communicates.
+*
+* For dual-core devices, the CSD driver functions can be called either by the
+* CM0+ or CM4 cores. In case both cores need access to the CSD Driver, you
+* should properly manage the memory access.
+*
+* There is no restriction on the CSD Driver usage in RTOS.
+*
+********************************************************************************
+* \section group_csd_config_usage Usage
+********************************************************************************
+*
+* The CSD driver is simple wrapper driver specifically designed to be used by higher
+* level middleware. Hence, is highly not recommended to use CSD driver
+* directly in the application program. To incorporate CSD HW block
+* functionality in the application program, an associated middleware
+* should be used.
+*
+* The CSD Driver can be used to implement a custom sensing solution. In such a case,
+* the application program must acquire and lock the CSD HW block prior to
+* accessing it.
+*
+* Setting up and using the CSD driver can be summed up in these four stages:
+* * Define configuration in the config structure.
+* * Allocate context structure variable for the driver.
+* * Capture the CSD HW block.
+* * Execute the action required to perform any kind of conversion.
+*
+* The following code snippet demonstrates how to capture the CSD HW block for
+* custom implementation:
+*
+* \snippet csd/snippet/main.c snippet_Cy_CSD_Conversion
+*
+* The entire solution, either CapSense or CSDADC, in addition to
+* the CSD HW block, incorporates the following instances:
+*
+* * \ref group_csd_config_clocks
+* * \ref group_csd_config_refgen
+* * \ref group_csd_config_interrupts
+* * \ref group_csd_config_pin
+*
+* The CSD driver does not configure those blocks and they should be managed by
+* an upper level. When using CapSense or CSDADC, those blocks are managed by
+* middleware.
+*
+********************************************************************************
+* \subsection group_csd_config_clocks Clocks
+********************************************************************************
+*
+* The CSD HW block requires a peripheral clock (clk_peri) input. It can be
+* assigned using two methods:
+* * Using the Device Configurator (Peripheral-Clocks tab ).
+* * Using the SysClk (System Clock) driver. Refer to \ref group_sysclk driver
+* section for more details.
+* If middleware is used, the clock is managed by middleware.
+*
+********************************************************************************
+* \subsection group_csd_config_pin GPIO Pins
+********************************************************************************
+*
+* Any analog-capable GPIO pin that can be connected to an analog multiplexed bus
+* (AMUXBUS) can be connected to the CSD HW block as an input.
+*
+* GPIO input can be assigned to the CSD HW block using the following methods:
+* * Using the Device Configurator (Pins tab).
+* * Using the GPIO (General Purpose Input Output) driver. Refer to \ref group_gpio
+* driver section.
+*
+* If middleware is used, pin configuration is managed by middleware. When
+* using the CSD driver for custom implementation, the application program must
+* manage pin connections.
+*
+* Each AMUXBUS can be split into multiple segments. Ensure the CSD HW block
+* and a GPIO belong to the same bus segment or join the segments to establish
+* connection of the GPIO to the CSD HW block.
+*
+* For more information about pin configuration, refer to the \ref group_gpio
+* driver.
+*
+********************************************************************************
+* \subsection group_csd_config_refgen Reference Voltage Input
+********************************************************************************
+*
+* The CSD HW block requires a reference voltage input to generate programmable
+* reference voltage within the CSD HW block. There are two on-chip reference
+* sources:
+* * VREF
+* * AREF
+*
+* For more information about specification and startup of reference voltage
+* sources, refer to the \ref group_sysanalog driver prior to making the
+* selection.
+*
+********************************************************************************
+* \subsection group_csd_config_interrupts Interrupts
+********************************************************************************
+*
+* The CSD HW block has one interrupt that can be assigned to either the
+* Cortex M4 or Cortex M0+ core. The CSD HW block can generate interrupts
+* on the following events:
+*
+* * End of sample: when scanning of a single sensor is complete.
+* * End of initialization: when initialization of an analog circuit is complete.
+* * End of measurement: when conversion of an CSDADC channel is complete.
+*
+* Additionally, the CSD interrupt can wake the device from the Sleep power mode.
+* The CSD HW block is powered down in the Deep Sleep or Hibernate power modes.
+* So, it cannot be used as a wake-up source in these power modes.
+*
+* If a CapSense or ADC middleware is used, the interrupt service routine is managed
+* by middleware. When using the CSD driver for custom implementation or other
+* middleware, the application program must manage the interrupt service routine.
+*
+* Implement an interrupt routine and assign it to the CSD interrupt. Use the
+* pre-defined enumeration as the interrupt source of the CSD HW block.
+* The CSD interrupt to the NVIC is raised any time the intersection
+* (logic AND) of the interrupt flags and the corresponding interrupt
+* masks are non-zero. The peripheral interrupt status register should be
+* read in the ISR to detect which condition generated the interrupt.
+* The appropriate interrupt registers should be cleared so that
+* subsequent interrupts can be handled.
+*
+* The following code snippet demonstrates how to implement a routine to handle
+* the interrupt. The routine is called when a CSD interrupt is triggered.
+*
+* \snippet csd/snippet/main.c snippet_Cy_CSD_IntHandler
+*
+* The following code snippet demonstrates how to configure and enable
+* the CSD interrupt:
+*
+* \snippet csd/snippet/main.c snippet_Cy_CSD_IntEnabling
+*
+* For more information, refer to the \ref group_sysint driver.
+*
+* Alternatively, instead of handling the interrupts, the
+* \ref Cy_CSD_GetConversionStatus() function allows for firmware
+* polling of the CSD block status.
+*
+********************************************************************************
+* \section group_csd_config_power_modes Power Modes
+********************************************************************************
+*
+* The CSD HW block can operate in Active and Sleep CPU power modes. It is also
+* possible to switch between Low power and Ultra Low power system modes.
+* In Deep Sleep and in Hibernate power modes, the CSD HW block is powered off.
+* When the device wakes up from Deep Sleep, the CSD HW block resumes operation
+* without the need for re-initialization. In the case of wake up from Hibernate power
+* mode, the CSD HW block does not retain configuration and it requires
+* re-initialization.
+*
+* \note
+* 1. The CSD driver does not provide a callback function to facilitate the
+* low-power mode transitions. The responsibility belongs to an upper
+* level that uses the CSD HW block to ensure the CSD HW block is not
+* busy prior to a power mode transition.
+* 2. A power mode transition is not recommended while the CSD HW block is busy.
+* The CSD HW block status must be checked using the Cy_CSD_GetStatus()
+* function prior to a power mode transition. Instead, use the same power mode
+* for active operation of the CSD HW block. This restriction is not
+* applicable to Sleep mode and the device can seamlessly enter and exit
+* Sleep mode while the CSD HW block is busy.
+*
+* \warning
+* 1. Do not enter Deep Sleep power mode if the CSD HW block conversion is in
+* progress. Unexpected behavior may occur.
+* 2. Analog start up time for the CSD HW block is 25 us. Initiate
+* any kind of conversion only after 25 us from Deep Sleep / Hibernate exit.
+*
+* Refer to the \ref group_syspm driver for more information about
+* low-power mode transitions.
+*
+********************************************************************************
+* \section group_csd_more_information More Information
+********************************************************************************
+*
+* For more information, refer to the following documents:
+*
+* * <a href="http://www.cypress.com/trm218176"><b>Technical Reference Manual (TRM)</b></a>
+*
+* * <a href="https://github.com/cypresssemiconductorco/capsense">
+* <b>Cypress CapSense Middleware Library</b></a>
+*
+* * <a href="https://cypresssemiconductorco.github.io/capsense/capsense_api_reference_manual/html/index.html">
+* <b>Cypress CapSense Middleware API Reference Guide</b></a>
+*
+* * <a href="https://github.com/cypresssemiconductorco/csdadc">
+* <b>Cypress CSDADC Middleware Library</b></a>
+*
+* * <a href="https://cypresssemiconductorco.github.io/csdadc/csdadc_api_reference_manual/html/index.html">
+* <b>Cypress CSDADC Middleware API Reference Guide</b></a>
+*
+* * <a href="https://github.com/cypresssemiconductorco/csdidac">
+* <b>Cypress CSDIDAC Middleware Library</b></a>
+*
+* * <a href="https://cypresssemiconductorco.github.io/csdidac/csdidac_api_reference_manual/html/index.html">
+* <b>Cypress CSDIDAC Middleware API Reference Guide</b></a>
+*
+* * \ref page_getting_started "Getting Started with the PDL"
+*
+* * <a href="http://www.cypress.com/ds218787"><b>PSoC 63 with BLE Datasheet Programmable System-on-Chip</b></a>
+*
+* * <a href="http://www.cypress.com/an85951"><b>AN85951 PSoC 4 and PSoC 6 MCU CapSense Design Guide for more detail</b></a>
+*
+* * <a href="http://www.cypress.com/an210781"><b>AN210781 Getting Started with PSoC 6 MCU with Bluetooth Low Energy (BLE) Connectivity</b></a>
+*
+********************************************************************************
+* \section group_csd_MISRA MISRA-C Compliance
+********************************************************************************
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>14.2</td>
+* <td>R</td>
+* <td>All non-null statements shall either: a) have at least one side-effect
+* however executed, or b) cause control flow to change.</td>
+* <td>The unused function parameters are cast to void. This statement
+* has no side effect and is used to suppress a compiler warning.</td>
+* </tr>
+* <tr>
+* <td>20.6</td>
+* <td>R</td>
+* <td>The macro offsetof, in library <stddef.h>, shall not be used.</td>
+* <td>The only CSD HW block register offsets are defined using this macro
+* to implement functions Read/WriteReg.</td>
+* </tr>
+* </table>
+*
+********************************************************************************
+* \section group_csd_changelog Changelog
+********************************************************************************
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td rowspan="2">1.10</td>
+* <td>The CSD driver sources are enclosed with the conditional compilation
+* to ensure a successful compilation for non-CapSense-capable devices
+* </td>
+* <td>Compilation for non-CapSense-capable devices</td>
+* <tr>
+* <td>Changed the Cy_CSD_GetConversionStatus() function implementation</td>
+* <td>Fixed defect</td>
+* </tr>
+* </tr>
+* <tr>
+* <td>1.0.1</td>
+* <td>Documentation updates</td>
+* <td>Improve user's experience</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>The initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*/
+
+/** \} group_csd */
+
+/**
+********************************************************************************
+* \addtogroup group_csd
+********************************************************************************
+* \{
+* \defgroup group_csd_macros Macros
+* \defgroup group_csd_functions Functions
+* \defgroup group_csd_data_structures Data Structures
+* \defgroup group_csd_enums Enumerated Types
+*/
+
+
+#if !defined(CY_CSD_H)
+#define CY_CSD_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+
+#if defined(CY_IP_MXCSDV2)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+* \addtogroup group_csd_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_CSD_DRV_VERSION_MAJOR (1)
+
+/** Driver minor version */
+#define CY_CSD_DRV_VERSION_MINOR (10)
+
+
+/******************************************************************************
+* API Constants
+******************************************************************************/
+
+/** CSD driver identifier */
+#define CY_CSD_ID (CY_PDL_DRV_ID(0x41U))
+
+/** Initialization macro for the driver context variable */
+#define CY_CSD_CONTEXT_INIT_VALUE {.lockKey = CY_CSD_NONE_KEY}
+
+/** Nominal Vref stored in SFLASH register */
+#define CY_CSD_ADC_VREF_0P8 (800U)
+/** Nominal Vref stored in SFLASH register */
+#define CY_CSD_ADC_VREF_1P2 (1164U)
+/** Nominal Vref stored in SFLASH register */
+#define CY_CSD_ADC_VREF_1P6 (1600U)
+/** Nominal Vref stored in SFLASH register */
+#define CY_CSD_ADC_VREF_2P1 (2133U)
+/** Nominal Vref stored in SFLASH register */
+#define CY_CSD_ADC_VREF_2P6 (2560U)
+/** One hundred percent */
+#define CY_CSDADC_PERCENTAGE_100 (100u)
+/** Max deviation for trim */
+#define CY_CSDADC_VREF_TRIM_MAX_DEVIATION (20u)
+/** Vref max gain */
+#define CY_CSDADC_VREF_GAIN_MAX (32u)
+
+/*******************************************************************************
+* The CSD HW Block Registers Constants
+*******************************************************************************/
+
+/**
+* \defgroup group_csd_reg_const Registers Constants
+* \{
+*/
+
+/** \} group_csd_reg_const */
+
+/** \} group_csd_macros */
+
+
+/*******************************************************************************
+ * Enumerations
+ ******************************************************************************/
+
+/**
+* \addtogroup group_csd_enums
+* \{
+*/
+
+/** CSD status definitions */
+typedef enum
+{
+ /** Successful */
+ CY_CSD_SUCCESS = 0x00U,
+
+ /** One or more invalid parameters */
+ CY_CSD_BAD_PARAM = CY_CSD_ID | CY_PDL_STATUS_ERROR | 0x01U,
+
+ /** The CSD HW block performs conversion */
+ CY_CSD_BUSY = CY_CSD_ID | CY_PDL_STATUS_ERROR | 0x02U,
+
+ /** The CSD HW block is captured by another middleware */
+ CY_CSD_LOCKED = CY_CSD_ID | CY_PDL_STATUS_ERROR | 0x03U
+
+} cy_en_csd_status_t;
+
+
+/**
+* Definitions of upper level keys that use the driver.
+*
+* Each middleware has a unique key assigned. When middleware successfully
+* captures the CSD HW block, this key is placed into the CSD driver context
+* structure. All attempts to capture the CSD HW block by other middleware
+* are rejected. When the first middleware releases the CSD HW block,
+* CY_CSD_NONE_KEY is written to the lockKey variable of the CSD driver context
+* structure and any other middleware can capture the CSD HW block.
+*/
+typedef enum
+{
+ /** The CSD HW block is unused and not captured by any middleware */
+ CY_CSD_NONE_KEY = 0U,
+
+ /**
+ * The CSD HW block is captured by the application program
+ * directly to implement a customer's specific case
+ */
+ CY_CSD_USER_DEFINED_KEY = 1U,
+
+ /** The CSD HW block is captured by a CapSense middleware */
+ CY_CSD_CAPSENSE_KEY = 2U,
+
+ /** The CSD HW block is captured by a ADC middleware */
+ CY_CSD_ADC_KEY = 3U,
+
+ /** The CSD HW block is captured by a IDAC middleware */
+ CY_CSD_IDAC_KEY = 4U,
+
+ /** The CSD HW block is captured by a CMP middleware */
+ CY_CSD_CMP_KEY = 5U
+
+}cy_en_csd_key_t;
+
+/** \} group_csd_enums */
+
+
+/*******************************************************************************
+* Type Definitions
+*******************************************************************************/
+
+/**
+* \addtogroup group_csd_data_structures
+* \{
+*/
+
+/**
+* CSD configuration structure.
+*
+* This structure contains all register values of the CSD HW block. This
+* structure is provided by middleware through the Cy_CSD_Init() and
+* Cy_CSD_Configure() functions to implement the CSD HW block supported
+* sensing modes like self-cap / mutual-cap scanning, ADC measurement, etc.
+*/
+typedef struct
+{
+ uint32_t config; /**< Stores the CSD.CONFIG register value */
+ uint32_t spare; /**< Stores the CSD.SPARE register value */
+ uint32_t status; /**< Stores the CSD.STATUS register value */
+ uint32_t statSeq; /**< Stores the CSD.STAT_SEQ register value */
+ uint32_t statCnts; /**< Stores the CSD.STAT_CNTS register value */
+ uint32_t statHcnt; /**< Stores the CSD.STAT_HCNT register value */
+ uint32_t resultVal1; /**< Stores the CSD.RESULT_VAL1 register value */
+ uint32_t resultVal2; /**< Stores the CSD.RESULT_VAL2 register value */
+ uint32_t adcRes; /**< Stores the CSD.ADC_RES register value */
+ uint32_t intr; /**< Stores the CSD.INTR register value */
+ uint32_t intrSet; /**< Stores the CSD.INTR_SET register value */
+ uint32_t intrMask; /**< Stores the CSD.INTR_MASK register value */
+ uint32_t intrMasked; /**< Stores the CSD.INTR_MASKED register value */
+ uint32_t hscmp; /**< Stores the CSD.HSCMP register value */
+ uint32_t ambuf; /**< Stores the CSD.AMBUF register value */
+ uint32_t refgen; /**< Stores the CSD.REFGEN register value */
+ uint32_t csdCmp; /**< Stores the CSD.CSDCMP register value */
+ uint32_t swRes; /**< Stores the CSD.SW_RES register value */
+ uint32_t sensePeriod; /**< Stores the CSD.SENSE_PERIOD register value */
+ uint32_t senseDuty; /**< Stores the CSD.SENSE_DUTY register value */
+ uint32_t swHsPosSel; /**< Stores the CSD.SW_HS_P_SEL register value */
+ uint32_t swHsNegSel; /**< Stores the CSD.SW_HS_N_SEL register value */
+ uint32_t swShieldSel; /**< Stores the CSD.SW_SHIELD_SEL register value */
+ uint32_t swAmuxbufSel; /**< Stores the CSD.SW_AMUXBUF_SEL register value */
+ uint32_t swBypSel; /**< Stores the CSD.SW_BYP_SEL register value */
+ uint32_t swCmpPosSel; /**< Stores the CSD.SW_CMP_P_SEL register value */
+ uint32_t swCmpNegSel; /**< Stores the CSD.SW_CMP_N_SEL register value */
+ uint32_t swRefgenSel; /**< Stores the CSD.SW_REFGEN_SEL register value */
+ uint32_t swFwModSel; /**< Stores the CSD.SW_FW_MOD_SEL register value */
+ uint32_t swFwTankSel; /**< Stores the CSD.SW_FW_TANK_SEL register value */
+ uint32_t swDsiSel; /**< Stores the CSD.SW_DSI_SEL register value */
+ uint32_t ioSel; /**< Stores the CSD.IO_SEL register value */
+ uint32_t seqTime; /**< Stores the CSD.SEQ_TIME register value */
+ uint32_t seqInitCnt; /**< Stores the CSD.SEQ_INIT_CNT register value */
+ uint32_t seqNormCnt; /**< Stores the CSD.SEQ_NORM_CNT register value */
+ uint32_t adcCtl; /**< Stores the CSD.ADC_CTL register value */
+ uint32_t seqStart; /**< Stores the CSD.SEQ_START register value */
+ uint32_t idacA; /**< Stores the CSD.IDACA register value */
+ uint32_t idacB; /**< Stores the CSD.IDACB register value */
+} cy_stc_csd_config_t;
+
+
+/**
+* CSD driver context structure.
+* This structure is an internal structure of the CSD driver and should not be
+* accessed directly by the application program.
+*/
+typedef struct
+{
+ /** Middleware ID that currently captured CSD */
+ cy_en_csd_key_t lockKey;
+} cy_stc_csd_context_t;
+
+/** \} group_csd_data_structures */
+
+/**
+* \addtogroup group_csd_reg_const
+* \{
+*/
+
+
+/** The register offset */
+#define CY_CSD_REG_OFFSET_CONFIG (offsetof(CSD_Type, CONFIG))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SPARE (offsetof(CSD_Type, SPARE))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_STATUS (offsetof(CSD_Type, STATUS))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_STAT_SEQ (offsetof(CSD_Type, STAT_SEQ))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_STAT_CNTS (offsetof(CSD_Type, STAT_CNTS))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_STAT_HCNT (offsetof(CSD_Type, STAT_HCNT))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_RESULT_VAL1 (offsetof(CSD_Type, RESULT_VAL1))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_RESULT_VAL2 (offsetof(CSD_Type, RESULT_VAL2))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_ADC_RES (offsetof(CSD_Type, ADC_RES))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_INTR (offsetof(CSD_Type, INTR))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_INTR_SET (offsetof(CSD_Type, INTR_SET))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_INTR_MASK (offsetof(CSD_Type, INTR_MASK))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_INTR_MASKED (offsetof(CSD_Type, INTR_MASKED))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_HSCMP (offsetof(CSD_Type, HSCMP))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_AMBUF (offsetof(CSD_Type, AMBUF))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_REFGEN (offsetof(CSD_Type, REFGEN))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_CSDCMP (offsetof(CSD_Type, CSDCMP))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SW_RES (offsetof(CSD_Type, SW_RES))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SENSE_PERIOD (offsetof(CSD_Type, SENSE_PERIOD))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SENSE_DUTY (offsetof(CSD_Type, SENSE_DUTY))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SW_HS_P_SEL (offsetof(CSD_Type, SW_HS_P_SEL))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SW_HS_N_SEL (offsetof(CSD_Type, SW_HS_N_SEL))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SW_SHIELD_SEL (offsetof(CSD_Type, SW_SHIELD_SEL))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SW_AMUXBUF_SEL (offsetof(CSD_Type, SW_AMUXBUF_SEL))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SW_BYP_SEL (offsetof(CSD_Type, SW_BYP_SEL))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SW_CMP_P_SEL (offsetof(CSD_Type, SW_CMP_P_SEL))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SW_CMP_N_SEL (offsetof(CSD_Type, SW_CMP_N_SEL))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SW_REFGEN_SEL (offsetof(CSD_Type, SW_REFGEN_SEL))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SW_FW_MOD_SEL (offsetof(CSD_Type, SW_FW_MOD_SEL))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SW_FW_TANK_SEL (offsetof(CSD_Type, SW_FW_TANK_SEL))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SW_DSI_SEL (offsetof(CSD_Type, SW_DSI_SEL))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_IO_SEL (offsetof(CSD_Type, IO_SEL))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SEQ_TIME (offsetof(CSD_Type, SEQ_TIME))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SEQ_INIT_CNT (offsetof(CSD_Type, SEQ_INIT_CNT))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SEQ_NORM_CNT (offsetof(CSD_Type, SEQ_NORM_CNT))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_ADC_CTL (offsetof(CSD_Type, ADC_CTL))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_SEQ_START (offsetof(CSD_Type, SEQ_START))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_IDACA (offsetof(CSD_Type, IDACA))
+/** The register offset */
+#define CY_CSD_REG_OFFSET_IDACB (offsetof(CSD_Type, IDACB))
+/** \} group_csd_reg_const */
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_csd_functions
+* \{
+*/
+
+cy_en_csd_status_t Cy_CSD_Init(CSD_Type * base, cy_stc_csd_config_t const * config, cy_en_csd_key_t key, cy_stc_csd_context_t * context);
+cy_en_csd_status_t Cy_CSD_DeInit(const CSD_Type * base, cy_en_csd_key_t key, cy_stc_csd_context_t * context);
+cy_en_csd_status_t Cy_CSD_Configure(CSD_Type * base, const cy_stc_csd_config_t * config, cy_en_csd_key_t key, const cy_stc_csd_context_t * context);
+
+__STATIC_INLINE cy_en_csd_key_t Cy_CSD_GetLockStatus(const CSD_Type * base, const cy_stc_csd_context_t * context);
+__STATIC_INLINE cy_en_csd_status_t Cy_CSD_GetConversionStatus(const CSD_Type * base, const cy_stc_csd_context_t * context);
+
+uint32_t Cy_CSD_GetVrefTrim(uint32_t referenceVoltage);
+
+__STATIC_INLINE uint32_t Cy_CSD_ReadReg(const CSD_Type * base, uint32_t offset);
+__STATIC_INLINE void Cy_CSD_WriteReg(CSD_Type * base, uint32_t offset, uint32_t value);
+__STATIC_INLINE void Cy_CSD_SetBits(CSD_Type * base, uint32_t offset, uint32_t mask);
+__STATIC_INLINE void Cy_CSD_ClrBits(CSD_Type * base, uint32_t offset, uint32_t mask);
+__STATIC_INLINE void Cy_CSD_WriteBits(CSD_Type* base, uint32_t offset, uint32_t mask, uint32_t value);
+
+/*******************************************************************************
+* Function Name: Cy_CSD_ReadReg
+****************************************************************************//**
+*
+* Reads value from the specified the CSD HW block register.
+*
+* \param base
+* Pointer to a CSD HW block base address.
+*
+* \param offset
+* Register offset relative to base address.
+*
+* \return
+* Returns a value of the CSD HW block register, specified by the offset
+* parameter.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_CSD_ReadReg(const CSD_Type * base, uint32_t offset)
+{
+ return(* (volatile uint32_t *)((uint32_t)base + offset));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_CSD_WriteReg
+****************************************************************************//**
+*
+* Writes a value to the specified CSD HW block register.
+*
+* \param base
+* Pointer to a CSD HW block base address.
+*
+* \param offset
+* Register offset relative to base address.
+*
+* \param value
+* Value to be written to the register.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CSD_WriteReg(CSD_Type * base, uint32_t offset, uint32_t value)
+{
+ (* (volatile uint32_t *)((uint32_t)base + offset)) = value;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_CSD_SetBits
+****************************************************************************//**
+*
+* Sets bits, specified by the Mask parameter in the CSD HW block register,
+* specified by the Offset parameter.
+*
+* \param base
+* Pointer to a CSD HW block base address.
+*
+* \param offset
+* Register offset relative to base address.
+*
+* \param mask
+* Mask value for register bits to be set.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CSD_SetBits(CSD_Type * base, uint32_t offset, uint32_t mask)
+{
+ volatile uint32_t * regPtr = (volatile uint32_t *)((uint32_t)base + offset);
+ (* regPtr) |= mask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_CSD_ClrBits
+****************************************************************************//**
+*
+* Clears bits, specified by the Mask parameter in the CSD HW block register,
+* specified by the Offset parameter.
+*
+* \param base
+* Pointer to a CSD HW block base address.
+*
+* \param offset
+* Register offset relative to base address.
+*
+* \param mask
+* Mask value for register bits to be cleared.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CSD_ClrBits(CSD_Type * base, uint32_t offset, uint32_t mask)
+{
+ volatile uint32_t * regPtr = (volatile uint32_t *)((uint32_t)base + offset);
+ (* regPtr) &= ~mask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_CSD_WriteBits
+****************************************************************************//**
+*
+* Writes field, specified by the Mask parameter with the value, specified by
+* the Value parameter.
+*
+* \param base
+* Pointer to a CSD HW block base address.
+*
+* \param offset
+* Register offset relative to base address.
+*
+* \param mask
+* Specifies bits to be modified.
+*
+* \param value
+* Specifies a value to be written to the register.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CSD_WriteBits(CSD_Type * base, uint32_t offset, uint32_t mask, uint32_t value)
+{
+ volatile uint32_t * regPtr = (volatile uint32_t *)((uint32_t)base + offset);
+ (* regPtr) = ((* regPtr) & ~mask) | (value & mask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_CSD_GetLockStatus
+****************************************************************************//**
+*
+* Verifies whether the specified CSD HW block is acquired and locked by a
+* higher-level firmware.
+*
+* \param base
+* Pointer to a CSD HW block base address.
+*
+* \param context
+* The pointer to the context structure allocated by a user or middleware.
+*
+* \return
+* Returns a key code. See \ref cy_en_csd_key_t.
+*
+* \funcusage
+*
+* \snippet csd/snippet/main.c snippet_Cy_CSD_CheckKey
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_csd_key_t Cy_CSD_GetLockStatus(const CSD_Type * base, const cy_stc_csd_context_t * context)
+{
+ (void)base;
+ return(context->lockKey);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_CSD_GetConversionStatus
+****************************************************************************//**
+*
+* Verifies whether the specified CSD HW block is busy
+* (performing scan or conversion).
+*
+* \param base
+* Pointer to a CSD HW block base address.
+*
+* \param context
+* The pointer to the context structure allocated by a user or middleware.
+*
+* \return
+* Returns status code. See \ref cy_en_csd_status_t.
+*
+* \funcusage
+*
+* \snippet csd/snippet/main.c snippet_Cy_CSD_CheckStatus
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_csd_status_t Cy_CSD_GetConversionStatus(const CSD_Type * base, const cy_stc_csd_context_t * context)
+{
+ cy_en_csd_status_t csdStatus = CY_CSD_BUSY;
+
+ (void)context;
+ if (((base->SEQ_START & CSD_SEQ_START_START_Msk) == 0u) &&
+ ((base->STAT_SEQ & (CSD_STAT_SEQ_SEQ_STATE_Msk | CSD_STAT_SEQ_ADC_STATE_Msk)) == 0u))
+ {
+ csdStatus = CY_CSD_SUCCESS;
+ }
+
+ return(csdStatus);
+}
+/** \} group_csd_functions */
+
+/** \} group_csd */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_IP_MXCSDV2 */
+
+#endif /* CY_CSD_H */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_device.h b/platform/ext/target/psoc64/Native_Driver/include/cy_device.h
new file mode 100644
index 0000000000..1f2060bf82
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_device.h
@@ -0,0 +1,1262 @@
+/***************************************************************************//**
+* \file cy_device.h
+* \version 2.10
+*
+* This file specifies the structure for core and peripheral block HW base
+* addresses, versions, and parameters.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+/**
+* \section group_device_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>10.1</td>
+* <td>R</td>
+* <td>The value of an expression of integer type shall not be implicitly converted to a different underlying type
+* under some circumstances.</td>
+* <td>An operand of essentially enum type is being converted to unsigned type as a result of an arithmetic or
+* conditional operation. The conversion does not have any unintended effect.</td>
+* </tr>
+* <tr>
+* <td>20.6</td>
+* <td>R</td>
+* <td>The macro offsetof, in library <stddef.h>, shall not be used.</td>
+* <td>The only HW block register offsets are defined using this macro.</td>
+* </tr>
+* </table>
+*/
+
+#ifndef CY_DEVICE_H_
+#define CY_DEVICE_H_
+
+#include <stdint.h>
+#include <stddef.h>
+
+#include "ip/cyip_cpuss.h"
+#include "ip/cyip_cpuss_v2.h"
+#include "ip/cyip_flashc.h"
+#include "ip/cyip_flashc_v2.h"
+#include "ip/cyip_gpio.h"
+#include "ip/cyip_gpio_v2.h"
+#include "ip/cyip_hsiom.h"
+#include "ip/cyip_hsiom_v2.h"
+#include "ip/cyip_sflash.h"
+#include "ip/cyip_srss.h"
+#include "ip/cyip_backup.h"
+#include "ip/cyip_peri.h"
+#include "ip/cyip_peri_v2.h"
+#include "ip/cyip_peri_ms_v2.h"
+#include "ip/cyip_profile.h"
+#include "ip/cyip_prot.h"
+#include "ip/cyip_prot_v2.h"
+#include "ip/cyip_ipc.h"
+#include "ip/cyip_ipc_v2.h"
+#include "ip/cyip_udb.h"
+#include "ip/cyip_dw.h"
+#include "ip/cyip_dw_v2.h"
+#include "ip/cyip_dmac_v2.h"
+#include "ip/cyip_i2s.h"
+#include "ip/cyip_pdm.h"
+#include "ip/cyip_lcd.h"
+#include "ip/cyip_lcd_v2.h"
+#include "ip/cyip_sdhc.h"
+#include "ip/cyip_canfd.h"
+#include "ip/cyip_smartio.h"
+
+/* Device descriptor type */
+typedef struct
+{
+ /* Base HW addresses */
+ uint32_t cpussBase;
+ uint32_t flashcBase;
+ uint32_t periBase;
+ uint32_t udbBase;
+ uint32_t protBase;
+ uint32_t hsiomBase;
+ uint32_t gpioBase;
+ uint32_t passBase;
+ uint32_t ipcBase;
+ uint32_t cryptoBase;
+
+ /* IP block versions: [7:4] major, [3:0] minor */
+ uint8_t cpussVersion;
+ uint8_t cryptoVersion;
+ uint8_t dwVersion;
+ uint8_t ipcVersion;
+ uint8_t periVersion;
+ uint8_t srssVersion;
+
+ /* Parameters */
+ uint8_t cpussIpcNr;
+ uint8_t cpussIpcIrqNr;
+ uint8_t cpussDw0ChNr;
+ uint8_t cpussDw1ChNr;
+ uint8_t cpussFlashPaSize;
+ int16_t cpussIpc0Irq;
+ int16_t cpussFmIrq;
+ int16_t cpussNotConnectedIrq;
+ uint8_t srssNumClkpath;
+ uint8_t srssNumPll;
+ uint8_t srssNumHfroot;
+ uint8_t periClockNr;
+ uint8_t smifDeviceNr;
+ uint8_t passSarChannels;
+ uint8_t epMonitorNr;
+ uint8_t udbPresent;
+ uint8_t sysPmSimoPresent;
+ uint32_t protBusMasterMask;
+ uint32_t cryptoMemSize;
+ uint8_t flashRwwRequired;
+ uint8_t flashPipeRequired;
+ uint8_t flashWriteDelay;
+ uint8_t flashProgramDelay;
+ uint8_t flashEraseDelay;
+ uint8_t flashCtlMainWs0Freq;
+ uint8_t flashCtlMainWs1Freq;
+ uint8_t flashCtlMainWs2Freq;
+ uint8_t flashCtlMainWs3Freq;
+ uint8_t flashCtlMainWs4Freq;
+
+ /* Peripheral register offsets */
+
+ /* DW registers */
+ uint16_t dwChOffset;
+ uint16_t dwChSize;
+ uint8_t dwChCtlPrioPos;
+ uint8_t dwChCtlPreemptablePos;
+ uint8_t dwStatusChIdxPos;
+ uint32_t dwStatusChIdxMsk;
+
+ /* PERI registers */
+ uint16_t periTrCmdOffset;
+ uint16_t periTrCmdGrSelMsk;
+ uint16_t periTrGrOffset;
+ uint16_t periTrGrSize;
+
+ uint8_t periDivCmdDivSelMsk;
+ uint8_t periDivCmdTypeSelPos;
+ uint8_t periDivCmdPaDivSelPos;
+ uint8_t periDivCmdPaTypeSelPos;
+
+ uint16_t periDiv8CtlOffset;
+ uint16_t periDiv16CtlOffset;
+ uint16_t periDiv16_5CtlOffset;
+ uint16_t periDiv24_5CtlOffset;
+
+ /* GPIO registers */
+ uint8_t gpioPrtIntrCfgOffset;
+ uint8_t gpioPrtCfgOffset;
+ uint8_t gpioPrtCfgInOffset;
+ uint8_t gpioPrtCfgOutOffset;
+ uint8_t gpioPrtCfgSioOffset;
+
+ /* CPUSS registers */
+ uint32_t cpussCm0ClockCtlOffset;
+ uint32_t cpussCm4ClockCtlOffset;
+ uint32_t cpussCm4StatusOffset;
+ uint32_t cpussCm0StatusOffset;
+ uint32_t cpussCm4PwrCtlOffset;
+ uint32_t cpussTrimRamCtlOffset;
+ uint32_t cpussTrimRomCtlOffset;
+ uint32_t cpussSysTickCtlOffset;
+ uint16_t cpussCm0NmiCtlOffset;
+ uint16_t cpussCm4NmiCtlOffset;
+ uint16_t cpussRomCtl;
+ uint16_t cpussRam0Ctl0;
+ uint16_t cpussRam1Ctl0;
+ uint16_t cpussRam2Ctl0;
+
+ /* IPC registers */
+ uint16_t ipcStructSize;
+ uint32_t ipcLockStatusOffset;
+} cy_stc_device_t;
+
+/*******************************************************************************
+* Global Variables
+*******************************************************************************/
+
+extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01;
+extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02;
+extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03;
+extern const cy_stc_device_t * cy_device;
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+void Cy_PDL_Init(const cy_stc_device_t * device);
+
+
+/*******************************************************************************
+* Register Access Helper Macros
+*******************************************************************************/
+
+#define CY_CRYPTO_V1 (0x20U > cy_device->cryptoVersion) /* true if the mxcrypto version is 1.x */
+
+#define CY_SRSS_V1_3 (0x13U == cy_device->srssVersion)
+#define CY_SRSS_MFO_PRESENT (CY_SRSS_V1_3)
+
+#define CY_SRSS_NUM_CLKPATH ((uint32_t)(cy_device->srssNumClkpath))
+#define CY_SRSS_NUM_PLL ((uint32_t)(cy_device->srssNumPll))
+#define CY_SRSS_NUM_HFROOT ((uint32_t)(cy_device->srssNumHfroot))
+
+#define SRSS_PWR_CTL (((SRSS_V1_Type *) SRSS)->PWR_CTL)
+#define SRSS_PWR_HIBERNATE (((SRSS_V1_Type *) SRSS)->PWR_HIBERNATE)
+#define SRSS_PWR_TRIM_PWRSYS_CTL (((SRSS_V1_Type *) SRSS)->PWR_TRIM_PWRSYS_CTL)
+#define SRSS_PWR_BUCK_CTL (((SRSS_V1_Type *) SRSS)->PWR_BUCK_CTL)
+#define SRSS_PWR_BUCK_CTL2 (((SRSS_V1_Type *) SRSS)->PWR_BUCK_CTL2)
+#define SRSS_PWR_TRIM_WAKE_CTL (((SRSS_V1_Type *) SRSS)->PWR_TRIM_WAKE_CTL)
+#define SRSS_PWR_LVD_CTL (((SRSS_V1_Type *) SRSS)->PWR_LVD_CTL)
+#define SRSS_PWR_LVD_STATUS (((SRSS_V1_Type *) SRSS)->PWR_LVD_STATUS)
+#define SRSS_WDT_CTL (((SRSS_V1_Type *) SRSS)->WDT_CTL)
+#define SRSS_WDT_CNT (((SRSS_V1_Type *) SRSS)->WDT_CNT)
+#define SRSS_WDT_MATCH (((SRSS_V1_Type *) SRSS)->WDT_MATCH)
+#define SRSS_CLK_DSI_SELECT (((SRSS_V1_Type *) SRSS)->CLK_DSI_SELECT)
+#define SRSS_CLK_PATH_SELECT (((SRSS_V1_Type *) SRSS)->CLK_PATH_SELECT)
+#define SRSS_CLK_ROOT_SELECT (((SRSS_V1_Type *) SRSS)->CLK_ROOT_SELECT)
+#define SRSS_CLK_CSV_HF_LIMIT(clk) (((SRSS_V1_Type *) SRSS)->CLK_CSV[(clk)].HF_LIMIT)
+#define SRSS_CLK_CSV_HF_CTL(clk) (((SRSS_V1_Type *) SRSS)->CLK_CSV[(clk)].HF_CTL)
+#define SRSS_CLK_SELECT (((SRSS_V1_Type *) SRSS)->CLK_SELECT)
+#define SRSS_CLK_TIMER_CTL (((SRSS_V1_Type *) SRSS)->CLK_TIMER_CTL)
+#define SRSS_CLK_CSV_WCO_CTL (((SRSS_V1_Type *) SRSS)->CLK_CSV_WCO_CTL)
+#define SRSS_CLK_ILO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_ILO_CONFIG)
+#define SRSS_CLK_OUTPUT_SLOW (((SRSS_V1_Type *) SRSS)->CLK_OUTPUT_SLOW)
+#define SRSS_CLK_OUTPUT_FAST (((SRSS_V1_Type *) SRSS)->CLK_OUTPUT_FAST)
+#define SRSS_CLK_CAL_CNT1 (((SRSS_V1_Type *) SRSS)->CLK_CAL_CNT1)
+#define SRSS_CLK_CAL_CNT2 (((SRSS_V1_Type *) SRSS)->CLK_CAL_CNT2)
+#define SRSS_CLK_ECO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_ECO_CONFIG)
+#define SRSS_CLK_ECO_STATUS (((SRSS_V1_Type *) SRSS)->CLK_ECO_STATUS)
+#define SRSS_CLK_PILO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_PILO_CONFIG)
+#define SRSS_CLK_MF_SELECT (((SRSS_V1_Type *) SRSS)->CLK_MF_SELECT) /* for CY_SRSS_V1_3 only */
+#define SRSS_CLK_MFO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_MFO_CONFIG) /* for CY_SRSS_V1_3 only */
+#define SRSS_CLK_FLL_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG)
+#define SRSS_CLK_FLL_CONFIG2 (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG2)
+#define SRSS_CLK_FLL_CONFIG3 (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG3)
+#define SRSS_CLK_FLL_CONFIG4 (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG4)
+#define SRSS_CLK_FLL_STATUS (((SRSS_V1_Type *) SRSS)->CLK_FLL_STATUS)
+#define SRSS_CLK_PLL_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_PLL_CONFIG)
+#define SRSS_CLK_PLL_STATUS (((SRSS_V1_Type *) SRSS)->CLK_PLL_STATUS)
+#define SRSS_SRSS_INTR (((SRSS_V1_Type *) SRSS)->SRSS_INTR)
+#define SRSS_SRSS_INTR_SET (((SRSS_V1_Type *) SRSS)->SRSS_INTR_SET)
+#define SRSS_SRSS_INTR_CFG (((SRSS_V1_Type *) SRSS)->SRSS_INTR_CFG)
+#define SRSS_SRSS_INTR_MASK (((SRSS_V1_Type *) SRSS)->SRSS_INTR_MASK)
+#define SRSS_SRSS_INTR_MASKED (((SRSS_V1_Type *) SRSS)->SRSS_INTR_MASKED)
+#define SRSS_CLK_TRIM_ILO_CTL (((SRSS_V1_Type *) SRSS)->CLK_TRIM_ILO_CTL)
+#define SRSS_CLK_TRIM_ECO_CTL (((SRSS_V1_Type *) SRSS)->CLK_TRIM_ECO_CTL)
+
+#define SRSS_RES_CAUSE (((SRSS_V1_Type *) SRSS)->RES_CAUSE)
+#define SRSS_RES_CAUSE2 (((SRSS_V1_Type *) SRSS)->RES_CAUSE2)
+
+#define SRSS_TST_DDFT_SLOW_CTL_REG (*(volatile uint32_t *) 0x40260108U)
+#define SRSS_TST_DDFT_FAST_CTL_REG (*(volatile uint32_t *) 0x40260104U)
+
+#define SRSS_TST_DDFT_SLOW_CTL_MASK (0x00001F1EU)
+#define SRSS_TST_DDFT_FAST_CTL_MASK (62U)
+
+/*******************************************************************************
+* BACKUP
+*******************************************************************************/
+
+#define BACKUP_PMIC_CTL (((BACKUP_V1_Type *) BACKUP)->PMIC_CTL)
+#define BACKUP_CTL (((BACKUP_V1_Type *) BACKUP)->CTL)
+#define BACKUP_RTC_TIME (((BACKUP_V1_Type *) BACKUP)->RTC_TIME)
+#define BACKUP_RTC_DATE (((BACKUP_V1_Type *) BACKUP)->RTC_DATE)
+#define BACKUP_RTC_RW (((BACKUP_V1_Type *) BACKUP)->RTC_RW)
+#define BACKUP_ALM1_TIME (((BACKUP_V1_Type *) BACKUP)->ALM1_TIME)
+#define BACKUP_ALM1_DATE (((BACKUP_V1_Type *) BACKUP)->ALM1_DATE)
+#define BACKUP_ALM2_TIME (((BACKUP_V1_Type *) BACKUP)->ALM2_TIME)
+#define BACKUP_ALM2_DATE (((BACKUP_V1_Type *) BACKUP)->ALM2_DATE)
+#define BACKUP_STATUS (((BACKUP_V1_Type *) BACKUP)->STATUS)
+#define BACKUP_INTR (((BACKUP_V1_Type *) BACKUP)->INTR)
+#define BACKUP_INTR_SET (((BACKUP_V1_Type *) BACKUP)->INTR_SET)
+#define BACKUP_INTR_MASK (((BACKUP_V1_Type *) BACKUP)->INTR_MASK)
+#define BACKUP_INTR_MASKED (((BACKUP_V1_Type *) BACKUP)->INTR_MASKED)
+#define BACKUP_RESET (((BACKUP_V1_Type *) BACKUP)->RESET)
+
+/*******************************************************************************
+* CANFD
+*******************************************************************************/
+
+#define CANFD_CTL(base) (((CANFD_V1_Type *)(base))->CTL)
+#define CANFD_STATUS(base) (((CANFD_V1_Type *)(base))->STATUS)
+#define CANFD_NBTP(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.NBTP)
+#define CANFD_IR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.IR)
+#define CANFD_IE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.IE)
+#define CANFD_ILS(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.ILS)
+#define CANFD_ILE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.ILE)
+#define CANFD_CCCR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.CCCR)
+#define CANFD_SIDFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.SIDFC)
+#define CANFD_XIDFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.XIDFC)
+#define CANFD_XIDAM(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.XIDAM)
+#define CANFD_RXESC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXESC)
+#define CANFD_RXF0C(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF0C)
+#define CANFD_RXF1C(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF1C)
+#define CANFD_RXFTOP_CTL(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].RXFTOP_CTL)
+#define CANFD_RXBC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXBC)
+#define CANFD_TXESC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXESC)
+#define CANFD_TXEFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXEFC)
+#define CANFD_TXBC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBC)
+#define CANFD_DBTP(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.DBTP)
+#define CANFD_TDCR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TDCR)
+#define CANFD_GFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.GFC)
+#define CANFD_TXBRP(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBRP)
+#define CANFD_TXBAR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBAR)
+#define CANFD_TXBCR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBCR)
+#define CANFD_TXBTO(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBTO)
+#define CANFD_TXBCF(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBCF)
+#define CANFD_TXBTIE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBTIE)
+#define CANFD_TXBCIE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBCIE)
+#define CANFD_NDAT1(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.NDAT1)
+#define CANFD_NDAT2(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.NDAT2)
+#define CANFD_RXF0S(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF0S)
+#define CANFD_RXFTOP0_DATA(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].RXFTOP0_DATA)
+#define CANFD_RXFTOP1_DATA(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].RXFTOP1_DATA)
+#define CANFD_RXF0A(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF0A)
+#define CANFD_RXF1S(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF1S)
+#define CANFD_RXF1A(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF1A)
+#define CANFD_PSR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.PSR)
+#define CANFD_TEST(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TEST)
+#define CANFD_CREL(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.CREL)
+
+#define CY_CANFD_CHANNELS_NUM (0x1UL)
+
+
+/*******************************************************************************
+* FLASHC
+*******************************************************************************/
+
+#define FLASHC_FM_CTL_ANA_CTL0 (((FLASHC_V1_Type *) cy_device->flashcBase)->FM_CTL.ANA_CTL0)
+#define FLASHC_FM_CTL_BOOKMARK (((FLASHC_V1_Type *) cy_device->flashcBase)->FM_CTL.BOOKMARK)
+#define FLASHC_FLASH_CMD (((FLASHC_V1_Type *) cy_device->flashcBase)->FLASH_CMD)
+#define FLASHC_FLASH_CTL (((FLASHC_V1_Type *) cy_device->flashcBase)->FLASH_CTL)
+#define FLASHC_BIST_DATA_0 (((FLASHC_V1_Type *) cy_device->flashcBase)->BIST_DATA[0U])
+
+
+/*******************************************************************************
+* SFLASH
+*******************************************************************************/
+
+#define SFLASH_DIE_YEAR (((SFLASH_V1_Type *) SFLASH)->DIE_YEAR)
+#define SFLASH_DIE_MINOR (((SFLASH_V1_Type *) SFLASH)->DIE_MINOR)
+#define SFLASH_DIE_SORT (((SFLASH_V1_Type *) SFLASH)->DIE_SORT)
+#define SFLASH_DIE_Y (((SFLASH_V1_Type *) SFLASH)->DIE_Y)
+#define SFLASH_DIE_X (((SFLASH_V1_Type *) SFLASH)->DIE_X)
+#define SFLASH_DIE_WAFER (((SFLASH_V1_Type *) SFLASH)->DIE_WAFER)
+#define SFLASH_DIE_LOT(val) (((SFLASH_V1_Type *) SFLASH)->DIE_LOT[(val)])
+#define SFLASH_FAMILY_ID (((SFLASH_V1_Type *) SFLASH)->FAMILY_ID)
+#define SFLASH_SI_REVISION_ID (((SFLASH_V1_Type *) SFLASH)->SI_REVISION_ID)
+#define SFLASH_PWR_TRIM_WAKE_CTL (((SFLASH_V1_Type *) SFLASH)->PWR_TRIM_WAKE_CTL)
+#define SFLASH_LDO_0P9V_TRIM (((SFLASH_V1_Type *) SFLASH)->LDO_0P9V_TRIM)
+#define SFLASH_LDO_1P1V_TRIM (((SFLASH_V1_Type *) SFLASH)->LDO_1P1V_TRIM)
+#define SFLASH_BLE_DEVICE_ADDRESS (((SFLASH_V1_Type *) SFLASH)->BLE_DEVICE_ADDRESS)
+#define SFLASH_SILICON_ID (((SFLASH_V1_Type *) SFLASH)->SILICON_ID)
+#define SFLASH_SINGLE_CORE (*(volatile uint8_t *) (SFLASH_BASE + 0xBU))
+
+
+#define SFLASH_CPUSS_TRIM_ROM_CTL_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_LP)
+#define SFLASH_CPUSS_TRIM_RAM_CTL_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_LP)
+#define SFLASH_CPUSS_TRIM_ROM_CTL_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_ULP)
+#define SFLASH_CPUSS_TRIM_RAM_CTL_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_ULP)
+#define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_LP)
+#define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_LP)
+#define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_ULP)
+#define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_ULP)
+
+
+#define SFLASH_CSD0_ADC_VREF0_TRIM (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF0)
+#define SFLASH_CSD0_ADC_VREF1_TRIM (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF1)
+#define SFLASH_CSD0_ADC_VREF2_TRIM (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF2)
+
+
+/*******************************************************************************
+* CPUSS
+*******************************************************************************/
+
+#define CY_CPUSS_V1 (0x20U > cy_device->cpussVersion)
+
+#define CY_CPUSS_NOT_CONNECTED_IRQN ((uint32_t)(cy_device->cpussNotConnectedIrq))
+#define CY_CPUSS_DISCONNECTED_IRQN ((cy_en_intr_t)CY_CPUSS_NOT_CONNECTED_IRQN)
+#define CY_CPUSS_UNCONNECTED_IRQN ((IRQn_Type)CY_CPUSS_NOT_CONNECTED_IRQN)
+
+#define CPUSS_CM0_CLOCK_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm0ClockCtlOffset))
+#define CPUSS_CM4_CLOCK_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm4ClockCtlOffset))
+#define CPUSS_CM4_STATUS (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm4StatusOffset))
+#define CPUSS_CM0_STATUS (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm0StatusOffset))
+#define CPUSS_CM4_PWR_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm4PwrCtlOffset))
+#define CPUSS_TRIM_RAM_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussTrimRamCtlOffset))
+#define CPUSS_TRIM_ROM_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussTrimRomCtlOffset))
+#define CPUSS_SYSTICK_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussSysTickCtlOffset))
+
+#define CPUSS_ROM_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRomCtl))
+#define CPUSS_RAM0_CTL0 (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam0Ctl0))
+#define CPUSS_RAM1_CTL0 (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam1Ctl0))
+#define CPUSS_RAM2_CTL0 (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam2Ctl0))
+
+#define CPUSS_CM0_NMI_CTL(nmi) (((volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm0NmiCtlOffset))[(nmi)])
+#define CPUSS_CM4_NMI_CTL(nmi) (((volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm4NmiCtlOffset))[(nmi)])
+
+/* used in V1 code only */
+#define CPUSS_CM0_INT_CTL ((volatile uint32_t *) &(((CPUSS_V1_Type *)(cy_device->cpussBase))->CM0_INT_CTL0))
+
+/* used in V2 code only */
+#define CPUSS_CM0_SYSTEM_INT_CTL (((CPUSS_V2_Type *)(cy_device->cpussBase))->CM0_SYSTEM_INT_CTL)
+#define CPUSS_CM0_INT_STATUS ((volatile const uint32_t *) &(((CPUSS_V2_Type *)(cy_device->cpussBase))->CM0_INT0_STATUS))
+
+/* ARM core registers */
+#define SYSTICK_CTRL (((SysTick_Type *)SysTick)->CTRL)
+#define SYSTICK_LOAD (((SysTick_Type *)SysTick)->LOAD)
+#define SYSTICK_VAL (((SysTick_Type *)SysTick)->VAL)
+#define SCB_SCR (((SCB_Type *)SCB)->SCR)
+
+#define UDB_UDBIF_BANK_CTL (((UDB_V1_Type *) cy_device->udbBase)->UDBIF.BANK_CTL)
+#define UDB_BCTL_MDCLK_EN (((UDB_V1_Type *) cy_device->udbBase)->BCTL.MDCLK_EN)
+#define UDB_BCTL_MBCLK_EN (((UDB_V1_Type *) cy_device->udbBase)->BCTL.MBCLK_EN)
+#define UDB_BCTL_BOTSEL_L (((UDB_V1_Type *) cy_device->udbBase)->BCTL.BOTSEL_L)
+#define UDB_BCTL_BOTSEL_U (((UDB_V1_Type *) cy_device->udbBase)->BCTL.BOTSEL_U)
+#define UDB_BCTL_QCLK_EN_0 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[0U])
+#define UDB_BCTL_QCLK_EN_1 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[1U])
+#define UDB_BCTL_QCLK_EN_2 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[2U])
+
+
+/*******************************************************************************
+* LPCOMP
+*******************************************************************************/
+
+#define LPCOMP_CMP0_CTRL(base) (((LPCOMP_V1_Type *)(base))->CMP0_CTRL)
+#define LPCOMP_CMP1_CTRL(base) (((LPCOMP_V1_Type *)(base))->CMP1_CTRL)
+#define LPCOMP_CMP0_SW_CLEAR(base) (((LPCOMP_V1_Type *)(base))->CMP0_SW_CLEAR)
+#define LPCOMP_CMP1_SW_CLEAR(base) (((LPCOMP_V1_Type *)(base))->CMP1_SW_CLEAR)
+#define LPCOMP_CMP0_SW(base) (((LPCOMP_V1_Type *)(base))->CMP0_SW)
+#define LPCOMP_CMP1_SW(base) (((LPCOMP_V1_Type *)(base))->CMP1_SW)
+#define LPCOMP_STATUS(base) (((LPCOMP_V1_Type *)(base))->STATUS)
+#define LPCOMP_CONFIG(base) (((LPCOMP_V1_Type *)(base))->CONFIG)
+#define LPCOMP_INTR(base) (((LPCOMP_V1_Type *)(base))->INTR)
+#define LPCOMP_INTR_SET(base) (((LPCOMP_V1_Type *)(base))->INTR_SET)
+#define LPCOMP_INTR_MASK(base) (((LPCOMP_V1_Type *)(base))->INTR_MASK)
+#define LPCOMP_INTR_MASKED(base) (((LPCOMP_V1_Type *)(base))->INTR_MASKED)
+
+
+/*******************************************************************************
+* MCWDT
+*******************************************************************************/
+
+#define MCWDT_STRUCT_MCWDT_CNTLOW(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_CNTLOW)
+#define MCWDT_STRUCT_MCWDT_CNTHIGH(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_CNTHIGH)
+#define MCWDT_STRUCT_MCWDT_MATCH(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_MATCH)
+#define MCWDT_STRUCT_MCWDT_CONFIG(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_CONFIG)
+#define MCWDT_STRUCT_MCWDT_LOCK(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_LOCK)
+#define MCWDT_STRUCT_MCWDT_CTL(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_CTL)
+#define MCWDT_STRUCT_MCWDT_INTR(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_INTR)
+#define MCWDT_STRUCT_MCWDT_INTR_SET(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_INTR_SET)
+#define MCWDT_STRUCT_MCWDT_INTR_MASK(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_INTR_MASK)
+#define MCWDT_STRUCT_MCWDT_INTR_MASKED(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_INTR_MASKED)
+
+
+/*******************************************************************************
+* TCPWM
+*******************************************************************************/
+
+#define TCPWM_CTRL_SET(base) (((TCPWM_V1_Type *)(base))->CTRL_SET)
+#define TCPWM_CTRL_CLR(base) (((TCPWM_V1_Type *)(base))->CTRL_CLR)
+#define TCPWM_CMD_START(base) (((TCPWM_V1_Type *)(base))->CMD_START)
+#define TCPWM_CMD_RELOAD(base) (((TCPWM_V1_Type *)(base))->CMD_RELOAD)
+#define TCPWM_CMD_STOP(base) (((TCPWM_V1_Type *)(base))->CMD_STOP)
+#define TCPWM_CMD_CAPTURE(base) (((TCPWM_V1_Type *)(base))->CMD_CAPTURE)
+
+#define TCPWM_CNT_CTRL(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].CTRL)
+#define TCPWM_CNT_CC(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].CC)
+#define TCPWM_CNT_CC_BUFF(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].CC_BUFF)
+#define TCPWM_CNT_COUNTER(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].COUNTER)
+#define TCPWM_CNT_PERIOD(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].PERIOD)
+#define TCPWM_CNT_PERIOD_BUFF(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].PERIOD_BUFF)
+#define TCPWM_CNT_STATUS(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].STATUS)
+#define TCPWM_CNT_INTR(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].INTR)
+#define TCPWM_CNT_INTR_SET(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].INTR_SET)
+#define TCPWM_CNT_INTR_MASK(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].INTR_MASK)
+#define TCPWM_CNT_INTR_MASKED(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].INTR_MASKED)
+#define TCPWM_CNT_TR_CTRL0(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].TR_CTRL0)
+#define TCPWM_CNT_TR_CTRL1(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].TR_CTRL1)
+#define TCPWM_CNT_TR_CTRL2(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].TR_CTRL2)
+
+
+/*******************************************************************************
+* SAR
+*******************************************************************************/
+
+#define SAR_SAMPLE_CTRL(base) (((SAR_V1_Type *)(base))->SAMPLE_CTRL)
+#define SAR_SAMPLE_TIME01(base) (((SAR_V1_Type *)(base))->SAMPLE_TIME01)
+#define SAR_SAMPLE_TIME23(base) (((SAR_V1_Type *)(base))->SAMPLE_TIME23)
+
+#define SAR_RANGE_THRES(base) (((SAR_V1_Type *)(base))->RANGE_THRES)
+#define SAR_RANGE_COND(base) (((SAR_V1_Type *)(base))->RANGE_COND)
+#define SAR_RANGE_INTR(base) (((SAR_V1_Type *)(base))->RANGE_INTR)
+#define SAR_RANGE_INTR_SET(base) (((SAR_V1_Type *)(base))->RANGE_INTR_SET)
+
+#define SAR_RANGE_INTR_MASK(base) (((SAR_V1_Type *)(base))->RANGE_INTR_MASK)
+#define SAR_RANGE_INTR_MASKED(base) (((SAR_V1_Type *)(base))->RANGE_INTR_MASKED)
+
+#define SAR_CHAN_EN(base) (((SAR_V1_Type *)(base))->CHAN_EN)
+#define SAR_CHAN_CONFIG(base, chan) (((SAR_V1_Type *)(base))->CHAN_CONFIG[(chan)])
+#define SAR_CHAN_RESULT(base, chan ) (((SAR_V1_Type *)(base))->CHAN_RESULT[(chan)])
+#define SAR_CHAN_RESULT_UPDATED(base) (((SAR_V1_Type *)(base))->CHAN_RESULT_UPDATED)
+
+#define SAR_INTR(base) (((SAR_V1_Type *)(base))->INTR)
+#define SAR_INTR_MASK(base) (((SAR_V1_Type *)(base))->INTR_MASK)
+#define SAR_INTR_MASKED(base) (((SAR_V1_Type *)(base))->INTR_MASKED)
+#define SAR_INTR_SET(base) (((SAR_V1_Type *)(base))->INTR_SET)
+#define SAR_INTR_CAUSE(base) (((SAR_V1_Type *)(base))->INTR_CAUSE)
+
+#define SAR_MUX_SWITCH_CLEAR0(base) (((SAR_V1_Type *)(base))->MUX_SWITCH_CLEAR0)
+#define SAR_MUX_SWITCH0(base) (((SAR_V1_Type *)(base))->MUX_SWITCH0)
+#define SAR_MUX_SWITCH_SQ_CTRL(base) (((SAR_V1_Type *)(base))->MUX_SWITCH_SQ_CTRL)
+#define SAR_MUX_SWITCH_DS_CTRL(base) (((SAR_V1_Type *)(base))->MUX_SWITCH_DS_CTRL)
+
+#define SAR_ANA_TRIM0(base) (((SAR_V1_Type *)(base))->ANA_TRIM0)
+#define SAR_CTRL(base) (((SAR_V1_Type *)(base))->CTRL)
+#define SAR_STATUS(base) (((SAR_V1_Type *)(base))->STATUS)
+#define SAR_START_CTRL(base) (((SAR_V1_Type *)(base))->START_CTRL)
+
+#define SAR_SATURATE_INTR(base) (((SAR_V1_Type *)(base))->SATURATE_INTR)
+#define SAR_SATURATE_INTR_MASK(base) (((SAR_V1_Type *)(base))->SATURATE_INTR_MASK)
+#define SAR_SATURATE_INTR_MASKED(base) (((SAR_V1_Type *)(base))->SATURATE_INTR_MASKED)
+#define SAR_SATURATE_INTR_SET(base) (((SAR_V1_Type *)(base))->SATURATE_INTR_SET)
+
+
+/*******************************************************************************
+* SDHC
+*******************************************************************************/
+
+#define SDHC_WRAP_CTL(base) (((SDHC_V1_Type *)(base))->WRAP.CTL)
+#define SDHC_CORE_SDMASA_R(base) (((SDHC_V1_Type *)(base))->CORE.SDMASA_R)
+#define SDHC_CORE_BLOCKSIZE_R(base) (((SDHC_V1_Type *)(base))->CORE.BLOCKSIZE_R)
+#define SDHC_CORE_BLOCKCOUNT_R(base) (((SDHC_V1_Type *)(base))->CORE.BLOCKCOUNT_R)
+#define SDHC_CORE_ARGUMENT_R(base) (((SDHC_V1_Type *)(base))->CORE.ARGUMENT_R)
+#define SDHC_CORE_XFER_MODE_R(base) (((SDHC_V1_Type *)(base))->CORE.XFER_MODE_R)
+#define SDHC_CORE_CMD_R(base) (((SDHC_V1_Type *)(base))->CORE.CMD_R)
+#define SDHC_CORE_RESP01_R(base) (((SDHC_V1_Type *)(base))->CORE.RESP01_R)
+#define SDHC_CORE_RESP23_R(base) (((SDHC_V1_Type *)(base))->CORE.RESP23_R)
+#define SDHC_CORE_RESP45_R(base) (((SDHC_V1_Type *)(base))->CORE.RESP45_R)
+#define SDHC_CORE_RESP67_R(base) (((SDHC_V1_Type *)(base))->CORE.RESP67_R)
+#define SDHC_CORE_BUF_DATA_R(base) (((SDHC_V1_Type *)(base))->CORE.BUF_DATA_R)
+#define SDHC_CORE_PSTATE_REG(base) (((SDHC_V1_Type *)(base))->CORE.PSTATE_REG)
+#define SDHC_CORE_HOST_CTRL1_R(base) (((SDHC_V1_Type *)(base))->CORE.HOST_CTRL1_R)
+#define SDHC_CORE_PWR_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.PWR_CTRL_R)
+#define SDHC_CORE_BGAP_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.BGAP_CTRL_R)
+#define SDHC_CORE_WUP_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.WUP_CTRL_R)
+#define SDHC_CORE_CLK_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.CLK_CTRL_R)
+#define SDHC_CORE_TOUT_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.TOUT_CTRL_R)
+#define SDHC_CORE_SW_RST_R(base) (((SDHC_V1_Type *)(base))->CORE.SW_RST_R)
+#define SDHC_CORE_NORMAL_INT_STAT_R(base) (((SDHC_V1_Type *)(base))->CORE.NORMAL_INT_STAT_R)
+#define SDHC_CORE_ERROR_INT_STAT_R(base) (((SDHC_V1_Type *)(base))->CORE.ERROR_INT_STAT_R)
+#define SDHC_CORE_NORMAL_INT_STAT_EN_R(base) (((SDHC_V1_Type *)(base))->CORE.NORMAL_INT_STAT_EN_R)
+#define SDHC_CORE_ERROR_INT_STAT_EN_R(base) (((SDHC_V1_Type *)(base))->CORE.ERROR_INT_STAT_EN_R)
+#define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R(base) (((SDHC_V1_Type *)(base))->CORE.NORMAL_INT_SIGNAL_EN_R)
+#define SDHC_CORE_ERROR_INT_SIGNAL_EN_R(base) (((SDHC_V1_Type *)(base))->CORE.ERROR_INT_SIGNAL_EN_R)
+#define SDHC_CORE_AUTO_CMD_STAT_R(base) (((SDHC_V1_Type *)(base))->CORE.AUTO_CMD_STAT_R)
+#define SDHC_CORE_HOST_CTRL2_R(base) (((SDHC_V1_Type *)(base))->CORE.HOST_CTRL2_R)
+#define SDHC_CORE_CAPABILITIES1_R(base) (((SDHC_V1_Type *)(base))->CORE.CAPABILITIES1_R)
+#define SDHC_CORE_CAPABILITIES2_R(base) (((SDHC_V1_Type *)(base))->CORE.CAPABILITIES2_R)
+#define SDHC_CORE_CURR_CAPABILITIES1_R(base) (((SDHC_V1_Type *)(base))->CORE.CURR_CAPABILITIES1_R)
+#define SDHC_CORE_CURR_CAPABILITIES2_R(base) (((SDHC_V1_Type *)(base))->CORE.CURR_CAPABILITIES2_R)
+#define SDHC_CORE_ADMA_ERR_STAT_R(base) (((SDHC_V1_Type *)(base))->CORE.ADMA_ERR_STAT_R)
+#define SDHC_CORE_ADMA_SA_LOW_R(base) (((SDHC_V1_Type *)(base))->CORE.ADMA_SA_LOW_R)
+#define SDHC_CORE_ADMA_ID_LOW_R(base) (((SDHC_V1_Type *)(base))->CORE.ADMA_ID_LOW_R)
+#define SDHC_CORE_EMMC_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.EMMC_CTRL_R)
+#define SDHC_CORE_GP_OUT_R(base) (((SDHC_V1_Type *)(base))->CORE.GP_OUT_R)
+
+
+/*******************************************************************************
+* SMARTIO
+*******************************************************************************/
+
+#define SMARTIO_PRT_CTL(base) (((SMARTIO_PRT_V1_Type *)(base))->CTL)
+#define SMARTIO_PRT_SYNC_CTL(base) (((SMARTIO_PRT_V1_Type *)(base))->SYNC_CTL)
+#define SMARTIO_PRT_LUT_SEL(base, idx) (((SMARTIO_PRT_V1_Type *)(base))->LUT_SEL[idx])
+#define SMARTIO_PRT_LUT_CTL(base, idx) (((SMARTIO_PRT_V1_Type *)(base))->LUT_CTL[idx])
+#define SMARTIO_PRT_DU_SEL(base) (((SMARTIO_PRT_V1_Type *)(base))->DU_SEL)
+#define SMARTIO_PRT_DU_CTL(base) (((SMARTIO_PRT_V1_Type *)(base))->DU_CTL)
+#define SMARTIO_PRT_DATA(base) (((SMARTIO_PRT_V1_Type *)(base))->DATA)
+
+
+/*******************************************************************************
+* SMIF
+*******************************************************************************/
+
+#define SMIF_DEVICE_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->CTL)
+#define SMIF_DEVICE_ADDR(base) (((SMIF_DEVICE_V1_Type *)(base))->ADDR)
+#define SMIF_DEVICE_ADDR_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->ADDR_CTL)
+#define SMIF_DEVICE_MASK(base) (((SMIF_DEVICE_V1_Type *)(base))->MASK)
+#define SMIF_DEVICE_RD_CMD_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_CMD_CTL)
+#define SMIF_DEVICE_RD_ADDR_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_ADDR_CTL)
+#define SMIF_DEVICE_RD_MODE_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_MODE_CTL)
+#define SMIF_DEVICE_RD_DUMMY_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_DUMMY_CTL)
+#define SMIF_DEVICE_RD_DATA_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_DATA_CTL)
+#define SMIF_DEVICE_WR_CMD_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_CMD_CTL)
+#define SMIF_DEVICE_WR_ADDR_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_ADDR_CTL)
+#define SMIF_DEVICE_WR_MODE_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_MODE_CTL)
+#define SMIF_DEVICE_WR_DUMMY_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_DUMMY_CTL)
+#define SMIF_DEVICE_WR_DATA_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_DATA_CTL)
+
+#define SMIF_DEVICE_IDX(base, deviceIndex) (((SMIF_V1_Type *)(base))->DEVICE[deviceIndex])
+
+#define SMIF_DEVICE_IDX_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).CTL)
+#define SMIF_DEVICE_IDX_ADDR(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).ADDR)
+#define SMIF_DEVICE_IDX_ADDR_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).ADDR_CTL)
+#define SMIF_DEVICE_IDX_MASK(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).MASK)
+#define SMIF_DEVICE_IDX_RD_CMD_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_CMD_CTL)
+#define SMIF_DEVICE_IDX_RD_ADDR_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_ADDR_CTL)
+#define SMIF_DEVICE_IDX_RD_MODE_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_MODE_CTL)
+#define SMIF_DEVICE_IDX_RD_DUMMY_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_DUMMY_CTL)
+#define SMIF_DEVICE_IDX_RD_DATA_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_DATA_CTL)
+#define SMIF_DEVICE_IDX_WR_CMD_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_CMD_CTL)
+#define SMIF_DEVICE_IDX_WR_ADDR_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_ADDR_CTL)
+#define SMIF_DEVICE_IDX_WR_MODE_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_MODE_CTL)
+#define SMIF_DEVICE_IDX_WR_DUMMY_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_DUMMY_CTL)
+#define SMIF_DEVICE_IDX_WR_DATA_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_DATA_CTL)
+
+#define SMIF_CTL(base) (((SMIF_V1_Type *)(base))->CTL)
+#define SMIF_STATUS(base) (((SMIF_V1_Type *)(base))->STATUS)
+#define SMIF_TX_DATA_FIFO_CTL(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_CTL)
+#define SMIF_RX_DATA_FIFO_CTL(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_CTL)
+#define SMIF_TX_DATA_FIFO_WR1(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_WR1)
+#define SMIF_TX_DATA_FIFO_WR2(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_WR2)
+#define SMIF_TX_DATA_FIFO_WR4(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_WR4)
+#define SMIF_RX_DATA_FIFO_RD1(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_RD1)
+#define SMIF_RX_DATA_FIFO_RD2(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_RD2)
+#define SMIF_RX_DATA_FIFO_RD4(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_RD4)
+#define SMIF_TX_CMD_FIFO_WR(base) (((SMIF_V1_Type *)(base))->TX_CMD_FIFO_WR)
+#define SMIF_TX_CMD_FIFO_STATUS(base) (((SMIF_V1_Type *)(base))->TX_CMD_FIFO_STATUS)
+#define SMIF_RX_DATA_FIFO_STATUS(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_STATUS)
+#define SMIF_TX_DATA_FIFO_STATUS(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_STATUS)
+#define SMIF_INTR(base) (((SMIF_V1_Type *)(base))->INTR)
+#define SMIF_INTR_SET(base) (((SMIF_V1_Type *)(base))->INTR_SET)
+#define SMIF_INTR_MASK(base) (((SMIF_V1_Type *)(base))->INTR_MASK)
+#define SMIF_INTR_MASKED(base) (((SMIF_V1_Type *)(base))->INTR_MASKED)
+#define SMIF_CRYPTO_INPUT0(base) (((SMIF_V1_Type *)(base))->CRYPTO_INPUT0)
+#define SMIF_CRYPTO_OUTPUT0(base) (((SMIF_V1_Type *)(base))->CRYPTO_OUTPUT0)
+#define SMIF_CRYPTO_OUTPUT1(base) (((SMIF_V1_Type *)(base))->CRYPTO_OUTPUT1)
+#define SMIF_CRYPTO_OUTPUT2(base) (((SMIF_V1_Type *)(base))->CRYPTO_OUTPUT2)
+#define SMIF_CRYPTO_OUTPUT3(base) (((SMIF_V1_Type *)(base))->CRYPTO_OUTPUT3)
+#define SMIF_CRYPTO_CMD(base) (((SMIF_V1_Type *)(base))->CRYPTO_CMD)
+#define SMIF_SLOW_CA_CTL(base) (((SMIF_V1_Type *)(base))->SLOW_CA_CTL)
+#define SMIF_FAST_CA_CTL(base) (((SMIF_V1_Type *)(base))->FAST_CA_CTL)
+#define SMIF_SLOW_CA_CMD(base) (((SMIF_V1_Type *)(base))->SLOW_CA_CMD)
+#define SMIF_FAST_CA_CMD(base) (((SMIF_V1_Type *)(base))->FAST_CA_CMD)
+
+
+/*******************************************************************************
+* DW
+*******************************************************************************/
+
+#define CY_DW_V1 (0x20U > cy_device->dwVersion)
+#define CY_DW_CRC (0x20U <= cy_device->dwVersion)
+#define CY_DW0_BASE ((DW_Type*) 0x40280000UL)
+#define CY_DW0_CH_NR (cy_device->cpussDw0ChNr)
+#define CY_DW1_CH_NR (cy_device->cpussDw1ChNr)
+
+#define CY_DW_CH_CTL_PRIO_Pos ((uint32_t)(cy_device->dwChCtlPrioPos))
+#define CY_DW_CH_CTL_PRIO_Msk ((uint32_t)(0x3UL << CY_DW_CH_CTL_PRIO_Pos))
+#define CY_DW_CH_CTL_PREEMPTABLE_Pos ((uint32_t)(cy_device->dwChCtlPreemptablePos))
+#define CY_DW_CH_CTL_PREEMPTABLE_Msk ((uint32_t)(0x1UL << CY_DW_CH_CTL_PREEMPTABLE_Pos))
+#define CY_DW_STATUS_CH_IDX_Pos ((uint32_t)(cy_device->dwStatusChIdxPos))
+#define CY_DW_STATUS_CH_IDX_Msk (cy_device->dwStatusChIdxMsk)
+
+#define DW_CTL(base) (((DW_V1_Type*)(base))->CTL)
+#define DW_STATUS(base) (((DW_V1_Type const*)(base))->STATUS)
+#define DW_DESCR_SRC(base) (((DW_V1_Type*)(base))->ACT_DESCR_SRC)
+#define DW_DESCR_DST(base) (((DW_V1_Type*)(base))->ACT_DESCR_DST)
+
+#define DW_CRC_CTL(base) (((DW_V2_Type*)(base))->CRC_CTL)
+#define DW_CRC_DATA_CTL(base) (((DW_V2_Type*)(base))->CRC_DATA_CTL)
+#define DW_CRC_REM_CTL(base) (((DW_V2_Type*)(base))->CRC_REM_CTL)
+#define DW_CRC_POL_CTL(base) (((DW_V2_Type*)(base))->CRC_POL_CTL)
+#define DW_CRC_LFSR_CTL(base) (((DW_V2_Type*)(base))->CRC_LFSR_CTL)
+
+#define DW_CH(base, chan) ((DW_CH_STRUCT_V2_Type*)((uint32_t)(base) + cy_device->dwChOffset + ((chan) * cy_device->dwChSize)))
+#define DW_CH_CTL(base, chan) (DW_CH(base, chan)->CH_CTL)
+#define DW_CH_STATUS(base, chan) (DW_CH(base, chan)->CH_STATUS)
+#define DW_CH_IDX(base, chan) (DW_CH(base, chan)->CH_IDX)
+#define DW_CH_CURR_PTR(base, chan) (DW_CH(base, chan)->CH_CURR_PTR)
+
+#define DW_CH_INTR(base, chan) (DW_CH(base, chan)->INTR)
+#define DW_CH_INTR_SET(base, chan) (DW_CH(base, chan)->INTR_SET)
+#define DW_CH_INTR_MASK(base, chan) (DW_CH(base, chan)->INTR_MASK)
+#define DW_CH_INTR_MASKED(base, chan) (DW_CH(base, chan)->INTR_MASKED)
+
+
+/*******************************************************************************
+* DMAC
+*******************************************************************************/
+
+#define CY_DMAC_CH_NR (4UL)
+#define DMAC_CTL(base) (((DMAC_V2_Type*)(base))->CTL)
+#define DMAC_ACTIVE(base) (((DMAC_V2_Type const*)(base))->ACTIVE)
+#define DMAC_CH(base, chan) (&(((DMAC_V2_Type*)(base))->CH[(chan)]))
+#define DMAC_CH_CTL(base, chan) (DMAC_CH(base, chan)->CTL)
+#define DMAC_CH_IDX(base, chan) (DMAC_CH(base, chan)->IDX)
+#define DMAC_CH_CURR(base, chan) (DMAC_CH(base, chan)->CURR)
+#define DMAC_CH_DESCR_SRC(base, chan) (DMAC_CH(base, chan)->DESCR_SRC)
+#define DMAC_CH_DESCR_DST(base, chan) (DMAC_CH(base, chan)->DESCR_DST)
+#define DMAC_CH_INTR(base, chan) (DMAC_CH(base, chan)->INTR)
+#define DMAC_CH_INTR_SET(base, chan) (DMAC_CH(base, chan)->INTR_SET)
+#define DMAC_CH_INTR_MASK(base, chan) (DMAC_CH(base, chan)->INTR_MASK)
+#define DMAC_CH_INTR_MASKED(base, chan) (DMAC_CH(base, chan)->INTR_MASKED)
+
+
+/*******************************************************************************
+* PERI
+*******************************************************************************/
+#define CY_PERI_BASE ((PERI_V1_Type *) cy_device->periBase)
+
+#define CY_PERI_V1 (0x20U > cy_device->periVersion) /* true if the mxperi version is 1.x */
+#define CY_PERI_V2_TR_GR_SIZE (sizeof(PERI_TR_GR_V2_Type))
+#define CY_PERI_TR_CTL_NUM (cy_device->periTrGrSize / sizeof(uint32_t))
+#define CY_PERI_TR_CTL_SEL_Pos (0UL)
+#define CY_PERI_TR_CTL_SEL_Msk ((uint32_t)CY_PERI_TR_CTL_NUM - 1UL)
+#define CY_PERI_TR_CMD_GROUP_SEL_Pos (PERI_TR_CMD_GROUP_SEL_Pos)
+#define CY_PERI_TR_CMD_GROUP_SEL_Msk ((uint32_t)cy_device->periTrCmdGrSelMsk)
+
+#define PERI_TR_CMD (*(volatile uint32_t*)((uint32_t)cy_device->periBase + \
+ (uint32_t)cy_device->periTrCmdOffset))
+#define PERI_TR_GR_TR_CTL(group, trCtl) (*(volatile uint32_t*)((uint32_t)cy_device->periBase + \
+ (uint32_t)cy_device->periTrGrOffset + \
+ ((group) * (uint32_t)cy_device->periTrGrSize) + \
+ ((trCtl) * (uint32_t)sizeof(uint32_t))))
+
+#define CY_PERI_CLOCK_NR ((uint32_t)(cy_device->periClockNr))
+
+#define PERI_DIV_CMD ((CY_PERI_BASE)->DIV_CMD)
+
+#define CY_PERI_DIV_CMD_DIV_SEL_Pos (PERI_DIV_CMD_DIV_SEL_Pos)
+#define CY_PERI_DIV_CMD_DIV_SEL_Msk ((uint32_t)(cy_device->periDivCmdDivSelMsk))
+#define CY_PERI_DIV_CMD_TYPE_SEL_Pos ((uint32_t)(cy_device->periDivCmdTypeSelPos))
+#define CY_PERI_DIV_CMD_TYPE_SEL_Msk ((uint32_t)(0x3UL << CY_PERI_DIV_CMD_TYPE_SEL_Pos))
+#define CY_PERI_DIV_CMD_PA_DIV_SEL_Pos ((uint32_t)(cy_device->periDivCmdPaDivSelPos))
+#define CY_PERI_DIV_CMD_PA_DIV_SEL_Msk ((uint32_t)(CY_PERI_DIV_CMD_DIV_SEL_Msk << CY_PERI_DIV_CMD_PA_DIV_SEL_Pos))
+#define CY_PERI_DIV_CMD_PA_TYPE_SEL_Pos ((uint32_t)(cy_device->periDivCmdPaTypeSelPos))
+#define CY_PERI_DIV_CMD_PA_TYPE_SEL_Msk ((uint32_t)(0x3UL << CY_PERI_DIV_CMD_PA_TYPE_SEL_Pos))
+
+#define PERI_CLOCK_CTL ((CY_PERI_BASE)->CLOCK_CTL)
+
+#define CY_PERI_CLOCK_CTL_DIV_SEL_Pos (PERI_CLOCK_CTL_DIV_SEL_Pos)
+#define CY_PERI_CLOCK_CTL_DIV_SEL_Msk (CY_PERI_DIV_CMD_DIV_SEL_Msk)
+#define CY_PERI_CLOCK_CTL_TYPE_SEL_Pos (CY_PERI_DIV_CMD_TYPE_SEL_Pos)
+#define CY_PERI_CLOCK_CTL_TYPE_SEL_Msk (CY_PERI_DIV_CMD_TYPE_SEL_Msk)
+
+#define PERI_DIV_8_CTL ((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv8CtlOffset)))
+#define PERI_DIV_16_CTL ((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv16CtlOffset)))
+#define PERI_DIV_16_5_CTL ((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv16_5CtlOffset)))
+#define PERI_DIV_24_5_CTL ((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv24_5CtlOffset)))
+
+#define PERI_GR_SL_CTL(udbGroupNr) ((CY_PERI_BASE)->GR[udbGroupNr].SL_CTL)
+
+#define PERI_PPU_PR_ADDR0(base) (((PERI_PPU_PR_V1_Type *) (base))->ADDR0)
+#define PERI_PPU_PR_ATT0(base) (((PERI_PPU_PR_V1_Type *) (base))->ATT0)
+#define PERI_PPU_PR_ATT1(base) (((PERI_PPU_PR_V1_Type *) (base))->ATT1)
+
+#define PERI_PPU_GR_ADDR0(base) (((PERI_PPU_GR_V1_Type *) (base))->ADDR0)
+#define PERI_PPU_GR_ATT0(base) (((PERI_PPU_GR_V1_Type *) (base))->ATT0)
+#define PERI_PPU_GR_ATT1(base) (((PERI_PPU_GR_V1_Type *) (base))->ATT1)
+
+#define PERI_GR_PPU_SL_ADDR0(base) (((PERI_GR_PPU_SL_V1_Type *) (base))->ADDR0)
+#define PERI_GR_PPU_SL_ATT0(base) (((PERI_GR_PPU_SL_V1_Type *) (base))->ATT0)
+#define PERI_GR_PPU_SL_ATT1(base) (((PERI_GR_PPU_SL_V1_Type *) (base))->ATT1)
+
+#define PERI_GR_PPU_RG_ADDR0(base) (((PERI_GR_PPU_RG_V1_Type *) (base))->ADDR0)
+#define PERI_GR_PPU_RG_ATT0(base) (((PERI_GR_PPU_RG_V1_Type *) (base))->ATT0)
+#define PERI_GR_PPU_RG_ATT1(base) (((PERI_GR_PPU_RG_V1_Type *) (base))->ATT1)
+
+#define PERI_MS_PPU_PR_SL_ADDR(base) (((PERI_MS_PPU_PR_V2_Type *) (base))->SL_ADDR)
+#define PERI_MS_PPU_PR_SL_SIZE(base) (((PERI_MS_PPU_PR_V2_Type *) (base))->SL_SIZE)
+#define PERI_MS_PPU_PR_MS_ATT(base) ((volatile uint32_t *) &(((PERI_MS_PPU_PR_V2_Type *)(base))->MS_ATT0))
+#define PERI_MS_PPU_PR_SL_ATT(base) ((volatile uint32_t *) &(((PERI_MS_PPU_PR_V2_Type *)(base))->SL_ATT0))
+#define PERI_MS_PPU_FX_MS_ATT(base) ((volatile uint32_t *) &(((PERI_MS_PPU_FX_V2_Type *)(base))->MS_ATT0))
+#define PERI_MS_PPU_FX_SL_ATT(base) ((volatile uint32_t *) &(((PERI_MS_PPU_FX_V2_Type *)(base))->SL_ATT0))
+
+#define PROT_PERI_PPU_PR_STRUCT_IDX_ATT0(stcIdx) ((CY_PERI_BASE)->PPU_PR[(stcIdx)].ATT0)
+#define PROT_PERI_PPU_PR_STRUCT_IDX_ATT1(stcIdx) ((CY_PERI_BASE)->PPU_PR[(stcIdx)].ATT1)
+
+#define PROT_PERI_PPU_PR_STRUCT_IDX(stcIdx) ((PERI_PPU_PR_Type*) &(CY_PERI_BASE)->PPU_PR[(stcIdx)])
+
+
+/*******************************************************************************
+* PROT
+*******************************************************************************/
+#define CY_PROT_BASE (cy_device->protBase)
+
+#define CY_PROT_PC_MAX (8UL)
+#define CY_PROT_BUS_MASTER_MASK (cy_device->protBusMasterMask)
+#define PROT_MPU_MS_CTL(mpu) (((PROT_V1_Type*)CY_PROT_BASE)->CYMPU[(mpu)].MS_CTL)
+#define PROT_MPU_MPU_STRUCT_ADDR(base) (((PROT_MPU_MPU_STRUCT_V1_Type *) (base))->ADDR)
+#define PROT_MPU_MPU_STRUCT_ATT(base) (((PROT_MPU_MPU_STRUCT_V1_Type *) (base))->ATT)
+
+#define PROT_SMPU_SMPU_STRUCT_ADDR0(base) (((PROT_SMPU_SMPU_STRUCT_V1_Type *) (base))->ADDR0)
+#define PROT_SMPU_SMPU_STRUCT_ADDR1(base) (((PROT_SMPU_SMPU_STRUCT_V1_Type *) (base))->ADDR1)
+#define PROT_SMPU_SMPU_STRUCT_ATT0(base) (((PROT_SMPU_SMPU_STRUCT_V1_Type *) (base))->ATT0)
+#define PROT_SMPU_SMPU_STRUCT_ATT1(base) (((PROT_SMPU_SMPU_STRUCT_V1_Type *) (base))->ATT1)
+
+#define PROT_SMPU_SMPU_STRUCT_IDX_ATT0(stcIdx) (((PROT_SMPU_V1_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)].ATT0)
+#define PROT_SMPU_SMPU_STRUCT_IDX_ATT1(stcIdx) (((PROT_SMPU_V1_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)].ATT1)
+#define PROT_SMPU_SMPU_STRUCT_IDX(stcIdx) (((PROT_SMPU_SMPU_STRUCT_V1_Type *) &((PROT_SMPU_V1_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)]))
+
+
+/*******************************************************************************
+* IOSS
+*******************************************************************************/
+
+#define CY_GPIO_BASE ((uint32_t)(cy_device->gpioBase))
+
+#define GPIO_INTR_CAUSE0 (((GPIO_V1_Type*)(cy_device->gpioBase))->INTR_CAUSE0)
+#define GPIO_INTR_CAUSE1 (((GPIO_V1_Type*)(cy_device->gpioBase))->INTR_CAUSE1)
+#define GPIO_INTR_CAUSE2 (((GPIO_V1_Type*)(cy_device->gpioBase))->INTR_CAUSE2)
+#define GPIO_INTR_CAUSE3 (((GPIO_V1_Type*)(cy_device->gpioBase))->INTR_CAUSE3)
+
+#define GPIO_PRT_OUT(base) (((GPIO_PRT_V1_Type*)(base))->OUT)
+#define GPIO_PRT_OUT_CLR(base) (((GPIO_PRT_V1_Type*)(base))->OUT_CLR)
+#define GPIO_PRT_OUT_SET(base) (((GPIO_PRT_V1_Type*)(base))->OUT_SET)
+#define GPIO_PRT_OUT_INV(base) (((GPIO_PRT_V1_Type*)(base))->OUT_INV)
+#define GPIO_PRT_IN(base) (((GPIO_PRT_V1_Type*)(base))->IN)
+#define GPIO_PRT_INTR(base) (((GPIO_PRT_V1_Type*)(base))->INTR)
+#define GPIO_PRT_INTR_MASK(base) (((GPIO_PRT_V1_Type*)(base))->INTR_MASK)
+#define GPIO_PRT_INTR_MASKED(base) (((GPIO_PRT_V1_Type*)(base))->INTR_MASKED)
+#define GPIO_PRT_INTR_SET(base) (((GPIO_PRT_V1_Type*)(base))->INTR_SET)
+
+#define GPIO_PRT_INTR_CFG(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtIntrCfgOffset)))
+#define GPIO_PRT_CFG(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtCfgOffset)))
+#define GPIO_PRT_CFG_IN(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtCfgInOffset)))
+#define GPIO_PRT_CFG_OUT(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtCfgOutOffset)))
+#define GPIO_PRT_CFG_SIO(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtCfgSioOffset)))
+
+#define CY_HSIOM_BASE ((uint32_t)(cy_device->hsiomBase))
+
+#define HSIOM_PRT_PORT_SEL0(base) (((HSIOM_PRT_V1_Type *)(base))->PORT_SEL0)
+#define HSIOM_PRT_PORT_SEL1(base) (((HSIOM_PRT_V1_Type *)(base))->PORT_SEL1)
+
+#define HSIOM_AMUX_SPLIT_CTL(switchCtrl) (((HSIOM_V1_Type *) CY_HSIOM_BASE)->AMUX_SPLIT_CTL[switchCtrl])
+
+
+/*******************************************************************************
+* I2S
+*******************************************************************************/
+
+#define REG_I2S_CTL(base) (((I2S_V1_Type*)(base))->CTL)
+#define REG_I2S_CMD(base) (((I2S_V1_Type*)(base))->CMD)
+#define REG_I2S_CLOCK_CTL(base) (((I2S_V1_Type*)(base))->CLOCK_CTL)
+#define REG_I2S_TR_CTL(base) (((I2S_V1_Type*)(base))->TR_CTL)
+#define REG_I2S_TX_CTL(base) (((I2S_V1_Type*)(base))->TX_CTL)
+#define REG_I2S_TX_FIFO_CTL(base) (((I2S_V1_Type*)(base))->TX_FIFO_CTL)
+#define REG_I2S_TX_FIFO_STATUS(base) (((I2S_V1_Type*)(base))->TX_FIFO_STATUS)
+#define REG_I2S_TX_FIFO_WR(base) (((I2S_V1_Type*)(base))->TX_FIFO_WR)
+#define REG_I2S_TX_WATCHDOG(base) (((I2S_V1_Type*)(base))->TX_WATCHDOG)
+#define REG_I2S_RX_CTL(base) (((I2S_V1_Type*)(base))->RX_CTL)
+#define REG_I2S_RX_FIFO_CTL(base) (((I2S_V1_Type*)(base))->RX_FIFO_CTL)
+#define REG_I2S_RX_FIFO_STATUS(base) (((I2S_V1_Type*)(base))->RX_FIFO_STATUS)
+#define REG_I2S_RX_FIFO_RD(base) (((I2S_V1_Type*)(base))->RX_FIFO_RD)
+#define REG_I2S_RX_FIFO_RD_SILENT(base) (((I2S_V1_Type*)(base))->RX_FIFO_RD_SILENT)
+#define REG_I2S_RX_WATCHDOG(base) (((I2S_V1_Type*)(base))->RX_WATCHDOG)
+#define REG_I2S_INTR(base) (((I2S_V1_Type*)(base))->INTR)
+#define REG_I2S_INTR_SET(base) (((I2S_V1_Type*)(base))->INTR_SET)
+#define REG_I2S_INTR_MASK(base) (((I2S_V1_Type*)(base))->INTR_MASK)
+#define REG_I2S_INTR_MASKED(base) (((I2S_V1_Type*)(base))->INTR_MASKED)
+
+
+/*******************************************************************************
+* PDM
+*******************************************************************************/
+
+#define PDM_PCM_CTL(base) (((PDM_V1_Type*)(base))->CTL)
+#define PDM_PCM_CMD(base) (((PDM_V1_Type*)(base))->CMD)
+#define PDM_PCM_CLOCK_CTL(base) (((PDM_V1_Type*)(base))->CLOCK_CTL)
+#define PDM_PCM_MODE_CTL(base) (((PDM_V1_Type*)(base))->MODE_CTL)
+#define PDM_PCM_DATA_CTL(base) (((PDM_V1_Type*)(base))->DATA_CTL)
+#define PDM_PCM_TR_CTL(base) (((PDM_V1_Type*)(base))->TR_CTL)
+#define PDM_PCM_INTR_MASK(base) (((PDM_V1_Type*)(base))->INTR_MASK)
+#define PDM_PCM_INTR_MASKED(base) (((PDM_V1_Type*)(base))->INTR_MASKED)
+#define PDM_PCM_INTR(base) (((PDM_V1_Type*)(base))->INTR)
+#define PDM_PCM_INTR_SET(base) (((PDM_V1_Type*)(base))->INTR_SET)
+#define PDM_PCM_RX_FIFO_STATUS(base) (((PDM_V1_Type*)(base))->RX_FIFO_STATUS)
+#define PDM_PCM_RX_FIFO_CTL(base) (((PDM_V1_Type*)(base))->RX_FIFO_CTL)
+#define PDM_PCM_RX_FIFO_RD(base) (((PDM_V1_Type*)(base))->RX_FIFO_RD)
+#define PDM_PCM_RX_FIFO_RD_SILENT(base) (((PDM_V1_Type*)(base))->RX_FIFO_RD_SILENT)
+
+
+/*******************************************************************************
+* LCD
+*******************************************************************************/
+
+#define LCD_OCTET_NUM (8U) /* LCD_NUMPORTS - number of octets supporting up to 4 COMs */
+#define LCD_OCTET_NUM_8 (8U) /* LCD_NUMPORTS8 - number of octets supporting up to 8 COMs */
+#define LCD_OCTET_NUM_16 (0U) /* LCD_NUMPORTS16 - number of octets supporting up to 16 COMs */
+#define LCD_COM_NUM (8U) /* LCD_CHIP_TOP_COM_NR - maximum number of commons */
+
+#define LCD_ID(base) (((LCD_V1_Type*)(base))->ID)
+#define LCD_CONTROL(base) (((LCD_V1_Type*)(base))->CONTROL)
+#define LCD_DIVIDER(base) (((LCD_V1_Type*)(base))->DIVIDER)
+#define LCD_DATA0(base) (((LCD_V1_Type*)(base))->DATA0)
+#define LCD_DATA1(base) (((LCD_V1_Type*)(base))->DATA1)
+#define LCD_DATA2(base) (((LCD_V1_Type*)(base))->DATA2)
+#define LCD_DATA3(base) (((LCD_V1_Type*)(base))->DATA3)
+
+
+/*******************************************************************************
+* IPC
+*******************************************************************************/
+
+#define CY_IPC_V1 (0x20u > cy_device->ipcVersion) /* true if the IPC version is 1.x */
+
+#define REG_IPC_STRUCT_ACQUIRE(base) (((IPC_STRUCT_V1_Type*)(base))->ACQUIRE)
+#define REG_IPC_STRUCT_RELEASE(base) (((IPC_STRUCT_V1_Type*)(base))->RELEASE)
+#define REG_IPC_STRUCT_NOTIFY(base) (((IPC_STRUCT_V1_Type*)(base))->NOTIFY)
+#define REG_IPC_STRUCT_DATA(base) (((IPC_STRUCT_V1_Type*)(base))->DATA)
+#define REG_IPC_STRUCT_DATA1(base) (((IPC_STRUCT_V2_Type*)(base))->DATA1)
+#define REG_IPC_STRUCT_LOCK_STATUS(base) (*(volatile uint32_t*)((uint32_t)(base) + cy_device->ipcLockStatusOffset))
+
+#define REG_IPC_INTR_STRUCT_INTR(base) (((IPC_INTR_STRUCT_V1_Type*)(base))->INTR)
+#define REG_IPC_INTR_STRUCT_INTR_SET(base) (((IPC_INTR_STRUCT_V1_Type*)(base))->INTR_SET)
+#define REG_IPC_INTR_STRUCT_INTR_MASK(base) (((IPC_INTR_STRUCT_V1_Type*)(base))->INTR_MASK)
+#define REG_IPC_INTR_STRUCT_INTR_MASKED(base) (((IPC_INTR_STRUCT_V1_Type*)(base))->INTR_MASKED)
+
+#define CY_IPC_STRUCT_PTR(ipcIndex) ((IPC_STRUCT_V1_Type*)(cy_device->ipcBase + (cy_device->ipcStructSize * (ipcIndex))))
+
+#define CY_IPC_CHANNELS (uint32_t)(cy_device->cpussIpcNr)
+#define CY_IPC_INTERRUPTS (uint32_t)(cy_device->cpussIpcIrqNr)
+
+/* IPC channel definitions */
+#define CY_IPC_CHAN_SYSCALL_CM0 (0U) /* System calls for the CM0 processor */
+#define CY_IPC_CHAN_SYSCALL_CM4 (1U) /* System calls for the 1st non-CM0 processor */
+#define CY_IPC_CHAN_SYSCALL_DAP (2UL) /* System calls for the DAP */
+#define CY_IPC_CHAN_SEMA (3UL) /* IPC data channel for the Semaphores */
+#define CY_IPC_CHAN_CYPIPE_EP0 (5UL) /* IPC data channel for CYPIPE EP0 */
+#define CY_IPC_CHAN_CYPIPE_EP1 (6UL) /* IPC data channel for CYPIPE EP1 */
+#define CY_IPC_CHAN_DDFT (7UL) /* IPC data channel for DDFT */
+
+/* IPC Notify interrupts definitions */
+#define CY_IPC_INTR_SYSCALL1 (0UL)
+#define CY_IPC_INTR_CYPIPE_EP0 (3UL)
+#define CY_IPC_INTR_CYPIPE_EP1 (4UL)
+#define CY_IPC_INTR_SPARE (7UL)
+
+/* Endpoint indexes in the pipe array */
+#define CY_IPC_EP_CYPIPE_CM0_ADDR (0UL)
+#define CY_IPC_EP_CYPIPE_CM4_ADDR (1UL)
+
+
+/*******************************************************************************
+* CTB
+*******************************************************************************/
+
+#define CTBM_CTB_CTRL(base) (((CTBM_V1_Type *) (base))->CTB_CTRL)
+#define CTBM_CTB_SW_DS_CTRL(base) (((CTBM_V1_Type *) (base))->CTB_SW_DS_CTRL)
+#define CTBM_CTB_SW_SQ_CTRL(base) (((CTBM_V1_Type *) (base))->CTB_SW_SQ_CTRL)
+#define CTBM_CTD_SW(base) (((CTBM_V1_Type *) (base))->CTD_SW)
+#define CTBM_CTD_SW_CLEAR(base) (((CTBM_V1_Type *) (base))->CTD_SW_CLEAR)
+#define CTBM_COMP_STAT(base) (((CTBM_V1_Type *) (base))->COMP_STAT)
+#define CTBM_OA0_SW_CLEAR(base) (((CTBM_V1_Type *) (base))->OA0_SW_CLEAR)
+#define CTBM_OA1_SW_CLEAR(base) (((CTBM_V1_Type *) (base))->OA1_SW_CLEAR)
+#define CTBM_OA0_SW(base) (((CTBM_V1_Type *) (base))->OA0_SW)
+#define CTBM_OA1_SW(base) (((CTBM_V1_Type *) (base))->OA1_SW)
+#define CTBM_OA_RES0_CTRL(base) (((CTBM_V1_Type *) (base))->OA_RES0_CTRL)
+#define CTBM_OA_RES1_CTRL(base) (((CTBM_V1_Type *) (base))->OA_RES1_CTRL)
+#define CTBM_OA0_COMP_TRIM(base) (((CTBM_V1_Type *) (base))->OA0_COMP_TRIM)
+#define CTBM_OA1_COMP_TRIM(base) (((CTBM_V1_Type *) (base))->OA1_COMP_TRIM)
+#define CTBM_OA0_OFFSET_TRIM(base) (((CTBM_V1_Type *) (base))->OA0_OFFSET_TRIM)
+#define CTBM_OA1_OFFSET_TRIM(base) (((CTBM_V1_Type *) (base))->OA1_OFFSET_TRIM)
+#define CTBM_OA0_SLOPE_OFFSET_TRIM(base) (((CTBM_V1_Type *) (base))->OA0_SLOPE_OFFSET_TRIM)
+#define CTBM_OA1_SLOPE_OFFSET_TRIM(base) (((CTBM_V1_Type *) (base))->OA1_SLOPE_OFFSET_TRIM)
+#define CTBM_INTR(base) (((CTBM_V1_Type *) (base))->INTR)
+#define CTBM_INTR_SET(base) (((CTBM_V1_Type *) (base))->INTR_SET)
+#define CTBM_INTR_MASK(base) (((CTBM_V1_Type *) (base))->INTR_MASK)
+#define CTBM_INTR_MASKED(base) (((CTBM_V1_Type *) (base))->INTR_MASKED)
+
+
+/*******************************************************************************
+* CTDAC
+*******************************************************************************/
+
+#define CTDAC_CTDAC_CTRL(base) (((CTDAC_V1_Type *) (base))->CTDAC_CTRL)
+#define CTDAC_CTDAC_SW(base) (((CTDAC_V1_Type *) (base))->CTDAC_SW)
+#define CTDAC_CTDAC_SW_CLEAR(base) (((CTDAC_V1_Type *) (base))->CTDAC_SW_CLEAR)
+#define CTDAC_CTDAC_VAL(base) (((CTDAC_V1_Type *) (base))->CTDAC_VAL)
+#define CTDAC_CTDAC_VAL_NXT(base) (((CTDAC_V1_Type *) (base))->CTDAC_VAL_NXT)
+#define CTDAC_INTR(base) (((CTDAC_V1_Type *) (base))->INTR)
+#define CTDAC_INTR_SET(base) (((CTDAC_V1_Type *) (base))->INTR_SET)
+#define CTDAC_INTR_MASK(base) (((CTDAC_V1_Type *) (base))->INTR_MASK)
+#define CTDAC_INTR_MASKED(base) (((CTDAC_V1_Type *) (base))->INTR_MASKED)
+
+
+/*******************************************************************************
+* SYSANALOG
+*******************************************************************************/
+
+#define PASS_AREF_AREF_CTRL (((PASS_V1_Type*) cy_device->passBase)->AREF.AREF_CTRL)
+#define PASS_INTR_CAUSE (((PASS_V1_Type*) cy_device->passBase)->INTR_CAUSE)
+
+
+/*******************************************************************************
+* SCB
+*******************************************************************************/
+
+#define SCB_CTRL(base) (((CySCB_V1_Type*) (base))->CTRL)
+#define SCB_SPI_CTRL(base) (((CySCB_V1_Type*) (base))->SPI_CTRL)
+#define SCB_SPI_STATUS(base) (((CySCB_V1_Type*) (base))->SPI_STATUS)
+#define SCB_UART_CTRL(base) (((CySCB_V1_Type*) (base))->UART_CTRL)
+#define SCB_UART_TX_CTRL(base) (((CySCB_V1_Type*) (base))->UART_TX_CTRL)
+#define SCB_UART_RX_CTRL(base) (((CySCB_V1_Type*) (base))->UART_RX_CTRL)
+#define SCB_UART_FLOW_CTRL(base) (((CySCB_V1_Type*) (base))->UART_FLOW_CTRL)
+#define SCB_I2C_CTRL(base) (((CySCB_V1_Type*) (base))->I2C_CTRL)
+#define SCB_I2C_STATUS(base) (((CySCB_V1_Type*) (base))->I2C_STATUS)
+#define SCB_I2C_M_CMD(base) (((CySCB_V1_Type*) (base))->I2C_M_CMD)
+#define SCB_I2C_S_CMD(base) (((CySCB_V1_Type*) (base))->I2C_S_CMD)
+#define SCB_I2C_CFG(base) (((CySCB_V1_Type*) (base))->I2C_CFG)
+#define SCB_TX_CTRL(base) (((CySCB_V1_Type*) (base))->TX_CTRL)
+#define SCB_TX_FIFO_CTRL(base) (((CySCB_V1_Type*) (base))->TX_FIFO_CTRL)
+#define SCB_TX_FIFO_STATUS(base) (((CySCB_V1_Type*) (base))->TX_FIFO_STATUS)
+#define SCB_TX_FIFO_WR(base) (((CySCB_V1_Type*) (base))->TX_FIFO_WR)
+#define SCB_RX_CTRL(base) (((CySCB_V1_Type*) (base))->RX_CTRL)
+#define SCB_RX_FIFO_CTRL(base) (((CySCB_V1_Type*) (base))->RX_FIFO_CTRL)
+#define SCB_RX_FIFO_STATUS(base) (((CySCB_V1_Type*) (base))->RX_FIFO_STATUS)
+#define SCB_RX_MATCH(base) (((CySCB_V1_Type*) (base))->RX_MATCH)
+#define SCB_RX_FIFO_RD(base) (((CySCB_V1_Type*) (base))->RX_FIFO_RD)
+#define SCB_INTR_CAUSE(base) (((CySCB_V1_Type*) (base))->INTR_CAUSE)
+#define SCB_INTR_I2C_EC(base) (((CySCB_V1_Type*) (base))->INTR_I2C_EC)
+#define SCB_INTR_I2C_EC_MASK(base) (((CySCB_V1_Type*) (base))->INTR_I2C_EC_MASK)
+#define SCB_INTR_I2C_EC_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_I2C_EC_MASKED)
+#define SCB_INTR_SPI_EC(base) (((CySCB_V1_Type*) (base))->INTR_SPI_EC)
+#define SCB_INTR_SPI_EC_MASK(base) (((CySCB_V1_Type*) (base))->INTR_SPI_EC_MASK)
+#define SCB_INTR_SPI_EC_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_SPI_EC_MASKED)
+#define SCB_INTR_M(base) (((CySCB_V1_Type*) (base))->INTR_M)
+#define SCB_INTR_M_SET(base) (((CySCB_V1_Type*) (base))->INTR_M_SET)
+#define SCB_INTR_M_MASK(base) (((CySCB_V1_Type*) (base))->INTR_M_MASK)
+#define SCB_INTR_M_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_M_MASKED)
+#define SCB_INTR_S(base) (((CySCB_V1_Type*) (base))->INTR_S)
+#define SCB_INTR_S_SET(base) (((CySCB_V1_Type*) (base))->INTR_S_SET)
+#define SCB_INTR_S_MASK(base) (((CySCB_V1_Type*) (base))->INTR_S_MASK)
+#define SCB_INTR_S_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_S_MASKED)
+#define SCB_INTR_TX(base) (((CySCB_V1_Type*) (base))->INTR_TX)
+#define SCB_INTR_TX_SET(base) (((CySCB_V1_Type*) (base))->INTR_TX_SET)
+#define SCB_INTR_TX_MASK(base) (((CySCB_V1_Type*) (base))->INTR_TX_MASK)
+#define SCB_INTR_TX_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_TX_MASKED)
+#define SCB_INTR_RX(base) (((CySCB_V1_Type*) (base))->INTR_RX)
+#define SCB_INTR_RX_SET(base) (((CySCB_V1_Type*) (base))->INTR_RX_SET)
+#define SCB_INTR_RX_MASK(base) (((CySCB_V1_Type*) (base))->INTR_RX_MASK)
+#define SCB_INTR_RX_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_RX_MASKED)
+
+
+/*******************************************************************************
+* PROFILE
+*******************************************************************************/
+
+#define CY_EP_MONITOR_COUNT ((uint32_t)(cy_device->epMonitorNr))
+#define CY_EP_CNT_NR (8UL)
+#define PROFILE_CTL (((PROFILE_V1_Type*) PROFILE_BASE)->CTL)
+#define PROFILE_STATUS (((PROFILE_V1_Type*) PROFILE_BASE)->STATUS)
+#define PROFILE_CMD (((PROFILE_V1_Type*) PROFILE_BASE)->CMD)
+#define PROFILE_INTR (((PROFILE_V1_Type*) PROFILE_BASE)->INTR)
+#define PROFILE_INTR_MASK (((PROFILE_V1_Type*) PROFILE_BASE)->INTR_MASK)
+#define PROFILE_INTR_MASKED (((PROFILE_V1_Type*) PROFILE_BASE)->INTR_MASKED)
+#define PROFILE_CNT_STRUCT (((PROFILE_V1_Type*) PROFILE_BASE)->CNT_STRUCT)
+
+
+/*******************************************************************************
+* BLE
+*******************************************************************************/
+
+#define BLE_RCB_INTR (((BLE_V1_Type *) BLE)->RCB.INTR)
+#define BLE_RCB_TX_FIFO_WR (((BLE_V1_Type *) BLE)->RCB.TX_FIFO_WR)
+#define BLE_RCB_RX_FIFO_RD (((BLE_V1_Type *) BLE)->RCB.RX_FIFO_RD)
+#define BLE_RCB_CTRL (((BLE_V1_Type *) BLE)->RCB.CTRL)
+#define BLE_RCB_RCBLL_CTRL (((BLE_V1_Type *) BLE)->RCB.RCBLL.CTRL)
+#define BLE_BLESS_XTAL_CLK_DIV_CONFIG (((BLE_V1_Type *) BLE)->BLESS.XTAL_CLK_DIV_CONFIG)
+#define BLE_BLESS_MT_CFG (((BLE_V1_Type *) BLE)->BLESS.MT_CFG)
+#define BLE_BLESS_MT_STATUS (((BLE_V1_Type *) BLE)->BLESS.MT_STATUS)
+#define BLE_BLESS_MT_DELAY_CFG (((BLE_V1_Type *) BLE)->BLESS.MT_DELAY_CFG)
+#define BLE_BLESS_MT_DELAY_CFG2 (((BLE_V1_Type *) BLE)->BLESS.MT_DELAY_CFG2)
+#define BLE_BLESS_MT_DELAY_CFG3 (((BLE_V1_Type *) BLE)->BLESS.MT_DELAY_CFG3)
+#define BLE_BLESS_MT_VIO_CTRL (((BLE_V1_Type *) BLE)->BLESS.MT_VIO_CTRL)
+#define BLE_BLESS_LL_CLK_EN (((BLE_V1_Type *) BLE)->BLESS.LL_CLK_EN)
+#define BLE_BLESS_MISC_EN_CTRL (((BLE_V1_Type *) BLE)->BLESS.MISC_EN_CTRL)
+#define BLE_BLESS_INTR_STAT (((BLE_V1_Type *) BLE)->BLESS.INTR_STAT)
+#define BLE_BLELL_EVENT_INTR (((BLE_V1_Type *) BLE)->BLELL.EVENT_INTR)
+#define BLE_BLELL_CONN_INTR (((BLE_V1_Type *) BLE)->BLELL.CONN_INTR)
+#define BLE_BLELL_CONN_EXT_INTR (((BLE_V1_Type *) BLE)->BLELL.CONN_EXT_INTR)
+#define BLE_BLELL_SCAN_INTR (((BLE_V1_Type *) BLE)->BLELL.SCAN_INTR)
+#define BLE_BLELL_ADV_INTR (((BLE_V1_Type *) BLE)->BLELL.ADV_INTR)
+
+
+/*******************************************************************************
+* USBFS Device
+*******************************************************************************/
+
+#define USBFS_DEV_CR0(base) (((USBFS_V1_Type *)(base))->USBDEV.CR0)
+#define USBFS_DEV_CR1(base) (((USBFS_V1_Type *)(base))->USBDEV.CR1)
+#define USBFS_DEV_USBIO_CR0(base) (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR0)
+#define USBFS_DEV_USBIO_CR2(base) (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR2)
+#define USBFS_DEV_USBIO_CR1(base) (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR1)
+#define USBFS_DEV_USB_CLK_EN(base) (((USBFS_V1_Type *)(base))->USBDEV.USB_CLK_EN)
+#define USBFS_DEV_BUS_RST_CNT(base) (((USBFS_V1_Type *)(base))->USBDEV.BUS_RST_CNT)
+#define USBFS_DEV_OSCLK_DR0(base) (((USBFS_V1_Type *)(base))->USBDEV.EP_TYPE)
+#define USBFS_DEV_OSCLK_DR1(base) (((USBFS_V1_Type *)(base))->USBDEV.OSCLK_DR0)
+#define USBFS_DEV_SOF0(base) (((USBFS_V1_Type *)(base))->USBDEV.SOF0)
+#define USBFS_DEV_SOF1(base) (((USBFS_V1_Type *)(base))->USBDEV.SOF1)
+#define USBFS_DEV_SOF16(base) (((USBFS_V1_Type *)(base))->USBDEV.OSCLK_DR1)
+#define USBFS_DEV_OSCLK_DR16(base) (((USBFS_V1_Type *)(base))->USBDEV.SOF16)
+#define USBFS_DEV_ARB_CFG(base) (((USBFS_V1_Type *)(base))->USBDEV.ARB_CFG)
+#define USBFS_DEV_DYN_RECONFIG(base) (((USBFS_V1_Type *)(base))->USBDEV.DYN_RECONFIG)
+#define USBFS_DEV_BUF_SIZE(base) (((USBFS_V1_Type *)(base))->USBDEV.BUF_SIZE)
+#define USBFS_DEV_EP_ACTIVE(base) (((USBFS_V1_Type *)(base))->USBDEV.EP_ACTIVE)
+#define USBFS_DEV_EP_TYPE(base) (((USBFS_V1_Type *)(base))->USBDEV.EP_TYPE)
+#define USBFS_DEV_CWA16(base) (((USBFS_V1_Type *)(base))->USBDEV.CWA16)
+#define USBFS_DEV_CWA(base) (((USBFS_V1_Type *)(base))->USBDEV.CWA)
+#define USBFS_DEV_CWA_MSB(base) (((USBFS_V1_Type *)(base))->USBDEV.CWA_MSB)
+#define USBFS_DEV_DMA_THRES16(base) (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES16)
+#define USBFS_DEV_DMA_THRES(base) (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES)
+#define USBFS_DEV_DMA_THRES_MSB(base) (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES_MSB)
+
+#define USBFS_DEV_SIE_EP_INT_EN(base) (((USBFS_V1_Type *)(base))->USBDEV.SIE_EP_INT_EN)
+#define USBFS_DEV_SIE_EP_INT_SR(base) (((USBFS_V1_Type *)(base))->USBDEV.SIE_EP_INT_SR)
+#define USBFS_DEV_ARB_INT_EN(base) (((USBFS_V1_Type *)(base))->USBDEV.ARB_INT_EN)
+#define USBFS_DEV_ARB_INT_SR(base) (((USBFS_V1_Type *)(base))->USBDEV.ARB_INT_SR)
+
+#define USBFS_DEV_EP0_CR(base) (((USBFS_V1_Type *)(base))->USBDEV.EP0_CR)
+#define USBFS_DEV_EP0_CNT(base) (((USBFS_V1_Type *)(base))->USBDEV.EP0_CNT)
+#define USBFS_DEV_EP0_DR(base, idx) (((USBFS_V1_Type *)(base))->USBDEV.EP0_DR[idx])
+
+#define USBFS_DEV_MEM_DATA(base, idx) (((USBFS_V1_Type *)(base))->USBDEV.MEM[idx])
+
+#define USBFS_DEV_SIE_REGS_BASE (0x30U)
+#define USBFS_DEV_SIE_REGS_SIZE (0x40U)
+#define USBFS_DEV_SIE_EP_CNT0_OFFSET (0x00U)
+#define USBFS_DEV_SIE_EP_CNT1_OFFSET (0x04U)
+#define USBFS_DEV_SIE_EP_CR0_OFFSET (0x08U)
+#define USBFS_DEV_SIE_REGS(base, endpoint) ((uint32_t)(base) + USBFS_DEV_SIE_REGS_BASE + ((endpoint) * USBFS_DEV_SIE_REGS_SIZE))
+
+#define USBFS_DEV_SIE_EP_CNT0(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \
+ USBFS_DEV_SIE_EP_CNT0_OFFSET))
+#define USBFS_DEV_SIE_EP_CNT1(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \
+ USBFS_DEV_SIE_EP_CNT1_OFFSET))
+#define USBFS_DEV_SIE_EP_CR0(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \
+ USBFS_DEV_SIE_EP_CR0_OFFSET))
+
+#define USBFS_DEV_ARB_REGS_BASE (0x200U)
+#define USBFS_DEV_ARB_REGS_SIZE (0x40U)
+#define USBFS_DEV_ARB_EP_CFG_OFFSET (0x00U)
+#define USBFS_DEV_ARB_EP_INT_EN_OFFSET (0x04U)
+#define USBFS_DEV_ARB_EP_SR_OFFSET (0x08U)
+#define USBFS_DEV_ARB_RW_WA_OFFSET (0x10U)
+#define USBFS_DEV_ARB_RW_WA_MSB_OFFSET (0x14U)
+#define USBFS_DEV_ARB_RW_RA_OFFSET (0x18U)
+#define USBFS_DEV_ARB_RW_RA_MSB_OFFSET (0x1CU)
+#define USBFS_DEV_ARB_RW_DR_OFFSET (0x20U)
+#define USBFS_DEV_ARB_REGS(base, endpoint) ((uint32_t)(base) + USBFS_DEV_ARB_REGS_BASE + ((endpoint) * USBFS_DEV_ARB_REGS_SIZE))
+
+#define USBFS_DEV_ARB_EP_CFG(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
+ USBFS_DEV_ARB_EP_CFG_OFFSET))
+#define USBFS_DEV_ARB_EP_INT_EN(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
+ USBFS_DEV_ARB_EP_INT_EN_OFFSET))
+#define USBFS_DEV_ARB_EP_SR(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
+ USBFS_DEV_ARB_EP_SR_OFFSET))
+#define USBFS_DEV_ARB_RW_WA(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
+ USBFS_DEV_ARB_RW_WA_OFFSET))
+#define USBFS_DEV_ARB_RW_WA_MSB(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
+ USBFS_DEV_ARB_RW_WA_MSB_OFFSET))
+#define USBFS_DEV_ARB_RW_RA(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
+ USBFS_DEV_ARB_RW_RA_OFFSET))
+#define USBFS_DEV_ARB_RW_RA_MSB(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
+ USBFS_DEV_ARB_RW_RA_MSB_OFFSET))
+#define USBFS_DEV_ARB_RW_DR(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
+ USBFS_DEV_ARB_RW_DR_OFFSET))
+
+#define USBFS_DEV_ARB_REGS16_BASE (0x1210U)
+#define USBFS_DEV_ARB_REGS16_SIZE (0x40U)
+#define USBFS_DEV_ARB_RW_WA16_OFFSET (0x00U)
+#define USBFS_DEV_ARB_RW_RA16_OFFSET (0x08U)
+#define USBFS_DEV_ARB_RW_DR16_OFFSET (0x10U)
+#define USBFS_DEV_ARB_REGS_16(base, endpoint) ((uint32_t)(base) + USBFS_DEV_ARB_REGS16_BASE + ((endpoint) * USBFS_DEV_ARB_REGS16_SIZE))
+
+#define USBFS_DEV_ARB_RW_WA16(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \
+ USBFS_DEV_ARB_RW_WA16_OFFSET))
+#define USBFS_DEV_ARB_RW_RA16(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \
+ USBFS_DEV_ARB_RW_RA16_OFFSET))
+#define USBFS_DEV_ARB_RW_DR16(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \
+ USBFS_DEV_ARB_RW_DR16_OFFSET))
+
+#define USBFS_DEV_LPM_POWER_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.POWER_CTL)
+#define USBFS_DEV_LPM_USBIO_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.USBIO_CTL)
+#define USBFS_DEV_LPM_FLOW_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.FLOW_CTL)
+#define USBFS_DEV_LPM_LPM_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.LPM_CTL)
+#define USBFS_DEV_LPM_LPM_STAT(base) (((USBFS_V1_Type const *)(base))->USBLPM.LPM_STAT)
+#define USBFS_DEV_LPM_INTR_SIE(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE)
+#define USBFS_DEV_LPM_INTR_SIE_SET(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_SET)
+#define USBFS_DEV_LPM_INTR_SIE_MASK(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_MASK)
+#define USBFS_DEV_LPM_INTR_SIE_MASKED(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_MASKED)
+#define USBFS_DEV_LPM_INTR_LVL_SEL(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_LVL_SEL)
+#define USBFS_DEV_LPM_INTR_CAUSE_HI(base) (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_HI)
+#define USBFS_DEV_LPM_INTR_CAUSE_MED(base) (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_MED)
+#define USBFS_DEV_LPM_INTR_CAUSE_LO(base) (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_LO)
+#define USBFS_DEV_LPM_DFT_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.DFT_CTL)
+
+#define USBFS_HOST_CTL0(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL0)
+#define USBFS_HOST_CTL1(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL1)
+#define USBFS_HOST_CTL2(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL2)
+#define USBFS_HOST_ERR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_ERR)
+#define USBFS_HOST_STATUS(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_STATUS)
+#define USBFS_HOST_FCOMP(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_FCOMP)
+#define USBFS_HOST_RTIMER(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_RTIMER)
+#define USBFS_HOST_ADDR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_ADDR)
+#define USBFS_HOST_EOF(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EOF)
+#define USBFS_HOST_FRAME(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_FRAME)
+#define USBFS_HOST_TOKEN(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_TOKEN)
+#define USBFS_HOST_EP1_CTL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_CTL)
+#define USBFS_HOST_EP1_STATUS(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_STATUS)
+#define USBFS_HOST_EP1_RW1_DR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_RW1_DR)
+#define USBFS_HOST_EP1_RW2_DR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_RW2_DR)
+#define USBFS_HOST_EP2_CTL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_CTL)
+#define USBFS_HOST_EP2_STATUS(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_STATUS)
+#define USBFS_HOST_EP2_RW1_DR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_RW1_DR)
+#define USBFS_HOST_EP2_RW2_DR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_RW2_DR)
+#define USBFS_HOST_LVL1_SEL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_LVL1_SEL)
+#define USBFS_HOST_LVL2_SEL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_LVL2_SEL)
+#define USBFS_INTR_USBHOST_CAUSE_HI(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_HI)
+#define USBFS_INTR_USBHOST_CAUSE_MED(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_MED)
+#define USBFS_INTR_USBHOST_CAUSE_LO(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_LO)
+#define USBFS_INTR_HOST_EP_CAUSE_HI(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_HI)
+#define USBFS_INTR_HOST_EP_CAUSE_MED(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_MED)
+#define USBFS_INTR_HOST_EP_CAUSE_LO(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_LO)
+#define USBFS_INTR_USBHOST(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST)
+#define USBFS_INTR_USBHOST_SET(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_SET)
+#define USBFS_INTR_USBHOST_MASK(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_MASK)
+#define USBFS_INTR_USBHOST_MASKED(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_MASKED)
+#define USBFS_INTR_HOST_EP(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP)
+#define USBFS_INTR_HOST_EP_SET(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_SET)
+#define USBFS_INTR_HOST_EP_MASK(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_MASK)
+#define USBFS_INTR_HOST_EP_MASKED(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_MASKED)
+#define USBFS_HOST_DMA_ENBL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_DMA_ENBL)
+#define USBFS_HOST_EP1_BLK(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_BLK)
+#define USBFS_HOST_EP2_BLK(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_BLK)
+
+#endif /* CY_DEVICE_H_ */
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_dma.h b/platform/ext/target/psoc64/Native_Driver/include/cy_dma.h
new file mode 100644
index 0000000000..514ba7b8ee
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_dma.h
@@ -0,0 +1,2015 @@
+/***************************************************************************//**
+* \file cy_dma.h
+* \version 2.20
+*
+* \brief
+* The header file of the DMA driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_dma
+* \{
+* Configures a DMA channel and its descriptor(s).
+*
+* The functions and other declarations used in this driver are in cy_dma.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions
+* and declarations in the PDL.
+*
+* The DMA channel can be used in any project to transfer data
+* without CPU intervention basing on a hardware trigger signal from another component.
+*
+* A device may support more than one DMA hardware block. Each block has a set of
+* registers, a base hardware address, and supports multiple channels.
+* Many API functions for the DMA driver require a base hardware address and
+* channel number. Ensure that you use the correct hardware address for the DMA block in use.
+*
+* Features:
+* * Multiple DW blocks (device specific)
+* * Multiple channels per each DW block (device specific)
+* * Four priority levels for each channel
+* * Byte, half-word (2-byte), and word (4-byte) transfers
+* * Configurable source and destination addresses
+* * CRC calculation support (only for CPUSS_ver2)
+*
+* \section group_dma_configuration Configuration Considerations
+*
+* To set up a DMA driver, initialize a descriptor,
+* initialize and enable a channel, and enable the DMA block.
+*
+* To set up a descriptor, provide the configuration parameters for the
+* descriptor in the \ref cy_stc_dma_descriptor_config_t structure. Then call the
+* \ref Cy_DMA_Descriptor_Init function to initialize the descriptor in SRAM. You can
+* modify the source and destination addresses dynamically by calling
+* \ref Cy_DMA_Descriptor_SetSrcAddress and \ref Cy_DMA_Descriptor_SetDstAddress.
+*
+* To set up a DMA channel, provide a filled \ref cy_stc_dma_channel_config_t
+* structure. Call the \ref Cy_DMA_Channel_Init function, specifying the channel
+* number. Use \ref Cy_DMA_Channel_Enable to enable the configured DMA channel.
+*
+* Call \ref Cy_DMA_Channel_Enable for each DMA channel in use.
+*
+* When configured, another peripheral typically triggers the DMA. The trigger is
+* connected to the DMA using the trigger multiplexer. The trigger multiplexer
+* driver has a software trigger you can use in firmware to trigger the DMA. See the
+* <a href="group__group__trigmux.html">Trigger Multiplexer</a> documentation.
+*
+* The following is a simplified structure of the DMA driver API interdependencies
+* in a typical user application:
+* \image html dma.png
+*
+* <B>NOTE:</B> Even if a DMA channel is enabled, it is not operational until
+* the DMA block is enabled using function \ref Cy_DMA_Enable.\n
+* <B>NOTE:</B> If the DMA descriptor is configured to generate an interrupt,
+* the interrupt must be enabled using the \ref Cy_DMA_Channel_SetInterruptMask
+* function for each DMA channel.
+*
+* For example:
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
+*
+* \section group_dma_more_information More Information.
+* See: the DMA chapter of the device technical reference manual (TRM);
+* the DMA Component datasheet;
+* CE219940 - PSoC 6 MCU Multiple DMA Concatenation.
+*
+* \section group_dma_MISRA MISRA-C Compliance
+* The DMA driver has the following specific deviations:
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>10.3</td>
+* <td>R</td>
+* <td>A composite expression of the "essentially unsigned" type is being
+* cast to a different type category.</td>
+* <td>The value got from the bitfield physically cannot exceed the enumeration
+* that describes this bitfield. So, the code is safe by design.</td>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to object type and
+* a different pointer to object type.</td>
+* <td>This piece of code is written for DW_V2_Type only and it will be never
+* executed for DW_V1_Type (which is a default build option for DW_Type).</td>
+* </tr>
+* </table>
+*
+* \section group_dma_changelog Changelog
+*
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.20</td>
+* <td>The channel number validation method is updated.</td>
+* <td>New devices support.</td>
+* </tr>
+* <tr>
+* <td rowspan="3">2.10</td>
+* <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Added CRC mode and the CRC descriptor support. \n Added the \ref Cy_DMA_Crc_Init function.</td>
+* <td>New devices support.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>2.0.1</td>
+* <td>Changed CY_DMA_BWC macro values from Boolean to numeric</td>
+* <td>Improvements made based on usability feedback</td>
+* </tr>
+* <tr>
+* <td>2.0</td>
+* <td> * All the API is refactored to be consistent within itself and with the
+* rest of the PDL content.
+* * The descriptor API is updated as follows:
+* The \ref Cy_DMA_Descriptor_Init function sets a full bunch of descriptor
+* settings, and the rest of the descriptor API is a get/set interface
+* to each of the descriptor settings.
+* * There is a group of macros to support the backward compatibility with most
+* of the driver version 1.0 API. But, you should use
+* the new v2.0 interface in new designs (do not just copy-paste from old
+* projects). To enable the backward compatibility support, the CY_DMA_BWC
+* definition should be changed to "1".</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+
+* \defgroup group_dma_macros Macros
+* \defgroup group_dma_functions Functions
+* \{
+* \defgroup group_dma_block_functions Block Functions
+* \defgroup group_dma_channel_functions Channel Functions
+* \defgroup group_dma_descriptor_functions Descriptor Functions
+* \}
+* \defgroup group_dma_data_structures Data Structures
+* \defgroup group_dma_enums Enumerated Types
+*/
+
+#if !defined(CY_DMA_H)
+#define CY_DMA_H
+
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef CY_IP_M4CPUSS_DMA
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+
+/**
+* \addtogroup group_dma_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_DMA_DRV_VERSION_MAJOR 2
+
+/** The driver minor version */
+#define CY_DMA_DRV_VERSION_MINOR 20
+
+/** The DMA driver identifier */
+#define CY_DMA_ID (CY_PDL_DRV_ID(0x13U))
+
+/** The DMA channel interrupt mask */
+#define CY_DMA_INTR_MASK (0x01UL)
+
+/** The minimum X/Y Count API parameters */
+#define CY_DMA_LOOP_COUNT_MIN (1UL)
+/** The maximum X/Y Count API parameters */
+#define CY_DMA_LOOP_COUNT_MAX (256UL)
+
+/** The minimum X/Y Increment API parameters */
+#define CY_DMA_LOOP_INCREMENT_MIN (-2048L)
+/** The maximum X/Y Increment API parameters */
+#define CY_DMA_LOOP_INCREMENT_MAX (2047L)
+
+/** The backward compatibility flag. Enables a group of macros which provide
+* the backward compatibility with most of the DMA driver version 1.0 interface. */
+#ifndef CY_DMA_BWC
+ #define CY_DMA_BWC (0U) /* Disabled by default */
+#endif
+
+/** \} group_dma_macros */
+
+
+/**
+* \addtogroup group_dma_enums
+* \{
+*/
+
+/** Contains the possible interrupt cause values */
+typedef enum
+{
+ CY_DMA_INTR_CAUSE_NO_INTR = 0U, /**< No interrupt. */
+ CY_DMA_INTR_CAUSE_COMPLETION = 1U, /**< Completion. */
+ CY_DMA_INTR_CAUSE_SRC_BUS_ERROR = 2U, /**< Source bus error. */
+ CY_DMA_INTR_CAUSE_DST_BUS_ERROR = 3U, /**< Destination bus error. */
+ CY_DMA_INTR_CAUSE_SRC_MISAL = 4U, /**< Source address is not aligned. */
+ CY_DMA_INTR_CAUSE_DST_MISAL = 5U, /**< Destination address is not aligned. */
+ CY_DMA_INTR_CAUSE_CURR_PTR_NULL = 6U, /**< Current descriptor pointer is NULL. */
+ CY_DMA_INTR_CAUSE_ACTIVE_CH_DISABLED = 7U, /**< Active channel is disabled. */
+ CY_DMA_INTR_CAUSE_DESCR_BUS_ERROR = 8U /**< Descriptor bus error. */
+} cy_en_dma_intr_cause_t;
+
+/** Contains the options for the descriptor type */
+typedef enum
+{
+ CY_DMA_SINGLE_TRANSFER = 0UL, /**< Single transfer. */
+ CY_DMA_1D_TRANSFER = 1UL, /**< 1D transfer. */
+ CY_DMA_2D_TRANSFER = 2UL, /**< 2D transfer. */
+ CY_DMA_CRC_TRANSFER = 3UL, /**< CRC transfer. Supported by the CPUSS_ver2 only. */
+} cy_en_dma_descriptor_type_t;
+
+/** Contains the options for the interrupt, trig-in and trig-out type parameters of the descriptor */
+typedef enum
+{
+ CY_DMA_1ELEMENT = 0UL, /**< One element transfer. */
+ CY_DMA_X_LOOP = 1UL, /**< One X loop transfer. */
+ CY_DMA_DESCR = 2UL, /**< One descriptor transfer. */
+ CY_DMA_DESCR_CHAIN = 3UL /**< Entire descriptor chain transfer. */
+} cy_en_dma_trigger_type_t;
+
+/** Contains the options for the data size */
+typedef enum
+{
+ CY_DMA_BYTE = 0UL, /**< One byte. */
+ CY_DMA_HALFWORD = 1UL, /**< Half word (two bytes). */
+ CY_DMA_WORD = 2UL /**< Full word (four bytes). */
+} cy_en_dma_data_size_t;
+
+/** Contains the options for descriptor retriggering */
+typedef enum
+{
+ CY_DMA_RETRIG_IM = 0UL, /**< Retrigger immediately. */
+ CY_DMA_RETRIG_4CYC = 1UL, /**< Retrigger after 4 Clk_Slow cycles. */
+ CY_DMA_RETRIG_16CYC = 2UL, /**< Retrigger after 16 Clk_Slow cycles. */
+ CY_DMA_WAIT_FOR_REACT = 3UL /**< Wait for trigger reactivation. */
+} cy_en_dma_retrigger_t;
+
+/** Contains the options for the transfer size */
+typedef enum
+{
+ CY_DMA_TRANSFER_SIZE_DATA = 0UL, /**< As specified by dataSize. */
+ CY_DMA_TRANSFER_SIZE_WORD = 1UL, /**< A full word (four bytes). */
+} cy_en_dma_transfer_size_t;
+
+/** Contains the options for the state of the channel when the descriptor is completed */
+typedef enum
+{
+ CY_DMA_CHANNEL_ENABLED = 0UL, /**< Channel stays enabled. */
+ CY_DMA_CHANNEL_DISABLED = 1UL /**< Channel is disabled. */
+} cy_en_dma_channel_state_t;
+
+/** Contains the return values of the DMA driver */
+typedef enum
+{
+ CY_DMA_SUCCESS = 0x00UL, /**< Success. */
+ CY_DMA_BAD_PARAM = CY_DMA_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< The input parameters passed to the DMA API are not valid. */
+} cy_en_dma_status_t;
+
+/** \} group_dma_enums */
+
+
+/** \cond Internal */
+
+/* Macros for the conditions used by CY_ASSERT calls */
+#define CY_DMA_IS_LOOP_COUNT_VALID(count) (((count) >= CY_DMA_LOOP_COUNT_MIN) && ((count) <= CY_DMA_LOOP_COUNT_MAX))
+#define CY_DMA_IS_LOOP_INCR_VALID(incr) (((incr) >= CY_DMA_LOOP_INCREMENT_MIN) && ((incr) <= CY_DMA_LOOP_INCREMENT_MAX))
+#define CY_DMA_IS_PRIORITY_VALID(prio) ((prio) <= 3UL)
+#define CY_DMA_IS_INTR_MASK_VALID(intr) (0UL == ((intr) & ((uint32_t) ~CY_DMA_INTR_MASK)))
+
+#define CY_DMA_IS_RETRIG_VALID(retrig) ((CY_DMA_RETRIG_IM == (retrig)) || \
+ (CY_DMA_RETRIG_4CYC == (retrig)) || \
+ (CY_DMA_RETRIG_16CYC == (retrig)) || \
+ (CY_DMA_WAIT_FOR_REACT == (retrig)))
+
+#define CY_DMA_IS_TRIG_TYPE_VALID(trigType) ((CY_DMA_1ELEMENT == (trigType)) || \
+ (CY_DMA_X_LOOP == (trigType)) || \
+ (CY_DMA_DESCR == (trigType)) || \
+ (CY_DMA_DESCR_CHAIN == (trigType)))
+
+#define CY_DMA_IS_XFER_SIZE_VALID(xferSize) ((CY_DMA_TRANSFER_SIZE_DATA == (xferSize)) || \
+ (CY_DMA_TRANSFER_SIZE_WORD == (xferSize)))
+
+#define CY_DMA_IS_CHANNEL_STATE_VALID(state) ((CY_DMA_CHANNEL_ENABLED == (state)) || \
+ (CY_DMA_CHANNEL_DISABLED == (state)))
+
+#define CY_DMA_IS_DATA_SIZE_VALID(dataSize) ((CY_DMA_BYTE == (dataSize)) || \
+ (CY_DMA_HALFWORD == (dataSize)) || \
+ (CY_DMA_WORD == (dataSize)))
+
+#define CY_DMA_IS_TYPE_VALID(descrType) ((CY_DMA_SINGLE_TRANSFER == (descrType)) || \
+ (CY_DMA_1D_TRANSFER == (descrType)) || \
+ (CY_DMA_2D_TRANSFER == (descrType)) || \
+ (CY_DMA_CRC_TRANSFER == (descrType)))
+
+#define CY_DMA_IS_CH_NR_VALID(base, chNr) ((CY_DW0_BASE == (base)) ? ((chNr) < CY_DW0_CH_NR) : \
+ ((chNr) < CY_DW1_CH_NR))
+
+/* The descriptor structure bit field definitions */
+#define CY_DMA_CTL_RETRIG_Pos (0UL)
+#define CY_DMA_CTL_RETRIG_Msk ((uint32_t)0x3UL << CY_DMA_CTL_RETRIG_Pos)
+#define CY_DMA_CTL_INTR_TYPE_Pos (2UL)
+#define CY_DMA_CTL_INTR_TYPE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_INTR_TYPE_Pos)
+#define CY_DMA_CTL_TR_OUT_TYPE_Pos (4UL)
+#define CY_DMA_CTL_TR_OUT_TYPE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_TR_OUT_TYPE_Pos)
+#define CY_DMA_CTL_TR_IN_TYPE_Pos (6UL)
+#define CY_DMA_CTL_TR_IN_TYPE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_TR_IN_TYPE_Pos)
+#define CY_DMA_CTL_CH_DISABLE_Pos (24UL)
+#define CY_DMA_CTL_CH_DISABLE_Msk ((uint32_t)0x1UL << CY_DMA_CTL_CH_DISABLE_Pos)
+#define CY_DMA_CTL_SRC_SIZE_Pos (26UL)
+#define CY_DMA_CTL_SRC_SIZE_Msk ((uint32_t)0x1UL << CY_DMA_CTL_SRC_SIZE_Pos)
+#define CY_DMA_CTL_DST_SIZE_Pos (27UL)
+#define CY_DMA_CTL_DST_SIZE_Msk ((uint32_t)0x1UL << CY_DMA_CTL_DST_SIZE_Pos)
+#define CY_DMA_CTL_DATA_SIZE_Pos (28UL)
+#define CY_DMA_CTL_DATA_SIZE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_DATA_SIZE_Pos)
+#define CY_DMA_CTL_TYPE_Pos (30UL)
+#define CY_DMA_CTL_TYPE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_TYPE_Pos)
+
+#define CY_DMA_CTL_SRC_INCR_Pos (0UL)
+#define CY_DMA_CTL_SRC_INCR_Msk ((uint32_t)0xFFFUL << CY_DMA_CTL_SRC_INCR_Pos)
+#define CY_DMA_CTL_DST_INCR_Pos (12UL)
+#define CY_DMA_CTL_DST_INCR_Msk ((uint32_t)0xFFFUL << CY_DMA_CTL_DST_INCR_Pos)
+#define CY_DMA_CTL_COUNT_Pos (24UL)
+#define CY_DMA_CTL_COUNT_Msk ((uint32_t)0xFFUL << CY_DMA_CTL_COUNT_Pos)
+
+/** \endcond */
+
+
+/**
+* \addtogroup group_dma_data_structures
+* \{
+*/
+
+/**
+* DMA descriptor structure type. It is a user/component-declared structure
+* allocated in RAM. The DMA HW requires a pointer to this structure to work with it.
+*
+* For advanced users: the descriptor can be allocated even in flash, then the user
+* manually predefines all the structure items with constants. This is
+* because most of the driver's API (especially functions modifying
+* descriptors, including \ref Cy_DMA_Descriptor_Init()) can't work with
+* read-only descriptors.
+*/
+typedef struct
+{
+ uint32_t ctl; /*!< 0x00000000 Descriptor control */
+ uint32_t src; /*!< 0x00000004 Descriptor source */
+ uint32_t dst; /*!< 0x00000008 Descriptor destination */
+ uint32_t xCtl; /*!< 0x0000000C Descriptor X loop control */
+ uint32_t yCtl; /*!< 0x00000010 Descriptor Y loop control */
+ uint32_t nextPtr; /*!< 0x00000014 Descriptor next pointer */
+} cy_stc_dma_descriptor_t;
+
+/**
+* This structure is a configuration structure pre-initialized by the user and
+* passed as a parameter to the \ref Cy_DMA_Descriptor_Init().
+* It can be allocated in RAM/flash (the user's choice).
+* In case of flash allocation, there is a possibility to reinitialize the descriptor in runtime.
+* This structure has all the parameters of the descriptor as separate parameters.
+* Most of these parameters are represented in the \ref cy_stc_dma_descriptor_t structure as bitfields.
+*/
+typedef struct
+{
+ cy_en_dma_retrigger_t retrigger; /**< Specifies whether the DW controller should wait for the input trigger to be deactivated. */
+ cy_en_dma_trigger_type_t interruptType; /**< Sets the event that triggers an interrupt. See \ref cy_en_dma_trigger_type_t. */
+ cy_en_dma_trigger_type_t triggerOutType; /**< Sets the event that triggers an output. See \ref cy_en_dma_trigger_type_t. */
+ cy_en_dma_channel_state_t channelState; /**< Specifies whether the channel is enabled or disabled on completion of descriptor. See \ref cy_en_dma_channel_state_t. */
+ cy_en_dma_trigger_type_t triggerInType; /**< Sets what type of transfer is triggered. See \ref cy_en_dma_trigger_type_t. */
+ cy_en_dma_data_size_t dataSize; /**< The size of the data bus for transfer. See \ref cy_en_dma_data_size_t. */
+ cy_en_dma_transfer_size_t srcTransferSize; /**< The source transfer size. */
+ cy_en_dma_transfer_size_t dstTransferSize; /**< The destination transfer size. */
+ cy_en_dma_descriptor_type_t descriptorType; /**< The type of the descriptor. See \ref cy_en_dma_descriptor_type_t. */
+ void * srcAddress; /**< The source address of the transfer. */
+ void * dstAddress; /**< The destination address of the transfer.
+ * For CPUSS_ver2 only: for CRC transfer, the CRC result without post-processing
+ * (reversing and/or XORing, if used) is placed into the dstAddress.
+ */
+ int32_t srcXincrement; /**< The address increment of the source after each X-loop transfer. Valid range is -2048 ... 2047. */
+ int32_t dstXincrement; /**< The address increment of the destination after each X-loop transfer. Valid range is -2048 ... 2047. */
+ uint32_t xCount; /**< The number of transfers in an X-loop. Valid range is 1 ... 256. */
+ int32_t srcYincrement; /**< The address increment of the source after each Y-loop transfer. Valid range is -2048 ... 2047. */
+ int32_t dstYincrement; /**< The address increment of the destination after each Y-loop transfer. Valid range is -2048 ... 2047. */
+ uint32_t yCount; /**< The number of X-loops in the Y-loop. Valid range is 1 ... 256. */
+ cy_stc_dma_descriptor_t * nextDescriptor; /**< The next descriptor to chain after completion. A NULL value will signify no chaining. */
+} cy_stc_dma_descriptor_config_t;
+
+/** This structure holds the initialization values for the DMA channel */
+typedef struct
+{
+ cy_stc_dma_descriptor_t * descriptor; /**< The DMA descriptor associated with the channel being initialized. */
+ bool preemptable; /**< Specifies whether the channel is preemptable by another higher-priority channel. */
+ uint32_t priority; /**< This parameter specifies the channel's priority. */
+ bool enable; /**< This parameter specifies whether the channel is enabled after initializing. */
+ bool bufferable; /**< This parameter specifies whether a write transaction can complete.
+ without waiting for the destination to accept the write transaction data. */
+} cy_stc_dma_channel_config_t;
+
+
+/** This structure holds the initialization values for the CRC feature, only for CPUSS_ver2 */
+typedef struct
+{
+ bool dataReverse; /**< Specifies the bit order in which a data byte is processed (reversal is performed after XORing):
+ * 'false': Most significant bit (bit 1) first.
+ * 'true': Least significant bit (bit 0) first.
+ */
+ uint32_t dataXor; /**< Specifies a byte mask with which each data byte is XORed. The XOR is performed before data reversal. */
+ bool reminderReverse; /**< Specifies whether the remainder is bit reversed (reversal is performed after XORing).
+ * Note: this parameter doesn't affect the CRC value stored into the dstAddress.
+ * The reversed value remains in the CRC_REM_RESULT register.
+ */
+ uint32_t reminderXor; /**< Specifies a mask with which the remainder is XORed. The XOR is performed before remainder reversal.
+ * Note: this parameter doesn't affect the CRC value stored into the dstAddress.
+ * The XORed value remains in the CRC_REM_RESULT register.
+ */
+ uint32_t polynomial; /**< CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1').
+ * The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial
+ * and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials:
+ * - CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1).
+ * - CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions).
+ * - CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions).
+ */
+ uint32_t lfsrInitVal; /**< The initial value of the Linear Feedback Shift Register */
+} cy_stc_dma_crc_config_t;
+
+/** \} group_dma_data_structures */
+
+
+/**
+* \addtogroup group_dma_functions
+* \{
+*/
+
+
+/**
+* \addtogroup group_dma_block_functions
+* \{
+*/
+
+
+__STATIC_INLINE void Cy_DMA_Enable (DW_Type * base);
+__STATIC_INLINE void Cy_DMA_Disable (DW_Type * base);
+__STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel (DW_Type const * base);
+__STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type * base);
+__STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type * base);
+ cy_en_dma_status_t Cy_DMA_Crc_Init (DW_Type * base, cy_stc_dma_crc_config_t const * crcConfig);
+
+/** \} group_dma_block_functions */
+
+
+/**
+* \addtogroup group_dma_channel_functions
+* \{
+*/
+ cy_en_dma_status_t Cy_DMA_Channel_Init (DW_Type * base, uint32_t channel, cy_stc_dma_channel_config_t const * channelConfig);
+ void Cy_DMA_Channel_DeInit (DW_Type * base, uint32_t channel);
+__STATIC_INLINE void Cy_DMA_Channel_SetDescriptor (DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE void Cy_DMA_Channel_Enable (DW_Type * base, uint32_t channel);
+__STATIC_INLINE void Cy_DMA_Channel_Disable (DW_Type * base, uint32_t channel);
+__STATIC_INLINE void Cy_DMA_Channel_SetPriority (DW_Type * base, uint32_t channel, uint32_t priority);
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority (DW_Type const * base, uint32_t channel);
+__STATIC_INLINE
+ cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus (DW_Type const * base, uint32_t channel);
+__STATIC_INLINE
+cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor (DW_Type const * base, uint32_t channel);
+
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus (DW_Type const * base, uint32_t channel);
+__STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt (DW_Type * base, uint32_t channel);
+__STATIC_INLINE void Cy_DMA_Channel_SetInterrupt (DW_Type * base, uint32_t channel);
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask (DW_Type const * base, uint32_t channel);
+__STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask (DW_Type * base, uint32_t channel, uint32_t interrupt);
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel);
+
+/** \} group_dma_channel_functions */
+
+
+/**
+* \addtogroup group_dma_descriptor_functions
+* \{
+*/
+
+ cy_en_dma_status_t Cy_DMA_Descriptor_Init (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_config_t const * config);
+ void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor);
+
+ void Cy_DMA_Descriptor_SetNextDescriptor (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor);
+ void Cy_DMA_Descriptor_SetDescriptorType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress (cy_stc_dma_descriptor_t * descriptor, void const * srcAddress);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress (cy_stc_dma_descriptor_t * descriptor, void const * dstAddress);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount (cy_stc_dma_descriptor_t * descriptor, uint32_t xCount);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount (cy_stc_dma_descriptor_t * descriptor, uint32_t yCount);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcXincrement);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstYincrement);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t srcTransferSize);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState);
+
+ cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState (cy_stc_dma_descriptor_t const * descriptor);
+
+/** \} group_dma_descriptor_functions */
+
+
+
+/***************************************
+* In-line Function Implementation
+***************************************/
+
+
+/**
+* \addtogroup group_dma_block_functions
+* \{
+*/
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Enable
+****************************************************************************//**
+*
+* Enables the DMA block.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Enable(DW_Type * base)
+{
+ DW_CTL(base) |= DW_CTL_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Disable
+****************************************************************************//**
+*
+* Disables the DMA block.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Disable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Disable(DW_Type * base)
+{
+ DW_CTL(base) &= (uint32_t) ~DW_CTL_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_GetActiveChannel
+****************************************************************************//**
+*
+* Returns the status of the active/pending channels.
+* the DMA block.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \return
+* Returns a bit-field with all of the currently active/pending channels in the
+* DMA block.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Disable
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel(DW_Type const * base)
+{
+ return(_FLD2VAL(CY_DW_STATUS_CH_IDX, DW_STATUS(base)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_GetActiveSrcAddress
+****************************************************************************//**
+*
+* Returns the source address being used for the current transfer.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \return
+* Returns the pointer to the source of transfer.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_GetActiveSrcAddress
+*
+*******************************************************************************/
+__STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type * base)
+{
+ return ((void *) DW_DESCR_SRC(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_GetActiveDstAddress
+****************************************************************************//**
+*
+* Returns the destination address being used for the current transfer.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \return
+* Returns the pointer to the destination of transfer.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_GetActiveSrcAddress
+*
+*******************************************************************************/
+__STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type * base)
+{
+ return ((void *) DW_DESCR_DST(base));
+}
+
+/** \} group_dma_block_functions */
+
+/**
+* \addtogroup group_dma_descriptor_functions
+* \{
+*/
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetSrcAddress
+****************************************************************************//**
+*
+* Sets the source address for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param srcAddress
+* The source address value for the descriptor.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress(cy_stc_dma_descriptor_t * descriptor, void const * srcAddress)
+{
+ descriptor->src = (uint32_t) srcAddress;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetSrcAddress
+****************************************************************************//**
+*
+* Returns the source address parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The source address value of the descriptor.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress(cy_stc_dma_descriptor_t const * descriptor)
+{
+ return ((void *) descriptor->src);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetDstAddress
+****************************************************************************//**
+*
+* Sets the destination address for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param dstAddress
+* The destination address value for the descriptor.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress(cy_stc_dma_descriptor_t * descriptor, void const * dstAddress)
+{
+ descriptor->dst = (uint32_t) dstAddress;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetDstAddress
+****************************************************************************//**
+*
+* Returns the destination address parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The destination address value of the descriptor.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress(cy_stc_dma_descriptor_t const * descriptor)
+{
+ return ((void *) descriptor->dst);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetInterruptType
+****************************************************************************//**
+*
+* Sets the interrupt type for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param interruptType
+* The interrupt type set for the descriptor. \ref cy_en_dma_trigger_type_t
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType)
+{
+ CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(interruptType));
+
+ CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_INTR_TYPE, interruptType);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetInterruptType
+****************************************************************************//**
+*
+* Returns the Interrupt-Type of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Interrupt-Type \ref cy_en_dma_trigger_type_t.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType(cy_stc_dma_descriptor_t const * descriptor)
+{
+ return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_INTR_TYPE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetTriggerInType
+****************************************************************************//**
+*
+* Sets the Trigger-In-Type for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param triggerInType
+* The Trigger In Type parameter \ref cy_en_dma_trigger_type_t
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType)
+{
+ CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerInType));
+
+ CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TR_IN_TYPE, triggerInType);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetTriggerInType
+****************************************************************************//**
+*
+* Returns the Trigger-In-Type parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Trigger-In-Type \ref cy_en_dma_trigger_type_t
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType(cy_stc_dma_descriptor_t const * descriptor)
+{
+ return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_IN_TYPE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetTriggerOutType
+****************************************************************************//**
+*
+* Sets the Trigger-Out-Type for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param triggerOutType
+* The Trigger-Out-Type set for the descriptor. \ref cy_en_dma_trigger_type_t
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType)
+{
+ CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerOutType));
+
+ CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TR_OUT_TYPE, triggerOutType);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetTriggerOutType
+****************************************************************************//**
+*
+* Returns the Trigger-Out-Type parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Trigger-Out-Type parameter \ref cy_en_dma_trigger_type_t.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType(cy_stc_dma_descriptor_t const * descriptor)
+{
+ return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_OUT_TYPE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetDataSize
+****************************************************************************//**
+*
+* Sets the Data Element Size for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param dataSize
+* The Data Element Size \ref cy_en_dma_data_size_t
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize)
+{
+ CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(dataSize));
+
+ CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_DATA_SIZE, dataSize);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetDataSize
+****************************************************************************//**
+*
+* Returns the Data Element Size parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Data Element Size \ref cy_en_dma_data_size_t.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize(cy_stc_dma_descriptor_t const * descriptor)
+{
+ return((cy_en_dma_data_size_t) _FLD2VAL(CY_DMA_CTL_DATA_SIZE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetSrcTransferSize
+****************************************************************************//**
+*
+* Sets the Source Transfer Size for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param srcTransferSize
+* The Source Transfer Size \ref cy_en_dma_transfer_size_t.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t srcTransferSize)
+{
+ CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(srcTransferSize));
+
+ CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_SRC_SIZE, srcTransferSize);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetSrcTransferSize
+****************************************************************************//**
+*
+* Returns the Source Transfer Size parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Source Transfer Size \ref cy_en_dma_transfer_size_t.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize(cy_stc_dma_descriptor_t const * descriptor)
+{
+ return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_SRC_SIZE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetDstTransferSize
+****************************************************************************//**
+*
+* Sets the Destination Transfer Size for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param dstTransferSize
+* The Destination Transfer Size \ref cy_en_dma_transfer_size_t.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize)
+{
+ CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(dstTransferSize));
+
+ CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_DST_SIZE, dstTransferSize);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetDstTransferSize
+****************************************************************************//**
+*
+* Returns the Destination Transfer Size parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Destination Transfer Size \ref cy_en_dma_transfer_size_t.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize(cy_stc_dma_descriptor_t const * descriptor)
+{
+ return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_DST_SIZE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetRetrigger
+****************************************************************************//**
+*
+* Sets the retrigger value that specifies whether the controller should
+* wait for the input trigger to be deactivated.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param retrigger
+* The \ref cy_en_dma_retrigger_t parameter specifies whether the controller
+* should wait for the input trigger to be deactivated.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger)
+{
+ CY_ASSERT_L3(CY_DMA_IS_RETRIG_VALID(retrigger));
+
+ CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_RETRIG, retrigger);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetRetrigger
+****************************************************************************//**
+*
+* Returns a value that specifies whether the controller should
+* wait for the input trigger to be deactivated.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Retrigger setting \ref cy_en_dma_retrigger_t.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_descriptor_t const * descriptor)
+{
+ return((cy_en_dma_retrigger_t) _FLD2VAL(CY_DMA_CTL_RETRIG, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetDescriptorType
+****************************************************************************//**
+*
+* Returns the descriptor's type of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The descriptor type \ref cy_en_dma_descriptor_type_t.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType(cy_stc_dma_descriptor_t const * descriptor)
+{
+ return((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetChannelState
+****************************************************************************//**
+*
+* Sets the channel state on completion of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param channelState
+* The channel state \ref cy_en_dma_channel_state_t.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState)
+{
+ CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(channelState));
+
+ CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_CH_DISABLE, channelState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetChannelState
+****************************************************************************//**
+*
+* Returns the channel state on completion of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Channel State setting \ref cy_en_dma_channel_state_t.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState(cy_stc_dma_descriptor_t const * descriptor)
+{
+ return((cy_en_dma_channel_state_t) _FLD2VAL(CY_DMA_CTL_CH_DISABLE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetXloopDataCount
+****************************************************************************//**
+*
+* Sets the number of data elements to transfer in the X loop
+* for the specified descriptor (for 1D or 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param xCount
+* The number of data elements to transfer in the X loop. Valid range is 1 ... 256.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t xCount)
+{
+ CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ CY_ASSERT_L2(CY_DMA_IS_LOOP_COUNT_VALID(xCount));
+ /* Convert the data count from the user's range (1-256) into the machine range (0-255). */
+ CY_REG32_CLR_SET(descriptor->xCtl, CY_DMA_CTL_COUNT, xCount - 1UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetXloopDataCount
+****************************************************************************//**
+*
+* Returns the number of data elements for the X loop of the specified
+* descriptor (for 1D or 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The number of data elements to transfer in the X loop. The range is 1 ... 256.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ /* Convert the data count from the machine range (0-255) into the user's range (1-256). */
+ return (_FLD2VAL(CY_DMA_CTL_COUNT, descriptor->xCtl) + 1UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetXloopSrcIncrement
+****************************************************************************//**
+*
+* Sets the source increment parameter for the X loop of the specified
+* descriptor (for 1D or 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param srcXincrement
+* The value of the source increment. The valid range is -2048 ... 2047.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcXincrement)
+{
+ CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(srcXincrement));
+
+ CY_REG32_CLR_SET(descriptor->xCtl, CY_DMA_CTL_SRC_INCR, srcXincrement);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetXloopSrcIncrement
+****************************************************************************//**
+*
+* Returns the source increment parameter for the X loop of the specified
+* descriptor (for 1D or 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The value of the source increment. The range is -2048 ... 2047.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+
+ return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->xCtl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetXloopDstIncrement
+****************************************************************************//**
+*
+* Sets the destination increment parameter for the X loop for the specified
+* descriptor (for 1D or 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param dstXincrement
+* The value of the destination increment. The valid range is -2048 ... 2047.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement)
+{
+ CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(dstXincrement));
+
+ CY_REG32_CLR_SET(descriptor->xCtl, CY_DMA_CTL_DST_INCR, dstXincrement);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetXloopDstIncrement
+****************************************************************************//**
+*
+* Returns the destination increment parameter for the X loop of the specified
+* descriptor (for 1D or 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The value of the destination increment. The range is -2048 ... 2047.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+
+ return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->xCtl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetYloopDataCount
+****************************************************************************//**
+*
+* Sets the number of data elements for the Y loop of the specified descriptor
+* (for 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param yCount
+* The number of X loops to execute in the Y loop. The valid range is 1 ... 256.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t yCount)
+{
+ CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ CY_ASSERT_L2(CY_DMA_IS_LOOP_COUNT_VALID(yCount));
+ /* Convert the data count from the user's range (1-256) into the machine range (0-255). */
+ CY_REG32_CLR_SET(descriptor->yCtl, CY_DMA_CTL_COUNT, yCount - 1UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetYloopDataCount
+****************************************************************************//**
+*
+* Returns the number of X loops to execute in the Y loop of the specified
+* descriptor (for 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The number of X loops to execute in the Y loop. The range is 1 ... 256.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ /* Convert the data count from the machine range (0-255) into the user's range (1-256). */
+ return (_FLD2VAL(CY_DMA_CTL_COUNT, descriptor->yCtl) + 1UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetYloopSrcIncrement
+****************************************************************************//**
+*
+* Sets the source increment parameter for the Y loop for the specified
+* descriptor (for 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param srcYincrement
+* The value of the source increment. The valid range is -2048 ... 2047.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement)
+{
+ CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(srcYincrement));
+
+ CY_REG32_CLR_SET(descriptor->yCtl, CY_DMA_CTL_SRC_INCR, srcYincrement);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetYloopSrcIncrement
+****************************************************************************//**
+*
+* Returns the source increment parameter for the outer Y of the specified
+* descriptor (for 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The value of the source increment. The range is -2048 ... 2047.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+
+ return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->yCtl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetYloopDstIncrement
+****************************************************************************//**
+*
+* Sets the destination increment parameter for the Y loop of the specified
+* descriptor (for 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param dstYincrement
+* The value of the destination increment. The valid range is -2048 ... 2047.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstYincrement)
+{
+ CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(dstYincrement));
+
+ CY_REG32_CLR_SET(descriptor->yCtl, CY_DMA_CTL_DST_INCR, dstYincrement);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetYloopDstIncrement
+****************************************************************************//**
+*
+* Returns the destination increment parameter for the Y loop of the specified
+* descriptor (for 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The value of the destination increment. The range is -2048 ... 2047.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
+*
+*******************************************************************************/
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+
+ return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->yCtl));
+}
+
+
+/** \} group_dma_descriptor_functions */
+
+
+/**
+* \addtogroup group_dma_channel_functions
+* \{
+*/
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_SetDescriptor
+****************************************************************************//**
+*
+* Sets a descriptor as current for the specified DMA channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \param descriptor
+* This is the descriptor to be associated with the channel.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
+
+ DW_CH_CURR_PTR(base, channel) = (uint32_t)descriptor;
+ DW_CH_IDX(base, channel) &= (uint32_t) ~(DW_CH_STRUCT_CH_IDX_X_IDX_Msk | DW_CH_STRUCT_CH_IDX_Y_IDX_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_Enable
+****************************************************************************//**
+*
+* The function is used to enable a DMA channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_Enable(DW_Type * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
+
+ DW_CH_CTL(base, channel) |= DW_CH_STRUCT_CH_CTL_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_Disable
+****************************************************************************//**
+*
+* The function is used to disable a DMA channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Disable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_Disable(DW_Type * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
+
+ DW_CH_CTL(base, channel) &= (uint32_t) ~DW_CH_STRUCT_CH_CTL_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_SetPriority
+****************************************************************************//**
+*
+* The function is used to set a priority for the DMA channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \param priority
+* The priority to be set for the DMA channel. The allowed values are 0,1,2,3.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_SetPriority(DW_Type * base, uint32_t channel, uint32_t priority)
+{
+ CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
+ CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(priority));
+
+ CY_REG32_CLR_SET(DW_CH_CTL(base, channel), CY_DW_CH_CTL_PRIO, priority);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_GetPriority
+****************************************************************************//**
+*
+* Returns the priority of the DMA channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \return
+* The priority of the channel.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Disable
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority(DW_Type const * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
+
+ return ((uint32_t) _FLD2VAL(CY_DW_CH_CTL_PRIO, DW_CH_CTL(base, channel)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_GetCurrentDescriptor
+****************************************************************************//**
+*
+* Returns the descriptor that is active in the channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \return
+* The pointer to the descriptor associated with the channel.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_Deinit
+*
+*******************************************************************************/
+__STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
+
+ return ((cy_stc_dma_descriptor_t*)(DW_CH_CURR_PTR(base, channel)));
+}
+
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_GetInterruptStatus
+****************************************************************************//**
+*
+* Returns the interrupt status of the specified channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \return
+* The status of an interrupt for the specified channel.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_GetInterruptStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
+
+ return (DW_CH_INTR(base, channel));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_GetStatus
+****************************************************************************//**
+*
+* Returns the interrupt reason of the specified channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \return
+* The cause \ref cy_en_dma_intr_cause_t of the interrupt.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
+
+ return ((cy_en_dma_intr_cause_t) _FLD2VAL(DW_CH_STRUCT_CH_STATUS_INTR_CAUSE, DW_CH_STATUS(base, channel)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_ClearInterrupt
+****************************************************************************//**
+*
+* Clears the interrupt status of the specified channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt(DW_Type * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
+
+ DW_CH_INTR(base, channel) = CY_DMA_INTR_MASK;
+ (void) DW_CH_INTR(base, channel);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_SetInterrupt
+****************************************************************************//**
+*
+* Sets the interrupt for the specified channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_SetInterrupt(DW_Type * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
+
+ DW_CH_INTR_SET(base, channel) = CY_DMA_INTR_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_GetInterruptMask
+****************************************************************************//**
+*
+* Returns the interrupt mask value of the specified channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \return
+* The interrupt mask value.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask(DW_Type const * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
+
+ return (DW_CH_INTR_MASK(base, channel));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_SetInterruptMask
+****************************************************************************//**
+*
+* Sets an interrupt mask value for the specified channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \param interrupt
+* The interrupt mask:
+* CY_DMA_INTR_MASK to enable the interrupt or 0UL to disable the interrupt.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask(DW_Type * base, uint32_t channel, uint32_t interrupt)
+{
+ CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
+ CY_ASSERT_L2(CY_DMA_IS_INTR_MASK_VALID(interrupt));
+ DW_CH_INTR_MASK(base, channel) = interrupt;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the logical AND of the corresponding INTR and INTR_MASK fields
+* in a single-load operation.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \funcusage
+* \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
+
+ return (DW_CH_INTR_MASKED(base, channel));
+}
+
+
+/** \} group_dma_channel_functions */
+
+/** \} group_dma_functions */
+
+
+/** \cond The definitions to support the backward compatibility, do not use them in new designs */
+
+#if(0U != CY_DMA_BWC)
+
+ /* Type definitions */
+ #define cy_stc_dma_chnl_config_t cy_stc_dma_channel_config_t
+ #define cy_stc_dma_descr_t cy_stc_dma_descriptor_t
+ #define cy_stc_dma_descr_config_t cy_stc_dma_descriptor_config_t
+ #define cy_en_dma_trig_type_t cy_en_dma_trigger_type_t
+
+ /* Structure items */
+ #define DMA_Descriptor descriptor
+ #define deact retrigger
+ #define intrType interruptType
+ #define chStateAtCmplt channelState
+ #define srcTxfrSize srcTransferSize
+ #define destTxfrSize dstTransferSize
+ #define trigoutType triggerOutType
+ #define triginType triggerInType
+ #define descrType descriptorType
+ #define srcAddr srcAddress
+ #define destAddr dstAddress
+ #define srcXincr srcXincrement
+ #define srcYincr srcYincrement
+ #define destXincr dstXincrement
+ #define destYincr dstYincrement
+ #define descrNext nextDescriptor
+
+ /* Constants */
+ #define CY_DMA_CH_DISABLED (CY_DMA_CHANNEL_DISABLED)
+ #define CY_DMA_CH_ENABLED (CY_DMA_CHANNEL_ENABLED)
+
+ #define CY_DMA_TXFR_SIZE_DATA_SIZE (CY_DMA_TRANSFER_SIZE_DATA)
+ #define CY_DMA_TXFR_SIZE_WORD (CY_DMA_TRANSFER_SIZE_WORD)
+
+ #define CY_DMA_INTR_1ELEMENT_CMPLT (CY_DMA_1ELEMENT)
+ #define CY_DMA_INTR_X_LOOP_CMPLT (CY_DMA_X_LOOP)
+ #define CY_DMA_INTR_DESCR_CMPLT (CY_DMA_DESCR)
+ #define CY_DMA_INTR_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN)
+
+ #define CY_DMA_TRIGOUT_1ELEMENT_CMPLT (CY_DMA_1ELEMENT)
+ #define CY_DMA_TRIGOUT_X_LOOP_CMPLT (CY_DMA_X_LOOP)
+ #define CY_DMA_TRIGOUT_DESCR_CMPLT (CY_DMA_DESCR)
+ #define CY_DMA_TRIGOUT_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN)
+
+ #define CY_DMA_TRIGIN_1ELEMENT (CY_DMA_1ELEMENT)
+ #define CY_DMA_TRIGIN_XLOOP (CY_DMA_X_LOOP)
+ #define CY_DMA_TRIGIN_DESCR (CY_DMA_DESCR)
+ #define CY_DMA_TRIGIN_DESCRCHAIN (CY_DMA_DESCR_CHAIN)
+
+ #define CY_DMA_INVALID_INPUT_PARAMETERS (CY_DMA_BAD_PARAM)
+
+ #define CY_DMA_RETDIG_IM (CY_DMA_RETRIG_IM)
+ #define CY_DMA_RETDIG_4CYC (CY_DMA_RETRIG_4CYC)
+ #define CY_DMA_RETDIG_16CYC (CY_DMA_RETRIG_16CYC)
+
+ /* Descriptor structure items */
+ #define DESCR_CTL ctl
+ #define DESCR_SRC src
+ #define DESCR_DST dst
+ #define DESCR_X_CTL xCtl
+ #define DESCR_Y_CTL yCtl
+ #define DESCR_NEXT_PTR nextPtr
+
+ /* Descriptor structure bitfields */
+ #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Pos 2UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Msk 0xCUL
+ #define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Pos 4UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Msk 0x30UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Pos 6UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Msk 0xC0UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Pos 24UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Msk 0x1000000UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Pos 26UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Msk 0x4000000UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Pos 27UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Msk 0x8000000UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Pos 28UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk 0x30000000UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Pos 30UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Msk 0xC0000000UL
+ #define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Pos 0UL
+ #define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL
+ #define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Pos 0UL
+ #define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Msk 0xFFFFFFFFUL
+ #define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Pos 0UL
+ #define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Msk 0xFFFUL
+ #define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Pos 12UL
+ #define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Msk 0xFFF000UL
+ #define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Pos 24UL
+ #define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Msk 0xFF000000UL
+ #define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Pos 0UL
+ #define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Msk 0xFFFUL
+ #define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Pos 12UL
+ #define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Msk 0xFFF000UL
+ #define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Pos 24UL
+ #define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Msk 0xFF000000UL
+ #define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Pos 2UL
+ #define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL
+
+ /* Functions */
+ #define Cy_DMA_GetActiveChnl Cy_DMA_GetActiveChannel
+ #define Cy_DMA_GetActiveSrcAddr Cy_DMA_GetActiveSrcAddress
+ #define Cy_DMA_GetActiveDstAddr Cy_DMA_GetActiveDstAddress
+ #define Cy_DMA_Descr_Init Cy_DMA_Descriptor_Init
+ #define Cy_DMA_Descr_DeInit Cy_DMA_Descriptor_DeInit
+ #define Cy_DMA_Descr_SetSrcAddr Cy_DMA_Descriptor_SetSrcAddress
+ #define Cy_DMA_Descr_SetDestAddr Cy_DMA_Descriptor_SetDstAddress
+ #define Cy_DMA_Descr_SetNxtDescr Cy_DMA_Descriptor_SetNextDescriptor
+ #define Cy_DMA_Descr_SetIntrType Cy_DMA_Descriptor_SetInterruptType
+ #define Cy_DMA_Descr_SetTrigInType Cy_DMA_Descriptor_SetTriggerInType
+ #define Cy_DMA_Descr_SetTrigOutType Cy_DMA_Descriptor_SetTriggerOutType
+ #define Cy_DMA_Chnl_Init Cy_DMA_Channel_Init
+ #define Cy_DMA_Chnl_DeInit Cy_DMA_Channel_DeInit
+ #define Cy_DMA_Chnl_SetDescr Cy_DMA_Channel_SetDescriptor
+ #define Cy_DMA_Chnl_Enable Cy_DMA_Channel_Enable
+ #define Cy_DMA_Chnl_Disable Cy_DMA_Channel_Disable
+ #define Cy_DMA_Chnl_GetCurrentDescr Cy_DMA_Channel_GetCurrentDescriptor
+ #define Cy_DMA_Chnl_SetPriority Cy_DMA_Channel_SetPriority
+ #define Cy_DMA_Chnl_GetPriority Cy_DMA_Channel_GetPriority
+ #define Cy_DMA_Chnl_GetInterruptStatus Cy_DMA_Channel_GetInterruptStatus
+ #define Cy_DMA_Chnl_GetInterruptCause Cy_DMA_Channel_GetStatus
+ #define Cy_DMA_Chnl_ClearInterrupt Cy_DMA_Channel_ClearInterrupt
+ #define Cy_DMA_Chnl_SetInterrupt Cy_DMA_Channel_SetInterrupt
+ #define Cy_DMA_Chnl_GetInterruptMask Cy_DMA_Channel_GetInterruptMask
+ #define Cy_DMA_Chnl_GetInterruptStatusMasked Cy_DMA_Channel_GetInterruptStatusMasked
+ #define Cy_DMA_Chnl_SetInterruptMask(base, channel) (Cy_DMA_Channel_SetInterruptMask(base, channel, CY_DMA_INTR_MASK))
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descr_SetTxfrWidth
+****************************************************************************//**
+* This is a legacy API function. It is left here just for backward compatibility.
+* Do not use it in new designs.
+*******************************************************************************/
+ __STATIC_INLINE void Cy_DMA_Descr_SetTxfrWidth(cy_stc_dma_descr_t * descriptor,
+ uint32_t dataElementSize,
+ uint32_t srcTxfrWidth,
+ uint32_t dstTxfrWidth)
+ {
+ uint32_t regValue;
+ regValue = descriptor->ctl & ((uint32_t)(~(DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk |
+ DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Msk |
+ DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Msk)));
+
+ descriptor->ctl = regValue |
+ _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE, dataElementSize) |
+ _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE, srcTxfrWidth) |
+ _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE, dstTxfrWidth);
+ }
+
+#endif /* CY_DMA_BWC */
+
+/** \endcond */
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_IP_M4CPUSS_DMA */
+
+#endif /* (CY_DMA_H) */
+
+/** \} group_dma */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_flash.h b/platform/ext/target/psoc64/Native_Driver/include/cy_flash.h
new file mode 100644
index 0000000000..ad3c50820e
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_flash.h
@@ -0,0 +1,504 @@
+/***************************************************************************//**
+* \file cy_flash.h
+* \version 3.30.2
+*
+* Provides the API declarations of the Flash driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#if !defined(CY_FLASH_H)
+#define CY_FLASH_H
+
+/**
+* \addtogroup group_flash
+* \{
+* Internal flash memory programming
+*
+* The functions and other declarations used in this driver are in cy_flash.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions
+* and declarations in the PDL.
+*
+* Flash memory in PSoC devices provides non-volatile storage for user firmware,
+* user configuration data, and bulk data storage.
+*
+* Flash operations are implemented as system calls. System calls are executed
+* out of SROM in the privileged mode of operation. Users have no access to read
+* or modify the SROM code. The driver API requests the system call by acquiring
+* the Inter-processor communication (IPC) and writing the SROM function opcode
+* and parameters to its input registers. As a result, an NMI interrupt is invoked
+* and the requested SROM API is executed. The operation status is returned to the
+* driver context and a release interrupt is triggered.
+*
+* Writing to flash can take up to 20 milliseconds. During this time,
+* the device should not be reset (including XRES pin, software reset, and
+* watchdog) or unexpected changes may be made to portions of the flash.
+* Also, the low-voltage detect circuits should be configured to generate an
+* interrupt instead of a reset.
+*
+* A Read while Write violation occurs when a flash Read operation is initiated
+* in the same or neighboring (neighboring restriction is applicable just for the
+* CY8C6xx6, CY8C6xx7 devices) flash sector where the flash Write, Erase, or
+* Program operation is working. This violation may cause a HardFault exception.
+* To avoid the Read while Write violation, the user must carefully split the
+* Read and Write operation on flash sectors which are not neighboring,
+* considering both cores in the multi-processor device. If the flash is divided
+* into four equal sectors, you may edit the linker script to place the code
+* into neighboring sectors. For example, use sectors number 0 and 1 for code
+* and sectors 2 and 3 for data storage.
+*
+* \section group_flash_configuration Configuration Considerations
+*
+* \subsection group_flash_config_intro Introduction:
+* The PSoC 6 MCU user-programmable Flash consists of:
+* - Four User Flash sectors (0 through 3) - 256KB each.
+* - EEPROM emulation sector - 32KB.
+*
+* Write operations are performed on a per-sector basis and may be done as
+* Blocking or Partially Blocking, defined as follows:
+*
+* \subsection group_flash_config_blocking Blocking:
+* In this case, the entire Flash block is not available for the duration of the
+* Write (&sim;16ms). Therefore, no Flash accesses (from any Bus Master) can
+* occur during that time. CPU execution can be performed from SRAM. All
+* pre-fetching must be disabled. Application code execution from Flash is
+* blocked for the Flash Write duration for both cores.
+*
+* \subsection group_flash_config_block_const Constraints for Blocking Flash operations:
+* -# During write to flash, the device should not be reset (including XRES pin,
+* software reset, and watchdog), or unexpected changes may be made to portions
+* of the flash.
+* -# The low-voltage detect circuits should be configured to generate an
+* interrupt instead of a reset.
+* -# Flash write operation is allowed only in one of the following CM4 states:
+* -# CM4 is Active and initialized:<br>
+* call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)".
+* <b>Note:</b> If desired user may put CM4 core in Deep Sleep any time
+* after calling Cy_SysEnableCM4().
+* -# CM4 is Off:<br>
+* call Cy_SysDisableCM4(). <b>Note:</b> In this state Debug mode is not
+* supported.
+* .
+* -# Flash write cannot be performed in ULP (core voltage 0.9V) mode.
+* -# Interrupts must be enabled on both active cores. Do not enter a critical
+* section during flash operation.
+* -# User must guarantee that system pipe interrupts (IPC interrupts 3 and 4)
+* have the highest priority, or at least that pipe interrupts are not
+* interrupted or in a pending state for more than 700 &micro;s.
+* -# User must guarantee that during flash write operation no flash read
+* operations are performed by bus masters other than CM0+ and CM4 (DMA and
+* Crypto).
+* -# If you do not use the default startup, perform the following steps
+* before any flash write/erase operations:
+* \snippet flash/snippet/main.c Flash Initialization
+*
+* \subsection group_flash_config_rww Partially Blocking:
+* This method has a much shorter time window during which Flash accesses are not
+* allowed. Application code execution from Flash is blocked for only a part of
+* Flash Write duration, for both cores. Blocking duration depends upon the API
+* sequence used.
+*
+* For API sequence Cy_Flash_StartEraseRow() + Cy_Flash_StartProgram() there are
+* four block-out regions during which the read is blocked using the software
+* driver (PDL). See <b>Figure 1</b>.
+*
+* <center>
+* <table class="doxtable">
+* <caption>Table 1 - Block-out periods</caption>
+* <tr>
+* <th>Block-out</th>
+* <th>Phase</th>
+* <th>Duration</th>
+* </tr>
+* <tr>
+* <td>A</td>
+* <td>The beginning of the Erase operation</td>
+* <td>2ms + 9500 SlowClk cycles</td>
+* </tr>
+* <tr>
+* <td>B</td>
+* <td>The end of the Erase operation</td>
+* <td>0.13ms + 1000 SlowClk cycles</td>
+* </tr>
+* <tr>
+* <td>C</td>
+* <td>The beginning of the Program operation</td>
+* <td>0.8ms + 6000 SlowClk cycles</td>
+* </tr>
+* <tr>
+* <td>D</td>
+* <td>The end of the Program operation</td>
+* <td>0.13ms + 1000 SlowClk cycles</td>
+* </tr>
+* </table>
+* </center>
+*
+* This allows both cores to execute an application for about 80% of Flash Write
+* operation - see <b>Figure 1</b>.
+* This capability is important for communication protocols that rely on fast
+* response.
+*
+* \image html flash-rww-diagram.png "Figure 1 - Blocking Intervals in Flash Write operation"
+*
+* For the Cy_Flash_StartWrite() function, the block-out period is different for
+* the two cores. The core that initiates Cy_Flash_StartWrite() is blocked for
+* two periods:
+* - From start of Erase operation (start of A on Figure 1) till the start of
+* Program operation (end of C on Figure 1).
+* - During D period on <b>Figure 1</b>.
+*
+* The core that performs read/execute is blocked identically to the previous
+* scenario - see <b>Figure 1</b>.
+*
+* This allows the core that initiates Cy_Flash_StartWrite() to execute an
+* application for about 20% of the Flash Write operation. The other core executes
+* the application for about 80% of the Flash Write operation.
+*
+* Some constraints must be planned for in the Partially Blocking mode which are
+* described in detail below.
+*
+* \subsection group_flash_config_rww_const Constraints for Partially Blocking Flash operations:
+* -# During write to flash, the device should not be reset (including XRES pin,
+* software reset, and watchdog) or unexpected changes may be made to portions
+* of the flash.
+* -# The low-voltage detect circuits should be configured to generate an
+* interrupt instead of a reset.
+* -# During write to flash, application code should not change the clock
+* settings. Use Cy_Flash_IsOperationComplete() to ensure flash write
+* operation is finished.
+* -# During write to flash, application code should not start the clock
+* measurements (should not call Cy_SysClk_StartClkMeasurementCounters()).
+* -# Flash write operation is allowed only in one of the following CM4 states:
+* -# CM4 is Active and initialized:<br>
+* call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)".
+* <b>Note:</b> If desired user may put CM4 core in Deep Sleep any time
+* after calling Cy_SysEnableCM4().
+* -# CM4 is Off:<br>
+* call Cy_SysDisableCM4(). <b>Note:</b> In this state Debug mode is not
+* supported.
+* .
+* -# Use the following rules for split by sectors. (In this context, read means
+* read of any bus master: CM0+, CM4, DMA, Crypto, etc.)
+* -# Do not write to and read/execute from the same flash sector at the same
+* time. This is true for all sectors.
+* -# Writing rules in User Flash:
+* -# Any bus master can read/execute from UFLASH S0 and/or S1, during
+* flash write to UFLASH S2 or S3.
+* -# Any bus master can read/execute from UFLASH S2 and/or S3, during
+* flash write to UFLASH S0 or S1.
+*
+* <b>Suggestion:</b> in case of bootloading, it is recommended to place
+* code for CM4 in either S0 or S1. CM0+ code resides in S0. Write data
+* to S2 and S3 sections.
+* .
+* -# Flash write cannot be performed in ULP mode (core voltage 0.9V).
+* -# Interrupts must be enabled on both active cores. Do not enter a critical
+* section during flash operation.
+* -# User must guarantee that system pipe interrupts (IPC interrupts 3 and 4)
+* have the highest priority, or at least that pipe interrupts are not
+* interrupted or in a pending state for more than 700 &micro;s.
+* -# User must guarantee that during flash write operation no flash read
+* operations are performed by bus masters other than CM0+ and CM4
+* (DMA and Crypto).
+* -# If you do not use the default startup, perform the following steps
+* before any flash write/erase operations:
+* \snippet flash/snippet/main.c Flash Initialization
+*
+* \subsection group_flash_config_emeeprom EEPROM section use:
+* If you plan to use "cy_em_eeprom" section for different purposes for both of
+* device cores or use <b>Em_EEPROM Middleware</b> together with flash driver
+* write operations you must modify the linker scripts.<br>
+* For more information, refer to the <b>Middleware/Cypress Em_EEPROM Middleware
+* Library</b> section of the PDL documentation.
+*
+* \section group_flash_more_information More Information
+*
+* See the technical reference manual (TRM) for more information about the Flash
+* architecture.
+*
+* \section group_flash_MISRA MISRA-C Compliance
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th style="width: 50%;">Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>Casting to different object pointer type.</td>
+* <td>The cast of the uint32_t pointer to pipe message structure pointer
+* is used to get transmitted data via the \ref group_ipc channel.
+* We cast only one pointer, so there is no way to avoid this cast.</td>
+* </tr>
+*
+* </table>
+*
+* \section group_flash_changelog Changelog
+*
+* <table class="doxtable">
+* <tr><th>Version</th><th style="width: 52%;">Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td rowspan="1">3.30.2</td>
+* <td>Updated documentation to limit devices with the neighboring restriction.</td>
+* <td>User experience enhancement.</td>
+* </tr>
+* <tr>
+* <td rowspan="1">3.30.1</td>
+* <td>Used the CY_RAMFUNC_BEGIN and CY_RAMFUNC_END macros that allocate the function in RAM instead of using the CY_SECTION(".cy_ramfunc") macros.</td>
+* <td>Removed the code duplication.</td>
+* </tr>
+* <tr>
+* <td rowspan="3">3.30</td>
+* <td>Moved ipcWaitMessageStc structure to the RAM section called ".cy_sharedmem".</td>
+* <td>Support Secure Boot devices.</td>
+* </tr>
+* <tr>
+* <td>Renamed Function Cy_Flash_StartErase() to Cy_Flash_StartEraseRow().</td>
+* <td>The driver improvements based on the usability feedback.</td>
+* </tr>
+* <tr>
+* <td>Added new API functions \ref Cy_Flash_EraseSector,
+* \ref Cy_Flash_StartEraseSector, \ref Cy_Flash_EraseSubsector,
+* \ref Cy_Flash_StartEraseSubsector </td>
+* <td>The driver improvements based on the usability feedback.</td>
+* </tr>
+* <tr>
+* <td rowspan="3">3.20</td>
+* <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Added new API function \ref Cy_Flash_InitExt</td>
+* <td>The driver improvements based on the usability feedback</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>3.11</td>
+* <td>Updated driver functionality to correctly use the SysClk measurement
+* counters while partially blocking flash operations</td>
+* <td>Added arbiter mechanism for correct usage of the SysClk measurement
+* counters</td>
+* </tr>
+* <tr>
+* <td>3.10</td>
+* <td>Updated Cy_Flash_SendCmd() code to support single core devices.</td>
+* <td>Support new devices</td>
+* </tr>
+* <tr>
+* <td>3.0</td>
+* <td>New function - Cy_Flash_ProgramRow();<br>
+* Updated Cy_Flash_RowChecksum(): changed input parameter to take the
+* <b>row address</b> (rowAddr) instead of the <b>row number</b>
+* (rowNum);<br>
+* Renamed macro for disabling RWW support in driver to
+* <b>CY_FLASH_RWW_DRV_SUPPORT_DISABLED</b>.<br>
+* Updated \ref group_flash_configuration documentation section with
+* flash usage constraints.</td>
+* <td>Improvements made based on usability feedback to use a common
+* interface</td>
+* </tr>
+* <tr>
+* <td rowspan="3">2.0</td>
+* <td>Added non-blocking erase function - Cy_Flash_StartErase().
+* Removed the clear cache function call.</td>
+* <td>The clear cache operation is removed from the blocking Write/Erase
+* function because in this case it is performed by the hardware.
+* Otherwise it is documented that it is the user's responsibility to
+* clear the cache after executing the non-blocking Write/Erase flash
+* operation.</td>
+* </tr>
+* <tr>
+* <td>Added new Cy_Flash_IsOperationComplete() function to check completeness.
+* Obsoleted Cy_Flash_IsWriteComplete(), Cy_Flash_IsProgramComplete(),
+* and Cy_Flash_IsEraseComplete() functions.<br>
+* Added Cy_Flash_GetExternalStatus() function to get unparsed status where
+* flash driver will be used in security applications with other modules
+* as SecureImage.<br>
+* Added Cy_Flash_Init() function to initialize all needed prerequisites
+* for Erase/Write operations.</td>
+* <td>Updated driver design to improve user experience.</td>
+* </tr>
+* <tr>
+* <td>Updated driver implementation to remove MISRA rules deviations.</td>
+* <td>Driver implementation quality improvement.</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_flash_macros Macros
+* \{
+* \defgroup group_flash_general_macros Flash general parameters
+* Provides general information about flash
+*
+* \defgroup group_flash_config_macros Flash configuration
+* Specifies the parameter values passed to SROM API
+* \}
+* \defgroup group_flash_functions Functions
+* \defgroup group_flash_enumerated_types Enumerated Types
+*/
+
+#include "cy_device.h"
+#include <cy_device_headers.h>
+
+#include "cy_syslib.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/***************************************
+* Macro definitions
+***************************************/
+/**
+* \addtogroup group_flash_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_FLASH_DRV_VERSION_MAJOR 3
+
+/** Driver minor version */
+#define CY_FLASH_DRV_VERSION_MINOR 30
+
+#define CY_FLASH_ID (CY_PDL_DRV_ID(0x14UL)) /**< FLASH PDL ID */
+
+#define CY_FLASH_ID_INFO (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_INFO ) /**< Return prefix for FLASH driver function status codes */
+#define CY_FLASH_ID_WARNING (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_WARNING) /**< Return prefix for FLASH driver function warning return values */
+#define CY_FLASH_ID_ERROR (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_ERROR) /**< Return prefix for FLASH driver function error return values */
+
+/** \} group_flash_macros */
+
+
+/**
+* \addtogroup group_flash_general_macros
+* \{
+*/
+
+/** Flash row size */
+#define CY_FLASH_SIZEOF_ROW (CPUSS_FLASHC_PA_SIZE * 4u)
+/** Long words flash row size */
+#define CY_FLASH_SIZEOF_ROW_LONG_UNITS (CY_FLASH_SIZEOF_ROW / sizeof(uint32_t))
+
+/** \} group_flash_general_macros */
+
+
+/**
+* \addtogroup group_flash_enumerated_types
+* \{
+*/
+
+/** This enum has the return values of the Flash driver */
+typedef enum cy_en_flashdrv_status
+{
+ CY_FLASH_DRV_SUCCESS = 0x00UL, /**< Success */
+ CY_FLASH_DRV_INV_PROT = ( CY_FLASH_ID_ERROR + 0x0UL), /**< Invalid device protection state */
+ CY_FLASH_DRV_INVALID_FM_PL = ( CY_FLASH_ID_ERROR + 0x1UL), /**< Invalid flash page latch address */
+ CY_FLASH_DRV_INVALID_FLASH_ADDR = ( CY_FLASH_ID_ERROR + 0x2UL), /**< Invalid flash address */
+ CY_FLASH_DRV_ROW_PROTECTED = ( CY_FLASH_ID_ERROR + 0x3UL), /**< Row is write protected */
+ CY_FLASH_DRV_IPC_BUSY = ( CY_FLASH_ID_ERROR + 0x5UL), /**< IPC structure is already locked by another process */
+ CY_FLASH_DRV_INVALID_INPUT_PARAMETERS = ( CY_FLASH_ID_ERROR + 0x6UL), /**< Input parameters passed to Flash API are not valid */
+ CY_FLASH_DRV_PL_ROW_COMP_FA = ( CY_FLASH_ID_ERROR + 0x22UL), /**< Comparison between Page Latches and FM row failed */
+ CY_FLASH_DRV_ERR_UNC = ( CY_FLASH_ID_ERROR + 0xFFUL), /**< Unknown error code. See \ref Cy_Flash_GetExternalStatus() */
+ CY_FLASH_DRV_PROGRESS_NO_ERROR = ( CY_FLASH_ID_INFO + 0x0UL), /**< Command in progress; no error */
+ CY_FLASH_DRV_OPERATION_STARTED = ( CY_FLASH_ID_INFO + 0x1UL), /**< Flash operation is successfully initiated */
+ CY_FLASH_DRV_OPCODE_BUSY = ( CY_FLASH_ID_INFO + 0x2UL) /**< Flash is under operation */
+} cy_en_flashdrv_status_t;
+
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ /** Flash notification configuration structure */
+ typedef struct
+ {
+ uint8_t clientID; /**< Client ID */
+ uint8_t pktType; /**< Message Type */
+ uint16_t intrRelMask; /**< Mask */
+ } cy_stc_flash_notify_t;
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+
+/** \} group_flash_enumerated_types */
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_flash_functions
+* \{
+*/
+void Cy_Flash_Init(void);
+cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr);
+cy_en_flashdrv_status_t Cy_Flash_StartEraseRow(uint32_t rowAddr);
+cy_en_flashdrv_status_t Cy_Flash_EraseSector(uint32_t sectorAddr);
+cy_en_flashdrv_status_t Cy_Flash_StartEraseSector(uint32_t sectorAddr);
+cy_en_flashdrv_status_t Cy_Flash_EraseSubsector(uint32_t subSectorAddr);
+cy_en_flashdrv_status_t Cy_Flash_StartEraseSubsector(uint32_t subSectorAddr);
+cy_en_flashdrv_status_t Cy_Flash_ProgramRow(uint32_t rowAddr, const uint32_t* data);
+cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data);
+cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data);
+cy_en_flashdrv_status_t Cy_Flash_StartProgram(uint32_t rowAddr, const uint32_t* data);
+cy_en_flashdrv_status_t Cy_Flash_IsOperationComplete(void);
+cy_en_flashdrv_status_t Cy_Flash_RowChecksum(uint32_t rowAddr, uint32_t* checksumPtr);
+cy_en_flashdrv_status_t Cy_Flash_CalculateHash(const uint32_t* data, uint32_t numberOfBytes, uint32_t* hashPtr);
+uint32_t Cy_Flash_GetExternalStatus(void);
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ void Cy_Flash_InitExt(cy_stc_flash_notify_t *ipcWaitMessageAddr);
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+
+/** \} group_flash_functions */
+
+/** \cond INTERNAL */
+#if (CY_CPU_CORTEX_M4)
+void Cy_Flash_ResumeIrqHandler(void);
+#endif
+
+/*******************************************************************************
+Backward compatibility macro. The following code is DEPRECATED and must
+not be used in new projects
+*******************************************************************************/
+#define Cy_Flash_IsWriteComplete(...) Cy_Flash_IsOperationComplete()
+#define Cy_Flash_IsProgramComplete(...) Cy_Flash_IsOperationComplete()
+#define Cy_Flash_IsEraseComplete(...) Cy_Flash_IsOperationComplete()
+#define CY_FLASH_NUMBER_ROWS (CY_FLASH_SIZE / CY_FLASH_SIZEOF_ROW)
+#define Cy_Flash_StartErase Cy_Flash_StartEraseRow
+
+/** \endcond */
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* #if !defined(CY_FLASH_H) */
+
+/** \} group_flash */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_gpio.h b/platform/ext/target/psoc64/Native_Driver/include/cy_gpio.h
new file mode 100644
index 0000000000..c74bdc9102
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_gpio.h
@@ -0,0 +1,1973 @@
+/***************************************************************************//**
+* \file cy_gpio.h
+* \version 1.20
+*
+* Provides an API declaration of the GPIO driver
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_gpio
+* \{
+* The GPIO driver provides an API to configure and access device Input/Output pins.
+*
+* The functions and other declarations used in this driver are in cy_gpio.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions
+* and declarations in the PDL.
+*
+* IO pins include all general purpose types such as GPIO, SIO, HSIO, AUXIO, and
+* their variants.
+*
+* Initialization can be performed either at the port level or by configuring the
+* individual pins. For efficient use of code space, port
+* configuration should be used in the field. Refer to the product device header files
+* for the list of supported ports and pins.
+*
+* - Single pin configuration is performed by using \ref Cy_GPIO_Pin_FastInit
+* (provide specific values) or \ref Cy_GPIO_Pin_Init (provide a filled
+* cy_stc_gpio_pin_config_t structure).
+* - An entire port can be configured using \ref Cy_GPIO_Port_Init. Provide a filled
+* cy_stc_gpio_prt_config_t structure. The values in the structure are
+* bitfields representing the desired value for each pin in the port.
+* - Pin configuration and management is based on the port address and pin number.
+* \ref Cy_GPIO_PortToAddr function can optionally be used to calculate the port
+* address from the port number at run-time.
+*
+* Once the pin/port initialization is complete, each pin can be accessed by
+* specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API
+* functions.
+*
+* \section group_gpio_configuration Configuration Considerations
+*
+* 1. Pin multiplexing is controlled through the High-Speed IO Matrix (HSIOM) selection.
+* This allows the pin to connect to signal sources/sinks throughout the device,
+* as defined by the pin HSIOM selection options (en_hsiom_sel_t).
+* 2. All pins are initialized to High-Z drive mode with HSIOM connected to CPU (SW
+* control digital pin only) at Power-On-Reset(POR).
+* 3. Some API functions perform read-modify-write operations on shared port
+* registers. These functions are not thread safe and care must be taken when
+* called by the application.
+* 4. Digital input buffer provides a high-impedance buffer for the external
+* digital input. The input buffer is connected to the HSIOM for routing to
+* the CPU port registers and selected peripheral. Enabling the input
+* buffer provides possibility to read the pin state via the CPU.
+* If pin is connected to an analog signal, the input buffer should be
+* disabled to avoid crowbar currents. For more information refer to device
+* TRM and the device datasheet.
+*
+* Multiple pins on a port can be updated using direct port register writes with an
+* appropriate port mask. An example is shown below, highlighting the different ways of
+* configuring Port 1 pins using:
+*
+* - Port output data register
+* - Port output data set register
+* - Port output data clear register
+*
+* \snippet gpio/snippet/main.c Cy_GPIO_Snippet
+*
+* \section group_gpio_more_information More Information
+*
+* Refer to the technical reference manual (TRM) and the device datasheet.
+*
+* \section group_gpio_MISRA MISRA-C Compliance
+* The GPIO driver has the following specific deviations:
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to object type and
+* a different pointer to object type.</td>
+* <td> This code is safe because the elements of both GPIO_PRT_V1_Type and GPIO_PRT_V2_Type
+* types have identical alignment.</td>
+* </tr>
+* <tr>
+* <td>16.7</td>
+* <td>A</td>
+* <td>A pointer parameter in a function prototype should be declared as pointer
+* to const if the pointer is not used to modify the addressed object.</td>
+* <td>The objects pointed to by the base addresses of the GPIO port are not always modified.
+* While a const qualifier can be used in select scenarios, it brings little benefit
+* in adding this to the affected functions. </td>
+* </tr>
+* </table>
+*
+* \section group_gpio_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td rowspan="3">1.20</td>
+* <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Added the functions for configuring the AMux bus splitter switch cells:
+* - \ref Cy_GPIO_SetAmuxSplit
+* - \ref Cy_GPIO_GetAmuxSplit
+* </td>
+* <td>Added a new functionality related to AMux bus.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Updated description for the functions: \ref Cy_GPIO_GetInterruptStatus,
+* \ref Cy_GPIO_GetInterruptMask, \ref Cy_GPIO_GetInterruptStatusMasked.
+*
+* Minor documentation edits.
+* </td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.10</td>
+* <td>Added input parameter validation to the API functions</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_gpio_macros Macros
+* \defgroup group_gpio_functions Functions
+* \{
+* \defgroup group_gpio_functions_init Initialization Functions
+* \defgroup group_gpio_functions_gpio GPIO Functions
+* \defgroup group_gpio_functions_sio SIO Functions
+* \defgroup group_gpio_functions_interrupt Port Interrupt Functions
+* \}
+* \defgroup group_gpio_data_structures Data Structures
+* \defgroup group_gpio_enums Enumerated Types
+*/
+
+#if !defined(CY_GPIO_H)
+#define CY_GPIO_H
+
+#include <stddef.h>
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/** \addtogroup group_gpio_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_GPIO_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_GPIO_DRV_VERSION_MINOR 20
+
+/** GPIO driver ID */
+#define CY_GPIO_ID CY_PDL_DRV_ID(0x16U)
+
+/** \} group_gpio_macros */
+
+
+/***************************************
+* Enumerations
+***************************************/
+/**
+* \addtogroup group_gpio_enums
+* \{
+*/
+
+/** GPIO Driver error codes */
+typedef enum
+{
+ CY_GPIO_SUCCESS = 0x00U, /**< Returned successful */
+ CY_GPIO_BAD_PARAM = CY_GPIO_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< Bad parameter was passed */
+} cy_en_gpio_status_t;
+
+/** AMux switch open/close config */
+typedef enum
+{
+ CY_GPIO_AMUX_OPENALL, /**< Open ground switch. Open right switch. Open left switch */
+ CY_GPIO_AMUX_L, /**< Open ground switch. Open right switch. Close left switch */
+ CY_GPIO_AMUX_R, /**< Open ground switch. Close right switch. Open left switch */
+ CY_GPIO_AMUX_LR, /**< Open ground switch. Close right switch. Close left switch */
+ CY_GPIO_AMUX_G, /**< Close ground switch. Open right switch. Open left switch */
+ CY_GPIO_AMUX_GL, /**< Close ground switch. Open right switch. Close left switch */
+ CY_GPIO_AMUX_GR, /**< Close ground switch. Close right switch. Open left switch */
+ CY_GPIO_AMUX_GLR, /**< Close ground switch. Close right switch. Close left switch */
+}cy_en_gpio_amuxconnect_t;
+
+/**
+* AMux Bus selection
+*/
+typedef enum
+{
+ CY_GPIO_AMUXBUSA, /**< AMuxBus A */
+ CY_GPIO_AMUXBUSB /**< AMuxBus B */
+}cy_en_gpio_amuxselect_t;
+
+/** \} group_gpio_enums */
+
+
+/***************************************
+* Configuration Structures
+***************************************/
+
+/**
+* \addtogroup group_gpio_data_structures
+* \{
+*/
+
+/** This structure is used to initialize a port of GPIO pins */
+typedef struct
+{
+ uint32_t out; /**< Initial output data for the IO pins in the port */
+ uint32_t intrMask; /**< Interrupt enable mask for the port interrupt */
+ uint32_t intrCfg; /**< Port pin interrupt edge detection configuration */
+ uint32_t cfg; /**< Port pin drive modes and input buffer enable configuration */
+ uint32_t cfgIn; /**< Port pin input buffer configuration */
+ uint32_t cfgOut; /**< Port pin output buffer configuration */
+ uint32_t cfgSIO; /**< Port SIO pins configuration */
+ uint32_t sel0Active; /**< HSIOM selection for port pins 0,1,2,3 */
+ uint32_t sel1Active; /**< HSIOM selection for port pins 4,5,6,7 */
+} cy_stc_gpio_prt_config_t;
+
+/** This structure is used to initialize a single GPIO pin */
+typedef struct
+{
+ uint32_t outVal; /**< Pin output state */
+ uint32_t driveMode; /**< Drive mode */
+ en_hsiom_sel_t hsiom; /**< HSIOM selection */
+ uint32_t intEdge; /**< Interrupt Edge type */
+ uint32_t intMask; /**< Interrupt enable mask */
+ uint32_t vtrip; /**< Input buffer voltage trip type */
+ uint32_t slewRate; /**< Output buffer slew rate */
+ uint32_t driveSel; /**< Drive strength */
+ uint32_t vregEn; /**< SIO pair output buffer mode */
+ uint32_t ibufMode; /**< SIO pair input buffer mode */
+ uint32_t vtripSel; /**< SIO pair input buffer trip point */
+ uint32_t vrefSel; /**< SIO pair reference voltage for input buffer trip point */
+ uint32_t vohSel; /**< SIO pair regulated voltage output level */
+} cy_stc_gpio_pin_config_t;
+
+/** \} group_gpio_data_structures */
+
+/***************************************
+* Constants
+***************************************/
+
+/** \cond INTERNAL */
+
+/* General Constants */
+#define CY_GPIO_PRT_HALF (4UL) /**< Half-way point of a GPIO port */
+#define CY_GPIO_PRT_DEINIT (0UL) /**< De-init value for port registers */
+
+/* GPIO Masks */
+#define CY_GPIO_HSIOM_MASK (0x1FUL) /**< HSIOM selection mask */
+#define CY_GPIO_OUT_MASK (0x01UL) /**< Single pin mask for OUT register */
+#define CY_GPIO_IN_MASK (0x01UL) /**< Single pin mask for IN register */
+#define CY_GPIO_CFG_DM_MASK (0x0FUL) /**< Single pin mask for drive mode in CFG register */
+#define CY_GPIO_CFG_IN_VTRIP_SEL_MASK (0x01UL) /**< Single pin mask for VTRIP selection in CFG IN register */
+#define CY_GPIO_CFG_OUT_SLOW_MASK (0x01UL) /**< Single pin mask for slew rate in CFG OUT register */
+#define CY_GPIO_CFG_OUT_DRIVE_SEL_MASK (0x03UL) /**< Single pin mask for drive strength in CFG OUT register */
+#define CY_GPIO_INTR_STATUS_MASK (0x01UL) /**< Single pin mask for interrupt status in INTR register */
+#define CY_GPIO_INTR_EN_MASK (0x01UL) /**< Single pin mask for interrupt status in INTR register */
+#define CY_GPIO_INTR_MASKED_MASK (0x01UL) /**< Single pin mask for masked interrupt status in INTR_MASKED register */
+#define CY_GPIO_INTR_SET_MASK (0x01UL) /**< Single pin mask for setting the interrupt in INTR_MASK register */
+#define CY_GPIO_INTR_EDGE_MASK (0x03UL) /**< Single pin mask for interrupt edge type in INTR_EDGE register */
+#define CY_GPIO_INTR_FLT_EDGE_MASK (0x07UL) /**< Single pin mask for setting filtered interrupt */
+
+/* SIO Masks */
+#define CY_GPIO_VREG_EN_MASK (0x01UL) /**< Single SIO pin mask for voltage regulation enable */
+#define CY_GPIO_IBUF_MASK (0x01UL) /**< Single SIO pin mask for input buffer */
+#define CY_GPIO_IBUF_SHIFT (0x01UL) /**< Single SIO pin shift for input buffer */
+#define CY_GPIO_VTRIP_SEL_MASK (0x01UL) /**< Single SIO pin mask for the input buffer trip point */
+#define CY_GPIO_VTRIP_SEL_SHIFT (0x02UL) /**< Single SIO pin shift for the input buffer trip point */
+#define CY_GPIO_VREF_SEL_MASK (0x03UL) /**< Single SIO pin mask for voltage reference */
+#define CY_GPIO_VREF_SEL_SHIFT (0x03UL) /**< Single SIO pin shift for voltage reference */
+#define CY_GPIO_VOH_SEL_MASK (0x07UL) /**< Single SIO pin mask for VOH */
+#define CY_GPIO_VOH_SEL_SHIFT (0x05UL) /**< Single SIO pin shift for VOH */
+
+/* Special mask for SIO pin pair setting */
+#define CY_GPIO_SIO_ODD_PIN_MASK (0x00FEUL) /**< SIO pin pair selection mask */
+#define CY_GPIO_SIO_PIN_MASK (0x00FFUL) /**< SIO pin pair mask */
+
+/* Offsets */
+#define CY_GPIO_HSIOM_OFFSET (3UL) /**< Offset for HSIOM */
+#define CY_GPIO_DRIVE_MODE_OFFSET (2UL) /**< Offset for Drive mode */
+#define CY_GPIO_INBUF_OFFSET (3UL) /**< Offset for input buffer */
+#define CY_GPIO_CFG_OUT_DRIVE_OFFSET (16UL) /**< Offset for drive strength */
+#define CY_GPIO_INTR_CFG_OFFSET (1UL) /**< Offset for interrupt config */
+#define CY_GPIO_INTR_FILT_OFFSET (18UL) /**< Offset for filtered interrupt config */
+#define CY_GPIO_CFG_SIO_OFFSET (2UL) /**< Offset for SIO config */
+
+/* Parameter validation constants */
+#define CY_GPIO_PINS_MAX (8UL) /**< Number of pins in the port */
+#define CY_GPIO_PRT_PINS_MASK (0x0000000FFUL)
+#define CY_GPIO_PRT_INTR_CFG_EDGE_SEL_MASK (GPIO_PRT_INTR_CFG_EDGE0_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE1_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE2_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE3_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk)
+#define CY_GPIO_PRT_INTR_CFG_RANGE_MASK (CY_GPIO_PRT_INTR_CFG_EDGE_SEL_MASK | \
+ GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_FLT_SEL_Msk)
+#define CY_GPIO_PRT_INT_MASK_MASK (0x0000001FFUL)
+#define CY_GPIO_PRT_SEL_ACTIVE_MASK (0x1FFFFFFFUL)
+
+#define GPIO_MAX_SPLIT_CELL_SEGMENTS (9U)
+
+/* Parameter validation macros */
+#define CY_GPIO_IS_PIN_VALID(pinNum) (CY_GPIO_PINS_MAX > (pinNum))
+#define CY_GPIO_IS_FILTER_PIN_VALID(pinNum) (CY_GPIO_PINS_MAX >= (pinNum))
+#define CY_GPIO_IS_VALUE_VALID(outVal) (1UL >= (outVal))
+#define CY_GPIO_IS_DM_VALID(driveMode) (0U == ((driveMode) & (uint32_t)~CY_GPIO_CFG_DM_MASK))
+
+#define CY_GPIO_IS_HSIOM_VALID(hsiom) (0U == ((hsiom) & (uint32_t)~CY_GPIO_HSIOM_MASK))
+
+#define CY_GPIO_IS_INT_EDGE_VALID(intEdge) ((CY_GPIO_INTR_DISABLE == (intEdge)) || \
+ (CY_GPIO_INTR_RISING == (intEdge)) || \
+ (CY_GPIO_INTR_FALLING == (intEdge)) || \
+ (CY_GPIO_INTR_BOTH == (intEdge)))
+
+#define CY_GPIO_IS_DRIVE_SEL_VALID(driveSel) ((CY_GPIO_DRIVE_FULL == (driveSel)) || \
+ (CY_GPIO_DRIVE_1_2 == (driveSel)) || \
+ (CY_GPIO_DRIVE_1_4 == (driveSel)) || \
+ (CY_GPIO_DRIVE_1_8 == (driveSel)))
+
+#define CY_GPIO_IS_VREF_SEL_VALID(vrefSel) ((CY_SIO_VREF_PINREF == (vrefSel)) || \
+ (CY_SIO_VREF_1_2V == (vrefSel)) || \
+ (CY_SIO_VREF_AMUX_A == (vrefSel)) || \
+ (CY_SIO_VREF_AMUX_B == (vrefSel)))
+
+#define CY_GPIO_IS_VOH_SEL_VALID(vrefSel) ((CY_SIO_VOH_1_00 == (vrefSel)) || \
+ (CY_SIO_VOH_1_25 == (vrefSel)) || \
+ (CY_SIO_VOH_1_49 == (vrefSel)) || \
+ (CY_SIO_VOH_1_67 == (vrefSel)) || \
+ (CY_SIO_VOH_2_08 == (vrefSel)) || \
+ (CY_SIO_VOH_2_50 == (vrefSel)) || \
+ (CY_SIO_VOH_2_78 == (vrefSel)) || \
+ (CY_SIO_VOH_4_16 == (vrefSel)))
+
+#define CY_GPIO_IS_PIN_BIT_VALID(pinBit) (0U == ((pinBit) & (uint32_t)~CY_GPIO_PRT_PINS_MASK))
+#define CY_GPIO_IS_INTR_CFG_VALID(intrCfg) (0U == ((intrCfg) & (uint32_t)~CY_GPIO_PRT_INTR_CFG_RANGE_MASK))
+#define CY_GPIO_IS_INTR_MASK_VALID(intrMask) (0U == ((intrMask) & (uint32_t)~CY_GPIO_PRT_INT_MASK_MASK))
+#define CY_GPIO_IS_SEL_ACT_VALID(selActive) (0U == ((selActive) & (uint32_t)~CY_GPIO_PRT_SEL_ACTIVE_MASK))
+
+#define CY_GPIO_IS_AMUX_SPLIT_VALID(switchCtrl) (((uint32_t) (switchCtrl)) < GPIO_MAX_SPLIT_CELL_SEGMENTS)
+
+#define CY_GPIO_IS_AMUX_CONNECT_VALID(amuxConnect) ((CY_GPIO_AMUX_OPENALL == (amuxConnect)) || \
+ (CY_GPIO_AMUX_L == (amuxConnect)) || \
+ (CY_GPIO_AMUX_R == (amuxConnect)) || \
+ (CY_GPIO_AMUX_LR == (amuxConnect)) || \
+ (CY_GPIO_AMUX_G == (amuxConnect)) || \
+ (CY_GPIO_AMUX_GL == (amuxConnect)) || \
+ (CY_GPIO_AMUX_GR == (amuxConnect)) || \
+ (CY_GPIO_AMUX_GLR == (amuxConnect)))
+
+#define CY_GPIO_IS_AMUX_SELECT_VALID(amuxBus) ((CY_GPIO_AMUXBUSA == (amuxBus)) || \
+ (CY_GPIO_AMUXBUSB == (amuxBus)))
+/** \endcond */
+
+
+/***************************************
+* Function Constants
+***************************************/
+
+/**
+* \addtogroup group_gpio_macros
+* \{
+*/
+
+/**
+* \defgroup group_gpio_driveModes Pin drive mode
+* \{
+* Constants to be used for setting the drive mode of the pin.
+*/
+#define CY_GPIO_DM_ANALOG (0x00UL) /**< Analog High-Z. Input buffer off */
+#define CY_GPIO_DM_PULLUP_IN_OFF (0x02UL) /**< Resistive Pull-Up. Input buffer off */
+#define CY_GPIO_DM_PULLDOWN_IN_OFF (0x03UL) /**< Resistive Pull-Down. Input buffer off */
+#define CY_GPIO_DM_OD_DRIVESLOW_IN_OFF (0x04UL) /**< Open Drain, Drives Low. Input buffer off */
+#define CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF (0x05UL) /**< Open Drain, Drives High. Input buffer off */
+#define CY_GPIO_DM_STRONG_IN_OFF (0x06UL) /**< Strong Drive. Input buffer off */
+#define CY_GPIO_DM_PULLUP_DOWN_IN_OFF (0x07UL) /**< Resistive Pull-Up/Down. Input buffer off */
+#define CY_GPIO_DM_HIGHZ (0x08UL) /**< Digital High-Z. Input buffer on */
+#define CY_GPIO_DM_PULLUP (0x0AUL) /**< Resistive Pull-Up. Input buffer on */
+#define CY_GPIO_DM_PULLDOWN (0x0BUL) /**< Resistive Pull-Down. Input buffer on */
+#define CY_GPIO_DM_OD_DRIVESLOW (0x0CUL) /**< Open Drain, Drives Low. Input buffer on */
+#define CY_GPIO_DM_OD_DRIVESHIGH (0x0DUL) /**< Open Drain, Drives High. Input buffer on */
+#define CY_GPIO_DM_STRONG (0x0EUL) /**< Strong Drive. Input buffer on */
+#define CY_GPIO_DM_PULLUP_DOWN (0x0FUL) /**< Resistive Pull-Up/Down. Input buffer on */
+/** \} */
+
+/**
+* \defgroup group_gpio_vtrip Voltage trip mode
+* \{
+* Constants to be used for setting the voltage trip type on the pin.
+*/
+#define CY_GPIO_VTRIP_CMOS (0x00UL) /**< Input buffer compatible with CMOS and I2C interfaces */
+#define CY_GPIO_VTRIP_TTL (0x01UL) /**< Input buffer compatible with TTL and MediaLB interfaces */
+/** \} */
+
+/**
+* \defgroup group_gpio_slewRate Slew Rate Mode
+* \{
+* Constants to be used for setting the slew rate of the pin.
+*/
+#define CY_GPIO_SLEW_FAST (0x00UL) /**< Fast slew rate */
+#define CY_GPIO_SLEW_SLOW (0x01UL) /**< Slow slew rate */
+/** \} */
+
+/**
+* \defgroup group_gpio_driveStrength Pin drive strength
+* \{
+* Constants to be used for setting the drive strength of the pin.
+*/
+#define CY_GPIO_DRIVE_FULL (0x00UL) /**< Full drive strength: Max drive current */
+#define CY_GPIO_DRIVE_1_2 (0x01UL) /**< 1/2 drive strength: 1/2 drive current */
+#define CY_GPIO_DRIVE_1_4 (0x02UL) /**< 1/4 drive strength: 1/4 drive current */
+#define CY_GPIO_DRIVE_1_8 (0x03UL) /**< 1/8 drive strength: 1/8 drive current */
+/** \} */
+
+/**
+* \defgroup group_gpio_interruptTrigger Interrupt trigger type
+* \{
+* Constants to be used for setting the interrupt trigger type on the pin.
+*/
+#define CY_GPIO_INTR_DISABLE (0x00UL) /**< Disable the pin interrupt generation */
+#define CY_GPIO_INTR_RISING (0x01UL) /**< Rising-Edge interrupt */
+#define CY_GPIO_INTR_FALLING (0x02UL) /**< Falling-Edge interrupt */
+#define CY_GPIO_INTR_BOTH (0x03UL) /**< Both-Edge interrupt */
+/** \} */
+
+/**
+* \defgroup group_gpio_sioVreg SIO output buffer mode
+* \{
+* Constants to be used for setting the SIO output buffer mode on the pin.
+*/
+#define CY_SIO_VREG_UNREGULATED (0x00UL) /**< Unregulated output buffer */
+#define CY_SIO_VREG_REGULATED (0x01UL) /**< Regulated output buffer */
+/** \} */
+
+/**
+* \defgroup group_gpio_sioIbuf SIO input buffer mode
+* \{
+* Constants to be used for setting the SIO input buffer mode on the pin.
+*/
+#define CY_SIO_IBUF_SINGLEENDED (0x00UL) /**< Single ended input buffer */
+#define CY_SIO_IBUF_DIFFERENTIAL (0x01UL) /**< Differential input buffer */
+/** \} */
+
+/**
+* \defgroup group_gpio_sioVtrip SIO input buffer trip-point
+* \{
+* Constants to be used for setting the SIO input buffer trip-point of the pin.
+*/
+#define CY_SIO_VTRIP_CMOS (0x00UL) /**< CMOS input buffer (single-ended) */
+#define CY_SIO_VTRIP_TTL (0x01UL) /**< TTL input buffer (single-ended) */
+#define CY_SIO_VTRIP_0_5VDDIO_0_5VOH (0x00UL) /**< 0.5xVddio or 0.5xVoh (differential) */
+#define CY_SIO_VTRIP_0_4VDDIO_1_0VREF (0x01UL) /**< 0.4xVddio or 0.4xVoh (differential) */
+/** \} */
+
+/**
+* \defgroup group_gpio_sioVref SIO reference voltage for input buffer trip-point
+* \{
+* Constants to be used for setting the reference voltage of SIO input buffer trip-point.
+*/
+#define CY_SIO_VREF_PINREF (0x00UL) /**< Vref from analog pin */
+#define CY_SIO_VREF_1_2V (0x01UL) /**< Vref from internal 1.2V reference */
+#define CY_SIO_VREF_AMUX_A (0x02UL) /**< Vref from AMUXBUS_A */
+#define CY_SIO_VREF_AMUX_B (0x03UL) /**< Vref from AMUXBUS_B */
+/** \} */
+
+/**
+* \defgroup group_gpio_sioVoh Regulated output voltage level (Voh) and input buffer trip-point of an SIO pair
+* \{
+* Constants to be used for setting the Voh and input buffer trip-point of an SIO pair
+*/
+#define CY_SIO_VOH_1_00 (0x00UL) /**< Voh = 1 x Reference */
+#define CY_SIO_VOH_1_25 (0x01UL) /**< Voh = 1.25 x Reference */
+#define CY_SIO_VOH_1_49 (0x02UL) /**< Voh = 1.49 x Reference */
+#define CY_SIO_VOH_1_67 (0x03UL) /**< Voh = 1.67 x Reference */
+#define CY_SIO_VOH_2_08 (0x04UL) /**< Voh = 2.08 x Reference */
+#define CY_SIO_VOH_2_50 (0x05UL) /**< Voh = 2.50 x Reference */
+#define CY_SIO_VOH_2_78 (0x06UL) /**< Voh = 2.78 x Reference */
+#define CY_SIO_VOH_4_16 (0x07UL) /**< Voh = 4.16 x Reference */
+/** \} */
+
+/** \} group_gpio_macros */
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_gpio_functions
+* \{
+*/
+
+/**
+* \addtogroup group_gpio_functions_init
+* \{
+*/
+
+cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type* base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config);
+cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config);
+void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode, uint32_t outVal, en_hsiom_sel_t hsiom);
+void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base);
+__STATIC_INLINE void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value);
+__STATIC_INLINE en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum);
+
+/** \} group_gpio_functions_init */
+
+/**
+* \addtogroup group_gpio_functions_gpio
+* \{
+*/
+
+void Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_t amuxConnect, cy_en_gpio_amuxselect_t amuxBus);
+cy_en_gpio_amuxconnect_t Cy_GPIO_GetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxselect_t amuxBus);
+
+__STATIC_INLINE uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum);
+
+/** \} group_gpio_functions_gpio */
+
+/**
+* \addtogroup group_gpio_functions_sio
+* \{
+*/
+
+__STATIC_INLINE void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum);
+
+/** \} group_gpio_functions_sio */
+
+/**
+* \addtogroup group_gpio_functions_interrupt
+* \{
+*/
+
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base);
+
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void);
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void);
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void);
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void);
+
+/** \} group_gpio_functions_interrupt */
+
+
+/**
+* \addtogroup group_gpio_functions_init
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetHSIOM
+****************************************************************************//**
+*
+* Configures the HSIOM connection to the pin.
+*
+* Connects the specified High-Speed Input Output Multiplexer (HSIOM) selection
+* to the pin.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* HSIOM input selection
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetHSIOM
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value)
+{
+ uint32_t portNum;
+ uint32_t tempReg;
+ HSIOM_PRT_V1_Type* portAddrHSIOM;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(value));
+
+ portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
+ portAddrHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
+
+ if(pinNum < CY_GPIO_PRT_HALF)
+ {
+ tempReg = HSIOM_PRT_PORT_SEL0(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
+ HSIOM_PRT_PORT_SEL0(portAddrHSIOM) = tempReg | ((value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET));
+ }
+ else
+ {
+ pinNum -= CY_GPIO_PRT_HALF;
+ tempReg = HSIOM_PRT_PORT_SEL1(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
+ HSIOM_PRT_PORT_SEL1(portAddrHSIOM) = tempReg | ((value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET));
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetHSIOM
+****************************************************************************//**
+*
+* Returns the current HSIOM multiplexer connection to the pin.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* HSIOM input selection
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetHSIOM
+*
+*******************************************************************************/
+__STATIC_INLINE en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ uint32_t returnValue;
+ uint32_t portNum;
+ HSIOM_PRT_V1_Type* portAddrHSIOM;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
+ portAddrHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
+
+ if(pinNum < CY_GPIO_PRT_HALF)
+ {
+ returnValue = (HSIOM_PRT_PORT_SEL0(portAddrHSIOM) >> (pinNum << CY_GPIO_HSIOM_OFFSET)) & CY_GPIO_HSIOM_MASK;
+ }
+ else
+ {
+ pinNum -= CY_GPIO_PRT_HALF;
+ returnValue = (HSIOM_PRT_PORT_SEL1(portAddrHSIOM) >> (pinNum << CY_GPIO_HSIOM_OFFSET)) & CY_GPIO_HSIOM_MASK;
+ }
+
+ return (en_hsiom_sel_t)returnValue;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_PortToAddr
+****************************************************************************//**
+*
+* Retrieves the port address based on the given port number.
+*
+* This is a helper function to calculate the port base address when given a port
+* number. It is to be used when pin access needs to be calculated at runtime.
+*
+* \param portNum
+* Port number
+*
+* \return
+* Base address of the port register structure
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_PortToAddr
+*
+*******************************************************************************/
+__STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum)
+{
+ GPIO_PRT_Type* portBase;
+
+ if(portNum < (uint32_t)IOSS_GPIO_GPIO_PORT_NR)
+ {
+ portBase = (GPIO_PRT_Type *)(CY_GPIO_BASE + (GPIO_PRT_SECTION_SIZE * portNum));
+ }
+ else
+ {
+ /* Error: Return default base address */
+ portBase = (GPIO_PRT_Type *)(CY_GPIO_BASE);
+ }
+
+ return (portBase);
+}
+
+/** \} group_gpio_functions_init */
+
+/**
+* \addtogroup group_gpio_functions_gpio
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Read
+****************************************************************************//**
+*
+* Reads the current logic level on the input buffer of the pin.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \return
+* Logic level present on the pin
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_Read
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_IN(base) >> (pinNum)) & CY_GPIO_IN_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Write
+****************************************************************************//**
+*
+* Write a logic 0 or logic 1 state to the output driver.
+*
+* This function should be used only for software driven pins. It does not have
+* any effect on peripheral driven pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* Logic level to drive out on the pin
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_Write
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ /* Thread-safe: Directly access the pin registers instead of base->OUT */
+ if(0UL == value)
+ {
+ GPIO_PRT_OUT_CLR(base) = CY_GPIO_OUT_MASK << pinNum;
+ }
+ else
+ {
+ GPIO_PRT_OUT_SET(base) = CY_GPIO_OUT_MASK << pinNum;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_ReadOut
+****************************************************************************//**
+*
+* Reads the current logic level on the pin output driver.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* Logic level on the pin output driver
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_ReadOut
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_OUT(base) >> pinNum) & CY_GPIO_OUT_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Set
+****************************************************************************//**
+*
+* Set a pin output to logic state high.
+*
+* This function should be used only for software driven pins. It does not have
+* any effect on peripheral driven pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_Set
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ GPIO_PRT_OUT_SET(base) = CY_GPIO_OUT_MASK << pinNum;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Clr
+****************************************************************************//**
+*
+* Set a pin output to logic state Low.
+*
+* This function should be used only for software driven pins. It does not have
+* any effect on peripheral driven pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_Clr
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ GPIO_PRT_OUT_CLR(base) = CY_GPIO_OUT_MASK << pinNum;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Inv
+****************************************************************************//**
+*
+* Set a pin output logic state to the inverse of the current output
+* logic state.
+*
+* This function should be used only for software driven pins. It does not have
+* any effect on peripheral driven pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_Inv
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ GPIO_PRT_OUT_INV(base) = CY_GPIO_OUT_MASK << pinNum;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetDrivemode
+****************************************************************************//**
+*
+* Configures the pin output buffer drive mode and input buffer enable.
+*
+* The output buffer drive mode and input buffer enable are combined into a single
+* parameter. The drive mode controls the behavior of the pin in general.
+* Enabling the input buffer allows the digital pin state to be read but also
+* contributes to extra current consumption.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetDrivemode
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(value));
+
+ pinLoc = pinNum << CY_GPIO_DRIVE_MODE_OFFSET;
+ tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << pinLoc));
+ GPIO_PRT_CFG(base) = tempReg | ((value & CY_GPIO_CFG_DM_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetDrivemode
+****************************************************************************//**
+*
+* Returns the pin output buffer drive mode and input buffer enable state.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetDrivemode
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_CFG(base) >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetVtrip
+****************************************************************************//**
+*
+* Configures the GPIO pin input buffer voltage threshold mode.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* Pin voltage threshold mode. Options are detailed in \ref group_gpio_vtrip macros
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVtrip
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ tempReg = GPIO_PRT_CFG_IN(base) & ~(CY_GPIO_CFG_IN_VTRIP_SEL_MASK << pinNum);
+ GPIO_PRT_CFG_IN(base) = tempReg | ((value & CY_GPIO_CFG_IN_VTRIP_SEL_MASK) << pinNum);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetVtrip
+****************************************************************************//**
+*
+* Returns the pin input buffer voltage threshold mode.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* Pin voltage threshold mode. Options are detailed in \ref group_gpio_vtrip macros
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVtrip
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_CFG_IN(base) >> pinNum) & CY_GPIO_CFG_IN_VTRIP_SEL_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetSlewRate
+****************************************************************************//**
+*
+* Configures the pin output buffer slew rate.
+*
+* \note
+* This function has no effect for the GPIO ports, where the slew rate
+* configuration is not available. Refer to device datasheet for details.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* Pin slew rate. Options are detailed in \ref group_gpio_slewRate macros
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetSlewRate
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_SLOW_MASK << pinNum);
+ GPIO_PRT_CFG_OUT(base) = tempReg | ((value & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetSlewRate
+****************************************************************************//**
+*
+* Returns the pin output buffer slew rate.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* Pin slew rate. Options are detailed in \ref group_gpio_slewRate macros
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetSlewRate
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_CFG_OUT(base) >> pinNum) & CY_GPIO_CFG_OUT_SLOW_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetDriveSel
+****************************************************************************//**
+*
+* Configures the pin output buffer drive strength.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* Pin drive strength. Options are detailed in \ref group_gpio_driveStrength macros
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetDriveSel
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_DRIVE_SEL_VALID(value));
+
+ pinLoc = (uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET;
+ tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc);
+ GPIO_PRT_CFG_OUT(base) = tempReg | ((value & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetDriveSel
+****************************************************************************//**
+*
+* Returns the pin output buffer drive strength.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* Pin drive strength. Options are detailed in \ref group_gpio_driveStrength macros
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetDriveSel
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return ((GPIO_PRT_CFG_OUT(base) >> ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET))
+ & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK);
+}
+
+/** \} group_gpio_functions_gpio */
+
+/**
+* \addtogroup group_gpio_functions_sio
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetVregEn
+****************************************************************************//**
+*
+* Configures the SIO pin pair output buffer regulation mode.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* SIO pair output buffer regulator mode. Options are detailed in \ref group_gpio_sioVreg macros
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVregEn
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ pinLoc = (pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET;
+ tempReg = GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREG_EN_MASK << pinLoc);
+ GPIO_PRT_CFG_SIO(base) = tempReg | ((value & CY_GPIO_VREG_EN_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetVregEn
+****************************************************************************//**
+*
+* Returns the SIO pin pair output buffer regulation mode.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* SIO pair output buffer regulator mode. Options are detailed in \ref group_gpio_sioVreg macros
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVregEn
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_CFG_SIO(base) >> ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET)) & CY_GPIO_VREG_EN_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetIbufMode
+****************************************************************************//**
+*
+* Configures the SIO pin pair input buffer mode.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* SIO pair input buffer mode. Options are detailed in \ref group_gpio_sioIbuf macros
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetIbufMode
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT;
+ tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_IBUF_MASK << pinLoc));
+ GPIO_PRT_CFG_SIO(base) = tempReg | ((value & CY_GPIO_IBUF_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetIbufMode
+****************************************************************************//**
+*
+* Returns the SIO pin pair input buffer mode.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* SIO pair input buffer mode. Options are detailed in \ref group_gpio_sioIbuf macros
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetIbufMode
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_CFG_SIO(base) >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT)) & CY_GPIO_IBUF_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetVtripSel
+****************************************************************************//**
+*
+* Configures the SIO pin pair input buffer trip point.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* SIO pair input buffer trip point. Options are detailed in \ref group_gpio_sioVtrip macros
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVtripSel
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VTRIP_SEL_SHIFT;
+ tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VTRIP_SEL_MASK << pinLoc));
+ GPIO_PRT_CFG_SIO(base) = tempReg | ((value & CY_GPIO_VTRIP_SEL_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetVtripSel
+****************************************************************************//**
+*
+* Returns the SIO pin pair input buffer trip point.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* SIO pair input buffer trip point. Options are detailed in \ref group_gpio_sioVtrip macros
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVtripSel
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_CFG_SIO(base) >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VTRIP_SEL_SHIFT)) & CY_GPIO_VTRIP_SEL_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetVrefSel
+****************************************************************************//**
+*
+* Configures the SIO reference voltage for the input buffer trip point.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVref macros
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVrefSel
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(value));
+
+ pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT;
+ tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREF_SEL_MASK << pinLoc));
+ GPIO_PRT_CFG_SIO(base) = tempReg | ((value & CY_GPIO_VREF_SEL_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetVrefSel
+****************************************************************************//**
+*
+* Returns the SIO reference voltage for the input buffer trip point.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVref macros
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVrefSel
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_CFG_SIO(base) >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT)) & CY_GPIO_VREF_SEL_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetVohSel
+****************************************************************************//**
+*
+* Configures the regulated output reference multiplier for the SIO pin pair.
+*
+* The regulated output reference controls both the output level of digital output
+* pin and the input trip point of digital input pin in the SIO pair.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVoh macros
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVohSel
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VOH_SEL_VALID(value));
+
+ pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT;
+ tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VOH_SEL_MASK << pinLoc));
+ GPIO_PRT_CFG_SIO(base) = tempReg | ((value & CY_GPIO_VOH_SEL_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetVohSel
+****************************************************************************//**
+*
+* Returns the regulated output reference multiplier for the SIO pin pair.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVoh macros
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVohSel
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_CFG_SIO(base) >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT)) & CY_GPIO_VOH_SEL_MASK;
+}
+
+/** \} group_gpio_functions_sio */
+
+/**
+* \addtogroup group_gpio_functions_interrupt
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptStatus
+****************************************************************************//**
+*
+* Returns the current unmasked interrupt state of the pin.
+*
+* The core processor's NVIC is triggered by the masked interrupt bits. This
+* function allows reading the unmasked interrupt state. Whether the bit
+* positions actually trigger the interrupt are defined by the interrupt mask bits.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \return
+* 0 = Pin interrupt condition not detected
+* 1 = Pin interrupt condition detected
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_GetInterruptStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_INTR(base) >> pinNum) & CY_GPIO_INTR_STATUS_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_ClearInterrupt
+****************************************************************************//**
+*
+* Clears the triggered pin interrupt.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_ClearInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ /* Any INTR MMIO registers AHB clearing must be preceded with an AHB read access */
+ (void)GPIO_PRT_INTR(base);
+
+ GPIO_PRT_INTR(base) = CY_GPIO_INTR_STATUS_MASK << pinNum;
+
+ /* This read ensures that the initial write has been flushed out to the hardware */
+ (void)GPIO_PRT_INTR(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetInterruptMask
+****************************************************************************//**
+*
+* Configures the pin interrupt to be forwarded to the CPU NVIC.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \param value
+* 0 = Pin interrupt not forwarded to CPU interrupt controller
+* 1 = Pin interrupt masked and forwarded to CPU interrupt controller
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetInterruptMask
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ tempReg= GPIO_PRT_INTR_MASK(base) & ~(CY_GPIO_INTR_EN_MASK << pinNum);
+ GPIO_PRT_INTR_MASK(base) = tempReg | ((value & CY_GPIO_INTR_EN_MASK) << pinNum);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptMask
+****************************************************************************//**
+*
+* Returns the state of the pin interrupt mask.
+*
+* This mask is used to determine whether the pin is configured to be forwarded
+* to the CPU NVIC.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \return
+* 0 = Pin interrupt not forwarded to CPU interrupt controller
+* 1 = Pin interrupt masked and forwarded to CPU interrupt controller
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetInterruptMask
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_INTR_MASK(base) >> pinNum) & CY_GPIO_INTR_EN_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Return the pin's current interrupt state after being masked.
+*
+* The core processor's NVIC is triggered by the masked interrupt bits. This
+* function allows reading this masked interrupt state. Note that the bits that
+* are not masked will not be forwarded to the NVIC.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \return
+* 0 = Pin interrupt not detected or not forwarded to CPU interrupt controller
+* 1 = Pin interrupt detected and forwarded to CPU interrupt controller
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_INTR_MASKED(base) >> pinNum) & CY_GPIO_INTR_MASKED_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetSwInterrupt
+****************************************************************************//**
+*
+* Force a pin interrupt to trigger.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetSwInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ GPIO_PRT_INTR_SET(base) = CY_GPIO_INTR_SET_MASK << pinNum;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetInterruptEdge
+****************************************************************************//**
+*
+* Configures the type of edge that will trigger a pin interrupt.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \param value
+* Pin interrupt mode. Options are detailed in \ref group_gpio_interruptTrigger macros
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetInterruptEdge
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(value));
+
+ pinLoc = pinNum << CY_GPIO_INTR_CFG_OFFSET;
+ tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_EDGE_MASK << pinLoc);
+ GPIO_PRT_INTR_CFG(base) = tempReg | ((value & CY_GPIO_INTR_EDGE_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptEdge
+****************************************************************************//**
+*
+* Returns the current pin interrupt edge type.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \return
+* Pin interrupt mode. Options are detailed in \ref group_gpio_interruptTrigger macros
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetInterruptEdge
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ return (GPIO_PRT_INTR_CFG(base) >> (pinNum << CY_GPIO_INTR_CFG_OFFSET)) & CY_GPIO_INTR_EDGE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetFilter
+****************************************************************************//**
+*
+* Configures which pin on the port connects to the port-specific glitch filter.
+*
+* Each port contains a single 50ns glitch filter. Any of the pins on the port
+* can be routed to this filter such that the input signal is filtered before
+* reaching the edge-detect interrupt circuitry. The state of the filtered pin
+* can also be read by calling the Cy_GPIO_Read() function.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param value
+* The number of the port pin to route to the port filter (0...7)
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \note
+* The filtered pin does not have an associated HSIOM connection. Therefore
+* it cannot be routed directly to other peripherals in hardware.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetFilter
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value)
+{
+ uint32_t tempReg;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(value));
+
+ tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET);
+ GPIO_PRT_INTR_CFG(base) = tempReg | ((value & CY_GPIO_INTR_FLT_EDGE_MASK) << CY_GPIO_INTR_FILT_OFFSET);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetFilter
+****************************************************************************//**
+*
+* Returns which pin is currently configured to connect to the port-specific
+* glitch filter.
+*
+* Each port contains a single 50ns glitch filter. Any of the pins on the port
+* can be routed to this filter such that the input signal is filtered before
+* reaching the edge-detect interrupt circuitry. The state of the filtered pin
+* can also be read by calling the Cy_GPIO_Read() function.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \return
+* The number of the port pin routed to the port filter (0...7)
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetFilter
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base)
+{
+ return ((GPIO_PRT_INTR_CFG(base) >> CY_GPIO_INTR_FILT_OFFSET) & CY_GPIO_INTR_FLT_EDGE_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptCause0
+****************************************************************************//**
+*
+* Returns the interrupt status for ports 0 to 31.
+*
+* \return
+* 0 = Interrupt not detected on port
+* 1 = Interrupt detected on port
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_GetInterruptCause0
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void)
+{
+ return (GPIO_INTR_CAUSE0);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptCause1
+****************************************************************************//**
+*
+* Returns the interrupt status for ports 32 to 63.
+*
+* \return
+* 0 = Interrupt not detected on port
+* 1 = Interrupt detected on port
+*
+* \funcusage
+* Refer to the Cy_GPIO_GetInterruptCause0() example.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void)
+{
+ return (GPIO_INTR_CAUSE1);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptCause2
+****************************************************************************//**
+*
+* Returns the interrupt status for ports 64 to 95.
+*
+* \return
+* 0 = Interrupt not detected on port
+* 1 = Interrupt detected on port
+* \funcusage
+* Refer to the Cy_GPIO_GetInterruptCause0() example.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void)
+{
+ return (GPIO_INTR_CAUSE2);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptCause3
+****************************************************************************//**
+*
+* Returns the interrupt status for ports 96 to 127.
+*
+* \return
+* 0 = Interrupt not detected on port
+* 1 = Interrupt detected on port
+*
+* \funcusage
+* Refer to the Cy_GPIO_GetInterruptCause0() example.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void)
+{
+ return (GPIO_INTR_CAUSE3);
+}
+
+/** \} group_gpio_functions_interrupt */
+
+/** \} group_gpio_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_GPIO_H */
+
+/** \} group_gpio */
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_ipc_drv.h b/platform/ext/target/psoc64/Native_Driver/include/cy_ipc_drv.h
new file mode 100644
index 0000000000..95d3dc8087
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_ipc_drv.h
@@ -0,0 +1,1002 @@
+/***************************************************************************//**
+* \file cy_ipc_drv.h
+* \version 1.40
+*
+* Provides an API declaration of the IPC driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CY_IPC_DRV_H
+#define CY_IPC_DRV_H
+
+
+/**
+* \addtogroup group_ipc
+* \{
+* The inter-processor communication (IPC) driver provides a safe and reliable
+* method to transfer data between CPUs. Hardware locking ensures that only one
+* device can acquire and transfer data at a time so no data is lost or
+* overwritten by asynchronous processes or CPUs.
+*
+* Include either cy_ipc_pipe.h or cy_ipc_sema.h. Alternatively include cy_pdl.h
+* (ModusToolbox only) to get access to all functions and declarations in the PDL.
+*
+* There are three parts to the API:
+* - Driver-level (DRV) API - used internally by Semaphore and Pipe levels
+* - Pipe-level (PIPE) API - establishes a communication channel between
+* processors
+* - Semaphore-level (SEMA) API - enables users to set and clear flags to
+* synchronize operations.
+*
+* Firmware does not need to use the DRV API. It can implement IPC functionality
+* entirely with the PIPE and SEMA APIs.
+*
+* \section group_ipc_background Background
+*
+* IPC is implemented in hardware as a collection of individual communication
+* channels, each with a set of 32-bit registers. The IPC design implements a set
+* of interrupts that enable each processor to notify the other that data is
+* available, or has been processed. There is also a locking mechanism that
+* allows only one CPU to gain access at a time.
+*
+* The Driver-level API manages each channel's registers to implement IPC
+* functionality. For information on the IPC registers, see the IPC chapter of
+* the Technical Reference Manual (TRM).
+*
+* At the hardware level, communication is a five-step process.
+* -# The sending processor acquires a channel
+* -# It puts data into the channel
+* -# The sender generates a notify event (interrupt)
+* -# The receiving processor identifies the sender and retrieves the data
+* -# The receiving processor generates a release event (interrupt)
+*
+* \image html ipc_driver.png
+*
+* These transactions are handled transparently by the DRV-level API. Use the
+* PIPE and SEMA layers of the API to implement communication in your application.
+* The data transferred is limited to a single 32-bit value. As implemented by
+* the PIPE API, that value is a pointer to a data structure of arbitrary size
+* and complexity.
+*
+* \section group_ipc_overview Overview
+*
+* The Pipe is the key element in the PDL design. A pipe is typically a
+* full-duplex communication channel between CPU cores. A pipe allows a single
+* conduit to transfer messages or data to and from multiple processes or CPUs.
+*
+* A pipe has two endpoints, one on each core. Each endpoint contains a dedicated
+* IPC channel and an interrupt. IPC channels 0-7(8 for the CYB064XX devices)
+* and IPC interrupts 0-7 are reserved for system use.
+*
+* The pipe also contains the number of clients it supports, and for each client
+* a callback function. So the pipe can service a number of clients, each with a
+* separate callback function, on either endpoint. The number of clients a pipe
+* supports is the sum of each endpoint's clients.
+*
+* This design enables any number of processes on the sending core to put
+* arbitrary data into a single pipe. The first element of that data is the
+* client ID of the client that should handle the data.
+*
+* An interrupt notifies the receiving core that data is available. The receiving
+* core parses the data to identify the client, and then dispatches the event to
+* the appropriate client via the client callback function. An interrupt notifies
+* the sending core that the receiver is finished. In this way a single pipe can
+* manage arbitrary data transfers between cores with data flowing in either
+* direction.
+*
+* \image html ipc_ints.png
+*
+* The application can use semaphores to control access to shared resources, as
+* required by the application's logic.
+*
+* The PDL provides specific files that set up default IPC functionality.
+* They are system_psoc6.h, system_psoc6_cm0plus.c and system_psoc6_cm4.c. You
+* can modify these files based on the requirements of your design.
+* If you use PSoC Creator as a development environment, it will not overwrite
+* your changes when you generate the application or build your code.
+*
+* \section group_ipc_pipe_layer PIPE layer
+*
+* A pipe is a communication channel between two endpoints. PSoC 6 devices support
+* 16 IPC channels, and 16 IPC interrupts, each numbered 0-15. IPC Channels 0-7
+* and IPC interrupts 0-7 are reserved for system use. Channels 8-15 and
+* interrupts 8-15 are available for application use.
+*
+* A full duplex pipe uses two IPC channels, one per endpoint. Each endpoint
+* specifies all the information required to process a message (either sent or
+* received). Each endpoint is configured to use an IPC channel, and an IPC
+* interrupt. Common practice is to use the interrupt with the same number as
+* the IPC channel. However, IPC Interrupts are not directly associated with the
+* IPC channels, so any channel can use any interrupt. Any IPC channel can
+* trigger 0, 1 or all the IPC interrupts at once, depending on the Notify or
+* Release masks used.
+*
+* It is also possible to set up a one-directional pipe, using a single IPC
+* channel. In this design one processor is always the sender, and the other is
+* always the receiver. However, there are still two endpoints.
+*
+* A pipe supports an arbitrary number of clients with an array of callback
+* functions, one per client. The client ID is the index number into the array
+* for the client. After a pipe is configured and initialized, the application
+* calls Cy_IPC_Pipe_RegisterCallback() once per client to register each client's
+* callback function. Multiple clients can use the same callback function. The
+* endpoints in a pipe share the callback array.
+*
+* Use Cy_IPC_Pipe_SendMessage() to send data. You specify both the "to" and
+* "from" endpoints, and a callback function to be used when the data transfer is
+* complete. The data is a 32-bit void pointer. The data pointed to is arbitrary,
+* and can be an array, a structure, or a location in memory. The only limitation
+* is that the first element of the data must be a 32-bit unsigned word containing
+* a client ID number. The ID number is the index into the callback array.
+*
+* When a message is sent, the receiving endpoint's interrupt handler is called.
+* The ISR can perform any task required by the design. However, as part of its
+* function it calls \ref Cy_IPC_Pipe_ExecCallback. This function retrieves the
+* client ID from the data and calls the associated callback function.
+* The user-supplied callback function handles the data in whatever way is
+* appropriate based on the application logic.
+*
+* After the callback function is returned by the receiver, it invokes the release
+* callback function defined by the sender of the message.
+*
+* \section group_ipc_sema_layer SEMA Layer
+*
+* A semaphore is a flag the application uses to control access to a shared
+* resource. The SEMA-level API uses an IPC channel to implement
+* semaphores. Startup code sets up a default semaphore system. The
+* default system creates an array of 128 semaphores (four 32-bit values).
+* Semaphores 0-15 are reserved for system use. See
+* Configuration Considerations - SEMA.
+*
+* Functions are available to initialize the semaphore system, to set or
+* clear a semaphore, or to get the semaphore's current status. Application
+* logic uses SEMA functions to relate a particular semaphore to a particular
+* shared resource, and set, clear, or check the flag when accessing the
+* shared resource.
+*
+* \section group_ipc_configuration_cypipe Configuration Considerations - CYPIPE
+*
+* There are none. The startup files set up the required CYPIPE for system
+* use. Do not modify the CYPIPE. It uses IPC channels 5 and 6 to implement full
+* duplex communication between cores. See System Interrupt (SysInt) for background.
+*
+* To create your own pipe (<b>USRPIPE</b>) you should edit startup files
+* and take 4 steps:
+* -# Define a pipe callbacks processing interrupt handler
+* (similar to <b>Cy_SysIpcPipeIsrCm0</b> or <b>Cy_SysIpcPipeIsrCm4</b>)
+* -# Define a callbacks array (similar to <b>systemIpcPipeSysCbArray</b>)
+* -# Define your pipe configuration with a cy_stc_ipc_pipe_config_t type structure
+* (similar to <b>systemIpcPipeConfigCm0</b> and <b>systemIpcPipeConfigCm4</b>)
+* -# Call Cy_IPC_Pipe_Init() from each core to initialize your pipe (similar
+* to call in the <b>SystemInit</b>)
+*
+* \section group_ipc_configuration_sema Configuration Considerations - SEMA
+*
+* Startup code calls Cy_IPC_Sema_Init() with default values to set up semaphore
+* functionality. By default the semaphore system uses IPC channel 4, and
+* creates 128 semaphores. Do <b>not</b> change the IPC channel.
+* You can change the number of semaphores.
+*
+* To change the number of semaphores, modify this line of code in system_psoc6.h.
+*
+* \code
+* #define CY_IPC_SEMA_COUNT (uint32_t)(128u)
+* \endcode
+*
+* Startup also declares array ipcSemaArray to hold the semaphore
+* flags based on the size defined for this symbol. Use increments of 32. You
+* must have at least 32 semaphores. Semaphores 0-15 are reserved for
+* system use. Your application can use semaphores greater than 15.
+*
+* \section group_ipc_more_information More Information
+*
+* If the default startup file is not used, or SystemInit() is not called in your
+* project, call the following three functions prior to executing any flash or
+* EmEEPROM write or erase operation:
+* -# Cy_IPC_Sema_Init()
+* -# Cy_IPC_Pipe_Config()
+* -# Cy_IPC_Pipe_Init()
+* -# Cy_Flash_Init()
+*
+* See the technical reference manual(TRM) for more information on the IPC.
+*
+* \section group_ipc_MISRA MISRA-C Compliance
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th style="width: 50%;">Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>10.3</td>
+* <td>R</td>
+* <td>The value of a complex expression of integer type shall be cast
+* only to a type of the same signedness that is no wider than the underlying
+* type of the expression.</td>
+* <td>The cast from integer to enumeration value is used to calculate
+* the interrupt vector source from the integer number of the IPC interrupt
+* structure, so there is no way to avoid this cast.</td>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to the void to a
+* pointer to the object type.</td>
+* <td>The cast from the void to pointer and vice versa is used to transmit
+* data via the \ref group_ipc channel by exchanging the pointer. We
+* exchange only one pointer, so there is no way to avoid this cast.</td>
+* </tr>
+* </table>
+*
+* \section group_ipc_changelog Changelog
+*
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td rowspan="1">1.40</td>
+* <td>Moved cy_semaData structure to the RAM section called ".cy_sharedmem".</td>
+* <td>Support Secure Boot devices.</td>
+* </tr>
+* <tr>
+* <td rowspan="3">1.30</td>
+* <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup, removed cy_ipc_config.c and cy_ipc_config.h files.</td>
+* <td>Changed IPC driver configuration method from compile time to run time.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>1.20</td>
+* <td>Added \ref Cy_IPC_Pipe_ExecuteCallback function.
+* Updated documentation about user pipe initialization.
+* </td>
+* <td>Interface improvement, documentation update</td>
+* </tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Updated description of the \ref Cy_IPC_Pipe_Init,
+* \ref Cy_IPC_Pipe_EndpointInit, \ref Cy_IPC_Sema_Set functions.
+* Added / updated code snippets.
+* </td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.10</td>
+* <td>Added support for more IPC structures</td>
+* <td>New device support</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_ipc_drv IPC driver layer (IPC_DRV)
+* \{
+* The functions of this layer are used in the higher IPC levels
+* (Semaphores and Pipes).
+* Users are not expected to call any of these IPC functions directly (cy_ipc_drv.h).
+* Instead include either of cy_ipc_sema.h or cy_ipc_pipe.h.
+* Alternatively include cy_pdl.h to get access to all functions and declarations in the PDL.
+*
+* \defgroup group_ipc_macros Macros
+* Macro definitions are used in the driver
+*
+* \defgroup group_ipc_functions Functions
+* Functions are used in the driver
+*
+* \defgroup group_ipc_data_structures Data Structures
+* Data structures are used in the driver
+*
+* \defgroup group_ipc_enums Enumerated Types
+* Enumerations are used in the driver
+* \}
+*
+* \defgroup group_ipc_sema IPC semaphores layer (IPC_SEMA)
+* \defgroup group_ipc_pipe IPC pipes layer (IPC_PIPE)
+*
+*/
+
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include <stddef.h>
+
+
+/**
+* \addtogroup group_ipc_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_IPC_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_IPC_DRV_VERSION_MINOR 40
+
+/** Defines a value to indicate that no notification events are needed */
+#define CY_IPC_NO_NOTIFICATION (uint32_t)(0x00000000ul)
+
+/* Error Code constants */
+#define CY_IPC_ID CY_PDL_DRV_ID(0x22u) /**< Software PDL driver ID for IPC */
+
+/** Return prefix for IPC driver function status codes */
+#define CY_IPC_ID_INFO (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_INFO )
+/** Return prefix for IPC driver function warning return values */
+#define CY_IPC_ID_WARNING (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_WARNING)
+/** Return prefix for IPC driver function error return values */
+#define CY_IPC_ID_ERROR (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_ERROR)
+
+/** Converts the IPC interrupt channel number to interrupt vector */
+#define CY_IPC_INTR_NUM_TO_VECT(x) ((int32_t) cy_device->cpussIpc0Irq + (x))
+
+/** \} group_ipc_macros */
+
+/* end of definition in device.h */
+
+/** \cond INTERNAL */
+#if (CY_CPU_CORTEX_M0P)
+ #define CY_IPC_CHAN_SYSCALL CY_IPC_CHAN_SYSCALL_CM0
+#else
+ #define CY_IPC_CHAN_SYSCALL CY_IPC_CHAN_SYSCALL_CM4
+#endif /* (CY_CPU_CORTEX_M0P) */
+/** \endcond */
+
+/**
+* \addtogroup group_ipc_enums
+* \{
+*/
+
+/**
+* This is a list of ENUMs used for function return status.
+*/
+typedef enum
+{
+ /** Function was successfully executed */
+ CY_IPC_DRV_SUCCESS = (0x00u),
+ /** Function was not executed due to an error.
+ Typical conditions for the error explained
+ in the function description */
+ CY_IPC_DRV_ERROR = ( CY_IPC_ID_ERROR + 1ul),
+} cy_en_ipcdrv_status_t;
+
+/** \} group_ipc_enums */
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \cond INTERNAL */
+
+__STATIC_INLINE void Cy_IPC_Drv_WriteDataValue (IPC_STRUCT_Type* base, uint32_t dataValue);
+__STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base);
+
+__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractAcquireMask (uint32_t intMask);
+__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractReleaseMask (uint32_t intMask);
+
+/** \endcond */
+
+/**
+* \addtogroup group_ipc_functions
+* \{
+*/
+
+__STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex);
+__STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIntrIndex);
+
+__STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type * base, uint32_t notifyEventIntr);
+__STATIC_INLINE void Cy_IPC_Drv_ReleaseNotify (IPC_STRUCT_Type * base, uint32_t notifyEventIntr);
+
+__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_LockAcquire (IPC_STRUCT_Type const * base);
+cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type * base, uint32_t releaseEventIntr);
+__STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base);
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetLockStatus (IPC_STRUCT_Type const * base);
+
+cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type * base, uint32_t notifyEventIntr, uint32_t message);
+cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgWord (IPC_STRUCT_Type const * base, uint32_t * message);
+__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr (IPC_STRUCT_Type* base, uint32_t notifyEventIntr, void const * msgPtr);
+__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type const * base, void ** msgPtr);
+
+__STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type * base,
+ uint32_t ipcReleaseMask, uint32_t ipcAcquireMask);
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask (IPC_INTR_STRUCT_Type const * base);
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Type const * base);
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus (IPC_INTR_STRUCT_Type const * base);
+__STATIC_INLINE void Cy_IPC_Drv_SetInterrupt (IPC_INTR_STRUCT_Type * base,
+ uint32_t ipcReleaseMask, uint32_t ipcAcquireMask);
+__STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt (IPC_INTR_STRUCT_Type * base,
+ uint32_t ipcReleaseMask, uint32_t ipcAcquireMask);
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_GetIpcBaseAddress
+****************************************************************************//**
+*
+* This function takes an IPC channel index as a parameter and returns the base
+* address the IPC registers corresponding to the IPC channel.
+*
+* \note The user is responsible for ensuring that ipcIndex does not exceed the
+* limits.
+*
+* \param ipcIndex
+* Represents the number of IPC structure. This is converted to the base address of
+* the IPC channel registers.
+*
+* \return
+* Returns a pointer to the base of the IPC registers.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_SendMsgWord
+*
+*******************************************************************************/
+__STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex)
+{
+ CY_ASSERT_L1(CY_IPC_CHANNELS > ipcIndex);
+ return ( (IPC_STRUCT_Type*) CY_IPC_STRUCT_PTR(ipcIndex));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_GetIntrBaseAddr
+****************************************************************************//**
+*
+* This function takes an IPC interrupt structure index and returns the base
+* address of the IPC interrupt registers corresponding to the IPC Interrupt.
+*
+* \note The user is responsible for ensuring that ipcIntrIndex does not exceed the
+* limits.
+*
+* \param ipcIntrIndex
+* Represents the number of IPC interrupt structure. This is converted to the
+* base address of the IPC interrupt registers.
+*
+* \return
+* Returns a pointer to the base of the IPC interrupt registers.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetInterruptStatus
+*
+*******************************************************************************/
+__STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIntrIndex)
+{
+ CY_ASSERT_L1(CY_IPC_INTERRUPTS > ipcIntrIndex);
+ return ( (IPC_INTR_STRUCT_Type*) &(((IPC_Type *)cy_device->ipcBase)->INTR_STRUCT[ipcIntrIndex]) );
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_SetInterruptMask
+****************************************************************************//**
+*
+* This function is used to set the interrupt mask for an IPC Interrupt.
+* The mask sets release or acquire notification events for all IPC channels.
+*
+* \param base
+* This is a handle to the IPC interrupt. This handle can be calculated from the
+* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
+*
+* \param ipcReleaseMask
+* An encoded list of all IPC channels that can trigger the interrupt on a
+* release event.
+*
+* \param ipcAcquireMask
+* An encoded list of all IPC channels that can trigger the interrupt on a
+* notify event.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type* base,
+ uint32_t ipcReleaseMask, uint32_t ipcAcquireMask)
+{
+ CY_ASSERT_L1(0ul == (ipcAcquireMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk)));
+ CY_ASSERT_L1(0ul == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk)));
+ REG_IPC_INTR_STRUCT_INTR_MASK(base) = _VAL2FLD( IPC_INTR_STRUCT_INTR_MASK_NOTIFY, ipcAcquireMask) |
+ _VAL2FLD( IPC_INTR_STRUCT_INTR_MASK_RELEASE, ipcReleaseMask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_GetInterruptMask
+****************************************************************************//**
+*
+* This function is used to read the interrupt mask.
+*
+* \param base
+* This is a handle to the IPC interrupt. This handle can be calculated from
+* the IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
+*
+* \return
+* The return value is encoded as follows
+* <table>
+* <tr><th>Interrupt sources <th>Value
+* <tr><td>Ipc_PORTX_RELEASE <td>Xth bit set
+* <tr><td>Ipc_PORTX_NOTIFY <td>X+16th bit set
+* </table>
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask(IPC_INTR_STRUCT_Type const * base)
+{
+ return REG_IPC_INTR_STRUCT_INTR_MASK(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* This function is used to read the active unmasked interrupt. This function
+* can be used in the interrupt service routine to find which source triggered
+* the interrupt.
+*
+* \param base
+* This is a handle to the IPC interrupt. This handle can be calculated from the
+* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
+*
+* \return
+* The return value is encoded as follows
+* <table>
+* <tr><th>Interrupt sources <th>Value
+* <tr><td>Ipc_PORTX_RELEASE <td>Xth bit set
+* <tr><td>Ipc_PORTX_NOTIFY <td>X+16th bit set
+* </table>
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Type const * base)
+{
+ return REG_IPC_INTR_STRUCT_INTR_MASKED(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_GetInterruptStatus
+****************************************************************************//**
+*
+* This function is used to read the pending interrupts. Note that this read is
+* an unmasked read of the interrupt status. Interrupt sources read as active by
+* this function would generate interrupts only if they were not masked.
+*
+* \param base
+* This is a handle to the IPC interrupt. This handle can be calculated from the
+* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
+*
+* \return
+* The return value is encoded as follows
+* <table>
+* <tr><th>Interrupt sources <th>Value
+* <tr><td>Ipc_PORTX_RELEASE <td>Xth bit set
+* <tr><td>Ipc_PORTX_NOTIFY <td>X+16th bit set
+* </table>
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetInterruptStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus(IPC_INTR_STRUCT_Type const * base)
+{
+ return REG_IPC_INTR_STRUCT_INTR(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_SetInterrupt
+****************************************************************************//**
+*
+* This function is used to set the interrupt source. This function can be used
+* to activate interrupts through software.
+* \note That interrupt sources set using this interrupt would generate interrupts
+* only if they are not masked.
+*
+* \param base
+* This is a handle to the IPC interrupt. This handle can be calculated from the
+* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
+*
+* \param ipcReleaseMask
+* An encoded list of all IPC channels that can trigger the interrupt on a
+* release event.
+*
+* \param ipcAcquireMask
+* An encoded list of all IPC channels that can trigger the interrupt on a
+* notify event.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_SetInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_IPC_Drv_SetInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcAcquireMask)
+{
+ CY_ASSERT_L1(0ul == (ipcAcquireMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk)));
+ CY_ASSERT_L1(0ul == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk)));
+ REG_IPC_INTR_STRUCT_INTR_SET(base) = _VAL2FLD( IPC_INTR_STRUCT_INTR_NOTIFY, ipcAcquireMask ) |
+ _VAL2FLD( IPC_INTR_STRUCT_INTR_RELEASE, ipcReleaseMask );
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ClearInterrupt
+****************************************************************************//**
+*
+* This function is used to clear the interrupt source. Use this function to clear
+* a pending interrupt source in the interrupt status.
+*
+* \param base
+* This is a handle to the IPC interrupt. This handle can be calculated from the
+* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
+*
+* \param ipcReleaseMask
+* An encoded list of all IPC channels that can trigger the interrupt on a
+* release event.
+*
+* \param ipcAcquireMask
+* An encoded list of all IPC channels that can trigger the interrupt on a
+* notify event.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcAcquireMask)
+{
+ CY_ASSERT_L1(0ul == (ipcAcquireMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk)));
+ CY_ASSERT_L1(0ul == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk)));
+ REG_IPC_INTR_STRUCT_INTR(base) = _VAL2FLD(IPC_INTR_STRUCT_INTR_NOTIFY, ipcAcquireMask) |
+ _VAL2FLD(IPC_INTR_STRUCT_INTR_RELEASE, ipcReleaseMask);
+ (void)REG_IPC_INTR_STRUCT_INTR(base); /* Read the register to flush the cache */
+}
+
+/** \} group_ipc_functions */
+
+/** \} group_ipc */
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_AcquireNotify
+****************************************************************************//**
+*
+* The function generates a acquire notification event by IPC interrupt structure.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param notifyEventIntr
+* Bit encoded list of IPC interrupt structures that are triggered
+* by a notification. Bit number correspond to number of the IPC interrupt
+* structure.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_LockAcquire
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr)
+{
+ CY_ASSERT_L1(0ul == (notifyEventIntr & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk)));
+ REG_IPC_STRUCT_NOTIFY(base) = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, notifyEventIntr);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ReleaseNotify
+****************************************************************************//**
+*
+* The function generates a release notification event by IPC interrupt structure.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param notifyEventIntr
+* Bit encoded list of IPC interrupt lines that are triggered by a notification.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_ReadMsgWord
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_IPC_Drv_ReleaseNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr)
+{
+ CY_ASSERT_L1(0ul == (notifyEventIntr & ~(uint32_t)(IPC_INTR_STRUCT_INTR_RELEASE_Msk)));
+ REG_IPC_STRUCT_RELEASE(base) = _VAL2FLD(IPC_INTR_STRUCT_INTR_RELEASE, notifyEventIntr);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_WriteDataValue
+****************************************************************************//**
+*
+* The function writes a value to the DATA register of the IPC channel.
+*
+* This function is internal and should not be called directly by user
+* software.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param dataValue
+* Value to be written.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_IPC_Drv_WriteDataValue (IPC_STRUCT_Type* base, uint32_t dataValue)
+{
+ REG_IPC_STRUCT_DATA(base) = dataValue;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ReadDataValue
+****************************************************************************//**
+*
+* The function reads a value from the DATA register of the IPC channel.
+*
+* This function is internal and should not be called directly by user
+* software.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \return
+* Value from DATA register.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base)
+{
+ return REG_IPC_STRUCT_DATA(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_IsLockAcquired
+****************************************************************************//**
+*
+* The function is used to test the status of an IPC channel. The function
+* tells the reader if the IPC channel was in the locked or released state.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \return
+* Status for the function:
+* true: The IPC channel is in the Locked state.
+* false: The IPC channel is in the Released state.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_LockAcquire
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base)
+{
+ return ( 0u != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_LOCK_STATUS(base)) );
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_GetLockStatus
+****************************************************************************//**
+*
+* The function is used to get the status of an IPC channel.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \return
+* Value from LOCK_STATUS register.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_GetLockStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetLockStatus (IPC_STRUCT_Type const * base)
+{
+ return REG_IPC_STRUCT_LOCK_STATUS(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ExtractAcquireMask
+****************************************************************************//**
+*
+* The function extracts an Acquire mask part from full interrupt mask value.
+*
+* This function is internal and should not be called directly by user
+* software.
+*
+* \param intMask
+* Interrupt mask value to be processed.
+*
+* \return
+* Acquire mask value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractAcquireMask (uint32_t intMask)
+{
+ return _FLD2VAL(IPC_INTR_STRUCT_INTR_MASK_NOTIFY, intMask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ExtractReleaseMask
+****************************************************************************//**
+*
+* The function extracts a Release mask part from full interrupt mask value.
+*
+* This function is internal and should not be called directly by user
+* software.
+*
+* \param intMask
+* Interrupt mask value to be processed.
+*
+* \return
+* Release mask value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractReleaseMask (uint32_t intMask)
+{
+ return _FLD2VAL(IPC_INTR_STRUCT_INTR_MASK_RELEASE, intMask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_SendMsgPtr
+****************************************************************************//**
+*
+* This function is used to send a message pointer through an IPC channel.
+* The message structure may hold a generic pointer that may contain the address
+* of any user data type or structure. This parameter could be a pointer to a 32-bit
+* integer, an array, or even a data structure defined in the user code. This
+* function acts as a transfer engine for sending the pointer. Any memory
+* management of the pointer allocation and deallocation is up to the application
+* code.
+* The function also has an associated notification field that will let the
+* message notify one or multiple interrupts.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param notifyEventIntr
+* Bit encoded list of IPC interrupt lines that are triggered during the release
+* action.
+*
+* \param msgPtr
+* The message pointer that is being sent over the IPC channel.
+*
+* \return Status of the operation:
+* \retval CY_IPC_DRV_SUCCESS: The send operation was successful.
+* \retval CY_IPC_DRV_ERROR: The IPC channel is unavailable because
+* it is already locked.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_SendMsgPtr
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr(IPC_STRUCT_Type* base, uint32_t notifyEventIntr, void const * msgPtr)
+{
+ CY_ASSERT_L1(NULL != msgPtr);
+ return Cy_IPC_Drv_SendMsgWord(base, notifyEventIntr, (uint32_t)msgPtr);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ReadMsgPtr
+****************************************************************************//**
+*
+* This function is used to read a 32-bit pointer message through an IPC channel.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param msgPtr
+* Pointer variable to hold the data pointer that is being read from the IPC
+* channel.
+*
+*
+* \return Status of the operation
+* \retval CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC
+* was acquired.
+* \retval CY_IPC_DRV_ERROR: The function encountered an error because the IPC
+* channel was already in a released state meaning the data
+* in it is invalid.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_ReadMsgPtr
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type const * base, void ** msgPtr)
+{
+ CY_ASSERT_L1(NULL != msgPtr);
+ return Cy_IPC_Drv_ReadMsgWord(base, (uint32_t *)msgPtr);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_LockAcquire
+****************************************************************************//**
+*
+* This function is used to acquire the IPC channel.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress
+*
+* \return Status of the operation
+* \retval CY_IPC_DRV_SUCCESS: The IPC was successfully acquired
+* \retval CY_IPC_DRV_ERROR: The IPC was not acquired because it was already acquired
+* by another master
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_LockAcquire
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_LockAcquire (IPC_STRUCT_Type const * base)
+{
+ return ( 0ul != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_ACQUIRE(base))) ? CY_IPC_DRV_SUCCESS : CY_IPC_DRV_ERROR;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(CY_IPC_DRV_H) */
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_ipc_pipe.h b/platform/ext/target/psoc64/Native_Driver/include/cy_ipc_pipe.h
new file mode 100644
index 0000000000..a8c9e78680
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_ipc_pipe.h
@@ -0,0 +1,291 @@
+/***************************************************************************//**
+* \file cy_ipc_pipe.h
+* \version 1.40
+*
+* Description:
+* IPC Pipe Driver - This header file contains all the function prototypes,
+* structure definitions, pipe constants, and pipe endpoint address definitions.
+*
+********************************************************************************
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#ifndef CY_IPC_PIPE_H
+#define CY_IPC_PIPE_H
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include "cy_ipc_drv.h"
+#include "cy_syslib.h"
+#include "cy_sysint.h"
+
+/**
+* \addtogroup group_ipc_pipe IPC pipes layer (IPC_PIPE)
+* \{
+* The Pipe functions provide a method to transfer one or more words of data
+* between CPUs or tasks.
+*
+* Include cy_ipc_pipe.h. Alternatively include cy_pdl.h (ModusToolbox only)
+* to get access to all functions and declarations in the PDL.
+*
+* The data can be defined as a single 32-bit unsigned
+* word, an array of data, or a user-defined structure. The only limitation is
+* that the first word in the array or structure must be a 32-bit unsigned word
+* in which a client ID number is passed. The client ID dictates the callback
+* function that will be called by the receiver of the message. After the
+* callback function returns by the receiver, it will invoke a release callback
+* function defined by the sender of the message.
+*
+* A User Pipe is provided for the user to transfer data between CPUs and
+* tasks.
+*
+* \defgroup group_ipc_pipe_macros Macros
+* Macro definitions are used in the driver
+*
+* \defgroup group_ipc_pipe_functions Functions
+* Functions are used in the driver
+*
+* \defgroup group_ipc_pipe_data_structures Data Structures
+* Data structures are used in the driver
+*
+* \defgroup group_ipc_pipe_enums Enumerated Types
+* Enumerations are used in the driver
+* \}
+*
+*/
+
+/*
+ * This section defines the system level constants required to define
+ * callback arrays for the Cypress pipe and the user pipe. These defines
+ * are used for both the max callback count and maximum clients.
+*/
+
+/** Typedef for pipe callback function pointer */
+typedef void (* cy_ipc_pipe_callback_ptr_t)(uint32_t * msgPtr);
+
+/** Typedef for a pipe release callback function pointer */
+typedef void (* cy_ipc_pipe_relcallback_ptr_t)(void);
+
+/** Typedef for array of callback function pointers */
+typedef cy_ipc_pipe_callback_ptr_t *cy_ipc_pipe_callback_array_ptr_t;
+
+
+/**
+* \addtogroup group_ipc_pipe_macros
+* \{
+*/
+
+/*
+ * The System pipe address is what is used to send a message to one of the
+ * endpoints of a pipe. Currently the Cypress pipe and the User pipe
+ * are supported. For parts with extra IPC channels users may create
+ * their own custom pipes and create their own pipe addresses.
+ *
+ * The format of the endpoint configuration
+ * Bits[31:16] Interrupt Mask
+ * Bits[15:8 ] IPC interrupt
+ * Bits[ 7:0 ] IPC channel
+ */
+#define CY_IPC_PIPE_CFG_IMASK_Pos (16UL) /**< Interrupts shift value for endpoint address */
+#define CY_IPC_PIPE_CFG_IMASK_Msk (0xFFFF0000UL) /**< Interrupts mask for endpoint address */
+#define CY_IPC_PIPE_CFG_INTR_Pos (8UL) /**< IPC Interrupt shift value for endpoint address */
+#define CY_IPC_PIPE_CFG_INTR_Msk (0x0000FF00UL) /**< IPC Interrupt mask for endpoint address */
+#define CY_IPC_PIPE_CFG_CHAN_Pos (0UL) /**< IPC Channel shift value for endpoint address */
+#define CY_IPC_PIPE_CFG_CHAN_Msk (0x000000FFUL) /**< IPC Channel mask for endpoint address */
+
+
+
+#define CY_IPC_PIPE_MSG_CLIENT_Msk (0x000000FFul) /**< Client mask for first word of Pipe message */
+#define CY_IPC_PIPE_MSG_CLIENT_Pos (0ul) /**< Client shift for first word of Pipe message */
+#define CY_IPC_PIPE_MSG_USR_Msk (0x0000FF00ul) /**< User data mask for first word of Pipe message */
+#define CY_IPC_PIPE_MSG_USR_Pos (8ul) /**< User data shift for first word of Pipe message */
+#define CY_IPC_PIPE_MSG_RELEASE_Msk (0xFFFF0000ul) /**< Mask for message release mask */
+#define CY_IPC_PIPE_MSG_RELEASE_Pos (16UL) /**< Shift require to line up mask to LSb */
+
+/** Use to set the busy flag when waiting for a release interrupt */
+#define CY_IPC_PIPE_ENDPOINT_BUSY (1UL)
+/** Denotes that a release interrupt is not pending */
+#define CY_IPC_PIPE_ENDPOINT_NOTBUSY (0UL)
+
+/** \} group_ipc_pipe_macros */
+
+/**
+* \addtogroup group_ipc_pipe_data_structures
+* \{
+*/
+
+/**
+* This is the definition of a pipe endpoint. There is one endpoint structure
+* for each CPU in a pipe. It contains all the information to process a message
+* send to other CPUs in the pipe.
+*/
+typedef struct
+{
+ uint32_t ipcChan; /**< IPC channel number used for this endpoint to receive messages */
+ uint32_t intrChan; /**< IPC interrupt channel number used for this endpoint to receive interrupts */
+ uint32_t pipeIntMask; /**< Release/Notify interrupt mask that includes all endpoints on pipe */
+ IRQn_Type pipeIntrSrc; /**< Interrupt vector number that includes all endpoints on pipe */
+
+ IPC_STRUCT_Type *ipcPtr; /**< Pointer to receive IPC channel ( If ipcPtr == NULL, cannot receive ) */
+ IPC_INTR_STRUCT_Type *ipcIntrPtr; /**< Pointer to IPC interrupt, needed to clear the interrupt */
+ uint32_t busy; /**< Endpoint busy flag. If sent no messages can be sent from this endpoint */
+ uint32_t clientCount; /**< Client count and size of MsgCallback array */
+
+ cy_ipc_pipe_callback_array_ptr_t callbackArray; /**< Pointer to array of callback functions, one for each Client */
+ cy_ipc_pipe_relcallback_ptr_t releaseCallbackPtr; /**< Pointer to release callback function */
+ cy_ipc_pipe_relcallback_ptr_t defaultReleaseCallbackPtr; /**< Pointer to default release callback function */
+} cy_stc_ipc_pipe_ep_t;
+
+/** The Pipe endpoint configuration structure. */
+typedef struct
+{
+ uint32_t ipcNotifierNumber; /**< Notifier */
+ uint32_t ipcNotifierPriority; /**< Notifier Priority */
+ uint32_t ipcNotifierMuxNumber; /**< CM0+ interrupt multiplexer number */
+
+ uint32_t epAddress; /**< Index in the array of endpoint structure */
+ uint32_t epConfig; /**< Configuration mask, contains IPC channel, IPC interrupt number,
+ and the interrupt mask */
+} cy_stc_ipc_pipe_ep_config_t;
+
+/** The Pipe channel configuration structure. */
+typedef struct
+{
+ /** Specifies the notify interrupt number for the first endpoint */
+ cy_stc_ipc_pipe_ep_config_t ep0ConfigData;
+
+ /** Specifies the notify interrupt number for the second endpoint */
+ cy_stc_ipc_pipe_ep_config_t ep1ConfigData;
+
+ /** Client count and size of MsgCallback array */
+ uint32_t endpointClientsCount;
+
+ /** Pipes callback function array. */
+ cy_ipc_pipe_callback_array_ptr_t endpointsCallbacksArray;
+
+ /** User IRQ handler function that is called when IPC receive data to process (interrupt was raised). */
+ cy_israddress userPipeIsrHandler;
+} cy_stc_ipc_pipe_config_t;
+
+/** \} goup_ipc_pipe_data_structures */
+
+/**
+* \addtogroup group_ipc_pipe_macros
+* \{
+*/
+/* Status and error types */
+#define CY_IPC_PIPE_RTN (0x0200ul) /**< Software PDL driver ID for IPC pipe functions */
+#define CY_IPC_PIPE_ID_INFO (uint32_t)( CY_IPC_ID_INFO | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function status codes */
+#define CY_IPC_PIPE_ID_WARNING (uint32_t)( CY_IPC_ID_WARNING | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function warning return values */
+#define CY_IPC_PIPE_ID_ERROR (uint32_t)( CY_IPC_ID_ERROR | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function error return values */
+
+/** \} group_ipc_pipe_macros */
+
+/**
+* \addtogroup group_ipc_pipe_enums
+* \{
+*/
+
+/** Return constants for IPC pipe functions. */
+typedef enum
+{
+ CY_IPC_PIPE_SUCCESS =(uint32_t)(0x00u), /**< Pipe API return for no error */
+ CY_IPC_PIPE_ERROR_NO_IPC =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 1ul), /**< Pipe API return for no valid IPC channel */
+ CY_IPC_PIPE_ERROR_NO_INTR =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 2ul), /**< Pipe API return for no valid interrupt */
+ CY_IPC_PIPE_ERROR_BAD_PRIORITY =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 3ul), /**< Pipe API return for bad priority parameter */
+ CY_IPC_PIPE_ERROR_BAD_HANDLE =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 4ul), /**< Pipe API return for bad pipe handle */
+ CY_IPC_PIPE_ERROR_BAD_ID =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 5ul), /**< Pipe API return for bad pipe ID */
+ CY_IPC_PIPE_ERROR_DIR_ERROR =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 6ul), /**< Pipe API return for invalid direction (Not used at this time) */
+ CY_IPC_PIPE_ERROR_SEND_BUSY =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 7ul), /**< Pipe API return for pipe is currently busy */
+ CY_IPC_PIPE_ERROR_NO_MESSAGE =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 8ul), /**< Pipe API return for no message indicated */
+ CY_IPC_PIPE_ERROR_BAD_CPU =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 9ul), /**< Pipe API return for invalid CPU value */
+ CY_IPC_PIPE_ERROR_BAD_CLIENT =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 10ul) /**< Pipe API return for client out of range */
+} cy_en_ipc_pipe_status_t;
+
+/** \} group_ipc_pipe_enums */
+
+#if (CY_CPU_CORTEX_M0P)
+ #define CY_IPC_EP_CYPIPE_ADDR CY_IPC_EP_CYPIPE_CM0_ADDR
+#else
+ #define CY_IPC_EP_CYPIPE_ADDR CY_IPC_EP_CYPIPE_CM4_ADDR
+#endif /* (CY_CPU_CORTEX_M0P) */
+
+/**
+* \addtogroup group_ipc_pipe_data_structures
+* \{
+*/
+
+/** \cond
+* NOTE: This doxygen comment must be placed before some code entity, or else
+* it will belong to a random entity that follows it, e.g. group_ipc_functions
+*
+* Client identifier for a message.
+* For a given pipe, traffic across the pipe can be multiplexed with multiple
+* senders on one end and multiple receivers on the other end.
+*
+* The first 32-bit word of the message is used to identify the client that owns
+* the message.
+*
+* The upper 16 bits are the client ID.
+*
+* The lower 16 bits are for use by the client in any way desired.
+*
+* The lower 16 bits are preserved (not modified) and not interpreted in any way.
+* \endcond
+*/
+
+/** \} group_ipc_pipe_data_structures */
+
+
+/******************************************************************************/
+/* Global function prototypes (definition in C source) */
+/******************************************************************************/
+
+/**
+* \addtogroup group_ipc_pipe_functions
+* \{
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void Cy_IPC_Pipe_EndpointInit(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t cbArray,
+ uint32_t cbCnt, uint32_t epConfig, cy_stc_sysint_t const *epInterrupt);
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAddr, void *msgPtr,
+ cy_ipc_pipe_relcallback_ptr_t callBackPtr);
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_RegisterCallback(uint32_t epAddr,
+ cy_ipc_pipe_callback_ptr_t callBackPtr, uint32_t clientId);
+void Cy_IPC_Pipe_ExecuteCallback(uint32_t epAddr);
+void Cy_IPC_Pipe_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_ptr_t callBackPtr);
+void Cy_IPC_Pipe_Config(cy_stc_ipc_pipe_ep_t * theEpArray);
+void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config);
+
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointPause(uint32_t epAddr);
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointResume(uint32_t epAddr);
+
+/* This function is obsolete and will be removed in the next releases */
+void Cy_IPC_Pipe_ExecCallback(cy_stc_ipc_pipe_ep_t * endpoint);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** \} group_ipc_pipe_functions */
+
+#endif /* CY_IPC_PIPE_H */
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_ipc_sema.h b/platform/ext/target/psoc64/Native_Driver/include/cy_ipc_sema.h
new file mode 100644
index 0000000000..a221e49977
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_ipc_sema.h
@@ -0,0 +1,141 @@
+/***************************************************************************//**
+* \file cy_ipc_sema.h
+* \version 1.40
+*
+* \brief
+* Header file for IPC SEM functions
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CY_IPC_SEMA_H
+#define CY_IPC_SEMA_H
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include "cy_ipc_drv.h"
+#include <stdbool.h>
+
+/**
+* \addtogroup group_ipc_sema IPC semaphores layer (IPC_SEMA)
+* \{
+* The semaphores layer functions made use of a single IPC channel to allow
+* multiple semaphores that can be used by system or user function calls.
+*
+* Include cy_ipc_sema.h. Alternatively include cy_pdl.h (ModusToolbox only)
+* to get access to all functions and declarations in the PDL.
+*
+* By default there are 128 semaphores provided, although the user may modify
+* the default value to any number, limited only by SRAM.
+*
+* \defgroup group_ipc_sema_macros Macros
+* Macro definitions are used in the driver
+*
+* \defgroup group_ipc_sema_functions Functions
+* Functions are used in the driver
+*
+* \defgroup group_ipc_sema_enums Enumerated Types
+* Enumerations are used in the driver
+* \}
+*
+* \addtogroup group_ipc_sema_macros
+* \{
+*/
+
+/** Software PDL driver ID for IPC semaphore functions */
+#define CY_IPC_SEMA_RTN (0x0100ul)
+/** Return prefix for IPC semaphore function status codes */
+#define CY_IPC_SEMA_ID_INFO (uint32_t)( CY_IPC_ID_INFO | CY_IPC_SEMA_RTN)
+/** Return prefix for IPC semaphore function warning return values */
+#define CY_IPC_SEMA_ID_WARNING (uint32_t)( CY_IPC_ID_WARNING | CY_IPC_SEMA_RTN)
+/** Return prefix for IPC semaphore function error return values */
+#define CY_IPC_SEMA_ID_ERROR (uint32_t)( CY_IPC_ID_ERROR | CY_IPC_SEMA_RTN)
+
+#define CY_IPC_SEMA_PER_WORD (uint32_t)32u /**< 32 semaphores per word */
+
+/** \} group_ipc_sema_macros */
+
+/**
+* \addtogroup group_ipc_sema_enums
+* \{
+*/
+
+/** Return constants for IPC semaphores functions. */
+typedef enum
+{
+ /** No error has occurred */
+ CY_IPC_SEMA_SUCCESS = (uint32_t)(0ul),
+ /** Semaphores IPC channel has already been locked */
+ CY_IPC_SEMA_ERROR_LOCKED = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 1ul),
+ /** Semaphores IPC channel is unlocked */
+ CY_IPC_SEMA_ERROR_UNLOCKED = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 2ul),
+ /** Semaphore API bad parameter */
+ CY_IPC_SEMA_BAD_PARAM = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 3ul),
+ /** Semaphore API return when semaphore number is out of the range */
+ CY_IPC_SEMA_OUT_OF_RANGE = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 4ul),
+
+ /** Semaphore API return when IPC channel was not acquired */
+ CY_IPC_SEMA_NOT_ACQUIRED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 2ul),
+ /** Semaphore API return status when semaphore channel is busy or locked
+* by another process */
+ CY_IPC_SEMA_LOCKED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 3ul),
+ /** Semaphore status return that the semaphore is set */
+ CY_IPC_SEMA_STATUS_LOCKED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 1ul),
+ /** Semaphore status return that the semaphore is cleared */
+ CY_IPC_SEMA_STATUS_UNLOCKED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 0ul)
+} cy_en_ipcsema_status_t;
+
+
+/** IPC semaphore control data structure. */
+typedef struct
+{
+ /** Maximum semaphores in system */
+ uint32_t maxSema;
+ /** Pointer to semaphores array */
+ uint32_t *arrayPtr;
+} cy_stc_ipc_sema_t;
+
+/** \} group_ipc_sema_enums */
+
+/**
+* \addtogroup group_ipc_sema_functions
+* \{
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+cy_en_ipcsema_status_t Cy_IPC_Sema_Init (uint32_t ipcChannel, uint32_t count, uint32_t memPtr[]);
+cy_en_ipcsema_status_t Cy_IPC_Sema_InitExt(uint32_t ipcChannel, cy_stc_ipc_sema_t *ipcSema);
+cy_en_ipcsema_status_t Cy_IPC_Sema_Set (uint32_t semaNumber, bool preemptable);
+cy_en_ipcsema_status_t Cy_IPC_Sema_Clear (uint32_t semaNumber, bool preemptable);
+cy_en_ipcsema_status_t Cy_IPC_Sema_Status (uint32_t semaNumber);
+uint32_t Cy_IPC_Sema_GetMaxSems(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** \} group_ipc_sema_functions */
+
+#endif /* CY_IPC_SEMA_H */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_mcwdt.h b/platform/ext/target/psoc64/Native_Driver/include/cy_mcwdt.h
new file mode 100644
index 0000000000..e6023c613e
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_mcwdt.h
@@ -0,0 +1,1122 @@
+/***************************************************************************//**
+* \file cy_mcwdt.h
+* \version 1.30
+*
+* Provides an API declaration of the Cypress PDL 3.0 MCWDT driver
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_mcwdt
+* \{
+* A MCWDT has two 16-bit counters and one 32-bit counter.
+*
+* The functions and other declarations used in this driver are in cy_mcwdt.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions
+* and declarations in the PDL.
+*
+* You can use this driver to create a free-running
+* timer or generate periodic interrupts. The driver also
+* includes support for the watchdog function to recover from CPU or
+* firmware failures.
+*
+* There are two primary use cases for MCWDT: generating periodic CPU interrupts;
+* and implementing a free-running timer. Both have many applications in
+* embedded systems:
+* * Measuring time between events
+* * Generating periodic events
+* * Synchronizing actions
+* * Real-time clocking
+* * Polling
+*
+* An additional use case is to implement a watchdog used for recovering from a CPU or
+* firmware failure.
+*
+* \section group_mcwdt_configuration Configuration Considerations
+*
+* Each MCWDT may be configured for a particular product.
+* One MCWDT block can be associated with only one CPU during runtime.
+* A single MCWDT is not intended to be used by multiple CPUs simultaneously.
+* Each block contains three sub-counters, each of which can be configured for
+* various system utility functions - free running counter, periodic interrupts,
+* watchdog reset, or three interrupts followed by a watchdog reset.
+* All counters are clocked by either LFCLK (nominal 32 kHz) or by a cascaded
+* counter.
+* A simplified diagram of the MCWDT hardware is shown below:
+* \image html mcwdt.png
+* The frequency of the periodic interrupts can be configured using the Match
+* value with combining Clear on match option, which can be set individually
+* for each counter using Cy_MCWDT_SetClearOnMatch(). When the Clear on match option
+* is not set, the periodic interrupts of the C0 and C1 16-bit sub-counters occur
+* after 65535 counts and the match value defines the shift between interrupts
+* (see the figure below). The enabled Clear on match option
+* resets the counter when the interrupt occurs.
+* \image html mcwdt_counters.png
+* 32-bit sub-counter C2 does not have Clear on match option.
+* The interrupt of counter C2 occurs when the counts equal
+* 2<sup>Toggle bit</sup> value.
+* \image html mcwdt_subcounters.png
+* To set up an MCWDT, provide the configuration parameters in the
+* cy_stc_mcwdt_config_t structure. Then call
+* Cy_MCWDT_Init() to initialize the driver.
+* Call Cy_MCWDT_Enable() to enable all specified counters.
+*
+* You can also set the mode of operation for any counter. If you choose
+* interrupt mode, use Cy_MCWDT_SetInterruptMask() with the
+* parameter for the masks described in Macro Section. All counter interrupts
+* are OR'd together to from a single combined MCWDT interrupt.
+* Additionally, enable the Global interrupts and initialize the referenced
+* interrupt by setting the priority and the interrupt vector using
+* \ref Cy_SysInt_Init() of the sysint driver.
+*
+* The values of the MCWDT counters can be monitored using
+* Cy_MCWDT_GetCount().
+*
+* \note In addition to the MCWDTs, each device has a separate watchdog timer
+* (WDT) that can also be used to generate a watchdog reset or periodic
+* interrupts. For more information on the WDT, see the appropriate section
+* of the PDL.
+*
+* \section group_mcwdt_more_information More Information
+*
+* For more information on the MCWDT peripheral, refer to
+* the technical reference manual (TRM).
+*
+* \section group_mcwdt_MISRA MISRA-C Compliance
+* The mcwdt driver does not have any specific deviations.
+*
+* \section group_mcwdt_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.30</td>
+* <td>In version 1.20 the Cy_MCWDT_GetCountCascaded() function
+* returned the wrong value when counter#1 overflowed.
+* This bug is corrected in version 1.30.
+* </td>
+* <td>Defect fixes.
+* </td>
+* </tr>
+* <tr>
+* <td>1.20</td>
+* <td>Flattened the organization of the driver source code into the single
+* source directory and the single include directory.
+* </td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Updated description of the \ref cy_stc_mcwdt_config_t structure type</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.10</td>
+* <td>Added input parameter validation to the API functions.<br>
+* Added API function GetCountCascaded()</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_mcwdt_macros Macros
+* \defgroup group_mcwdt_functions Functions
+* \defgroup group_mcwdt_data_structures Data Structures
+* \defgroup group_mcwdt_enums Enumerated Types
+*/
+
+#ifndef CY_MCWDT_H
+#define CY_MCWDT_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <stddef.h>
+#include "cy_device_headers.h"
+#include "cy_device.h"
+#include "cy_syslib.h"
+
+#ifdef CY_IP_MXS40SRSS_MCWDT
+
+/**
+* \addtogroup group_mcwdt_data_structures
+* \{
+*/
+
+/** The MCWDT component configuration structure. */
+typedef struct
+{
+ uint16_t c0Match; /**< The sub-counter#0 match comparison value, for interrupt or watchdog timeout.
+ Range: 0 - 65535 for c0ClearOnMatch = 0 and 1 - 65535 for
+ c0ClearOnMatch = 1. */
+ uint16_t c1Match; /**< The sub-counter#1 match comparison value, for interrupt or watchdog timeout.
+ Range: 0 - 65535 for c1ClearOnMatch = 0 and 1 - 65535 for
+ c1ClearOnMatch = 1. */
+ uint8_t c0Mode; /**< The sub-counter#0 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
+ \ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET. */
+ uint8_t c1Mode; /**< The sub-counter#1 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
+ \ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET. */
+ uint8_t c2ToggleBit; /**< The sub-counter#2 Period / Toggle Bit value.
+ Range: 0 - 31. */
+ uint8_t c2Mode; /**< The sub-counter#2 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE
+ and \ref CY_MCWDT_MODE_INT. */
+ bool c0ClearOnMatch; /**< The sub-counter#0 Clear On Match parameter enabled/disabled. */
+ bool c1ClearOnMatch; /**< The sub-counter#1 Clear On Match parameter enabled/disabled. */
+ bool c0c1Cascade; /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade. */
+ bool c1c2Cascade; /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade. */
+} cy_stc_mcwdt_config_t;
+
+/** \} group_mcwdt_data_structures */
+
+/**
+* \addtogroup group_mcwdt_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_MCWDT_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_MCWDT_DRV_VERSION_MINOR 30
+
+/** \cond INTERNAL_MACROS */
+
+/***************************************
+* Registers Constants
+***************************************/
+
+#define CY_MCWDT_LOCK_CLR0 (1u)
+#define CY_MCWDT_LOCK_CLR1 (2u)
+#define CY_MCWDT_LOCK_SET01 (3u)
+
+#define CY_MCWDT_BYTE_SHIFT (8u)
+#define CY_MCWDT_C0C1_MODE_MASK (3u)
+#define CY_MCWDT_C2_MODE_MASK (1u)
+
+
+/***************************************
+* API Constants
+***************************************/
+
+#define CY_MCWDT_ALL_WDT_ENABLE_Msk (MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk | MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk | \
+ MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk)
+
+#define CY_MCWDT_CTR0_Pos (0u)
+#define CY_MCWDT_CTR1_Pos (1u)
+#define CY_MCWDT_CTR2_Pos (2u)
+#define CY_MCWDT_CTR_Pos (0UL)
+
+/** \endcond */
+
+#define CY_MCWDT_ID CY_PDL_DRV_ID(0x35u) /**< MCWDT PDL ID */
+
+#define CY_MCWDT_CTR0 (1UL << CY_MCWDT_CTR0_Pos) /**< The sub-counter#0 mask. This macro is used with functions
+ that handle multiple counters, including Cy_MCWDT_Enable(),
+ Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
+#define CY_MCWDT_CTR1 (1UL << CY_MCWDT_CTR1_Pos) /**< The sub-counter#1 mask. This macro is used with functions
+ that handle multiple counters, including Cy_MCWDT_Enable(),
+ Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
+#define CY_MCWDT_CTR2 (1UL << CY_MCWDT_CTR2_Pos) /**< The sub-counter#2 mask. This macro is used with functions
+ that handle multiple counters, including Cy_MCWDT_Enable(),
+ Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
+#define CY_MCWDT_CTR_Msk (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2) /**< The mask for all sub-counters. This macro is used with functions
+ that handle multiple counters, including Cy_MCWDT_Enable(),
+ Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
+
+/** \} group_mcwdt_macros */
+
+
+/**
+* \addtogroup group_mcwdt_enums
+* \{
+*/
+
+/** The mcwdt sub-counter identifiers. */
+typedef enum
+{
+ CY_MCWDT_COUNTER0, /**< Sub-counter#0 identifier. */
+ CY_MCWDT_COUNTER1, /**< Sub-counter#1 identifier. */
+ CY_MCWDT_COUNTER2 /**< Sub-counter#2 identifier. */
+} cy_en_mcwdtctr_t;
+
+/** The mcwdt modes. */
+typedef enum
+{
+ CY_MCWDT_MODE_NONE, /**< The No action mode. It is used for Set/GetMode functions. */
+ CY_MCWDT_MODE_INT, /**< The Interrupt mode. It is used for Set/GetMode functions. */
+ CY_MCWDT_MODE_RESET, /**< The Reset mode. It is used for Set/GetMode functions. */
+ CY_MCWDT_MODE_INT_RESET /**< The Three interrupts then watchdog reset mode. It is used for
+ Set/GetMode functions. */
+} cy_en_mcwdtmode_t;
+
+/** The mcwdt cascading. */
+typedef enum
+{
+ CY_MCWDT_CASCADE_NONE, /**< The cascading is disabled. It is used for Set/GetCascade functions. */
+ CY_MCWDT_CASCADE_C0C1, /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade.
+ It is used for Set/GetCascade functions. */
+ CY_MCWDT_CASCADE_C1C2, /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
+ It is used for Set/GetCascade functions. */
+ CY_MCWDT_CASCADE_BOTH /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade
+ and the sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
+ It is used for Set/GetCascade functions. */
+} cy_en_mcwdtcascade_t;
+
+/** The MCWDT error codes. */
+typedef enum
+{
+ CY_MCWDT_SUCCESS = 0x00u, /**< Successful */
+ CY_MCWDT_BAD_PARAM = CY_MCWDT_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */
+} cy_en_mcwdt_status_t;
+
+/** \} group_mcwdt_enums */
+
+
+/** \cond PARAM_CHECK_MACROS */
+
+/** Parameter check macros */
+#define CY_MCWDT_IS_CNTS_MASK_VALID(counters) (0U == ((counters) & (uint32_t)~CY_MCWDT_CTR_Msk))
+
+#define CY_MCWDT_IS_CNT_NUM_VALID(counter) ((CY_MCWDT_COUNTER0 == (counter)) || \
+ (CY_MCWDT_COUNTER1 == (counter)) || \
+ (CY_MCWDT_COUNTER2 == (counter)))
+
+#define CY_MCWDT_IS_MODE_VALID(mode) ((CY_MCWDT_MODE_NONE == (mode)) || \
+ (CY_MCWDT_MODE_INT == (mode)) || \
+ (CY_MCWDT_MODE_RESET == (mode)) || \
+ (CY_MCWDT_MODE_INT_RESET == (mode)))
+
+#define CY_MCWDT_IS_ENABLE_VALID(enable) (1UL >= (enable))
+
+
+#define CY_MCWDT_IS_CASCADE_VALID(cascade) ((CY_MCWDT_CASCADE_NONE == (cascade)) || \
+ (CY_MCWDT_CASCADE_C0C1 == (cascade)) || \
+ (CY_MCWDT_CASCADE_C1C2 == (cascade)) || \
+ (CY_MCWDT_CASCADE_BOTH == (cascade)))
+
+#define CY_MCWDT_IS_MATCH_VALID(clearOnMatch, match) ((clearOnMatch) ? (1UL <= (match)) : true)
+
+#define CY_MCWDT_IS_BIT_VALID(bit) (31UL >= (bit))
+
+
+/** \endcond */
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_mcwdt_functions
+* \{
+*/
+cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_STRUCT_Type *base, cy_stc_mcwdt_config_t const *config);
+ void Cy_MCWDT_DeInit(MCWDT_STRUCT_Type *base);
+__STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
+__STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
+__STATIC_INLINE void Cy_MCWDT_Lock(MCWDT_STRUCT_Type *base);
+__STATIC_INLINE void Cy_MCWDT_Unlock(MCWDT_STRUCT_Type *base);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const *base);
+__STATIC_INLINE void Cy_MCWDT_SetMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdtmode_t mode);
+__STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
+__STATIC_INLINE void Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
+__STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade);
+__STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const *base);
+__STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
+__STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetToggleBit(MCWDT_STRUCT_Type const *base);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
+__STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const *base);
+__STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters);
+__STATIC_INLINE void Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base);
+__STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const *base);
+uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base);
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_Enable
+****************************************************************************//**
+*
+* Enables all specified counters.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counters
+* OR of all counters to enable. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+* \param waitUs
+* The function waits for some delay in microseconds before returning,
+* because the counter begins counting after two lf_clk cycles pass.
+* The recommended value is 93 us.
+* \note
+* Setting this parameter to a zero means No wait. In this case, it is
+* the user's responsibility to check whether the selected counters were enabled
+* immediately after the function call. This can be done by the
+* Cy_MCWDT_GetEnabledStatus() API.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
+{
+ uint32_t enableCounters;
+
+ CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
+
+ /* Extract particular counters for enable */
+ enableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
+ ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
+ ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk : 0UL);
+
+ MCWDT_STRUCT_MCWDT_CTL(base) |= enableCounters;
+
+ Cy_SysLib_DelayUs(waitUs);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_Disable
+****************************************************************************//**
+*
+* Disables all specified counters.
+*
+* \param base
+* The base pointer to a structure describing registers.
+*
+* \param counters
+* OR of all counters to disable. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+* \param waitUs
+* The function waits for some delay in microseconds before returning,
+* because the counter stops counting after two lf_clk cycles pass.
+* The recommended value is 93 us.
+* \note
+* Setting this parameter to a zero means No wait. In this case, it is
+* the user's responsibility to check whether the selected counters were disabled
+* immediately after the function call. This can be done by the
+* Cy_MCWDT_GetEnabledStatus() API.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
+{
+ uint32_t disableCounters;
+
+ CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
+
+ /* Extract particular counters for disable */
+ disableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
+ ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
+ ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk : 0UL);
+
+ MCWDT_STRUCT_MCWDT_CTL(base) &= ~disableCounters;
+
+ Cy_SysLib_DelayUs(waitUs);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetEnabledStatus
+****************************************************************************//**
+*
+* Reports the enabled status of the specified counter.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the MCWDT counter. The valid range is [0-2].
+*
+* \return
+* The status of the MCWDT counter: 0 = disabled, 1 = enabled.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
+{
+ uint32_t status = 0u;
+
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+
+ switch (counter)
+ {
+ case CY_MCWDT_COUNTER0:
+ status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0, MCWDT_STRUCT_MCWDT_CTL(base));
+ break;
+ case CY_MCWDT_COUNTER1:
+ status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1, MCWDT_STRUCT_MCWDT_CTL(base));
+ break;
+ case CY_MCWDT_COUNTER2:
+ status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2, MCWDT_STRUCT_MCWDT_CTL(base));
+ break;
+
+ default:
+ CY_ASSERT(0u != 0u);
+ break;
+ }
+
+ return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_Lock
+****************************************************************************//**
+*
+* Locks out configuration changes to all MCWDT registers.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_Lock(MCWDT_STRUCT_Type *base)
+{
+ uint32_t interruptState;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ MCWDT_STRUCT_MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_SET01);
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_Unlock
+****************************************************************************//**
+*
+* Unlocks the MCWDT configuration registers.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_Unlock(MCWDT_STRUCT_Type *base)
+{
+ uint32_t interruptState;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ MCWDT_STRUCT_MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR0);
+ MCWDT_STRUCT_MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR1);
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetLockStatus
+****************************************************************************//**
+*
+* Reports the locked/unlocked state of the MCWDT.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \return
+* The state of the MCWDT counter: 0 = unlocked, 1 = locked.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const *base)
+{
+ return ((0UL != (MCWDT_STRUCT_MCWDT_LOCK(base) & MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Msk)) ? 1UL : 0UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetMode
+****************************************************************************//**
+*
+* Sets the mode of the specified counter.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-2].
+*
+* \param mode
+* The mode of operation for the counter. See enum typedef cy_en_mcwdtmode_t.
+*
+* \note
+* The mode for Counter 2 can be set only to CY_MCWDT_MODE_NONE or CY_MCWDT_MODE_INT.
+*
+* \note
+* This API must not be called while the counters are running.
+* Prior to calling this API, the counter must be disabled.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdtmode_t mode)
+{
+ uint32_t mask, shift;
+
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+ CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID(mode));
+
+ shift = CY_MCWDT_BYTE_SHIFT * counter;
+ mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK;
+ mask = mask << shift;
+
+ MCWDT_STRUCT_MCWDT_CONFIG(base) = (MCWDT_STRUCT_MCWDT_CONFIG(base) & ~mask) | ((uint32_t) mode << shift);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetMode
+****************************************************************************//**
+*
+* Reports the mode of the specified counter.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-2].
+*
+* \return
+* The current mode of the counter. See enum typedef cy_en_mcwdtmode_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
+{
+ uint32_t mode, mask;
+
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+
+ mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK;
+ mode = (MCWDT_STRUCT_MCWDT_CONFIG(base) >> (CY_MCWDT_BYTE_SHIFT * counter)) & mask;
+
+ return ((cy_en_mcwdtmode_t) mode);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetClearOnMatch
+****************************************************************************//**
+*
+* Sets the Clear on match option for the specified counter.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-1].
+*
+* \note
+* The match values are not supported by Counter 2.
+*
+* \param enable
+* Set 0 to disable; 1 to enable.
+*
+* \note
+* This API must not be called while the counters are running.
+* Prior to calling this API, the counter must be disabled.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable)
+{
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+ CY_ASSERT_L2(CY_MCWDT_IS_ENABLE_VALID(enable));
+
+ if (CY_MCWDT_COUNTER0 == counter)
+ {
+ MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, enable);
+ }
+ else
+ {
+ MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, enable);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetClearOnMatch
+****************************************************************************//**
+*
+* Reports the Clear on match setting for the specified counter.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-1].
+*
+* \return
+* The Clear on match status: 1 = enabled, 0 = disabled.
+*
+* \note
+* The match value is not supported by Counter 2.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
+{
+ uint32_t getClear;
+
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+
+ if (CY_MCWDT_COUNTER0 == counter)
+ {
+ getClear = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, MCWDT_STRUCT_MCWDT_CONFIG(base));
+ }
+ else
+ {
+ getClear = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, MCWDT_STRUCT_MCWDT_CONFIG(base));
+ }
+
+ return (getClear);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetCascade
+****************************************************************************//**
+*
+* Sets all the counter cascade options.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param cascade
+* Sets or clears each of the cascade options.
+*
+* \note
+* This API must not be called when the counters are running.
+* Prior to calling this API, the counter must be disabled.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade)
+{
+ CY_ASSERT_L3(CY_MCWDT_IS_CASCADE_VALID(cascade));
+
+ MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1,
+ (uint32_t) cascade);
+ MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2,
+ ((uint32_t) cascade >> 1u));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetCascade
+****************************************************************************//**
+*
+* Reports all the counter cascade option settings.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \return
+* The current cascade option values.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const *base)
+{
+ uint32_t cascade;
+
+ cascade = (_FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2, MCWDT_STRUCT_MCWDT_CONFIG(base)) << 1u) |
+ _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1, MCWDT_STRUCT_MCWDT_CONFIG(base));
+
+ return ((cy_en_mcwdtcascade_t) cascade);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetMatch
+****************************************************************************//**
+*
+* Sets the match comparison value for the specified counter (0 or 1).
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-1].
+*
+* \param match
+* The value to match against the counter.
+* The valid range is [0-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 0
+* and [1-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 1.
+*
+* \note
+* The match value is not supported by Counter 2.
+*
+* \note
+* Action on match is taken on the next increment after the counter value
+* equal to match value.
+*
+* \param waitUs
+* The function waits for some delay in microseconds before returning,
+* because the match affects after two lf_clk cycles pass. The recommended
+* value is 93 us.
+* \note
+* Setting this parameter to a zero means No wait. This must be taken
+* into account when changing the match values on the running counters.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs)
+{
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+ CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID((CY_MCWDT_COUNTER0 == counter) ?
+ ((MCWDT_STRUCT_MCWDT_CONFIG(base) & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk) > 0U) :
+ ((MCWDT_STRUCT_MCWDT_CONFIG(base) & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk) > 0U),
+ match));
+
+ MCWDT_STRUCT_MCWDT_MATCH(base) = (counter == CY_MCWDT_COUNTER0) ?
+ _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_MATCH(base), MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0,
+ (match & MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk)) :
+ _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_MATCH(base), MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1,
+ (match & MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk));
+
+ Cy_SysLib_DelayUs(waitUs);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetMatch
+****************************************************************************//**
+*
+* Reports the match comparison value for the specified counter (0 or 1).
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-1].
+*
+* \note
+* The match values are not supported by Counter 2.
+*
+* \return
+* A 16-bit match value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
+{
+ uint32_t match;
+
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+
+ match = (counter == CY_MCWDT_COUNTER0) ? _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, MCWDT_STRUCT_MCWDT_MATCH(base)) :
+ _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, MCWDT_STRUCT_MCWDT_MATCH(base));
+
+ return (match);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetToggleBit
+****************************************************************************//**
+*
+* Sets a bit in Counter 2 to monitor for a toggle.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param bit
+* The Counter 2 bit is set to monitor for a toggle. The valid range [0-31].
+*
+* \note
+* This API must not be called when counters are running.
+* Prior to calling this API, the counter must be disabled.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit)
+{
+ CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(bit));
+
+ MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, bit);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetToggleBit
+****************************************************************************//**
+*
+* Reports which bit in Counter 2 is monitored for a toggle.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \return
+* The bit that is monitored (range 0 to 31).
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetToggleBit(MCWDT_STRUCT_Type const *base)
+{
+ return (_FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, MCWDT_STRUCT_MCWDT_CONFIG(base)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetCount
+****************************************************************************//**
+*
+* Reports the current counter value of the specified counter.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-2].
+*
+* \return
+* A live counter value. Counters 0 and 1 are 16-bit counters and Counter 2 is
+* a 32-bit counter.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
+{
+ uint32_t countVal = 0u;
+
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+
+ switch (counter)
+ {
+ case CY_MCWDT_COUNTER0:
+ countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0, MCWDT_STRUCT_MCWDT_CNTLOW(base));
+ break;
+ case CY_MCWDT_COUNTER1:
+ countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1, MCWDT_STRUCT_MCWDT_CNTLOW(base));
+ break;
+ case CY_MCWDT_COUNTER2:
+ countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2, MCWDT_STRUCT_MCWDT_CNTHIGH(base));
+ break;
+
+ default:
+ CY_ASSERT(0u != 0u);
+ break;
+ }
+
+ return (countVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_ResetCounters
+****************************************************************************//**
+*
+* Resets all specified counters.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counters
+* OR of all counters to reset. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+* \param waitUs
+* The function waits for some delay in microseconds before returning, because
+* a reset occurs after one lf_clk cycle passes. The recommended value is 62 us.
+* \note This function resets the counters two times to prevent the case when
+* the Counter 1 is not reset when the counters are cascaded. The delay waitUs
+* must be greater than 100 us when the counters are cascaded.
+* The total delay is greater than 2*waitUs because the function has
+* the delay after the first reset.
+* \note
+* Setting this parameter to a zero means No wait. In this case, it is the
+* user's responsibility to check whether the selected counters were reset
+* immediately after the function call. This can be done by the
+* Cy_MCWDT_GetCount() API.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
+{
+ uint32_t resetCounters;
+
+ CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
+
+ /* Extract particular counters for reset */
+ resetCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk : 0UL) |
+ ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk : 0UL) |
+ ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk : 0UL);
+
+ MCWDT_STRUCT_MCWDT_CTL(base) |= resetCounters;
+
+ Cy_SysLib_DelayUs(waitUs);
+
+ MCWDT_STRUCT_MCWDT_CTL(base) |= resetCounters;
+
+ Cy_SysLib_DelayUs(waitUs);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetInterruptStatus
+****************************************************************************//**
+*
+* Reports the state of all MCWDT interrupts.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \return
+* The OR'd state of the interrupts. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const *base)
+{
+ return (MCWDT_STRUCT_MCWDT_INTR(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_ClearInterrupt
+****************************************************************************//**
+*
+* Clears all specified MCWDT interrupts.
+*
+* All the WDT interrupts must be cleared by the firmware; otherwise
+* interrupts are generated continuously.
+*
+* \param base
+* The base pointer to a structure describes registers.
+*
+* \param counters
+* OR of all interrupt sources to clear. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters)
+{
+ CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
+
+ MCWDT_STRUCT_MCWDT_INTR(base) = counters;
+ (void) MCWDT_STRUCT_MCWDT_INTR(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetInterrupt
+****************************************************************************//**
+*
+* Sets MCWDT interrupt sources in the interrupt request register.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counters
+* OR of all interrupt sources to set. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters)
+{
+ CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
+
+ MCWDT_STRUCT_MCWDT_INTR_SET(base) = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetInterruptMask
+****************************************************************************//**
+*
+* Returns the CWDT interrupt mask register. This register specifies which bits
+* from the MCWDT interrupt request register will trigger an interrupt event.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \return
+* The OR'd state of the interrupt masks. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base)
+{
+ return (MCWDT_STRUCT_MCWDT_INTR_MASK(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetInterruptMask
+****************************************************************************//**
+*
+* Writes MCWDT interrupt mask register. This register configures which bits
+* from MCWDT interrupt request register will trigger an interrupt event.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counters
+* OR of all interrupt masks to set. See \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters)
+{
+ CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
+
+ MCWDT_STRUCT_MCWDT_INTR_MASK(base) = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the MCWDT interrupt masked request register. This register contains
+* the logical AND of corresponding bits from the MCWDT interrupt request and
+* mask registers.
+* In the interrupt service routine, this function identifies which of the
+* enabled MCWDT interrupt sources caused an interrupt event.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \return
+* The current status of enabled MCWDT interrupt sources. See
+* the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and CY_MCWDT_CTR2 macros.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const *base)
+{
+ return (MCWDT_STRUCT_MCWDT_INTR_MASKED(base));
+}
+
+
+/** \} group_mcwdt_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_IP_MXS40SRSS_MCWDT */
+
+#endif /* CY_MCWDT_H */
+
+/** \} group_mcwdt */
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_prot.h b/platform/ext/target/psoc64/Native_Driver/include/cy_prot.h
new file mode 100644
index 0000000000..14bf4072ae
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_prot.h
@@ -0,0 +1,1200 @@
+/***************************************************************************//**
+* \file cy_prot.h
+* \version 1.30.1
+*
+* \brief
+* Provides an API declaration of the Protection Unit driver
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_prot
+* \{
+*
+* The Protection Unit driver provides an API to configure the Memory Protection
+* Units (MPU), Shared Memory Protection Units (SMPU), and Peripheral Protection
+* Units (PPU). These are separate from the ARM Core MPUs and provide additional
+* mechanisms for securing resource accesses. The Protection units address the
+* following concerns in an embedded design:
+* - <b>Security requirements:</b> This includes the prevention of malicious attacks
+* to access secure memory or peripherals.
+* - <b>Safety requirements:</b> This includes detection of accidental (non-malicious)
+* SW errors and random HW errors. It is important to enable failure analysis
+* to investigate the root cause of a safety violation.
+*
+* The functions and other declarations used in this driver are in cy_prot.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions
+* and declarations in the PDL.
+*
+* \section group_prot_protection_type Protection Types
+*
+* Protection units are hardware configuration structures that control bus accesses
+* to the resources that they protect. By combining these individual configuration
+* structures, a system is built to allow strict restrictions on the capabilities
+* of individual bus masters (e.g. CM0+, CM4, Crypt) and their operating modes.
+* This architecture can then be integrated into the overall security system
+* of the end application. To build this system, 3 main protection unit types
+* are available; MPU, SMPU and PPU. When a resource is accessed (memory/register),
+* it must pass the evaluation performed for each category. These access evaluations
+* are prioritized, where MPU has the highest priority, followed by SMPU, followed
+* by PPU. i.e. if an SMPU and a PPU protect the same resource and if access is
+* denied by the SMPU, then the PPU access evaluation is skipped. This can lead to a
+* denial-of-service scenario and the application should pay special attention in
+* taking ownership of the protection unit configurations.
+*
+* \subsection group_prot_memory_protection Memory Protection
+*
+* Memory access control for a bus master is controlled using an MPU. These are
+* most often used to distinguish user and privileged accesses from a single bus
+* master such as task switching in an OS/kernel. For ARM cores (CM0+, CM4), the
+* core MPUs are used to perform this task. For other non-ARM bus masters such
+* as Crypto, MPU structs are available, which can be used in a similar manner
+* as the ARM core MPUs. These MPUs however must be configured by the ARM cores.
+* Other bus masters that do not have an MPU, such as DMA (DW), inherit the access
+* control attributes of the bus master that configured the channel. Also note
+* that unlike other protection units, MPUs do not support protection context
+* evaluation. MPU structs have a descending priority, where larger index struct
+* has higher priority access evaluation over lower index structs. E.g. MPU_STRUCT15
+* has higher priority than MPU_STRUCT14 and its access will be evaluated before
+* MPU_STRUCT14. If both target the same memory, then the higher index (MPU_STRUCT15)
+* will be used, and the lower index (MPU_STRUCT14) will be ignored.
+*
+* \subsection group_prot_shared_memory_protection Shared Memory Protection
+*
+* In order to protect a region of memory from all bus masters, an SMPU is used.
+* This protection effectively allows only those with correct bus master access
+* settings to read/write/execute the memory region. This type of protection
+* is used in general memory such as Flash and SRAM. Peripheral registers are
+* best configured using the peripheral protection units instead. SMPU structs
+* have a descending priority, where larger index struct has higher priority
+* access evaluation over lower index structs. E.g. SMPU_STRUCT15 has higher priority
+* than SMPU_STRUCT14 and its access will be evaluated before SMPU_STRUCT14.
+* If both target the same memory, then the higher index (MPU_STRUCT15) will be
+* used, and the lower index (SMPU_STRUCT14) will be ignored.
+*
+* \subsection group_prot_peripheral_protection Peripheral Protection
+*
+* Peripheral protection is provided by PPUs and allow control of peripheral
+* register accesses by bus masters. Four types of PPUs are available.
+* - <b>Fixed Group (GR) PPUs</b> are used to protect an entire peripheral MMIO group
+* from invalid bus master accesses. The MMIO grouping information and which
+* resource belongs to which group is device specific and can be obtained
+* from the device technical reference manual (TRM). Group PPUs have the highest
+* priority in the PPU category. Therefore their access evaluations take precedence
+* over the other types of PPUs.
+* - <b>Programmable (PROG) PPUs</b> are used to protect any peripheral memory region
+* in a device from invalid bus master accesses. It is the most versatile
+* type of peripheral protection unit. Programmable PPUs have the second highest
+* priority and take precedence over Region PPUs and Slave PPUs. Similar to SMPUs,
+* higher index PROG PPUs have higher priority than lower indexes PROG PPUs.
+* - <b>Fixed Region (RG) PPUs</b> are used to protect an entire peripheral slave
+* instance from invalid bus master accesses. For example, TCPWM0, TCPWM1,
+* SCB0, and SCB1, etc. Region PPUs have the third highest priority and take precedence
+* over Slave PPUs.
+* - <b>Fixed Slave (SL) PPUs</b> are used to protect specified regions of peripheral
+* instances. For example, individual DW channel structs, SMPU structs, and
+* IPC structs, etc. Slave PPUs have the lowest priority in the PPU category and
+* therefore are evaluated last.
+*
+* \section group_prot_protection_context Protection Context
+*
+* Protection context (PC) attribute is present in all bus masters and is evaluated
+* when accessing memory protected by an SMPU or a PPU. There are no limitations
+* to how the PC values are allocated to the bus masters and this makes it
+* possible for multiple bus masters to essentially share protection context
+* values. The exception to this rule is the PC value 0.
+*
+* \subsection group_prot_pc0 PC=0
+*
+* Protection context 0 is a hardware controlled protection context update
+* mechanism that allows only a single entry point for transitioning into PC=0
+* value. This mechanism is only present for the secure CM0+ core and is a
+* fundamental feature in defining a security solution. While all bus masters
+* are configured to PC=0 at device boot, it is up to the security solution
+* to transition these bus masters to PC!=0 values. Once this is done, those
+* bus masters can no longer revert back to PC=0 and can no longer access
+* resources protected at PC=0.
+*
+* In order to enter PC=0, the CM0+ core must assign an interrupt vector or
+* an exception handler address to the CPUSS.CM0_PC0_HANDLER register. This
+* allows the hardware to check whether the executing code address matches the
+* value in this register. If they match, the current PC value is saved and
+* the CM0+ bus master automatically transitions to PC=0. It is then up to
+* the executing code to decide if and when it will revert to a PC!=0 value.
+* At that point, the only way to re-transition to PC=0 is through the defined
+* exception/interrupt handler.
+*
+* \note Devices with CPUSS ver_2 have a hardware-controlled protection context
+* update mechanism that allows only a single-entry point for transitioning
+* into PC=0, 1, 2, and 3. The interrupt vector or the exception handler
+* address can be assigned to the CPUSS.CM0_PC0_HANDLER, CPUSS.CM0_PC1_HANDLER,
+* CPUSS.CM0_PC2_HANDLER or CPUSS.CM0_PC2_HANDLER register. Also, the control
+* register CPUSS.CM0_PC_CTL of the CM0+ protection context must be set:
+* bit 0 - the valid field for CM0_PC0_HANDLER,
+* bit 1 - the valid field for CM0_PC1_HANDLER,
+* bit 2 - the valid field for CM0_PC2_HANDLER,
+* and bit 3 - the valid field for CM0_PC3_HANDLER.
+*
+* The example of using of the single entry point mechanism is shown below.
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ProtectionContext
+*
+* \section group_prot_access_evaluation Access Evaluation
+*
+* Each protection unit is capable of evaluating several access types. These can
+* be used to build a system of logical evaluations for different kinds of
+* bus master modes of operations. These access types can be divided into
+* three broad access categories.
+*
+* - <b>User/Privileged access:</b> The ARM convention of user mode versus privileged
+* mode is applied in the protection units. For ARM cores, switching between
+* user and privileged modes is handled by updating its Control register or
+* by exception entries. Other bus masters such as Crypto have their own
+* user/privileged settings bit in the bus master control register. This is
+* then controlled by the ARM cores. Bus masters that do not have
+* user/privileged access controls, such as DMA, inherit their attributes
+* from the bus master that configured it. The user/privileged distinction
+* is used mainly in the MPUs for single bus master accesses but they can
+* also be used in all other protection units.
+* - <b>Secure/Non-secure access:</b> The secure/non-secure attribute is another
+* identifier to distinguish between two separate modes of operations. Much
+* like the user/privileged access, the secure/non-secure mode flag is present
+* in the bus master control register. The ARM core does not have this
+* attribute in its control register and must use the bus master control
+* register instead. Bus masters that inherit their attributes, such as DMA,
+* inherit the secure/non-secure attribute. The primary use-case for this
+* access evaluation is to define a region to be secure or non-secure using
+* an SMPU or a PPU. A bus master with a secure attribute can access
+* both secure and non-secure regions, whereas a bus master with non-secure
+* attribute can only access non-secure regions.
+* - <b>Protection Context access:</b> Protection Context is an attribute
+* that serves two purposes; To enter the hardware controlled secure PC=0
+* mode of operation from non-secure modes and to provide finer granularity
+* to the bus master access definitions. It is used in SMPU and PPU configuration
+* to control which bus master protection context can access the resources
+* that they protect.
+*
+* \section group_prot_protection_structure Protection Structure
+*
+* Each protection unit is comprised of a master struct and a slave struct pair.
+* The exception to this rule is MPU structs, which only have the slave struct
+* equivalent. The protection units apply their access evaluations in a decreasing
+* index order. For example, if SMPU1 and SMPU2 both protect a specific memory region,
+* the the higher index (SMPU2) will be evaluated first. In a secure system, the
+* higher index protection structs would then provide the high level of security
+* and the lower indexes would provide the lower level of security. Refer to the
+* \ref group_prot_protection_type section for more information.
+*
+* \subsection group_prot_slave_struct Slave Struct
+*
+* The slave struct is used to configure the protection settings for the resource
+* of interest (memory/registers). Depending on the type of protection unit,
+* the available attributes differ. However all Slave protection units have the
+* following general format.
+*
+* \subsubsection group_prot_slave_addr Slave Struct Address Definition
+*
+* - Address: For MPU, SMPU and PROG PPU, the address field is used to define
+* the base memory region to apply the protection. This field has a dependency
+* on the region size, which dictates the alignment of the protection unit. E.g.
+* if the region size is 64KB, the address field is aligned to 64KB. Hence
+* the lowest bits [15:0] are ignored. For instance, if the address is defined
+* at 0x0800FFFF, the protection unit would apply its protection settings from
+* 0x08000000. Thus alignment must be checked before defining the protection
+* address. The address field for other PPUs are not used, as they are bound
+* to their respective peripheral memory locations.
+* - Region Size: For MPU, SMPU and PROG PPU, the region size is used to define
+* the memory block size to apply the protection settings, starting from the
+* defined base address. It is also used to define the 8 sub-regions for the
+* chosen memory block. E.g. If the region size is 64KB, each subregion would
+* be 8KB. This information can then be used to disable the protection
+* settings for select subregions, which gives finer granularity to the
+* memory regions. PPUs do not have region size definitions as they are bound
+* to their respective peripheral memory locations.
+* - Subregions: The memory block defined by the address and region size fields
+* is divided into 8 (0 to 7) equally spaced subregions. The protection settings
+* of the protection unit can be disabled for these subregions. E.g. for a
+* given 64KB of memory block starting from address 0x08000000, disabling
+* subregion 0 would result in the protection settings not affecting the memory
+* located between 0x08000000 to 0x08001FFF. PPUs do not have subregion
+* definitions as they are bound to their respective peripheral memory locations.
+*
+* \subsubsection group_prot_slave_attr Slave Struct Attribute Definition
+*
+* - User Permission: Protection units can control the access restrictions
+* of the read (R), write (W) and execute (X) (subject to their availability
+* depending on the type of protection unit) operations on the memory block
+* when the bus master is operating in user mode. PPU structs do not provide
+* execute attributes.
+* - Privileged Permission: Similar to the user permission, protection units can
+* control the access restrictions of the read (R), write (W) and execute (X)
+* (subject to their availability depending on the type of protection unit)
+* operations on the memory block when the bus master is operating in
+* privileged mode. PPU structs do not provide execute attributes.
+* - Secure/Non-secure: Applies the secure/non-secure protection settings to
+* the defined memory region. Secure protection allows only bus masters that
+* access the memory with secure attribute. Non-secure protection allows
+* bus masters that have either secure or non-secure attributes.
+* - PC match: This attribute allows the protection unit to either apply the
+* 3 access evaluations (user/privileged, secure/non-secure, protection context)
+* or to only provide an address range match. This is useful when multiple
+* protection units protect an overlapping memory region and it's desirable
+* to only have access evaluations applied from only one of these protection
+* units. For example, SMPU1 protects memory A and SMPU2 protects memory B.
+* There exists a region where A and B intersect and this is accessed by a
+* bus master. Both SMPU1 and SMPU2 are configured to operate in "match" mode.
+* In this scenario, the access evaluation will only be applied by the higher
+* index protection unit (i.e. SMPU2) and the access attributes of SMPU1 will
+* be ignored. If the bus master then tries to access a memory region A (that
+* does not intersect with B), the access evaluation from SMPU1 will be used.
+* Note that the PC match functionality is only available in SMPUs.
+* - PC mask: Defines the allowed protection context values that can access the
+* protected memory. The bus master attribute must be operating in one of the
+* protection context values allowed by the protection unit. E.g. If SMPU1 is
+* configured to allow only PC=1 and PC=5, a bus master (such as CM4) must
+* be operating at PC=1 or PC=5 when accessing the protected memory region.
+*
+* \subsection group_prot_master_struct Master Struct
+*
+* The master struct protects its slave struct in the protection unit. This
+* architecture makes possible for the slave configuration to be protected from
+* reconfiguration by an unauthorized bus master. The configuration attributes
+* and the format are similar to that of the slave structs.
+*
+* \subsubsection group_prot_master_addr Master Struct Address Definition
+*
+* - Address: The address definition for master struct is fixed to the slave
+* struct that it protects.
+* - Region Size: The region size is fixed to 256B region.
+* - Subregion: This value is fixed to only enable the first 64B subregions,
+* which applies the protection settings to the entire protection unit.
+*
+* \subsubsection group_prot_master_attr Master Struct Attribute Definition
+*
+* - User Permission: Only the write (W) access attribute is allowed for
+* master structs, which controls whether a bus master operating in user
+* mode has the write access.
+* - Privileged Permission: Only the write (W) access attribute is allowed for
+* master structs, which controls whether a bus master operating in privileged
+* mode has the write access.
+* - Secure/Non-Secure: Same behavior as slave struct.
+* - PC match: Same behavior as slave struct.
+* - PC mask: Same behavior as slave struct.
+*
+* \section group_prot_driver_usage Driver Usage
+*
+* Setting up and using protection units can be summed up in four stages:
+*
+* - Configure the bus master attributes. This defines the capabilities of
+* the bus master when trying to access the protected resources.
+* - Configure the slave struct of a given protection unit. This defines
+* the protection attributes to be applied to the bus master accessing
+* the protected resource and also defines the size and location of the
+* memory block to protect.
+* - Configure the master struct of the protection unit. This defines the
+* attributes to be checked against the bus master that is trying to
+* reconfigure the slave struct.
+* - Set the active PC value of the bus master and place it in the correct
+* mode of operation (user/privileged, secure/non-secure). Then access
+* the protected memory.
+*
+* For example, by configuring the CM0+ bus master configuration to allow
+* only protection contexts 2 and 3, the bus master will be able to
+* set its protection context only to 2 or 3. During runtime, the CM0+ core
+* can set its protection context to 2 by calling Cy_Prot_SetActivePC()
+* and access all regions of protected memory that allow PC=2. A fault will
+* be triggered if a resource is protected with different protection settings.
+*
+* Note that each protection unit is distinguished by its type (e.g.
+* PROT_MPU_MPU_STRUCT_Type). The list of supported protection units can be
+* obtained from the device definition header file. Choose a protection unit
+* of interest, and call its corresponding Cy_Prot_Config<X>Struct() function
+* with its software protection unit configuration structure populated. Then
+* enable the protection unit by calling the Cy_Prot_Enable<X>Struct() function.
+*
+* Note that the bus master ID (en_prot_master_t) is defined in the device
+* config header file.
+*
+* \section group_prot_configuration Configuration Considerations
+*
+* When a resource (memory/register) is accessed, it must pass evaluation of
+* all three protection unit categories in the following order: MPU->SMPU->PPU.
+* The application should ensure that a denial-of-service attack cannot be
+* made on the PPU by the SMPU. For this reason, it is recommended that the
+* application's security policy limit the ability for the non-secure client
+* from configuring the SMPUs.
+*
+* Within each category, the priority hierarchy must be carefully considered
+* to ensure that a higher priority protection unit cannot be configured to
+* override the security configuration of a lower index protection unit.
+* Therefore if a lower index protection unit is configured, relevant higher
+* priority indexes should be configured (or protected from unwanted
+* reconfiguration). E.g. If a PPU_SL is configured, PPU_RG and PPU_GR that
+* overlaps with the protected registers should also be configured. SImilar
+* to SMPUs, it is recommended that the configuration of PPU_PROG be limited.
+* Otherwise they can be used to override the protection settings of PPU_RG
+* and PPU_SL structs.
+*
+* All bus masters are set to PC=0 value at device reset and therefore have full
+* access to all resources. It is up to the security solution to implement
+* what privileges each bus master has. Once transitioned to a PC!=0 value,
+* only the CM0+ core is capable of re-entering the PC=0 via the user-defined
+* exception entry in the CPUSS.CM0_PC0_HANDLER register.
+*
+* - SMPU 15 and 14 are configured and enabled to only allow PC=0 accesses at
+* device boot.
+* - PROG PPU 15, 14, 13 and 12 are configured to only allow PC=0 accesses at
+* device boot.
+* - GR PPU 0 and 2 are configured to only allow PC=0 accesses at device boot.
+*
+* \section group_prot_more_information More Information
+*
+* Refer to Technical Reference Manual (TRM) and the device datasheet.
+*
+* \section group_prot_MISRA MISRA-C Compliance
+* The Prot driver has the following specific deviations:
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to object type and
+* a different pointer to object type.</td>
+* <td>This piece of code is written for DW_V2_Type only and it will be never
+* executed for DW_V1_Type (which is a default build option for DW_Type).</td>
+* </tr>
+* </table>
+*
+* \section group_prot_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.30.1</td>
+* <td>Snippet updated.</td>
+* <td>Old snippet outdated.</td>
+* </tr>
+* <tr>
+* <td>1.30</td>
+* <td>Defect in \ref Cy_Prot_GetPpuProgStruct() function due to faulty defines is fixed.</td>
+* <td>Defect fixing.</td>
+* </tr>
+* <tr>
+* <td rowspan="3">1.20</td>
+* <td>Flattened the organization of the driver source code into the single
+* source directory and the single include directory.</td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Added functions for CPUSS ver_2:
+* - \ref Cy_Prot_ConfigPpuProgMasterAtt()
+* - \ref Cy_Prot_ConfigPpuProgSlaveAddr()
+* - \ref Cy_Prot_ConfigPpuProgSlaveAtt()
+* - \ref Cy_Prot_EnablePpuProgSlaveRegion()
+* - \ref Cy_Prot_DisablePpuProgSlaveRegion()
+* - \ref Cy_Prot_ConfigPpuFixedMasterAtt()
+* - \ref Cy_Prot_ConfigPpuFixedSlaveAtt()
+* </td>
+* <td>Added support for CPUSS ver_2.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td rowspan="2">1.10</td>
+* <td>Added input parameter validation to the API functions.<br>
+* cy_en_prot_pcmask_t, cy_en_prot_subreg_t and cy_en_prot_pc_t
+* types are set to typedef enum</td>
+* <td>Improved debugging capability</td>
+* </tr>
+* <tr>
+* <td>Expanded documentation</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_prot_macros Macros
+* \defgroup group_prot_functions Functions
+* \{
+* \defgroup group_prot_functions_busmaster Bus Master and PC Functions
+* \defgroup group_prot_functions_mpu MPU Functions
+* \defgroup group_prot_functions_smpu SMPU Functions
+* \defgroup group_prot_functions_ppu_prog_v2 PPU Programmable (PROG) v2 Functions
+* \defgroup group_prot_functions_ppu_fixed_v2 PPU Fixed (FIXED) v2 Functions
+* \defgroup group_prot_functions_ppu_prog PPU Programmable (PROG) v1 Functions
+* \defgroup group_prot_functions_ppu_gr PPU Group (GR) v1 Functions
+* \defgroup group_prot_functions_ppu_sl PPU Slave (SL) v1 Functions
+* \defgroup group_prot_functions_ppu_rg PPU Region (RG) v1 Functions
+* \}
+* \defgroup group_prot_data_structures Data Structures
+* \defgroup group_prot_enums Enumerated Types
+*/
+
+#if !defined(CY_CY_PROT_PDL_H)
+#define CY_CY_PROT_PDL_H
+
+#include <stdbool.h>
+#include <stddef.h>
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/** \addtogroup group_prot_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_PROT_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_PROT_DRV_VERSION_MINOR 30
+
+/** Prot driver ID */
+#define CY_PROT_ID (CY_PDL_DRV_ID(0x30U))
+
+/** \} group_prot_macros */
+
+/**
+* \addtogroup group_prot_enums
+* \{
+*/
+
+/**
+* Prot Driver error codes
+*/
+typedef enum
+{
+ CY_PROT_SUCCESS = 0x00U, /**< Returned successful */
+ CY_PROT_BAD_PARAM = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< Bad parameter was passed */
+ CY_PROT_INVALID_STATE = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x02U, /**< The operation is not setup */
+ CY_PROT_FAILURE = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x03U, /**< The resource is locked */
+ CY_PROT_UNAVAILABLE = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x04U /**< The resource is unavailable */
+} cy_en_prot_status_t;
+
+/**
+* User/Privileged permission
+*/
+typedef enum
+{
+ CY_PROT_PERM_DISABLED = 0x00U, /**< Read, Write and Execute disabled */
+ CY_PROT_PERM_R = 0x01U, /**< Read enabled */
+ CY_PROT_PERM_W = 0x02U, /**< Write enabled */
+ CY_PROT_PERM_RW = 0x03U, /**< Read and Write enabled */
+ CY_PROT_PERM_X = 0x04U, /**< Execute enabled */
+ CY_PROT_PERM_RX = 0x05U, /**< Read and Execute enabled */
+ CY_PROT_PERM_WX = 0x06U, /**< Write and Execute enabled */
+ CY_PROT_PERM_RWX = 0x07U /**< Read, Write and Execute enabled */
+}cy_en_prot_perm_t;
+
+/**
+* Bit shift of memory region size setting
+*/
+#define PROT_SIZE_4B_BIT_SHIFT 1U /**< 4 bytes */
+#define PROT_SIZE_8B_BIT_SHIFT 2U /**< 8 bytes */
+#define PROT_SIZE_16B_BIT_SHIFT 3U /**< 16 bytes */
+#define PROT_SIZE_32B_BIT_SHIFT 4U /**< 32 bytes */
+#define PROT_SIZE_64B_BIT_SHIFT 5U /**< 64 bytes */
+#define PROT_SIZE_128B_BIT_SHIFT 6U /**< 128 bytes */
+#define PROT_SIZE_256B_BIT_SHIFT 7U /**< 256 bytes */
+#define PROT_SIZE_512B_BIT_SHIFT 8U /**< 512 bytes */
+
+#define PROT_SIZE_1KB_BIT_SHIFT 9U /**< 1 Kilobyte */
+#define PROT_SIZE_2KB_BIT_SHIFT 10U /**< 2 Kilobytes */
+#define PROT_SIZE_4KB_BIT_SHIFT 11U /**< 4 Kilobytes */
+#define PROT_SIZE_8KB_BIT_SHIFT 12U /**< 8 Kilobytes */
+#define PROT_SIZE_16KB_BIT_SHIFT 13U /**< 16 Kilobytes */
+#define PROT_SIZE_32KB_BIT_SHIFT 14U /**< 32 Kilobytes */
+#define PROT_SIZE_64KB_BIT_SHIFT 15U /**< 64 Kilobytes */
+#define PROT_SIZE_128KB_BIT_SHIFT 16U /**< 128 Kilobytes */
+#define PROT_SIZE_256KB_BIT_SHIFT 17U /**< 256 Kilobytes */
+#define PROT_SIZE_512KB_BIT_SHIFT 18U /**< 512 Kilobytes */
+
+#define PROT_SIZE_1MB_BIT_SHIFT 19U /**< 1 Megabyte */
+#define PROT_SIZE_2MB_BIT_SHIFT 20U /**< 2 Megabytes */
+#define PROT_SIZE_4MB_BIT_SHIFT 21U /**< 4 Megabytes */
+#define PROT_SIZE_8MB_BIT_SHIFT 22U /**< 8 Megabytes */
+#define PROT_SIZE_16MB_BIT_SHIFT 23U /**< 16 Megabytes */
+#define PROT_SIZE_32MB_BIT_SHIFT 24U /**< 32 Megabytes */
+#define PROT_SIZE_64MB_BIT_SHIFT 25U /**< 64 Megabytes */
+#define PROT_SIZE_128MB_BIT_SHIFT 26U /**< 128 Megabytes */
+#define PROT_SIZE_256MB_BIT_SHIFT 27U /**< 256 Megabytes */
+#define PROT_SIZE_512MB_BIT_SHIFT 28U /**< 512 Megabytes */
+
+#define PROT_SIZE_1GB_BIT_SHIFT 29U /**< 1 Gigabyte */
+#define PROT_SIZE_2GB_BIT_SHIFT 30U /**< 2 Gigabytes */
+#define PROT_SIZE_4GB_BIT_SHIFT 31U /**< 4 Gigabytes */
+
+/**
+* Memory region size
+*/
+typedef enum
+{
+ CY_PROT_SIZE_4B = PROT_SIZE_4B_BIT_SHIFT, /**< 4 bytes */
+ CY_PROT_SIZE_8B = PROT_SIZE_8B_BIT_SHIFT, /**< 8 bytes */
+ CY_PROT_SIZE_16B = PROT_SIZE_16B_BIT_SHIFT, /**< 16 bytes */
+ CY_PROT_SIZE_32B = PROT_SIZE_32B_BIT_SHIFT, /**< 32 bytes */
+ CY_PROT_SIZE_64B = PROT_SIZE_64B_BIT_SHIFT, /**< 64 bytes */
+ CY_PROT_SIZE_128B = PROT_SIZE_128B_BIT_SHIFT, /**< 128 bytes */
+
+ CY_PROT_SIZE_256B = PROT_SIZE_256B_BIT_SHIFT, /**< 256 bytes */
+ CY_PROT_SIZE_512B = PROT_SIZE_512B_BIT_SHIFT, /**< 512 bytes */
+ CY_PROT_SIZE_1KB = PROT_SIZE_1KB_BIT_SHIFT, /**< 1 Kilobyte */
+ CY_PROT_SIZE_2KB = PROT_SIZE_2KB_BIT_SHIFT, /**< 2 Kilobytes */
+ CY_PROT_SIZE_4KB = PROT_SIZE_4KB_BIT_SHIFT, /**< 4 Kilobytes */
+ CY_PROT_SIZE_8KB = PROT_SIZE_8KB_BIT_SHIFT, /**< 8 Kilobytes */
+ CY_PROT_SIZE_16KB = PROT_SIZE_16KB_BIT_SHIFT, /**< 16 Kilobytes */
+ CY_PROT_SIZE_32KB = PROT_SIZE_32KB_BIT_SHIFT, /**< 32 Kilobytes */
+ CY_PROT_SIZE_64KB = PROT_SIZE_64KB_BIT_SHIFT, /**< 64 Kilobytes */
+ CY_PROT_SIZE_128KB = PROT_SIZE_128KB_BIT_SHIFT, /**< 128 Kilobytes */
+ CY_PROT_SIZE_256KB = PROT_SIZE_256KB_BIT_SHIFT, /**< 256 Kilobytes */
+ CY_PROT_SIZE_512KB = PROT_SIZE_512KB_BIT_SHIFT, /**< 512 Kilobytes */
+ CY_PROT_SIZE_1MB = PROT_SIZE_1MB_BIT_SHIFT, /**< 1 Megabyte */
+ CY_PROT_SIZE_2MB = PROT_SIZE_2MB_BIT_SHIFT, /**< 2 Megabytes */
+ CY_PROT_SIZE_4MB = PROT_SIZE_4MB_BIT_SHIFT, /**< 4 Megabytes */
+ CY_PROT_SIZE_8MB = PROT_SIZE_8MB_BIT_SHIFT, /**< 8 Megabytes */
+ CY_PROT_SIZE_16MB = PROT_SIZE_16MB_BIT_SHIFT, /**< 16 Megabytes */
+ CY_PROT_SIZE_32MB = PROT_SIZE_32MB_BIT_SHIFT, /**< 32 Megabytes */
+ CY_PROT_SIZE_64MB = PROT_SIZE_64MB_BIT_SHIFT, /**< 64 Megabytes */
+ CY_PROT_SIZE_128MB = PROT_SIZE_128MB_BIT_SHIFT, /**< 128 Megabytes */
+ CY_PROT_SIZE_256MB = PROT_SIZE_256MB_BIT_SHIFT, /**< 256 Megabytes */
+ CY_PROT_SIZE_512MB = PROT_SIZE_512MB_BIT_SHIFT, /**< 512 Megabytes */
+ CY_PROT_SIZE_1GB = PROT_SIZE_1GB_BIT_SHIFT, /**< 1 Gigabyte */
+ CY_PROT_SIZE_2GB = PROT_SIZE_2GB_BIT_SHIFT, /**< 2 Gigabytes */
+ CY_PROT_SIZE_4GB = PROT_SIZE_4GB_BIT_SHIFT /**< 4 Gigabytes */
+}cy_en_prot_size_t;
+
+/**
+* Protection Context (PC)
+*/
+enum cy_en_prot_pc_t
+{
+ CY_PROT_PC1 = 1U, /**< PC = 1 */
+ CY_PROT_PC2 = 2U, /**< PC = 2 */
+ CY_PROT_PC3 = 3U, /**< PC = 3 */
+ CY_PROT_PC4 = 4U, /**< PC = 4 */
+ CY_PROT_PC5 = 5U, /**< PC = 5 */
+ CY_PROT_PC6 = 6U, /**< PC = 6 */
+ CY_PROT_PC7 = 7U, /**< PC = 7 */
+ CY_PROT_PC8 = 8U, /**< PC = 8 */
+ CY_PROT_PC9 = 9U, /**< PC = 9 */
+ CY_PROT_PC10 = 10U, /**< PC = 10 */
+ CY_PROT_PC11 = 11U, /**< PC = 11 */
+ CY_PROT_PC12 = 12U, /**< PC = 12 */
+ CY_PROT_PC13 = 13U, /**< PC = 13 */
+ CY_PROT_PC14 = 14U, /**< PC = 14 */
+ CY_PROT_PC15 = 15U /**< PC = 15 */
+};
+
+/**
+* Subregion disable (0-7)
+*/
+enum cy_en_prot_subreg_t
+{
+ CY_PROT_SUBREGION_DIS0 = 0x01U, /**< Disable subregion 0 */
+ CY_PROT_SUBREGION_DIS1 = 0x02U, /**< Disable subregion 1 */
+ CY_PROT_SUBREGION_DIS2 = 0x04U, /**< Disable subregion 2 */
+ CY_PROT_SUBREGION_DIS3 = 0x08U, /**< Disable subregion 3 */
+ CY_PROT_SUBREGION_DIS4 = 0x10U, /**< Disable subregion 4 */
+ CY_PROT_SUBREGION_DIS5 = 0x20U, /**< Disable subregion 5 */
+ CY_PROT_SUBREGION_DIS6 = 0x40U, /**< Disable subregion 6 */
+ CY_PROT_SUBREGION_DIS7 = 0x80U /**< Disable subregion 7 */
+};
+
+/**
+* Protection context mask (PC_MASK)
+*/
+enum cy_en_prot_pcmask_t
+{
+ CY_PROT_PCMASK1 = 0x0001U, /**< Mask to allow PC = 1 */
+ CY_PROT_PCMASK2 = 0x0002U, /**< Mask to allow PC = 2 */
+ CY_PROT_PCMASK3 = 0x0004U, /**< Mask to allow PC = 3 */
+ CY_PROT_PCMASK4 = 0x0008U, /**< Mask to allow PC = 4 */
+ CY_PROT_PCMASK5 = 0x0010U, /**< Mask to allow PC = 5 */
+ CY_PROT_PCMASK6 = 0x0020U, /**< Mask to allow PC = 6 */
+ CY_PROT_PCMASK7 = 0x0040U, /**< Mask to allow PC = 7 */
+ CY_PROT_PCMASK8 = 0x0080U, /**< Mask to allow PC = 8 */
+ CY_PROT_PCMASK9 = 0x0100U, /**< Mask to allow PC = 9 */
+ CY_PROT_PCMASK10 = 0x0200U, /**< Mask to allow PC = 10 */
+ CY_PROT_PCMASK11 = 0x0400U, /**< Mask to allow PC = 11 */
+ CY_PROT_PCMASK12 = 0x0800U, /**< Mask to allow PC = 12 */
+ CY_PROT_PCMASK13 = 0x1000U, /**< Mask to allow PC = 13 */
+ CY_PROT_PCMASK14 = 0x2000U, /**< Mask to allow PC = 14 */
+ CY_PROT_PCMASK15 = 0x4000U /**< Mask to allow PC = 15 */
+};
+
+/**
+* Request mode to get the SMPU or programmed PU structure
+*/
+typedef enum
+{
+ CY_PROT_REQMODE_HIGHPRIOR = 0U, /**< Request mode to return PU structure with highest priority */
+ CY_PROT_REQMODE_LOWPRIOR = 1U, /**< Request mode to return PU structure with lowest priority */
+ CY_PROT_REQMODE_INDEX = 2U /**< Request mode to return PU structure with specific index */
+}cy_en_prot_req_mode_t;
+
+/** \} group_prot_enums */
+
+
+/***************************************
+* Constants
+***************************************/
+
+/** \cond INTERNAL */
+
+/* Number of SMPU structures with highest priority */
+#define PROT_SMPU_STRUCT_WTH_HIGHEST_PR (15)
+
+/* Number of Programmable PPU structures with lowest priority */
+#define PROT_PPU_PROG_STRUCT_WTH_LOWEST_PR (15)
+
+/* Define to check maximum value of active PC */
+#define PROT_PC_MAX (16U)
+
+/* Define to check maximum mask of PC */
+#define PROT_PC_MASK_MAX (0x7FFFUL)
+
+#if defined (CY_IP_MXPERI_VERSION) && (CY_IP_MXPERI_VERSION == 1U)
+ typedef PERI_MS_PPU_PR_V2_Type PERI_MS_PPU_PR_Type;
+ typedef PERI_MS_PPU_FX_V2_Type PERI_MS_PPU_FX_Type;
+#endif /* defined (CY_IP_MXPERI_VERSION) && (CY_IP_MXPERI_VERSION == 1U) */
+
+#if defined (CY_IP_MXPERI_VERSION) && (CY_IP_MXPERI_VERSION > 1U)
+ typedef PERI_PPU_PR_V1_Type PERI_PPU_PR_Type;
+ typedef PERI_PPU_GR_V1_Type PERI_PPU_GR_Type;
+ typedef PERI_GR_PPU_SL_V1_Type PERI_GR_PPU_SL_Type;
+ typedef PERI_GR_PPU_RG_V1_Type PERI_GR_PPU_RG_Type;
+#endif /* defined (CY_IP_MXPERI_VERSION) && (CY_IP_MXPERI_VERSION > 1U) */
+
+
+/* General Masks and shifts */
+#define CY_PROT_MSX_CTL_SHIFT (0x02UL) /**< Shift for MSx_CTL register */
+#define CY_PROT_STRUCT_ENABLE (0x01UL) /**< Enable protection unit struct */
+#define CY_PROT_STRUCT_DISABLE (0x00UL) /**< Disable protection unit struct */
+#define CY_PROT_ADDR_SHIFT (8UL) /**< Address shift for MPU, SMPU and PROG PPU structs */
+#define CY_PROT_PCMASK_CHECK (0x01UL) /**< Shift and mask for pcMask check */
+
+/* Permission masks and shifts */
+#define CY_PROT_ATT_PERMISSION_MASK (0x07UL) /**< Protection Unit attribute permission mask */
+#define CY_PROT_ATT_PRIV_PERMISSION_SHIFT (0x03UL) /**< Protection Unit privileged attribute permission shift */
+
+#define CY_PROT_ATT_PERI_USER_PERM_Pos (0UL) /**< PERI v2 privileged attribute permission shift */
+#define CY_PROT_ATT_PERI_USER_PERM_Msk (0x03UL) /**< PERI v2 attribute permission mask */
+#define CY_PROT_ATT_PERI_PRIV_PERM_Pos (2UL) /**< PERI v2 privileged attribute permission shift */
+#define CY_PROT_ATT_PERI_PRIV_PERM_Msk ((uint32_t)(0x03UL << CY_PROT_ATT_PERI_PRIV_PERM_Pos)) /**< PERI v2 attribute permission mask */
+
+#define CY_PROT_ATT_REGS_MAX (4U) /**< Maximum number of ATT registers */
+#define CY_PROT_ATT_PC_MAX (4U) /**< Maximum PC value per ATT reg */
+
+/* BWC macros */
+#define CY_PROT_ATT_PERI_PERM_MASK (0x03UL)
+#define CY_PROT_ATT_PERI_PRIV_PERM_SHIFT (0x02UL)
+/* End of BWC macros */
+
+#define CY_PROT_SMPU_PC_LIMIT_MASK ((uint32_t) 0xFFFFFFFFUL << (CY_PROT_PC_MAX - 1UL))
+#define CY_PROT_PPU_PROG_PC_LIMIT_MASK ((uint32_t) 0xFFFFFFFFUL << (CY_PROT_PC_MAX - 1UL))
+#define CY_PROT_PPU_FIXED_PC_LIMIT_MASK ((uint32_t) 0xFFFFFFFFUL << (CY_PROT_PC_MAX - 1UL))
+
+#define CY_PROT_SMPU_ATT0_MASK ((uint32_t)~(PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk))
+#define CY_PROT_SMPU_ATT1_MASK ((uint32_t)~(PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk \
+ | PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk \
+ | PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Msk \
+ | PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Msk \
+ ))
+
+#define CY_PROT_PPU_PROG_ATT0_MASK ((uint32_t)~(PERI_PPU_PR_ATT0_UX_Msk \
+ | PERI_PPU_PR_ATT0_PX_Msk \
+ | PERI_PPU_PR_ATT0_PC_MASK_0_Msk \
+ ))
+#define CY_PROT_PPU_PROG_ATT1_MASK ((uint32_t)~(PERI_PPU_PR_ATT1_UX_Msk \
+ | PERI_PPU_PR_ATT1_PX_Msk \
+ | PERI_PPU_PR_ATT1_PC_MASK_0_Msk \
+ | PERI_PPU_PR_ATT1_REGION_SIZE_Msk \
+ ))
+#define CY_PROT_PPU_GR_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT0_UX_Msk \
+ | PERI_PPU_GR_ATT0_PX_Msk \
+ | PERI_PPU_GR_ATT0_PC_MASK_0_Msk \
+ | PERI_PPU_GR_ATT0_REGION_SIZE_Msk \
+ ))
+#define CY_PROT_PPU_GR_ATT1_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UX_Msk \
+ | PERI_PPU_GR_ATT1_PX_Msk \
+ | PERI_PPU_GR_ATT1_PC_MASK_0_Msk \
+ | PERI_PPU_GR_ATT1_REGION_SIZE_Msk \
+ ))
+#define CY_PROT_PPU_SL_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT0_UX_Msk \
+ | PERI_PPU_GR_ATT0_PX_Msk \
+ | PERI_PPU_GR_ATT0_PC_MASK_0_Msk \
+ | PERI_PPU_GR_ATT0_REGION_SIZE_Msk \
+ ))
+#define CY_PROT_PPU_SL_ATT1_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UX_Msk \
+ | PERI_PPU_GR_ATT1_PX_Msk \
+ | PERI_PPU_GR_ATT1_PC_MASK_0_Msk \
+ | PERI_PPU_GR_ATT1_REGION_SIZE_Msk \
+ ))
+#define CY_PROT_PPU_RG_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT0_UX_Msk \
+ | PERI_PPU_GR_ATT0_PX_Msk \
+ | PERI_PPU_GR_ATT0_PC_MASK_0_Msk \
+ | PERI_PPU_GR_ATT0_REGION_SIZE_Msk \
+ ))
+#define CY_PROT_PPU_RG_ATT1_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UX_Msk \
+ | PERI_PPU_GR_ATT1_PX_Msk \
+ | PERI_PPU_GR_ATT1_PC_MASK_0_Msk \
+ | PERI_PPU_GR_ATT1_REGION_SIZE_Msk \
+ ))
+
+/* Parameter check macros */
+#define CY_PROT_IS_BUS_MASTER_VALID(busMaster) ((CY_PROT_BUS_MASTER_MASK & (1UL << (uint32_t)(busMaster))) != 0UL)
+
+#define CY_PROT_IS_MPU_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
+ ((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_W) || \
+ ((permission) == CY_PROT_PERM_RW) || \
+ ((permission) == CY_PROT_PERM_X) || \
+ ((permission) == CY_PROT_PERM_RX) || \
+ ((permission) == CY_PROT_PERM_WX) || \
+ ((permission) == CY_PROT_PERM_RWX))
+
+#define CY_PROT_IS_SMPU_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_RW))
+
+#define CY_PROT_IS_SMPU_SL_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
+ ((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_W) || \
+ ((permission) == CY_PROT_PERM_RW) || \
+ ((permission) == CY_PROT_PERM_X) || \
+ ((permission) == CY_PROT_PERM_RX) || \
+ ((permission) == CY_PROT_PERM_WX) || \
+ ((permission) == CY_PROT_PERM_RWX))
+
+#define CY_PROT_IS_PROG_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_RW))
+
+#define CY_PROT_IS_PROG_SL_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
+ ((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_W) || \
+ ((permission) == CY_PROT_PERM_RW))
+
+#define CY_PROT_IS_FIXED_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
+ ((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_W) || \
+ ((permission) == CY_PROT_PERM_RW))
+
+#define CY_PROT_IS_FIXED_MS_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_RW))
+
+
+#define CY_PROT_IS_FIXED_SL_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
+ ((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_W) || \
+ ((permission) == CY_PROT_PERM_RW))
+
+#define CY_PROT_IS_REGION_SIZE_VALID(regionSize) (((regionSize) == CY_PROT_SIZE_256B) || \
+ ((regionSize) == CY_PROT_SIZE_512B) || \
+ ((regionSize) == CY_PROT_SIZE_1KB) || \
+ ((regionSize) == CY_PROT_SIZE_2KB) || \
+ ((regionSize) == CY_PROT_SIZE_4KB) || \
+ ((regionSize) == CY_PROT_SIZE_8KB) || \
+ ((regionSize) == CY_PROT_SIZE_16KB) || \
+ ((regionSize) == CY_PROT_SIZE_32KB) || \
+ ((regionSize) == CY_PROT_SIZE_64KB) || \
+ ((regionSize) == CY_PROT_SIZE_128KB) || \
+ ((regionSize) == CY_PROT_SIZE_256KB) || \
+ ((regionSize) == CY_PROT_SIZE_512KB) || \
+ ((regionSize) == CY_PROT_SIZE_1MB) || \
+ ((regionSize) == CY_PROT_SIZE_2MB) || \
+ ((regionSize) == CY_PROT_SIZE_4MB) || \
+ ((regionSize) == CY_PROT_SIZE_8MB) || \
+ ((regionSize) == CY_PROT_SIZE_16MB) || \
+ ((regionSize) == CY_PROT_SIZE_32MB) || \
+ ((regionSize) == CY_PROT_SIZE_64MB) || \
+ ((regionSize) == CY_PROT_SIZE_128MB) || \
+ ((regionSize) == CY_PROT_SIZE_256MB) || \
+ ((regionSize) == CY_PROT_SIZE_512MB) || \
+ ((regionSize) == CY_PROT_SIZE_1GB) || \
+ ((regionSize) == CY_PROT_SIZE_2GB) || \
+ ((regionSize) == CY_PROT_SIZE_4GB))
+
+#define CY_PROT_IS_PPU_V2_SIZE_VALID(regionSize) (((regionSize) == CY_PROT_SIZE_4B) || \
+ ((regionSize) == CY_PROT_SIZE_8B) || \
+ ((regionSize) == CY_PROT_SIZE_16B) || \
+ ((regionSize) == CY_PROT_SIZE_32B) || \
+ ((regionSize) == CY_PROT_SIZE_64B) || \
+ ((regionSize) == CY_PROT_SIZE_128B) || \
+ ((regionSize) == CY_PROT_SIZE_256B) || \
+ ((regionSize) == CY_PROT_SIZE_512B) || \
+ ((regionSize) == CY_PROT_SIZE_1KB) || \
+ ((regionSize) == CY_PROT_SIZE_2KB) || \
+ ((regionSize) == CY_PROT_SIZE_4KB) || \
+ ((regionSize) == CY_PROT_SIZE_8KB) || \
+ ((regionSize) == CY_PROT_SIZE_16KB) || \
+ ((regionSize) == CY_PROT_SIZE_32KB) || \
+ ((regionSize) == CY_PROT_SIZE_64KB) || \
+ ((regionSize) == CY_PROT_SIZE_128KB) || \
+ ((regionSize) == CY_PROT_SIZE_256KB) || \
+ ((regionSize) == CY_PROT_SIZE_512KB) || \
+ ((regionSize) == CY_PROT_SIZE_1MB) || \
+ ((regionSize) == CY_PROT_SIZE_2MB) || \
+ ((regionSize) == CY_PROT_SIZE_4MB) || \
+ ((regionSize) == CY_PROT_SIZE_8MB) || \
+ ((regionSize) == CY_PROT_SIZE_16MB) || \
+ ((regionSize) == CY_PROT_SIZE_32MB) || \
+ ((regionSize) == CY_PROT_SIZE_64MB) || \
+ ((regionSize) == CY_PROT_SIZE_128MB) || \
+ ((regionSize) == CY_PROT_SIZE_256MB) || \
+ ((regionSize) == CY_PROT_SIZE_512MB) || \
+ ((regionSize) == CY_PROT_SIZE_1GB) || \
+ ((regionSize) == CY_PROT_SIZE_2GB) || \
+ ((regionSize) == CY_PROT_SIZE_4GB))
+
+#define CY_PROT_IS_SMPU_REQ_MODE_VALID(reqMode) (((reqMode) == CY_PROT_REQMODE_HIGHPRIOR) || \
+ ((reqMode) == CY_PROT_REQMODE_LOWPRIOR) || \
+ ((reqMode) == CY_PROT_REQMODE_INDEX))
+
+#define CY_PROT_IS_PPU_PROG_REQ_MODE_VALID(reqMode) (((reqMode) == CY_PROT_REQMODE_HIGHPRIOR) || \
+ ((reqMode) == CY_PROT_REQMODE_LOWPRIOR) || \
+ ((reqMode) == CY_PROT_REQMODE_INDEX))
+
+#define CY_PROT_IS_SMPU_IDX_VALID(smpuIndex) ((smpuIndex) <= (uint32_t)PROT_SMPU_STRUCT_WTH_HIGHEST_PR)
+
+#define CY_PROT_IS_PPU_PROG_IDX_VALID(ppuIndex) ((ppuIndex) <= (uint32_t)PROT_PPU_PROG_STRUCT_WTH_LOWEST_PR)
+
+#define CY_PROT_IS_PC_VALID(pc) ((pc) < PROT_PC_MAX)
+#define CY_PROT_IS_PC_MASK_VALID(pcMask) (((pcMask) & ((uint32_t)~PROT_PC_MASK_MAX)) == 0UL)
+
+/** \endcond */
+
+
+/***************************************
+* Configuration Structures
+***************************************/
+
+/**
+* \addtogroup group_prot_data_structures
+* \{
+*/
+
+/** Configuration structure for MPU Struct initialization */
+typedef struct
+{
+ uint32_t* address; /**< Base address of the memory region */
+ cy_en_prot_size_t regionSize; /**< Size of the memory region */
+ uint8_t subregions; /**< Mask of the 8 subregions to disable */
+ cy_en_prot_perm_t userPermission; /**< User permissions for the region */
+ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
+ bool secure; /**< Non Secure = 0, Secure = 1 */
+} cy_stc_mpu_cfg_t;
+
+/** Configuration structure for SMPU struct initialization */
+typedef struct
+{
+ uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */
+ cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */
+ uint8_t subregions; /**< Mask of the 8 subregions to disable (Only applicable to slave) */
+ cy_en_prot_perm_t userPermission; /**< User permissions for the region */
+ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
+ bool secure; /**< Non Secure = 0, Secure = 1 */
+ bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
+ uint16_t pcMask; /**< Mask of allowed protection context(s) */
+} cy_stc_smpu_cfg_t;
+
+/** Configuration structure for Programmable (PROG) PPU (PPU_PR) struct initialization */
+typedef struct
+{
+ uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */
+ cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */
+ uint8_t subregions; /**< Mask of the 8 subregions to disable (Only applicable to slave) */
+ cy_en_prot_perm_t userPermission; /**< User permissions for the region */
+ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
+ bool secure; /**< Non Secure = 0, Secure = 1 */
+ bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
+ uint16_t pcMask; /**< Mask of allowed protection context(s) */
+} cy_stc_ppu_prog_cfg_t;
+
+/** Configuration structure for Fixed Group (GR) PPU (PPU_GR) struct initialization */
+typedef struct
+{
+ cy_en_prot_perm_t userPermission; /**< User permissions for the region */
+ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
+ bool secure; /**< Non Secure = 0, Secure = 1 */
+ bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
+ uint16_t pcMask; /**< Mask of allowed protection context(s) */
+} cy_stc_ppu_gr_cfg_t;
+
+/** Configuration structure for Fixed Slave (SL) PPU (PPU_SL) struct initialization */
+typedef struct
+{
+ cy_en_prot_perm_t userPermission; /**< User permissions for the region */
+ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
+ bool secure; /**< Non Secure = 0, Secure = 1 */
+ bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
+ uint16_t pcMask; /**< Mask of allowed protection context(s) */
+} cy_stc_ppu_sl_cfg_t;
+
+/** Configuration structure for Fixed Region (RG) PPU (PPU_RG) struct initialization */
+typedef struct
+{
+ cy_en_prot_perm_t userPermission; /**< User permissions for the region */
+ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
+ bool secure; /**< Non Secure = 0, Secure = 1 */
+ bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
+ uint16_t pcMask; /**< Mask of allowed protection context(s) */
+} cy_stc_ppu_rg_cfg_t;
+
+/** \} group_prot_data_structures */
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_prot_functions
+* \{
+*/
+
+/**
+* \addtogroup group_prot_functions_busmaster
+* \{
+*/
+cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool privileged, bool secure, uint32_t pcMask);
+cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc);
+uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster);
+/** \} group_prot_functions_busmaster */
+
+/**
+* \addtogroup group_prot_functions_mpu
+* \{
+*/
+cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, const cy_stc_mpu_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base);
+cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base);
+/** \} group_prot_functions_mpu */
+
+/**
+* \addtogroup group_prot_functions_smpu
+* \{
+*/
+__STATIC_INLINE cy_en_prot_status_t Cy_Prot_DisableSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
+cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, cy_en_prot_req_mode_t reqMode, uint32_t smpuIndex);
+
+cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
+cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
+cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
+cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
+
+/** \} group_prot_functions_smpu */
+
+
+
+/**
+* \addtogroup group_prot_functions_ppu_prog_v2
+* \{
+*/
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterAtt(PERI_MS_PPU_PR_Type* base, uint16_t pcMask, cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure);
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAddr(PERI_MS_PPU_PR_Type* base, uint32_t address, cy_en_prot_size_t regionSize);
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAtt(PERI_MS_PPU_PR_Type* base, uint16_t pcMask, cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure);
+cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base);
+
+/** \} group_prot_functions_ppu_prog_v2 */
+
+/**
+* \addtogroup group_prot_functions_ppu_fixed_v2
+* \{
+*/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedMasterAtt(PERI_MS_PPU_FX_Type* base, uint16_t pcMask, cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure);
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlaveAtt(PERI_MS_PPU_FX_Type* base, uint16_t pcMask, cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure);
+/** \} group_prot_functions_ppu_fixed_v2 */
+
+
+/**
+* \addtogroup group_prot_functions_ppu_prog
+* \{
+*/
+__STATIC_INLINE cy_en_prot_status_t Cy_Prot_DisablePpuProgStruct(PERI_PPU_PR_Type* base);
+
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base);
+cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base);
+
+cy_en_prot_status_t Cy_Prot_GetPpuProgStruct(PERI_PPU_PR_Type** base, cy_en_prot_req_mode_t reqMode, uint32_t ppuProgIndex);
+
+/** \} group_prot_functions_ppu_prog */
+
+/**
+* \addtogroup group_prot_functions_ppu_gr
+* \{
+*/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base);
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base);
+/** \} group_prot_functions_ppu_gr */
+
+/**
+* \addtogroup group_prot_functions_ppu_sl
+* \{
+*/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base);
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base);
+/** \} group_prot_functions_ppu_sl */
+
+/**
+* \addtogroup group_prot_functions_ppu_rg
+* \{
+*/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base);
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base);
+/** \} group_prot_functions_ppu_rg */
+
+/** \} group_prot_functions */
+
+
+
+/**
+* \addtogroup group_prot_functions
+* \{
+*/
+
+/**
+* \addtogroup group_prot_functions_smpu
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisableSmpuStruct
+****************************************************************************//**
+*
+* This function disables both the master and slave parts of a protection unit.
+*
+* \param base
+* The base address for the SMPU structure to be disabled.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ---------------------| -----------
+* CY_PROT_SUCCESS | The Master and Slave SMPU struct was disabled
+* CY_PROT_FAILURE | The Master and/or slave SMPU struct was not disabled
+* CY_PROT_INVALID_STATE | Function was called on the unsupported PERI IP version
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisableSmpuStruct
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_prot_status_t Cy_Prot_DisableSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
+{
+ cy_en_prot_status_t status = Cy_Prot_DisableSmpuMasterStruct(base);
+
+ if (CY_PROT_SUCCESS == status)
+ {
+ status = Cy_Prot_DisableSmpuSlaveStruct(base);
+ }
+
+ return status;
+}
+/** \} group_prot_functions_smpu */
+
+
+/**
+* \addtogroup group_prot_functions_ppu_prog
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuProgStruct
+****************************************************************************//**
+*
+* This function disables both the master and slave parts of a protection unit.
+*
+* \note
+* This functions has an effect only on devices with PERI IP version 1. Refer
+* to the device datasheet for information about PERI HW IP version.
+*
+* \param base
+* The base address for the Programmable PU structure to be disabled.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ---------------------| -----------
+* CY_PROT_SUCCESS | The Master and Slave Programmable PU struct was disabled
+* CY_PROT_FAILURE | The Master and/or slave Programmable PU struct was not disabled
+* CY_PROT_INVALID_STATE | Function was called on the unsupported PERI IP version
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuProgStruct
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_prot_status_t Cy_Prot_DisablePpuProgStruct(PERI_PPU_PR_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ if (CY_PERI_V1)
+ {
+ status = Cy_Prot_DisablePpuProgMasterStruct(base);
+
+ if (CY_PROT_SUCCESS == status)
+ {
+ status = Cy_Prot_DisablePpuProgSlaveStruct(base);
+ }
+ }
+
+ return status;
+}
+/** \} group_prot_functions_ppu_prog */
+/** \} group_prot_functions */
+/** \} group_prot */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_PROT_H */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_prot.h.rej b/platform/ext/target/psoc64/Native_Driver/include/cy_prot.h.rej
new file mode 100644
index 0000000000..9bd2fdcea8
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_prot.h.rej
@@ -0,0 +1,116 @@
+--- a/platform/ext/target/psoc6/Native_Driver/include/cy_prot.h
++++ b/platform/ext/target/psoc6/Native_Driver/include/cy_prot.h
+@@ -513,43 +513,81 @@ typedef enum
+ CY_PROT_PERM_RWX = 0x07U /**< Read, Write and Execute enabled */
+ }cy_en_prot_perm_t;
+
++/**
++* Bit shift of memory region size setting
++*/
++#define PROT_SIZE_4B_BIT_SHIFT 1U /**< 4 bytes */
++#define PROT_SIZE_8B_BIT_SHIFT 2U /**< 8 bytes */
++#define PROT_SIZE_16B_BIT_SHIFT 3U /**< 16 bytes */
++#define PROT_SIZE_32B_BIT_SHIFT 4U /**< 32 bytes */
++#define PROT_SIZE_64B_BIT_SHIFT 5U /**< 64 bytes */
++#define PROT_SIZE_128B_BIT_SHIFT 6U /**< 128 bytes */
++#define PROT_SIZE_256B_BIT_SHIFT 7U /**< 256 bytes */
++#define PROT_SIZE_512B_BIT_SHIFT 8U /**< 512 bytes */
++
++#define PROT_SIZE_1KB_BIT_SHIFT 9U /**< 1 Kilobyte */
++#define PROT_SIZE_2KB_BIT_SHIFT 10U /**< 2 Kilobytes */
++#define PROT_SIZE_4KB_BIT_SHIFT 11U /**< 4 Kilobytes */
++#define PROT_SIZE_8KB_BIT_SHIFT 12U /**< 8 Kilobytes */
++#define PROT_SIZE_16KB_BIT_SHIFT 13U /**< 16 Kilobytes */
++#define PROT_SIZE_32KB_BIT_SHIFT 14U /**< 32 Kilobytes */
++#define PROT_SIZE_64KB_BIT_SHIFT 15U /**< 64 Kilobytes */
++#define PROT_SIZE_128KB_BIT_SHIFT 16U /**< 128 Kilobytes */
++#define PROT_SIZE_256KB_BIT_SHIFT 17U /**< 256 Kilobytes */
++#define PROT_SIZE_512KB_BIT_SHIFT 18U /**< 512 Kilobytes */
++
++#define PROT_SIZE_1MB_BIT_SHIFT 19U /**< 1 Megabyte */
++#define PROT_SIZE_2MB_BIT_SHIFT 20U /**< 2 Megabytes */
++#define PROT_SIZE_4MB_BIT_SHIFT 21U /**< 4 Megabytes */
++#define PROT_SIZE_8MB_BIT_SHIFT 22U /**< 8 Megabytes */
++#define PROT_SIZE_16MB_BIT_SHIFT 23U /**< 16 Megabytes */
++#define PROT_SIZE_32MB_BIT_SHIFT 24U /**< 32 Megabytes */
++#define PROT_SIZE_64MB_BIT_SHIFT 25U /**< 64 Megabytes */
++#define PROT_SIZE_128MB_BIT_SHIFT 26U /**< 128 Megabytes */
++#define PROT_SIZE_256MB_BIT_SHIFT 27U /**< 256 Megabytes */
++#define PROT_SIZE_512MB_BIT_SHIFT 28U /**< 512 Megabytes */
++
++#define PROT_SIZE_1GB_BIT_SHIFT 29U /**< 1 Gigabyte */
++#define PROT_SIZE_2GB_BIT_SHIFT 30U /**< 2 Gigabytes */
++#define PROT_SIZE_4GB_BIT_SHIFT 31U /**< 4 Gigabytes */
++
+ /**
+ * Memory region size
+ */
+ typedef enum
+ {
+- CY_PROT_SIZE_4B = 1U, /**< 4 bytes */
+- CY_PROT_SIZE_8B = 2U, /**< 8 bytes */
+- CY_PROT_SIZE_16B = 3U, /**< 16 bytes */
+- CY_PROT_SIZE_32B = 4U, /**< 32 bytes */
+- CY_PROT_SIZE_64B = 5U, /**< 64 bytes */
+- CY_PROT_SIZE_128B = 6U, /**< 128 bytes */
+-
+- CY_PROT_SIZE_256B = 7U, /**< 256 bytes */
+- CY_PROT_SIZE_512B = 8U, /**< 512 bytes */
+- CY_PROT_SIZE_1KB = 9U, /**< 1 Kilobyte */
+- CY_PROT_SIZE_2KB = 10U, /**< 2 Kilobytes */
+- CY_PROT_SIZE_4KB = 11U, /**< 4 Kilobytes */
+- CY_PROT_SIZE_8KB = 12U, /**< 8 Kilobytes */
+- CY_PROT_SIZE_16KB = 13U, /**< 16 Kilobytes */
+- CY_PROT_SIZE_32KB = 14U, /**< 32 Kilobytes */
+- CY_PROT_SIZE_64KB = 15U, /**< 64 Kilobytes */
+- CY_PROT_SIZE_128KB = 16U, /**< 128 Kilobytes */
+- CY_PROT_SIZE_256KB = 17U, /**< 256 Kilobytes */
+- CY_PROT_SIZE_512KB = 18U, /**< 512 Kilobytes */
+- CY_PROT_SIZE_1MB = 19U, /**< 1 Megabyte */
+- CY_PROT_SIZE_2MB = 20U, /**< 2 Megabytes */
+- CY_PROT_SIZE_4MB = 21U, /**< 4 Megabytes */
+- CY_PROT_SIZE_8MB = 22U, /**< 8 Megabytes */
+- CY_PROT_SIZE_16MB = 23U, /**< 16 Megabytes */
+- CY_PROT_SIZE_32MB = 24U, /**< 32 Megabytes */
+- CY_PROT_SIZE_64MB = 25U, /**< 64 Megabytes */
+- CY_PROT_SIZE_128MB = 26U, /**< 128 Megabytes */
+- CY_PROT_SIZE_256MB = 27U, /**< 256 Megabytes */
+- CY_PROT_SIZE_512MB = 28U, /**< 512 Megabytes */
+- CY_PROT_SIZE_1GB = 29U, /**< 1 Gigabyte */
+- CY_PROT_SIZE_2GB = 30U, /**< 2 Gigabytes */
+- CY_PROT_SIZE_4GB = 31U /**< 4 Gigabytes */
++ CY_PROT_SIZE_4B = PROT_SIZE_4B_BIT_SHIFT, /**< 4 bytes */
++ CY_PROT_SIZE_8B = PROT_SIZE_8B_BIT_SHIFT, /**< 8 bytes */
++ CY_PROT_SIZE_16B = PROT_SIZE_16B_BIT_SHIFT, /**< 16 bytes */
++ CY_PROT_SIZE_32B = PROT_SIZE_32B_BIT_SHIFT, /**< 32 bytes */
++ CY_PROT_SIZE_64B = PROT_SIZE_64B_BIT_SHIFT, /**< 64 bytes */
++ CY_PROT_SIZE_128B = PROT_SIZE_128B_BIT_SHIFT, /**< 128 bytes */
++
++ CY_PROT_SIZE_256B = PROT_SIZE_256B_BIT_SHIFT, /**< 256 bytes */
++ CY_PROT_SIZE_512B = PROT_SIZE_512B_BIT_SHIFT, /**< 512 bytes */
++ CY_PROT_SIZE_1KB = PROT_SIZE_1KB_BIT_SHIFT, /**< 1 Kilobyte */
++ CY_PROT_SIZE_2KB = PROT_SIZE_2KB_BIT_SHIFT, /**< 2 Kilobytes */
++ CY_PROT_SIZE_4KB = PROT_SIZE_4KB_BIT_SHIFT, /**< 4 Kilobytes */
++ CY_PROT_SIZE_8KB = PROT_SIZE_8KB_BIT_SHIFT, /**< 8 Kilobytes */
++ CY_PROT_SIZE_16KB = PROT_SIZE_16KB_BIT_SHIFT, /**< 16 Kilobytes */
++ CY_PROT_SIZE_32KB = PROT_SIZE_32KB_BIT_SHIFT, /**< 32 Kilobytes */
++ CY_PROT_SIZE_64KB = PROT_SIZE_64KB_BIT_SHIFT, /**< 64 Kilobytes */
++ CY_PROT_SIZE_128KB = PROT_SIZE_128KB_BIT_SHIFT, /**< 128 Kilobytes */
++ CY_PROT_SIZE_256KB = PROT_SIZE_256KB_BIT_SHIFT, /**< 256 Kilobytes */
++ CY_PROT_SIZE_512KB = PROT_SIZE_512KB_BIT_SHIFT, /**< 512 Kilobytes */
++ CY_PROT_SIZE_1MB = PROT_SIZE_1MB_BIT_SHIFT, /**< 1 Megabyte */
++ CY_PROT_SIZE_2MB = PROT_SIZE_2MB_BIT_SHIFT, /**< 2 Megabytes */
++ CY_PROT_SIZE_4MB = PROT_SIZE_4MB_BIT_SHIFT, /**< 4 Megabytes */
++ CY_PROT_SIZE_8MB = PROT_SIZE_8MB_BIT_SHIFT, /**< 8 Megabytes */
++ CY_PROT_SIZE_16MB = PROT_SIZE_16MB_BIT_SHIFT, /**< 16 Megabytes */
++ CY_PROT_SIZE_32MB = PROT_SIZE_32MB_BIT_SHIFT, /**< 32 Megabytes */
++ CY_PROT_SIZE_64MB = PROT_SIZE_64MB_BIT_SHIFT, /**< 64 Megabytes */
++ CY_PROT_SIZE_128MB = PROT_SIZE_128MB_BIT_SHIFT, /**< 128 Megabytes */
++ CY_PROT_SIZE_256MB = PROT_SIZE_256MB_BIT_SHIFT, /**< 256 Megabytes */
++ CY_PROT_SIZE_512MB = PROT_SIZE_512MB_BIT_SHIFT, /**< 512 Megabytes */
++ CY_PROT_SIZE_1GB = PROT_SIZE_1GB_BIT_SHIFT, /**< 1 Gigabyte */
++ CY_PROT_SIZE_2GB = PROT_SIZE_2GB_BIT_SHIFT, /**< 2 Gigabytes */
++ CY_PROT_SIZE_4GB = PROT_SIZE_4GB_BIT_SHIFT /**< 4 Gigabytes */
+ }cy_en_prot_size_t;
+
+ /**
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_rtc.h b/platform/ext/target/psoc64/Native_Driver/include/cy_rtc.h
new file mode 100644
index 0000000000..36cac15f57
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_rtc.h
@@ -0,0 +1,1329 @@
+/***************************************************************************//**
+* \file cy_rtc.h
+* \version 2.20.1
+*
+* This file provides constants and parameter values for the APIs for the
+* Real-Time Clock (RTC).
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+* \addtogroup group_rtc
+* \{
+*
+* The Real-Time Clock (RTC) driver provides an application interface
+* for keeping track of time and date.
+*
+* The functions and other declarations used in this driver are in cy_rtc.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions
+* and declarations in the PDL.
+*
+* Use the RTC driver when the system requires the current time or date. You
+* can also use the RTC when you do not need the current time and date but you
+* do need accurate timing of events with one-second resolution.
+*
+* The RTC driver provides these features:
+* * Different hour format support.
+* * Multiple alarm function (two-alarms).
+* * Daylight Savings Time (DST) support.
+* * Automatic leap year compensation.
+* * Option to drive the RTC by an external 50 Hz or 60 Hz clock source
+*
+* The RTC driver provides access to the HW real-time clock. The HW RTC is
+* located in the Backup domain. You need to choose the clock source for the
+* Backup domain using the Cy_SysClk_ClkBakSetSource() function. If the clock
+* for the Backup domain is set and enabled, the RTC automatically
+* starts counting.
+*
+* The RTC driver keeps track of second, minute, hour, day of the week, day of
+* the month, month, and year.
+*
+* DST may be enabled and supports any start and end date. The start and end
+* dates can be a fixed date (like 24 March) or a relative date (like the
+* second Sunday in March).
+*
+* The RTC has two alarms that you can configure to generate an interrupt.
+* You specify the match value for the time when you want the alarm to occur.
+* Your interrupt handler then handles the response. The alarm flexibility
+* supports periodic alarms (such as every minute), or a single alarm
+* (13:45 on 28 September, 2043).
+*
+* <b> Clock Source </b>
+*
+* The Backup domain can be driven by:
+* * Watch-crystal oscillator (WCO). This is a high-accuracy oscillator that is
+* suitable for RTC applications and requires a 32.768 kHz external crystal
+* populated on the application board. The WCO can be supplied by Backup domain
+* and therefore can run without Vddd/Vccd present. This can be used to wake the
+* chip from Hibernate mode.
+*
+* * The Internal Low-speed Oscillator (ILO) routed from Clk_LF or directly
+* (as alternate backup domain clock source). Depending on the device power
+* mode the alternate backup domain clock source is set. For example, for
+* Deep Sleep mode the ILO is routed through Clk_LF. But for Hibernate
+* power mode the ILO is set directly. Note that, the ILO should be configured to
+* work in the Hibernate mode. For more info refer to the \ref group_sysclk
+* driver. The ILO is a low-accuracy RC-oscillator that does not require
+* any external elements on the board. Its poor accuracy (+/- 30%) means it is
+* less useful for the RTC. However, current can be supplied by an internal
+* power supply (Vback) and therefore it can run without Vddd/Vccd present.
+* This also can be used to wake the chip from Hibernate mode using RTC alarm
+* interrupt. For more details refer to \ref group_syspm driver description.
+*
+* * The Precision Internal Low-speed Oscillator (PILO), routed from Clk_LF
+* (alternate backup domain clock source). This is an RC-oscillator (ILO) that
+* can achieve accuracy of +/- 2% with periodic calibration. It is not expected
+* to be accurate enough for good RTC capability. The PILO requires
+* Vddd/Vccd present. It can be used in modes down to Deep Sleep, but ceases to
+* function in Hibernate mode.
+*
+* * External 50 Hz or 60 Hz sine-wave clock source or 32.768 kHz square clock
+* source.
+* For example, the wall AC frequency can be the clock source. Such a clock
+* source can be used if the external 32.768 kHz WCO is absent from the board.
+* For more details, refer to the Cy_RTC_SelectFrequencyPrescaler() function
+* description.
+*
+* The WCO is the recommended clock source for the RTC, if it is present
+* in design. For setting the Backup domain clock source, refer to the
+* \ref group_sysclk driver.
+*
+* \note If the WCO is enabled, it should source the Backup domain directly.
+* Do not route the WCO through the Clk_LF. This is because Clk_LF is not
+* available in all low-power modes.
+*
+* \section group_rtc_section_configuration Configuration Considerations
+*
+* Before RTC set up, ensure that the Backup domain is clocked with the desired
+* clock source.
+*
+* To set up an RTC, provide the configuration parameters in the
+* cy_stc_rtc_config_t structure. Then call Cy_RTC_Init(). You can also set the
+* date and time at runtime. Call Cy_RTC_SetDateAndTime() using the filled
+* cy_stc_rtc_config_t structure, or call Cy_RTC_SetDateAndTimeDirect() with
+* valid time and date values.
+*
+* <b> RTC Interrupt Handling </b>
+*
+* The RTC driver provides three interrupt handler functions:
+* Cy_RTC_Alarm1Interrupt(), Cy_RTC_Alarm2Interrupt(), and
+* Cy_RTC_CenturyInterrupt(). All three functions are blank functions with
+* the WEAK attribute. For any interrupt you use, redefine the interrupt handler
+* in your source code.
+*
+* When an interrupt occurs, call the Cy_RTC_Interrupt() function. The RTC
+* hardware provides a single interrupt line to the NVIC for the three RTC
+* interrupts. This function checks the interrupt register to determine which
+* interrupt (out of the three) was generated. It then calls the
+* appropriate handler.
+*
+* \warning The Cy_RTC_Alarm2Interrupt() is not called if the DST feature is
+* enabled. If DST is enabled, the Cy_RTC_Interrupt() function redirects that
+* interrupt to manage daylight savings time using Cy_RTC_DstInterrupt().
+* In general, the RTC interrupt handler function the Cy_RTC_DstInterrupt()
+* function is called instead of Cy_RTC_Alarm2Interrupt().
+*
+* For RTC interrupt handling, the user should:
+* -# Implement strong interrupt handling function(s) for the required events
+* (see above). If DST is enabled, then Alarm2 is not available. The DST handler
+* is built into the PDL.
+* -# Implement an RTC interrupt handler and call Cy_RTC_Interrupt()
+* from there.
+* -# Configure the RTC interrupt:
+* - Set the mask for RTC required interrupt using
+* Cy_RTC_SetInterruptMask().
+* - Initialize the RTC interrupt by setting priority and the RTC interrupt
+* vector using the Cy_SysInt_Init() function.
+* - Enable the RTC interrupt using the CMSIS core function NVIC_EnableIRQ().
+*
+* <b> Alarm functionality </b>
+*
+* To set up an alarm, enable the required RTC interrupt. Then provide the
+* configuration parameters in the cy_stc_rtc_alarm_t structure. You enable
+* any item you want matched, and provide a match value. You disable any other.
+* You do not need to set match values for disabled elements, as they are
+* ignored.
+* \note The alarm itself must be enabled in this structure. When a match
+* occurs, the alarm is triggered and your interrupt handler is called.
+*
+* An example is the best way to explain how this works. If you want an alarm
+* on every hour, then in the cy_stc_rtc_alarm_t structure, you provide
+* these values:
+*
+* Alarm_1.sec = 0u \n
+* Alarm_1.secEn = CY_RTC_ALARM_ENABLE \n
+* Alarm_1.min = 0u \n
+* Alarm_1.minEn = CY_RTC_ALARM_ENABLE \n
+* Alarm_1.hourEn = CY_RTC_ALARM_DISABLE \n
+* Alarm_1.dayOfWeekEn = CY_RTC_ALARM_DISABLE \n
+* Alarm_1.dateEn = CY_RTC_ALARM_DISABLE \n
+* Alarm_1.monthEn = CY_RTC_ALARM_DISABLE \n
+* Alarm_1.almEn = CY_RTC_ALARM_ENABLE \n
+*
+* With this setup, every time both the second and minute are zero, Alarm1 is
+* asserted. That happens once per hour. Note that, counterintuitively, to have
+* an alarm every hour, Alarm_1.hourEn is disabled. This is disabled because
+* for an hourly alarm you do not match the value of the hour.
+*
+* After cy_stc_rtc_alarm_t structure is filled, call the
+* Cy_RTC_SetAlarmDateAndTime(). The alarm can also be set without using the
+* cy_stc_rtc_alarm_t structure. Call Cy_RTC_SetAlarmDateAndTimeDirect() with
+* valid values.
+*
+* <b> The DST Feature </b>
+*
+* The DST feature is managed by the PDL using the RTC Alarm2 interrupt.
+* Therefore, you cannot have both DST enabled and use the Alarm2 interrupt.
+*
+* To set up the DST, route the RTC interrupt to NVIC:
+*
+* -# Initialize the RTC interrupt by setting priority and the RTC interrupt
+* vector using Cy_SysInt_Init().
+* -# Enable the RTC interrupt using the CMSIS core function NVIC_EnableIRQ().
+*
+* After this, provide the configuration parameters in the
+* cy_stc_rtc_dst_t structure. This structure consists of two
+* cy_stc_rtc_dst_format_t structures, one for DST Start time and one for
+* DST Stop time. You also specify whether these times are absolute or relative.
+*
+* After the cy_stc_rtc_dst_t structure is filled, call Cy_RTC_EnableDstTime()
+*
+* \section group_rtc_lp Low Power Support
+* The RTC provides the callback functions to facilitate
+* the low-power mode transition. The callback
+* \ref Cy_RTC_DeepSleepCallback must be called during execution
+* of \ref Cy_SysPm_CpuEnterDeepSleep, \ref Cy_RTC_HibernateCallback must be
+* called during execution of \ref Cy_SysPm_SystemEnterHibernate.
+* To trigger the callback execution, the callback must be registered
+* before calling the mode transition function.
+* Refer to \ref group_syspm driver for more
+* information about low-power mode transitions.
+*
+* \section group_rtc_section_more_information More Information
+*
+* For more information on the RTC peripheral, refer to the technical reference
+* manual (TRM).
+*
+* \section group_rtc_MISRA MISRA-C Compliance
+* The RTC driver does not have any specific deviations.
+*
+* \section group_rtc_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.20.1</td>
+* <td>Modified header guard CY_IP_MXS40SRSS_RTC.</td>
+* <td>To enable the PDL compilation with wounded out IP blocks.</td>
+* </tr>
+* <tr>
+* <td rowspan="3">2.20</td>
+* <td>Flattened the organization of the driver source code into the single
+* source directory and the single include directory.
+* </td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>Documentation update.</td>
+* <td>Documentation enhancement.</td>
+* </tr>
+* <tr>
+* <td>2.10</td>
+* <td>
+* * Corrected Cy_RTC_SetDateAndTimeDirect(), Cy_RTC_SetNextDstTime()
+* function.
+* * Corrected internal macro.
+* * Documentation updates.
+* </td>
+* <td>
+* * Incorrect behavior of \ref Cy_RTC_SetDateAndTimeDirect() and
+* \ref Cy_RTC_SetNextDstTime() work in debug mode.
+* * Debug assert correction in \ref Cy_RTC_ConvertDayOfWeek,
+* \ref Cy_RTC_IsLeapYear, \ref Cy_RTC_DaysInMonth.
+* </td>
+* </tr>
+* <tr>
+* <td>2.0</td>
+* <td>
+* Enhancement and defect fixes:
+* * Added input parameter(s) validation to all public functions.
+* * Removed "Cy_RTC_" prefixes from the internal functions names.
+* * Renamed the elements in the cy_stc_rtc_alarm structure.
+* * Changed the type of elements with limited set of values, from
+* uint32_t to enumeration.
+* </td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_rtc_macros Macros
+* \defgroup group_rtc_functions Functions
+* \{
+* \defgroup group_rtc_general_functions General
+* \defgroup group_rtc_alarm_functions Alarm
+* \defgroup group_rtc_dst_functions DST functions
+* \defgroup group_rtc_low_level_functions Low-Level
+* \defgroup group_rtc_interrupt_functions Interrupt
+* \defgroup group_rtc_low_power_functions Low Power Callbacks
+* \}
+* \defgroup group_rtc_data_structures Data Structures
+* \defgroup group_rtc_enums Enumerated Types
+*/
+
+#if !defined (CY_RTC_H)
+#define CY_RTC_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include "cy_device_headers.h"
+#include "cy_device.h"
+#include "cy_syslib.h"
+#include "cy_syspm.h"
+
+#ifdef CY_IP_MXS40SRSS_RTC
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+* \addtogroup group_rtc_macros
+* \{
+*/
+
+/** RTC driver identifier */
+#define CY_RTC_ID (CY_PDL_DRV_ID(0x28U))
+
+/** Driver major version */
+#define CY_RTC_DRV_VERSION_MAJOR 2
+
+/** Driver minor version */
+#define CY_RTC_DRV_VERSION_MINOR 20
+/** \} group_rtc_macros */
+
+/*******************************************************************************
+* Enumerated Types
+*******************************************************************************/
+
+/**
+* \addtogroup group_rtc_enums
+* \{
+*/
+
+/** RTC status enumeration */
+typedef enum
+ {
+ CY_RTC_SUCCESS = 0x00U, /**< Successful */
+ CY_RTC_BAD_PARAM = CY_RTC_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< One or more invalid parameters */
+ CY_RTC_TIMEOUT = CY_RTC_ID | CY_PDL_STATUS_ERROR | 0x02U, /**< Time-out occurs */
+ CY_RTC_INVALID_STATE = CY_RTC_ID | CY_PDL_STATUS_ERROR | 0x03U, /**< Operation not setup or is in an improper state */
+ CY_RTC_UNKNOWN = CY_RTC_ID | CY_PDL_STATUS_ERROR | 0xFFU /**< Unknown failure */
+} cy_en_rtc_status_t;
+
+/** This enumeration is used to set frequency by changing the it pre-scaler */
+typedef enum
+{
+ CY_RTC_FREQ_WCO_32768_HZ, /**< prescaler value for 32.768 kHz oscillator */
+ CY_RTC_FREQ_60_HZ, /**< prescaler value for 60 Hz source */
+ CY_RTC_FREQ_50_HZ, /**< prescaler value for 50 Hz source */
+} cy_en_rtc_clock_freq_t;
+
+/** This enumeration is used to set/get information for alarm 1 or alarm 2 */
+typedef enum cy_en_rtc_alarm
+{
+ CY_RTC_ALARM_1, /**< Alarm 1 enum */
+ CY_RTC_ALARM_2 /**< Alarm 2 enum */
+} cy_en_rtc_alarm_t;
+
+/** This enumeration is used to set/get hours format */
+typedef enum
+{
+ CY_RTC_24_HOURS, /**< The 24 hour format */
+ CY_RTC_12_HOURS /**< The 12 hour (AM/PM) format */
+} cy_en_rtc_hours_format_t;
+
+/** Enumeration to configure the RTC Write register */
+typedef enum
+{
+ CY_RTC_WRITE_DISABLED, /**< Writing the RTC is disabled */
+ CY_RTC_WRITE_ENABLED /**< Writing the RTC is enabled */
+} cy_en_rtc_write_status_t;
+
+/** Enumeration used to set/get DST format */
+typedef enum
+{
+ CY_RTC_DST_RELATIVE, /**< Relative DST format */
+ CY_RTC_DST_FIXED /**< Fixed DST format */
+} cy_en_rtc_dst_format_t;
+
+/** Enumeration to indicate the AM/PM period of day */
+typedef enum
+{
+ CY_RTC_AM, /**< AM period of day */
+ CY_RTC_PM /**< PM period of day */
+} cy_en_rtc_am_pm_t;
+
+/** Enumeration to enable/disable the RTC alarm on match with required value */
+typedef enum
+{
+ CY_RTC_ALARM_DISABLE, /**< Disable alarm on match with required value */
+ CY_RTC_ALARM_ENABLE /**< Enable alarm on match with required value */
+} cy_en_rtc_alarm_enable_t;
+/** \} group_rtc_enums */
+
+
+/*******************************************************************************
+* Types definition
+*******************************************************************************/
+
+/**
+* \addtogroup group_rtc_data_structures
+* \{
+*/
+
+/**
+* This is the data structure that is used to configure the rtc time
+* and date values.
+*/
+typedef struct cy_stc_rtc_config
+{
+ /* Time information */
+ uint32_t sec; /**< Seconds value, range [0-59] */
+ uint32_t min; /**< Minutes value, range [0-59] */
+ uint32_t hour; /**< Hour, range depends on hrFormat, if hrFormat = CY_RTC_24_HOURS, range [0-23];
+ If hrFormat = CY_RTC_12_HOURS, range [1-12] and appropriate AM/PM day
+ period should be set (amPm) */
+ cy_en_rtc_am_pm_t amPm; /**< AM/PM hour period, see \ref cy_en_rtc_am_pm_t.
+ This element is actual when hrFormat = CY_RTC_12_HOURS. The firmware
+ ignores this element if hrFormat = CY_RTC_24_HOURS */
+ cy_en_rtc_hours_format_t hrFormat; /**< Hours format, see \ref cy_en_rtc_hours_format_t */
+ uint32_t dayOfWeek; /**< Day of the week, range [1-7], see \ref group_rtc_day_of_the_week */
+
+ /* Date information */
+ uint32_t date; /**< Date of month, range [1-31] */
+ uint32_t month; /**< Month, range [1-12]. See \ref group_rtc_month */
+ uint32_t year; /**< Year, range [0-99] */
+} cy_stc_rtc_config_t;
+
+/** Decimal data structure that is used to save the Alarms */
+typedef struct cy_stc_rtc_alarm
+{
+ /* Alarm time information */
+ uint32_t sec; /**< Alarm seconds, range [0-59].
+ The appropriate ALARMX interrupt is be asserted on matching with this
+ value if secEn is previous enabled (secEn = 1) */
+ cy_en_rtc_alarm_enable_t secEn; /**< Enable alarm on seconds matching, see \ref cy_en_rtc_alarm_enable_t. */
+
+ uint32_t min; /**< Alarm minutes, range [0-59].
+ The appropriate ALARMX interrupt is be asserted on matching with this
+ value if minEn is previous enabled (minEn = 1) */
+ cy_en_rtc_alarm_enable_t minEn; /**< Enable alarm on minutes matching, see \ref cy_en_rtc_alarm_enable_t. */
+
+ uint32_t hour; /**< Alarm hours, range [0-23]
+ The appropriate ALARMX interrupt is be asserted on matching with this
+ value if hourEn is previous enabled (hourEn = 1) */
+ cy_en_rtc_alarm_enable_t hourEn; /**< Enable alarm on hours matching, see \ref cy_en_rtc_alarm_enable_t. */
+
+ uint32_t dayOfWeek; /**< Alarm day of the week, range [1-7]
+ The appropriate ALARMX interrupt is be asserted on matching with this
+ value if dayOfWeek is previous enabled (dayOfWeekEn = 1) */
+ cy_en_rtc_alarm_enable_t dayOfWeekEn; /**< Enable alarm on day of the week matching,
+ see \ref cy_en_rtc_alarm_enable_t */
+
+ /* Alarm date information */
+ uint32_t date; /**< Alarm date, range [1-31].
+ The appropriate ALARMX interrupt is be asserted on matching with this
+ value if dateEn is previous enabled (dateEn = 1) */
+ cy_en_rtc_alarm_enable_t dateEn; /**< Enable alarm on date matching, see \ref cy_en_rtc_alarm_enable_t. */
+
+ uint32_t month; /**< Alarm Month, range [1-12].
+ The appropriate ALARMX interrupt is be asserted on matching with this
+ value if dateEn is previous enabled (dateEn = 1) */
+ cy_en_rtc_alarm_enable_t monthEn; /**< Enable alarm on month matching, see \ref cy_en_rtc_alarm_enable_t. */
+
+ cy_en_rtc_alarm_enable_t almEn; /**< Enable Alarm for appropriate ALARMX, see \ref cy_en_rtc_alarm_enable_t.
+ If all alarm structure elements are enabled (almEn = CY_RTC_ALARM_ENABLE)
+ the alarm interrupt is be asserted every second. */
+} cy_stc_rtc_alarm_t;
+
+/**
+* This is DST structure for DST feature setting. Structure is combined with the
+* fixed format and the relative format. It is used to save the DST time and date
+* fixed or relative time format.
+*/
+typedef struct
+{
+ cy_en_rtc_dst_format_t format; /**< DST format. See /ref cy_en_rtc_dst_format_t.
+ Based on this value other structure elements
+ should be filled or could be ignored */
+ uint32_t hour; /**< Should be filled for both format types.
+ Hour is always presented in 24hour format, range[0-23] */
+ uint32_t dayOfMonth; /**< Day of Month, range[1-31]. This element should be filled if
+ format = CY_RTC_DST_FIXED. Firmware calculates this value in condition that
+ format = CY_RTC_DST_RELATIVE is selected */
+ uint32_t weekOfMonth; /**< Week of month, range[1-6]. This element should be filled if
+ format = CY_RTC_DST_RELATIVE.
+ Firmware calculates dayOfMonth value based on weekOfMonth
+ and dayOfWeek values */
+ uint32_t dayOfWeek; /**< Day of the week, this element should be filled in condition that
+ format = CY_RTC_DST_RELATIVE. Range[1- 7],
+ see \ref group_rtc_day_of_the_week. Firmware calculates dayOfMonth value
+ based on dayOfWeek and weekOfMonth values */
+ uint32_t month; /**< Month value, range[1-12], see \ref group_rtc_month.
+ This value should be filled for both format types */
+} cy_stc_rtc_dst_format_t;
+
+/** This is the DST structure to handle start DST and stop DST */
+typedef struct
+{
+ cy_stc_rtc_dst_format_t startDst; /**< DST start time structure */
+ cy_stc_rtc_dst_format_t stopDst; /**< DST stop time structure */
+} cy_stc_rtc_dst_t;
+
+/** \} group_rtc_data_structures */
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_rtc_functions
+* \{
+*/
+
+/**
+* \addtogroup group_rtc_general_functions
+* \{
+*/
+cy_en_rtc_status_t Cy_RTC_Init(cy_stc_rtc_config_t const *config);
+cy_en_rtc_status_t Cy_RTC_SetDateAndTime(cy_stc_rtc_config_t const *dateTime);
+void Cy_RTC_GetDateAndTime(cy_stc_rtc_config_t *dateTime);
+cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour,
+ uint32_t date, uint32_t month, uint32_t year);
+cy_en_rtc_status_t Cy_RTC_SetHoursFormat(cy_en_rtc_hours_format_t hoursFormat);
+void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel);
+/** \} group_rtc_general_functions */
+
+/**
+* \addtogroup group_rtc_alarm_functions
+* \{
+*/
+cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTime(cy_stc_rtc_alarm_t const *alarmDateTime, cy_en_rtc_alarm_t alarmIndex);
+void Cy_RTC_GetAlarmDateAndTime(cy_stc_rtc_alarm_t *alarmDateTime, cy_en_rtc_alarm_t alarmIndex);
+cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour,
+ uint32_t date, uint32_t month, cy_en_rtc_alarm_t alarmIndex);
+/** \} group_rtc_alarm_functions */
+
+/**
+* \addtogroup group_rtc_dst_functions
+* \{
+*/
+cy_en_rtc_status_t Cy_RTC_EnableDstTime(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate);
+cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst);
+bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate);
+/** \} group_rtc_dst_functions */
+
+/**
+* \addtogroup group_rtc_interrupt_functions
+* \{
+*/
+void Cy_RTC_Interrupt(cy_stc_rtc_dst_t const *dstTime, bool mode);
+void Cy_RTC_Alarm1Interrupt(void);
+void Cy_RTC_Alarm2Interrupt(void);
+void Cy_RTC_DstInterrupt(cy_stc_rtc_dst_t const *dstTime);
+void Cy_RTC_CenturyInterrupt(void);
+uint32_t Cy_RTC_GetInterruptStatus(void);
+uint32_t Cy_RTC_GetInterruptStatusMasked(void);
+uint32_t Cy_RTC_GetInterruptMask(void);
+void Cy_RTC_ClearInterrupt(uint32_t interruptMask);
+void Cy_RTC_SetInterrupt(uint32_t interruptMask);
+void Cy_RTC_SetInterruptMask(uint32_t interruptMask);
+/** \} group_rtc_interrupt_functions */
+
+/**
+* \addtogroup group_rtc_low_power_functions
+* \{
+*/
+cy_en_syspm_status_t Cy_RTC_DeepSleepCallback(const cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
+cy_en_syspm_status_t Cy_RTC_HibernateCallback(const cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
+/** \} group_rtc_low_power_functions */
+
+/**
+* \addtogroup group_rtc_low_level_functions
+* \{
+*/
+__STATIC_INLINE uint32_t Cy_RTC_ConvertDayOfWeek(uint32_t day, uint32_t month, uint32_t year);
+__STATIC_INLINE bool Cy_RTC_IsLeapYear(uint32_t year);
+__STATIC_INLINE uint32_t Cy_RTC_DaysInMonth(uint32_t month, uint32_t year);
+__STATIC_INLINE void Cy_RTC_SyncFromRtc(void);
+__STATIC_INLINE cy_en_rtc_status_t Cy_RTC_WriteEnable(cy_en_rtc_write_status_t writeEnable);
+__STATIC_INLINE uint32_t Cy_RTC_GetSyncStatus(void);
+__STATIC_INLINE uint32_t Cy_RTC_ConvertBcdToDec(uint32_t bcdNum);
+__STATIC_INLINE uint32_t Cy_RTC_ConvertDecToBcd(uint32_t decNum);
+__STATIC_INLINE cy_en_rtc_hours_format_t Cy_RTC_GetHoursFormat(void);
+__STATIC_INLINE bool Cy_RTC_IsExternalResetOccurred(void);
+
+__STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t dateBcd);
+__STATIC_INLINE void Cy_RTC_SyncToRtcAhbAlarm(uint32_t alarmTimeBcd, uint32_t alarmDateBcd, cy_en_rtc_alarm_t alarmIndex);
+/** \} group_rtc_low_level_functions */
+
+/** \} group_rtc_functions */
+
+/**
+* \addtogroup group_rtc_macros
+* \{
+*/
+
+/*******************************************************************************
+* API Constants
+*******************************************************************************/
+
+/**
+* \defgroup group_rtc_day_of_the_week Day of the week definitions
+* \{
+* Definitions of days in the week
+*/
+#define CY_RTC_SUNDAY (1UL) /**< Sequential number of Sunday in the week */
+#define CY_RTC_MONDAY (2UL) /**< Sequential number of Monday in the week */
+#define CY_RTC_TUESDAY (3UL) /**< Sequential number of Tuesday in the week */
+#define CY_RTC_WEDNESDAY (4UL) /**< Sequential number of Wednesday in the week */
+#define CY_RTC_THURSDAY (5UL) /**< Sequential number of Thursday in the week */
+#define CY_RTC_FRIDAY (6UL) /**< Sequential number of Friday in the week */
+#define CY_RTC_SATURDAY (7UL) /**< Sequential number of Saturday in the week */
+/** \} group_rtc_day_of_the_week */
+
+/**
+* \defgroup group_rtc_dst_week_of_month Week of month definitions
+* \{
+* Week of Month setting constants definitions for Daylight Saving Time feature
+*/
+#define CY_RTC_FIRST_WEEK_OF_MONTH (1UL) /**< First week in the month */
+#define CY_RTC_SECOND_WEEK_OF_MONTH (2UL) /**< Second week in the month */
+#define CY_RTC_THIRD_WEEK_OF_MONTH (3UL) /**< Third week in the month */
+#define CY_RTC_FOURTH_WEEK_OF_MONTH (4UL) /**< Fourth week in the month */
+#define CY_RTC_FIFTH_WEEK_OF_MONTH (5UL) /**< Fifth week in the month */
+#define CY_RTC_LAST_WEEK_OF_MONTH (6UL) /**< Last week in the month */
+/** \} group_rtc_dst_week_of_month */
+
+/**
+* \defgroup group_rtc_month Month definitions
+* \{
+* Constants definition for Months
+*/
+#define CY_RTC_JANUARY (1UL) /**< Sequential number of January in the year */
+#define CY_RTC_FEBRUARY (2UL) /**< Sequential number of February in the year */
+#define CY_RTC_MARCH (3UL) /**< Sequential number of March in the year */
+#define CY_RTC_APRIL (4UL) /**< Sequential number of April in the year */
+#define CY_RTC_MAY (5UL) /**< Sequential number of May in the year */
+#define CY_RTC_JUNE (6UL) /**< Sequential number of June in the year */
+#define CY_RTC_JULY (7UL) /**< Sequential number of July in the year */
+#define CY_RTC_AUGUST (8UL) /**< Sequential number of August in the year */
+#define CY_RTC_SEPTEMBER (9UL) /**< Sequential number of September in the year */
+#define CY_RTC_OCTOBER (10UL) /**< Sequential number of October in the year */
+#define CY_RTC_NOVEMBER (11UL) /**< Sequential number of November in the year */
+#define CY_RTC_DECEMBER (12UL) /**< Sequential number of December in the year */
+/** \} group_rtc_month */
+
+/**
+* \defgroup group_rtc_days_in_month Number of days in month definitions
+* \{
+* Definition of days in current month
+*/
+#define CY_RTC_DAYS_IN_JANUARY (31U) /**< Number of days in January */
+#define CY_RTC_DAYS_IN_FEBRUARY (28U) /**< Number of days in February */
+#define CY_RTC_DAYS_IN_MARCH (31U) /**< Number of days in March */
+#define CY_RTC_DAYS_IN_APRIL (30U) /**< Number of days in April */
+#define CY_RTC_DAYS_IN_MAY (31U) /**< Number of days in May */
+#define CY_RTC_DAYS_IN_JUNE (30U) /**< Number of days in June */
+#define CY_RTC_DAYS_IN_JULY (31U) /**< Number of days in July */
+#define CY_RTC_DAYS_IN_AUGUST (31U) /**< Number of days in August */
+#define CY_RTC_DAYS_IN_SEPTEMBER (30U) /**< Number of days in September */
+#define CY_RTC_DAYS_IN_OCTOBER (31U) /**< Number of days in October */
+#define CY_RTC_DAYS_IN_NOVEMBER (30U) /**< Number of days in November */
+#define CY_RTC_DAYS_IN_DECEMBER (31U) /**< Number of days in December */
+/** \} group_rtc_days_in_month */
+
+/**
+* \defgroup group_rtc_macros_interrupts RTC Interrupt sources
+* \{
+* Definitions for RTC interrupt sources
+*/
+/** Alarm 1 status */
+#define CY_RTC_INTR_ALARM1 BACKUP_INTR_ALARM1_Msk
+
+/** Alarm 2 status */
+#define CY_RTC_INTR_ALARM2 BACKUP_INTR_ALARM2_Msk
+
+/**
+* This interrupt occurs when the year is reached to 2100 which is rolling
+* over the year field value from 99 to 0
+*/
+#define CY_RTC_INTR_CENTURY BACKUP_INTR_CENTURY_Msk
+/** \} group_rtc_macros_interrupts */
+
+/**
+* \defgroup group_rtc_busy_status RTC Status definitions
+* \{
+* Definitions for indicating the RTC BUSY bit
+*/
+#define CY_RTC_BUSY (1UL) /**< RTC Busy bit is set, RTC is pending */
+#define CY_RTC_AVAILABLE (0UL) /**< RTC Busy bit is cleared, RTC is available */
+/** \} group_rtc_busy_status */
+
+/*******************************************************************************
+* Internal Constants
+*******************************************************************************/
+
+/** \cond INTERNAL */
+
+/** Days per week definition */
+#define CY_RTC_DAYS_PER_WEEK (7UL)
+
+/** Month per year definition */
+#define CY_RTC_MONTHS_PER_YEAR (12U)
+
+/** Maximum value of seconds and minutes */
+#define CY_RTC_MAX_SEC_OR_MIN (59UL)
+
+/** Biggest value of hours definition */
+#define CY_RTC_MAX_HOURS_24H (23UL)
+
+/** Maximum value of year definition */
+#define CY_RTC_MAX_DAYS_IN_MONTH (31UL)
+
+/** Maximum value of year definition */
+#define CY_RTC_MAX_YEAR (99UL)
+
+/** Number of RTC interrupts */
+#define CY_RTC_NUM_OF_INTR (3U)
+
+/** Number of RTC interrupts */
+#define CY_RTC_TRYES_TO_SETUP_DST (24U)
+
+/** RTC AM/PM bit for 12H hour mode */
+#define CY_RTC_12HRS_PM_BIT (0x20UL)
+
+/** Mask for reading RTC AM/PM bit for 12H mode */
+#define CY_RTC_BACKUP_RTC_TIME_RTC_PM ((uint32_t) (CY_RTC_12HRS_PM_BIT << BACKUP_RTC_TIME_RTC_HOUR_Pos))
+
+/** Internal define for BCD values converting */
+#define CY_RTC_BCD_NUMBER_SIZE (4UL)
+
+/** Internal mask for BCD values converting */
+#define CY_RTC_BCD_ONE_DIGIT_MASK (0x0000000FUL)
+
+/** Internal define of dozen degree for BCD values converting */
+#define CY_RTC_BCD_DOZED_DEGREE (10UL)
+
+/** Internal define of hundred degree for BCD values converting */
+#define CY_RTC_BCD_HUNDRED_DEGRE (100UL)
+
+/** Definition of six WCO clocks in microseconds */
+#define CY_RTC_DELAY_WHILE_READING_US (183U)
+
+/** Definition of two WCO clocks in microseconds */
+#define CY_RTC_DELAY_WRITE_US (62U)
+
+/** Definition of two WCO clocks in microseconds */
+#define CY_RTC_DELAY_FOR_NEXT_DST (2000U)
+
+/** Two thousand years definition */
+#define CY_RTC_TWO_THOUSAND_YEARS (2000UL)
+
+/** Two thousand years definition */
+#define CY_RTC_TWENTY_ONE_HUNDRED_YEARS (2100UL)
+
+/** Mask for reading RTC hour for 12H mode */
+#define CY_RTC_BACKUP_RTC_TIME_RTC_12HOUR (0x1f0000UL)
+
+/** Half day hours definition */
+#define CY_RTC_HOURS_PER_HALF_DAY (12UL)
+
+/** First day of the month definition */
+#define CY_RTC_FIRST_DAY_OF_MONTH (1UL)
+
+/** Internal definition for DST GetDstStatus() function */
+#define CY_RTC_DST_MONTH_POSITION (10UL)
+
+/** Internal definition for DST GetDstStatus() function */
+#define CY_RTC_DST_DAY_OF_MONTH_POSITION (5UL)
+
+/** Definition of delay in microseconds after try to set DST */
+#define CY_RTC_DELAY_AFTER_DST_US (62U)
+
+/** RTC days in months table */
+extern uint8_t const cy_RTC_daysInMonthTbl[CY_RTC_MONTHS_PER_YEAR];
+
+/* Internal macro to validate parameters in Cy_RTC_SelectFrequencyPrescaler() function */
+#define CY_RTC_IS_CLK_VALID(clkSel) (((clkSel) == CY_RTC_FREQ_WCO_32768_HZ) || \
+ ((clkSel) == CY_RTC_FREQ_60_HZ) || \
+ ((clkSel) == CY_RTC_FREQ_50_HZ))
+
+/* Internal macro to validate parameters in Cy_RTC_SetHoursFormat() function */
+#define CY_RTC_IS_HRS_FORMAT_VALID(hoursFormat) (((hoursFormat) == CY_RTC_24_HOURS) || \
+ ((hoursFormat) == CY_RTC_12_HOURS))
+
+/* Internal macro to validate parameters in Cy_RTC_WriteEnable() function */
+#define CY_RTC_IS_WRITE_VALID(writeEnable) (((writeEnable) == CY_RTC_WRITE_DISABLED) || \
+ ((writeEnable) == CY_RTC_WRITE_ENABLED))
+
+/* Internal macro of all possible RTC interrupts */
+#define CY_RTC_INTR_MASK (CY_RTC_INTR_ALARM1 | CY_RTC_INTR_ALARM2 | CY_RTC_INTR_CENTURY)
+
+/* Macro to validate parameters in interrupt related functions */
+#define CY_RTC_INTR_VALID(interruptMask) (0UL == ((interruptMask) & ((uint32_t) ~(CY_RTC_INTR_MASK))))
+
+/* Internal macro to validate RTC seconds and minutes parameters */
+#define CY_RTC_IS_SEC_VALID(sec) ((sec) <= CY_RTC_MAX_SEC_OR_MIN)
+
+/* Internal macro to validate RTC seconds and minutes parameters */
+#define CY_RTC_IS_MIN_VALID(min) ((min) <= CY_RTC_MAX_SEC_OR_MIN)
+
+/* Internal macro to validate RTC hour parameter */
+#define CY_RTC_IS_HOUR_VALID(hour) ((hour) <= CY_RTC_MAX_HOURS_24H)
+
+/* Internal macro to validate RTC day of the week parameter */
+#define CY_RTC_IS_DOW_VALID(dayOfWeek) (((dayOfWeek) > 0U) && ((dayOfWeek) <= CY_RTC_DAYS_PER_WEEK))
+
+/* Internal macro to validate RTC day parameter */
+#define CY_RTC_IS_DAY_VALID(day) (((day) > 0U) && ((day) <= CY_RTC_MAX_DAYS_IN_MONTH))
+
+/* Internal macro to validate RTC month parameter */
+#define CY_RTC_IS_MONTH_VALID(month) (((month) > 0U) && ((month) <= CY_RTC_MONTHS_PER_YEAR))
+
+/* Internal macro to validate RTC year parameter */
+#define CY_RTC_IS_YEAR_SHORT_VALID(year) ((year) <= CY_RTC_MAX_YEAR)
+
+/* Internal macro to validate the year value in the Cy_RTC_ConvertDayOfWeek() */
+#define CY_RTC_IS_YEAR_LONG_VALID(year) ((year) > 0U)
+
+/* Internal macro to validate RTC alarm parameter */
+#define CY_RTC_IS_ALARM_EN_VALID(alarmEn) (((alarmEn) == CY_RTC_ALARM_DISABLE) || \
+ ((alarmEn) == CY_RTC_ALARM_ENABLE))
+
+/* Internal macro to validate RTC alarm index parameter */
+#define CY_RTC_IS_ALARM_IDX_VALID(alarmIndex) (((alarmIndex) == CY_RTC_ALARM_1) || ((alarmIndex) == CY_RTC_ALARM_2))
+
+/* Internal macro to validate RTC alarm index parameter */
+#define CY_RTC_IS_DST_FORMAT_VALID(format) (((format) == CY_RTC_DST_RELATIVE) || ((format) == CY_RTC_DST_FIXED))
+
+/** \endcond */
+/** \} group_rtc_macros */
+
+/**
+* \addtogroup group_rtc_low_level_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_RTC_ConvertDayOfWeek
+****************************************************************************//**
+*
+* Returns a day of the week for a year, month, and day of month that are passed
+* through parameters. Zeller's congruence is used to calculate the day of
+* the week.
+* RTC HW block does not provide the converting function for day of week. This
+* function should be called before Cy_RTC_SetDateAndTime() to get the day of
+* week.
+*
+* For the Georgian calendar, Zeller's congruence is:
+* h = (q + [13 * (m + 1)] + K + [K/4] + [J/4] - 2J) mod 7
+*
+* h - The day of the week (0 = Saturday, 1 = Sunday, 2 = Monday, ., 6 = Friday).
+* q - The day of the month.
+* m - The month (3 = March, 4 = April, 5 = May, ..., 14 = February)
+* K - The year of the century (year mod 100).
+* J - The zero-based century (actually [year/100]) For example, the zero-based
+* centuries for 1995 and 2000 are 19 and 20 respectively (not to be
+* confused with the common ordinal century enumeration which indicates
+* 20th for both cases).
+*
+* \note In this algorithm January and February are counted as months 13 and 14
+* of the previous year.
+*
+* \param day
+* The day of the month, Valid range 1..31.
+*
+* \param month
+* The month of the year, see \ref group_rtc_month.
+*
+* \param year
+* The year value. Valid range non-zero value.
+*
+* \return
+* Returns a day of the week, see \ref group_rtc_day_of_the_week.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_RTC_ConvertDayOfWeek(uint32_t day, uint32_t month, uint32_t year)
+{
+ uint32_t retVal;
+
+ CY_ASSERT_L2(CY_RTC_IS_DAY_VALID(day));
+ CY_ASSERT_L2(CY_RTC_IS_MONTH_VALID(month));
+ CY_ASSERT_L2(CY_RTC_IS_YEAR_LONG_VALID(year));
+
+ /* Converts month number from regular convention
+ * (1=January,..., 12=December) to convention required for this
+ * algorithm (January and February are counted as months 13 and 14 of
+ * previous year).
+ */
+ if (month < CY_RTC_MARCH)
+ {
+ month = CY_RTC_MONTHS_PER_YEAR + month;
+ year--;
+ }
+
+ /* Calculates Day of Week using Zeller's congruence algorithms */
+ retVal =
+ (day + (((month + 1UL) * 26UL) / 10UL) + year + (year / 4UL) + (6UL * (year / 100UL)) + (year / 400UL)) % 7UL;
+
+ /* Makes correction for Saturday. Saturday number should be 7 instead of 0*/
+ if (0u == retVal)
+ {
+ retVal = CY_RTC_SATURDAY;
+ }
+
+ return(retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_IsLeapYear
+****************************************************************************//**
+*
+* Checks whether the year passed through the parameter is leap or not.
+*
+* This API is for checking an invalid value input for leap year.
+* RTC HW block does not provide a validation checker against time/date values,
+* the valid range of days in Month should be checked before SetDateAndTime()
+* function call. Leap year is identified as a year that is a multiple of 4
+* or 400 but not 100.
+*
+* \param year
+* The year to be checked. Valid range non-zero value.
+*
+* \return
+* False - The year is not leap.
+* True - The year is leap.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_RTC_IsLeapYear(uint32_t year)
+{
+ CY_ASSERT_L2(CY_RTC_IS_YEAR_LONG_VALID(year));
+
+ return(((0U == (year % 4UL)) && (0U != (year % 100UL))) || (0U == (year % 400UL)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_DaysInMonth
+****************************************************************************//**
+*
+* Returns a number of days in a month passed through the parameters. This API
+* is for checking an invalid value input for days.
+* RTC HW block does not provide a validation checker against time/date values,
+* the valid range of days in Month should be checked before SetDateAndTime()
+* function call.
+*
+* \param month
+* The month of the year, see \ref group_rtc_month.
+*
+* \param year
+* A year value. Valid range non-zero value.
+*
+* \return
+* A number of days in a month in the year passed through the parameters.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_RTC_DaysInMonth(uint32_t month, uint32_t year)
+{
+ uint32_t retVal;
+
+ CY_ASSERT_L2(CY_RTC_IS_MONTH_VALID(month));
+ CY_ASSERT_L2(CY_RTC_IS_YEAR_LONG_VALID(year));
+
+ retVal = cy_RTC_daysInMonthTbl[month - 1UL];
+
+ if (CY_RTC_FEBRUARY == month)
+ {
+ if (Cy_RTC_IsLeapYear(year))
+ {
+ retVal++;
+ }
+ }
+ return(retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SyncFromRtc
+****************************************************************************//**
+*
+* The Synchronizer updates RTC values into AHB RTC user registers from the
+* actual RTC. By calling this function, the actual RTC register values is
+* copied to AHB user registers.
+*
+* \note Only after calling Cy_RTC_SyncFromRtc(), the RTC time values can be
+* read. After Cy_RTC_SyncFromRtc() calling the snapshot of the actual RTC
+* registers are copied to the user registers. Meanwhile the RTC continues to
+* clock.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_RTC_SyncFromRtc(void)
+{
+ uint32_t interruptState;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ /* RTC Write is possible only in the condition that CY_RTC_BUSY bit = 0
+ * or RTC Write bit is not set.
+ */
+ if ((CY_RTC_BUSY != Cy_RTC_GetSyncStatus()) && (!_FLD2BOOL(BACKUP_RTC_RW_WRITE, BACKUP_RTC_RW)))
+ {
+ /* Setting RTC Read bit */
+ BACKUP_RTC_RW = BACKUP_RTC_RW_READ_Msk;
+
+ /* Delay to guarantee RTC data reading */
+ Cy_SysLib_DelayUs(CY_RTC_DELAY_WHILE_READING_US);
+
+ /* Clearing RTC Read bit */
+ BACKUP_RTC_RW = 0U;
+ }
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_WriteEnable
+****************************************************************************//**
+*
+* Set/Clear writeable option for RTC user registers. When the Write bit is set,
+* data can be written into the RTC user registers. After all the RTC writes are
+* done, the firmware must clear (call Cy_RTC_WriteEnable(RTC_WRITE_DISABLED))
+* the Write bit for the RTC update to take effect.
+*
+* Set/Clear cannot be done if the RTC is still busy with a previous update
+* (CY_RTC_BUSY = 1) or RTC Reading is executing.
+*
+* \param writeEnable
+* Write status, see \ref cy_en_rtc_write_status_t.
+*
+* \return
+* CY_RTC_SUCCESS - Set/Clear Write bit was successful.
+* CY_RTC_INVALID_STATE - RTC is busy with a previous update.
+* See \ref cy_en_rtc_status_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_rtc_status_t Cy_RTC_WriteEnable(cy_en_rtc_write_status_t writeEnable)
+{
+ cy_en_rtc_status_t retVal = CY_RTC_INVALID_STATE;
+
+ CY_ASSERT_L3(CY_RTC_IS_WRITE_VALID(writeEnable));
+
+ if (writeEnable == CY_RTC_WRITE_ENABLED)
+ {
+ /* RTC Write bit set is possible only in condition that CY_RTC_BUSY bit = 0
+ * or RTC Read bit is not set
+ */
+ if ((CY_RTC_BUSY != Cy_RTC_GetSyncStatus()) && (!_FLD2BOOL(BACKUP_RTC_RW_READ, BACKUP_RTC_RW)))
+ {
+ BACKUP_RTC_RW |= BACKUP_RTC_RW_WRITE_Msk;
+ retVal = CY_RTC_SUCCESS;
+ }
+ }
+ else
+ {
+ /* Clearing Write Bit to complete write procedure */
+ BACKUP_RTC_RW &= ((uint32_t) ~BACKUP_RTC_RW_WRITE_Msk);
+
+ /* Delay to guarantee data write after clearing write bit */
+ Cy_SysLib_DelayUs(CY_RTC_DELAY_WRITE_US);
+ retVal = CY_RTC_SUCCESS;
+ }
+
+ return(retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_GetSyncStatus
+****************************************************************************//**
+*
+* Return current status of CY_RTC_BUSY. The status indicates
+* synchronization between the RTC user register and the actual RTC register.
+* CY_RTC_BUSY bit is set if it is synchronizing. It is not possible to set
+* the Read or Write bit until CY_RTC_BUSY clears.
+*
+* \return
+* The status of RTC user register synchronization. See
+* \ref group_rtc_busy_status
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_RTC_GetSyncStatus(void)
+{
+ return((_FLD2BOOL(BACKUP_STATUS_RTC_BUSY, BACKUP_STATUS)) ? CY_RTC_BUSY : CY_RTC_AVAILABLE);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_ConvertBcdToDec
+****************************************************************************//**
+*
+* Converts an 8-bit BCD number into an 8-bit hexadecimal number. Each byte is
+* converted individually and returned as an individual byte in the 32-bit
+* variable.
+*
+* \param
+* bcdNum An 8-bit BCD number. Each byte represents BCD.
+*
+* \return
+* decNum An 8-bit hexadecimal equivalent number of the BCD number.
+*
+* For example, for 0x11223344 BCD number, the function returns
+* 0x2C in hexadecimal format.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_RTC_ConvertBcdToDec(uint32_t bcdNum)
+{
+ uint32_t retVal;
+
+ retVal =
+ ((bcdNum & (CY_RTC_BCD_ONE_DIGIT_MASK << CY_RTC_BCD_NUMBER_SIZE))
+ >> CY_RTC_BCD_NUMBER_SIZE ) * CY_RTC_BCD_DOZED_DEGREE;
+
+ retVal += bcdNum & CY_RTC_BCD_ONE_DIGIT_MASK;
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_ConvertDecToBcd
+****************************************************************************//**
+*
+* Converts an 8-bit hexadecimal number into an 8-bit BCD number. Each byte
+* is converted individually and returned as an individual byte in the 32-bit
+* variable.
+*
+* \param
+* decNum An 8-bit hexadecimal number. Each byte is represented in hex.
+* 0x11223344 -> 0x20 hex format.
+*
+* \return
+* An 8-bit BCD equivalent of the passed hexadecimal number.
+*
+* For example, for 0x11223344 hexadecimal number, the function returns
+* 0x20 BCD number.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_RTC_ConvertDecToBcd(uint32_t decNum)
+{
+ uint32_t retVal;
+ uint32_t tmpVal;
+
+ tmpVal = decNum % CY_RTC_BCD_HUNDRED_DEGRE;
+ retVal = ((uint32_t)(tmpVal / CY_RTC_BCD_DOZED_DEGREE)) << CY_RTC_BCD_NUMBER_SIZE;
+ retVal += tmpVal % CY_RTC_BCD_DOZED_DEGREE;
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_GetHoursFormat
+****************************************************************************//**
+*
+* Returns current 12/24 hours format.
+*
+* \note
+* Before getting the RTC current hours format, the Cy_RTC_SyncFromRtc() function
+* should be called.
+*
+* \return
+* The current RTC hours format. See \ref cy_en_rtc_hours_format_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_rtc_hours_format_t Cy_RTC_GetHoursFormat(void)
+{
+ return((_FLD2BOOL(BACKUP_RTC_TIME_CTRL_12HR, BACKUP_RTC_TIME)) ? CY_RTC_12_HOURS : CY_RTC_24_HOURS);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_IsExternalResetOccurred
+****************************************************************************//**
+*
+* The function checks the reset cause and returns the Boolean result.
+*
+* \return
+* True if the reset reason is the power cycle and the XRES (external reset).
+* False if the reset reason is other than power cycle and the XRES.
+*
+* \note Based on a return value the RTC time and date can be updated or skipped
+* after the device reset. For example, you should skip the
+* Cy_RTC_SetAlarmDateAndTime() call function if internal WDT reset occurs.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_RTC_IsExternalResetOccurred(void)
+{
+ return(0u == Cy_SysLib_GetResetReason());
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SyncToRtcAhbDateAndTime
+****************************************************************************//**
+*
+* This function updates new time and date into the time and date RTC AHB
+* registers.
+*
+* \param timeBcd
+* The BCD-formatted time variable which has the same bit masks as the
+* RTC_TIME register:
+*
+* [0:6] - Calendar seconds in BCD, the range 0-59. \n
+* [14:8] - Calendar minutes in BCD, the range 0-59. \n
+* [21:16] - Calendar hours in BCD, value depends on the 12/24-hour mode. \n
+* 12HR: [21]:0 = AM, 1 = PM, [20:16] = 1 - 12; \n
+* 24HR: [21:16] = 0-23. \n
+* [22] - Selects the 12/24-hour mode: 1 - 12-hour, 0 - 24-hour. \n
+* [26:24] - A calendar day of the week, the range 1 - 7, where 1 - Sunday. \n
+*
+* \param dateBcd
+* The BCD-formatted time variable which has the same bit masks as the
+* RTC_DATE register:
+*
+* [5:0] - A calendar day of a month in BCD, the range 1-31. \n
+* [12:8] - A calendar month in BCD, the range 1-12. \n
+* [23:16] - A calendar year in BCD, the range 0-99. \n
+*
+* \note Ensure that the parameters are presented in the BCD format. Use the
+* ConstructTimeDate() function to construct BCD time and date values.
+* Refer to ConstructTimeDate() function description for more details
+* about the RTC_TIME and RTC_DATE bit fields format.
+*
+* The RTC AHB registers can be updated only under condition that the
+* Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0). Call the
+* Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED) and ensure that Cy_RTC_WriteEnable()
+* returned CY_RTC_SUCCESS. Then you can call Cy_RTC_SyncToRtcAhbDateAndTime().
+* Do not forget to clear the RTC Write bit to finish an RTC register update by
+* calling Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED) after you executed
+* Cy_RTC_SyncToRtcAhbDateAndTime(). Ensure that Cy_RTC_WriteEnable()
+* returned CY_RTC_SUCCESS.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t dateBcd)
+{
+ BACKUP_RTC_TIME = timeBcd;
+ BACKUP_RTC_DATE = dateBcd;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SyncToRtcAhbAlarm
+****************************************************************************//**
+*
+* This function updates new alarm time and date into the alarm tire and date
+* RTC AHB registers.
+*
+* \param alarmTimeBcd
+* The BCD-formatted time variable which has the same bit masks as the
+* ALMx_TIME register time fields:
+*
+* [0:6] - Alarm seconds in BCD, the range 0-59. \n
+* [7] - Alarm seconds Enable: 0 - ignore, 1 - match. \n
+* [14:8] - Alarm minutes in BCD, the range 0-59. \n
+* [15] - Alarm minutes Enable: 0 - ignore, 1 - match. \n
+* [21:16] - Alarm hours in BCD, value depending on the 12/24-hour mode
+* (RTC_CTRL_12HR)\n
+* 12HR: [21]:0 = AM, 1 = PM, [20:16] = 1 - 12; \n
+* 24HR: [21:16] = the range 0-23. \n
+* [23] - Alarm hours Enable: 0 - ignore, 1 - match. \n
+* [26:24] - An alarm day of the week, the range 1 - 7, where 1 - Monday. \n
+* [31] - An alarm day of the week Enable: 0 - ignore, 1 - match. \n
+*
+* \param alarmDateBcd
+* The BCD-formatted date variable which has the same bit masks as the
+* ALMx_DATE register date fields: \n
+* [5:0] - An alarm day of a month in BCD, the range 1-31. \n
+* [7] - An alarm day of a month Enable: 0 - ignore, 1 - match. \n
+* [12:8] - An alarm month in BCD, the range 1-12. \n
+* [15] - An alarm month Enable: 0 - ignore, 1 - match. \n
+* [31] - The Enable alarm: 0 - Alarm is disabled, 1 - Alarm is enabled. \n
+*
+* \param alarmIndex
+* The alarm index to be configured, see \ref cy_en_rtc_alarm_t.
+*
+* \note Ensure that the parameters are presented in the BCD format. Use the
+* ConstructTimeDate() function to construct BCD time and date values.
+* Refer to ConstructTimeDate() function description for more details
+* about the RTC ALMx_TIME and ALMx_DATE bit-fields format.
+*
+* The RTC AHB registers can be updated only under condition that the
+* Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0). Call the
+* Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED) and ensure that Cy_RTC_WriteEnable()
+* returned CY_RTC_SUCCESS. Then you can call Cy_RTC_SyncToRtcAhbDateAndTime().
+* Do not forget to clear the RTC Write bit to finish an RTC register update by
+* calling the Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED) after you executed
+* Cy_RTC_SyncToRtcAhbDateAndTime(). Ensure that Cy_RTC_WriteEnable()
+* returned CY_RTC_SUCCESS.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_RTC_SyncToRtcAhbAlarm(uint32_t alarmTimeBcd, uint32_t alarmDateBcd, cy_en_rtc_alarm_t alarmIndex)
+{
+ CY_ASSERT_L3(CY_RTC_IS_ALARM_IDX_VALID(alarmIndex));
+
+ if (alarmIndex != CY_RTC_ALARM_2)
+ {
+ BACKUP_ALM1_TIME = alarmTimeBcd;
+ BACKUP_ALM1_DATE = alarmDateBcd;
+ }
+ else
+ {
+ BACKUP_ALM2_TIME = alarmTimeBcd;
+ BACKUP_ALM2_DATE = alarmDateBcd;
+ }
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_IP_MXS40SRSS_RTC */
+
+#endif /* CY_RTC_H */
+
+/** \} group_rtc_low_level_functions */
+/** \} group_rtc */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_scb_common.h b/platform/ext/target/psoc64/Native_Driver/include/cy_scb_common.h
new file mode 100644
index 0000000000..d8f30c116b
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_scb_common.h
@@ -0,0 +1,1983 @@
+/***************************************************************************//**
+* \file cy_scb_common.h
+* \version 2.30.1
+*
+* Provides common API declarations of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb
+* \{
+* The Serial Communications Block (SCB) supports three serial communication
+* protocols: Serial Peripheral Interface (SPI), Universal Asynchronous Receiver
+* Transmitter (UART), and Inter Integrated Circuit (I2C or IIC). Only one of
+* the protocols is supported by an SCB at any given time.
+*
+* The functions and other declarations used in this driver are in cy_scb_spi.h,
+* cy_scb_uart.h, cy_scb_ezi2c.h, cy_scb_i2c.h respectively. Include cy_pdl.h
+* (ModusToolbox only) to get access to all functions and declarations in the PDL.
+
+* \defgroup group_scb_common Common
+* \defgroup group_scb_ezi2c EZI2C (SCB)
+* \defgroup group_scb_i2c I2C (SCB)
+* \defgroup group_scb_spi SPI (SCB)
+* \defgroup group_scb_uart UART (SCB)
+* \} */
+
+/**
+* \addtogroup group_scb
+* \{
+*
+********************************************************************************
+* \section group_scb_more_information More Information
+********************************************************************************
+* For more information on the SCB peripheral, refer to the technical reference
+* manual (TRM).
+*
+*******************************************************************************
+* \section group_scb_common_MISRA MISRA-C Compliance
+*******************************************************************************
+* <table class="doxtable">
+* <tr>
+* <th>MISRA rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to object type and
+* a different pointer to object type.</td>
+* <td>
+* * The pointer to the buffer memory is void to allow handling of
+* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits).
+* The cast operation is safe because the configuration is verified
+* before operation is performed.
+* * The functions \ref Cy_SCB_I2C_DeepSleepCallback and
+* \ref Cy_SCB_I2C_HibernateCallback are callback of
+* \ref cy_en_syspm_status_t type. The cast operation safety in these
+* functions becomes the user's responsibility because pointers are
+* initialized when callback is registered in SysPm driver.
+* * The functions \ref Cy_SCB_EZI2C_DeepSleepCallback and
+* \ref Cy_SCB_EZI2C_HibernateCallback are callback of
+* \ref cy_en_syspm_status_t type. The cast operation safety in these
+* functions becomes the user's responsibility because pointers are
+* initialized when callback is registered in SysPm driver.
+* * The functions \ref Cy_SCB_UART_DeepSleepCallback and
+* \ref Cy_SCB_UART_HibernateCallback are callback of
+* \ref cy_en_syspm_status_t type. The cast operation safety in these
+* functions becomes the user's responsibility because pointers are
+* initialized when callback is registered in SysPm driver.
+* * The functions \ref Cy_SCB_SPI_DeepSleepCallback and
+* \ref Cy_SCB_SPI_HibernateCallback are callback of
+* \ref cy_en_syspm_status_t type. The cast operation safety in these
+* functions becomes the user's responsibility because pointers are
+* initialized when callback is registered in SysPm driver.
+* </td>
+* </tr>
+* <tr>
+* <td>14.1</td>
+* <td>R</td>
+* <td>There shall be no unreachable code.</td>
+* <td>The SCB block parameters can be a constant false or true depends on
+* the selected device and cause code to be unreachable.</td>
+* </tr>
+* <tr>
+* <td>14.2</td>
+* <td>R</td>
+* <td>All non-null statements shall either: a) have at least one side-effect
+* however executed, or b) cause control flow to change.</td>
+* <td>The unused function parameters are cast to void. This statement
+* has no side-effect and is used to suppress a compiler warning.</td>
+* </tr>
+* <tr>
+* <td>14.7</td>
+* <td>R</td>
+* <td>A function shall have a single point of exit at the end of the
+* function.</td>
+* <td>The functions can return from several points. This is done to improve
+* code clarity when returning error status code if input parameters
+* validation fails.</td>
+* </tr>
+* <tr>
+* <td>13.7</td>
+* <td>R</td>
+* <td>Boolean operations whose results are invariant shall not be
+* permitted.</td>
+* <td>
+* * The SCB block parameters can be a constant false or true depends on
+* the selected device and cause this violation.
+* * The same condition check is executed before and after callback is
+* called because after the callback returns, the condition might be not
+* true any more.</td>
+* </tr>
+* </table>
+*
+*******************************************************************************
+* \section group_scb_common_changelog Changelog
+*******************************************************************************
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.30.1</td>
+* <td>Added header guards CY_IP_MXSCB.</td>
+* <td>To enable the PDL compilation with wounded out IP blocks.</td>
+* </tr>
+* <tr>
+* <td rowspan="5">2.30</td>
+* <td>Fixed MISRA violation.</td>
+* <td>MISRA compliance.</td>
+* </tr>
+* <tr>
+* <td>Changed values CY_SCB_SPI_CPHA0_CPOL1 and CY_SCB_SPI_CPHA1_CPOL0 in enum \ref cy_en_scb_spi_sclk_mode_t.</td>
+* <td>The incorrect values in \ref cy_en_scb_spi_sclk_mode_t caused incorrect initialization of the combination of
+* phases and polarity: "CHPA = 0, CPOL = 1" and "CHPA = 1, CPOL = 0".
+* </td>
+* </tr>
+* <tr>
+* <td>Added new CY_SCB_UART_RECEIVE_NOT_EMTPY and CY_SCB_UART_TRANSMIT_EMTPY callback events \ref group_scb_uart_macros_callback_events.</td>
+* <td>Extended the driver callback events to support the MBED-OS.</td>
+* </tr>
+* <tr>
+* <td>Merged SCB changelogs for each mode into one changelog.</td>
+* <td>Changelog optimization.</td>
+* </tr>
+* <tr>
+* <td>Merged SCB MISRA-C Compliance sections for each mode into one section.</td>
+* <td>To optimize the SCB MISRA-C Compliance sections.</td>
+* </tr>
+* <tr>
+* <td> 2.20.1</td>
+* <td>Documentation of the MISRA rule violation.</td>
+* <td>MISRA compliance.</td>
+* </tr>
+* <tr>
+* <td rowspan="4">2.20</td>
+* <td>Flattened the organization of the driver source code into the single
+* source directory and the single include directory.
+* </td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>Added the enableDigitalFilter, highPhaseDutyCycle and lowPhaseDutyCycle
+* fields to the \ref cy_stc_scb_i2c_config_t configuration structure.
+* </td>
+* <td>Added the I2C master data rate configuration using the configuration structure.
+* </td>
+* </tr>
+* <tr>
+* <td>Fixed the \ref Cy_SCB_I2C_SetDataRate function to properly configure data rates
+* greater than 400 kbps in Master and Master-Slave modes. \n
+* Added verification that clk_scb is within the valid range for the desired data rate.
+* </td>
+* <td>The analog filter was enabled for all data rates in Master and Master-Slave modes.
+* This prevents reaching the maximum supported data rate of 1000 kbps which requires a digital filter.
+* </td>
+* </tr>
+* <tr>
+* <td rowspan="4"> 2.10</td>
+* <td>Fixed the ReStart condition generation sequence for a write
+* transaction in the \ref Cy_SCB_I2C_MasterWrite function.</td>
+* <td>The driver can notify about a zero length write transaction completion
+* before the address byte is sent if the \ref Cy_SCB_I2C_MasterWrite
+* function execution was interrupted between setting the restart
+* generation command and writing the address byte into the TX FIFO.</td>
+* </tr>
+* <tr>
+* <td>Added the slave- and master-specific interrupt functions:
+* \ref Cy_SCB_I2C_SlaveInterrupt and \ref Cy_SCB_I2C_MasterInterrupt.
+* </td>
+* <td>Improved the interrupt configuration options for the I2C slave and
+* master mode configurations.</td>
+* </tr>
+* <tr>
+* <td>Updated the Start condition generation sequence in the \ref
+* Cy_SCB_I2C_MasterWrite and \ref Cy_SCB_I2C_MasterRead.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Updated the ReStart condition generation sequence for a write
+* transaction in the \ref Cy_SCB_I2C_MasterSendReStart function.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td rowspan="9"> 2.0</td>
+* <td>Added parameters validation for public API.
+* <td></td>
+* </tr>
+* <tr>
+* <td>Fixed functions which return interrupt status to return only defined
+* set of interrupt statuses.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Added missing "cy_cb_" to the callback function type names.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Replaced variables that have limited range of values with enumerated
+* types.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Added function \ref Cy_SCB_UART_SendBreakBlocking for break condition
+* generation.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Fixed low power callbacks \ref Cy_SCB_UART_DeepSleepCallback and
+* \ref Cy_SCB_UART_HibernateCallback to prevent the device from entering
+* low power mode when RX FIFO is not empty.</td>
+* <td>The callbacks allowed entering device into low power mode when RX FIFO
+* had data.</td>
+* </tr>
+* <tr>
+* <td>Fixed SPI callback notification when error event occurred.</td>
+* <td>The SPI callback passed incorrect event value if error event occurred.</td>
+* </tr>
+* <tr>
+* <td>Fixed the \ref Cy_SCB_I2C_MasterSendReStart function to properly
+* generate the ReStart condition when the previous transaction was
+* a write.</td>
+* <td>The master interpreted the address byte written into the TX FIFO as a
+* data byte and continued a write transaction. The ReStart condition was
+* generated after the master completed transferring the data byte.
+* The SCL line was stretched by the master waiting for the address byte
+* to be written into the TX FIFO after the ReStart condition generation.
+* The following timeout detection released the bus from the master
+* control.</td>
+* </tr>
+* <tr>
+* <td>Fixed the slave operation after the address byte was NACKed by the
+* firmware.</td>
+* <td>The observed slave operation failure depends on whether Level 2 assert
+* is enabled or not. Enabled: the device stuck in the fault handler due
+* to the assert assignment in the \ref Cy_SCB_I2C_Interrupt. Disabled:
+* the slave sets the transaction completion status and notifies on the
+* transaction completion event after the address was NACKed. The failure
+* is observed only when the slave is configured to accept an address in
+* the RX FIFO.</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version.</td>
+* <td></td>
+* </tr>
+* </table>
+*/
+
+/** \} group_scb */
+/**
+* \addtogroup group_scb_common
+* \{
+*
+* Common API for the Serial Communication Block.
+*
+* This is the common API that provides an interface to the SCB hardware.
+* The I2C, SPI, and UART drivers use this common API.
+* Most users will use individual drivers and do not need to use the common
+* API for the SCB. However, you can use the common SCB API to implement
+* a custom driver based on the SCB hardware.
+*
+* The functions and other declarations used in this part of the driver are in
+* cy_scb_common.h. You can include either of cy_scb_spi.h, cy_scb_uart.h,
+* cy_scb_ezi2c.h, cy_scb_i2c.h depending on the desired functionality.
+* You can also include cy_pdl.h to get access to all functions and declarations
+* in the PDL.
+*
+*******************************************************************************
+* \section group_scb_common_configuration Configuration Considerations
+********************************************************************************
+* This is not a driver and it does not require configuration.
+*
+* \defgroup group_scb_common_macros Macros
+* \defgroup group_scb_common_functions Functions
+* \defgroup group_scb_common_data_structures Data Structures
+*
+*/
+
+#if !defined(CY_SCB_COMMON_H)
+#define CY_SCB_COMMON_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include "cy_syspm.h"
+
+#ifdef CY_IP_MXSCB
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_common_functions
+* \{
+*/
+__STATIC_INLINE uint32_t Cy_SCB_ReadRxFifo (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t level);
+__STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearRxFifo (CySCB_Type *base);
+
+__STATIC_INLINE void Cy_SCB_WriteTxFifo (CySCB_Type *base, uint32_t data);
+__STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t level);
+__STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid (CySCB_Type const *base);
+__STATIC_INLINE bool Cy_SCB_IsTxComplete (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearTxFifo (CySCB_Type *base);
+
+__STATIC_INLINE void Cy_SCB_SetByteMode(CySCB_Type *base, bool byteMode);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetInterruptCause(CySCB_Type const *base);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatus(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetRxInterruptMask (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptMask (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearRxInterrupt (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE void Cy_SCB_SetRxInterrupt (CySCB_Type *base, uint32_t interruptMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatus(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetTxInterruptMask (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptMask (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearTxInterrupt (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE void Cy_SCB_SetTxInterrupt (CySCB_Type *base, uint32_t interruptMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatus(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetMasterInterruptMask (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptMask (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearMasterInterrupt (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE void Cy_SCB_SetMasterInterrupt (CySCB_Type *base, uint32_t interruptMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetSlaveInterruptMask (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptMask (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearSlaveInterrupt (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE void Cy_SCB_SetSlaveInterrupt (CySCB_Type *base, uint32_t interruptMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatus(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetI2CInterruptMask (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptMask (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearI2CInterrupt (CySCB_Type *base, uint32_t interruptMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatus(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetSpiInterruptMask (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptMask (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearSpiInterrupt (CySCB_Type *base, uint32_t interruptMask);
+
+
+/*******************************************************************************
+* Internal Function Prototypes
+*******************************************************************************/
+
+/** \cond INTERNAL */
+void Cy_SCB_ReadArrayNoCheck (CySCB_Type const *base, void *buffer, uint32_t size);
+uint32_t Cy_SCB_ReadArray (CySCB_Type const *base, void *buffer, uint32_t size);
+void Cy_SCB_ReadArrayBlocking (CySCB_Type const *base, void *buffer, uint32_t size);
+uint32_t Cy_SCB_Write (CySCB_Type *base, uint32_t data);
+void Cy_SCB_WriteArrayNoCheck (CySCB_Type *base, void *buffer, uint32_t size);
+uint32_t Cy_SCB_WriteArray (CySCB_Type *base, void *buffer, uint32_t size);
+void Cy_SCB_WriteArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size);
+void Cy_SCB_WriteString (CySCB_Type *base, char_t const string[]);
+void Cy_SCB_WriteDefaultArrayNoCheck(CySCB_Type *base, uint32_t txData, uint32_t size);
+uint32_t Cy_SCB_WriteDefaultArray (CySCB_Type *base, uint32_t txData, uint32_t size);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetFifoSize (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_FwBlockReset(CySCB_Type *base);
+__STATIC_INLINE bool Cy_SCB_IsRxDataWidthByte(CySCB_Type const *base);
+__STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel (CySCB_Type const *base);
+/** \endcond */
+
+/** \} group_scb_common_functions */
+
+
+/*******************************************************************************
+* API Constants
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_common_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_SCB_DRV_VERSION_MAJOR (2)
+
+/** Driver minor version */
+#define CY_SCB_DRV_VERSION_MINOR (30)
+
+/** SCB driver identifier */
+#define CY_SCB_ID CY_PDL_DRV_ID(0x2AU)
+
+/** Position for SCB driver sub mode */
+#define CY_SCB_SUB_MODE_Pos (13UL)
+
+/** EZI2C mode identifier */
+#define CY_SCB_EZI2C_ID (0x0UL << CY_SCB_SUB_MODE_Pos)
+
+/** EZI2C mode identifier */
+#define CY_SCB_I2C_ID (0x1UL << CY_SCB_SUB_MODE_Pos)
+
+/** EZI2C mode identifier */
+#define CY_SCB_SPI_ID (0x2UL << CY_SCB_SUB_MODE_Pos)
+
+/** EZI2C mode identifier */
+#define CY_SCB_UART_ID (0x3UL << CY_SCB_SUB_MODE_Pos)
+
+/**
+* \defgroup group_scb_common_macros_intr_cause SCB Interrupt Causes
+* \{
+*/
+/** Interrupt from Master interrupt sources */
+#define CY_SCB_MASTER_INTR SCB_INTR_CAUSE_M_Msk
+
+/** Interrupt from Slave interrupt sources */
+#define CY_SCB_SLAVE_INTR SCB_INTR_CAUSE_S_Msk
+
+/** Interrupt from TX interrupt sources */
+#define CY_SCB_TX_INTR SCB_INTR_CAUSE_TX_Msk
+
+/** Interrupt from RX interrupt sources */
+#define CY_SCB_RX_INTR SCB_INTR_CAUSE_RX_Msk
+
+/** Interrupt from I2C externally clocked interrupt sources */
+#define CY_SCB_I2C_INTR SCB_INTR_CAUSE_I2C_EC_Msk
+
+/** Interrupt from SPI externally clocked interrupt sources */
+#define CY_SCB_SPI_INTR SCB_INTR_CAUSE_SPI_EC_Msk
+/** \} group_scb_common_macros_intr_cause */
+
+/**
+* \defgroup group_scb_common_macros_tx_intr TX Interrupt Statuses
+* \{
+*/
+/**
+* The number of data elements in the TX FIFO is less than the value
+* of the TX FIFO level
+*/
+#define CY_SCB_TX_INTR_LEVEL SCB_INTR_TX_TRIGGER_Msk
+
+/** The TX FIFO is not full */
+#define CY_SCB_TX_INTR_NOT_FULL SCB_INTR_TX_NOT_FULL_Msk
+
+/** The TX FIFO is empty */
+#define CY_SCB_TX_INTR_EMPTY SCB_INTR_TX_EMPTY_Msk
+
+/** An attempt to write to a full TX FIFO */
+#define CY_SCB_TX_INTR_OVERFLOW SCB_INTR_TX_OVERFLOW_Msk
+
+/** An attempt to read from an empty TX FIFO */
+#define CY_SCB_TX_INTR_UNDERFLOW SCB_INTR_TX_UNDERFLOW_Msk
+
+/** The UART transfer is complete: all data elements from the TX FIFO are sent
+*/
+#define CY_SCB_TX_INTR_UART_DONE SCB_INTR_TX_UART_DONE_Msk
+
+/** SmartCard only: UART received a NACK */
+#define CY_SCB_TX_INTR_UART_NACK SCB_INTR_TX_UART_NACK_Msk
+
+/**
+* SmartCard only: the value on the TX line of the UART does not match the
+* value on the RX line
+*/
+#define CY_SCB_TX_INTR_UART_ARB_LOST SCB_INTR_TX_UART_ARB_LOST_Msk
+/** \} group_scb_common_macros_tx_intr */
+
+/**
+* \defgroup group_scb_common_macros_rx_intr RX Interrupt Statuses
+* \{
+*/
+/**
+* The number of data elements in the RX FIFO is greater than the value of the
+* RX FIFO level
+*/
+#define CY_SCB_RX_INTR_LEVEL SCB_INTR_RX_TRIGGER_Msk
+
+/** The RX FIFO is not empty */
+#define CY_SCB_RX_INTR_NOT_EMPTY SCB_INTR_RX_NOT_EMPTY_Msk
+
+/** The RX FIFO is full */
+#define CY_SCB_RX_INTR_FULL SCB_INTR_RX_FULL_Msk
+
+/** An attempt to write to a full RX FIFO */
+#define CY_SCB_RX_INTR_OVERFLOW SCB_INTR_RX_OVERFLOW_Msk
+
+/** An attempt to read from an empty RX FIFO */
+#define CY_SCB_RX_INTR_UNDERFLOW SCB_INTR_RX_UNDERFLOW_Msk
+
+/** A UART framing error detected */
+#define CY_SCB_RX_INTR_UART_FRAME_ERROR SCB_INTR_RX_FRAME_ERROR_Msk
+
+/** A UART parity error detected */
+#define CY_SCB_RX_INTR_UART_PARITY_ERROR SCB_INTR_RX_PARITY_ERROR_Msk
+
+/** A UART break detected */
+#define CY_SCB_RX_INTR_UART_BREAK_DETECT SCB_INTR_RX_BREAK_DETECT_Msk
+/** \} group_scb_common_macros_rx_intr */
+
+/**
+* \defgroup group_scb_common_macros_slave_intr Slave Interrupt Statuses
+* \{
+*/
+/**
+* I2C slave lost arbitration: the value driven on the SDA line is not the same
+* as the value observed on the SDA line
+*/
+#define CY_SCB_SLAVE_INTR_I2C_ARB_LOST SCB_INTR_S_I2C_ARB_LOST_Msk
+
+/** The I2C slave received a NAK */
+#define CY_SCB_SLAVE_INTR_I2C_NACK SCB_INTR_S_I2C_NACK_Msk
+
+/** The I2C slave received an ACK */
+#define CY_SCB_SLAVE_INTR_I2C_ACK SCB_INTR_S_I2C_ACK_Msk
+
+/**
+* A Stop or Repeated Start event for a write transfer intended for this slave
+* was detected.
+*/
+#define CY_SCB_SLAVE_INTR_I2C_WRITE_STOP SCB_INTR_S_I2C_WRITE_STOP_Msk
+
+/** A Stop or Repeated Start event intended for this slave was detected */
+#define CY_SCB_SLAVE_INTR_I2C_STOP SCB_INTR_S_I2C_STOP_Msk
+
+/** The I2C slave received a Start condition */
+#define CY_SCB_SLAVE_INTR_I2C_START SCB_INTR_S_I2C_START_Msk
+
+/** The I2C slave received the matching address */
+#define CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH SCB_INTR_S_I2C_ADDR_MATCH_Msk
+
+/** The I2C Slave received the general call address */
+#define CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR SCB_INTR_S_I2C_GENERAL_Msk
+
+/** The I2C slave bus error (detection of unexpected Start or Stop condition) */
+#define CY_SCB_SLAVE_INTR_I2C_BUS_ERROR SCB_INTR_S_I2C_BUS_ERROR_Msk
+
+/**
+* The SPI slave select line is deselected at an expected time during an
+* SPI transfer.
+*/
+#define CY_SCB_SLAVE_INTR_SPI_BUS_ERROR SCB_INTR_S_SPI_BUS_ERROR_Msk
+/** \} group_scb_common_macros_slave_intr */
+
+/**
+* \defgroup group_scb_common_macros_master_intr Master Interrupt Statuses
+* \{
+*/
+/** The I2C master lost arbitration */
+#define CY_SCB_MASTER_INTR_I2C_ARB_LOST SCB_INTR_M_I2C_ARB_LOST_Msk
+
+/** The I2C master received a NACK */
+#define CY_SCB_MASTER_INTR_I2C_NACK SCB_INTR_M_I2C_NACK_Msk
+
+/** The I2C master received an ACK */
+#define CY_SCB_MASTER_INTR_I2C_ACK SCB_INTR_M_I2C_ACK_Msk
+
+/** The I2C master generated a Stop */
+#define CY_SCB_MASTER_INTR_I2C_STOP SCB_INTR_M_I2C_STOP_Msk
+
+/** The I2C master bus error (detection of unexpected START or STOP condition)
+*/
+#define CY_SCB_MASTER_INTR_I2C_BUS_ERROR SCB_INTR_M_I2C_BUS_ERROR_Msk
+
+/**
+* The SPI master transfer is complete: all data elements transferred from the
+* TX FIFO and TX shift register.
+*/
+#define CY_SCB_MASTER_INTR_SPI_DONE SCB_INTR_M_SPI_DONE_Msk
+/** \} group_scb_common_macros_master_intr */
+
+/**
+* \defgroup group_scb_common_macros_i2c_intr I2C Interrupt Statuses
+* \{
+*/
+/**
+* Wake up request: the I2C slave received the matching address.
+* Note that this interrupt source triggers in active mode.
+*/
+#define CY_SCB_I2C_INTR_WAKEUP SCB_INTR_I2C_EC_WAKE_UP_Msk
+/** \} group_scb_common_macros_i2c_intr */
+
+/**
+* \defgroup group_scb_common_macros_SpiIntrStatuses SPI Interrupt Statuses
+* \{
+*/
+/**
+* Wake up request: the SPI slave detects an active edge of the slave select
+* signal. Note that this interrupt source triggers in active mode.
+*/
+#define CY_SCB_SPI_INTR_WAKEUP SCB_INTR_SPI_EC_WAKE_UP_Msk
+/** \} group_scb_common_macros_SpiIntrStatuses */
+
+
+/*******************************************************************************
+* Internal Constants
+*******************************************************************************/
+
+/** \cond INTERNAL */
+
+/* Default registers values */
+#define CY_SCB_CTRL_DEF_VAL (_VAL2FLD(SCB_CTRL_OVS, 15UL) | \
+ _VAL2FLD(SCB_CTRL_MODE, 3UL))
+
+#define CY_SCB_I2C_CTRL_DEF_VAL (_VAL2FLD(SCB_I2C_CTRL_HIGH_PHASE_OVS, 8UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_HIGH_PHASE_OVS, 8UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_M_READY_DATA_ACK, 1UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_M_NOT_READY_DATA_NACK, 1UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_S_GENERAL_IGNORE, 1UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_S_READY_ADDR_ACK, 1UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_S_READY_DATA_ACK, 1UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK, 1UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_S_NOT_READY_DATA_NACK, 1UL))
+
+#define CY_SCB_I2C_CFG_DEF_VAL (_VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_TRIM, 3UL) | \
+ _VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_SEL, 1UL) | \
+ _VAL2FLD(SCB_I2C_CFG_SCL_IN_FILT_SEL, 1UL) | \
+ _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT0_TRIM, 2UL) | \
+ _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT1_TRIM, 2UL) | \
+ _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT2_TRIM, 2UL))
+
+#define CY_SCB_SPI_CTRL_DEF_VAL _VAL2FLD(SCB_SPI_CTRL_MODE, 3UL)
+#define CY_SCB_UART_CTRL_DEF_VAL _VAL2FLD(SCB_UART_CTRL_MODE, 3UL)
+
+#define CY_SCB_UART_RX_CTRL_DEF_VAL (_VAL2FLD(SCB_UART_RX_CTRL_STOP_BITS, 2UL) | \
+ _VAL2FLD(SCB_UART_RX_CTRL_BREAK_WIDTH, 10UL))
+
+#define CY_SCB_UART_TX_CTRL_DEF_VAL _VAL2FLD(SCB_UART_TX_CTRL_STOP_BITS, 2UL)
+
+#define CY_SCB_RX_CTRL_DEF_VAL (_VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, 7UL) | \
+ _VAL2FLD(SCB_RX_CTRL_MSB_FIRST, 1UL))
+
+#define CY_SCB_TX_CTRL_DEF_VAL (_VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, 7UL) | \
+ _VAL2FLD(SCB_TX_CTRL_MSB_FIRST, 1UL))
+
+/* SCB CTRL modes */
+#define CY_SCB_CTRL_MODE_I2C (0UL)
+#define CY_SCB_CTRL_MODE_SPI (1UL)
+#define CY_SCB_CTRL_MODE_UART (2UL)
+
+/* The position and mask to set the I2C mode */
+#define CY_SCB_I2C_CTRL_MODE_Pos SCB_I2C_CTRL_SLAVE_MODE_Pos
+#define CY_SCB_I2C_CTRL_MODE_Msk (SCB_I2C_CTRL_SLAVE_MODE_Msk | \
+ SCB_I2C_CTRL_MASTER_MODE_Msk)
+
+/* Cypress ID #282226:
+* SCB_I2C_CFG_SDA_IN_FILT_TRIM[1]: SCB clock enable (1), clock disable (0).
+*/
+#define CY_SCB_I2C_CFG_CLK_ENABLE_Msk (_VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_TRIM, 2UL))
+
+/* I2C has fixed data width */
+#define CY_SCB_I2C_DATA_WIDTH (7UL)
+
+/* RX and TX control register values */
+#define CY_SCB_I2C_RX_CTRL (_VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, CY_SCB_I2C_DATA_WIDTH) | \
+ SCB_RX_CTRL_MSB_FIRST_Msk)
+#define CY_SCB_I2C_TX_CTRL (_VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, CY_SCB_I2C_DATA_WIDTH) | \
+ SCB_TX_CTRL_MSB_FIRST_Msk | SCB_TX_CTRL_OPEN_DRAIN_Msk)
+
+/* The position and mask to make an address byte */
+#define CY_SCB_I2C_ADDRESS_Pos (1UL)
+#define CY_SCB_I2C_ADDRESS_Msk (0xFEUL)
+
+/* SPI slave select polarity */
+#define CY_SCB_SPI_CTRL_SSEL_POLARITY_Pos SCB_SPI_CTRL_SSEL_POLARITY0_Pos
+#define CY_SCB_SPI_CTRL_SSEL_POLARITY_Msk (SCB_SPI_CTRL_SSEL_POLARITY0_Msk | \
+ SCB_SPI_CTRL_SSEL_POLARITY1_Msk | \
+ SCB_SPI_CTRL_SSEL_POLARITY2_Msk | \
+ SCB_SPI_CTRL_SSEL_POLARITY3_Msk)
+
+/* SPI clock modes: CPHA and CPOL */
+#define CY_SCB_SPI_CTRL_CLK_MODE_Pos SCB_SPI_CTRL_CPHA_Pos
+#define CY_SCB_SPI_CTRL_CLK_MODE_Msk (SCB_SPI_CTRL_CPHA_Msk | SCB_SPI_CTRL_CPOL_Msk)
+
+/* UART parity and parity enable combination */
+#define CY_SCB_UART_RX_CTRL_SET_PARITY_Msk (SCB_UART_RX_CTRL_PARITY_ENABLED_Msk | \
+ SCB_UART_RX_CTRL_PARITY_Msk)
+#define CY_SCB_UART_RX_CTRL_SET_PARITY_Pos SCB_UART_RX_CTRL_PARITY_Pos
+
+#define CY_SCB_UART_TX_CTRL_SET_PARITY_Msk (SCB_UART_TX_CTRL_PARITY_ENABLED_Msk | \
+ SCB_UART_TX_CTRL_PARITY_Msk)
+#define CY_SCB_UART_TX_CTRL_SET_PARITY_Pos SCB_UART_TX_CTRL_PARITY_Pos
+
+/* Max number of bits for byte mode */
+#define CY_SCB_BYTE_WIDTH (8UL)
+
+/* Single unit to wait */
+#define CY_SCB_WAIT_1_UNIT (1U)
+
+/* Clear interrupt sources */
+#define CY_SCB_CLEAR_ALL_INTR_SRC (0UL)
+
+/* Hardware FIFO size: EZ_DATA_NR / 4 = (512 / 4) = 128 */
+#define CY_SCB_FIFO_SIZE (128UL)
+
+/* Provides a list of allowed sources */
+#define CY_SCB_TX_INTR_MASK (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_NOT_FULL | CY_SCB_TX_INTR_EMPTY | \
+ CY_SCB_TX_INTR_OVERFLOW | CY_SCB_TX_INTR_UNDERFLOW | CY_SCB_TX_INTR_UART_DONE | \
+ CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INTR_UART_ARB_LOST)
+
+#define CY_SCB_RX_INTR_MASK (CY_SCB_RX_INTR_LEVEL | CY_SCB_RX_INTR_NOT_EMPTY | CY_SCB_RX_INTR_FULL | \
+ CY_SCB_RX_INTR_OVERFLOW | CY_SCB_RX_INTR_UNDERFLOW | \
+ CY_SCB_RX_INTR_UART_FRAME_ERROR | CY_SCB_RX_INTR_UART_PARITY_ERROR | \
+ CY_SCB_RX_INTR_UART_BREAK_DETECT)
+
+
+#define CY_SCB_SLAVE_INTR_MASK (CY_SCB_SLAVE_INTR_I2C_ARB_LOST | CY_SCB_SLAVE_INTR_I2C_NACK | CY_SCB_SLAVE_INTR_I2C_ACK | \
+ CY_SCB_SLAVE_INTR_I2C_WRITE_STOP | CY_SCB_SLAVE_INTR_I2C_STOP | CY_SCB_SLAVE_INTR_I2C_START | \
+ CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR | \
+ CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_SPI_BUS_ERROR)
+
+#define CY_SCB_MASTER_INTR_MASK (CY_SCB_MASTER_INTR_I2C_ARB_LOST | CY_SCB_MASTER_INTR_I2C_NACK | \
+ CY_SCB_MASTER_INTR_I2C_ACK | CY_SCB_MASTER_INTR_I2C_STOP | \
+ CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_SPI_DONE)
+
+#define CY_SCB_I2C_INTR_MASK CY_SCB_I2C_INTR_WAKEUP
+
+#define CY_SCB_SPI_INTR_MASK CY_SCB_SPI_INTR_WAKEUP
+
+#define CY_SCB_IS_INTR_VALID(intr, mask) ( 0UL == ((intr) & ((uint32_t) ~(mask))) )
+#define CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level) ((level) < Cy_SCB_GetFifoSize(base))
+
+#define CY_SCB_IS_I2C_ADDR_VALID(addr) ( (0U == ((addr) & 0x80U)) )
+#define CY_SCB_IS_BUFFER_VALID(buffer, size) ( (NULL != (buffer)) && ((size) > 0UL) )
+#define CY_SCB_IS_I2C_BUFFER_VALID(buffer, size) ( (0UL == (size)) ? true : (NULL != (buffer)) )
+/** \endcond */
+
+/** \} group_scb_common_macros */
+
+
+/*******************************************************************************
+* In-line Function Implementation
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_common_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ReadRxFifo
+****************************************************************************//**
+*
+* Reads a data element directly out of the RX FIFO.
+* This function does not check whether the RX FIFO has data before reading it.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Data from RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_ReadRxFifo(CySCB_Type const *base)
+{
+ return (SCB_RX_FIFO_RD(base));
+}
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetRxFifoLevel
+****************************************************************************//**
+*
+* Sets the RX FIFO level. When there are more data elements in the RX FIFO than
+* this level, the RX FIFO level interrupt is triggered.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param level
+* When there are more data elements in the FIFO than this level, the RX level
+* interrupt is triggered.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t level)
+{
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level));
+
+ CY_REG32_CLR_SET(SCB_RX_FIFO_CTRL(base), SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, level);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetNumInRxFifo
+****************************************************************************//**
+*
+* Returns the number of data elements currently in the RX FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The number or data elements in RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base)
+{
+ return _FLD2VAL(SCB_RX_FIFO_STATUS_USED, SCB_RX_FIFO_STATUS(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetRxSrValid
+****************************************************************************//**
+*
+* Returns the status of the RX FIFO Shift Register valid bit.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* 1 - RX shift register valid; 0 - RX shift register not valid.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid(CySCB_Type const *base)
+{
+ return _FLD2VAL(SCB_RX_FIFO_STATUS_SR_VALID, SCB_RX_FIFO_STATUS(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearRxFifo
+****************************************************************************//**
+*
+* Clears the RX FIFO and shifter.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \note
+* If there is partial data in the shifter, it is cleared and lost.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearRxFifo(CySCB_Type* base)
+{
+ SCB_RX_FIFO_CTRL(base) |= (uint32_t) SCB_RX_FIFO_CTRL_CLEAR_Msk;
+ SCB_RX_FIFO_CTRL(base) &= (uint32_t) ~SCB_RX_FIFO_CTRL_CLEAR_Msk;
+
+ (void) SCB_RX_FIFO_CTRL(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteTxFifo
+****************************************************************************//**
+*
+* Writes data directly into the TX FIFO.
+* This function does not check whether the TX FIFO is not full before writing
+* into it.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param data
+* Data to write to the TX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_WriteTxFifo(CySCB_Type* base, uint32_t data)
+{
+ SCB_TX_FIFO_WR(base) = data;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetTxFifoLevel
+****************************************************************************//**
+*
+* Sets the TX FIFO level. When there are fewer data elements in the TX FIFO than
+* this level, the TX FIFO level interrupt is triggered.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param level
+* When there are fewer data elements in the FIFO than this level, the TX level
+* interrupt is triggered.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t level)
+{
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level));
+
+ CY_REG32_CLR_SET(SCB_TX_FIFO_CTRL(base), SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, level);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetNumInTxFifo
+****************************************************************************//**
+*
+* Returns the number of data elements currently in the TX FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The number or data elements in the TX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base)
+{
+ return _FLD2VAL(SCB_TX_FIFO_STATUS_USED, SCB_TX_FIFO_STATUS(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetTxSrValid
+****************************************************************************//**
+*
+* Returns the status of the TX FIFO Shift Register valid bit.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* 1 - TX shift register valid; 0 - TX shift register not valid.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid(CySCB_Type const *base)
+{
+ return _FLD2VAL(SCB_TX_FIFO_STATUS_SR_VALID, SCB_TX_FIFO_STATUS(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_IsTxComplete
+****************************************************************************//**
+*
+* Checks whether the TX FIFO and Shifter are empty and there is no more data to send.
+*
+* \param base
+* Pointer to SPI the SCB instance.
+*
+* \return
+* If true, transmission complete. If false, transmission is not complete.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SCB_IsTxComplete(CySCB_Type const *base)
+{
+ return (0UL == (Cy_SCB_GetNumInTxFifo(base) + Cy_SCB_GetTxSrValid(base)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearTxFifo
+****************************************************************************//**
+*
+* Clears the TX FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \note
+* The TX FIFO clear operation also clears the shift register. Thus the shifter
+* could be cleared in the middle of a data element transfer. Thia results in
+* "ones" being sent on the bus for the remainder of the transfer.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearTxFifo(CySCB_Type *base)
+{
+ SCB_TX_FIFO_CTRL(base) |= (uint32_t) SCB_TX_FIFO_CTRL_CLEAR_Msk;
+ SCB_TX_FIFO_CTRL(base) &= (uint32_t) ~SCB_TX_FIFO_CTRL_CLEAR_Msk;
+
+ (void) SCB_TX_FIFO_CTRL(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetByteMode
+****************************************************************************//**
+*
+* Sets whether the RX and TX FIFOs are in byte mode.
+* The FIFOs are either 16-bit wide or 8-bit wide (byte mode).
+* When the FIFO is in byte mode it is twice as deep. See the device datasheet
+* for FIFO depths.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param byteMode
+* If true, TX and RX FIFOs are 8-bit wide. If false, the FIFOs are 16-bit wide.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetByteMode(CySCB_Type *base, bool byteMode)
+{
+ if (byteMode)
+ {
+ SCB_CTRL(base) |= SCB_CTRL_BYTE_MODE_Msk;
+ }
+ else
+ {
+ SCB_CTRL(base) &= ~SCB_CTRL_BYTE_MODE_Msk;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetInterruptCause
+****************************************************************************//**
+*
+* Returns the mask of bits showing the source of the current triggered
+* interrupt. This is useful for modes of operation where an interrupt can
+* be generated by conditions in multiple interrupt source registers.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The mask with the OR of the following conditions that have been triggered.
+* See \ref group_scb_common_macros_intr_cause for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetInterruptCause(CySCB_Type const *base)
+{
+ return (SCB_INTR_CAUSE(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetRxInterruptStatus
+****************************************************************************//**
+*
+* Returns the RX interrupt request register. This register contains the current
+* status of the RX interrupt sources.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of the RX interrupt sources. Each constant is a bit field
+* value. The value returned may have multiple bits set to indicate the
+* current status.
+* See \ref group_scb_common_macros_rx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatus(CySCB_Type const *base)
+{
+ return (SCB_INTR_RX(base) & CY_SCB_RX_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetRxInterruptMask
+****************************************************************************//**
+*
+* Writes the RX interrupt mask register. This register configures which bits
+* from the RX interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* Enabled RX interrupt sources.
+* See \ref group_scb_common_macros_rx_intr.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetRxInterruptMask(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
+
+ SCB_INTR_RX_MASK(base) = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetRxInterruptMask
+****************************************************************************//**
+*
+* Returns the RX interrupt mask register. This register specifies which bits
+* from the RX interrupt request register trigger can an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Enabled RX interrupt sources.
+* See \ref group_scb_common_macros_rx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptMask(CySCB_Type const *base)
+{
+ return (SCB_INTR_RX_MASK(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetRxInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the RX interrupt masked request register. This register contains
+* a logical AND of corresponding bits from the RX interrupt request and
+* mask registers.
+* This function is intended to be used in the interrupt service routine to
+* identify which of the enabled RX interrupt sources caused the interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of enabled RX interrupt sources.
+* See \ref group_scb_common_macros_rx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const *base)
+{
+ return (SCB_INTR_RX_MASKED(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearRxInterrupt
+****************************************************************************//**
+*
+* Clears the RX interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The RX interrupt sources to be cleared.
+* See \ref group_scb_common_macros_rx_intr for the set of constants.
+*
+* \note
+* - CY_SCB_INTR_RX_FIFO_LEVEL interrupt source is not cleared when
+* the RX FIFO has more entries than the level.
+* - CY_SCB_INTR_RX_NOT_EMPTY interrupt source is not cleared when the
+* RX FIFO is not empty.
+* - CY_SCB_INTR_RX_FULL interrupt source is not cleared when the
+* RX FIFO is full.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearRxInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
+
+ SCB_INTR_RX(base) = interruptMask;
+ (void) SCB_INTR_RX(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetRxInterrupt
+****************************************************************************//**
+*
+* Sets the RX interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The RX interrupt sources to set in the RX interrupt request register.
+* See \ref group_scb_common_macros_rx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetRxInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
+
+ SCB_INTR_RX_SET(base) = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetTxInterruptStatus
+****************************************************************************//**
+*
+* Returns the TX interrupt request register. This register contains the current
+* status of the TX interrupt sources.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of TX interrupt sources.
+* Each constant is a bit field value. The value returned may have multiple
+* bits set to indicate the current status.
+* See \ref group_scb_common_macros_tx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatus(CySCB_Type const *base)
+{
+ return (SCB_INTR_TX(base) & CY_SCB_TX_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetTxInterruptMask
+****************************************************************************//**
+*
+* Writes the TX interrupt mask register. This register configures which bits
+* from the TX interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* Enabled TX interrupt sources.
+* See \ref group_scb_common_macros_tx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetTxInterruptMask(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
+
+ SCB_INTR_TX_MASK(base) = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetTxInterruptMask
+****************************************************************************//**
+*
+* Returns the TX interrupt mask register. This register specifies which
+* bits from the TX interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Enabled TX interrupt sources.
+* See \ref group_scb_common_macros_tx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptMask(CySCB_Type const *base)
+{
+ return (SCB_INTR_TX_MASK(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetTxInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the TX interrupt masked request register. This register contains
+* a logical AND of corresponding bits from the TX interrupt request and
+* mask registers.
+* This function is intended to be used in the interrupt service routine to
+* identify which of enabled TX interrupt sources caused the interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of enabled TX interrupt sources.
+* See \ref group_scb_common_macros_tx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const *base)
+{
+ return (SCB_INTR_TX_MASKED(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearTxInterrupt
+****************************************************************************//**
+*
+* Clears the TX interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The TX interrupt sources to be cleared.
+* See \ref group_scb_common_macros_tx_intr for the set of constants.
+*
+* \note
+* - CY_SCB_INTR_TX_FIFO_LEVEL interrupt source is not cleared when the
+* TX FIFO has fewer entries than the TX level.
+* - CY_SCB_INTR_TX_NOT_FULL interrupt source is not cleared when the
+* TX FIFO has empty entries in the TX FIFO.
+* - CY_SCB_INTR_TX_EMPTY interrupt source is not cleared when the
+* TX FIFO is empty.
+* - CY_SCB_INTR_TX_UNDERFLOW interrupt source is not cleared when the
+* TX FIFO is empty. Put data into the TX FIFO before clearing it.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearTxInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
+
+ SCB_INTR_TX(base) = interruptMask;
+ (void) SCB_INTR_TX(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetTxInterrupt
+****************************************************************************//**
+*
+* Sets TX interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The TX interrupt sources to set in the TX interrupt request register.
+* See \ref group_scb_common_macros_tx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetTxInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
+
+ SCB_INTR_TX_SET(base) = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetMasterInterruptStatus
+****************************************************************************//**
+*
+* Returns the master interrupt request register. This register contains the current
+* status of the master interrupt sources.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of the master interrupt sources.
+* Each constant is a bit field value. The value returned may have multiple
+* bits set to indicate the current status.
+* See \ref group_scb_common_macros_master_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatus(CySCB_Type const *base)
+{
+ return (SCB_INTR_M(base) & CY_SCB_MASTER_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetMasterInterruptMask
+****************************************************************************//**
+*
+* Writes the master interrupt mask register. This register specifies which bits
+* from the master interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The master interrupt sources to be enable.
+* See \ref group_scb_common_macros_master_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetMasterInterruptMask(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
+
+ SCB_INTR_M_MASK(base) = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetMasterInterruptMask
+****************************************************************************//**
+*
+* Returns the master interrupt mask register. This register specifies which bits
+* from the master interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Enabled master interrupt sources.
+* See \ref group_scb_common_macros_master_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptMask(CySCB_Type const *base)
+{
+ return (SCB_INTR_M_MASK(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetMasterInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the master interrupt masked request register. This register contains a
+* logical AND of corresponding bits from the master interrupt request and mask
+* registers.
+* This function is intended to be used in the interrupt service routine to
+* identify which of the enabled master interrupt sources caused the interrupt
+* event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of enabled master interrupt sources.
+* See \ref group_scb_common_macros_master_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const *base)
+{
+ return (SCB_INTR_M_MASKED(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearMasterInterrupt
+****************************************************************************//**
+*
+* Clears master interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The master interrupt sources to be cleared.
+* See \ref group_scb_common_macros_master_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearMasterInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
+
+ SCB_INTR_M(base) = interruptMask;
+ (void) SCB_INTR_M(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetMasterInterrupt
+****************************************************************************//**
+*
+* Sets master interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The master interrupt sources to set in the master interrupt request register.
+* See \ref group_scb_common_macros_master_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetMasterInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
+
+ SCB_INTR_M_SET(base) = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetSlaveInterruptStatus
+****************************************************************************//**
+*
+* Returns the slave interrupt request register. This register contains the current
+* status of the slave interrupt sources.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of the slave interrupt sources.
+* Each constant is a bit field value. The value returned may have multiple
+* bits set to indicate the current status.
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const *base)
+{
+ return (SCB_INTR_S(base) & CY_SCB_SLAVE_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetSlaveInterruptMask
+****************************************************************************//**
+*
+* Writes slave interrupt mask register.
+* This register specifies which bits from the slave interrupt request register
+* can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* Enabled slave interrupt sources.
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetSlaveInterruptMask(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
+
+ SCB_INTR_S_MASK(base) = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetSlaveInterruptMask
+****************************************************************************//**
+*
+* Returns the slave interrupt mask register.
+* This register specifies which bits from the slave interrupt request register
+* can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Enabled slave interrupt sources.
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptMask(CySCB_Type const *base)
+{
+ return (SCB_INTR_S_MASK(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetSlaveInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the slave interrupt masked request register. This register contains a
+* logical AND of corresponding bits from the slave interrupt request and mask
+* registers.
+* This function is intended to be used in the interrupt service routine to
+* identify which of enabled slave interrupt sources caused the interrupt
+* event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of enabled slave interrupt sources.
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const *base)
+{
+ return (SCB_INTR_S_MASKED(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearSlaveInterrupt
+****************************************************************************//**
+*
+* Clears the slave interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* Slave interrupt sources to be cleared.
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearSlaveInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
+
+ SCB_INTR_S(base) = interruptMask;
+ (void) SCB_INTR_S(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetSlaveInterrupt
+****************************************************************************//**
+*
+* Sets slave interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The slave interrupt sources to set in the slave interrupt request register
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetSlaveInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
+
+ SCB_INTR_S_SET(base) = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetI2CInterruptStatus
+****************************************************************************//**
+*
+* Returns the I2C interrupt request register. This register contains the
+* current status of the I2C interrupt sources.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of the I2C interrupt sources. Each constant is a bit
+* field value.
+* The value returned may have multiple bits set to indicate the current status.
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatus(CySCB_Type const *base)
+{
+ return (SCB_INTR_I2C_EC(base) & CY_SCB_I2C_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetI2CInterruptMask
+****************************************************************************//**
+*
+* Writes the I2C interrupt mask register. This register specifies which bits
+* from the I2C interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* Enabled I2C interrupt sources.
+* See \ref group_scb_common_macros_i2c_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetI2CInterruptMask(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_I2C_INTR_MASK));
+
+ SCB_INTR_I2C_EC_MASK(base) = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetI2CInterruptMask
+****************************************************************************//**
+*
+* Returns the I2C interrupt mask register. This register specifies which bits
+* from the I2C interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Enabled I2C interrupt sources.
+* See \ref group_scb_common_macros_i2c_intr.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptMask(CySCB_Type const *base)
+{
+ return (SCB_INTR_I2C_EC_MASK(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetI2CInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the I2C interrupt masked request register. This register contains
+* a logical AND of corresponding bits from I2C interrupt request and mask
+* registers.
+* This function is intended to be used in the interrupt service routine to
+* identify which of enabled I2C interrupt sources caused the interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of enabled I2C interrupt sources.
+* See \ref group_scb_common_macros_i2c_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const *base)
+{
+ return (SCB_INTR_I2C_EC_MASKED(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearI2CInterrupt
+****************************************************************************//**
+*
+* Clears I2C interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The I2C interrupt sources to be cleared.
+* See \ref group_scb_common_macros_i2c_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearI2CInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_I2C_INTR_MASK));
+
+ SCB_INTR_I2C_EC(base) = interruptMask;
+ (void) SCB_INTR_I2C_EC(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetSpiInterruptStatus
+****************************************************************************//**
+*
+* Returns the SPI interrupt request register. This register contains the current
+* status of the SPI interrupt sources.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of SPI interrupt sources. Each constant is a bit field value.
+* The value returned may have multiple bits set to indicate the current status
+* See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatus(CySCB_Type const *base)
+{
+ return (SCB_INTR_SPI_EC(base) & CY_SCB_SPI_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetSpiInterruptMask
+****************************************************************************//**
+*
+* Writes the SPI interrupt mask register. This register specifies which
+* bits from the SPI interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* Enabled SPI interrupt sources.
+* See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetSpiInterruptMask(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SPI_INTR_MASK));
+
+ SCB_INTR_SPI_EC_MASK(base) = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetSpiInterruptMask
+****************************************************************************//**
+*
+* Returns the SPI interrupt mask register. This register specifies which bits
+* from the SPI interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Enabled SPI interrupt sources.
+* See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptMask(CySCB_Type const *base)
+{
+ return (SCB_INTR_SPI_EC_MASK(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetSpiInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the SPI interrupt masked request register. This register contains
+* a logical AND of corresponding bits from the SPI interrupt request and
+* mask registers.
+* This function is intended to be used in the interrupt service routine to
+* identify which of enabled SPI interrupt sources caused the interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of enabled SPI interrupt sources.
+* See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const *base)
+{
+ return (SCB_INTR_SPI_EC_MASKED(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearSpiInterrupt
+****************************************************************************//**
+*
+* Clears SPI interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The SPI interrupt sources to be cleared.
+* See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearSpiInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SPI_INTR_MASK));
+
+ SCB_INTR_SPI_EC(base) = interruptMask;
+ (void) SCB_INTR_SPI_EC(base);
+}
+
+/** \cond INTERNAL */
+/*******************************************************************************
+* Function Name: Cy_SCB_GetFifoSize
+****************************************************************************//**
+*
+* Returns the RX and TX FIFO depth.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* FIFO depth.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetFifoSize(CySCB_Type const *base)
+{
+ return (_FLD2BOOL(SCB_CTRL_BYTE_MODE, SCB_CTRL(base)) ?
+ (CY_SCB_FIFO_SIZE) : (CY_SCB_FIFO_SIZE / 2UL));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_IsRxDataWidthByte
+****************************************************************************//**
+*
+* Returns true if the RX data width is a byte (8 bits).
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* True if the RX data width is a byte (8 bits).
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SCB_IsRxDataWidthByte(CySCB_Type const *base)
+{
+ return (_FLD2VAL(SCB_RX_CTRL_DATA_WIDTH, SCB_RX_CTRL(base)) < CY_SCB_BYTE_WIDTH);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_IsTxDataWidthByte
+****************************************************************************//**
+*
+* Returns true if the TX data width is a byte (8 bits).
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* If true, the TX data width is a byte (8 bits). Otherwise, false.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base)
+{
+ return (_FLD2VAL(SCB_TX_CTRL_DATA_WIDTH, SCB_TX_CTRL(base)) < CY_SCB_BYTE_WIDTH);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_FwBlockReset
+****************************************************************************//**
+*
+* Disables and enables the block to return it into the known state (default):
+* FIFOs and interrupt statuses are cleared.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_FwBlockReset(CySCB_Type *base)
+{
+ SCB_CTRL(base) &= (uint32_t) ~SCB_CTRL_ENABLED_Msk;
+
+ /* Clean-up command registers */
+ SCB_I2C_M_CMD(base) = 0UL;
+ SCB_I2C_S_CMD(base) = 0UL;
+
+ SCB_CTRL(base) |= (uint32_t) SCB_CTRL_ENABLED_Msk;
+
+ (void) SCB_CTRL(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetRxFifoLevel
+****************************************************************************//**
+*
+* Returns the RX FIFO level when there are more words in the RX FIFO than the
+* level, the RX FIFO level interrupt is triggered.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* RX FIFO level.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel(CySCB_Type const *base)
+{
+ return _FLD2VAL(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, SCB_RX_FIFO_CTRL(base));
+}
+
+/** \endcond */
+/** \} group_scb_common_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** \} group_scb_common */
+
+#endif /* CY_IP_MXSCB */
+
+#endif /* (CY_SCB_COMMON_H) */
+
+/* [] END OF FILE */
+
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_scb_ezi2c.h b/platform/ext/target/psoc64/Native_Driver/include/cy_scb_ezi2c.h
new file mode 100644
index 0000000000..324750b03e
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_scb_ezi2c.h
@@ -0,0 +1,555 @@
+/***************************************************************************//**
+* \file cy_scb_ezi2c.h
+* \version 2.30.1
+*
+* Provides EZI2C API declarations of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_ezi2c
+* \{
+* Driver API for EZI2C Slave Peripheral
+*
+* The functions and other declarations used in this part of the driver are in
+* cy_scb_ezi2c.h. You can also include cy_pdl.h (ModusToolbox only) to get access
+* to all functions and declarations in the PDL.
+*
+* I2C - The Inter-Integrated Circuit (I2C) bus is an industry-standard.
+*
+* The EZI2C slave peripheral driver provides an API to implement the I2C slave
+* device based on the SCB hardware block. This slave device emulates a common
+* I2C EEPROM interface that acts like dual-port memory between the external
+* master and your code. I2C devices based on the SCB hardware are compatible
+* with the I2C Standard mode, Fast mode, and Fast mode Plus specifications, as
+* defined in the I2C bus specification.
+*
+* Features:
+* * An industry-standard I2C bus interface
+* * Supports standard data rates of 100/400/1000 kbps
+* * Emulates a common I2C EEPROM Interface
+* * Acts like dual-port memory between the external master and your code
+* * Supports Hardware Address Match
+* * Supports two hardware addresses with separate buffers
+* * Supports Wake from Deep Sleep on address match
+* * Simple to set up and use; does not require calling EZI2C API
+* at run time.
+*
+********************************************************************************
+* \section group_scb_ezi2c_configuration Configuration Considerations
+********************************************************************************
+* The EZI2C slave driver configuration can be divided to number of sequential
+* steps listed below:
+* * \ref group_scb_ezi2c_config
+* * \ref group_scb_ezi2c_pins
+* * \ref group_scb_ezi2c_clock
+* * \ref group_scb_ezi2c_data_rate
+* * \ref group_scb_ezi2c_intr
+* * \ref group_scb_ezi2c_enable
+*
+* \note
+* EZI2C slave driver is built on top of the SCB hardware block. The SCB3
+* instance is used as an example for all code snippets. Modify the code to
+* match your design.
+*
+********************************************************************************
+* \subsection group_scb_ezi2c_config Configure EZI2C slave
+********************************************************************************
+* To set up the EZI2C slave driver, provide the configuration parameters in the
+* \ref cy_stc_scb_ezi2c_config_t structure. The primary slave address
+* slaveAddress1 must be provided. The other parameters are optional for
+* operation. To initialize the driver, call \ref Cy_SCB_EZI2C_Init
+* function providing a pointer to the populated \ref cy_stc_scb_ezi2c_config_t
+* structure and the allocated \ref cy_stc_scb_ezi2c_context_t structure.
+*
+* \snippet scb/ezi2c_snippet/main.c EZI2C_CFG
+*
+* Set up the EZI2C slave buffer before enabling its
+* operation by using \ref Cy_SCB_EZI2C_SetBuffer1 for the primary slave address
+* and \ref Cy_SCB_EZI2C_SetBuffer2 for the secondary (if the secondary is enabled).
+*
+* \snippet scb/ezi2c_snippet/main.c EZI2C_CFG_BUFFER
+*
+********************************************************************************
+* \subsection group_scb_ezi2c_pins Assign and Configure Pins
+********************************************************************************
+* Only dedicated SCB pins can be used for I2C operation. The HSIOM
+* register must be configured to connect dedicated SCB I2C pins to the
+* SCB block. Also the I2C pins must be configured in Open-Drain, Drives Low mode
+* (this pin configuration implies usage of external pull-up resistors):
+*
+* \snippet scb/ezi2c_snippet/main.c EZI2C_CFG_PINS
+*
+* \note
+* The alternative pins configuration is Resistive Pull-ups which implies usage
+* internal pull-up resistors. This configuration is not recommended because
+* resistor value is fixed and cannot be used for all supported data rates.
+* Refer to device datasheet parameter RPULLUP for resistor value specifications.
+*
+********************************************************************************
+* \subsection group_scb_ezi2c_clock Assign Clock Divider
+********************************************************************************
+* A clock source must be connected to the SCB block to oversample input and
+* output signals, in this document this clock will be referred as clk_scb.
+* You must use one of the 8-bit or 16-bit dividers. Use the \ref group_sysclk
+* driver API to do this.
+*
+* \snippet scb/ezi2c_snippet/main.c EZI2C_CFG_ASSIGN_CLOCK
+*
+********************************************************************************
+* \subsection group_scb_ezi2c_data_rate Configure Data Rate
+********************************************************************************
+* To get EZI2C slave to operate at the desired data rate, the clk_scb must be
+* fast enough to provide sufficient oversampling. Use the
+* \ref group_sysclk driver API to do this.
+*
+* <b>Refer to the technical reference manual (TRM) section I2C sub-section
+* Oversampling and Bit Rate to get information about how to configure the
+* I2C to run at the desired data rate</b>.
+*
+* \snippet scb/ezi2c_snippet/main.c EZI2C_CFG_DATA_RATE
+*
+********************************************************************************
+* \subsection group_scb_ezi2c_intr Configure Interrupt
+********************************************************************************
+* The interrupt is mandatory for the EZI2C slave operation.
+* The \ref Cy_SCB_EZI2C_Interrupt function must be called in the interrupt
+* handler for the selected SCB instance. Also, this interrupt must be enabled
+* in the NVIC or it will not work.
+*
+* \snippet scb/ezi2c_snippet/main.c EZI2C_INTR_A
+* \snippet scb/ezi2c_snippet/main.c EZI2C_INTR_B
+*
+********************************************************************************
+* \subsection group_scb_ezi2c_enable Enable EZI2C slave
+********************************************************************************
+* Finally, enable the EZI2C slave operation by calling \ref Cy_SCB_EZI2C_Enable.
+* Now the I2C device responds to the assigned address.
+* \snippet scb/ezi2c_snippet/main.c EZI2C_ENABLE
+*
+********************************************************************************
+* \section group_scb_ezi2c_use_cases Common Use Cases
+********************************************************************************
+* The EZI2C slave operation might not require calling any EZI2C slave function
+* because the I2C master is able to access the slave buffer. The application
+* can directly access it as well. Note that this is an application-level task
+* to ensure the buffer content integrity.
+*
+********************************************************************************
+* \subsection group_scb_ezi2c_master_wr Master Write operation
+********************************************************************************
+* This operation starts with sending a base address that is one
+* or two bytes, depending on the sub-address size configuration. This base
+* address is retained and will be used for later read operations. Following
+* the base address, there is a sequence of bytes written into the buffer
+* starting from the base address location. The buffer index is incremented
+* for each written byte, but this does not affect the base address that is
+* retained. The length of a write operation is limited by the maximum buffer
+* read/write region size.\n
+* When a master attempts to write outside the read/write region or past the
+* end of the buffer, the last byte is NACKed.
+*
+* \image html scb_ezi2c_write.png
+*
+********************************************************************************
+* \subsection group_scb_ezi2c_master_rd Master Read operation
+********************************************************************************
+* This operation always starts from the base address set by the most
+* recent write operation. The buffer index is incremented for each read byte.
+* Two sequential read operations start from the same base address no matter
+* how many bytes are read. The length of a read operation is not limited by
+* the maximum size of the data buffer. The EZI2C slave returns 0xFF bytes
+* if the read operation passes the end of the buffer.\n
+* Typically, a read operation requires the base address to be updated before
+* starting the read. In this case, the write and read operations must be
+* combined together.
+*
+* \image html scb_ezi2c_read.png
+*
+* The I2C master may use the ReStart or Stop/Start conditions to combine the
+* operations. The write operation sets only the base address and the following
+* read operation will start from the new base address. In cases where the base
+* address remains the same, there is no need for a write operation.
+* \image html scb_ezi2c_set_ba_read.png
+*
+********************************************************************************
+* \section group_scb_ezi2c_lp Low Power Support
+********************************************************************************
+* The EZI2C slave provides the callback functions to handle power mode
+* transition. The callback \ref Cy_SCB_EZI2C_DeepSleepCallback must be called
+* during execution of \ref Cy_SysPm_CpuEnterDeepSleep;
+* \ref Cy_SCB_EZI2C_HibernateCallback must be called during execution of
+* \ref Cy_SysPm_SystemEnterHibernate. To trigger the callback execution, the
+* callback must be registered before calling the power mode transition function.
+* Refer to \ref group_syspm driver for more information about power mode
+* transitions and callback registration.
+*
+* The EZI2C configured to support two addresses can wakeup the device on
+* address match to NACK not supported address. This happens because the
+* hardware address-match-logic uses address bit masking to support to two
+* addresses. The address mask defines which bits in the address are treated
+* as non-significant while performing an address match. One non-significant
+* bit results in two matching addresses; two bits will match 4 and so on.
+* If the two addresses differ by more than a single bit, then the extra
+* addresses that will pass the hardware match and wakeup the device from
+* Deep Sleep mode. Then firmware address matching will to generate a NAK.
+* Due to this reason, it is preferable to select a secondary address that
+* is different from the primary by one bit. The address mask in this case
+* makes one bit non-significant.
+* For example:
+* * Primary address = 0x24 and secondary address = 0x34, only one bit differs.
+* Only the two addresses are treated as matching by the hardware.
+* * Primary address = 0x24 and secondary address = 0x30, two bits differ.
+* Four addresses are treated as matching by the hardware: 0x24, 0x34, 0x20
+* and 0x30. Firmware is required to ACK only the primary and secondary
+* addresses 0x24 and 0x30 and NAK all others 0x20 and 0x34.
+*
+* \note
+* Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
+* For proper operation, when the EZI2C slave is configured to be a wakeup
+* source from Deep Sleep mode, the \ref Cy_SCB_EZI2C_DeepSleepCallback must
+* be copied and modified. Refer to the function description to get the details.
+*
+* \defgroup group_scb_ezi2c_macros Macros
+* \defgroup group_scb_ezi2c_functions Functions
+* \{
+* \defgroup group_scb_ezi2c_general_functions General
+* \defgroup group_scb_ezi2c_slave_functions Slave
+* \defgroup group_scb_ezi2c_low_power_functions Low Power Callbacks
+* \}
+* \defgroup group_scb_ezi2c_data_structures Data Structures
+* \defgroup group_scb_ezi2c_enums Enumerated Types
+*/
+
+#if !defined(CY_SCB_EZI2C_H)
+#define CY_SCB_EZI2C_H
+
+#include "cy_scb_common.h"
+
+#ifdef CY_IP_MXSCB
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Enumerated Types
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_ezi2c_enums
+* \{
+*/
+
+/** EZI2C slave status codes */
+typedef enum
+{
+ /** Operation completed successfully */
+ CY_SCB_EZI2C_SUCCESS = 0U,
+
+ /** One or more of input parameters are invalid */
+ CY_SCB_EZI2C_BAD_PARAM = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_EZI2C_ID | 1U),
+} cy_en_scb_ezi2c_status_t;
+
+/** Number of Addresses */
+typedef enum
+{
+ CY_SCB_EZI2C_ONE_ADDRESS, /**< Only one address */
+ CY_SCB_EZI2C_TWO_ADDRESSES /**< Two addresses */
+} cy_en_scb_ezi2c_num_of_addr_t;
+
+/** Size of Sub-Address */
+typedef enum
+{
+ CY_SCB_EZI2C_SUB_ADDR8_BITS, /**< Sub-address is 8 bits */
+ CY_SCB_EZI2C_SUB_ADDR16_BITS /**< Sub-address is 16 bits */
+} cy_en_scb_ezi2c_sub_addr_size_t;
+
+/** \cond INTERNAL */
+/** EZI2C slave FSM states */
+typedef enum
+{
+ CY_SCB_EZI2C_STATE_IDLE,
+ CY_SCB_EZI2C_STATE_ADDR,
+ CY_SCB_EZI2C_STATE_RX_OFFSET_MSB,
+ CY_SCB_EZI2C_STATE_RX_OFFSET_LSB,
+ CY_SCB_EZI2C_STATE_RX_DATA0,
+ CY_SCB_EZI2C_STATE_RX_DATA1,
+ CY_SCB_EZI2C_STATE_TX_DATA
+} cy_en_scb_ezi2c_state_t;
+/** \endcond */
+/** \} group_scb_ezi2c_enums */
+
+
+/*******************************************************************************
+* Type Definitions
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_ezi2c_data_structures
+* \{
+*/
+
+/** EZI2C slave configuration structure */
+typedef struct cy_stc_scb_ezi2c_config
+{
+ /** The number of supported addresses either */
+ cy_en_scb_ezi2c_num_of_addr_t numberOfAddresses;
+
+ /** The 7-bit right justified primary slave address */
+ uint8_t slaveAddress1;
+
+ /** The 7-bit right justified secondary slave address */
+ uint8_t slaveAddress2;
+
+ /** The size of the sub-address, can either be 8 or 16 bits */
+ cy_en_scb_ezi2c_sub_addr_size_t subAddressSize;
+
+ /**
+ * When set, the slave will wake the device from Deep Sleep on an address
+ * match (The device datasheet must be consulted to determine which SCBs
+ * support this mode)
+ */
+ bool enableWakeFromSleep;
+} cy_stc_scb_ezi2c_config_t;
+
+/** EZI2C slave context structure.
+* All fields for the context structure are internal. Firmware never reads or
+* writes these values. Firmware allocates the structure and provides the
+* address of the structure to the driver in function calls. Firmware must
+* ensure that the defined instance of this structure remains in scope
+* while the drive is in use.
+*/
+typedef struct cy_stc_scb_ezi2c_context
+{
+ /** \cond INTERNAL */
+ volatile cy_en_scb_ezi2c_state_t state; /**< The driver state */
+ volatile uint32_t status; /**< The slave status */
+
+ uint8_t address1; /**< The primary slave address (7-bits right justified) */
+ uint8_t address2; /**< The secondary slave address (7-bits right justified) */
+ cy_en_scb_ezi2c_sub_addr_size_t subAddrSize; /**< The sub-address size */
+
+ uint32_t idx; /**< The index within the buffer during operation */
+ uint32_t baseAddr1; /**< The valid base address for the primary slave address */
+ uint32_t baseAddr2; /**< The valid base address for the secondary slave address */
+
+ bool addr1Active; /**< Defines whether the request is intended for the primary slave address */
+ uint8_t *curBuf; /**< The pointer to the current location in the buffer (while it is accessed) */
+ uint32_t bufSize; /**< Specifies how many bytes are left in the current buffer */
+
+ uint8_t *buf1; /**< The pointer to the buffer exposed on the request intended for the primary slave address */
+ uint32_t buf1Size; /**< The buffer size assigned to the primary slave address */
+ uint32_t buf1rwBondary; /**< The Read/Write boundary within the buffer assigned to the primary slave address */
+
+ uint8_t *buf2; /**< The pointer to the buffer exposed on the request intended for the secondary slave address */
+ uint32_t buf2Size; /**< The buffer size assigned to the secondary slave address */
+ uint32_t buf2rwBondary; /**< The Read/Write boundary within the buffer assigned for the secondary slave address */
+ /** \endcond */
+} cy_stc_scb_ezi2c_context_t;
+/** \} group_scb_ezi2c_data_structures */
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_ezi2c_general_functions
+* \{
+*/
+cy_en_scb_ezi2c_status_t Cy_SCB_EZI2C_Init(CySCB_Type *base, cy_stc_scb_ezi2c_config_t const *config,
+ cy_stc_scb_ezi2c_context_t *context);
+void Cy_SCB_EZI2C_DeInit(CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_EZI2C_Enable(CySCB_Type *base);
+void Cy_SCB_EZI2C_Disable(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context);
+
+void Cy_SCB_EZI2C_SetAddress1(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_context_t *context);
+uint32_t Cy_SCB_EZI2C_GetAddress1(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t const *context);
+
+void Cy_SCB_EZI2C_SetAddress2(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_context_t *context);
+uint32_t Cy_SCB_EZI2C_GetAddress2(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t const *context);
+/** \} group_scb_ezi2c_general_functions */
+
+/**
+* \addtogroup group_scb_ezi2c_slave_functions
+* \{
+*/
+void Cy_SCB_EZI2C_SetBuffer1(CySCB_Type const *base, uint8_t *buffer, uint32_t size, uint32_t rwBoundary,
+ cy_stc_scb_ezi2c_context_t *context);
+void Cy_SCB_EZI2C_SetBuffer2(CySCB_Type const *base, uint8_t *buffer, uint32_t size, uint32_t rwBoundary,
+ cy_stc_scb_ezi2c_context_t *context);
+
+uint32_t Cy_SCB_EZI2C_GetActivity(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t *context);
+
+void Cy_SCB_EZI2C_Interrupt(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context);
+/** \} group_scb_ezi2c_slave_functions */
+
+/**
+* \addtogroup group_scb_ezi2c_low_power_functions
+* \{
+*/
+cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
+cy_en_syspm_status_t Cy_SCB_EZI2C_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
+/** \} group_scb_ezi2c_low_power_functions */
+
+
+/*******************************************************************************
+* API Constants
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_ezi2c_macros
+* \{
+*/
+
+/**
+* \defgroup group_scb_ezi2c_macros_get_activity EZI2C Activity Status
+* Macros to check current EZI2C activity slave status returned by
+* \ref Cy_SCB_EZI2C_GetActivity function. Each EZI2C slave status is encoded
+* in a separate bit, therefore multiple bits may be set to indicate the
+* current status.
+* \{
+*/
+
+/**
+* The Read transfer intended for the primary slave address is complete.
+* The error condition status bit must be checked to ensure that the Read
+* transfer was completed successfully.
+*/
+#define CY_SCB_EZI2C_STATUS_READ1 (0x01UL)
+
+/**
+* The Write transfer intended for the primary slave address is complete.
+* The buffer content was modified.
+* The error condition status bit must be checked to ensure that the Write
+* transfer was completed successfully.
+*/
+#define CY_SCB_EZI2C_STATUS_WRITE1 (0x02UL)
+
+/**
+* The Read transfer intended for the secondary slave address is complete.
+* The error condition status bit must be checked to ensure that the Read
+* transfer was completed successfully.
+*/
+#define CY_SCB_EZI2C_STATUS_READ2 (0x04UL)
+
+/**
+* The Write transfer intended for the secondary slave address is complete.
+* The buffer content was modified.
+* The error condition status bit must be checked to ensure that the Write
+* transfer was completed successfully.
+*/
+#define CY_SCB_EZI2C_STATUS_WRITE2 (0x08UL)
+
+/**
+* A transfer intended for the primary address or secondary address is in
+* progress. The status bit is set after an address match and cleared
+* on a Stop or ReStart condition.
+*/
+#define CY_SCB_EZI2C_STATUS_BUSY (0x10UL)
+
+/**
+* An error occurred during a transfer intended for the primary or secondary
+* slave address. The sources of the error are: a misplaced Start or Stop
+* condition or lost arbitration while the slave drives SDA.
+* When CY_SCB_EZI2C_STATUS_ERR is set, the slave buffer may contain an
+* invalid byte. Discard the buffer content in this case.
+*/
+#define CY_SCB_EZI2C_STATUS_ERR (0x20UL)
+/** \} group_scb_ezi2c_macros_get_activity */
+
+/**
+* This value is returned by the slave when the buffer is not configured or
+* the master requests more bytes than are available in the buffer.
+*/
+#define CY_SCB_EZI2C_DEFAULT_TX (0xFFUL)
+
+
+/*******************************************************************************
+* Internal Constants
+*******************************************************************************/
+
+/** \cond INTERNAL */
+/* Default registers values */
+#define CY_SCB_EZI2C_I2C_CTRL (SCB_I2C_CTRL_S_GENERAL_IGNORE_Msk | SCB_I2C_CTRL_SLAVE_MODE_Msk)
+#define CY_SCB_EZI2C_RX_CTRL (CY_SCB_I2C_RX_CTRL)
+#define CY_SCB_EZI2C_TX_CTRL (CY_SCB_I2C_TX_CTRL)
+
+#define CY_SCB_EZI2C_SLAVE_INTR (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_STOP | \
+ CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_I2C_ARB_LOST)
+/* Error interrupt sources */
+#define CY_SCB_EZI2C_SLAVE_INTR_ERROR (CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_I2C_ARB_LOST)
+
+/* Disables Stop interrupt source */
+#define CY_SCB_EZI2C_SLAVE_INTR_NO_STOP (CY_SCB_EZI2C_SLAVE_INTR & ((uint32_t) ~CY_SCB_SLAVE_INTR_I2C_STOP))
+
+/* Disable Address interrupt source */
+#define CY_SCB_EZI2C_SLAVE_INTR_NO_ADDR (CY_SCB_EZI2C_SLAVE_INTR & ((uint32_t) ~CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH))
+
+/* FIFO size */
+#define CY_SCB_EZI2C_FIFO_SIZE CY_SCB_FIFO_SIZE
+#define CY_SCB_EZI2C_HALF_FIFO_SIZE (CY_SCB_FIFO_SIZE / 2UL)
+
+#define CY_SCB_EZI2C_ONE_ADDRESS_MASK (0xFFUL)
+
+#define CY_SCB_EZI2C_IS_NUM_OF_ADDR_VALID(numAddr) ( (CY_SCB_EZI2C_ONE_ADDRESS == (numAddr)) || \
+ (CY_SCB_EZI2C_TWO_ADDRESSES == (numAddr)) )
+
+#define CY_SCB_EZI2C_IS_SUB_ADDR_SIZE_VALID(subAddrSize) ( (CY_SCB_EZI2C_SUB_ADDR8_BITS == (subAddrSize)) || \
+ (CY_SCB_EZI2C_SUB_ADDR16_BITS == (subAddrSize)) )
+/** \endcond */
+/** \} group_scb_ezi2c_macros */
+
+
+/*******************************************************************************
+* In-line Function Implementation
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_ezi2c_general_functions
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_Enable
+****************************************************************************//**
+*
+* Enables the SCB block for the EZI2C operation
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_EZI2C_Enable(CySCB_Type *base)
+{
+ SCB_CTRL(base) |= SCB_CTRL_ENABLED_Msk;
+}
+
+/** \} group_scb_ezi2c_general_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** \} group_scb_ezi2c */
+
+#endif /* (CY_IP_MXSCB) */
+
+#endif /* (CY_SCB_EZI2C_H) */
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_scb_uart.h b/platform/ext/target/psoc64/Native_Driver/include/cy_scb_uart.h
new file mode 100644
index 0000000000..37a22434f9
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_scb_uart.h
@@ -0,0 +1,1526 @@
+/***************************************************************************//**
+* \file cy_scb_uart.h
+* \version 2.30.1
+*
+* Provides UART API declarations of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_uart
+* \{
+* Driver API for UART
+*
+* The functions and other declarations used in this part of the driver are in
+* cy_scb_uart.h. You can also include cy_pdl.h (ModusToolbox only) to get access
+* to all functions and declarations in the PDL.
+*
+* The Universal Asynchronous Receiver/Transmitter (UART) protocol is an
+* asynchronous serial interface protocol. UART communication is typically
+* point-to-point. The UART interface consists of two signals:
+* * TX: Transmitter output
+* * RX: Receiver input
+*
+* Additionally, two side-band signals are used to implement flow control in
+* UART. Note that the flow control applies only to TX functionality.
+* * Clear to Send (CTS): This is an input signal to the transmitter.
+* When active, it indicates that the slave is ready for the master to
+* transmit data.
+* * Ready to Send (RTS): This is an output signal from the receiver. When
+* active, it indicates that the receiver is ready to receive data
+*
+* Features:
+* * Supports UART protocol
+* * Standard UART
+* * Multi-processor mode
+* * SmartCard (ISO7816) reader
+* * IrDA
+* * Data frame size programmable from 4 to 16 bits
+* * Programmable number of STOP bits, which can be set in terms of half bit
+* periods between 1 and 4
+* * Parity support (odd and even parity)
+* * Median filter on Rx input
+* * Programmable oversampling
+* * Start skipping
+*
+********************************************************************************
+* \section group_scb_uart_configuration Configuration Considerations
+********************************************************************************
+* The UART driver configuration can be divided to number of sequential
+* steps listed below:
+* * \ref group_scb_uart_config
+* * \ref group_scb_uart_pins
+* * \ref group_scb_uart_clock
+* * \ref group_scb_uart_data_rate
+* * \ref group_scb_uart_intr
+* * \ref group_scb_uart_enable
+*
+* \note
+* UART driver is built on top of the SCB hardware block. The SCB5 instance is
+* used as an example for all code snippets. Modify the code to match your
+* design.
+*
+********************************************************************************
+* \subsection group_scb_uart_config Configure UART
+********************************************************************************
+* To set up the UART driver, provide the configuration parameters in the
+* \ref cy_stc_scb_uart_config_t structure. For example: provide uartMode,
+* oversample, dataWidth, enableMsbFirst, parity, and stopBits. The other
+* parameters are optional. To initialize the driver, call \ref Cy_SCB_UART_Init
+* function providing a pointer to the populated \ref cy_stc_scb_uart_config_t
+* structure and the allocated \ref cy_stc_scb_uart_context_t structure.
+*
+* \snippet scb/uart_snippet/main.c UART_CFG
+*
+********************************************************************************
+* \subsection group_scb_uart_pins Assign and Configure Pins
+********************************************************************************
+* Only dedicated SCB pins can be used for UART operation. The HSIOM
+* register must be configured to connect dedicated SCB UART pins to the
+* SCB block. Also, the UART output pins must be configured in Strong Drive
+* Input Off mode and UART input pins in Digital High-Z:
+*
+* \snippet scb/uart_snippet/main.c UART_CFG_PINS
+*
+********************************************************************************
+* \subsection group_scb_uart_clock Assign Clock Divider
+********************************************************************************
+* A clock source must be connected to the SCB block to oversample input and
+* output signals, in this document this clock will be referred as clk_scb.
+* You must use one of available integer or fractional dividers. Use the
+* \ref group_sysclk driver API to do this.
+*
+* \snippet scb/uart_snippet/main.c UART_CFG_ASSIGN_CLOCK
+*
+********************************************************************************
+* \subsection group_scb_uart_data_rate Configure Baud Rate
+********************************************************************************
+* To get the UART to operate with the desired baud rate, the clk_scb frequency
+* and the oversample must be configured. Use the \ref group_sysclk driver API
+* to configure clk_scb frequency. Set the <em><b>oversample parameter
+* in configuration structure</b></em> to define the number of the SCB clocks
+* within one UART bit-time.
+*
+* \snippet scb/uart_snippet/main.c UART_CFG_DATA_RATE
+*
+* <b>Refer to the technical reference manual (TRM) section UART sub-section
+* Clocking and Oversampling to get information about how to configure the UART to run with
+* desired baud rate.</b>
+*
+********************************************************************************
+* \subsection group_scb_uart_intr Configure Interrupt
+********************************************************************************
+* The interrupt is optional for the UART operation. To configure interrupt
+* the \ref Cy_SCB_UART_Interrupt function must be called in the interrupt
+* handler for the selected SCB instance. Also, this interrupt must be enabled
+* in the NVIC.
+* The interrupt must be configured when \ref group_scb_uart_hl will be used.
+*
+* \snippet scb/uart_snippet/main.c UART_INTR_A
+* \snippet scb/uart_snippet/main.c UART_INTR_B
+*
+********************************************************************************
+* \subsection group_scb_uart_enable Enable UART
+********************************************************************************
+* Finally, enable the UART operation by calling \ref Cy_SCB_UART_Enable.
+*
+* \snippet scb/uart_snippet/main.c UART_ENABLE
+*
+********************************************************************************
+* \section group_scb_uart_use_cases Common Use Cases
+********************************************************************************
+* The UART API is divided into two categories: \ref group_scb_uart_low_level_functions
+* and \ref group_scb_uart_high_level_functions. \n
+* <em>Do not mix <b>High-Level</b> and <b>Low-Level</b> API because a Low-Level
+* API can adversely affect the operation of a High-Level API.</em>
+*
+********************************************************************************
+* \subsection group_scb_uart_ll Low-Level API
+********************************************************************************
+* The \ref group_scb_uart_low_level_functions functions allow
+* interacting directly with the hardware and do not use \ref Cy_SCB_UART_Interrupt.
+* These functions do not require context for operation. Thus, NULL can be
+* passed for context parameter in \ref Cy_SCB_UART_Init and \ref Cy_SCB_UART_Disable
+* instead of a pointer to the context structure.
+*
+* * To write data into the TX FIFO, use one of the provided functions:
+* \ref Cy_SCB_UART_Put, \ref Cy_SCB_UART_PutArray,
+* \ref Cy_SCB_UART_PutArrayBlocking or \ref Cy_SCB_UART_PutString.
+* Note that putting data into the TX FIFO starts data transfer.
+*
+* * To read data from the RX FIFO, use one of the provided functions:
+* \ref Cy_SCB_UART_Get, \ref Cy_SCB_UART_GetArray or
+* \ref Cy_SCB_UART_GetArrayBlocking.
+*
+* * The statuses can be polled using: \ref Cy_SCB_UART_GetRxFifoStatus and
+* \ref Cy_SCB_UART_GetTxFifoStatus.
+* <em>The statuses are <b>W1C (Write 1 to Clear)</b> and after a status
+* is set, it must be cleared.</em> Note that there are statuses evaluated as level.
+* These statuses remain set until an event is true. Therefore, after the clear
+* operation, the status is cleared but then it is restored (if event is still
+* true).
+* Also, the following functions can be used for polling as well
+* \ref Cy_SCB_UART_IsTxComplete, \ref Cy_SCB_UART_GetNumInRxFifo and
+* \ref Cy_SCB_UART_GetNumInTxFifo.
+*
+* \snippet scb/uart_snippet/main.c UART_TRANSMIT_DATA_LL
+*
+********************************************************************************
+* \subsection group_scb_uart_hl High-Level API
+********************************************************************************
+* The \ref group_scb_uart_high_level_functions API use \ref Cy_SCB_UART_Interrupt
+* to execute the transfer. Call \ref Cy_SCB_UART_Transmit to start transmission.
+* Call \ref Cy_SCB_UART_Receive to start receive operation. After the
+* operation is started the \ref Cy_SCB_UART_Interrupt handles the data
+* transfer until its completion.
+* Therefore \ref Cy_SCB_UART_Interrupt must be called inside the user
+* interrupt handler to make the High-Level API work. To monitor status
+* of transmit operation, use \ref Cy_SCB_UART_GetTransmitStatus and
+* \ref Cy_SCB_UART_GetReceiveStatus to monitor receive status appropriately.
+* Alternatively use \ref Cy_SCB_UART_RegisterCallback to register callback
+* function to be notified about \ref group_scb_uart_macros_callback_events.
+*
+* <b>Receive Operation</b>
+* \snippet scb/uart_snippet/main.c UART_RECEIVE_DATA_HL
+*
+* <b>Transmit Operation</b>
+* \snippet scb/uart_snippet/main.c UART_TRANSMIT_DATA_HL
+*
+* There is also capability to insert a receive ring buffer that operates between
+* the RX FIFO and the user buffer. The received data is copied into the ring
+* buffer from the RX FIFO. This process runs in the background after the ring
+* buffer operation is started by \ref Cy_SCB_UART_StartRingBuffer.
+* When \ref Cy_SCB_UART_Receive is called, it first reads data from the ring
+* buffer and then sets up an interrupt to receive more data if the required
+* amount has not yet been read.
+*
+********************************************************************************
+* \section group_scb_uart_dma_trig DMA Trigger
+********************************************************************************
+* The SCB provides TX and RX output trigger signals that can be routed to the
+* DMA controller inputs. These signals are assigned based on the data availability
+* in the TX and RX FIFOs appropriately.
+*
+* * The RX trigger signal is active while the number of data
+* elements in the RX FIFO is greater than the value of RX FIFO level. Use
+* function \ref Cy_SCB_SetRxFifoLevel or set configuration structure
+* rxFifoTriggerLevel parameter to configure RX FIFO level value. \n
+* <em>For example, the RX FIFO has 8 data elements and the RX FIFO level is 0.
+* The RX trigger signal is active until DMA reads all data from
+* the RX FIFO.</em>
+*
+* * The TX trigger signal is active while the number of data elements
+* in the TX FIFO is less than the value of TX FIFO level. Use function
+* \ref Cy_SCB_SetTxFifoLevel or set configuration structure txFifoTriggerLevel
+* parameter to configure TX FIFO level value. \n
+* <em>For example, the TX FIFO has 0 data elements (empty) and the TX FIFO level
+* is 7. The TX trigger signal is active until DMA loads TX FIFO
+* with 8 data elements (note that after the first TX load operation, the data
+* element goes to the shift register and TX FIFO is empty).</em>
+*
+* To route SCB TX or RX trigger signals to DMA controller use \ref group_trigmux
+* driver API.
+*
+* \note
+* To properly handle DMA level request signal activation and de-activation from the SCB
+* peripheral block the DMA Descriptor typically must be configured to re-trigger
+* after 16 Clk_Slow cycles.
+*
+********************************************************************************
+* \section group_scb_uart_lp Low Power Support
+********************************************************************************
+* The UART driver provides callback functions to handle power mode
+* transition. The callback \ref Cy_SCB_UART_DeepSleepCallback must be called
+* during execution of \ref Cy_SysPm_CpuEnterDeepSleep \ref Cy_SCB_UART_HibernateCallback
+* must be called during execution of \ref Cy_SysPm_SystemEnterHibernate. To trigger the
+* callback execution, the callback must be registered before calling the
+* power mode transition function. Refer to \ref group_syspm driver for more
+* information about power mode transitions and callback registration.
+*
+* The UART is disabled during Deep Sleep and Hibernate and stops driving
+* the output pins. The state of the UART output pins TX and RTS is High-Z,
+* which can cause unexpected behavior of the UART receiver due to possible
+* glitches on these lines. These pins must be set to the inactive state before
+* entering Deep Sleep or Hibernate mode.
+* These pins must keep the inactive level (the same state
+* when UART TX is enabled and does not transfer data) before entering Deep
+* Sleep or Hibernate mode. To do that, write the GPIO data register of each pin
+* to the inactive level for each output pin. Then configure High-Speed Input
+* Output Multiplexer (HSIOM) of each pin to be controlled by the GPIO (use
+* \ref group_gpio driver API). After exiting Deep Sleep mode the UART
+* must be enabled and the pins configuration restored to return the
+* UART control of the pins (after exiting Hibernate mode, the
+* system initialization code does the same). Copy either or
+* both \ref Cy_SCB_UART_DeepSleepCallback and \ref Cy_SCB_UART_HibernateCallback
+* as appropriate, and make the changes described above inside the function.
+* Alternately, external pull-up or pull-down resistors can be connected
+* to the appropriate UART lines to keep them inactive during Deep-Sleep or
+* Hibernate.
+*
+* \defgroup group_scb_uart_macros Macros
+* \defgroup group_scb_uart_functions Functions
+* \{
+* \defgroup group_scb_uart_general_functions General
+* \defgroup group_scb_uart_high_level_functions High-Level
+* \defgroup group_scb_uart_low_level_functions Low-Level
+* \defgroup group_scb_uart_interrupt_functions Interrupt
+* \defgroup group_scb_uart_low_power_functions Low Power Callbacks
+* \}
+* \defgroup group_scb_uart_data_structures Data Structures
+* \defgroup group_scb_uart_enums Enumerated Types
+*/
+
+#if !defined(CY_SCB_UART_H)
+#define CY_SCB_UART_H
+
+#include "cy_scb_common.h"
+
+#ifdef CY_IP_MXSCB
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/***************************************
+* Enumerated Types
+***************************************/
+
+/**
+* \addtogroup group_scb_uart_enums
+* \{
+*/
+
+/** UART status codes */
+typedef enum
+{
+ /** Operation completed successfully */
+ CY_SCB_UART_SUCCESS = 0U,
+
+ /** One or more of input parameters are invalid */
+ CY_SCB_UART_BAD_PARAM = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_UART_ID | 1U),
+
+ /**
+ * The UART is busy processing a receive operation.
+ */
+ CY_SCB_UART_RECEIVE_BUSY = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_UART_ID | 2U),
+
+ /**
+ * The UART is busy processing a transmit operation.
+ */
+ CY_SCB_UART_TRANSMIT_BUSY = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_UART_ID | 3U)
+} cy_en_scb_uart_status_t;
+
+/** UART Mode */
+typedef enum
+{
+ CY_SCB_UART_STANDARD = 0U, /**< Configures the SCB for Standard UART operation */
+ CY_SCB_UART_SMARTCARD = 1U, /**< Configures the SCB for SmartCard operation */
+ CY_SCB_UART_IRDA = 2U, /**< Configures the SCB for IrDA operation */
+} cy_en_scb_uart_mode_t;
+
+/** UART Stop Bits */
+typedef enum
+{
+ CY_SCB_UART_STOP_BITS_1 = 2U, /**< UART looks for 1 Stop Bit */
+ CY_SCB_UART_STOP_BITS_1_5 = 3U, /**< UART looks for 1.5 Stop Bits */
+ CY_SCB_UART_STOP_BITS_2 = 4U, /**< UART looks for 2 Stop Bits */
+ CY_SCB_UART_STOP_BITS_2_5 = 5U, /**< UART looks for 2.5 Stop Bits */
+ CY_SCB_UART_STOP_BITS_3 = 6U, /**< UART looks for 3 Stop Bits */
+ CY_SCB_UART_STOP_BITS_3_5 = 7U, /**< UART looks for 3.5 Stop Bits */
+ CY_SCB_UART_STOP_BITS_4 = 8U, /**< UART looks for 4 Stop Bits */
+} cy_en_scb_uart_stop_bits_t;
+
+/** UART Parity */
+typedef enum
+{
+ CY_SCB_UART_PARITY_NONE = 0U, /**< UART has no parity check */
+ CY_SCB_UART_PARITY_EVEN = 2U, /**< UART has even parity check */
+ CY_SCB_UART_PARITY_ODD = 3U, /**< UART has odd parity check */
+} cy_en_scb_uart_parity_t;
+
+/** UART Polarity */
+typedef enum
+{
+ CY_SCB_UART_ACTIVE_LOW = 0U, /**< Signal is active low */
+ CY_SCB_UART_ACTIVE_HIGH = 1U, /**< Signal is active high */
+} cy_en_scb_uart_polarity_t;
+/** \} group_scb_uart_enums */
+
+
+/*******************************************************************************
+* Type Definitions
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_uart_data_structures
+* \{
+*/
+
+/**
+* Provides the typedef for the callback function called in the
+* \ref Cy_SCB_UART_Interrupt to notify the user about occurrences of
+* \ref group_scb_uart_macros_callback_events.
+*/
+typedef void (* cy_cb_scb_uart_handle_events_t)(uint32_t event);
+
+/** UART configuration structure */
+typedef struct stc_scb_uart_config
+{
+ /** Specifies the UART's mode of operation */
+ cy_en_scb_uart_mode_t uartMode;
+
+ /**
+ * Oversample factor for UART.
+ * * The UART baud rate is the SCB Clock frequency / oversample
+ * (valid range is 8-16).
+ * * For IrDA, the oversample is always 16, unless
+ * \ref irdaEnableLowPowerReceiver is enabled. Then the oversample is
+ * reduced to the \ref group_scb_uart_macros_irda_lp_ovs set.
+ */
+ uint32_t oversample;
+
+ /** The width of UART data (valid range is 5 to 9) */
+ uint32_t dataWidth;
+
+ /**
+ * Enables the hardware to shift out data element MSB first; otherwise,
+ * LSB first
+ */
+ bool enableMsbFirst;
+
+ /**
+ * Specifies the number of stop bits in the UART transaction, in half-bit
+ * increments
+ */
+ cy_en_scb_uart_stop_bits_t stopBits;
+
+ /** Configures the UART parity */
+ cy_en_scb_uart_parity_t parity;
+
+ /**
+ * Enables a digital 3-tap median filter (2 out of 3 voting) to be applied
+ * to the input of the RX FIFO to filter glitches on the line (for IrDA,
+ * this parameter is ignored)
+ *
+ */
+ bool enableInputFilter;
+
+ /**
+ * Enables the hardware to drop data in the RX FIFO when a parity error is
+ * detected
+ */
+ bool dropOnParityError;
+
+ /**
+ * Enables the hardware to drop data in the RX FIFO when a frame error is
+ * detected
+ */
+ bool dropOnFrameError;
+
+ /**
+ * Enables the UART operation in Multi-Processor mode which requires
+ * dataWidth to be 9 bits (the 9th bit is used to indicate address byte)
+ */
+ bool enableMutliProcessorMode;
+
+ /**
+ * If Multi Processor mode is enabled, this is the address of the RX
+ * FIFO. If the address matches, data is accepted into the FIFO. If
+ * it does not match, the data is ignored.
+ */
+ uint32_t receiverAddress;
+
+ /**
+ * This is the address mask for the Multi Processor address. 1 indicates
+ * that the incoming address must match the corresponding bit in the slave
+ * address. A 0 in the mask indicates that the incoming address does
+ * not need to match.
+ */
+ uint32_t receiverAddressMask;
+
+ /**
+ * Enables the hardware to accept the matching address in the RX FIFO.
+ * This is useful when the device supports more than one address.
+ */
+ bool acceptAddrInFifo;
+
+ /** Inverts the IrDA RX input */
+ bool irdaInvertRx;
+
+ /**
+ * Enables the low-power receive for IrDA mode.
+ * Note that the transmission must be disabled if this mode is enabled.
+ */
+ bool irdaEnableLowPowerReceiver;
+
+ /**
+ * Enables retransmission of the frame placed in the TX FIFO when
+ * NACK is received in SmartCard mode (for Standard and IrDA , this parameter
+ * is ignored)
+ */
+ bool smartCardRetryOnNack;
+
+ /**
+ * Enables the usage of the CTS input signal for the transmitter. The
+ * transmitter waits for CTS to be active before sending data
+ */
+ bool enableCts;
+
+ /** Sets the CTS Polarity */
+ cy_en_scb_uart_polarity_t ctsPolarity;
+
+ /**
+ * When the RX FIFO has fewer entries than rtsRxFifoLevel, the
+ * RTS signal is active (note to disable RTS, set this field to zero)
+ */
+ uint32_t rtsRxFifoLevel;
+
+ /** Sets the RTS Polarity */
+ cy_en_scb_uart_polarity_t rtsPolarity;
+
+ /** Specifies the number of bits to detect a break condition */
+ uint32_t breakWidth;
+
+ /**
+ * When there are more entries in the RX FIFO than this level
+ * the RX trigger output goes high. This output can be connected
+ * to a DMA channel through a trigger mux.
+ * Also, it controls the \ref CY_SCB_UART_RX_TRIGGER interrupt source.
+ */
+ uint32_t rxFifoTriggerLevel;
+
+ /**
+ * The bits set in this mask allow the event to cause an interrupt
+ * (See \ref group_scb_uart_macros_rx_fifo_status for the set of constants)
+ */
+ uint32_t rxFifoIntEnableMask;
+
+ /**
+ * When there are fewer entries in the TX FIFO then this level
+ * the TX trigger output goes high. This output can be connected
+ * to a DMA channel through a trigger mux.
+ * Also, it controls \ref CY_SCB_UART_TX_TRIGGER interrupt source.
+ */
+ uint32_t txFifoTriggerLevel;
+
+ /**
+ * Bits set in this mask allows the event to cause an interrupt
+ * (See \ref group_scb_uart_macros_tx_fifo_status for the set of constants)
+ */
+ uint32_t txFifoIntEnableMask;
+} cy_stc_scb_uart_config_t;
+
+/** UART context structure.
+* All fields for the context structure are internal. Firmware never reads or
+* writes these values. Firmware allocates the structure and provides the
+* address of the structure to the driver in function calls. Firmware must
+* ensure that the defined instance of this structure remains in scope
+* while the drive is in use.
+*/
+typedef struct cy_stc_scb_uart_context
+{
+ /** \cond INTERNAL */
+ uint32_t volatile txStatus; /**< The transmit status */
+ uint32_t volatile rxStatus; /**< The receive status */
+
+ void *rxRingBuf; /**< The pointer to the ring buffer */
+ uint32_t rxRingBufSize; /**< The ring buffer size */
+ uint32_t volatile rxRingBufHead; /**< The ring buffer head index */
+ uint32_t volatile rxRingBufTail; /**< The ring buffer tail index */
+
+ void *rxBuf; /**< The pointer to the receive buffer */
+ uint32_t rxBufSize; /**< The receive buffer size */
+ uint32_t volatile rxBufIdx; /**< The current location in the receive buffer */
+
+ void *txBuf; /**< The pointer to the transmit buffer */
+ uint32_t txBufSize; /**< The transmit buffer size */
+ uint32_t volatile txLeftToTransmit; /**< The number of data elements left to be transmitted */
+
+ /** The pointer to an event callback that is called when any of
+ * \ref group_scb_uart_macros_callback_events occurs
+ */
+ cy_cb_scb_uart_handle_events_t cbEvents;
+
+#if !defined(NDEBUG)
+ uint32_t initKey; /**< Tracks the context initialization */
+#endif /* !(NDEBUG) */
+ /** \endcond */
+} cy_stc_scb_uart_context_t;
+/** \} group_scb_uart_data_structures */
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_uart_general_functions
+* \{
+*/
+cy_en_scb_uart_status_t Cy_SCB_UART_Init(CySCB_Type *base, cy_stc_scb_uart_config_t const *config,
+ cy_stc_scb_uart_context_t *context);
+void Cy_SCB_UART_DeInit (CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_UART_Enable(CySCB_Type *base);
+void Cy_SCB_UART_Disable(CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+
+__STATIC_INLINE void Cy_SCB_UART_EnableCts (CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_UART_DisableCts (CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_UART_SetRtsFifoLevel(CySCB_Type *base, uint32_t level);
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetRtsFifoLevel(CySCB_Type const *base);
+
+__STATIC_INLINE void Cy_SCB_UART_EnableSkipStart (CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_UART_DisableSkipStart(CySCB_Type *base);
+/** \} group_scb_uart_general_functions */
+
+/**
+* \addtogroup group_scb_uart_high_level_functions
+* \{
+*/
+void Cy_SCB_UART_StartRingBuffer (CySCB_Type *base, void *buffer, uint32_t size,
+ cy_stc_scb_uart_context_t *context);
+void Cy_SCB_UART_StopRingBuffer (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+uint32_t Cy_SCB_UART_GetNumInRingBuffer(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
+void Cy_SCB_UART_ClearRingBuffer (CySCB_Type const *base, cy_stc_scb_uart_context_t *context);
+
+cy_en_scb_uart_status_t Cy_SCB_UART_Receive(CySCB_Type *base, void *buffer, uint32_t size,
+ cy_stc_scb_uart_context_t *context);
+void Cy_SCB_UART_AbortReceive (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+uint32_t Cy_SCB_UART_GetReceiveStatus(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
+uint32_t Cy_SCB_UART_GetNumReceived (CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
+
+cy_en_scb_uart_status_t Cy_SCB_UART_Transmit(CySCB_Type *base, void *buffer, uint32_t size,
+ cy_stc_scb_uart_context_t *context);
+void Cy_SCB_UART_AbortTransmit (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+uint32_t Cy_SCB_UART_GetTransmitStatus (CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
+uint32_t Cy_SCB_UART_GetNumLeftToTransmit(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
+/** \} group_scb_uart_high_level_functions */
+
+/**
+* \addtogroup group_scb_uart_low_level_functions
+* \{
+*/
+__STATIC_INLINE uint32_t Cy_SCB_UART_Put (CySCB_Type *base, uint32_t data);
+__STATIC_INLINE uint32_t Cy_SCB_UART_PutArray (CySCB_Type *base, void *buffer, uint32_t size);
+__STATIC_INLINE void Cy_SCB_UART_PutArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size);
+__STATIC_INLINE void Cy_SCB_UART_PutString (CySCB_Type *base, char_t const string[]);
+void Cy_SCB_UART_SendBreakBlocking(CySCB_Type *base, uint32_t breakWidth);
+
+__STATIC_INLINE uint32_t Cy_SCB_UART_Get (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetArray (CySCB_Type const *base, void *buffer, uint32_t size);
+__STATIC_INLINE void Cy_SCB_UART_GetArrayBlocking(CySCB_Type const *base, void *buffer, uint32_t size);
+
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetTxFifoStatus (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_UART_ClearTxFifoStatus(CySCB_Type *base, uint32_t clearMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetRxFifoStatus (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_UART_ClearRxFifoStatus(CySCB_Type *base, uint32_t clearMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInTxFifo (CySCB_Type const *base);
+__STATIC_INLINE bool Cy_SCB_UART_IsTxComplete (CySCB_Type const *base);
+
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInRxFifo (CySCB_Type const *base);
+
+__STATIC_INLINE void Cy_SCB_UART_ClearRxFifo (CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_UART_ClearTxFifo (CySCB_Type *base);
+/** \} group_scb_uart_low_level_functions */
+
+/**
+* \addtogroup group_scb_uart_interrupt_functions
+* \{
+*/
+void Cy_SCB_UART_Interrupt(CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+
+__STATIC_INLINE void Cy_SCB_UART_RegisterCallback(CySCB_Type const *base, cy_cb_scb_uart_handle_events_t callback,
+ cy_stc_scb_uart_context_t *context);
+/** \} group_scb_uart_interrupt_functions */
+
+/**
+* \addtogroup group_scb_uart_low_power_functions
+* \{
+*/
+cy_en_syspm_status_t Cy_SCB_UART_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
+cy_en_syspm_status_t Cy_SCB_UART_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
+/** \} group_scb_uart_low_power_functions */
+
+
+/*******************************************************************************
+* API Constants
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_uart_macros
+* \{
+*/
+
+/**
+* \defgroup group_scb_uart_macros_irda_lp_ovs UART IRDA Low Power Oversample factors
+* \{
+*/
+#define CY_SCB_UART_IRDA_LP_OVS16 (1UL) /**< IrDA in low-power mode oversampled by 16 */
+#define CY_SCB_UART_IRDA_LP_OVS32 (2UL) /**< IrDA in low-power mode oversampled by 32 */
+#define CY_SCB_UART_IRDA_LP_OVS48 (3UL) /**< IrDA in low-power mode oversampled by 48 */
+#define CY_SCB_UART_IRDA_LP_OVS96 (4UL) /**< IrDA in low-power mode oversampled by 96 */
+#define CY_SCB_UART_IRDA_LP_OVS192 (5UL) /**< IrDA in low-power mode oversampled by 192 */
+#define CY_SCB_UART_IRDA_LP_OVS768 (6UL) /**< IrDA in low-power mode oversampled by 768 */
+#define CY_SCB_UART_IRDA_LP_OVS1536 (7UL) /**< IrDA in low-power mode oversampled by 1536 */
+/** \} group_scb_uart_macros_irda_lp_ovs */
+
+/**
+* \defgroup group_scb_uart_macros_rx_fifo_status UART RX FIFO status.
+* \{
+* Macros to check UART RX FIFO status returned by \ref Cy_SCB_UART_GetRxFifoStatus
+* function or assign mask for \ref Cy_SCB_UART_ClearRxFifoStatus function.
+* Each UART RX FIFO status is encoded in a separate bit, therefore multiple
+* bits may be set to indicate the current status.
+*/
+
+/** The number of entries in the RX FIFO is more than the RX FIFO trigger level
+* value
+*/
+#define CY_SCB_UART_RX_TRIGGER (SCB_INTR_RX_TRIGGER_Msk)
+
+/** The RX FIFO is not empty, there is data to read */
+#define CY_SCB_UART_RX_NOT_EMPTY (SCB_INTR_RX_NOT_EMPTY_Msk)
+
+/**
+* The RX FIFO is full, there is no more space for additional data, and
+* any additional data will be dropped
+*/
+#define CY_SCB_UART_RX_FULL (SCB_INTR_RX_FULL_Msk)
+
+/**
+* The RX FIFO was full and there was an attempt to write to it.
+* That additional data was dropped.
+*/
+#define CY_SCB_UART_RX_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk)
+
+/** An attempt to read from an empty RX FIFO */
+#define CY_SCB_UART_RX_UNDERFLOW (SCB_INTR_RX_UNDERFLOW_Msk)
+
+/** The RX FIFO detected a frame error, either a stop or stop-bit error */
+#define CY_SCB_UART_RX_ERR_FRAME (SCB_INTR_RX_FRAME_ERROR_Msk)
+
+/** The RX FIFO detected a parity error */
+#define CY_SCB_UART_RX_ERR_PARITY (SCB_INTR_RX_PARITY_ERROR_Msk)
+
+/** The RX FIFO detected a break transmission from the transmitter */
+#define CY_SCB_UART_RX_BREAK_DETECT (SCB_INTR_RX_BREAK_DETECT_Msk)
+/** \} group_scb_uart_macros_rx_fifo_status */
+
+/**
+* \defgroup group_scb_uart_macros_tx_fifo_status UART TX FIFO Statuses
+* \{
+* Macros to check UART TX FIFO status returned by \ref Cy_SCB_UART_GetTxFifoStatus
+* function or assign mask for \ref Cy_SCB_UART_ClearTxFifoStatus function.
+* Each UART TX FIFO status is encoded in a separate bit, therefore multiple bits
+* may be set to indicate the current status.
+*/
+
+/** The number of entries in the TX FIFO is less than the TX FIFO trigger level
+* value
+*/
+#define CY_SCB_UART_TX_TRIGGER (SCB_INTR_TX_TRIGGER_Msk)
+
+/** The TX FIFO is not full, there is a space for more data */
+#define CY_SCB_UART_TX_NOT_FULL (SCB_INTR_TX_NOT_FULL_Msk)
+
+/** The TX FIFO is empty, note there may still be data in the shift register.*/
+#define CY_SCB_UART_TX_EMPTY (SCB_INTR_TX_EMPTY_Msk)
+
+/** An attempt to write to the full TX FIFO */
+#define CY_SCB_UART_TX_OVERFLOW (SCB_INTR_TX_OVERFLOW_Msk)
+
+/** An attempt to read from an empty transmitter FIFO (hardware reads). */
+#define CY_SCB_UART_TX_UNDERFLOW (SCB_INTR_TX_UNDERFLOW_Msk)
+
+/** All data has been transmitted out of the FIFO, including shifter */
+#define CY_SCB_UART_TX_DONE (SCB_INTR_TX_UART_DONE_Msk)
+
+/** SmartCard only: the transmitter received a NACK */
+#define CY_SCB_UART_TX_NACK (SCB_INTR_TX_UART_NACK_Msk)
+
+/** SmartCard only: the transmitter lost arbitration */
+#define CY_SCB_UART_TX_ARB_LOST (SCB_INTR_TX_UART_ARB_LOST_Msk)
+/** \} group_scb_uart_macros_tx_fifo_status */
+
+/**
+* \defgroup group_scb_uart_macros_receive_status UART Receive Statuses
+* \{
+* Macros to check current UART receive status returned by
+* \ref Cy_SCB_UART_GetReceiveStatus function.
+* Each UART receive status is encoded in a separate bit, therefore multiple bits
+* may be set to indicate the current status.
+*/
+/** The receive operation started by \ref Cy_SCB_UART_Receive is in progress */
+#define CY_SCB_UART_RECEIVE_ACTIVE (0x01UL)
+
+/**
+* The hardware RX FIFO was full and there was an attempt to write to it.
+* That additional data was dropped.
+*/
+#define CY_SCB_UART_RECEIVE_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk)
+
+/** The receive hardware detected a frame error, either a start or
+* stop bit error
+*/
+#define CY_SCB_UART_RECEIVE_ERR_FRAME (SCB_INTR_RX_FRAME_ERROR_Msk)
+
+/** The receive hardware detected a parity error */
+#define CY_SCB_UART_RECEIVE_ERR_PARITY (SCB_INTR_RX_PARITY_ERROR_Msk)
+
+/** The receive hardware detected a break transmission from transmitter */
+#define CY_SCB_UART_RECEIVE_BREAK_DETECT (SCB_INTR_RX_BREAK_DETECT_Msk)
+/** \} group_scb_uart_macros_receive_status */
+
+/**
+* \defgroup group_scb_uart_macros_transmit_status UART Transmit Status
+* \{
+* Macros to check current UART transmit status returned by
+* \ref Cy_SCB_UART_GetTransmitStatus function.
+* Each UART transmit status is encoded in a separate bit, therefore multiple bits
+* may be set to indicate the current status.
+*/
+
+/** The transmit operation started by \ref Cy_SCB_UART_Transmit is in progress */
+#define CY_SCB_UART_TRANSMIT_ACTIVE (0x01UL)
+
+/**
+* All data elements specified by \ref Cy_SCB_UART_Transmit have been loaded
+* into the TX FIFO
+*/
+#define CY_SCB_UART_TRANSMIT_IN_FIFO (0x02UL)
+
+/** SmartCard only: the transmitter received a NACK */
+#define CY_SCB_UART_TRANSMIT_NACK (SCB_INTR_TX_UART_NACK_Msk)
+
+/** SmartCard only: the transmitter lost arbitration */
+#define CY_SCB_UART_TRANSMIT_ARB_LOST (SCB_INTR_TX_UART_ARB_LOST_Msk)
+/** \} group_scb_uart_macros_transmit_status */
+
+/**
+* \defgroup group_scb_uart_macros_callback_events UART Callback Events
+* \{
+* Macros to check UART events passed by \ref cy_cb_scb_uart_handle_events_t callback.
+* Note that only single event is notified by the callback when it is called.
+*/
+
+/**
+* All data elements specified by \ref Cy_SCB_UART_Transmit have been loaded
+* into the TX FIFO
+*/
+#define CY_SCB_UART_TRANSMIT_IN_FIFO_EVENT (0x01UL)
+
+/** The transmit operation started by \ref Cy_SCB_UART_Transmit is complete */
+#define CY_SCB_UART_TRANSMIT_DONE_EVENT (0x02UL)
+
+/** The receive operation started by \ref Cy_SCB_UART_Receive is complete */
+#define CY_SCB_UART_RECEIVE_DONE_EVENT (0x04UL)
+
+/**
+* The ring buffer is full, there is no more space for additional data.
+* Additional data is stored in the RX FIFO until it becomes full, at which
+* point data is dropped.
+*/
+#define CY_SCB_UART_RB_FULL_EVENT (0x08UL)
+
+/**
+* An error was detected during the receive operation. This includes overflow,
+* frame error, or parity error. Check \ref Cy_SCB_UART_GetReceiveStatus to
+* determine the source of the error.
+*/
+#define CY_SCB_UART_RECEIVE_ERR_EVENT (0x10UL)
+
+/**
+* An error was detected during the transmit operation. This includes a NACK
+* or lost arbitration. Check \ref Cy_SCB_UART_GetTransmitStatus to determine
+* the source of the error
+*/
+#define CY_SCB_UART_TRANSMIT_ERR_EVENT (0x20UL)
+
+/** The receive fifo is not empty. To use this event the \ref CY_SCB_RX_INTR_NOT_EMPTY interrupt must be enabled by the user. */
+#define CY_SCB_UART_RECEIVE_NOT_EMTPY (0x40UL)
+
+/** The transmit fifo is empty. To use this event the \ref CY_SCB_UART_TX_EMPTY interrupt must be enabled by the user. */
+#define CY_SCB_UART_TRANSMIT_EMTPY (0x80UL)
+/** \} group_scb_uart_macros_callback_events */
+
+
+/** Data returned by the hardware when an empty RX FIFO is read */
+#define CY_SCB_UART_RX_NO_DATA (0xFFFFFFFFUL)
+
+
+/*******************************************************************************
+* Internal Constants
+*******************************************************************************/
+
+/** \cond INTERNAL */
+#define CY_SCB_UART_TX_INTR_MASK (CY_SCB_UART_TX_TRIGGER | CY_SCB_UART_TX_NOT_FULL | CY_SCB_UART_TX_EMPTY | \
+ CY_SCB_UART_TX_OVERFLOW | CY_SCB_UART_TX_UNDERFLOW | CY_SCB_UART_TX_DONE | \
+ CY_SCB_UART_TX_NACK | CY_SCB_UART_TX_ARB_LOST)
+
+#define CY_SCB_UART_RX_INTR_MASK (CY_SCB_UART_RX_TRIGGER | CY_SCB_UART_RX_NOT_EMPTY | CY_SCB_UART_RX_FULL | \
+ CY_SCB_UART_RX_OVERFLOW | CY_SCB_UART_RX_UNDERFLOW | CY_SCB_UART_RX_ERR_FRAME | \
+ CY_SCB_UART_RX_ERR_PARITY | CY_SCB_UART_RX_BREAK_DETECT)
+
+#define CY_SCB_UART_TX_INTR (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INTR_UART_ARB_LOST)
+
+#define CY_SCB_UART_RX_INTR (CY_SCB_RX_INTR_LEVEL | CY_SCB_RX_INTR_OVERFLOW | CY_SCB_RX_INTR_UART_FRAME_ERROR | \
+ CY_SCB_RX_INTR_UART_PARITY_ERROR | CY_SCB_RX_INTR_UART_BREAK_DETECT)
+
+#define CY_SCB_UART_RECEIVE_ERR (CY_SCB_RX_INTR_OVERFLOW | CY_SCB_RX_INTR_UART_FRAME_ERROR | \
+ CY_SCB_RX_INTR_UART_PARITY_ERROR)
+
+#define CY_SCB_UART_TRANSMIT_ERR (CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INTR_UART_ARB_LOST)
+
+#define CY_SCB_UART_INIT_KEY (0x00ABCDEFUL)
+
+#define CY_SCB_UART_IS_MODE_VALID(mode) ( (CY_SCB_UART_STANDARD == (mode)) || \
+ (CY_SCB_UART_SMARTCARD == (mode)) || \
+ (CY_SCB_UART_IRDA == (mode)) )
+
+#define CY_SCB_UART_IS_STOP_BITS_VALID(stopBits) ( (CY_SCB_UART_STOP_BITS_1 == (stopBits)) || \
+ (CY_SCB_UART_STOP_BITS_1_5 == (stopBits)) || \
+ (CY_SCB_UART_STOP_BITS_2 == (stopBits)) || \
+ (CY_SCB_UART_STOP_BITS_2_5 == (stopBits)) || \
+ (CY_SCB_UART_STOP_BITS_3 == (stopBits)) || \
+ (CY_SCB_UART_STOP_BITS_3_5 == (stopBits)) || \
+ (CY_SCB_UART_STOP_BITS_4 == (stopBits)) )
+
+#define CY_SCB_UART_IS_PARITY_VALID(parity) ( (CY_SCB_UART_PARITY_NONE == (parity)) || \
+ (CY_SCB_UART_PARITY_EVEN == (parity)) || \
+ (CY_SCB_UART_PARITY_ODD == (parity)) )
+
+#define CY_SCB_UART_IS_POLARITY_VALID(polarity) ( (CY_SCB_UART_ACTIVE_LOW == (polarity)) || \
+ (CY_SCB_UART_ACTIVE_HIGH == (polarity)) )
+
+#define CY_SCB_UART_IS_IRDA_LP_OVS_VALID(ovs) ( (CY_SCB_UART_IRDA_LP_OVS16 == (ovs)) || \
+ (CY_SCB_UART_IRDA_LP_OVS32 == (ovs)) || \
+ (CY_SCB_UART_IRDA_LP_OVS48 == (ovs)) || \
+ (CY_SCB_UART_IRDA_LP_OVS96 == (ovs)) || \
+ (CY_SCB_UART_IRDA_LP_OVS192 == (ovs)) || \
+ (CY_SCB_UART_IRDA_LP_OVS768 == (ovs)) || \
+ (CY_SCB_UART_IRDA_LP_OVS1536 == (ovs)) )
+
+#define CY_SCB_UART_IS_ADDRESS_VALID(addr) ((addr) <= 0xFFUL)
+#define CY_SCB_UART_IS_ADDRESS_MASK_VALID(mask) ((mask) <= 0xFFUL)
+#define CY_SCB_UART_IS_DATA_WIDTH_VALID(width) ( ((width) >= 5UL) && ((width) <= 9UL) )
+#define CY_SCB_UART_IS_OVERSAMPLE_VALID(ovs, mode, lpRx) ( ((CY_SCB_UART_STANDARD == (mode)) || (CY_SCB_UART_SMARTCARD == (mode))) ? \
+ (((ovs) >= 8UL) && ((ovs) <= 16UL)) : \
+ ((lpRx) ? CY_SCB_UART_IS_IRDA_LP_OVS_VALID(ovs) : true) )
+
+#define CY_SCB_UART_IS_RX_BREAK_WIDTH_VALID(base, width) ( ((width) >= (_FLD2VAL(SCB_RX_CTRL_DATA_WIDTH, (base)->RX_CTRL) + 3UL)) && \
+ ((width) <= 16UL) )
+#define CY_SCB_UART_IS_TX_BREAK_WIDTH_VALID(width) ( ((width) >= 4UL) && ((width) <= 16UL) )
+
+#define CY_SCB_UART_IS_MUTLI_PROC_VALID(mp, mode, width, parity) ( (mp) ? ((CY_SCB_UART_STANDARD == (mode)) && ((width) == 9UL) && \
+ (CY_SCB_UART_PARITY_NONE == (parity))) : true)
+/** \endcond */
+
+/** \} group_scb_uart_macros */
+
+
+/*******************************************************************************
+* In-line Function Implementation
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_uart_general_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Enable
+****************************************************************************//**
+*
+* Enables the SCB block for the UART operation.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_Enable(CySCB_Type *base)
+{
+ SCB_CTRL(base) |= SCB_CTRL_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_EnableCts
+****************************************************************************//**
+*
+* Enables the Clear to Send (CTS) input for the UART. The UART will not transmit
+* data while this signal is inactive.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_EnableCts(CySCB_Type *base)
+{
+ SCB_UART_FLOW_CTRL(base) |= SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_DisableCts
+****************************************************************************//**
+*
+* Disables the Clear to Send (CTS) input for the UART.
+* See \ref Cy_SCB_UART_EnableCts for the details.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_DisableCts(CySCB_Type *base)
+{
+ SCB_UART_FLOW_CTRL(base) &= (uint32_t) ~SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_SetRtsFifoLevel
+****************************************************************************//**
+*
+* Sets a level for the Ready To Send (RTS) signal activation.
+* When the number of data elements in the receive FIFO is below this level,
+* then the RTS output is active. Otherwise, the RTS signal is inactive.
+* To disable the RTS signal generation, set this level to zero.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param level
+* The level in the RX FIFO for RTS signal activation.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_SetRtsFifoLevel(CySCB_Type *base, uint32_t level)
+{
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level));
+
+ CY_REG32_CLR_SET(SCB_UART_FLOW_CTRL(base), SCB_UART_FLOW_CTRL_TRIGGER_LEVEL, level);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetRtsFifoLevel
+****************************************************************************//**
+*
+* Returns the level in the RX FIFO for the RTS signal activation.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \return
+* The level in the RX FIFO for RTS signal activation.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetRtsFifoLevel(CySCB_Type const *base)
+{
+ return _FLD2VAL(SCB_UART_FLOW_CTRL_TRIGGER_LEVEL, SCB_UART_FLOW_CTRL(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_EnableSkipStart
+****************************************************************************//**
+*
+* Enables the skip start-bit functionality.
+* When skip start is enabled the UART hardware does not synchronize to a
+* start bit but synchronizes to the first rising edge. To create a rising edge,
+* the first data bit must be a 1. This feature is useful when the start bit
+* falling edge is used to wake the device through a GPIO interrupt.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \note
+* When skip start-bit feature is enabled, it is applied (UART synchronizes
+* to the first rising edge after start bit) whenever the SCB is enabled.
+* This can cause incorrect UART synchronization and data reception when
+* the first data bit is not a 1. Therefore, disable the skip start-bit
+* when it should not be applied.
+* Note that SCB is disabled before enter Deep Sleep mode or after calling
+* \ref Cy_SCB_UART_Disable.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_EnableSkipStart(CySCB_Type *base)
+{
+ SCB_UART_RX_CTRL(base) |= SCB_UART_RX_CTRL_SKIP_START_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_DisableSkipStart
+****************************************************************************//**
+*
+* Disable the skip start-bit functionality.
+* See \ref Cy_SCB_UART_EnableSkipStart for the details.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_DisableSkipStart(CySCB_Type *base)
+{
+ SCB_UART_RX_CTRL(base) &= (uint32_t) ~SCB_UART_RX_CTRL_SKIP_START_Msk;
+}
+/** \} group_scb_uart_general_functions */
+
+
+/**
+* \addtogroup group_scb_uart_low_level_functions
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Get
+****************************************************************************//**
+*
+* Reads a single data element from the UART RX FIFO.
+* This function does not check whether the RX FIFO has data before reading it.
+* If the RX FIFO is empty, the function returns \ref CY_SCB_UART_RX_NO_DATA.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \return
+* Data from the RX FIFO.
+* The data element size is defined by the configured data width.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_Get(CySCB_Type const *base)
+{
+ return Cy_SCB_ReadRxFifo(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetArray
+****************************************************************************//**
+*
+* Reads an array of data out of the UART RX FIFO.
+* This function does not block. It returns how many data elements were read
+* from the RX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* The pointer to the location to place the data read from the RX FIFO.
+* The element size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to read from the RX FIFO.
+*
+* \return
+* The number of data elements read from the RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetArray(CySCB_Type const *base, void *buffer, uint32_t size)
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ return Cy_SCB_ReadArray(base, buffer, size);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetArrayBlocking
+****************************************************************************//**
+*
+* Reads an array of data out of the UART RX FIFO.
+* This function blocks until the number of data elements specified by the
+* size has been read from the RX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* The pointer to the location to place the data read from the RX FIFO.
+* The element size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to read from the RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_GetArrayBlocking(CySCB_Type const *base, void *buffer, uint32_t size)
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ Cy_SCB_ReadArrayBlocking(base, buffer, size);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetRxFifoStatus
+****************************************************************************//**
+*
+* Returns the current status of the RX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \return
+* \ref group_scb_uart_macros_rx_fifo_status
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetRxFifoStatus(CySCB_Type const *base)
+{
+ return (Cy_SCB_GetRxInterruptStatus(base) & CY_SCB_UART_RX_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_ClearRxFifoStatus
+****************************************************************************//**
+*
+* Clears the selected statuses of the RX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param clearMask
+* The mask whose statuses to clear.
+* See \ref group_scb_uart_macros_rx_fifo_status for the set of constants.
+*
+* \note
+* * This status is also used for interrupt generation, so clearing it also
+* clears the interrupt sources.
+* * Level-sensitive statuses such as \ref CY_SCB_UART_RX_TRIGGER,
+* \ref CY_SCB_UART_RX_NOT_EMPTY and \ref CY_SCB_UART_RX_FULL are set high again after
+* being cleared if the condition remains true.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_ClearRxFifoStatus(CySCB_Type *base, uint32_t clearMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_UART_RX_INTR_MASK));
+
+ Cy_SCB_ClearRxInterrupt(base, clearMask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetNumInRxFifo
+****************************************************************************//**
+*
+* Returns the number of data elements in the UART RX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \return
+* The number of data elements in the RX FIFO.
+* The size of date element defined by the configured data width.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInRxFifo(CySCB_Type const *base)
+{
+ return Cy_SCB_GetNumInRxFifo(base);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_ClearRxFifo
+****************************************************************************//**
+*
+* Clears all data out of the UART RX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \sideeffect
+* Any data currently in the shifter is cleared and lost.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_ClearRxFifo(CySCB_Type *base)
+{
+ Cy_SCB_ClearRxFifo(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Put
+****************************************************************************//**
+*
+* Places a single data element in the UART TX FIFO.
+* This function does not block and returns how many data elements were placed
+* in the TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param data
+* Data to put in the TX FIFO.
+* The element size is defined by the data type, which depends on the configured
+* data width.
+*
+* \return
+* The number of data elements placed in the TX FIFO: 0 or 1.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_Put(CySCB_Type *base, uint32_t data)
+{
+ return Cy_SCB_Write(base, data);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_PutArray
+****************************************************************************//**
+*
+* Places an array of data in the UART TX FIFO.
+* This function does not block. It returns how many data elements were
+* placed in the TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* The pointer to data to place in the TX FIFO.
+* The element size is defined by the data type, which depends on the configured
+* TX data width.
+*
+* \param size
+* The number of data elements to TX.
+*
+* \return
+* The number of data elements placed in the TX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_PutArray(CySCB_Type *base, void *buffer, uint32_t size)
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ return Cy_SCB_WriteArray(base, buffer, size);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_PutArrayBlocking
+****************************************************************************//**
+*
+* Places an array of data in the UART TX FIFO.
+* This function blocks until the number of data elements specified by the size
+* is placed in the TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* The pointer to data to place in the TX FIFO.
+* The element size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to write into the TX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_PutArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size)
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ Cy_SCB_WriteArrayBlocking(base, buffer, size);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_PutString
+****************************************************************************//**
+*
+* Places a NULL terminated string in the UART TX FIFO.
+* This function blocks until the entire string is placed in the TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param string
+* The pointer to the null terminated string array.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_PutString(CySCB_Type *base, char_t const string[])
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(string, 1UL));
+
+ Cy_SCB_WriteString(base, string);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetTxFifoStatus
+****************************************************************************//**
+*
+* Returns the current status of the TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \return
+* \ref group_scb_uart_macros_tx_fifo_status
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetTxFifoStatus(CySCB_Type const *base)
+{
+ return (Cy_SCB_GetTxInterruptStatus(base) & CY_SCB_UART_TX_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_ClearTxFifoStatus
+****************************************************************************//**
+*
+* Clears the selected statuses of the TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param clearMask
+* The mask whose statuses to clear.
+* See \ref group_scb_uart_macros_tx_fifo_status for the set of constants.
+*
+* \note
+* * The status is also used for interrupt generation, so clearing it also
+* clears the interrupt sources.
+* * Level-sensitive statuses such as \ref CY_SCB_UART_TX_TRIGGER,
+* \ref CY_SCB_UART_TX_EMPTY and \ref CY_SCB_UART_TX_NOT_FULL are set high again after
+* being cleared if the condition remains true.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_ClearTxFifoStatus(CySCB_Type *base, uint32_t clearMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_UART_TX_INTR_MASK));
+
+ Cy_SCB_ClearTxInterrupt(base, clearMask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetNumInTxFifo
+****************************************************************************//**
+*
+* Returns the number of data elements in the UART TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \return
+* The number of data elements in the TX FIFO.
+* The size of date element defined by the configured data width.
+*
+* \note
+* This number does not include any data currently in the TX shifter.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInTxFifo(CySCB_Type const *base)
+{
+ return Cy_SCB_GetNumInTxFifo(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_IsTxComplete
+****************************************************************************//**
+*
+* Checks whether the TX FIFO and Shifter are empty and there is no more data to send
+*
+* \param base
+* Pointer to the UART SCB instance.
+*
+* \return
+* If true, transmission complete. If false, transmission is not complete.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SCB_UART_IsTxComplete(CySCB_Type const *base)
+{
+ return Cy_SCB_IsTxComplete(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_ClearTxFifo
+****************************************************************************//**
+*
+* Clears all data out of the UART TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \sideeffect
+* The TX FIFO clear operation also clears the shift register, so that
+* the shifter could be cleared in the middle of a data element transfer,
+* corrupting it. The data element corruption means that all bits that have
+* not been transmitted are transmitted as 1s on the bus.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_ClearTxFifo(CySCB_Type *base)
+{
+ Cy_SCB_ClearTxFifo(base);
+}
+/** \} group_scb_uart_low_level_functions */
+
+/**
+* \addtogroup group_scb_uart_interrupt_functions
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_RegisterCallback
+****************************************************************************//**
+*
+* Registers a callback function that notifies that
+* \ref group_scb_uart_macros_callback_events occurred in the
+* \ref Cy_SCB_UART_Interrupt.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param callback
+* The pointer to the callback function.
+* See \ref cy_cb_scb_uart_handle_events_t for the function prototype.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user should not modify anything
+* in this structure.
+*
+* \note
+* To remove the callback, pass NULL as the pointer to the callback function.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_RegisterCallback(CySCB_Type const *base,
+ cy_cb_scb_uart_handle_events_t callback, cy_stc_scb_uart_context_t *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ context->cbEvents = callback;
+}
+/** \} group_scb_uart_interrupt_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** \} group_scb_uart */
+
+#endif /* (CY_IP_MXSCB) */
+
+#endif /* (CY_SCB_UART_H) */
+/* [] END OF FILE */
+
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_smif.h b/platform/ext/target/psoc64/Native_Driver/include/cy_smif.h
new file mode 100644
index 0000000000..0bbdacd992
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_smif.h
@@ -0,0 +1,1621 @@
+/***************************************************************************//**
+* \file cy_smif.h
+* \version 1.40
+*
+* Provides an API declaration of the Cypress SMIF driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_smif
+* \{
+* The SPI-based communication interface for external memory devices.
+*
+* The functions and other declarations used in this driver are in cy_smif.h and
+* cy_smif_memslot.h (if used). If you are using the ModusToolbox QSPI Configurator,
+* also include cycfg_qspi_memslot.h.
+*
+* SMIF: Serial Memory Interface: This IP block implements an SPI-based
+* communication interface for interfacing external memory devices to PSoC. The SMIF
+* supports Octal-SPI, Dual Quad-SPI, Quad-SPI, Dual-SPI, and SPI.
+*
+* Features
+* - Standard SPI Master interface
+* - Supports Single/Dual/Quad/Octal SPI Memories
+* - Supports Dual-Quad SPI mode
+* - Design-time configurable support for multiple (up to 4) external serial
+* memory devices
+* - eXecute-In-Place (XIP) operation mode for both read and write accesses
+* with 4KB XIP read cache and on-the-fly encryption and decryption
+* - Supports external serial memory initialization via
+* <a href="https://www.jedec.org/standards-documents/docs/jesd216b" target="_blank">
+* Serial Flash Discoverable Parameters (SFDP)</a> standard
+*
+* The primary usage model for the SMIF is that of an external memory interface.
+* The SMIF is capable of interfacing with different types of memory, up to four
+* types.
+*
+* \b SMIF driver is divided into three layers
+* - cy_smif.h API
+* - cy_smif_memslot.h API
+* - SMIF configuration structures
+*
+* The SMIF API is divided into the low-level functions and memory-slot functions. Use
+* the low level API for the SMIF block initialization and for implementing a generic
+* SPI communication interface using the SMIF block.
+*
+* The memory slot API has functions to implement the basic memory operations such as
+* program, read, erase etc. These functions are implemented using the memory
+* parameters in the memory device configuration data structure. The
+* Cy_SMIF_MemInit() API initializes all the memory slots based on the settings
+* in the array.
+*
+* \image html smif_1_0_p01_layers.png
+*
+* SMIF Configuration Tool is a stand-alone application, which is a part of PDL
+* (Creator) and could be found in \<PDL_DIR\>/tools/\<OS_DIR\>/SMIFConfigurationTool
+* (e.g. for PDL 3.0.0 and Windows OS PDL/3.0.0/tools/win/SMIFConfigurationTool).
+*
+* In ModusToolbox this tool is called QSPI Configurator. QSPI Configurator is a part of
+* PSoC 6 Software Library and can be found in \<ModusToolbox\>/tools/qspi-configurator-1.1
+*
+* Tool generates *.c and *.h file with configuration structures. These configuration
+* structures are input parameters for cy_smif_memslot API level
+*
+* \warning The driver is not responsible for external memory persistence. You cannot edit
+* a buffer during the Read/Write operations. If there is a memory error, the SMIF ip block
+* can require a reset. To determine if this has happened, check the SMIF
+* busy status using Cy_SMIF_BusyCheck() and implement a timeout. Reset the SMIF
+* block by toggling CTL.ENABLED. Then reconfigure the SMIF block.
+*
+* For the Write operation, check that the SMIF driver has completed
+* transferring by calling Cy_SMIF_BusyCheck(). Also, check that the memory is
+* available with Cy_SMIF_MemIsBusy() before proceeding.
+*
+* Simple example of external flash memory programming using low level SMIF API.
+* All steps mentioned in example below are incorporated in
+* \ref Cy_SMIF_MemCmdWriteEnable(), \ref Cy_SMIF_MemCmdProgram(), and
+* \ref Cy_SMIF_MemIsBusy() of the
+* \ref group_smif_mem_slot_functions "memory slot level API".
+* \warning Example is simplified, without checks of error conditions.
+* \note Flash memories need erase operation before programming. Refer to
+* external memory datasheet for specific memory commands.
+*
+* \snippet smif/snippet/main.c SMIF_API: Write example
+*
+* For the Read operation, before accessing the read buffer, check that it is ready
+* by calling Cy_SMIF_GetTxFifoStatus().
+*
+* Simple example of external flash memory read using low level SMIF API. All
+* steps mentioned in example below are incorporated in
+* \ref Cy_SMIF_MemCmdRead() of the
+* \ref group_smif_mem_slot_functions "memory slot level API".
+* \warning Example is simplified, without checks of error conditions.
+* \note Refer to external memory datasheet for specific memory commands.
+*
+* \snippet smif/snippet/main.c SMIF_API: Read example
+*
+* The user should invalidate the cache by calling Cy_SMIF_CacheInvalidate() when
+* switching from the MMIO mode to XIP mode.
+*
+* \section group_smif_configuration Configuration Considerations
+*
+* PDL API has common parameters: base, context, config described in
+* \ref page_getting_started_pdl_design "PDL Design" section.
+*
+* See the documentation for Cy_SMIF_Init() and Cy_SMIF_MemInit() for details
+* on the required configuration structures and other initialization topics.
+*
+* The normal (MMIO) mode is used for implementing a generic SPI/DSPI/QSPI/Dual
+* Quad-SPI/Octal-SPI communication interface using the SMIF block. This
+* interface can be used to implement special commands like Program/Erase of
+* flash, memory device configuration, sleep mode entry for memory devices or
+* other special commands specific to the memory device. The transfer width
+* (SPI/DSP/Quad-SPI/Octal-SPI) of a transmission is a parameter set for each
+* transmit/receive operation. So these can be changed at run time.
+*
+* In a typical memory interface with flash memory, the SMIF is used in the
+* memory mode when reading from the memory and it switches to the normal mode when
+* writing to flash memory.
+* A typical memory device has multiple types of commands.
+*
+* The SMIF interface can be used to transmit different types of commands. Each
+* command has different phases: command, dummy cycles, and transmit and receive
+* data which require separate APIs.
+*
+* \subsection group_smif_init SMIF Initialization
+* Create interrupt function and allocate memory for SMIF context
+* structure
+* \snippet smif/snippet/main.c SMIF_INIT: context and interrupt
+* SMIF driver initialization for low level API usage (cysmif.h)
+* \snippet smif/snippet/main.c SMIF_INIT: low level
+* Additional steps to initialize SMIF driver for memory slot level API usage
+* (cy_smif_memslot.h).
+* \snippet smif/snippet/main.c SMIF_INIT: memslot level
+* \note Example does not include initialization of all needed configuration
+* structures (\ref cy_stc_smif_mem_device_cfg_t, \ref cy_stc_smif_mem_cmd_t).
+* SMIF/QSPI Configuration tool generates all configuration structures needed for
+* memslot level API usage.
+*
+* \subsection group_smif_xip_init SMIF XIP Initialization
+* The eXecute In Place (XIP) is a mode of operation where read or write commands
+* to the memory device are directed through the SMIF without any use of API
+* function calls. In this mode the SMIF block maps the AHB bus-accesses to
+* external memory device addresses to make it behave similar to internal memory.
+* This allows the CPU to execute code directly from external memory. This mode
+* is not limited to code and is suitable also for data read and write accesses.
+* The memory regions available for XIP addresses allocation are defined
+* in a linker script file (.ld).
+* \snippet smif/snippet/main.c SMIF_INIT: XIP
+* \note Example of input parameters initialization is in \ref group_smif_init
+* section.
+* \warning Functions that called from external memory should be declared with
+* long call attribute.
+*
+* \subsection group_smif_usage_rules Rules for PSoC6 QSPI/SMIF Block Usage
+* 1. All operations must use one or more dummy cycles between the PSoC 6 Command
+* and Address phase (when the PSoC 6 MCU drives the data pins) and the device's
+* Response phase (when the device drives the same data pins). Bus contention may
+* occur if no (zero) dummy cycles are used.
+* 2. Any transfer that does not allow dummy cycles (such as Register Status
+* Reads) must use the single-bit transfer mode. In single-bit mode, the PSoC 6
+* drives the Command on the Data0 line and the device responds on the Data1
+* line, so bus contention cannot occur.
+*
+* \section group_smif_more_information More Information
+*
+* More information regarding the Serial Memory Interface can be found in the component
+* datasheet and the Technical Reference Manual (TRM).
+* More information regarding the SMIF Configuration Tool are in SMIF
+* Configuration Tool User Guide located in \<PDL_DIR\>/tools/\<OS_DIR\>/SMIFConfigurationTool/
+* folder
+*
+* \section group_smif_MISRA MISRA-C Compliance]
+* <table class="doxtable">
+* <tr>
+* <th>MISRA rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>The cast is be performed between a pointer to the object type and a different pointer to the object type.</td>
+* <td>The cast from the pointer to void to the pointer to an unsigned integer does not have any unintended effect, as
+* it is a consequence of the definition of a structure based on hardware registers.</td>
+* </tr>
+* <tr>
+* <td>11.5</td>
+* <td>R</td>
+* <td>Not performed, the cast that removes any const or volatile qualification from the type addressed by a pointer.</td>
+* <td>The removal of the volatile qualification inside the function has no side effects.</td>
+* </tr>
+* </table>
+*
+* \section group_smif_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td rowspan="5">1.40</td>
+* <td>The following functions are renamed:\n
+* Cy_SMIF_GetTxfrStatus into Cy_SMIF_GetTransferStatus;\n
+* Cy_SMIF_Memslot_Init into Cy_SMIF_MemInit;\n
+* Cy_SMIF_Memslot_DeInit into Cy_SMIF_MemDeInit;\n
+* Cy_SMIF_Memslot_CmdWriteEnable into Cy_SMIF_MemCmdWriteEnable;\n
+* Cy_SMIF_Memslot_CmdWriteDisable into Cy_SMIF_MemCmdWriteDisable;\n
+* Cy_SMIF_Memslot_IsBusy into Cy_SMIF_MemIsBusy;\n
+* Cy_SMIF_Memslot_QuadEnable into Cy_SMIF_MemQuadEnable;\n
+* Cy_SMIF_Memslot_CmdReadSts into Cy_SMIF_MemCmdReadStatus;\n
+* Cy_SMIF_Memslot_CmdWriteSts into Cy_SMIF_MemCmdWriteStatus;\n
+* Cy_SMIF_Memslot_CmdChipErase into Cy_SMIF_MemCmdChipErase;\n
+* Cy_SMIF_Memslot_CmdSectorErase into Cy_SMIF_MemCmdSectorErase;\n
+* Cy_SMIF_Memslot_SfdpDetect into Cy_SMIF_MemSfdpDetect;\n
+* Cy_SMIF_Memslot_CmdProgram into Cy_SMIF_MemCmdProgram;\n
+* Cy_SMIF_Memslot_CmdRead into Cy_SMIF_MemCmdRead.\n
+* The following ENUMa are renamed:\n
+* CY_SMIF_SEND_CMPLT into CY_SMIF_SEND_COMPLETE;\n
+* CY_SMIF_REC_CMPLT into CY_SMIF_RX_COMPLETE;\n
+* CY_SMIF_REC_BUSY into CY_SMIF_RX_BUSY;\n
+* CY_SMIF_SEL_INV_INTERNAL_CLK into CY_SMIF_SEL_INVERTED_INTERNAL_CLK;\n
+* CY_SMIF_SEL_INV_FEEDBACK_CLK into CY_SMIF_SEL_INVERTED_FEEDBACK_CLK;\n
+* cy_en_smif_cache_en_t into cy_en_smif_cache_t.\n
+* The following MACROs are renamed:\n
+* CY_SMIF_FLAG_WR_EN into CY_SMIF_FLAG_WRITE_ENABLE;\n
+* CY_SMIF_FLAG_CRYPTO_EN into CY_SMIF_FLAG_CRYPTO_ENABLE;\n
+* CY_SMIF_SFDP_SING_BYTE_00 into CY_SMIF_SFDP_SIGNATURE_BYTE_00;\n
+* CY_SMIF_SFDP_SING_BYTE_01 into CY_SMIF_SFDP_SIGNATURE_BYTE_01;\n
+* CY_SMIF_SFDP_SING_BYTE_02 into CY_SMIF_SFDP_SIGNATURE_BYTE_02;\n
+* CY_SMIF_SFDP_SING_BYTE_03 into CY_SMIF_SFDP_SIGNATURE_BYTE_03;\n
+* CY_SMIF_WR_STS_REG1_CMD into CY_SMIF_WRITE_STATUS_REG1_CMD;\n
+* CY_SMIF_WR_DISABLE_CMD into CY_SMIF_WRITE_DISABLE_CMD;\n
+* CY_SMIF_RD_STS_REG1_CMD into CY_SMIF_READ_STATUS_REG1_CMD;\n
+* CY_SMIF_WR_ENABLE_CMD into CY_SMIF_WRITE_ENABLE_CMD;\n
+* CY_SMIF_RD_STS_REG2_T1_CMD into CY_SMIF_READ_STATUS_REG2_T1_CMD;\n
+* CY_SMIF_WR_STS_REG2_CMD into CY_SMIF_WRITE_STATUS_REG2_CMD;\n
+* CY_SMIF_RD_STS_REG2_T2_CMD into CY_SMIF_READ_STATUS_REG2_T2_CMD;\n
+* CY_SMIF_QE_BIT_STS_REG2_T1 into CY_SMIF_QE_BIT_STATUS_REG2_T1;\n
+* CY_SMIF_STS_REG_BUSY_MASK into CY_SMIF_STATUS_REG_BUSY_MASK.\n
+* </td>
+* <td rowspan="2">Documentation improvement.</td>
+* </tr>
+* <tr>
+* <td>Updated the description of the Cy_SMIF_MemInit() function.
+* Updated the Cy_SMIF_Encrypt() function usage example.
+* </td>
+* </tr>
+* <tr>
+* <td>The type of arguments that are not modified by the functions are set to const.
+* </td>
+* <td>Usability improvement.
+* </td>
+* </tr>
+* <tr>
+* <td>The Cy_SMIF_MemSfdpDetect() function is updated to support new
+* commands for 4 bytes addressing.
+* </td>
+* <td>Memory devices with new 4 byte addressing commands support.
+* </td>
+* </tr>
+* <tr>
+* <td>Added the blocking functions which take care of the
+* busy-status check of the memory:
+* - \ref Cy_SMIF_MemIsReady
+* - \ref Cy_SMIF_MemIsQuadEnabled
+* - \ref Cy_SMIF_MemEnableQuadMode
+* - \ref Cy_SMIF_MemRead
+* - \ref Cy_SMIF_MemWrite
+* - \ref Cy_SMIF_MemEraseSector
+* - \ref Cy_SMIF_MemEraseChip
+* </td>
+* <td>Added new high-level blocking functions.
+* </td>
+* </tr>
+* <tr>
+* <td rowspan="5">1.30</td>
+* <td>The CY_SMIF_CMD_FIFO_WR_RX_COUNT_Msk value is changed to 0x0000FFFFUL.</td>
+* <td rowspan="4">Driver maintenance.</td>
+* </tr>
+* <tr>
+* <td>Added the check of the size parameter in the Cy_SMIF_TransmitData() function.</td>
+* </tr>
+* <tr>
+* <td>Added conditional check for presence of the SMIF hardware IP.</td>
+* </tr>
+* <tr>
+* <td>Fixed the wrong erase command in the SFDP protocol for devices with Erase Type 3.</td>
+* </tr>
+* <tr>
+* <td>Updated the General Description section with minor changes.
+* Updated the ordering of the parameters descriptions for some functions.
+* Added the text saying that the Cy_SMIF_MemInit() function is applicable
+* to use the external memory as memory-mapped to PSoC (XIP mode).
+* Added the snippet for the Cy_SMIF_Encrypt() function to show how to use this function.
+* Added below the picture in the Low-Level Functions section the sequence of PDL
+* functions required in a Read or Write transaction.
+* Added the text below the picture about the address.
+* Updated DUMMY COUNT in this picture.
+* Added checking of the size parameter in the Cy_SMIF_TransmitData() function.
+* </td>
+* <td>Documentation improvement.</td>
+* </tr>
+* <tr>
+* <td>1.20.1</td>
+* <td>Added upper limit to size parameter in several functions.</td>
+* <td>Documentation improvement.</td>
+* </tr>
+* <tr>
+* <td rowspan="3">1.20</td>
+* <td>Flattened the organization of the driver source code into the single
+* source directory and the single include directory.
+* </td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Added a new return status and transfer width option for the case when the memory command is not supported.</td>
+* <td>Improved the memory command structure usability.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td rowspan="2">1.11</td>
+* <td>Fixed internal function that writes to the SMIF FIFO</td>
+* <td>The write function stuck in the loop when write speed in external
+* memory is significantly lower than PSoC CPU core speed and write
+* transfer is not finished during the single function call.
+* </td>
+* </tr>
+* <tr>
+* <td>Added optional mode part to the program command flow</td>
+* <td>Extend usability of program command</td>
+* </tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Added Low Power Callback section</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.10</td>
+* <td>Fix write to external memory from CM0+ core. Add checks of API input parameters.
+* Minor documentation updates</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_smif_macros Macros
+* \{
+* \defgroup group_smif_macros_status Status Macros
+* \defgroup group_smif_macros_cmd Command Macros
+* \defgroup group_smif_macros_flags External Memory Flags
+* \defgroup group_smif_macros_sfdp SFDP Macros
+* \defgroup group_smif_macros_isr Interrupt Macros
+* \}
+* \defgroup group_smif_functions Functions
+* \{
+* \defgroup group_smif_low_level_functions Low Level Functions
+* \{
+* Basic flow for read/write commands using \ref Cy_SMIF_TransmitCommand,
+* \ref Cy_SMIF_TransmitData, \ref Cy_SMIF_ReceiveData and
+* \ref Cy_SMIF_SendDummyCycles
+*
+* \image html smif_1_0_p03_rw_cmd.png
+*
+* The sequence of the PDL functions required in a read or write transaction is:
+* \ref Cy_SMIF_TransmitCommand() ->
+* \ref Cy_SMIF_SendDummyCycles() ->
+* \ref Cy_SMIF_ReceiveData() / \ref Cy_SMIF_TransmitData() ->
+* \ref Cy_SMIF_BusyCheck().
+* The address is sent as part of the Cy_SMIF_TransmitCommand() function.
+* No separate function call is required.
+*
+* \}
+* \defgroup group_smif_mem_slot_functions Memory Slot Functions
+* \defgroup group_smif_functions_syspm_callback Low Power Callback
+* \}
+* \defgroup group_smif_data_structures Data Structures
+* \{
+* \defgroup group_smif_data_structures_memslot SMIF Memory Description Structures
+* General hierarchy of memory structures are:
+* \image html smif_1_0_p02_memslot_stc.png
+* Top structure is \ref cy_stc_smif_block_config_t, which could have links up to
+* 4 \ref cy_stc_smif_mem_config_t which describes each connected to the SMIF
+* external memory.
+* \}
+* \defgroup group_smif_enums Enumerated Types
+*/
+
+#if !defined(CY_SMIF_H)
+#define CY_SMIF_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include "cy_syspm.h"
+
+
+#ifdef CY_IP_MXSMIF
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/***************************************
+* Constants
+****************************************/
+
+/**
+* \addtogroup group_smif_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_SMIF_DRV_VERSION_MAJOR 1
+
+/** The driver minor version */
+#define CY_SMIF_DRV_VERSION_MINOR 40
+
+/** One microsecond timeout for Cy_SMIF_TimeoutRun() */
+#define CY_SMIF_WAIT_1_UNIT (1U)
+
+/** The SMIF driver ID, reported as part of an unsuccessful API return status
+ * \ref cy_en_smif_status_t */
+#define CY_SMIF_ID CY_PDL_DRV_ID(0x2CU)
+
+
+/**
+* \addtogroup group_smif_macros_isr
+* \{
+*/
+
+/** Enable XIP_ALIGNMENT_ERROR interrupt see TRM for details */
+#define CY_SMIF_ALIGNMENT_ERROR (SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk)
+/** Enable RX_DATA_FIFO_UNDERFLOW interrupt see TRM for details */
+#define CY_SMIF_RX_DATA_FIFO_UNDERFLOW (SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk)
+/** Enable TX_DATA_FIFO_OVERFLOW interrupt see TRM for details */
+#define CY_SMIF_TX_DATA_FIFO_OVERFLOW (SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk)
+/** Enable TX_CMD_FIFO_OVERFLOW interrupt see TRM for details */
+#define CY_SMIF_TX_COMMAND_FIFO_OVERFLOW (SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk)
+/** Enable TR_TX_REQ interrupt see TRM for details */
+#define CY_SMIF_TX_DATA_FIFO_LEVEL_TRIGGER (SMIF_INTR_TR_TX_REQ_Msk)
+/** Enable TR_RX_REQ interrupt see TRM for details */
+#define CY_SMIF_RX_DATA_FIFO_LEVEL_TRIGGER (SMIF_INTR_TR_RX_REQ_Msk)
+
+/** \} group_smif_macros_isr */
+
+/** \cond INTERNAL */
+
+#define CY_SMIF_CMD_FIFO_TX_MODE (0UL)
+#define CY_SMIF_CMD_FIFO_TX_COUNT_MODE (1UL)
+#define CY_SMIF_CMD_FIFO_RX_COUNT_MODE (2UL)
+#define CY_SMIF_CMD_FIFO_DUMMY_COUNT_MODE (3UL)
+
+#define CY_SMIF_TX_CMD_FIFO_STATUS_RANGE (4U)
+#define CY_SMIF_TX_DATA_FIFO_STATUS_RANGE (8U)
+#define CY_SMIF_RX_DATA_FIFO_STATUS_RANGE (8U)
+
+#define CY_SMIF_ONE_BYTE (1U)
+#define CY_SMIF_TWO_BYTES (2U)
+#define CY_SMIF_THREE_BYTES (3U)
+#define CY_SMIF_FOUR_BYTES (4U)
+#define CY_SMIF_FIVE_BYTES (5U)
+#define CY_SMIF_SIX_BYTES (6U)
+#define CY_SMIF_SEVEN_BYTES (7U)
+#define CY_SMIF_EIGHT_BYTES (8U)
+
+#define CY_SMIF_CRYPTO_FIRST_WORD (0U)
+#define CY_SMIF_CRYPTO_SECOND_WORD (4U)
+#define CY_SMIF_CRYPTO_THIRD_WORD (8U)
+#define CY_SMIF_CRYPTO_FOURTH_WORD (12U)
+
+#define CY_SMIF_CRYPTO_START (1UL)
+#define CY_SMIF_CRYPTO_COMPLETED (0UL)
+#define CY_SMIF_CRYPTO_ADDR_MASK (0xFFFFFFF0UL)
+#define CY_SMIF_AES128_BYTES (16U)
+
+#define CY_SMIF_CTL_REG_DEFAULT (0x00000300U) /* 3 - [13:12] CLOCK_IF_RX_SEL */
+
+#define CY_SMIF_SFDP_FAIL (0x08U)
+#define CY_SMIF_SFDP_FAIL_SS0_POS (0x00U)
+#define CY_SMIF_SFDP_FAIL_SS1_POS (0x01U)
+#define CY_SMIF_SFDP_FAIL_SS2_POS (0x02U)
+#define CY_SMIF_SFDP_FAIL_SS3_POS (0x03U)
+
+#define CY_SMIF_MAX_DESELECT_DELAY (7U)
+#define CY_SMIF_MAX_TX_TR_LEVEL (8U)
+#define CY_SMIF_MAX_RX_TR_LEVEL (8U)
+
+#define CY_SMIF_MODE_VALID(mode) ((CY_SMIF_NORMAL == (cy_en_smif_mode_t)(mode)) || \
+ (CY_SMIF_MEMORY == (cy_en_smif_mode_t)(mode)))
+#define CY_SMIF_BLOCK_EVENT_VALID(event) ((CY_SMIF_BUS_ERROR == (cy_en_smif_error_event_t)(event)) || \
+ (CY_SMIF_WAIT_STATES == (cy_en_smif_error_event_t)(event)))
+#define CY_SMIF_CLOCK_SEL_VALID(clkSel) ((CY_SMIF_SEL_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
+ (CY_SMIF_SEL_INVERTED_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
+ (CY_SMIF_SEL_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
+ (CY_SMIF_SEL_INVERTED_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)))
+
+#define CY_SMIF_DESELECT_DELAY_VALID(delay) ((delay) <= CY_SMIF_MAX_DESELECT_DELAY)
+#define CY_SMIF_SLAVE_SEL_VALID(ss) ((CY_SMIF_SLAVE_SELECT_0 == (ss)) || \
+ (CY_SMIF_SLAVE_SELECT_1 == (ss)) || \
+ (CY_SMIF_SLAVE_SELECT_2 == (ss)) || \
+ (CY_SMIF_SLAVE_SELECT_3 == (ss)))
+#define CY_SMIF_DATA_SEL_VALID(ss) ((CY_SMIF_DATA_SEL0 == (ss)) || \
+ (CY_SMIF_DATA_SEL1 == (ss)) || \
+ (CY_SMIF_DATA_SEL2 == (ss)) || \
+ (CY_SMIF_DATA_SEL3 == (ss)))
+#define CY_SMIF_TXFR_WIDTH_VALID(width) ((CY_SMIF_WIDTH_SINGLE == (width)) || \
+ (CY_SMIF_WIDTH_DUAL == (width)) || \
+ (CY_SMIF_WIDTH_QUAD == (width)) || \
+ (CY_SMIF_WIDTH_OCTAL == (width)) || \
+ (CY_SMIF_WIDTH_NA == (width)))
+#define CY_SMIF_CMD_PARAM_VALID(param, paramSize) (((paramSize) > 0U)? (NULL != (param)) : (true))
+
+#define CY_SMIF_WIDTH_NA_VALID(paramWidth, paramSize) (((paramSize) > 0U)? \
+ (CY_SMIF_WIDTH_NA != (paramWidth)) : (true))
+
+#define CY_SMIF_BUFFER_SIZE_MAX (65536UL)
+#define CY_SMIF_BUF_SIZE_VALID(size) (((CY_SMIF_BUFFER_SIZE_MAX) >= (size)) && ((0UL) < (size)))
+
+/***************************************
+* Command FIFO Register
+***************************************/
+
+/* SMIF->TX_CMD_FIFO_WR */
+#define CY_SMIF_TX_CMD_FIFO_WR_MODE_POS (18U) /* [19:18] Command data mode */
+#define CY_SMIF_TX_CMD_FIFO_WR_WIDTH_POS (16U) /* [17:16] Transfer width */
+#define CY_SMIF_TX_CMD_FIFO_WR_LAST_BYTE_POS (15U) /* [15] Last byte */
+#define CY_SMIF_TX_CMD_FIFO_WR_SS_POS (8U) /* [11:8] Slave select */
+#define CY_SMIF_TX_CMD_FIFO_WR_TXDATA_POS (0U) /* [0] Transmitted byte */
+#define CY_SMIF_TX_CMD_FIFO_WR_DUMMY_POS (0U) /* [0] Dummy count */
+#define CY_SMIF_TX_CMD_FIFO_WR_TX_COUNT_POS (0U) /* [0] TX count */
+#define CY_SMIF_TX_CMD_FIFO_WR_RX_COUNT_POS (0U) /* [0] RX count */
+
+/* SMIF->TX_CMD_FIFO_WR Commands Fields */
+#define CY_SMIF_CMD_FIFO_WR_MODE_Pos (18UL) /* [19:18] Command data mode */
+#define CY_SMIF_CMD_FIFO_WR_MODE_Msk (0x000C0000UL) /* DATA[19:18] Command data mode */
+
+#define CY_SMIF_CMD_FIFO_WR_WIDTH_Pos (16UL) /* [17:16] Transfer width */
+#define CY_SMIF_CMD_FIFO_WR_WIDTH_Msk (0x00030000UL) /* DATA[17:16] Transfer width */
+
+#define CY_SMIF_CMD_FIFO_WR_LAST_BYTE_Pos (15UL) /* [15] Last byte */
+#define CY_SMIF_CMD_FIFO_WR_LAST_BYTE_Msk (0x00008000UL) /* DATA[15] Last byte */
+
+#define CY_SMIF_CMD_FIFO_WR_SS_Pos (8UL) /* [11:8] Slave select */
+#define CY_SMIF_CMD_FIFO_WR_SS_Msk (0x00000F00UL) /* DATA[11:8] Slave select */
+
+#define CY_SMIF_CMD_FIFO_WR_TXDATA_Pos (0UL) /* [0] Transmitted byte */
+#define CY_SMIF_CMD_FIFO_WR_TXDATA_Msk (0x000000FFUL) /* DATA[7:0] Transmitted byte */
+#define CY_SMIF_CMD_FIFO_WR_DUMMY_Pos (0UL) /* [0] Dummy count */
+#define CY_SMIF_CMD_FIFO_WR_DUMMY_Msk (0x0000FFFFUL) /* DATA[15:0] Dummy count */
+#define CY_SMIF_CMD_FIFO_WR_TX_COUNT_Msk (0x0000FFFFUL) /* DATA[15:0] TX count */
+#define CY_SMIF_CMD_FIFO_WR_TX_COUNT_Pos (0UL) /* [0] TX count */
+#define CY_SMIF_CMD_FIFO_WR_RX_COUNT_Msk (0x0000FFFFUL) /* DATA[15:0] RX count */
+#define CY_SMIF_CMD_FIFO_WR_RX_COUNT_Pos (0UL) /* [0] RX count */
+
+/** \endcond*/
+/** \} group_smif_macros */
+
+
+/**
+* \addtogroup group_smif_enums
+* \{
+*/
+
+/** The Transfer width options for the command, data, the address and the mode. */
+typedef enum
+{
+ CY_SMIF_WIDTH_SINGLE = 0U, /**< Normal SPI mode. */
+ CY_SMIF_WIDTH_DUAL = 1U, /**< Dual SPI mode. */
+ CY_SMIF_WIDTH_QUAD = 2U, /**< Quad SPI mode. */
+ CY_SMIF_WIDTH_OCTAL = 3U, /**< Octal SPI mode. */
+ CY_SMIF_WIDTH_NA = 0xFFU /**< The specific width parameter is not applicable for this memory command. */
+} cy_en_smif_txfr_width_t;
+
+/** The SMIF error-event selection. */
+typedef enum
+{
+ /**< Generates a bus error. */
+ CY_SMIF_BUS_ERROR = 0UL,
+ /** Stalls the bus with the wait states. This option will increase the
+ * interrupt latency.
+ */
+ CY_SMIF_WAIT_STATES = 1UL
+} cy_en_smif_error_event_t;
+
+/** The data line-selection options for a slave device. */
+typedef enum
+{
+ /**
+ * smif.spi_data[0] = DATA0, smif.spi_data[1] = DATA1, ..., smif.spi_data[7] = DATA7.
+ * This value is allowed for the SPI, DSPI, quad-SPI, dual quad-SPI, and octal-SPI modes.
+ */
+ CY_SMIF_DATA_SEL0 = 0,
+ /**
+ * smif.spi_data[2] = DATA0, smif.spi_data[3] = DATA1.
+ * This value is only allowed for the SPI and DSPI modes.
+ */
+ CY_SMIF_DATA_SEL1 = 1,
+ /**
+ * smif.spi_data[4] = DATA0, smif.spi_data[5] = DATA1, ..., smif.spi_data[7] = DATA3.
+ * This value is only allowed for the SPI, DSPI, quad-SPI and dual quad-SPI modes.
+ */
+ CY_SMIF_DATA_SEL2 = 2,
+ /**
+ * smif.spi_data[6] = DATA0, smif.spi_data[7] = DATA1.
+ * This value is only allowed for the SPI and DSPI modes.
+ */
+ CY_SMIF_DATA_SEL3 = 3
+} cy_en_smif_data_select_t;
+
+/** The SMIF modes to work with an external memory. */
+typedef enum
+{
+ CY_SMIF_NORMAL, /**< Command mode (MMIO mode). */
+ CY_SMIF_MEMORY /**< XIP (eXecute In Place) mode. */
+} cy_en_smif_mode_t;
+
+/** The SMIF transfer status return values. */
+typedef enum
+{
+ CY_SMIF_STARTED, /**< The SMIF started. */
+ CY_SMIF_SEND_COMPLETE, /**< The data transmission is complete. */
+ CY_SMIF_SEND_BUSY, /**< The data transmission is in progress. */
+ CY_SMIF_RX_COMPLETE, /**< The data reception is completed. */
+ CY_SMIF_RX_BUSY, /**< The data reception is in progress. */
+ CY_SMIF_XIP_ERROR, /**< An XIP alignment error. */
+ CY_SMIF_CMD_ERROR, /**< A TX CMD FIFO overflow. */
+ CY_SMIF_TX_ERROR, /**< A TX DATA FIFO overflow. */
+ CY_SMIF_RX_ERROR /**< An RX DATA FIFO underflow. */
+
+} cy_en_smif_txfr_status_t;
+
+/** The SMIF API return values. */
+typedef enum
+{
+ CY_SMIF_SUCCESS = 0x00U, /**< Successful SMIF operation. */
+ CY_SMIF_CMD_FIFO_FULL = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x01U, /**< The command is cancelled. The command FIFO is full. */
+ CY_SMIF_EXCEED_TIMEOUT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x02U, /**< The SMIF operation timeout exceeded. */
+ /**
+ * The device does not have a QE bit. The device detects
+ * 1-1-4 and 1-4-4 Reads based on the instruction.
+ */
+ CY_SMIF_NO_QE_BIT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x03U,
+ CY_SMIF_BAD_PARAM = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x04U, /**< The SMIF API received the wrong parameter */
+ CY_SMIF_NO_SFDP_SUPPORT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x05U, /**< The external memory does not support SFDP (JESD216B). */
+ /** Failed to initialize the slave select 0 external memory by auto detection (SFDP). */
+ CY_SMIF_SFDP_SS0_FAILED = CY_SMIF_ID |CY_PDL_STATUS_ERROR |
+ ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS0_POS),
+ /** Failed to initialize the slave select 1 external memory by auto detection (SFDP). */
+ CY_SMIF_SFDP_SS1_FAILED = CY_SMIF_ID | CY_PDL_STATUS_ERROR |
+ ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS1_POS),
+ /** Failed to initialize the slave select 2 external memory by auto detection (SFDP). */
+ CY_SMIF_SFDP_SS2_FAILED = CY_SMIF_ID |CY_PDL_STATUS_ERROR |
+ ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS2_POS),
+ /** Failed to initialize the slave select 3 external memory by auto detection (SFDP). */
+ CY_SMIF_SFDP_SS3_FAILED = CY_SMIF_ID |CY_PDL_STATUS_ERROR |
+ ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS3_POS),
+ /** The command API is not supported for this memory device. */
+ CY_SMIF_CMD_NOT_FOUND = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x80U
+} cy_en_smif_status_t;
+
+/** The SMIF slave select definitions for the driver API. Each slave select is
+ * represented by an enumeration that has the bit corresponding to the slave
+ * select number set. */
+typedef enum
+{
+ CY_SMIF_SLAVE_SELECT_0 = 1U, /**< The SMIF slave select 0 */
+ CY_SMIF_SLAVE_SELECT_1 = 2U, /**< The SMIF slave select 1 */
+ CY_SMIF_SLAVE_SELECT_2 = 4U, /**< The SMIF slave select 2 */
+ CY_SMIF_SLAVE_SELECT_3 = 8U /**< The SMIF slave select 3 */
+} cy_en_smif_slave_select_t;
+
+/** Specifies the clock source for the receiver clock. */
+typedef enum
+{
+ CY_SMIF_SEL_INTERNAL_CLK = 0U, /**< The SMIF internal clock */
+ CY_SMIF_SEL_INVERTED_INTERNAL_CLK = 1U, /**< The SMIF internal inverted clock */
+ CY_SMIF_SEL_FEEDBACK_CLK = 2U, /**< The SMIF feedback clock */
+ CY_SMIF_SEL_INVERTED_FEEDBACK_CLK = 3U /**< The SMIF feedback inverted clock */
+} cy_en_smif_clk_select_t;
+
+/** Specifies enabled type of SMIF cache. */
+typedef enum
+{
+ CY_SMIF_CACHE_SLOW = 1U, /**< The SMIF slow cache (in the clk_slow domain) see TRM for details */
+ CY_SMIF_CACHE_FAST = 2U, /**< The SMIF fast cache (in the clk_fast domain) see TRM for details */
+ CY_SMIF_CACHE_BOTH = 3U /**< The SMIF both caches */
+} cy_en_smif_cache_t;
+
+/** \cond INTERNAL */
+/*******************************************************************************
+* These are legacy macros. They are left here just for backward compatibility.
+* Do not use them in new designs.
+*******************************************************************************/
+
+#define CY_SMIF_SEND_CMPLT CY_SMIF_SEND_COMPLETE
+#define CY_SMIF_REC_CMPLT CY_SMIF_RX_COMPLETE
+#define CY_SMIF_REC_BUSY CY_SMIF_RX_BUSY
+#define CY_SMIF_SEL_INV_INTERNAL_CLK CY_SMIF_SEL_INVERTED_INTERNAL_CLK
+#define CY_SMIF_SEL_INV_FEEDBACK_CLK CY_SMIF_SEL_INVERTED_FEEDBACK_CLK
+#define cy_en_smif_cache_en_t cy_en_smif_cache_t
+#define Cy_SMIF_GetTxfrStatus Cy_SMIF_GetTransferStatus
+
+/** \endcond*/
+
+/** \} group_smif_enums */
+
+
+/**
+* \addtogroup group_smif_data_structures
+* \{
+*/
+
+/***************************************************************************//**
+*
+* The SMIF user callback function type called at the end of a transfer.
+*
+* \param event
+* The event which caused a callback call.
+*
+*******************************************************************************/
+typedef void (*cy_smif_event_cb_t)(uint32_t event);
+
+
+/** The SMIF configuration structure. */
+typedef struct
+{
+ uint32_t mode; /**< Specifies the mode of operation \ref cy_en_smif_mode_t. */
+ uint32_t deselectDelay; /**< Specifies the minimum duration of SPI de-selection between SPI transfers:
+ * - "0": 1 clock cycle.
+ * - "1": 2 clock cycles.
+ * - "2": 3 clock cycles.
+ * - "3": 4 clock cycles.
+ * - "4": 5 clock cycles.
+ * - "5": 6 clock cycles.
+ * - "6": 7 clock cycles.
+ * - "7": 8 clock cycles. */
+ uint32_t rxClockSel; /**< Specifies the clock source for the receiver
+ * clock \ref cy_en_smif_clk_select_t. */
+ uint32_t blockEvent; /**< Specifies what happens when there is a Read
+ * from an empty RX FIFO or a Write to a full
+ * TX FIFO. \ref cy_en_smif_error_event_t. */
+} cy_stc_smif_config_t;
+
+/** The SMIF internal context data. The user must not modify it. */
+typedef struct
+{
+ uint8_t const volatile * volatile txBufferAddress; /**< The pointer to the data to transfer */
+ uint32_t txBufferSize; /**< The size of the data to transmit in bytes */
+ /**
+ * The transfer counter. The number of the transmitted bytes = txBufferSize - txBufferCounter
+ */
+ uint32_t volatile txBufferCounter;
+ uint8_t volatile * volatile rxBufferAddress; /**< The pointer to the variable where the received data is stored */
+ uint32_t rxBufferSize; /**< The size of the data to be received in bytes */
+ /**
+ * The transfer counter. The number of the received bytes = rxBufferSize - rxBufferCounter
+ */
+ uint32_t volatile rxBufferCounter;
+ /**
+ * The status of the transfer. The transmitting / receiving is completed / in progress
+ */
+ uint32_t volatile transferStatus;
+ cy_smif_event_cb_t volatile txCompleteCb; /**< The user-defined callback executed at the completion of a transmission */
+ cy_smif_event_cb_t volatile rxCompleteCb; /**< The user-defined callback executed at the completion of a reception */
+ /**
+ * The timeout in microseconds for the blocking functions. This timeout value applies to all blocking APIs.
+ */
+ uint32_t timeout;
+} cy_stc_smif_context_t;
+
+/** \} group_smif_data_structures */
+
+
+/**
+* \addtogroup group_smif_low_level_functions
+* \{
+*/
+
+cy_en_smif_status_t Cy_SMIF_Init(SMIF_Type *base, cy_stc_smif_config_t const *config,
+ uint32_t timeout,
+ cy_stc_smif_context_t *context);
+void Cy_SMIF_DeInit(SMIF_Type *base);
+void Cy_SMIF_SetDataSelect(SMIF_Type *base, cy_en_smif_slave_select_t slaveSelect,
+ cy_en_smif_data_select_t dataSelect);
+void Cy_SMIF_SetMode(SMIF_Type *base, cy_en_smif_mode_t mode);
+cy_en_smif_mode_t Cy_SMIF_GetMode(SMIF_Type const *base);
+cy_en_smif_status_t Cy_SMIF_TransmitCommand(SMIF_Type *base,
+ uint8_t cmd,
+ cy_en_smif_txfr_width_t cmdTxfrWidth,
+ uint8_t const cmdParam[], uint32_t paramSize,
+ cy_en_smif_txfr_width_t paramTxfrWidth,
+ cy_en_smif_slave_select_t slaveSelect, uint32_t completeTxfr,
+ cy_stc_smif_context_t const *context);
+cy_en_smif_status_t Cy_SMIF_TransmitData(SMIF_Type *base,
+ uint8_t const *txBuffer, uint32_t size,
+ cy_en_smif_txfr_width_t transferWidth,
+ cy_smif_event_cb_t TxCompleteCb,
+ cy_stc_smif_context_t *context);
+cy_en_smif_status_t Cy_SMIF_TransmitDataBlocking(SMIF_Type *base,
+ uint8_t const *txBuffer,
+ uint32_t size,
+ cy_en_smif_txfr_width_t transferWidth,
+ cy_stc_smif_context_t const *context);
+cy_en_smif_status_t Cy_SMIF_ReceiveData(SMIF_Type *base,
+ uint8_t *rxBuffer, uint32_t size,
+ cy_en_smif_txfr_width_t transferWidth,
+ cy_smif_event_cb_t RxCompleteCb,
+ cy_stc_smif_context_t *context);
+cy_en_smif_status_t Cy_SMIF_ReceiveDataBlocking(SMIF_Type *base,
+ uint8_t *rxBuffer,
+ uint32_t size,
+ cy_en_smif_txfr_width_t transferWidth,
+ cy_stc_smif_context_t const *context);
+cy_en_smif_status_t Cy_SMIF_SendDummyCycles(SMIF_Type *base, uint32_t cycles);
+uint32_t Cy_SMIF_GetTransferStatus(SMIF_Type const *base, cy_stc_smif_context_t const *context);
+void Cy_SMIF_Enable(SMIF_Type *base, cy_stc_smif_context_t *context);
+__STATIC_INLINE void Cy_SMIF_Disable(SMIF_Type *base);
+__STATIC_INLINE void Cy_SMIF_SetInterruptMask(SMIF_Type *base, uint32_t interrupt);
+__STATIC_INLINE uint32_t Cy_SMIF_GetInterruptMask(SMIF_Type const *base);
+__STATIC_INLINE uint32_t Cy_SMIF_GetInterruptStatusMasked(SMIF_Type const *base);
+__STATIC_INLINE uint32_t Cy_SMIF_GetInterruptStatus(SMIF_Type const *base);
+__STATIC_INLINE void Cy_SMIF_SetInterrupt(SMIF_Type *base, uint32_t interrupt);
+__STATIC_INLINE void Cy_SMIF_ClearInterrupt(SMIF_Type *base, uint32_t interrupt);
+__STATIC_INLINE void Cy_SMIF_SetTxFifoTriggerLevel(SMIF_Type *base, uint32_t level);
+__STATIC_INLINE void Cy_SMIF_SetRxFifoTriggerLevel(SMIF_Type *base, uint32_t level);
+__STATIC_INLINE uint32_t Cy_SMIF_GetCmdFifoStatus(SMIF_Type const *base);
+__STATIC_INLINE uint32_t Cy_SMIF_GetTxFifoStatus(SMIF_Type const *base);
+__STATIC_INLINE uint32_t Cy_SMIF_GetRxFifoStatus(SMIF_Type const *base);
+cy_en_smif_status_t Cy_SMIF_Encrypt(SMIF_Type *base,
+ uint32_t address,
+ uint8_t data[],
+ uint32_t size,
+ cy_stc_smif_context_t const *context);
+__STATIC_INLINE bool Cy_SMIF_BusyCheck(SMIF_Type const *base);
+__STATIC_INLINE void Cy_SMIF_Interrupt(SMIF_Type *base, cy_stc_smif_context_t *context);
+cy_en_smif_status_t Cy_SMIF_CacheEnable(SMIF_Type *base, cy_en_smif_cache_t cacheType);
+cy_en_smif_status_t Cy_SMIF_CacheDisable(SMIF_Type *base, cy_en_smif_cache_t cacheType);
+cy_en_smif_status_t Cy_SMIF_CachePrefetchingEnable(SMIF_Type *base, cy_en_smif_cache_t cacheType);
+cy_en_smif_status_t Cy_SMIF_CachePrefetchingDisable(SMIF_Type *base, cy_en_smif_cache_t cacheType);
+cy_en_smif_status_t Cy_SMIF_CacheInvalidate(SMIF_Type *base, cy_en_smif_cache_t cacheType);
+
+/** \addtogroup group_smif_functions_syspm_callback
+* The driver supports SysPm callback for Deep Sleep and Hibernate transition.
+* \{
+*/
+cy_en_syspm_status_t Cy_SMIF_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
+cy_en_syspm_status_t Cy_SMIF_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
+/** \} */
+
+
+/***************************************
+* Internal SMIF function declarations
+****************************************/
+/** \cond INTERNAL */
+__STATIC_INLINE void Cy_SMIF_PushTxFifo(SMIF_Type *baseaddr, cy_stc_smif_context_t *context); /**< Writes transmitted data into the FIFO. */
+__STATIC_INLINE void Cy_SMIF_PopRxFifo(SMIF_Type *baseaddr, cy_stc_smif_context_t *context); /**< Reads received data from the FIFO. */
+__STATIC_INLINE uint32_t Cy_SMIF_PackBytesArray(uint8_t const buff[], bool fourBytes);
+__STATIC_INLINE void Cy_SMIF_UnPackByteArray(uint32_t inValue, uint8_t outBuff[], bool fourBytes);
+__STATIC_INLINE cy_en_smif_status_t Cy_SMIF_TimeoutRun(uint32_t *timeoutUnits);
+__STATIC_INLINE SMIF_DEVICE_Type volatile * Cy_SMIF_GetDeviceBySlot(SMIF_Type *base,
+ cy_en_smif_slave_select_t slaveSelect);
+/** \endcond*/
+
+/** \} group_smif_low_level_functions */
+
+
+/**
+* \addtogroup group_smif_low_level_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Disable
+****************************************************************************//**
+*
+* Disables the operation of the SMIF block. The SMIF block can be disabled only
+* when it is not in the active state. Use the Cy_SMIF_BusyCheck() API to check
+* it before calling this API.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_Disable(SMIF_Type *base)
+{
+ SMIF_CTL(base) &= ~SMIF_CTL_ENABLED_Msk;
+
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_SetInterruptMask
+****************************************************************************//**
+*
+* This function is used to set an interrupt mask for the SMIF Interrupt.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param interrupt
+* This is the mask for different source options that can be masked. See
+* \ref group_smif_macros_isr "Interrupt Macros" for possible values.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_SetInterruptMask(SMIF_Type *base, uint32_t interrupt)
+{
+ SMIF_INTR_MASK(base) = interrupt;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetInterruptMask
+****************************************************************************//**
+*
+* This function is used to read an interrupt mask for the SMIF Interrupt.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns the mask set for the SMIF interrupt.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_GetInterruptMask(SMIF_Type const *base)
+{
+ return (SMIF_INTR_MASK(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* This function is used to read an active masked interrupt. This function can
+* be used in the interrupt service-routine to find which source triggered the
+* interrupt.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns a word with bits set at positions corresponding to the
+* interrupts triggered in the system.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_GetInterruptStatusMasked(SMIF_Type const *base)
+{
+ return (SMIF_INTR_MASKED(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetInterruptStatus
+****************************************************************************//**
+*
+* This function is used to read an active interrupt. This status is the unmasked
+* result, so will also show interrupts that will not generate active interrupts.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns a word with bits set at positions corresponding to the
+* interrupts triggered in the system.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_GetInterruptStatus(SMIF_Type const *base)
+{
+ return (SMIF_INTR(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_SetInterrupt
+****************************************************************************//**
+*
+* This function is used to set an interrupt source. This function can be used
+* to activate interrupts through the software.
+*
+* \note Interrupt sources set using this interrupt will generate interrupts only
+* if they are not masked.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param interrupt
+* An encoded integer with a bit set corresponding to the interrupt to be
+* triggered. See \ref group_smif_macros_isr "Interrupt Macros" for possible
+* values.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_SetInterrupt(SMIF_Type *base, uint32_t interrupt)
+{
+ SMIF_INTR_SET(base) = interrupt;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_ClearInterrupt
+****************************************************************************//**
+*
+* This function is used to clear an interrupt source. This function can be used
+* in the user code to clear all pending interrupts.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param interrupt
+* An encoded integer with a bit set corresponding to the interrupt that must
+* be cleared. See \ref group_smif_macros_isr "Interrupt Macros" for possible
+* values.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_ClearInterrupt(SMIF_Type *base, uint32_t interrupt)
+{
+ SMIF_INTR(base) = interrupt;
+
+ /* Ensure that the initial Write has been flushed out to the hardware. */
+ interrupt = SMIF_INTR(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_SetTxFifoTriggerLevel()
+****************************************************************************//**
+*
+* This function is used to set a trigger level for the TX FIFO. This value must
+* be an integer between 0 and 7. For the normal mode only.
+* The triggering is active when TX_DATA_FIFO_STATUS <= level.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param level
+* The trigger level to set (0-8).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_SetTxFifoTriggerLevel(SMIF_Type *base, uint32_t level)
+{
+ CY_ASSERT_L2(level <= CY_SMIF_MAX_TX_TR_LEVEL);
+ SMIF_TX_DATA_FIFO_CTL(base) = level;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_SetRxFifoTriggerLevel()
+****************************************************************************//**
+*
+* This function is used to set a trigger level for the RX FIFO. This value must
+* be an integer between 0 and 7. For the normal mode only.
+* The triggering is active when RX_DATA_FIFOSTATUS > level.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param level
+* The trigger level to set(0-8).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_SetRxFifoTriggerLevel(SMIF_Type *base, uint32_t level)
+{
+ CY_ASSERT_L2(level <= CY_SMIF_MAX_RX_TR_LEVEL);
+ SMIF_RX_DATA_FIFO_CTL(base) = level;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetCmdFifoStatus()
+****************************************************************************//**
+*
+* This function is used to read the status of the CMD FIFO.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns the number of the entries in the CMD FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_GetCmdFifoStatus(SMIF_Type const *base)
+{
+ return (_FLD2VAL(SMIF_TX_CMD_FIFO_STATUS_USED3, SMIF_TX_CMD_FIFO_STATUS(base)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetTxFifoStatus()
+****************************************************************************//**
+*
+* This function is used to read the status of the TX FIFO.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns the number of the entries in the TX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_GetTxFifoStatus(SMIF_Type const *base)
+{
+ return (_FLD2VAL(SMIF_TX_DATA_FIFO_STATUS_USED4, SMIF_TX_DATA_FIFO_STATUS(base)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetRxFifoStatus()
+****************************************************************************//**
+*
+* This function is used to read the status of the RX FIFO.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns the number of the entries in the RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_GetRxFifoStatus(SMIF_Type const *base)
+{
+ return (_FLD2VAL(SMIF_RX_DATA_FIFO_STATUS_USED4, SMIF_RX_DATA_FIFO_STATUS(base)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_BusyCheck
+****************************************************************************//**
+*
+* This function provides the status of the IP block (False - not busy,
+* True - busy).
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns an IP block status.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SMIF_BusyCheck(SMIF_Type const *base)
+{
+ return (1UL == _FLD2VAL(SMIF_STATUS_BUSY, SMIF_STATUS(base)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Interrupt
+****************************************************************************//**
+*
+* The Interrupt Service Routine for the SMIF. The interrupt code will be
+* responsible for the FIFO operations on FIFO interrupts during ongoing transfers.
+* The user must place a call to this interrupt function in the interrupt
+* routine corresponding to the interrupt attached to the SMIF. If the
+* user does not do this, will break: the functionality of all the API functions in
+* the SMIF driver that use SMIF interrupts to affect transfers.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* \globalvars
+* - context->txBufferAddress - The pointer to the data to be transferred.
+*
+* - context->txBufferSize - The size of txBuffer.
+*
+* - context->txBufferCounter - The number of data entries left to be transferred.
+*
+* All the Global variables described above are used when the Software Buffer is
+* used.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_Interrupt(SMIF_Type *base, cy_stc_smif_context_t *context)
+{
+ uint32_t interruptStatus = Cy_SMIF_GetInterruptStatusMasked(base);
+
+ /* Check which interrupt occurred */
+ if (0U != (interruptStatus & SMIF_INTR_TR_TX_REQ_Msk))
+ {
+ /* Send data */
+ Cy_SMIF_PushTxFifo(base, context);
+
+ Cy_SMIF_ClearInterrupt(base, SMIF_INTR_TR_TX_REQ_Msk);
+ }
+ else if (0U != (interruptStatus & SMIF_INTR_TR_RX_REQ_Msk))
+ {
+ /* Receive data */
+ Cy_SMIF_PopRxFifo(base, context);
+
+ Cy_SMIF_ClearInterrupt(base, SMIF_INTR_TR_RX_REQ_Msk);
+ }
+ else if (0U != (interruptStatus & SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk))
+ {
+ /* An XIP alignment error */
+ context->transferStatus = (uint32_t) CY_SMIF_XIP_ERROR;
+
+ Cy_SMIF_ClearInterrupt(base, SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk);
+ }
+
+ else if (0U != (interruptStatus & SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk))
+ {
+ /* TX CMD FIFO overflow */
+ context->transferStatus = (uint32_t) CY_SMIF_CMD_ERROR;
+
+ Cy_SMIF_ClearInterrupt(base, SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk);
+ }
+
+ else if (0U != (interruptStatus & SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk))
+ {
+ /* A TX DATA FIFO overflow */
+ context->transferStatus = (uint32_t) CY_SMIF_TX_ERROR;
+
+ Cy_SMIF_ClearInterrupt(base, SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk);
+ }
+
+ else if (0U != (interruptStatus & SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk))
+ {
+ /* RX DATA FIFO underflow */
+ context->transferStatus = (uint32_t) CY_SMIF_RX_ERROR;
+
+ Cy_SMIF_ClearInterrupt(base, SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk);
+ }
+ else
+ {
+ /* Processing of errors */
+ }
+}
+
+
+/*******************************************************************************
+* Internal SMIF in-line functions
+*******************************************************************************/
+
+/** \cond INTERNAL */
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_PushTxFifo
+***************************************************************************//***
+*
+* \internal
+*
+* \param baseaddr
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* This function writes data in the TX FIFO SMIF buffer by 4, 2, or 1 bytes based
+* on the residual number of bytes and the available space in the TX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_PushTxFifo(SMIF_Type *baseaddr, cy_stc_smif_context_t *context)
+{
+ /* The variable that shows which is smaller: the free FIFO size or amount of bytes to be sent */
+ uint32_t writeBytes;
+ uint32_t freeFifoBytes;
+ uint32_t buffCounter = context->txBufferCounter;
+ uint8_t *buff = (uint8_t*) context->txBufferAddress;
+
+ freeFifoBytes = CY_SMIF_TX_DATA_FIFO_STATUS_RANGE - Cy_SMIF_GetTxFifoStatus(baseaddr);
+ writeBytes = (freeFifoBytes > buffCounter)? buffCounter: freeFifoBytes;
+
+ /* Check that after a FIFO Write, no data/FIFO space remains */
+ while (0U != writeBytes)
+ {
+ /* The first main use case for long transfers */
+ if (writeBytes == CY_SMIF_EIGHT_BYTES)
+ {
+ SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], true);
+ SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[4U], true);
+ }
+ /* The second main use case for short transfers */
+ else if(writeBytes == CY_SMIF_ONE_BYTE)
+ {
+ SMIF_TX_DATA_FIFO_WR1(baseaddr) = buff[0U];
+ }
+ else if(writeBytes == CY_SMIF_TWO_BYTES)
+ {
+ SMIF_TX_DATA_FIFO_WR2(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], false);
+ }
+ else if(writeBytes == CY_SMIF_THREE_BYTES)
+ {
+ SMIF_TX_DATA_FIFO_WR2(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], false);
+ SMIF_TX_DATA_FIFO_WR1(baseaddr) = buff[2U];
+ }
+ else if(writeBytes == CY_SMIF_FOUR_BYTES)
+ {
+ SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], true);
+ }
+ else if(writeBytes == CY_SMIF_FIVE_BYTES)
+ {
+ SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], true);
+ SMIF_TX_DATA_FIFO_WR1(baseaddr) = buff[4U];
+ }
+ else if(writeBytes == CY_SMIF_SIX_BYTES)
+ {
+ SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], true);
+ SMIF_TX_DATA_FIFO_WR2(baseaddr) = Cy_SMIF_PackBytesArray(&buff[4U], false);
+ }
+ else if(writeBytes == CY_SMIF_SEVEN_BYTES)
+ {
+ SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], true);
+ SMIF_TX_DATA_FIFO_WR2(baseaddr) = Cy_SMIF_PackBytesArray(&buff[4U], false);
+ SMIF_TX_DATA_FIFO_WR1(baseaddr) = buff[6U];
+ }
+ else /* The future IP block with FIFO > 8*/
+ {
+ SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], true);
+ SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[4U], true);
+ writeBytes = CY_SMIF_EIGHT_BYTES;
+ }
+ buff = &buff[writeBytes];
+ buffCounter -= writeBytes;
+ /* Check if we already got new data in TX_FIFO*/
+ freeFifoBytes = CY_SMIF_TX_DATA_FIFO_STATUS_RANGE - Cy_SMIF_GetTxFifoStatus(baseaddr);
+ writeBytes = (freeFifoBytes > buffCounter)? buffCounter: freeFifoBytes;
+ }
+
+ /* Save changes in the context */
+ context->txBufferAddress = buff;
+ context->txBufferCounter = buffCounter;
+
+ /* Check if all bytes are sent */
+ if (0u == buffCounter)
+ {
+ /* Disable the TR_TX_REQ interrupt */
+ Cy_SMIF_SetInterruptMask(baseaddr, Cy_SMIF_GetInterruptMask(baseaddr) & ~SMIF_INTR_TR_TX_REQ_Msk);
+
+ context->transferStatus = (uint32_t) CY_SMIF_SEND_COMPLETE;
+ if (NULL != context->txCompleteCb)
+ {
+ context->txCompleteCb((uint32_t) CY_SMIF_SEND_COMPLETE);
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_PopRxFifo
+***************************************************************************//***
+*
+* \internal
+*
+* \param baseaddr
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* This function reads data from the RX FIFO SMIF buffer by 4, 2, or 1 bytes
+* based on the data availability in the RX FIFO and amount of bytes to be
+* received.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_PopRxFifo(SMIF_Type *baseaddr, cy_stc_smif_context_t *context)
+{
+ /* The variable that shows which is smaller: the free FIFO size or amount of bytes to be received */
+ uint32_t readBytes;
+ uint32_t loadedFifoBytes;
+ uint32_t buffCounter = context->rxBufferCounter;
+ uint8_t *buff = (uint8_t*) context->rxBufferAddress;
+
+ loadedFifoBytes = Cy_SMIF_GetRxFifoStatus(baseaddr);
+ readBytes = (loadedFifoBytes > buffCounter)? buffCounter: loadedFifoBytes;
+
+ /* Check that after a FIFO Read, no new data is available */
+ while (0U != readBytes)
+ {
+ if (readBytes == CY_SMIF_EIGHT_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[0U], true);
+ Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[4U], true);
+ }
+ else if(readBytes == CY_SMIF_ONE_BYTE)
+ {
+ buff[0U] = (uint8_t)SMIF_RX_DATA_FIFO_RD1(baseaddr);
+ }
+ else if(readBytes == CY_SMIF_TWO_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD2(baseaddr), &buff[0U], false);
+ }
+ else if(readBytes == CY_SMIF_THREE_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD2(baseaddr), &buff[0U], false);
+ buff[2U] = (uint8_t)SMIF_RX_DATA_FIFO_RD1(baseaddr);
+ }
+ else if(readBytes == CY_SMIF_FOUR_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[0U], true);
+ }
+ else if(readBytes == CY_SMIF_FIVE_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[0U], true);
+ buff[4U] = (uint8_t)SMIF_RX_DATA_FIFO_RD1(baseaddr);
+ }
+ else if(readBytes == CY_SMIF_SIX_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[0U], true);
+ Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD2(baseaddr), &buff[4U], false);
+ }
+ else if(readBytes == CY_SMIF_SEVEN_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[0U], true);
+ Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD2(baseaddr), &buff[4U], false);
+ buff[6U] = (uint8_t)SMIF_RX_DATA_FIFO_RD1(baseaddr);
+ }
+ else /* The IP block FIFO > 8*/
+ {
+ Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[0U], true);
+ Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[4U], true);
+ readBytes = CY_SMIF_EIGHT_BYTES;
+ }
+
+ buff = &buff[readBytes];
+ buffCounter -= readBytes;
+ /* Check if we already got new data in RX_FIFO*/
+ loadedFifoBytes = Cy_SMIF_GetRxFifoStatus(baseaddr);
+ readBytes = (loadedFifoBytes > buffCounter)? buffCounter: loadedFifoBytes;
+ }
+
+ /* Save changes in the context */
+ context->rxBufferAddress = buff;
+ context->rxBufferCounter = buffCounter;
+
+ /* Check if all bytes are received */
+ if (0UL == buffCounter)
+ {
+ /* Disable the TR_RX_REQ interrupt */
+ Cy_SMIF_SetInterruptMask(baseaddr, Cy_SMIF_GetInterruptMask(baseaddr) & ~SMIF_INTR_TR_RX_REQ_Msk);
+ context->transferStatus = (uint32_t) CY_SMIF_RX_COMPLETE;
+ if (NULL != context->rxCompleteCb)
+ {
+ context->rxCompleteCb((uint32_t) CY_SMIF_RX_COMPLETE);
+ }
+ }
+
+ context->rxBufferCounter = buffCounter;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_PackBytesArray
+***************************************************************************//***
+*
+* \internal
+*
+* This function packs 0-numBytes of the buff byte array into a 4-byte value.
+*
+* \param buff
+* The byte array to pack.
+*
+* \param fourBytes
+* - True: The pack is for a 32-bit value.
+* - False: The pack is for a 16-bit value.
+*
+* \return
+* The 4-byte value packed from the byte array.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_PackBytesArray(uint8_t const buff[], bool fourBytes)
+{
+ uint32_t result = 0UL;
+
+ result = ((uint32_t)buff[1UL] << 8UL) | (uint32_t)buff[0UL];
+
+ if(fourBytes)
+ {
+ result |= ((uint32_t)buff[3UL] << 24UL) | ((uint32_t)buff[2UL] << 16UL);
+ }
+
+ return result;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_UnPackByteArray
+***************************************************************************//***
+*
+* \internal
+*
+* This function unpacks 0-numBytes from a 4-byte value into the byte array outBuff.
+*
+* \param smifReg
+* The 4-byte value to unpack.
+*
+* \param outBuff
+* The byte array to fill.
+*
+* \param fourBytes
+* - The True unpack is for a 32-bit value.
+* - The False unpack is for a 16-bit value.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_UnPackByteArray(uint32_t inValue, uint8_t outBuff[], bool fourBytes)
+{
+ outBuff[0UL] = (uint8_t)(inValue & 0xFFUL);
+ outBuff[1UL] = (uint8_t)((inValue >> 8UL ) & 0xFFUL);
+
+ if(fourBytes)
+ {
+ outBuff[2UL] = (uint8_t)((inValue >> 16UL) & 0xFFUL);
+ outBuff[3UL] = (uint8_t)((inValue >> 24UL) & 0xFFUL);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_TimeoutRun
+****************************************************************************//**
+*
+* \internal
+*
+* This function checks if the timeout is expired. Use the Cy_SysLib_DelayUs() function for
+* implementation.
+*
+* \param timeoutUnits
+* The pointer to the timeout. The timeout measured in microseconds is multiplied by
+* CY_SMIF_WAIT_1_UNIT.
+*
+* \return
+* A timeout status:
+* - \ref CY_SMIF_SUCCESS - The timeout has not expired or input timeoutUnits is 0.
+* - \ref CY_SMIF_EXCEED_TIMEOUT - The timeout has expired.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_smif_status_t Cy_SMIF_TimeoutRun(uint32_t *timeoutUnits)
+{
+ cy_en_smif_status_t status = CY_SMIF_SUCCESS;
+ if (*timeoutUnits > 0u)
+ {
+ Cy_SysLib_DelayUs(CY_SMIF_WAIT_1_UNIT);
+ --(*timeoutUnits);
+ status = (0u == (*timeoutUnits))? CY_SMIF_EXCEED_TIMEOUT: CY_SMIF_SUCCESS;
+ }
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetDeviceBySlot
+****************************************************************************//**
+*
+* \internal
+* This function returns the address of the SMIF device registers structure by the slave
+* slot number.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param slaveSelect
+* The slave device ID. This number is either CY_SMIF_SLAVE_SELECT_0 or
+* CY_SMIF_SLAVE_SELECT_1 or CY_SMIF_SLAVE_SELECT_2 or CY_SMIF_SLAVE_SELECT_3
+* (\ref cy_en_smif_slave_select_t). It defines the slave-select line to use
+* during the transmission.
+*
+*******************************************************************************/
+__STATIC_INLINE SMIF_DEVICE_Type volatile * Cy_SMIF_GetDeviceBySlot(SMIF_Type *base,
+ cy_en_smif_slave_select_t slaveSelect)
+{
+ SMIF_DEVICE_Type volatile *device;
+ /* Connect the slave to its data lines */
+ switch (slaveSelect)
+ {
+ case CY_SMIF_SLAVE_SELECT_0:
+ device = &(SMIF_DEVICE_IDX(base, 0));
+ break;
+ case CY_SMIF_SLAVE_SELECT_1:
+ device = &(SMIF_DEVICE_IDX(base, 1));
+ break;
+ case CY_SMIF_SLAVE_SELECT_2:
+ device = &(SMIF_DEVICE_IDX(base, 2));
+ break;
+ case CY_SMIF_SLAVE_SELECT_3:
+ device = &(SMIF_DEVICE_IDX(base, 3));
+ break;
+ default:
+ /* A user error*/
+ device = NULL;
+ break;
+ }
+
+ return device;
+}
+
+/** \endcond */
+/** \} group_smif_low_level_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_IP_MXSMIF */
+
+#endif /* (CY_SMIF_H) */
+
+/** \} group_smif */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_sysclk.h b/platform/ext/target/psoc64/Native_Driver/include/cy_sysclk.h
new file mode 100644
index 0000000000..7b80ad6739
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_sysclk.h
@@ -0,0 +1,3239 @@
+/***************************************************************************//**
+* \file cy_sysclk.h
+* \version 1.40.2
+*
+* Provides an API declaration of the sysclk driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_sysclk
+* \{
+* The System Clock (SysClk) driver contains the API for configuring system and
+* peripheral clocks.
+*
+* The functions and other declarations used in this driver are in cy_sysclk.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions
+* and declarations in the PDL.
+*
+* Firmware uses the API to configure , enable, or disable a clock.
+*
+* The clock system includes a variety of resources that can vary per device, including:
+* - Internal clock sources such as internal oscillators
+* - External clock sources such as crystal oscillators or a signal on an I/O pin
+* - Generated clocks such as an FLL, a PLL, and peripheral clocks
+*
+* Consult the Technical Reference Manual for your device for details of the
+* clock system.
+*
+* The PDL defines clock system capabilities in:\n
+* devices\<family\>/<series\>/include\<series\>_config.h. (E.g.
+* devices/psoc6/include/psoc6_01_config.h).
+* User-configurable clock speeds are defined in the file system_<series>.h.
+*
+* As an illustration of the clocking system, the following diagram shows the
+* PSoC 63 series clock tree. The actual tree may vary depending on the device series.
+* Consult the Technical Reference Manual for your device for details.
+* ![](sysclk_tree.png)
+*
+* The sysclk driver supports multiple peripheral clocks, as well as the fast
+* clock, slow clock, backup domain clock, timer clock, and pump clock. The API
+* for any given clock contains the functions to manage that clock. Functions
+* for clock measurement and trimming are also provided.
+*
+* \section group_sysclk_configuration Configuration Considerations
+* The availability of clock functions depend on the availability of the chip
+* resources that support those functions. Consult the device TRM before
+* attempting to use these functions.
+*
+* PSoC 6 power modes limit the maximum clock frequency.
+* Refer to the SysPm driver and the TRM for details.
+*
+* \section group_sysclk_more_information More Information
+* Refer to the technical reference manual (TRM) and the device datasheet.
+*
+* \section group_sysclk_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>10.3</td>
+* <td>R</td>
+* <td>A composite expression of the "essentially unsigned" type is being
+* cast to a different type category.</td>
+* <td>The value got from the bitfield physically cannot exceed the enumeration
+* that describes this bitfield. So, the code is safe by design.</td>
+* </tr>
+* <tr>
+* <td>13.7</td>
+* <td>R</td>
+* <td>Boolean operations whose result are invariant shall not be permitted.</td>
+* <td>This math is legacy, preserving the backward compatibility.</td>
+* </tr>
+* <tr>
+* <td>16.7</td>
+* <td>R</td>
+* <td>The object addressed by the pointer parameter is not modified and so the pointer could be of
+* type 'pointer to const'.</td>
+* <td>The callback function for system power management (SysPm) must be of generic callback type that
+* contains non-const pointer parameter.</td>
+* </tr>
+* </table>
+*
+* \section group_sysclk_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.40.2</td>
+* <td>Update documentation based on collateral review feedback.</td>
+* <td>User experience enhancement.</td>
+* </tr>
+* <tr>
+* <td>1.40.1</td>
+* <td>Fix compiler warning.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td rowspan="4">1.40</td>
+* <td>Updated the following functions implementation: \ref Cy_SysClk_PllConfigure and \ref Cy_SysClk_PllEnable.</td>
+* <td>
+* Fixed the \ref Cy_SysClk_PllConfigure API function behaviour when it is called with a bypass mode, \n
+* Fixed the \ref Cy_SysClk_PllEnable API function behaviour when it is called with a zero timeout.
+* </td>
+* </tr>
+* <tr>
+* <td>Added the following functions: \ref Cy_SysClk_MfoEnable, \ref Cy_SysClk_MfoIsEnabled,\n
+* \ref Cy_SysClk_MfoDisable, \ref Cy_SysClk_ClkMfEnable, \ref Cy_SysClk_ClkMfIsEnabled,\n
+* \ref Cy_SysClk_ClkMfDisable, \ref Cy_SysClk_ClkMfGetDivider, \ref Cy_SysClk_ClkMfSetDivider,\n.
+* \ref Cy_SysClk_ClkMfGetFrequency</td>
+* <td>New device support.</td>
+* </tr>
+* <tr>
+* <td>Added the following new API functions \ref Cy_SysClk_FllIsEnabled, \ref Cy_SysClk_PllIsEnabled,\n
+* \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_ClkHfGetFrequency, \ref Cy_SysClk_ClkFastGetFrequency,\n
+* \ref Cy_SysClk_ClkPeriGetFrequency and \ref Cy_SysClk_ClkSlowGetFrequency</td>
+* <td>Enhancement based on usability feedback</td>
+* </tr>
+* <tr>
+* <td>Deprecated the following macros: CY_SYSCLK_DIV_ROUND and CY_SYSCLK_DIV_ROUNDUP</td>
+* <td>Macros were moved into \ref group_syslib</td>
+* </tr>
+* <tr>
+* <td rowspan="2">1.30</td>
+* <td>Updated the following functions implementation: \ref Cy_SysClk_EcoConfigure and \ref Cy_SysClk_FllConfigure.</td>
+* <td>Math library dependency is removed, the floating-point math is replaced with integer math.</td>
+* </tr>
+* <tr>
+* <td>Updated the following functions implementation: \ref Cy_SysClk_EcoEnable, \ref Cy_SysClk_EcoGetStatus, \ref Cy_SysClk_FllGetConfiguration \n
+* and \ref Cy_SysClk_DeepSleepCallback. \n
+* The \ref Cy_SysClk_DeepSleepCallback now implements all four SysPm callback modes \ref cy_en_syspm_callback_mode_t. \n
+* The actions that were done in \ref CY_SYSPM_CHECK_READY case are moved to \ref CY_SYSPM_BEFORE_TRANSITION. \n
+* So the \ref cy_stc_syspm_callback_t::skipMode must be set to 0UL.</td>
+* <td>Defect fixing.</td>
+* </tr>
+* <tr>
+* <td rowspan="4">1.20</td>
+* <td>Flattened the organization of the driver source code into the single
+* source directory and the single include directory.
+* </td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Updated \ref Cy_SysClk_FllLocked function description</td>
+* <td>The SRSS_ver1 HW details clarification</td>
+* </tr>
+* <tr>
+* <td>Removed the following functions:
+* - Cy_SysClk_FllLostLock
+* - Cy_SysClk_WcoConfigureCsv
+* - Cy_SysClk_ClkHfConfigureCsv
+* </td>
+* <td>No hardware support for the removed functions.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>1.11</td>
+* <td>Updated the following functions. Now they use a semaphore when
+* try to read the status or configure the SysClk measurement counters:
+* * Cy_SysClk_StartClkMeasurementCounters()
+* * Cy_SysClk_ClkMeasurementCountersGetFreq()
+*
+* Now Cy_SysClk_ClkMeasurementCountersGetFreq() returns zero value,
+* if during measurement device was in the Deep Sleep or partially
+* blocking flash operation occurred </td>
+* <td>Added arbiter mechanism for correct usage of the SysClk measurement
+* counters</td>
+* </tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Renamed Power Management section to Low Power Callback section</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td rowspan="5">1.10</td>
+* <td>Updated FLL parameter calculation</td>
+* <td>Support low frequency sources</td>
+* </tr>
+* <tr>
+* <td>Added Cy_SysClk_PiloSetTrim() and Cy_SysclkPiloGetTrim() functions</td>
+* <td>Support PILO manual trims</td>
+* </tr>
+* <tr>
+* <td>Made Cy_SysClk_FllLostLock() function dependent on SRSS v1</td>
+* <td>Feature is not supported in SRSS v1</td>
+* </tr>
+* <tr>
+* <td>Updated Cy_SysClk_DeepSleepCallback() to save/restore both FLL and PLL settings</td>
+* <td>The function should return when the lock is established or a timeout has occurred</td>
+* </tr>
+* <tr>
+* <td>General documentation updates</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_sysclk_macros Macros
+* \{
+* \}
+* \defgroup group_sysclk_enums General Enumerated Types
+* \{
+* \defgroup group_sysclk_returns Function return values
+* \}
+* \defgroup group_sysclk_ext External Clock Source (EXTCLK)
+* \{
+* The External Clock Source (EXTCLK) is a clock source routed into PSoC
+* through a GPIO pin. The EXTCLK is a source clock that can be used to
+* source one or more clock paths (Refer to \ref group_sysclk_path_src).
+* These clock paths can then source the processors and peripherals in
+* the device.
+*
+* The EXTCLK relies on the presence of an external clock signal applied
+* to the GPIO pin. The pin must be configured to operate in Digital
+* High-Z drive mode with input buffer on and HSIOM connection
+* set to HSIOM_SEL_ACT_4 (P0_0_SRSS_EXT_CLK, P0_5_SRSS_EXT_CLK).
+*
+* \defgroup group_sysclk_ext_funcs Functions
+* \}
+* \defgroup group_sysclk_eco External Crystal Oscillator (ECO)
+* \{
+* The External Crystal Oscillator (ECO) is a clock source that consists
+* of an oscillator circuit that drives an external crystal through its
+* dedicated ECO pins. The ECO is a source clock that can be used to
+* source one or more clock paths (Refer to \ref group_sysclk_path_src).
+* These clock paths can then source the processors and peripherals in
+* the device.
+*
+* The ECO relies on the presence of an external crystal. The pins
+* connected to this crystal must be configured to operate in analog
+* drive mode with HSIOM connection set to GPIO control (HSIOM_SEL_GPIO).
+*
+* \defgroup group_sysclk_eco_funcs Functions
+* \}
+* \defgroup group_sysclk_path_src Clock Path Source
+* \{
+* Clock paths are a series of multiplexers that allow a source clock
+* to drive multiple clocking resources down the chain. These paths are
+* used for active domain clocks that are not operational during chip
+* Deep Sleep, hibernate and off modes. Illustrated below is a diagram
+* of the clock paths for the PSoC 63 series, showing the first three
+* clock paths. The source clocks for these paths are highlighted in
+* the red box.
+*
+* - IMO: 8 MHz Internal Main Oscillator (Default)
+* - EXTCLK: External clock (signal brought in through dedicated pins)
+* - ECO: External Crystal Oscillator (requires external crystal on dedicated pins)
+* - ALTHF: Select on-chip signals (e.g. BLE ECO)
+* - Digital Signal (DSI): Digital signal from a UDB source
+*
+* Some clock paths such as path 0 and path 1 have additional resources
+* that can be utilized to provide a higher frequency clock. For example,
+* path 0 source clock can be used as the reference clock for the FLL and
+* path 1 source clock can be used as the reference clock for the PLL.
+*
+* ![](sysclk_path_source.png)
+*
+* \note The PDL driver cannot configure a clock path to use Digital Signal
+* Interconnect (DSI) outputs as sources. This must be done through DSI
+* configuration tool such as PSoC Creator.
+*
+* \defgroup group_sysclk_path_src_funcs Functions
+* \defgroup group_sysclk_path_src_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_fll Frequency Locked Loop (FLL)
+* \{
+* The FLL is a clock generation circuit that can be used to produce a
+* higher frequency clock from a reference clock. The output clock exhibits
+* some characteristics of the reference clock such as the accuracy of the
+* source. However other attributes such as the clock phase are not preserved.
+* The FLL is similar in purpose to a (Phase locked loop) PLL but they are
+* not equivalent.
+*
+* - They may have different frequency ranges.
+* - The FLL starts up (locks) faster and consumes less current than the PLL.
+* - The FLL accepts a source clock with lower frequency than PLL, such as the WCO (32 KHz).
+* - The FLL does not lock phase. The hardware consist of a counter with a
+* current-controlled oscillator (CCO). The counter counts the number of output
+* clock edges in a reference clock period and adjusts the CCO until the
+* expected ratio is achieved (locked). After initial lock, the CCO is
+* adjusted dynamically to keep the ratio within tolerance. The lock tolerance
+* is user-adjustable.
+* ![](sysclk_fll.png)
+*
+* The SysClk driver supports two models for configuring the FLL. The first
+* model is to call the Cy_SysClk_FllConfigure() function, which calculates the
+* necessary parameters for the FLL at run-time. This may be necessary for dynamic
+* run-time changes to the FLL. However this method is slow as it needs to perform
+* the calculation before configuring the FLL. The other model is to call
+* Cy_SysClk_FllManualConfigure() function with pre-calculated parameter values.
+* This method is faster but requires prior knowledge of the necessary parameters.
+* Consult the device TRM for the FLL calculation equations.
+*
+* \defgroup group_sysclk_fll_funcs Functions
+* \defgroup group_sysclk_fll_structs Data Structures
+* \defgroup group_sysclk_fll_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_pll Phase Locked Loop (PLL)
+* \{
+* The PLL is a clock generation circuit that can be used to produce a
+* higher frequency clock from a reference clock. The output clock exhibits
+* characteristics of the reference clock such as the accuracy of the source
+* and its phase. The PLL is similar in purpose to a (Frequency locked loop) FLL
+* but they are not equivalent.
+*
+* - They may have different frequency ranges.
+* - The PLL starts up more slowly and consumes more current than the FLL.
+* - The PLL requires a higher frequency source clock than PLL.
+* ![](sysclk_pll.png)
+*
+* The SysClk driver supports two models for configuring the PLL. The first
+* model is to call the Cy_SysClk_PllConfigure() function, which calculates the
+* necessary parameters for the PLL at run-time. This may be necessary for dynamic
+* run-time changes to the PLL. However this method is slow as it needs to perform
+* the calculation before configuring the PLL. The other model is to call
+* Cy_SysClk_PllManualConfigure() function with pre-calculated parameter values.
+* This method is faster but requires prior knowledge of the necessary parameters.
+* Consult the device TRM for the PLL calculation equations.
+*
+* \defgroup group_sysclk_pll_funcs Functions
+* \defgroup group_sysclk_pll_structs Data Structures
+* \}
+* \defgroup group_sysclk_ilo Internal Low-Speed Oscillator (ILO)
+* \{
+* The ILO operates with no external components and outputs a stable clock at
+* 32.768 kHz nominal. The ILO is relatively low power and low accuracy. It is
+* available in all power modes and can be used as a source for the Backup domain clock.
+* ![](sysclk_backup.png)
+*
+* To ensure the ILO remains active in Hibernate mode, and across power-on-reset
+* (POR) or brown out detect (BOD), firmware must call Cy_SysClk_IloHibernateOn().
+*
+* Additionally, the ILO clock can be trimmed to +/- 1.5% of nominal frequency using
+* a higher precision clock source. Use the \ref group_sysclk_calclk API to measure
+* the current ILO frequency before trimming.
+*
+* \note The ILO is always the source clock for the \ref group_wdt. Therefore:
+* - The WDT must be unlocked when making an ILO function call in the PDL
+* - It is recommended to always have the ILO enabled
+*
+* \defgroup group_sysclk_ilo_funcs Functions
+* \}
+* \defgroup group_sysclk_pilo Precision Internal Low-Speed Oscillator (PILO)
+* \{
+* PILO provides a higher accuracy 32.768 kHz clock than the \ref group_sysclk_ilo "ILO".
+* When periodically calibrated using a high-accuracy clock such as the
+* \ref group_sysclk_eco "ECO", the PILO can achieve 250 ppm accuracy of nominal frequency.
+* The PILO is capable of operating in device Active, Sleep and Deep-Sleep power modes.
+* It is not available in Hibernate mode.
+*
+* The PILO can be used as a source for the \ref group_sysclk_clk_lf. However,
+* because PILO is disabled in Hibernate mode, RTC timers cannot operate in this mode
+* when clocked using the PILO. Instead, either the \ref group_sysclk_ilo "ILO" or
+* \ref group_sysclk_wco "WCO" should be used when hibernate operation is required.
+*
+* ![](sysclk_backup.png)
+*
+* Periodic calibration to a high-accuracy clock (such as ECO) is required to
+* maintain accuracy. The application should use the functions described in the
+* \ref group_sysclk_calclk API to measure the current PILO frequency before trimming.
+*
+* \defgroup group_sysclk_pilo_funcs Functions
+* \}
+* \defgroup group_sysclk_calclk Clock Measurement
+* \{
+* These functions measure the frequency of a specified clock relative to a
+* reference clock. They are typically called in the following order:
+*
+* 1. Specify the measured clock, the count, and the reference clock
+* 2. Start the counters
+* 3. Wait for the measurement counter to finish counting
+* 4. Retrieve the measured frequency
+*
+* \note These functions may also be used as part of a clock trimming
+* process. Refer to the \ref group_sysclk_trim "Clock Trim" API.
+*
+* \defgroup group_sysclk_calclk_funcs Functions
+* \defgroup group_sysclk_calclk_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_trim Clock Trim (ILO, PILO)
+* \{
+* These functions perform a single trim operation on the ILO or PILO. Each
+* function's parameter is the actual frequency of the clock. To measure the
+* frequency, use the functions described in the \ref group_sysclk_calclk API.
+*
+* To trim the clock as close as possible to the target frequency, multiple
+* calls to the trim function may be needed. A typical usage example is to:
+* 1. Call the clock measurement functions to get the actual frequency of the clock
+* 2. Call the trim function, passing in the measured frequency
+* 3. Repeat the above until the trim function reports that the clock is trimmed to within limits.
+*
+* \defgroup group_sysclk_trim_funcs Functions
+* \}
+* \defgroup group_sysclk_pm Low Power Callback
+* \{
+* Entering and exiting low power modes require compatible clock configurations
+* to be set before entering low power and restored upon wake-up and exit. The
+* SysClk driver provides a Cy_SysClk_DeepSleepCallback() function to support
+* Deep Sleep mode entry.
+*
+* This function can be called either by itself before initiating low-power mode
+* entry or it can be used in conjunction with the SysPm driver as a registered
+* callback. To do so, register this function as a callback before calling
+* Cy_SysPm_DeepSleep(). Specify \ref CY_SYSPM_DEEPSLEEP as the callback type,
+* and call Cy_SysPm_RegisterCallback().
+*
+* \note If the FLL or PLL source is the ECO, this function must be called.
+*
+* \defgroup group_sysclk_pm_funcs Functions
+* \}
+* \defgroup group_sysclk_wco Watch Crystal Oscillator (WCO)
+* \{
+* The WCO is a highly accurate 32.768 kHz clock source capable of operating
+* in all power modes (excluding the Off mode). It is the primary clock source for
+* the backup domain clock, which is used by the real-time clock (RTC). The
+* WCO can also be used as a source for the low-frequency clock to support other
+* low power mode peripherals.
+*
+* ![](sysclk_backup.png)
+*
+* The WCO requires the configuration of the dedicated WCO pins (SRSS_WCO_IN_PIN,
+* SRSS_WCO_OUT_PIN). These must be configured as Analog Hi-Z drive modes and the
+* HSIOM selection set to GPIO. The WCO can also be used in bypass mode, where
+* an external 32.768 kHz square wave is brought in directly through the
+* SRSS_WCO_OUT_PIN pin.
+*
+* \defgroup group_sysclk_wco_funcs Functions
+* \defgroup group_sysclk_wco_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_clk_hf High-Frequency Clocks
+* \{
+* Multiple high frequency clocks (CLK_HF) are available in the device. For example,
+* PSoC 63 series has five high-frequency root clocks. Each CLK_HF has a particular
+* connection and chip-specific destination on the device.
+*
+* |Name |Description |
+* |:--------|:-------------------------------------------------------|
+* |CLK_HF[0]| Root clock for CPUs, PERI, and AHB infrastructure |
+* |CLK_HF[1]| Root clock for the PDM/PCM and I2S audio subsystem |
+* |CLK_HF[2]| Root clock for the Serial Memory Interface subsystem |
+* |CLK_HF[3]| Root clock for USB communications |
+* |CLK_HF[4]| Clock output on clk_ext pin (when used as an output) |
+*
+* ![](sysclk_hf.png)
+*
+* Note this is a particular example. The actual tree may vary depending on the device series.
+* Consult the Technical Reference Manual for your device for details.
+*
+* High frequency clocks are sourced by path clocks, which should be configured
+* first. An exception to this rule is CLK_HF[0], which cannot be disabled.
+* This divided clock drives the core processors and the peripherals in the system.
+* In order to update its clock source, CLK_HF[0] source must be selected without
+* disabling the clock.
+*
+* ![](sysclk_hf_dist.png)
+*
+* \defgroup group_sysclk_clk_hf_funcs Functions
+* \defgroup group_sysclk_clk_hf_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_clk_fast Fast Clock
+* \{
+* The fast clock drives the "fast" processor (e.g. Cortex-M4 processor in PSoC 6).
+* This clock is sourced by CLK_HF[0] (\ref group_sysclk_clk_hf "HF Clocks").
+* A divider value of 1~256 can be used to further divide the CLK_HF[0] to a
+* desired clock speed for the processor.
+*
+* ![](sysclk_fast.png)
+*
+* \defgroup group_sysclk_clk_fast_funcs Functions
+* \}
+* \defgroup group_sysclk_clk_peri Peripheral Clock
+* \{
+* The peripheral clock is a divided clock of CLK_HF0 (\ref group_sysclk_clk_hf "HF Clocks").
+* It is the source clock for the \ref group_sysclk_clk_slow, and most active domain
+* peripheral clocks (\ref group_sysclk_clk_peripheral). A divider value of 1~256
+* can be used to further divide the CLK_HF[0] to a desired clock speed for the peripherals.
+*
+* ![](sysclk_peri.png)
+*
+* \defgroup group_sysclk_clk_peri_funcs Functions
+* \}
+* \defgroup group_sysclk_clk_peripheral Peripherals Clock Dividers
+* \{
+* There are multiple peripheral clock dividers that, in effect, create
+* multiple separate peripheral clocks. The available dividers vary per device
+* series. As an example, for the PSoC 63 series there are 29 dividers:
+*
+* - eight 8-bit dividers
+* - sixteen 16-bit dividers
+* - four fractional 16.5-bit dividers (16 integer bits, 5 fractional bits)
+* - one fractional 24.5-bit divider (24 integer bits, 5 fractional bits)
+*
+*
+* The 8-bit and 16-bit dividers are integer dividers. A divider value of 1
+* means the output frequency matches the input frequency (that is, there is
+* no change). Otherwise the frequency is divided by the value of the divider.
+* For example, if the input frequency is 50 MHz, and the divider is value 10,
+* the output frequency is 5 MHz.
+*
+* The five fractional bits supports further precision in 1/32nd increments. For
+* example, a divider with an integer value of 3 and a fractional value of
+* 4 (4/32) results in a divider of 3.125. Fractional dividers are useful when
+* a high-precision clock is required, for example, for a UART/SPI serial
+* interface.
+*
+* ![](sysclk_peri_divs.png)
+*
+* Each peripheral can connect to any one of the programmable dividers. A
+* particular peripheral clock divider can drive multiple peripherals.
+*
+* The SysClk driver also supports phase aligning two peripheral clock dividers using
+* Cy_SysClk_PeriphEnablePhaseAlignDivider(). Alignment works for both integer
+* and fractional dividers. The divider to which a second divider is aligned
+* must already be enabled.
+*
+* \defgroup group_sysclk_clk_peripheral_funcs Functions
+* \defgroup group_sysclk_clk_peripheral_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_clk_slow Slow Clock
+* \{
+* The slow clock is the source clock for the "slow" processor (e.g. Cortex-M0+ in PSoC 6).
+* This clock is a divided version of the \ref group_sysclk_clk_peri, which in turn is
+* a divided version of CLK_HF[0] (\ref group_sysclk_clk_hf "HF Clocks"). A divider
+* value of 1~256 can be used to further divide the Peri clock to a desired clock speed
+* for the processor.
+*
+* ![](sysclk_slow.png)
+*
+* \defgroup group_sysclk_clk_slow_funcs Functions
+* \}
+* \defgroup group_sysclk_clk_lf Low-Frequency Clock
+* \{
+* The low-frequency clock is the source clock for the \ref group_mcwdt
+* and can be the source clock for \ref group_sysclk_clk_bak, which drives the
+* \ref group_rtc.
+*
+* The low-frequency clock has three possible source clocks:
+* \ref group_sysclk_ilo "ILO", \ref group_sysclk_pilo "PILO", and
+* \ref group_sysclk_wco "WCO".
+*
+* ![](sysclk_lf.png)
+*
+* \defgroup group_sysclk_clk_lf_funcs Functions
+* \defgroup group_sysclk_clk_lf_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_clk_timer Timer Clock
+* \{
+* The timer clock can be a source for the alternative clock driving
+* the \ref group_arm_system_timer. It can also be used as a reference clock
+* for a counter in the \ref group_energy_profiler "Energy Profiler".
+*
+* The timer clock is a divided clock of either the IMO or CLK_HF[0]
+* (\ref group_sysclk_clk_hf "HF Clocks").
+*
+* \defgroup group_sysclk_clk_timer_funcs Functions
+* \defgroup group_sysclk_clk_timer_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_clk_pump Pump Clock
+* \{
+* The pump clock is a clock source used to provide analog precision in low voltage
+* applications. Depending on the usage scenario, it may be required to drive the
+* internal voltage pump for the Continuous Time Block mini (CTBm) in the analog
+* subsystem. The pump clock is a divided clock of one of the clock paths
+* (\ref group_sysclk_path_src).
+*
+* \defgroup group_sysclk_clk_pump_funcs Functions
+* \defgroup group_sysclk_clk_pump_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_clk_bak Backup Domain Clock
+* \{
+* The backup domain clock drives the \ref group_rtc.
+* This clock has two possible source clocks: \ref group_sysclk_wco "WCO"
+* or the \ref group_sysclk_clk_lf. In turn the low frequency clock is sourced by
+* \ref group_sysclk_ilo "ILO", \ref group_sysclk_pilo "PILO", or
+* \ref group_sysclk_wco "WCO". Typically the ILO is not suitable as an RTC source,
+* because of its low accuracy. However the ILO does operate in hibernate mode and
+* may be used as an alternative to the WCO with a tradeoff in precision.
+*
+* \defgroup group_sysclk_clk_bak_funcs Functions
+* \defgroup group_sysclk_clk_bak_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_mf_funcs Medium Frequency Domain Clock
+* \{
+* The Medium Frequency Domain Clock is present only in SRSS_ver1_3.
+* Consists of MFO - the Medium Frequency Oscillator,
+* and CLK_MF - the Medium Frequency Clock divider.
+* This clock chain is designed to source the LCD block
+* in Deep Sleep mode, see \ref cy_en_seglcd_lsclk_t.
+* \}
+*/
+
+#if !defined(CY_SYSCLK_H)
+#define CY_SYSCLK_H
+
+#include <stdbool.h>
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include "cy_syspm.h"
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+* \addtogroup group_sysclk_macros
+* \{
+*/
+/** Driver major version */
+#define CY_SYSCLK_DRV_VERSION_MAJOR 1
+/** Driver minor version */
+#define CY_SYSCLK_DRV_VERSION_MINOR 40
+/** Sysclk driver identifier */
+#define CY_SYSCLK_ID CY_PDL_DRV_ID(0x12U)
+
+/** ILO clock frequency */
+#define CY_SYSCLK_ILO_FREQ (32768UL) /* Hz */
+/** WCO clock frequency */
+#define CY_SYSCLK_WCO_FREQ (32768UL) /* Hz */
+/** PILO clock frequency */
+#define CY_SYSCLK_PILO_FREQ (32768UL) /* Hz */
+
+/** IMO clock frequency */
+#define CY_SYSCLK_IMO_FREQ (8000000UL) /* Hz */
+/** MFO clock frequency */
+#define CY_SYSCLK_MFO_FREQ (2000000UL) /* Hz */
+
+/** \} group_sysclk_macros */
+
+
+/**
+* \addtogroup group_sysclk_returns
+* \{
+*/
+/** Defines general-purpose function return values */
+typedef enum
+{
+ CY_SYSCLK_SUCCESS = 0x00UL, /**< Command completed with no errors */
+ CY_SYSCLK_BAD_PARAM = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x01UL), /**< Invalid function input parameter */
+ CY_SYSCLK_TIMEOUT = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x02UL), /**< Timeout occurred */
+ CY_SYSCLK_INVALID_STATE = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x03UL) /**< Clock is in an invalid state */
+} cy_en_sysclk_status_t;
+/** \} group_sysclk_returns */
+
+
+/* ========================================================================== */
+/* =========================== EXT SECTION ============================ */
+/* ========================================================================== */
+
+/**
+* \addtogroup group_sysclk_ext_funcs
+* \{
+*/
+void Cy_SysClk_ExtClkSetFrequency(uint32_t freq);
+/** \} group_sysclk_ext_funcs */
+
+/* ========================================================================== */
+/* =========================== ECO SECTION ============================ */
+/* ========================================================================== */
+
+/**
+* \addtogroup group_sysclk_macros
+* \{
+*/
+
+/**
+* \defgroup group_sysclk_ecostatus ECO status
+* \{
+* Constants used for expressing ECO status.
+*/
+#define CY_SYSCLK_ECOSTAT_AMPLITUDE 0UL /**< \brief ECO does not have sufficient amplitude */
+#define CY_SYSCLK_ECOSTAT_INACCURATE 1UL /**< \brief ECO may not be meeting accuracy and duty cycle specs */
+#define CY_SYSCLK_ECOSTAT_STABLE 2UL /**< \brief ECO has fully stabilized */
+/** \} */
+
+/** \} group_sysclk_macros */
+
+/** \cond */
+#define SRSS_CLK_ECO_STATUS_Msk (SRSS_CLK_ECO_STATUS_ECO_OK_Msk | SRSS_CLK_ECO_STATUS_ECO_READY_Msk)
+/** \endcond */
+
+
+/**
+* \addtogroup group_sysclk_eco_funcs
+* \{
+*/
+cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint32_t esr, uint32_t driveLevel);
+cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus);
+__STATIC_INLINE void Cy_SysClk_EcoDisable(void);
+__STATIC_INLINE uint32_t Cy_SysClk_EcoGetStatus(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_EcoDisable
+****************************************************************************//**
+*
+* Disables the external crystal oscillator (ECO). This function should not be
+* called if the ECO is sourcing clkHf[0].
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_EcoDisable(void)
+{
+ SRSS_CLK_ECO_CONFIG &= ~SRSS_CLK_ECO_CONFIG_ECO_EN_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_EcoGetStatus
+****************************************************************************//**
+*
+* Reports the current status of the external crystal oscillator (ECO).
+*
+* \return
+* CY_SYSCLK_ECOSTAT_AMPLITUDE = ECO does not have sufficient amplitude \n
+* CY_SYSCLK_ECOSTAT_INACCURATE = ECO has sufficient amplitude but may not be meeting accuracy and duty cycle specifications \n
+* CY_SYSCLK_ECOSTAT_STABLE = ECO has fully stabilized
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoGetStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysClk_EcoGetStatus(void)
+{
+ /* if ECO is not ready, just report the ECO_OK bit. Otherwise report 2 = ECO ready */
+ return ((SRSS_CLK_ECO_STATUS_Msk == (SRSS_CLK_ECO_STATUS_Msk & SRSS_CLK_ECO_STATUS)) ?
+ CY_SYSCLK_ECOSTAT_STABLE : (SRSS_CLK_ECO_STATUS_ECO_OK_Msk & SRSS_CLK_ECO_STATUS));
+}
+/** \} group_sysclk_eco_funcs */
+
+
+/* ========================================================================== */
+/* ==================== INPUT MULTIPLEXER SECTION ===================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_path_src_enums
+* \{
+*/
+/**
+* Input multiplexer clock sources
+*/
+typedef enum
+{
+ CY_SYSCLK_CLKPATH_IN_IMO = 0U, /**< Select the IMO as the output of the path mux */
+ CY_SYSCLK_CLKPATH_IN_EXT = 1U, /**< Select the EXT as the output of the path mux */
+ CY_SYSCLK_CLKPATH_IN_ECO = 2U, /**< Select the ECO as the output of the path mux */
+ CY_SYSCLK_CLKPATH_IN_ALTHF = 3U, /**< Select the ALTHF as the output of the path mux.
+ * Make sure the ALTHF clock source is available on used device.
+ */
+ CY_SYSCLK_CLKPATH_IN_DSIMUX = 4U, /**< Select the DSI MUX output as the output of the path mux */
+ CY_SYSCLK_CLKPATH_IN_DSI = 0x100U, /**< Select a DSI signal (0 - 15) as the output of the DSI mux and path mux.
+ * Make sure the DSI clock sources are available on used device.
+ */
+ CY_SYSCLK_CLKPATH_IN_ILO = 0x110U, /**< Select the ILO (16) as the output of the DSI mux and path mux */
+ CY_SYSCLK_CLKPATH_IN_WCO = 0x111U, /**< Select the WCO (17) as the output of the DSI mux and path mux */
+ CY_SYSCLK_CLKPATH_IN_ALTLF = 0x112U, /**< Select the ALTLF (18) as the output of the DSI mux and path mux.
+ * Make sure the ALTLF clock sources in available on used device.
+ */
+ CY_SYSCLK_CLKPATH_IN_PILO = 0x113U /**< Select the PILO (19) as the output of the DSI mux and path mux.
+ * Make sure the PILO clock sources in available on used device.
+ */
+} cy_en_clkpath_in_sources_t;
+/** \} group_sysclk_path_src_enums */
+
+/**
+* \addtogroup group_sysclk_path_src_funcs
+* \{
+*/
+cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source);
+cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath);
+/** \} group_sysclk_path_src_funcs */
+
+
+/* ========================================================================== */
+/* =========================== FLL SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_fll_enums
+* \{
+*/
+/** FLL and PLL output mode.
+* See registers CLK_FLL_CONFIG3 and CLK_PLL_CONFIG0, bits BYPASS_SEL.
+*/
+typedef enum
+{
+ CY_SYSCLK_FLLPLL_OUTPUT_AUTO = 0U, /**< Output FLL/PLL input source when not locked, and FLL/PLL output when locked */
+ CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 = 1U, /**< Same as AUTO */
+ CY_SYSCLK_FLLPLL_OUTPUT_INPUT = 2U, /**< Output FLL/PLL input source regardless of lock status */
+ CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT = 3U /**< Output FLL/PLL output regardless of lock status. This can be dangerous if used to clock clkHf, because FLL/PLL output may be unstable */
+} cy_en_fll_pll_output_mode_t;
+
+
+/** FLL current-controlled oscillator (CCO) frequency ranges.
+* See register CLK_FLL_CONFIG4, bits CCO_RANGE.
+*/
+typedef enum
+{
+ CY_SYSCLK_FLL_CCO_RANGE0, /**< Target frequency is in range 48 - 64 MHz */
+ CY_SYSCLK_FLL_CCO_RANGE1, /**< Target frequency is in range 64 - 85 MHz */
+ CY_SYSCLK_FLL_CCO_RANGE2, /**< Target frequency is in range 85 - 113 MHz */
+ CY_SYSCLK_FLL_CCO_RANGE3, /**< Target frequency is in range 113 - 150 MHz */
+ CY_SYSCLK_FLL_CCO_RANGE4 /**< Target frequency is in range 150 - 200 MHz */
+} cy_en_fll_cco_ranges_t;
+/** \} group_sysclk_fll_enums */
+
+
+/**
+* \addtogroup group_sysclk_fll_structs
+* \{
+*/
+/** Structure containing information for manual configuration of FLL.
+*/
+typedef struct
+{
+ uint32_t fllMult; /**< CLK_FLL_CONFIG register, FLL_MULT bits */
+ uint16_t refDiv; /**< CLK_FLL_CONFIG2 register, FLL_REF_DIV bits */
+ cy_en_fll_cco_ranges_t ccoRange; /**< CLK_FLL_CONFIG4 register, CCO_RANGE bits */
+ bool enableOutputDiv; /**< CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit */
+ uint16_t lockTolerance; /**< CLK_FLL_CONFIG2 register, LOCK_TOL bits */
+ uint8_t igain; /**< CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits */
+ uint8_t pgain; /**< CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits */
+ uint16_t settlingCount; /**< CLK_FLL_CONFIG3 register, SETTLING_COUNT bits */
+ cy_en_fll_pll_output_mode_t outputMode; /**< CLK_FLL_CONFIG3 register, BYPASS_SEL bits */
+ uint16_t cco_Freq; /**< CLK_FLL_CONFIG4 register, CCO_FREQ bits */
+} cy_stc_fll_manual_config_t;
+/** \} group_sysclk_fll_structs */
+
+/**
+* \addtogroup group_sysclk_fll_funcs
+* \{
+*/
+cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode);
+cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config);
+void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config);
+cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus);
+__STATIC_INLINE bool Cy_SysClk_FllLocked(void);
+__STATIC_INLINE bool Cy_SysClk_FllIsEnabled(void);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_FllDisable(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllIsEnabled
+****************************************************************************//**
+*
+* Reports whether or not the FLL is enabled.
+*
+* \return
+* false = disabled \n
+* true = enabled
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllDisable
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_FllIsEnabled(void)
+{
+ return (_FLD2BOOL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS_CLK_FLL_CONFIG));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllLocked
+****************************************************************************//**
+*
+* Reports whether the FLL is locked first time during FLL starting.
+* Intended to be used with \ref Cy_SysClk_FllEnable with zero timeout.
+*
+* \return
+* false = not locked \n
+* true = locked
+*
+* \note
+* The unlock occurrence may appear during FLL normal operation, so this function
+* is not recommended to check the FLL normal operation stability.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllLocked
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_FllLocked(void)
+{
+ return (_FLD2BOOL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS_CLK_FLL_STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllDisable
+****************************************************************************//**
+*
+* Disables the FLL and the CCO.
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling
+* if it affects the CLK_HF0 frequency.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates after calling this function if
+* the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllDisable
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_FllDisable(void)
+{
+ CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT);
+ SRSS_CLK_FLL_CONFIG &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
+ SRSS_CLK_FLL_CONFIG4 &= ~SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk;
+ return (CY_SYSCLK_SUCCESS);
+}
+/** \} group_sysclk_fll_funcs */
+
+
+/* ========================================================================== */
+/* =========================== PLL SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_pll_structs
+* \{
+*/
+/** Structure containing information for configuration of a PLL.
+*/
+typedef struct
+{
+ uint32_t inputFreq; /**< frequency of PLL source, in Hz */
+ uint32_t outputFreq; /**< frequency of PLL output, in Hz */
+ bool lfMode; /**< CLK_PLL_CONFIG register, PLL_LF_MODE bit */
+ cy_en_fll_pll_output_mode_t outputMode; /**< CLK_PLL_CONFIG register, BYPASS_SEL bits */
+} cy_stc_pll_config_t;
+
+/** Structure containing information for manual configuration of a PLL.
+*/
+typedef struct
+{
+ uint8_t feedbackDiv; /**< CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits */
+ uint8_t referenceDiv; /**< CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits */
+ uint8_t outputDiv; /**< CLK_PLL_CONFIG register, OUTPUT_DIV bits */
+ bool lfMode; /**< CLK_PLL_CONFIG register, PLL_LF_MODE bit */
+ cy_en_fll_pll_output_mode_t outputMode; /**< CLK_PLL_CONFIG register, BYPASS_SEL bits */
+} cy_stc_pll_manual_config_t;
+/** \} group_sysclk_pll_structs */
+
+/**
+* \addtogroup group_sysclk_pll_funcs
+* \{
+*/
+cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_config_t *config);
+cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t *config);
+cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll_manual_config_t *config);
+cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus);
+__STATIC_INLINE bool Cy_SysClk_PllLocked(uint32_t clkPath);
+__STATIC_INLINE bool Cy_SysClk_PllIsEnabled(uint32_t clkPath);
+__STATIC_INLINE bool Cy_SysClk_PllLostLock(uint32_t clkPath);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllIsEnabled
+****************************************************************************//**
+*
+* Reports whether or not the selected PLL is enabled.
+*
+* \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid.
+*
+* \return
+* false = disabled \n
+* true = enabled
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllDisable
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_PllIsEnabled(uint32_t clkPath)
+{
+ clkPath--; /* to correctly access PLL config and status registers structures */
+ CY_ASSERT_L1(clkPath < CY_SRSS_NUM_PLL);
+ return (_FLD2BOOL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS_CLK_PLL_CONFIG[clkPath]));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllLocked
+****************************************************************************//**
+*
+* Reports whether or not the selected PLL is locked.
+*
+* \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid.
+*
+* \return
+* false = not locked \n
+* true = locked
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllLocked
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_PllLocked(uint32_t clkPath)
+{
+ clkPath--; /* to correctly access PLL config and status registers structures */
+ CY_ASSERT_L1(clkPath < CY_SRSS_NUM_PLL);
+ return (_FLD2BOOL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS_CLK_PLL_STATUS[clkPath]));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllLostLock
+****************************************************************************//**
+*
+* Reports whether or not the selected PLL lost its lock since the last time this
+* function was called. Clears the lost lock indicator.
+*
+* \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid.
+*
+* \return
+* false = did not lose lock \n
+* true = lost lock
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllLostLock
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_PllLostLock(uint32_t clkPath)
+{
+ clkPath--; /* to correctly access PLL config and status registers structures */
+ CY_ASSERT_L1(clkPath < CY_SRSS_NUM_PLL);
+ bool retVal = _FLD2BOOL(SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED, SRSS_CLK_PLL_STATUS[clkPath]);
+ /* write a 1 to clear the unlock occurred bit */
+ SRSS_CLK_PLL_STATUS[clkPath] = SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk;
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllDisable
+****************************************************************************//**
+*
+* Disables the selected PLL.
+*
+* \param clkPath Selects which PLL to disable. 1 is the first PLL; 0 is invalid.
+*
+* \return Error / status code: \n
+* CY_SYSCLK_SUCCESS - PLL successfully disabled \n
+* CY_SYSCLK_BAD_PARAM - invalid clock path number
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling
+* if it affects the CLK_HF0 frequency.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates before calling this function if
+* the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates after calling this function if
+* the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllDisable
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ clkPath--; /* to correctly access PLL config and status registers structures */
+ if (clkPath < CY_SRSS_NUM_PLL)
+ {
+ /* First bypass PLL */
+ CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT);
+ /* Wait at least 6 PLL clock cycles */
+ Cy_SysLib_DelayUs(1U);
+ /* And now disable the PLL itself */
+ SRSS_CLK_PLL_CONFIG[clkPath] &= ~SRSS_CLK_PLL_CONFIG_ENABLE_Msk;
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ return (retVal);
+}
+/** \} group_sysclk_pll_funcs */
+
+
+/* ========================================================================== */
+/* =========================== ILO SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_ilo_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_IloEnable(void);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void);
+__STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_IloEnable
+****************************************************************************//**
+*
+* Enables the ILO.
+*
+* \note The watchdog timer (WDT) must be unlocked before calling this function.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_IloEnable(void)
+{
+ SRSS_CLK_ILO_CONFIG |= SRSS_CLK_ILO_CONFIG_ENABLE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_IloDisable
+****************************************************************************//**
+*
+* Disables the ILO. ILO can't be disabled if WDT is enabled.
+*
+* \return Error / status code: \n
+* CY_SYSCLK_SUCCESS - ILO successfully disabled \n
+* CY_SYSCLK_INVALID_STATE - Cannot disable the ILO if the WDT is enabled.
+*
+* \note The watchdog timer (WDT) must be unlocked before calling this function.
+* Do not call this function if the WDT is enabled, because the WDT is clocked by
+* the ILO.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloDisable
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_INVALID_STATE;
+ if (!_FLD2BOOL(SRSS_WDT_CTL_WDT_EN, SRSS_WDT_CTL)) /* if disabled */
+ {
+ SRSS_CLK_ILO_CONFIG &= ~SRSS_CLK_ILO_CONFIG_ENABLE_Msk;
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_IloHibernateOn
+****************************************************************************//**
+*
+* Controls whether the ILO stays on during a hibernate, or through an XRES or
+* brown-out detect (BOD) event.
+*
+* \param on
+* true = ILO stays on during hibernate or across XRES/BOD. \n
+* false = ILO turns off for hibernate or XRES/BOD.
+*
+* \note Writes to the register/bit are ignored if the watchdog (WDT) is locked.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloHibernateOn
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on)
+{
+ CY_REG32_CLR_SET(SRSS_CLK_ILO_CONFIG, SRSS_CLK_ILO_CONFIG_ILO_BACKUP, ((on) ? 1UL : 0UL));
+}
+/** \} group_sysclk_ilo_funcs */
+
+
+/* ========================================================================== */
+/* =========================== PILO SECTION =========================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_pilo_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_PiloEnable(void);
+__STATIC_INLINE void Cy_SysClk_PiloDisable(void);
+__STATIC_INLINE void Cy_SysClk_PiloSetTrim(uint32_t trimVal);
+__STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PiloEnable
+****************************************************************************//**
+*
+* Enables the PILO.
+*
+* \note This function blocks for 1 millisecond between enabling the PILO and
+* releasing the PILO reset.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_PiloEnable(void)
+{
+ SRSS_CLK_PILO_CONFIG |= _VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_EN, 1U); /* 1 = enable */
+ Cy_SysLib_Delay(1U/*msec*/);
+ /* release the reset and enable clock output */
+ SRSS_CLK_PILO_CONFIG |= SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk |
+ SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PiloDisable
+****************************************************************************//**
+*
+* Disables the PILO.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_PiloDisable(void)
+{
+ /* Clear PILO_EN, PILO_RESET_N, and PILO_CLK_EN bitfields. This disables the
+ PILO and holds the PILO in a reset state. */
+ SRSS_CLK_PILO_CONFIG &= (uint32_t)~(SRSS_CLK_PILO_CONFIG_PILO_EN_Msk |
+ SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk |
+ SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PiloSetTrim
+****************************************************************************//**
+*
+* Sets the PILO trim bits, which adjusts the PILO frequency. This is typically
+* done after measuring the PILO frequency; see \ref Cy_SysClk_StartClkMeasurementCounters().
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloSetTrim
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_PiloSetTrim(uint32_t trimVal)
+{
+ CY_REG32_CLR_SET(SRSS_CLK_PILO_CONFIG, SRSS_CLK_PILO_CONFIG_PILO_FFREQ, trimVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PiloGetTrim
+****************************************************************************//**
+*
+* Reports the current PILO trim bits value.
+*
+* \funcusage
+* Refer to the Cy_SysClk_PiloSetTrim() function usage.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void)
+{
+ return (_FLD2VAL(SRSS_CLK_PILO_CONFIG_PILO_FFREQ, SRSS_CLK_PILO_CONFIG));
+}
+/** \} group_sysclk_pilo_funcs */
+
+
+/* ========================================================================== */
+/* ==================== CLOCK MEASUREMENT SECTION ===================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_calclk_enums
+* \{
+*/
+/** Defines all possible clock sources */
+typedef enum
+{
+ CY_SYSCLK_MEAS_CLK_NC = 0U,
+ CY_SYSCLK_MEAS_CLK_ILO = 1U,
+ CY_SYSCLK_MEAS_CLK_WCO = 2U,
+ CY_SYSCLK_MEAS_CLK_BAK = 3U,
+ CY_SYSCLK_MEAS_CLK_ALTLF = 4U,
+ CY_SYSCLK_MEAS_CLK_LFCLK = 5U,
+ CY_SYSCLK_MEAS_CLK_IMO = 6U,
+ CY_SYSCLK_MEAS_CLK_PILO = 8U,
+ CY_SYSCLK_MEAS_CLK_FAST_CLKS = 0x100U,
+ CY_SYSCLK_MEAS_CLK_ECO = 0x101U,
+ CY_SYSCLK_MEAS_CLK_EXT = 0x102U,
+ CY_SYSCLK_MEAS_CLK_ALTHF = 0x103U,
+ CY_SYSCLK_MEAS_CLK_TIMERCLK = 0x104U,
+ CY_SYSCLK_MEAS_CLK_PATH_CLKS = 0x500U,
+ CY_SYSCLK_MEAS_CLK_PATH0 = 0x500U,
+ CY_SYSCLK_MEAS_CLK_PATH1 = 0x501U,
+ CY_SYSCLK_MEAS_CLK_PATH2 = 0x502U,
+ CY_SYSCLK_MEAS_CLK_PATH3 = 0x503U,
+ CY_SYSCLK_MEAS_CLK_PATH4 = 0x504U,
+ CY_SYSCLK_MEAS_CLK_PATH5 = 0x505U,
+ CY_SYSCLK_MEAS_CLK_PATH6 = 0x506U,
+ CY_SYSCLK_MEAS_CLK_PATH7 = 0x507U,
+ CY_SYSCLK_MEAS_CLK_PATH8 = 0x508U,
+ CY_SYSCLK_MEAS_CLK_PATH9 = 0x509U,
+ CY_SYSCLK_MEAS_CLK_PATH10 = 0x50AU,
+ CY_SYSCLK_MEAS_CLK_PATH11 = 0x50BU,
+ CY_SYSCLK_MEAS_CLK_PATH12 = 0x50CU,
+ CY_SYSCLK_MEAS_CLK_PATH13 = 0x50DU,
+ CY_SYSCLK_MEAS_CLK_PATH14 = 0x50EU,
+ CY_SYSCLK_MEAS_CLK_PATH15 = 0x50FU,
+ CY_SYSCLK_MEAS_CLK_CLKHFS = 0x600U,
+ CY_SYSCLK_MEAS_CLK_CLKHF0 = 0x600U,
+ CY_SYSCLK_MEAS_CLK_CLKHF1 = 0x601U,
+ CY_SYSCLK_MEAS_CLK_CLKHF2 = 0x602U,
+ CY_SYSCLK_MEAS_CLK_CLKHF3 = 0x603U,
+ CY_SYSCLK_MEAS_CLK_CLKHF4 = 0x604U,
+ CY_SYSCLK_MEAS_CLK_CLKHF5 = 0x605U,
+ CY_SYSCLK_MEAS_CLK_CLKHF6 = 0x606U,
+ CY_SYSCLK_MEAS_CLK_CLKHF7 = 0x607U,
+ CY_SYSCLK_MEAS_CLK_CLKHF8 = 0x608U,
+ CY_SYSCLK_MEAS_CLK_CLKHF9 = 0x609U,
+ CY_SYSCLK_MEAS_CLK_CLKHF10 = 0x60AU,
+ CY_SYSCLK_MEAS_CLK_CLKHF11 = 0x60BU,
+ CY_SYSCLK_MEAS_CLK_CLKHF12 = 0x60CU,
+ CY_SYSCLK_MEAS_CLK_CLKHF13 = 0x60DU,
+ CY_SYSCLK_MEAS_CLK_CLKHF14 = 0x60EU,
+ CY_SYSCLK_MEAS_CLK_CLKHF15 = 0x60FU,
+ CY_SYSCLK_MEAS_CLK_LAST_CLK = 0x610U
+} cy_en_meas_clks_t;
+/** \} group_sysclk_calclk_enums */
+
+/**
+* \addtogroup group_sysclk_calclk_funcs
+* \{
+*/
+cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t count1, cy_en_meas_clks_t clock2);
+__STATIC_INLINE bool Cy_SysClk_ClkMeasurementCountersDone(void);
+uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t refClkFreq);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkMeasurementCountersDone
+****************************************************************************//**
+*
+* Checks if clock measurement counting is done, that is, counter1 has counted down
+* to zero. Call \ref Cy_SysClk_StartClkMeasurementCounters() before calling this function.
+*
+* \return Status of calibration counters: \n
+* true = done \n
+* false = not done
+*
+* \funcusage
+* Refer to the Cy_SysClk_StartClkMeasurementCounters() function usage.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_ClkMeasurementCountersDone(void)
+{
+ return (_FLD2BOOL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS_CLK_CAL_CNT1));
+}
+/** \} group_sysclk_calclk_funcs */
+
+
+/* ========================================================================== */
+/* ========================== TRIM SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_trim_funcs
+* \{
+*/
+int32_t Cy_SysClk_IloTrim(uint32_t iloFreq);
+int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq);
+/** \} group_sysclk_trim_funcs */
+
+
+/* ========================================================================== */
+/* ====================== POWER MANAGEMENT SECTION ==================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_pm_funcs
+* \{
+*/
+cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
+/** \} group_sysclk_pm_funcs */
+
+
+/* ========================================================================== */
+/* =========================== WCO SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_wco_enums
+* \{
+*/
+/** WCO bypass modes */
+typedef enum
+{
+ CY_SYSCLK_WCO_NOT_BYPASSED = 0U, /**< WCO is not bypassed crystal is used */
+ CY_SYSCLK_WCO_BYPASSED = 1U /**< WCO is bypassed external clock must be supplied on XTAL pin */
+} cy_en_wco_bypass_modes_t;
+/** \} group_sysclk_wco_enums */
+
+/** \cond BWC */
+typedef enum
+{
+ CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO,
+ CY_SYSCLK_WCO_CSV_SUPERVISOR_ALTLF,
+ CY_SYSCLK_WCO_CSV_SUPERVISOR_PILO
+} cy_en_wco_csv_supervisor_clock_t;
+
+typedef enum
+{
+ CY_SYSCLK_CSV_LOSS_4_CYCLES = 0U,
+ CY_SYSCLK_CSV_LOSS_8_CYCLES = 1U,
+ CY_SYSCLK_CSV_LOSS_16_CYCLES = 2U,
+ CY_SYSCLK_CSV_LOSS_32_CYCLES = 3U,
+ CY_SYSCLK_CSV_LOSS_64_CYCLES = 4U,
+ CY_SYSCLK_CSV_LOSS_128_CYCLES = 5U,
+ CY_SYSCLK_CSV_LOSS_256_CYCLES = 6U,
+ CY_SYSCLK_CSV_LOSS_512_CYCLES = 7U
+} cy_en_csv_loss_window_t;
+
+typedef enum
+{
+ CY_SYSCLK_CSV_ERROR_IGNORE = 0U,
+ CY_SYSCLK_CSV_ERROR_FAULT = 1U,
+ CY_SYSCLK_CSV_ERROR_RESET = 2U,
+ CY_SYSCLK_CSV_ERROR_FAULT_RESET = 3U
+} cy_en_csv_error_actions_t;
+
+typedef struct
+{
+ cy_en_wco_csv_supervisor_clock_t supervisorClock;
+ bool enableLossDetection;
+ cy_en_csv_loss_window_t lossWindow;
+ cy_en_csv_error_actions_t lossAction;
+} cy_stc_wco_csv_config_t;
+/** \endcond */
+
+/**
+* \addtogroup group_sysclk_wco_funcs
+* \{
+*/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus);
+__STATIC_INLINE bool Cy_SysClk_WcoOkay(void);
+__STATIC_INLINE void Cy_SysClk_WcoDisable(void);
+__STATIC_INLINE void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_WcoEnable
+****************************************************************************//**
+*
+* Enables the WCO.
+*
+* \param timeoutus amount of time in microseconds to wait for the WCO to be ready.
+* If WCO is not ready, WCO is stopped. To avoid waiting for WCO ready set this to 0,
+* and manually check if WCO is okay using \ref Cy_SysClk_WcoOkay.
+*
+* \return Error / status code: \n
+* CY_SYSCLK_SUCCESS - WCO successfully enabled \n
+* CY_SYSCLK_TIMEOUT - Timeout waiting for WCO to stabilize
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoEnable
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_TIMEOUT;
+
+ /* first set the WCO enable bit */
+ BACKUP_CTL |= BACKUP_CTL_WCO_EN_Msk;
+
+ /* now do the timeout wait for STATUS, bit WCO_OK */
+ for (; (Cy_SysClk_WcoOkay() == false) && (0UL != timeoutus); timeoutus--)
+ {
+ Cy_SysLib_DelayUs(1U);
+ }
+
+ if (0UL != timeoutus)
+ {
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_WcoOkay
+****************************************************************************//**
+*
+* Reports the status of the WCO_OK bit.
+*
+* \return
+* true = okay \n
+* false = not okay
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoOkay
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_WcoOkay(void)
+{
+ return (_FLD2BOOL(BACKUP_STATUS_WCO_OK, BACKUP_STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_WcoDisable
+****************************************************************************//**
+*
+* Disables the WCO.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_WcoDisable(void)
+{
+ BACKUP_CTL &= (uint32_t)~BACKUP_CTL_WCO_EN_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_WcoBypass
+****************************************************************************//**
+*
+* Sets whether the WCO is bypassed or not. If it is bypassed, then a 32-kHz clock
+* must be provided on the wco_out pin.
+*
+* \param bypass \ref cy_en_wco_bypass_modes_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoBypass
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass)
+{
+ CY_REG32_CLR_SET(BACKUP_CTL, BACKUP_CTL_WCO_BYPASS, bypass);
+}
+/** \} group_sysclk_wco_funcs */
+
+
+/* ========================================================================== */
+/* ============================ MF SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_mf_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_MfoEnable(bool deepSleepEnable);
+__STATIC_INLINE bool Cy_SysClk_MfoIsEnabled(void);
+__STATIC_INLINE void Cy_SysClk_MfoDisable(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_MfoEnable
+****************************************************************************//**
+*
+* Enables the MFO.
+*
+* \param deepSleepEnable enables MFO operation is Deep Sleep low power mode.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_MfoEnable(bool deepSleepEnable)
+{
+ if (CY_SRSS_MFO_PRESENT)
+ {
+ SRSS_CLK_MFO_CONFIG = SRSS_CLK_MFO_CONFIG_ENABLE_Msk | (deepSleepEnable ? SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Msk : 0UL);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_MfoIsEnabled
+****************************************************************************//**
+*
+* Reports whether MFO is enabled or not.
+*
+* \return
+* false - disabled \n
+* true - enabled
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_MfoIsEnabled(void)
+{
+ return (CY_SRSS_MFO_PRESENT && (0UL != (SRSS_CLK_MFO_CONFIG & SRSS_CLK_MFO_CONFIG_ENABLE_Msk)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_MfoDisable
+****************************************************************************//**
+*
+* Disables the MFO.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_MfoDisable(void)
+{
+ if (CY_SRSS_MFO_PRESENT)
+ {
+ SRSS_CLK_MFO_CONFIG = 0UL;
+ }
+}
+
+
+__STATIC_INLINE void Cy_SysClk_ClkMfEnable(void);
+__STATIC_INLINE bool Cy_SysClk_ClkMfIsEnabled(void);
+__STATIC_INLINE void Cy_SysClk_ClkMfDisable(void);
+__STATIC_INLINE void Cy_SysClk_ClkMfSetDivider(uint32_t divider);
+__STATIC_INLINE uint32_t Cy_SysClk_ClkMfGetDivider(void);
+__STATIC_INLINE uint32_t Cy_SysClk_ClkMfGetFrequency(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkMfEnable
+****************************************************************************//**
+*
+* Enables the CLK_MF.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkMfEnable(void)
+{
+ if (CY_SRSS_MFO_PRESENT)
+ {
+ SRSS_CLK_MF_SELECT |= SRSS_CLK_MF_SELECT_ENABLE_Msk;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkMfIsEnabled
+****************************************************************************//**
+*
+* Reports whether CLK_MF is enabled or not.
+*
+* \return
+* false - disabled \n
+* true - enabled
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_ClkMfIsEnabled(void)
+{
+ return ((CY_SRSS_MFO_PRESENT) && (0UL != (SRSS_CLK_MF_SELECT & SRSS_CLK_MF_SELECT_ENABLE_Msk)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkMfDisable
+****************************************************************************//**
+*
+* Disables the CLK_MF.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkMfDisable(void)
+{
+ if (CY_SRSS_MFO_PRESENT)
+ {
+ SRSS_CLK_MF_SELECT &= ~SRSS_CLK_MF_SELECT_ENABLE_Msk;
+ }
+}
+
+
+/** \cond internal */
+#define CY_SYSCLK_MF_DIVIDER_MIN (1U)
+#define CY_SYSCLK_MF_DIVIDER_MAX (256U)
+#define CY_SYSCLK_IS_MF_DIVIDER_VALID(locDiv) ((CY_SYSCLK_MF_DIVIDER_MIN <= (locDiv)) && ((locDiv) <= CY_SYSCLK_MF_DIVIDER_MAX))
+/** \endcond */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkMfSetDivider
+****************************************************************************//**
+*
+* Sets the clock divider for CLK_MF.
+*
+* \pre If the CLK_MF is already enabled - it should be disabled
+* prior to use this function by \ref Cy_SysClk_ClkMfDisable.
+*
+* \param divider divider value between 1 and 256.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkMfSetDivider(uint32_t divider)
+{
+ if ((CY_SRSS_MFO_PRESENT) && CY_SYSCLK_IS_MF_DIVIDER_VALID(divider))
+ {
+ if (!Cy_SysClk_ClkMfIsEnabled())
+ {
+ CY_REG32_CLR_SET(SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_MFCLK_DIV, divider - 1UL);
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkMfGetDivider
+****************************************************************************//**
+*
+* Returns the clock divider of CLK_MF.
+*
+* \return divider value in range 1..256.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysClk_ClkMfGetDivider(void)
+{
+ return ((CY_SRSS_MFO_PRESENT) ? (1UL + _FLD2VAL(SRSS_CLK_MF_SELECT_MFCLK_DIV, SRSS_CLK_MF_SELECT)) : 1UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkMfGetFrequency
+****************************************************************************//**
+*
+* Reports the output clock signal frequency of CLK_MF.
+*
+* \return The frequency, in Hz.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysClk_ClkMfGetFrequency(void)
+{
+ uint32_t locFreq = (Cy_SysClk_MfoIsEnabled()) ? CY_SYSCLK_MFO_FREQ : 0UL; /* Get root frequency */
+ uint32_t locDiv = Cy_SysClk_ClkMfGetDivider(); /* clkMf prescaler (1-256) */
+
+ /* Divide the path input frequency down and return the result */
+ return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv));
+}
+/** \} group_sysclk_mf_funcs */
+
+
+/* ========================================================================== */
+/* ========================= clkHf[n] SECTION ========================= */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_hf_enums
+* \{
+*/
+/**
+* Selects which clkHf input, or root mux, to configure.
+* See CLK_ROOT_SELECT registers, bits ROOT_MUX.
+* Used with functions \ref Cy_SysClk_ClkHfSetSource and \ref Cy_SysClk_ClkHfGetSource.
+*/
+typedef enum
+{
+ CY_SYSCLK_CLKHF_IN_CLKPATH0 = 0U, /**< clkHf input is Clock Path 0 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH1 = 1U, /**< clkHf input is Clock Path 1 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH2 = 2U, /**< clkHf input is Clock Path 2 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH3 = 3U, /**< clkHf input is Clock Path 3 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH4 = 4U, /**< clkHf input is Clock Path 4 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH5 = 5U, /**< clkHf input is Clock Path 5 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH6 = 6U, /**< clkHf input is Clock Path 6 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH7 = 7U, /**< clkHf input is Clock Path 7 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH8 = 8U, /**< clkHf input is Clock Path 8 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH9 = 9U, /**< clkHf input is Clock Path 9 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH10 = 10U, /**< clkHf input is Clock Path 10 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH11 = 11U, /**< clkHf input is Clock Path 11 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH12 = 12U, /**< clkHf input is Clock Path 12 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH13 = 13U, /**< clkHf input is Clock Path 13 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH14 = 14U, /**< clkHf input is Clock Path 14 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH15 = 15U, /**< clkHf input is Clock Path 15 */
+} cy_en_clkhf_in_sources_t;
+
+
+/**
+* clkHf divider values. See CLK_ROOT_SELECT registers, bits ROOT_DIV.
+* Used with functions \ref Cy_SysClk_ClkHfSetDivider and \ref Cy_SysClk_ClkHfGetDivider.
+*/
+typedef enum
+{
+ CY_SYSCLK_CLKHF_NO_DIVIDE = 0U, /**< don't divide clkHf */
+ CY_SYSCLK_CLKHF_DIVIDE_BY_2 = 1U, /**< divide clkHf by 2 */
+ CY_SYSCLK_CLKHF_DIVIDE_BY_4 = 2U, /**< divide clkHf by 4 */
+ CY_SYSCLK_CLKHF_DIVIDE_BY_8 = 3U /**< divide clkHf by 8 */
+} cy_en_clkhf_dividers_t;
+/** \} group_sysclk_clk_hf_enums */
+
+/** \cond BWC */
+typedef enum
+{
+ CY_SYSCLK_CLKHF_CSV_SUPERVISOR_IMO = 0U,
+ CY_SYSCLK_CLKHF_CSV_SUPERVISOR_EXT = 1U,
+ CY_SYSCLK_CLKHF_CSV_SUPERVISOR_ALTHF = 2U
+} cy_en_clkhf_csv_supervisor_clock_t;
+
+typedef struct
+{
+ cy_en_clkhf_csv_supervisor_clock_t supervisorClock;
+ uint16_t supervisingWindow;
+ bool enableFrequencyFaultDetection;
+ uint16_t frequencyLowerLimit;
+ uint16_t frequencyUpperLimit;
+ cy_en_csv_error_actions_t frequencyAction;
+ bool enableLossDetection;
+ cy_en_csv_loss_window_t lossWindow;
+ cy_en_csv_error_actions_t lossAction;
+} cy_stc_clkhf_csv_config_t;
+/** \endcond */
+
+/** \cond INTERNAL */
+extern uint32_t altHfFreq; /* Internal storage for BLE ECO frequency user setting */
+/** \endcond */
+
+/**
+* \addtogroup group_sysclk_clk_hf_funcs
+* \{
+*/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source);
+__STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider);
+__STATIC_INLINE cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf);
+ uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfEnable
+****************************************************************************//**
+*
+* Enables the selected clkHf.
+*
+* \param clkHf Selects which clkHf to enable.
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ if (clkHf < CY_SRSS_NUM_HFROOT)
+ {
+ SRSS_CLK_ROOT_SELECT[clkHf] |= SRSS_CLK_ROOT_SELECT_ENABLE_Msk;
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfDisable
+****************************************************************************//**
+*
+* Disables the selected clkHf.
+*
+* \param clkHf Selects which clkHf to enable.
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \note clkHf[0] cannot be disabled.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfDisable
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ if ((0UL < clkHf) /* prevent CLK_HF0 disabling */
+ && (clkHf < CY_SRSS_NUM_HFROOT))
+ {
+ SRSS_CLK_ROOT_SELECT[clkHf] &= ~SRSS_CLK_ROOT_SELECT_ENABLE_Msk;
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfSetSource
+****************************************************************************//**
+*
+* Selects the source of the selected clkHf.
+*
+* \param clkHf selects which clkHf mux to configure.
+*
+* \param source \ref cy_en_clkhf_in_sources_t
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling
+* if it affects the CLK_HF0 frequency.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates before calling this function if
+* CLK_HF0 frequency is increasing.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates after calling this function if
+* CLK_HF0 frequency is decreasing.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ if ((clkHf < CY_SRSS_NUM_HFROOT) && (source <= CY_SYSCLK_CLKHF_IN_CLKPATH15))
+ {
+ CY_REG32_CLR_SET(SRSS_CLK_ROOT_SELECT[clkHf], SRSS_CLK_ROOT_SELECT_ROOT_MUX, source);
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfGetSource
+****************************************************************************//**
+*
+* Reports the source of the selected clkHf.
+*
+* \param clkHf selects which clkHf to get the source of.
+*
+* \return \ref cy_en_clkhf_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf)
+{
+ CY_ASSERT_L1(clkHf < CY_SRSS_NUM_HFROOT);
+ return ((cy_en_clkhf_in_sources_t)(_FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS_CLK_ROOT_SELECT[clkHf])));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfSetDivider
+****************************************************************************//**
+*
+* Sets the pre-divider for a clkHf.
+*
+* \param clkHf selects which clkHf divider to configure.
+*
+* \param divider \ref cy_en_clkhf_dividers_t
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \note Also call \ref Cy_SysClk_ClkHfSetSource to set the clkHf source.
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling
+* if it affects the CLK_HF0 frequency.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates before calling this function if
+* CLK_HF0 frequency is increasing.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates after calling this function if
+* CLK_HF0 frequency is decreasing.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ if ((clkHf < CY_SRSS_NUM_HFROOT) && (divider <= CY_SYSCLK_CLKHF_DIVIDE_BY_8))
+ {
+ CY_REG32_CLR_SET(SRSS_CLK_ROOT_SELECT[clkHf], SRSS_CLK_ROOT_SELECT_ROOT_DIV, divider);
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfGetDivider
+****************************************************************************//**
+*
+* Reports the pre-divider value for a clkHf.
+*
+* \param clkHf selects which clkHf to check divider of.
+*
+* \return \ref cy_en_clkhf_dividers_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf)
+{
+ CY_ASSERT_L1(clkHf < CY_SRSS_NUM_HFROOT);
+ return ((cy_en_clkhf_dividers_t)(_FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS_CLK_ROOT_SELECT[clkHf])));
+}
+/** \} group_sysclk_clk_hf_funcs */
+
+
+/* ========================================================================== */
+/* ========================= clk_fast SECTION ========================= */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_fast_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkFastSetDivider(uint8_t divider);
+__STATIC_INLINE uint8_t Cy_SysClk_ClkFastGetDivider(void);
+__STATIC_INLINE uint32_t Cy_SysClk_ClkFastGetFrequency(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkFastGetFrequency
+****************************************************************************//**
+*
+* Reports the frequency of the fast clock.
+*
+* \return The frequency, in Hz.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysClk_ClkFastGetFrequency(void)
+{
+ uint32_t locFreq = Cy_SysClk_ClkHfGetFrequency(0UL); /* Get root frequency */
+ uint32_t locDiv = 1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider(); /* fast prescaler (1-256) */
+
+ /* Divide the path input frequency down and return the result */
+ return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkFastSetDivider
+****************************************************************************//**
+*
+* Sets the clock divider for the fast clock, which sources the main processor.
+* The source of this divider is clkHf[0].
+*
+* \param divider divider value between 0 and 255.
+* Causes integer division of (divider value + 1), or division by 1 to 256.
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates before calling this function if
+* CLK_FAST frequency is increasing.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates after calling this function if
+* CLK_FAST frequency is decreasing.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkFastSetDivider(uint8_t divider)
+{
+ CY_REG32_CLR_SET(CPUSS_CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, divider);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkFastGetDivider
+****************************************************************************//**
+*
+* Returns the clock divider for the fast clock.
+*
+* \return The divider value for the fast clock.
+* The integer division done is by (divider value + 1), or division by 1 to 256.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_SysClk_ClkFastGetDivider(void)
+{
+ return ((uint8_t)_FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS_CM4_CLOCK_CTL));
+}
+/** \} group_sysclk_clk_fast_funcs */
+
+
+/* ========================================================================== */
+/* ======================== clk_peri SECTION ========================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_peri_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkPeriSetDivider(uint8_t divider);
+__STATIC_INLINE uint8_t Cy_SysClk_ClkPeriGetDivider(void);
+__STATIC_INLINE uint32_t Cy_SysClk_ClkPeriGetFrequency(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPeriGetFrequency
+****************************************************************************//**
+*
+* Reports the frequency of the peri clock.
+*
+* \return The frequency, in Hz.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysClk_ClkPeriGetFrequency(void)
+{
+ uint32_t locFreq = Cy_SysClk_ClkHfGetFrequency(0UL); /* Get root frequency */
+ uint32_t locDiv = 1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider(); /* peri prescaler (1-256) */
+
+ /* Divide the path input frequency down and return the result */
+ return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPeriSetDivider
+****************************************************************************//**
+*
+* Sets the clock divider for the peripheral clock tree. All peripheral clock
+* dividers are sourced from this clock. Also the Cortex M0+ clock divider is
+* sourced from this clock. The source of this divider is clkHf[0]
+*
+* \param divider divider value between 0 and 255
+* Causes integer division of (divider value + 1), or division by 1 to 256.
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkPeriSetDivider(uint8_t divider)
+{
+ CY_REG32_CLR_SET(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, divider);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPeriGetDivider
+****************************************************************************//**
+*
+* Returns the clock divider of the peripheral (peri) clock.
+*
+* \return The divider value.
+* The integer division done is by (divider value + 1), or division by 1 to 256.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_SysClk_ClkPeriGetDivider(void)
+{
+ return ((uint8_t)_FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS_CM0_CLOCK_CTL));
+}
+/** \} group_sysclk_clk_peri_funcs */
+
+
+/* ========================================================================== */
+/* ===================== clk_peripherals SECTION ====================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_peripheral_enums
+* \{
+*/
+/** Programmable clock divider types */
+typedef enum
+{
+ CY_SYSCLK_DIV_8_BIT = 0U, /**< Divider Type is an 8 bit divider */
+ CY_SYSCLK_DIV_16_BIT = 1U, /**< Divider Type is a 16 bit divider */
+ CY_SYSCLK_DIV_16_5_BIT = 2U, /**< Divider Type is a 16.5 bit fractional divider */
+ CY_SYSCLK_DIV_24_5_BIT = 3U /**< Divider Type is a 24.5 bit fractional divider */
+} cy_en_divider_types_t;
+/** \} group_sysclk_clk_peripheral_enums */
+
+
+/**
+* \addtogroup group_sysclk_clk_peripheral_funcs
+* \{
+*/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphSetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, uint32_t dividerValue);
+__STATIC_INLINE uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphSetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, uint32_t dividerIntValue, uint32_t dividerFracValue);
+__STATIC_INLINE void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, uint32_t *dividerIntValue, uint32_t *dividerFracValue);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphAssignDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum);
+__STATIC_INLINE uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphEnableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphDisableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphEnablePhaseAlignDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA);
+__STATIC_INLINE bool Cy_SysClk_PeriphGetDividerEnabled(cy_en_divider_types_t dividerType, uint32_t dividerNum);
+uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_t dividerNum);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphSetDivider
+****************************************************************************//**
+*
+* Sets one of the programmable clock dividers. This is only used for integer
+* dividers. Use \ref Cy_SysClk_PeriphSetFracDivider for setting factional dividers.
+*
+* \pre If the specified clock divider is already enabled - it should be disabled
+* prior to use this function by \ref Cy_SysClk_PeriphDisableDivider.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum the divider number.
+*
+* \param dividerValue divider value
+* Causes integer division of (divider value + 1), or division by 1 to 256
+* (8-bit divider) or 1 to 65536 (16-bit divider).
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t
+ Cy_SysClk_PeriphSetDivider(cy_en_divider_types_t dividerType,
+ uint32_t dividerNum, uint32_t dividerValue)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ if (dividerType == CY_SYSCLK_DIV_8_BIT)
+ {
+ if ((dividerNum < PERI_DIV_8_NR) &&
+ (dividerValue <= (PERI_DIV_8_CTL_INT8_DIV_Msk >> PERI_DIV_8_CTL_INT8_DIV_Pos)))
+ {
+ CY_REG32_CLR_SET(PERI_DIV_8_CTL[dividerNum], PERI_DIV_8_CTL_INT8_DIV, dividerValue);
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ }
+ else if (dividerType == CY_SYSCLK_DIV_16_BIT)
+ {
+ if ((dividerNum < PERI_DIV_16_NR) &&
+ (dividerValue <= (PERI_DIV_16_CTL_INT16_DIV_Msk >> PERI_DIV_16_CTL_INT16_DIV_Pos)))
+ {
+ CY_REG32_CLR_SET(PERI_DIV_16_CTL[dividerNum], PERI_DIV_16_CTL_INT16_DIV, dividerValue);
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ }
+ else
+ { /* return bad parameter */
+ }
+ return (retVal);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphGetDivider
+****************************************************************************//**
+*
+* Returns the integer divider value for the specified divider. One works for
+* integer dividers. Use \ref Cy_SysClk_PeriphGetFracDivider to get the fractional
+* divider value
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum specifies which divider of the selected type to configure
+*
+* \return The divider value.
+* The integer division done is by (divider value + 1), or division by 1 to 256
+* (8-bit divider) or 1 to 65536 (16-bit divider).
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum)
+{
+ uint32_t retVal;
+
+ CY_ASSERT_L1(dividerType <= CY_SYSCLK_DIV_16_BIT);
+
+ if (dividerType == CY_SYSCLK_DIV_8_BIT)
+ {
+ CY_ASSERT_L1(dividerNum < PERI_DIV_8_NR);
+ retVal = _FLD2VAL(PERI_DIV_8_CTL_INT8_DIV, PERI_DIV_8_CTL[dividerNum]);
+ }
+ else
+ { /* 16-bit divider */
+ CY_ASSERT_L1(dividerNum < PERI_DIV_16_NR);
+ retVal = _FLD2VAL(PERI_DIV_16_CTL_INT16_DIV, PERI_DIV_16_CTL[dividerNum]);
+ }
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphSetFracDivider
+****************************************************************************//**
+*
+* Sets one of the programmable clock dividers. This function should only be used
+* for fractional clock dividers.
+*
+* \pre If the specified clock divider is already enabled - it should be disabled
+* prior to use this function by \ref Cy_SysClk_PeriphDisableDivider.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum specifies which divider of the selected type to configure
+*
+* \param dividerIntValue the integer divider value
+* The source of the divider is peri_clk, which is a divided version of hf_clk[0].
+* The divider value causes integer division of (divider value + 1), or division
+* by 1 to 65536 (16-bit divider) or 1 to 16777216 (24-bit divider).
+*
+* \param dividerFracValue the fraction part of the divider
+* The fractional divider can be 1-32, thus it divides the clock by 1/32 for each
+* count. To divide the clock by 11/32nds set this value to 11.
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetFracDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t
+ Cy_SysClk_PeriphSetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum,
+ uint32_t dividerIntValue, uint32_t dividerFracValue)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ if (dividerType == CY_SYSCLK_DIV_16_5_BIT)
+ {
+ if ((dividerNum < PERI_DIV_16_5_NR) &&
+ (dividerIntValue <= (PERI_DIV_16_5_CTL_INT16_DIV_Msk >> PERI_DIV_16_5_CTL_INT16_DIV_Pos)) &&
+ (dividerFracValue <= (PERI_DIV_16_5_CTL_FRAC5_DIV_Msk >> PERI_DIV_16_5_CTL_FRAC5_DIV_Pos)))
+ {
+ CY_REG32_CLR_SET(PERI_DIV_16_5_CTL[dividerNum], PERI_DIV_16_5_CTL_INT16_DIV, dividerIntValue);
+ CY_REG32_CLR_SET(PERI_DIV_16_5_CTL[dividerNum], PERI_DIV_16_5_CTL_FRAC5_DIV, dividerFracValue);
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ }
+ else if (dividerType == CY_SYSCLK_DIV_24_5_BIT)
+ {
+ if ((dividerNum < PERI_DIV_24_5_NR) &&
+ (dividerIntValue <= (PERI_DIV_24_5_CTL_INT24_DIV_Msk >> PERI_DIV_24_5_CTL_INT24_DIV_Pos)) &&
+ (dividerFracValue <= (PERI_DIV_24_5_CTL_FRAC5_DIV_Msk >> PERI_DIV_24_5_CTL_FRAC5_DIV_Pos)))
+ {
+ CY_REG32_CLR_SET(PERI_DIV_24_5_CTL[dividerNum], PERI_DIV_24_5_CTL_INT24_DIV, dividerIntValue);
+ CY_REG32_CLR_SET(PERI_DIV_24_5_CTL[dividerNum], PERI_DIV_24_5_CTL_FRAC5_DIV, dividerFracValue);
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ }
+ else
+ { /* return bad parameter */
+ }
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphGetFracDivider
+****************************************************************************//**
+*
+* Reports the integer and fractional parts of the divider
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum specifies which divider of the selected type to configure
+*
+* \param *dividerIntValue pointer to return integer divider value
+*
+* \param *dividerFracValue pointer to return fractional divider value
+*
+* \return None. Loads pointed-to variables.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetFracDivider
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum,
+ uint32_t *dividerIntValue, uint32_t *dividerFracValue)
+{
+ CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_16_5_BIT) || (dividerType == CY_SYSCLK_DIV_24_5_BIT)) &&
+ (dividerIntValue != NULL) && (dividerFracValue != NULL));
+
+ if (dividerType == CY_SYSCLK_DIV_16_5_BIT)
+ {
+ CY_ASSERT_L1(dividerNum < PERI_DIV_16_5_NR);
+ *dividerIntValue = _FLD2VAL(PERI_DIV_16_5_CTL_INT16_DIV, PERI_DIV_16_5_CTL[dividerNum]);
+ *dividerFracValue = _FLD2VAL(PERI_DIV_16_5_CTL_FRAC5_DIV, PERI_DIV_16_5_CTL[dividerNum]);
+ }
+ else
+ { /* 24.5-bit divider */
+ CY_ASSERT_L1(dividerNum < PERI_DIV_24_5_NR);
+ *dividerIntValue = _FLD2VAL(PERI_DIV_24_5_CTL_INT24_DIV, PERI_DIV_24_5_CTL[dividerNum]);
+ *dividerFracValue = _FLD2VAL(PERI_DIV_24_5_CTL_FRAC5_DIV, PERI_DIV_24_5_CTL[dividerNum]);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphAssignDivider
+****************************************************************************//**
+*
+* Assigns a programmable divider to a selected IP block, such as a TCPWM or SCB.
+*
+* \param ipBlock specifies ip block to connect the clock divider to.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum specifies which divider of the selected type to configure
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphAssignDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t
+ Cy_SysClk_PeriphAssignDivider(en_clk_dst_t ipBlock,
+ cy_en_divider_types_t dividerType, uint32_t dividerNum)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ if ((CY_PERI_CLOCK_NR > (uint32_t)ipBlock) && (CY_SYSCLK_DIV_24_5_BIT >= dividerType))
+ {
+ if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR)))
+ {
+ PERI_CLOCK_CTL[ipBlock] = _VAL2FLD(CY_PERI_CLOCK_CTL_TYPE_SEL, dividerType) |
+ _VAL2FLD(CY_PERI_CLOCK_CTL_DIV_SEL, dividerNum);
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ }
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphGetAssignedDivider
+****************************************************************************//**
+*
+* Reports which clock divider is assigned to a selected IP block.
+*
+* \param ipBlock specifies ip block to connect the clock divider to.
+*
+* \return The divider type and number, where bits [7:6] = type, bits[5:0] = divider
+* number within that type
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphAssignDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock)
+{
+ CY_ASSERT_L1(CY_PERI_CLOCK_NR > (uint32_t)ipBlock);
+ return (PERI_CLOCK_CTL[ipBlock] & (CY_PERI_CLOCK_CTL_DIV_SEL_Msk | CY_PERI_CLOCK_CTL_TYPE_SEL_Msk));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphEnableDivider
+****************************************************************************//**
+*
+* Enables the selected divider.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum specifies which divider of the selected type to configure
+*
+* \note This function also sets the phase alignment bits such that the enabled
+* divider is aligned to clk_peri. See \ref Cy_SysClk_PeriphDisableDivider()
+* for information on how to phase-align a divider after it is enabled.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphEnableDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t
+ Cy_SysClk_PeriphEnableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ if (dividerType <= CY_SYSCLK_DIV_24_5_BIT)
+ {
+ if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR)))
+ {
+ /* specify the divider, make the reference = clk_peri, and enable the divider */
+ PERI_DIV_CMD = PERI_DIV_CMD_ENABLE_Msk |
+ CY_PERI_DIV_CMD_PA_TYPE_SEL_Msk |
+ CY_PERI_DIV_CMD_PA_DIV_SEL_Msk |
+ _VAL2FLD(CY_PERI_DIV_CMD_TYPE_SEL, dividerType) |
+ _VAL2FLD(CY_PERI_DIV_CMD_DIV_SEL, dividerNum);
+ (void)PERI_DIV_CMD; /* dummy read to handle buffered writes */
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ }
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphDisableDivider
+****************************************************************************//**
+*
+* Disables a selected divider.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t.
+*
+* \param dividerNum specifies which divider of the selected type to configure.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphDisableDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t
+ Cy_SysClk_PeriphDisableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ if (dividerType <= CY_SYSCLK_DIV_24_5_BIT)
+ {
+ if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR)))
+ {
+ /* specify the divider and disable it */
+ PERI_DIV_CMD = PERI_DIV_CMD_DISABLE_Msk |
+ _VAL2FLD(CY_PERI_DIV_CMD_TYPE_SEL, dividerType) |
+ _VAL2FLD(CY_PERI_DIV_CMD_DIV_SEL, dividerNum);
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ }
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphEnablePhaseAlignDivider
+****************************************************************************//**
+*
+* First disables a selected divider (\ref Cy_SysClk_PeriphDisableDivider),
+* then aligns that divider to another programmable divider, and enables the
+* selected divider. The divider to align to must already be enabled in order
+* to align a divider to it.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t.
+*
+* \param dividerNum specifies which divider of the selected type to configure.
+*
+* \param dividerTypePA type of divider to phase-align to; \ref cy_en_divider_types_t.
+*
+* \param dividerNumPA divider number of type specified to phase align to.
+*
+* \note
+* To phase-align a divider to clk_peri, set dividerTypePA to 3 and dividerNumPA
+* to 63.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphEnablePhaseAlignDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t
+ Cy_SysClk_PeriphEnablePhaseAlignDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum,
+ cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ if (dividerTypePA <= CY_SYSCLK_DIV_24_5_BIT)
+ {
+ if (((dividerTypePA == CY_SYSCLK_DIV_8_BIT) && (dividerNumPA < PERI_DIV_8_NR)) ||
+ ((dividerTypePA == CY_SYSCLK_DIV_16_BIT) && (dividerNumPA < PERI_DIV_16_NR)) ||
+ ((dividerTypePA == CY_SYSCLK_DIV_16_5_BIT) && (dividerNumPA < PERI_DIV_16_5_NR)) ||
+ ((dividerTypePA == CY_SYSCLK_DIV_24_5_BIT) && ((dividerNumPA < PERI_DIV_24_5_NR) || (dividerNumPA == 63u))))
+ {
+ /* First, disable the divider that is to be phase-aligned.
+ The other two parameters are checked in that function;
+ if they're not valid, the divider is not disabled. */
+ retVal = Cy_SysClk_PeriphDisableDivider(dividerType, dividerNum);
+ if (retVal == CY_SYSCLK_SUCCESS)
+ {
+ /* Then, specify the reference divider, and the divider, and enable the divider */
+ PERI_DIV_CMD = PERI_DIV_CMD_ENABLE_Msk |
+ _VAL2FLD(CY_PERI_DIV_CMD_PA_TYPE_SEL, dividerTypePA) |
+ _VAL2FLD(CY_PERI_DIV_CMD_PA_DIV_SEL, dividerNumPA) |
+ _VAL2FLD(CY_PERI_DIV_CMD_TYPE_SEL, dividerType) |
+ _VAL2FLD(CY_PERI_DIV_CMD_DIV_SEL, dividerNum);
+ }
+ }
+ }
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphGetDividerEnabled
+****************************************************************************//**
+*
+* Reports the enabled/disabled atate of the selected divider.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t.
+*
+* \param dividerNum specifies which divider of the selected type to configure.
+*
+* \return The enabled/disabled state; \n
+* false = disabled \n
+* true = enabled
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphGetDividerEnabled
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_PeriphGetDividerEnabled(cy_en_divider_types_t dividerType, uint32_t dividerNum)
+{
+ bool retVal = false;
+
+ CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR)));
+
+ switch(dividerType)
+ {
+ case CY_SYSCLK_DIV_8_BIT:
+ retVal = _FLD2BOOL(PERI_DIV_8_CTL_EN, PERI_DIV_8_CTL[dividerNum]);
+ break;
+ case CY_SYSCLK_DIV_16_BIT:
+ retVal = _FLD2BOOL(PERI_DIV_16_CTL_EN, PERI_DIV_16_CTL[dividerNum]);
+ break;
+ case CY_SYSCLK_DIV_16_5_BIT:
+ retVal = _FLD2BOOL(PERI_DIV_16_5_CTL_EN, PERI_DIV_16_5_CTL[dividerNum]);
+ break;
+ case CY_SYSCLK_DIV_24_5_BIT:
+ retVal = _FLD2BOOL(PERI_DIV_24_5_CTL_EN, PERI_DIV_24_5_CTL[dividerNum]);
+ break;
+ default:
+ break;
+ }
+ return (retVal);
+}
+/** \} group_sysclk_clk_peripheral_funcs */
+
+
+/* ========================================================================== */
+/* ========================= clk_slow SECTION ========================= */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_slow_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkSlowSetDivider(uint8_t divider);
+__STATIC_INLINE uint8_t Cy_SysClk_ClkSlowGetDivider(void);
+__STATIC_INLINE uint32_t Cy_SysClk_ClkSlowGetFrequency(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkSlowGetFrequency
+****************************************************************************//**
+*
+* Reports the frequency of the slow clock.
+*
+* \return The frequency, in Hz.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysClk_ClkSlowGetFrequency(void)
+{
+ uint32_t locFreq = Cy_SysClk_ClkPeriGetFrequency(); /* Get Peri frequency */
+ uint32_t locDiv = 1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider(); /* peri prescaler (1-256) */
+
+ /* Divide the path input frequency down and return the result */
+ return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkSlowSetDivider
+****************************************************************************//**
+*
+* Sets the clock divider for the slow clock. The source of this clock is the
+* peripheral clock (clkPeri), which is sourced from clkHf[0].
+*
+* \param divider Divider value between 0 and 255.
+* Causes integer division of (divider value + 1), or division by 1 to 256.
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkSlowSetDivider(uint8_t divider)
+{
+ CY_REG32_CLR_SET(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, divider);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkSlowGetDivider
+****************************************************************************//**
+*
+* Reports the divider value for the slow clock.
+*
+* \return The divider value.
+* The integer division done is by (divider value + 1), or division by 1 to 256.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_SysClk_ClkSlowGetDivider(void)
+{
+ return ((uint8_t)_FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS_CM0_CLOCK_CTL));
+}
+/** \} group_sysclk_clk_slow_funcs */
+
+
+/* ========================================================================== */
+/* =========================== clkLf SECTION ========================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_lf_enums
+* \{
+*/
+/**
+* Low frequency (clkLf) input sources. See CLK_SELECT register, LFCLK_SEL bits.
+* Used with functions \ref Cy_SysClk_ClkLfSetSource, and \ref Cy_SysClk_ClkLfGetSource.
+*/
+typedef enum
+{
+ CY_SYSCLK_CLKLF_IN_ILO = 0U, /**< clkLf is sourced by the internal low speed oscillator (ILO) */
+ CY_SYSCLK_CLKLF_IN_WCO = 1U, /**< clkLf is sourced by the watch crystal oscillator (WCO) */
+ CY_SYSCLK_CLKLF_IN_ALTLF = 2U, /**< clkLf is sourced by the Alternate Low Frequency Clock (ALTLF) */
+ CY_SYSCLK_CLKLF_IN_PILO = 3U /**< clkLf is sourced by the precision low speed oscillator (PILO) */
+} cy_en_clklf_in_sources_t;
+/** \} group_sysclk_clk_lf_enums */
+
+/**
+* \addtogroup group_sysclk_clk_lf_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source);
+__STATIC_INLINE cy_en_clklf_in_sources_t Cy_SysClk_ClkLfGetSource(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkLfSetSource
+****************************************************************************//**
+*
+* Sets the source for the low frequency clock(clkLf).
+*
+* \param source \ref cy_en_clklf_in_sources_t
+*
+* \note The watchdog timer (WDT) must be unlocked before calling this function.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source)
+{
+ CY_ASSERT_L3(source <= CY_SYSCLK_CLKLF_IN_PILO);
+ CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_LFCLK_SEL, source);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkLfGetSource
+****************************************************************************//**
+*
+* Reports the source for the low frequency clock (clkLf).
+*
+* \return \ref cy_en_clklf_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clklf_in_sources_t Cy_SysClk_ClkLfGetSource(void)
+{
+ return ((cy_en_clklf_in_sources_t)(_FLD2VAL(SRSS_CLK_SELECT_LFCLK_SEL, SRSS_CLK_SELECT)));
+}
+/** \} group_sysclk_clk_lf_funcs */
+
+
+/* ========================================================================== */
+/* ======================== clk_timer SECTION ========================= */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_timer_enums
+* \{
+*/
+/**
+* Timer clock (clk_timer) input sources. See CLK_TIMER_CTL register, TIMER_SEL
+* and TIMER_HF0_DIV bits. Used with functions \ref Cy_SysClk_ClkTimerSetSource, and
+* \ref Cy_SysClk_ClkTimerGetSource.
+*/
+typedef enum
+{
+ CY_SYSCLK_CLKTIMER_IN_IMO = 0x000U, /**< clk_timer is sourced by the internal main oscillator (IMO) */
+ CY_SYSCLK_CLKTIMER_IN_HF0_NODIV = 0x001U, /**< clk_timer is sourced by clkHf[0] undivided */
+ CY_SYSCLK_CLKTIMER_IN_HF0_DIV2 = 0x101U, /**< clk_timer is sourced by clkHf[0] divided by 2 */
+ CY_SYSCLK_CLKTIMER_IN_HF0_DIV4 = 0x201U, /**< clk_timer is sourced by clkHf[0] divided by 4 */
+ CY_SYSCLK_CLKTIMER_IN_HF0_DIV8 = 0x301U /**< clk_timer is sourced by clkHf[0] divided by 8 */
+} cy_en_clktimer_in_sources_t;
+/** \} group_sysclk_clk_timer_enums */
+
+/** \cond */
+#define CY_SRSS_CLK_TIMER_CTL_TIMER_Pos (SRSS_CLK_TIMER_CTL_TIMER_SEL_Pos)
+#define CY_SRSS_CLK_TIMER_CTL_TIMER_Msk (SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk | SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk)
+/** \endcond */
+
+/**
+* \addtogroup group_sysclk_clk_timer_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_in_sources_t source);
+__STATIC_INLINE cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void);
+__STATIC_INLINE void Cy_SysClk_ClkTimerSetDivider(uint8_t divider);
+__STATIC_INLINE uint8_t Cy_SysClk_ClkTimerGetDivider(void);
+__STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void);
+__STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkTimerSetSource
+****************************************************************************//**
+*
+* Sets the source for the timer clock (clk_timer). The timer clock can be used
+* as a source for SYSTICK as an alternate clock and one or more of the energy
+* profiler counters.
+*
+* \param source \ref cy_en_clktimer_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_in_sources_t source)
+{
+ CY_ASSERT_L3(source <= CY_SYSCLK_CLKTIMER_IN_HF0_DIV8);
+ /* set both fields TIMER_SEL and TIMER_HF0_DIV with the same input value */
+ CY_REG32_CLR_SET(SRSS_CLK_TIMER_CTL, CY_SRSS_CLK_TIMER_CTL_TIMER, source);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkTimerGetSource
+****************************************************************************//**
+*
+* Reports the source for the timer clock (clk_timer).
+*
+* \return \ref cy_en_clktimer_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void)
+{
+ /* return both fields TIMER_SEL and TIMER_HF0_DIV as a single combined value */
+ return ((cy_en_clktimer_in_sources_t)(SRSS_CLK_TIMER_CTL & CY_SRSS_CLK_TIMER_CTL_TIMER_Msk));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkTimerSetDivider
+****************************************************************************//**
+*
+* Sets the divider for the timer clock (clk_timer).
+*
+* \param divider Divider value; valid range is 0 to 255. Divides the selected
+* source (\ref Cy_SysClk_ClkTimerSetSource) by the (value + 1).
+*
+* \note
+* Do not change the divider value while the timer clock is enabled.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkTimerSetDivider(uint8_t divider)
+{
+ CY_REG32_CLR_SET(SRSS_CLK_TIMER_CTL, SRSS_CLK_TIMER_CTL_TIMER_DIV, divider);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkTimerGetDivider
+****************************************************************************//**
+*
+* Reports the divider value for the timer clock (clk_timer).
+*
+* \return The divider value
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_SysClk_ClkTimerGetDivider(void)
+{
+ return ((uint8_t)_FLD2VAL(SRSS_CLK_TIMER_CTL_TIMER_DIV, SRSS_CLK_TIMER_CTL));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkTimerEnable
+****************************************************************************//**
+*
+* Enables the timer clock (clk_timer). The timer clock can be used as a source
+* for SYSTICK and one or more of the energy profiler counters.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void)
+{
+ SRSS_CLK_TIMER_CTL |= SRSS_CLK_TIMER_CTL_ENABLE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkTimerDisable
+****************************************************************************//**
+*
+* Disables the timer clock (clk_timer).
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void)
+{
+ SRSS_CLK_TIMER_CTL &= ~SRSS_CLK_TIMER_CTL_ENABLE_Msk;
+}
+/** \} group_sysclk_clk_timer_funcs */
+
+
+/* ========================================================================== */
+/* ========================= clk_pump SECTION ========================= */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_pump_enums
+* \{
+*/
+/**
+* Pump clock (clk_pump) input sources. See CLK_SELECT register, PUMP_SEL bits.
+* Used with functions \ref Cy_SysClk_ClkPumpSetSource, and
+* \ref Cy_SysClk_ClkPumpGetSource.
+*/
+typedef enum
+{
+ CY_SYSCLK_PUMP_IN_CLKPATH0, /**< Pump clock input is clock path 0 */
+ CY_SYSCLK_PUMP_IN_CLKPATH1, /**< Pump clock input is clock path 1 */
+ CY_SYSCLK_PUMP_IN_CLKPATH2, /**< Pump clock input is clock path 2 */
+ CY_SYSCLK_PUMP_IN_CLKPATH3, /**< Pump clock input is clock path 3 */
+ CY_SYSCLK_PUMP_IN_CLKPATH4, /**< Pump clock input is clock path 4 */
+ CY_SYSCLK_PUMP_IN_CLKPATH5, /**< Pump clock input is clock path 5 */
+ CY_SYSCLK_PUMP_IN_CLKPATH6, /**< Pump clock input is clock path 6 */
+ CY_SYSCLK_PUMP_IN_CLKPATH7, /**< Pump clock input is clock path 7 */
+ CY_SYSCLK_PUMP_IN_CLKPATH8, /**< Pump clock input is clock path 8 */
+ CY_SYSCLK_PUMP_IN_CLKPATH9, /**< Pump clock input is clock path 9 */
+ CY_SYSCLK_PUMP_IN_CLKPATH10, /**< Pump clock input is clock path 10 */
+ CY_SYSCLK_PUMP_IN_CLKPATH11, /**< Pump clock input is clock path 11 */
+ CY_SYSCLK_PUMP_IN_CLKPATH12, /**< Pump clock input is clock path 12 */
+ CY_SYSCLK_PUMP_IN_CLKPATH13, /**< Pump clock input is clock path 13 */
+ CY_SYSCLK_PUMP_IN_CLKPATH14, /**< Pump clock input is clock path 14 */
+ CY_SYSCLK_PUMP_IN_CLKPATH15 /**< Pump clock input is clock path 15 */
+} cy_en_clkpump_in_sources_t;
+
+
+/**
+* Pump clock (clk_pump) divide options. See CLK_SELECT register, PUMP_DIV bits.
+* Used with functions \ref Cy_SysClk_ClkPumpSetDivider, and
+* \ref Cy_SysClk_ClkPumpGetDivider.
+*/
+typedef enum
+{
+ CY_SYSCLK_PUMP_NO_DIV = 0U, /**< No division on pump clock */
+ CY_SYSCLK_PUMP_DIV_2 = 1U, /**< Pump clock divided by 2 */
+ CY_SYSCLK_PUMP_DIV_4 = 2U, /**< Pump clock divided by 4 */
+ CY_SYSCLK_PUMP_DIV_8 = 3U, /**< Pump clock divided by 8 */
+ CY_SYSCLK_PUMP_DIV_16 = 4U /**< Pump clock divided by 16 */
+} cy_en_clkpump_divide_t;
+/** \} group_sysclk_clk_pump_enums */
+
+/** \cond */
+#define CY_SYSCLK_FLL_IS_DIVIDER_VALID(div) (((div) == CY_SYSCLK_PUMP_NO_DIV) || \
+ ((div) == CY_SYSCLK_PUMP_DIV_2) || \
+ ((div) == CY_SYSCLK_PUMP_DIV_4) || \
+ ((div) == CY_SYSCLK_PUMP_DIV_8) || \
+ ((div) == CY_SYSCLK_PUMP_DIV_16))
+/** \endcond */
+
+/**
+* \addtogroup group_sysclk_clk_pump_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_in_sources_t source);
+__STATIC_INLINE cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void);
+__STATIC_INLINE void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider);
+__STATIC_INLINE cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void);
+__STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void);
+__STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPumpSetSource
+****************************************************************************//**
+*
+* Sets the source for the pump clock (clk_pump). The pump clock can be used for
+* the analog pumps in the CTBm block.
+*
+* \param source \ref cy_en_clkpump_in_sources_t
+*
+* \note
+* Do not change the source while the pump clock is enabled.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_in_sources_t source)
+{
+ CY_ASSERT_L3(source <= CY_SYSCLK_PUMP_IN_CLKPATH15);
+ CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_PUMP_SEL, source);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPumpGetSource
+****************************************************************************//**
+*
+* Reports the source for the pump clock (clk_pump).
+*
+* \return \ref cy_en_clkpump_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void)
+{
+ return ((cy_en_clkpump_in_sources_t)_FLD2VAL(SRSS_CLK_SELECT_PUMP_SEL, SRSS_CLK_SELECT));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPumpSetDivider
+****************************************************************************//**
+*
+* Sets the divider of the pump clock (clk_pump).
+*
+* \param divider \ref cy_en_clkpump_divide_t
+*
+* \note
+* Do not change the divider value while the pump clock is enabled.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider)
+{
+ CY_ASSERT_L3(CY_SYSCLK_FLL_IS_DIVIDER_VALID(divider));
+ CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_PUMP_DIV, divider);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPumpGetDivider
+****************************************************************************//**
+*
+* Reports the divider value for the pump clock (clk_pump).
+*
+* \return \ref cy_en_clkpump_divide_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void)
+{
+ return ((cy_en_clkpump_divide_t)_FLD2VAL(SRSS_CLK_SELECT_PUMP_DIV, SRSS_CLK_SELECT));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPumpEnable
+****************************************************************************//**
+*
+* Enables the pump clock (clk_pump). The pump clock can be used for the analog
+* pumps in the CTBm block.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void)
+{
+ SRSS_CLK_SELECT |= SRSS_CLK_SELECT_PUMP_ENABLE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPumpDisable
+****************************************************************************//**
+*
+* Disables the pump clock (clk_pump).
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void)
+{
+ SRSS_CLK_SELECT &= ~SRSS_CLK_SELECT_PUMP_ENABLE_Msk;
+}
+/** \} group_sysclk_clk_pump_funcs */
+
+
+/* ========================================================================== */
+/* ========================== clk_bak SECTION ========================= */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_bak_enums
+* \{
+*/
+/**
+* Backup domain clock (clk_bak) input sources. See BACKUP->CTL register,
+* CLK_SEL bits. Used with functions \ref Cy_SysClk_ClkBakSetSource, and
+* \ref Cy_SysClk_ClkBakGetSource.
+*/
+typedef enum
+{
+ CY_SYSCLK_BAK_IN_WCO, /**< Backup domain clock input is WCO */
+ CY_SYSCLK_BAK_IN_CLKLF /**< Backup domain clock input is clkLf */
+} cy_en_clkbak_in_sources_t;
+/** \} group_sysclk_clk_bak_enums */
+
+
+/**
+* \addtogroup group_sysclk_clk_bak_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_in_sources_t source);
+__STATIC_INLINE cy_en_clkbak_in_sources_t Cy_SysClk_ClkBakGetSource(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkBakSetSource
+****************************************************************************//**
+*
+* Sets the source for the backup domain clock (clk_bak).
+*
+* \param source \ref cy_en_clkbak_in_sources_t
+*
+* \note
+* clkLf is not available in all power modes. For this reason, WCO is the
+* preferred source. If the WCO is routed through the clkLf multiplexer
+* (see \ref Cy_SysClk_ClkLfSetSource), select WCO directly - do not select clkLf.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkBakSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_in_sources_t source)
+{
+ CY_ASSERT_L3(source <= CY_SYSCLK_BAK_IN_CLKLF);
+ CY_REG32_CLR_SET(BACKUP_CTL, BACKUP_CTL_CLK_SEL, source);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkBakGetSource
+****************************************************************************//**
+*
+* Reports the source for the backup domain clock (clk_bak).
+*
+* \return \ref cy_en_clkbak_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkBakSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clkbak_in_sources_t Cy_SysClk_ClkBakGetSource(void)
+{
+ return ((cy_en_clkbak_in_sources_t)_FLD2VAL(BACKUP_CTL_CLK_SEL, BACKUP_CTL));
+}
+/** \} group_sysclk_clk_bak_funcs */
+
+
+/** \cond */
+/* Deprecated macros */
+#define CY_SYSCLK_DIV_ROUND(a, b) (CY_SYSLIB_DIV_ROUND((a),(b)))
+#define CY_SYSCLK_DIV_ROUNDUP(a, b) (CY_SYSLIB_DIV_ROUNDUP((a),(b)))
+/** \endcond */
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* CY_SYSCLK_H */
+
+/** \} group_sysclk */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_sysint.h b/platform/ext/target/psoc64/Native_Driver/include/cy_sysint.h
new file mode 100644
index 0000000000..ba6977eae7
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_sysint.h
@@ -0,0 +1,594 @@
+/***************************************************************************//**
+* \file cy_sysint.h
+* \version 1.30
+*
+* \brief
+* Provides an API declaration of the SysInt driver
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_sysint
+* \{
+* The SysInt driver provides an API to configure the device peripheral interrupts.
+* It provides a lightweight interface to complement
+* the <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html">CMSIS core NVIC API</a>.
+* The provided functions are applicable for all cores in a device and they can
+* be used to configure and connect device peripheral interrupts to one or more
+* cores.
+*
+* The functions and other declarations used in this driver are in cy_sysint.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions
+* and declarations in the PDL.
+*
+* \section group_sysint_vector_table Vector Table
+* The vector table defines the entry addresses of the processor exceptions and
+* the device specific interrupts. It is located at the start address of the flash
+* and is copied by the startup code to RAM. The symbol code __Vectors is the
+* address of the vector table in the startup code and the register SCB->VTOR
+* holds the start address of the vector table. See \ref group_system_config_device_vector_table
+* section for the implementation details.
+*
+* The default interrupt handler functions are defined as weak functions to a dummy handler
+* in the startup file. The naming convention is \<interrupt_name\>_IRQHandler.
+* Defining these in the user application allows the linker to place them in
+* the vector table in flash. For example:
+* \code
+* void ioss_interrupts_gpio_0_IRQHandler(void)
+* {
+* ...
+* }
+* \endcode
+* And can be used like this:
+* \snippet sysint/snippet/main.c snippet_Cy_SysInt_flashVT
+* Using this method avoids the need for a RAM vector table. However in this scenario,
+* interrupt handler re-location at run-time is not possible, unless the vector table is
+* relocated to RAM.
+
+* \section group_sysint_driver_usage Driver Usage
+*
+* \subsection group_sysint_initialization Initialization
+*
+* Interrupt numbers are defined in a device-specific header file, such as
+* cy8c68237bz_ble.h, and are consistent with interrupt handlers defined in the
+* vector table.
+*
+* To configure an interrupt, call Cy_SysInt_Init(). Populate
+* the configuration structure (cy_stc_sysint_t) and pass it as a parameter
+* along with the ISR address. This initializes the interrupt and
+* instructs the CPU to jump to the specified ISR vector upon a valid trigger.
+* For CM0+ core, the configuration structure (cy_stc_sysint_t)
+* must specify the device interrupt source (cm0pSrc) that feeds into the CM0+ NVIC
+* mux (intrSrc).
+*
+* For CM4 core, system interrupt source 'n' is connected to the
+* corresponding IRQn. Deep-sleep capable interrupts are allocated to Deep Sleep
+* capable IRQn channels.
+*
+* For CM0+ core, deep Sleep wakeup-capability is determined by the CPUSS_CM0_DPSLP_IRQ_NR
+* parameter, where the first N number of muxes (NvicMux0 ... NvicMuxN-1) have the
+* capability to trigger Deep Sleep interrupts. A Deep Sleep capable interrupt source
+* must be connected to one of these muxes to be able to trigger in Deep Sleep.
+* Refer to the IRQn_Type definition in the device header.
+*
+* 1. For CPUSS_ver1 the CM0+ core supports up to 32 interrupt channels (IRQn 0-31). To allow all device
+* interrupts to be routable to the NVIC of this core, there is a 240:1 multiplexer
+* at each of the 32 NVIC channels.
+*
+* 2. For CPUSS_ver2 the CM0+ core supports up to 8 hardware interrupt channels (IRQn 0-7) and software-only
+* interrupt channels (IRQn 8-15). The device has up to 1023 interrupts that can be connected to any of the
+* hardware interrupt channels. In this structure, multiple interrupt sources can be connected
+* simultaneously to one NVIC channel. The application must then query the interrupt source on the
+* channel and service the active interrupt(s). The priority of these interrupts is determined by the
+* interrupt number as defined in the cy_en_intr_t enum, where the lower number denotes higher priority
+* over the higher number.
+*
+* \subsection group_sysint_enable Enable
+*
+* After initializing an interrupt, use the CMSIS Core
+* <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ()</a> function
+* to enable it. Given an initialization structure named config,
+* the function should be called as follows:
+* \code
+* NVIC_EnableIRQ(config.intrSrc)
+* \endcode
+*
+* \subsection group_sysint_service Writing an interrupt service routine
+*
+* Servicing interrupts in the Peripheral Drivers should follow a prescribed
+* recipe to ensure all interrupts are serviced and duplicate interrupts are not
+* received. Any peripheral-specific register that must be written to clear the
+* source of the interrupt should be written as soon as possible in the interrupt
+* service routine. However, note that due to buffering on the output bus to the
+* peripherals, the write clearing of the interrupt may be delayed. After performing
+* the normal interrupt service that should respond to the interrupting
+* condition, the interrupt register that was initially written to clear the
+* register should be read before returning from the interrupt service routine.
+* This read ensures that the initial write has been flushed out to the hardware.
+* Note, no additional processing should be performed based on the result of this
+* read, as this read is intended only to ensure the write operation is flushed.
+*
+* This final read may indicate a pending interrupt. What this means is that in
+* the interval between when the write actually happened at the peripheral and
+* when the read actually happened at the peripheral, an interrupting condition
+* occurred. This is ok and a return from the interrupt is still the correct
+* action. As soon as conditions warrant, meaning interrupts are enabled and
+* there are no higher priority interrupts pending, the interrupt will be
+* triggered again to service the additional condition.
+*
+* \section group_sysint_section_configuration_considerations Configuration Considerations
+*
+* Certain CM0+ <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">NVIC IRQn</a>
+* channels are reserved for system use:
+* <table class="doxtable">
+* <tr><th>NVIC channel (\ref IRQn_Type)</th><th>Interrupt source (\ref cy_en_intr_t)</th><th>Purpose</th></tr>
+* <tr><td>#0 (NvicMux0_IRQn)</td><td>IPC Interrupt #0 (cpuss_interrupts_ipc_0_IRQn)</td><td>System Calls to ROM</td></tr>
+* <tr><td>#1 (NvicMux1_IRQn)</td><td>IPC Interrupt #3 (cpuss_interrupts_ipc_3_IRQn)</td><td>System IPC pipe in the default startup</td></tr>
+* </table>
+*
+* \note For CPUSS_ver2, each NVIC channel can be shared between multiple interrupt sources.
+* However it is not recommended to share the application NVIC channel with the reserved channels.
+*
+* \section group_sysint_more_information More Information
+*
+* Refer to the technical reference manual (TRM) and the device datasheet.
+*
+* \section group_sysint_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>8.12</td>
+* <td>R</td>
+* <td>Array declared with unknown size.</td>
+* <td>
+* __Vectors and __ramVectors arrays can have the different size depend on the selected device.</td>
+* </tr>
+* </table>
+*
+* \section group_sysint_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.30</td>
+* <td>The Cy_SysInt_SetNmiSource is updated with Protection Context check for CM0+.</td>
+* <td>User experience enhancement.</td>
+* </tr>
+* <tr>
+* <td>1.20.1</td>
+* <td>The Vector Table section is extended with a code snippet.</td>
+* <td>Documentation enhancement.</td>
+* </tr>
+* <tr>
+* <td rowspan="3">1.20</td>
+* <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Added CPUSS_ver2 support to the following API functions:
+* - \ref Cy_SysInt_SetInterruptSource
+* - \ref Cy_SysInt_SetNmiSource
+* - \ref Cy_SysInt_GetNmiSource
+*
+* Added new API functions:
+* - \ref Cy_SysInt_DisconnectInterruptSource
+* - \ref Cy_SysInt_GetNvicConnection
+* - \ref Cy_SysInt_GetInterruptActive
+*
+* Deprecated following functions:
+* - Cy_SysInt_SetIntSource
+* - Cy_SysInt_GetIntSource
+* - Cy_SysInt_SetIntSourceNMI
+* - Cy_SysInt_GetIntSourceNMI
+* </td>
+* <td>New devices support.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>1.10</td>
+* <td>Cy_SysInt_GetState() function is redefined to call NVIC_GetEnableIRQ()</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_sysint_macros Macros
+* \defgroup group_sysint_globals Global variables
+* \defgroup group_sysint_functions Functions
+* \defgroup group_sysint_data_structures Data Structures
+* \defgroup group_sysint_enums Enumerated Types
+*/
+
+
+#if !defined(CY_SYSINT_H)
+#define CY_SYSINT_H
+
+#include <stddef.h>
+#include "cy_device.h"
+#include "cy_syslib.h"
+#include "cy_device_headers.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/***************************************
+* Global Variable
+***************************************/
+
+/**
+* \addtogroup group_sysint_globals
+* \{
+*/
+
+extern const cy_israddress __Vectors[]; /**< Vector table in flash */
+extern cy_israddress __ramVectors[]; /**< Relocated vector table in SRAM */
+
+/** \} group_sysint_globals */
+
+
+/***************************************
+* Global Interrupt
+***************************************/
+
+/**
+* \addtogroup group_sysint_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_SYSINT_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_SYSINT_DRV_VERSION_MINOR 30
+
+/** SysInt driver ID */
+#define CY_SYSINT_ID CY_PDL_DRV_ID (0x15U)
+
+/** \} group_sysint_macros */
+
+
+/***************************************
+* Enumeration
+***************************************/
+
+/**
+* \addtogroup group_sysint_enums
+* \{
+*/
+
+/**
+* SysInt Driver error codes
+*/
+typedef enum
+{
+ CY_SYSINT_SUCCESS = 0x0UL, /**< Returned successful */
+ CY_SYSINT_BAD_PARAM = CY_SYSINT_ID | CY_PDL_STATUS_ERROR | 0x1UL, /**< Bad parameter was passed */
+} cy_en_sysint_status_t;
+
+/** NMI connection input */
+typedef enum
+{
+ CY_SYSINT_NMI1 = 1UL, /**< NMI source input 1 */
+ CY_SYSINT_NMI2 = 2UL, /**< NMI source input 2 */
+ CY_SYSINT_NMI3 = 3UL, /**< NMI source input 3 */
+ CY_SYSINT_NMI4 = 4UL, /**< NMI source input 4 */
+} cy_en_sysint_nmi_t;
+
+/** \} group_sysint_enums */
+
+
+/***************************************
+* Configuration Structure
+***************************************/
+
+/**
+* \addtogroup group_sysint_data_structures
+* \{
+*/
+
+/**
+* Initialization configuration structure for a single interrupt channel
+*/
+typedef struct {
+ IRQn_Type intrSrc; /**< Interrupt source */
+#if (CY_CPU_CORTEX_M0P)
+ cy_en_intr_t cm0pSrc; /**< Maps cm0pSrc device interrupt to intrSrc */
+#endif
+ uint32_t intrPriority; /**< Interrupt priority number (Refer to __NVIC_PRIO_BITS) */
+} cy_stc_sysint_t;
+
+/** \} group_sysint_data_structures */
+
+
+/***************************************
+* Constants
+***************************************/
+
+/** \cond INTERNAL */
+
+ #define CY_INT_IRQ_BASE (16U) /**< Start location of interrupts in the vector table */
+ #define CY_SYSINT_STATE_MASK (1UL) /**< Mask for interrupt state */
+ #define CY_SYSINT_STIR_MASK (0xFFUL) /**< Mask for software trigger interrupt register */
+ #define CY_SYSINT_DISABLE (0UL) /**< Disable interrupt */
+ #define CY_SYSINT_ENABLE (1UL) /**< Enable interrupt */
+ #define CY_SYSINT_INT_STATUS_MSK (0x7UL)
+
+ /*(CY_IP_M4CPUSS_VERSION == 1u) */
+ #define CY_SYSINT_CM0P_MUX_MASK (0xFFUL) /**< CM0+ NVIC multiplexer mask */
+ #define CY_SYSINT_CM0P_MUX_SHIFT (2U) /**< CM0+ NVIC multiplexer shift */
+ #define CY_SYSINT_CM0P_MUX_SCALE (3U) /**< CM0+ NVIC multiplexer scaling value */
+ #define CY_SYSINT_CM0P_MUX0 (0U) /**< CM0+ NVIC multiplexer register 0 */
+ #define CY_SYSINT_CM0P_MUX1 (1U) /**< CM0+ NVIC multiplexer register 1 */
+ #define CY_SYSINT_CM0P_MUX2 (2U) /**< CM0+ NVIC multiplexer register 2 */
+ #define CY_SYSINT_CM0P_MUX3 (3U) /**< CM0+ NVIC multiplexer register 3 */
+ #define CY_SYSINT_CM0P_MUX4 (4U) /**< CM0+ NVIC multiplexer register 4 */
+ #define CY_SYSINT_CM0P_MUX5 (5U) /**< CM0+ NVIC multiplexer register 5 */
+ #define CY_SYSINT_CM0P_MUX6 (6U) /**< CM0+ NVIC multiplexer register 6 */
+ #define CY_SYSINT_CM0P_MUX7 (7U) /**< CM0+ NVIC multiplexer register 7 */
+ #define CY_SYSINT_MUX_REG_MSK (0x7UL)
+
+ /* Parameter validation macros */
+ #define CY_SYSINT_IS_PRIORITY_VALID(intrPriority) ((uint32_t)(1UL << __NVIC_PRIO_BITS) > (intrPriority))
+ #define CY_SYSINT_IS_VECTOR_VALID(userIsr) (NULL != (userIsr))
+ #define CY_SYSINT_IS_NMI_NUM_VALID(nmiNum) (((nmiNum) == CY_SYSINT_NMI1) || \
+ ((nmiNum) == CY_SYSINT_NMI2) || \
+ ((nmiNum) == CY_SYSINT_NMI3) || \
+ ((nmiNum) == CY_SYSINT_NMI4))
+ #define CY_SYSINT_IS_PC_0 (0UL == _FLD2VAL(PROT_MPU_MS_CTL_PC, PROT_MPU_MS_CTL(0U)))
+/** \endcond */
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_sysint_functions
+* \{
+*/
+
+cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr);
+cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr);
+cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn);
+
+#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
+ void Cy_SysInt_SetInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc);
+ cy_en_intr_t Cy_SysInt_GetInterruptSource(IRQn_Type IRQn);
+ IRQn_Type Cy_SysInt_GetNvicConnection(cy_en_intr_t devIntrSrc);
+ cy_en_intr_t Cy_SysInt_GetInterruptActive(IRQn_Type IRQn);
+ void Cy_SysInt_DisconnectInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc);
+#endif
+#if (!CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
+ __STATIC_INLINE void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, IRQn_Type intrSrc);
+ __STATIC_INLINE IRQn_Type Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum);
+#else
+ __STATIC_INLINE void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, cy_en_intr_t devIntrSrc);
+ __STATIC_INLINE cy_en_intr_t Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum);
+#endif
+#if (!CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
+ __STATIC_INLINE void Cy_SysInt_SoftwareTrig(IRQn_Type IRQn);
+#endif
+
+
+/***************************************
+* Functions
+***************************************/
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_SetNmiSource
+****************************************************************************//**
+*
+* \brief Sets the interrupt source of the CPU core NMI.
+*
+* The interrupt source must be a positive number. Setting the value to
+* "unconnected_IRQn" or "disconnected_IRQn" disconnects the interrupt source
+* from the NMI. Depending on the device, the number of interrupt sources that
+* can provide the NMI trigger signal to the core can vary.
+*
+* \param nmiNum
+* NMI source number.
+* CPUSS_ver2 allows up to 4 sources to trigger the core NMI.
+* CPUSS_ver1 allows only one source to trigger the core NMI and
+* the specified NMI number is ignored.
+*
+* \param intrSrc
+* Interrupt source. This parameter can either be of type cy_en_intr_t or IRQn_Type
+* based on the selected core.
+*
+* \note CM0+ may call this function only at PC=0, CM4 may set its NMI handler at any PC.
+* \note The CM0+ NMI is used for performing system calls that execute out of ROM.
+*
+* \funcusage
+* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetNmiSource
+*
+*******************************************************************************/
+#if (!CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
+__STATIC_INLINE void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, IRQn_Type intrSrc)
+#else
+__STATIC_INLINE void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, cy_en_intr_t devIntrSrc)
+#endif
+{
+ CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum));
+
+#if (CY_CPU_CORTEX_M0P)
+ CY_ASSERT_L1(CY_SYSINT_IS_PC_0);
+#endif
+
+ if (CY_CPUSS_V1)
+ {
+ nmiNum = CY_SYSINT_NMI1; /* For CPUSS_ver1 the NMI number is 1 */
+ }
+
+ #if (CY_CPU_CORTEX_M0P)
+ CPUSS_CM0_NMI_CTL((uint32_t)nmiNum - 1UL) = (uint32_t)devIntrSrc;
+ #else
+ CPUSS_CM4_NMI_CTL((uint32_t)nmiNum - 1UL) = (uint32_t)intrSrc;
+ #endif
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_GetIntSourceNMI
+****************************************************************************//**
+*
+* \brief Gets the interrupt source of the CPU core NMI for the given NMI source
+* number.
+*
+* \param nmiNum
+* NMI source number.
+* CPUSS_ver2 allows up to 4 sources to trigger the core NMI (i.e. #1, 2, 3, 4).
+* CPUSS_ver1 allows only 1 source to trigger the core NMI (i.e #1).
+*
+* \return
+* Interrupt Source. This parameter can either be of type cy_en_intr_t or IRQn_Type
+* based on the selected core.
+*
+* \funcusage
+* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetNmiSource
+*
+*******************************************************************************/
+#if (!CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
+__STATIC_INLINE IRQn_Type Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum)
+#else
+__STATIC_INLINE cy_en_intr_t Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum)
+#endif
+{
+ CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum));
+
+ if (CY_CPUSS_V1)
+ {
+ nmiNum = CY_SYSINT_NMI1; /* For CPUSS_ver1 the NMI number is 1 */
+ }
+
+ #if (CY_CPU_CORTEX_M0P)
+ return ((cy_en_intr_t)(CPUSS_CM0_NMI_CTL((uint32_t)nmiNum - 1UL)));
+ #else
+ return ((IRQn_Type)(CPUSS_CM4_NMI_CTL((uint32_t)nmiNum - 1UL)));
+ #endif
+}
+
+
+#if (!CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_SoftwareTrig
+****************************************************************************//**
+*
+* \brief Triggers an interrupt using software (Not applicable for CM0+).
+*
+* \param IRQn
+* Interrupt source
+*
+* \funcusage
+* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SoftwareTrig
+*
+* \note Only privileged software can enable unprivileged access to the
+* Software Trigger Interrupt Register (STIR).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysInt_SoftwareTrig(IRQn_Type IRQn)
+{
+ NVIC->STIR = (uint32_t)IRQn & CY_SYSINT_STIR_MASK;
+}
+
+#endif
+
+/** \} group_sysint_functions */
+
+/** \cond INTERNAL */
+
+/***************************************
+* Deprecated functions
+***************************************/
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_GetState
+****************************************************************************//**
+*
+* This function is deprecated. It invokes the NVIC_GetEnableIRQ() function.
+*
+*******************************************************************************/
+#define Cy_SysInt_GetState NVIC_GetEnableIRQ
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_SetIntSource
+****************************************************************************//**
+*
+* This function is deprecated. It invokes the Cy_SysInt_SetInterruptSource() function.
+*
+*******************************************************************************/
+#define Cy_SysInt_SetIntSource(intrSrc, devIntrSrc) Cy_SysInt_SetInterruptSource(intrSrc, devIntrSrc)
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_GetIntSource
+****************************************************************************//**
+*
+* This function is deprecated. It invokes the Cy_SysInt_GetInterruptSource() function.
+*
+*******************************************************************************/
+#define Cy_SysInt_GetIntSource(intrSrc) Cy_SysInt_GetInterruptSource(intrSrc)
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_SetIntSourceNMI
+****************************************************************************//**
+*
+* This function is deprecated. It invokes the Cy_SysInt_SetNmiSource() function.
+*
+*******************************************************************************/
+#define Cy_SysInt_SetIntSourceNMI(srcParam) Cy_SysInt_SetNmiSource(CY_SYSINT_NMI1, srcParam)
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_GetIntSourceNMI
+****************************************************************************//**
+*
+* This function is deprecated. It invokes the Cy_SysInt_GetNmiSource() function.
+*
+*******************************************************************************/
+#define Cy_SysInt_GetIntSourceNMI() Cy_SysInt_GetNmiSource(CY_SYSINT_NMI1)
+
+/** \endcond */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_SYSINT_H */
+
+/** \} group_sysint */
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_syslib.h b/platform/ext/target/psoc64/Native_Driver/include/cy_syslib.h
new file mode 100644
index 0000000000..36f93ddc0a
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_syslib.h
@@ -0,0 +1,1165 @@
+/***************************************************************************//**
+* \file cy_syslib.h
+* \version 2.40.1
+*
+* Provides an API declaration of the SysLib driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_syslib
+* \{
+* The system libraries provide APIs that can be called in the user application
+* to handle the timing, logical checking or register.
+*
+* The functions and other declarations used in this driver are in cy_syslib.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions
+* and declarations in the PDL.
+*
+* The SysLib driver contains a set of different system functions. These functions
+* can be called in the application routine. Major features of the system library:
+* * Delay functions
+* * The register Read/Write macro
+* * Assert and Halt
+* * Assert Classes and Levels
+* * A software reset
+* * Reading the reset cause
+* * An API to invalidate the flash cache and buffer
+* * Data manipulation macro
+* * A variable type definition from MISRA-C which specifies signedness
+* * Cross compiler compatible attributes
+* * Getting a silicon-unique ID API
+* * Setting wait states API
+* * Resetting the backup domain API
+* * APIs to serve Fault handler
+*
+* \section group_syslib_configuration Configuration Considerations
+* <b> Assertion Usage </b> <br />
+* Use the CY_ASSERT() macro to check expressions that must be true as long as the
+* program is running correctly. It is a convenient way to insert sanity checks.
+* The CY_ASSERT() macro is defined in the cy_syslib.h file which is part of
+* the PDL library. The behavior of the macro is as follows: if the expression
+* passed to the macro is false, output an error message that includes the file
+* name and line number, and then halts the CPU. \n
+* In case of fault, the CY_ASSERT() macro calls the Cy_SysLib_AssertFailed() function.
+* This is a weakly linked function. The default implementation stores the file
+* name and line number of the ASSERT into global variables, cy_assertFileName
+* and cy_assertLine . It then calls the Cy_SysLib_Halt() function.
+* \note Firmware can redefine the Cy_SysLib_AssertFailed() function for custom processing.
+*
+* The PDL source code uses this assert mechanism extensively. It is recommended
+* that you enable asserts when debugging firmware. \n
+* <b> Assertion Classes and Levels </b> <br />
+* The PDL defines three assert classes, which correspond to different kinds
+* of parameters. There is a corresponding assert "level" for each class.
+* <table class="doxtable">
+* <tr><th>Class Macro</th><th>Level Macro</th><th>Type of check</th></tr>
+* <tr>
+* <td>CY_ASSERT_CLASS_1</td>
+* <td>CY_ASSERT_L1</td>
+* <td>A parameter that could change between different PSoC devices
+* (e.g. the number of clock paths)</td>
+* </tr>
+* <tr>
+* <td>CY_ASSERT_CLASS_2</td>
+* <td>CY_ASSERT_L2</td>
+* <td>A parameter that has fixed limits such as a counter period</td>
+* </tr>
+* <tr>
+* <td>CY_ASSERT_CLASS_3</td>
+* <td>CY_ASSERT_L3</td>
+* <td>A parameter that is an enum constant</td>
+* </tr>
+* </table>
+* Firmware defines which ASSERT class is enabled by defining CY_ASSERT_LEVEL.
+* This is a compiler command line argument, similar to how the DEBUG / NDEBUG
+* macro is passed. \n
+* Enabling any class also enables any lower-numbered class.
+* CY_ASSERT_CLASS_3 is the default level, and it enables asserts for all three
+* classes. The following example shows the command-line option to enable all
+* the assert levels:
+* \code -D CY_ASSERT_LEVEL=CY_ASSERT_CLASS_3 \endcode
+* \note The use of special characters, such as spaces, parenthesis, etc. must
+* be protected with quotes.
+*
+* After CY_ASSERT_LEVEL is defined, firmware can use
+* one of the three level macros to make an assertion. For example, if the
+* parameter can vary between devices, firmware uses the L1 macro.
+* \code CY_ASSERT_L1(clkPath < SRSS_NUM_CLKPATH); \endcode
+* If the parameter has bounds, firmware uses L2.
+* \code CY_ASSERT_L2(trim <= CY_CTB_TRIM_VALUE_MAX); \endcode
+* If the parameter is an enum, firmware uses L3.
+* \code CY_ASSERT_L3(config->LossAction <= CY_SYSCLK_CSV_ERROR_FAULT_RESET); \endcode
+* Each check uses the appropriate level macro for the kind of parameter being checked.
+* If a particular assert class/level is not enabled, then the assert does nothing.
+*
+* \section group_syslib_more_information More Information
+* Refer to the technical reference manual (TRM).
+*
+* \section group_syslib_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>1.2</td>
+* <td>R</td>
+* <td>No reliance shall be placed on undefined or unspecified behaviour.</td>
+* <td>This specific behavior is explicitly covered in rule 20.1.</td>
+* </tr>
+* <tr>
+* <td>2.1</td>
+* <td>R</td>
+* <td>This function contains a mixture of in-line assembler statements and C statements.</td>
+* <td>This si required by design of the Cy_SysLib_Halt function.</td>
+* </tr>
+* <tr>
+* <td>18.4</td>
+* <td>R</td>
+* <td>Unions shall not be used.</td>
+* <td>The unions are used for CFSR, HFSR and SHCSR Fault Status Registers
+* content access as a word in code and as a structure during debug.</td>
+* </tr>
+* <tr>
+* <td>19.13</td>
+* <td>A</td>
+* <td>The # and ## operators should not be used.</td>
+* <td>The ## preprocessor operator is used in macros to form the field mask.</td>
+* </tr>
+* <tr>
+* <td>20.1</td>
+* <td>R</td>
+* <td>Reserved identifiers, macros and functions in the standard library, shall not be
+* defined, redefined or undefined.</td>
+* <td>The driver defines the macros with leading underscores
+* (_CLR_SET_FLD/_BOOL2FLD/_FLD2BOOL) and therefore generates this MISRA violation.</td>
+* </tr>
+* </table>
+*
+* \section group_syslib_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.40.1</td>
+* <td>Correct the CY_RAMFUNC_BEGIN macro for the IAR compiler.</td>
+* <td>Removed the IAR compiler warning.</td>
+* </tr>
+* <tr>
+* <td>2.40</td>
+* <td>Added new macros CY_SYSLIB_DIV_ROUND and CY_SYSLIB_DIV_ROUNDUP to easy perform integer division with rounding.</td>
+* <td>Improve PDL code base.</td>
+* </tr>
+* <tr>
+* <td rowspan="3">2.30</td>
+* <td>Updated implementation of the Cy_SysLib_AsmInfiniteLoop() function to be compatible with ARMC6.</td>
+* <td>Provided support for the ARM Compiler 6.</td>
+* </tr>
+* <tr>
+* <td>Minor documentation edits.</td>
+* <td>Documentation update and clarification.</td>
+* </tr>
+* <tr>
+* <td>Added new macros CY_RAMFUNC_BEGIN and CY_RAMFUNC_END for convenient placement function in RAM for all supported compilers.</td>
+* <td>Improve user experience.</td>
+* </tr>
+* <tr>
+* <td rowspan="2">2.20</td>
+* <td>Updated implementation of the \ref Cy_SysLib_AssertFailed() function to be available in Release and Debug modes.</td>
+* <td>Provided support for the PDL static library in Release mode.</td>
+* </tr>
+* <tr>
+* <td>Minor documentation edits.</td>
+* <td>Documentation update and clarification.</td>
+* </tr>
+* <tr>
+* <td rowspan="4">2.10</td>
+* <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Added the following macros: \ref CY_REG32_CLR_SET, \ref _CLR_SET_FLD16U, \ref CY_REG16_CLR_SET, \ref _CLR_SET_FLD8U, \ref CY_REG8_CLR_SET</td>
+* <td>Register access simplification.</td>
+* </tr>
+* <tr>
+* <td>Removed the Cy_SysLib_GetNumHfclkResetCause API function.</td>
+* <td>This feature is not supported by SRSS_ver1.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>2.0.1</td>
+* <td>Minor documentation edits</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td rowspan="4"> 2.0</td>
+* <td>
+* Added Cy_SysLib_ResetBackupDomain() API implementation. \n
+* Added CY_NOINLINE attribute implementation. \n
+* Added DIE_YEAR field to 64-bit unique ID return value of Cy_SysLib_GetUniqueId() API. \n
+* Added storing of SCB->HFSR, SCB->SHCSR registers and SCB->MMFAR, SCB->BFAR addresses to Fault Handler debug structure. \n
+* Optimized Cy_SysLib_SetWaitStates() API implementation.
+* </td>
+* <td>Improvements made based on usability feedback.</td>
+* </tr>
+* <tr>
+* <td>Added Assertion Classes and Levels.</td>
+* <td>For error checking, parameter validation and status returns in the PDL API.</td>
+* </tr>
+* <tr>
+* <td>Applied CY_NOINIT attribute to cy_assertFileName, cy_assertLine, and cy_faultFrame global variables.</td>
+* <td>To store debug information into a non-zero init area for future analysis.</td>
+* </tr>
+* <tr>
+* <td>Removed CY_WEAK attribute implementation.</td>
+* <td>CMSIS __WEAK attribute should be used instead.</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_syslib_macros Macros
+* \defgroup group_syslib_functions Functions
+* \defgroup group_syslib_data_structures Data Structures
+* \defgroup group_syslib_enumerated_types Enumerated Types
+*
+*/
+
+#if !defined(CY_SYSLIB_H)
+#define CY_SYSLIB_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "cy_device.h"
+#include "cy_device_headers.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* defined(__cplusplus) */
+
+#if defined( __ICCARM__ )
+ /* Suppress the warning for multiple volatile variables in an expression. */
+ /* This is common for driver's code and the usage is not order-dependent. */
+ #pragma diag_suppress=Pa082
+#endif /* defined( __ICCARM__ ) */
+
+/**
+* \addtogroup group_syslib_macros
+* \{
+*/
+
+/******************************************************************************
+* Macros
+*****************************************************************************/
+
+#define CY_CPU_CORTEX_M0P (__CORTEX_M == 0) /**< CM0+ core CPU Code */
+#define CY_CPU_CORTEX_M4 (__CORTEX_M == 4) /**< CM4 core CPU Code */
+
+/** The macro to disable the Fault Handler */
+#define CY_ARM_FAULT_DEBUG_DISABLED (0U)
+/** The macro to enable the Fault Handler */
+#define CY_ARM_FAULT_DEBUG_ENABLED (1U)
+
+#if !defined(CY_ARM_FAULT_DEBUG)
+ /** The macro defines if the Fault Handler is enabled. Enabled by default. */
+ #define CY_ARM_FAULT_DEBUG (CY_ARM_FAULT_DEBUG_ENABLED)
+#endif /* CY_ARM_FAULT_DEBUG */
+
+/**
+* \defgroup group_syslib_macros_status_codes Status codes
+* \{
+* Function status type codes
+*/
+#define CY_PDL_STATUS_CODE_Pos (0U) /**< The module status code position in the status code */
+#define CY_PDL_STATUS_TYPE_Pos (16U) /**< The status type position in the status code */
+#define CY_PDL_MODULE_ID_Pos (18U) /**< The software module ID position in the status code */
+#define CY_PDL_STATUS_INFO (0UL << CY_PDL_STATUS_TYPE_Pos) /**< The information status type */
+#define CY_PDL_STATUS_WARNING (1UL << CY_PDL_STATUS_TYPE_Pos) /**< The warning status type */
+#define CY_PDL_STATUS_ERROR (2UL << CY_PDL_STATUS_TYPE_Pos) /**< The error status type */
+#define CY_PDL_MODULE_ID_Msk (0x3FFFU) /**< The software module ID mask */
+/** Get the software PDL module ID */
+#define CY_PDL_DRV_ID(id) ((uint32_t)((uint32_t)((id) & CY_PDL_MODULE_ID_Msk) << CY_PDL_MODULE_ID_Pos))
+#define CY_SYSLIB_ID CY_PDL_DRV_ID(0x11U) /**< SYSLIB PDL ID */
+/** \} group_syslib_macros_status_codes */
+
+/** \} group_syslib_macros */
+
+/**
+* \addtogroup group_syslib_enumerated_types
+* \{
+*/
+
+/** The SysLib status code structure. */
+typedef enum
+{
+ CY_SYSLIB_SUCCESS = 0x00UL, /**< The success status code */
+ CY_SYSLIB_BAD_PARAM = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x01UL, /**< The bad parameter status code */
+ CY_SYSLIB_TIMEOUT = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x02UL, /**< The time out status code */
+ CY_SYSLIB_INVALID_STATE = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x03UL, /**< The invalid state status code */
+ CY_SYSLIB_UNKNOWN = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0xFFUL /**< Unknown status code */
+} cy_en_syslib_status_t;
+
+/** \} group_syslib_enumerated_types */
+/**
+* \addtogroup group_syslib_data_structures
+* \{
+*/
+
+#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
+ #if (CY_CPU_CORTEX_M4)
+ /** Configurable Fault Status Register - CFSR */
+ typedef struct
+ {
+ /** MemManage Fault Status Sub-register - MMFSR */
+ uint32_t iaccViol : 1; /**< MemManage Fault - The instruction access violation flag */
+ uint32_t daccViol : 1; /**< MemManage Fault - The data access violation flag */
+ uint32_t reserved1 : 1; /**< Reserved */
+ uint32_t mUnstkErr : 1; /**< MemManage Fault - Unstacking for a return from exception */
+ uint32_t mStkErr : 1; /**< MemManage Fault - MemManage fault on stacking for exception entry */
+ uint32_t mlspErr : 1; /**< MemManage Fault - MemManage fault occurred during floating-point lazy state preservation */
+ uint32_t reserved2 : 1; /**< Reserved */
+ uint32_t mmarValid : 1; /**< MemManage Fault - The MemManage Address register valid flag */
+ /** Bus Fault Status Sub-register - UFSR */
+ uint32_t iBusErr : 1; /**< Bus Fault - The instruction bus error */
+ uint32_t precisErr : 1; /**< Bus Fault - The precise Data bus error */
+ uint32_t imprecisErr : 1; /**< Bus Fault - The imprecise data bus error */
+ uint32_t unstkErr : 1; /**< Bus Fault - Unstacking for an exception return has caused one or more bus faults */
+ uint32_t stkErr : 1; /**< Bus Fault - Stacking for an exception entry has caused one or more bus faults */
+ uint32_t lspErr : 1; /**< Bus Fault - A bus fault occurred during the floating-point lazy state */
+ uint32_t reserved3 : 1; /**< Reserved */
+ uint32_t bfarValid : 1; /**< Bus Fault - The bus fault address register valid flag */
+ /** Usage Fault Status Sub-register - UFSR */
+ uint32_t undefInstr : 1; /**< Usage Fault - An undefined instruction */
+ uint32_t invState : 1; /**< Usage Fault - The invalid state */
+ uint32_t invPC : 1; /**< Usage Fault - An invalid PC */
+ uint32_t noCP : 1; /**< Usage Fault - No coprocessor */
+ uint32_t reserved4 : 4; /**< Reserved */
+ uint32_t unaligned : 1; /**< Usage Fault - Unaligned access */
+ uint32_t divByZero : 1; /**< Usage Fault - Divide by zero */
+ uint32_t reserved5 : 6; /**< Reserved */
+ } cy_stc_fault_cfsr_t;
+
+ /** Hard Fault Status Register - HFSR */
+ typedef struct
+ {
+ uint32_t reserved1 : 1; /**< Reserved. */
+ uint32_t vectTbl : 1; /**< HFSR - Indicates a bus fault on a vector table read during exception processing */
+ uint32_t reserved2 : 28; /**< Reserved. */
+ uint32_t forced : 1; /**< HFSR - Indicates a forced hard fault */
+ uint32_t debugEvt : 1; /**< HFSR - Reserved for the debug use. */
+ } cy_stc_fault_hfsr_t;
+
+ /** System Handler Control and State Register - SHCSR */
+ typedef struct
+ {
+ uint32_t memFaultAct : 1; /**< SHCSR - The MemManage exception active bit, reads as 1 if the exception is active */
+ uint32_t busFaultAct : 1; /**< SHCSR - The BusFault exception active bit, reads as 1 if the exception is active */
+ uint32_t reserved1 : 1; /**< Reserved. */
+ uint32_t usgFaultAct : 1; /**< SHCSR - The UsageFault exception active bit, reads as 1 if the exception is active */
+ uint32_t reserved2 : 3; /**< Reserved. */
+ uint32_t svCallAct : 1; /**< SHCSR - The SVCall active bit, reads as 1 if the SVC call is active */
+ uint32_t monitorAct : 1; /**< SHCSR - The debug monitor active bit, reads as 1 if the debug monitor is active */
+ uint32_t reserved3 : 1; /**< Reserved. */
+ uint32_t pendSVAct : 1; /**< SHCSR - The PendSV exception active bit, reads as 1 if the exception is active */
+ uint32_t sysTickAct : 1; /**< SHCSR - The SysTick exception active bit, reads as 1 if the exception is active */
+ uint32_t usgFaultPended : 1; /**< SHCSR - The UsageFault exception pending bit, reads as 1 if the exception is pending */
+ uint32_t memFaultPended : 1; /**< SHCSR - The MemManage exception pending bit, reads as 1 if the exception is pending */
+ uint32_t busFaultPended : 1; /**< SHCSR - The BusFault exception pending bit, reads as 1 if the exception is pending */
+ uint32_t svCallPended : 1; /**< SHCSR - The SVCall pending bit, reads as 1 if the exception is pending */
+ uint32_t memFaultEna : 1; /**< SHCSR - The MemManage enable bit, set to 1 to enable */
+ uint32_t busFaultEna : 1; /**< SHCSR - The BusFault enable bit, set to 1 to enable */
+ uint32_t usgFaultEna : 1; /**< SHCSR - The UsageFault enable bit, set to 1 to enable */
+ uint32_t reserved4 : 13; /**< Reserved */
+ } cy_stc_fault_shcsr_t;
+ #endif /* CY_CPU_CORTEX_M4 */
+
+ /** The fault configuration structure. */
+ typedef struct
+ {
+ uint32_t r0; /**< R0 register content */
+ uint32_t r1; /**< R1 register content */
+ uint32_t r2; /**< R2 register content */
+ uint32_t r3; /**< R3 register content */
+ uint32_t r12; /**< R12 register content */
+ uint32_t lr; /**< LR register content */
+ uint32_t pc; /**< PC register content */
+ uint32_t psr; /**< PSR register content */
+ #if (CY_CPU_CORTEX_M4)
+ union
+ {
+ uint32_t cfsrReg; /**< CFSR register content as a word */
+ cy_stc_fault_cfsr_t cfsrBits; /**< CFSR register content as a structure */
+ } cfsr;
+ union
+ {
+ uint32_t hfsrReg; /**< HFSR register content as a word */
+ cy_stc_fault_hfsr_t hfsrBits; /**< HFSR register content as a structure */
+ } hfsr;
+ union
+ {
+ uint32_t shcsrReg; /**< SHCSR register content as a word */
+ cy_stc_fault_shcsr_t shcsrBits; /**< SHCSR register content as a structure */
+ } shcsr;
+ uint32_t mmfar; /**< MMFAR register content */
+ uint32_t bfar; /**< BFAR register content */
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)))
+ uint32_t s0; /**< FPU S0 register content */
+ uint32_t s1; /**< FPU S1 register content */
+ uint32_t s2; /**< FPU S2 register content */
+ uint32_t s3; /**< FPU S3 register content */
+ uint32_t s4; /**< FPU S4 register content */
+ uint32_t s5; /**< FPU S5 register content */
+ uint32_t s6; /**< FPU S6 register content */
+ uint32_t s7; /**< FPU S7 register content */
+ uint32_t s8; /**< FPU S8 register content */
+ uint32_t s9; /**< FPU S9 register content */
+ uint32_t s10; /**< FPU S10 register content */
+ uint32_t s11; /**< FPU S11 register content */
+ uint32_t s12; /**< FPU S12 register content */
+ uint32_t s13; /**< FPU S13 register content */
+ uint32_t s14; /**< FPU S14 register content */
+ uint32_t s15; /**< FPU S15 register content */
+ uint32_t fpscr; /**< FPU FPSCR register content */
+ #endif /* __FPU_PRESENT */
+ #endif /* CY_CPU_CORTEX_M4 */
+ } cy_stc_fault_frame_t;
+#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
+
+/** \} group_syslib_data_structures */
+
+/**
+* \addtogroup group_syslib_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_SYSLIB_DRV_VERSION_MAJOR 2
+
+/** The driver minor version */
+#define CY_SYSLIB_DRV_VERSION_MINOR 40
+
+
+/*******************************************************************************
+* Data manipulation defines
+*******************************************************************************/
+
+/** Get the lower 8 bits of a 16-bit value. */
+#define CY_LO8(x) ((uint8_t) ((x) & 0xFFU))
+/** Get the upper 8 bits of a 16-bit value. */
+#define CY_HI8(x) ((uint8_t) ((uint16_t)(x) >> 8U))
+
+/** Get the lower 16 bits of a 32-bit value. */
+#define CY_LO16(x) ((uint16_t) ((x) & 0xFFFFU))
+/** Get the upper 16 bits of a 32-bit value. */
+#define CY_HI16(x) ((uint16_t) ((uint32_t)(x) >> 16U))
+
+/** Swap the byte ordering of a 16-bit value */
+#define CY_SWAP_ENDIAN16(x) ((uint16_t)(((x) << 8U) | (((x) >> 8U) & 0x00FFU)))
+
+/** Swap the byte ordering of a 32-bit value */
+#define CY_SWAP_ENDIAN32(x) ((uint32_t)((((x) >> 24U) & 0x000000FFU) | (((x) & 0x00FF0000U) >> 8U) | \
+ (((x) & 0x0000FF00U) << 8U) | ((x) << 24U)))
+
+/** Swap the byte ordering of a 64-bit value */
+#define CY_SWAP_ENDIAN64(x) ((uint64_t) (((uint64_t) CY_SWAP_ENDIAN32((uint32_t)(x)) << 32U) | \
+ CY_SWAP_ENDIAN32((uint32_t)((x) >> 32U))))
+
+
+/*******************************************************************************
+* Memory model definitions
+*******************************************************************************/
+#if defined(__ARMCC_VERSION)
+ /** To create cross compiler compatible code, use the CY_NOINIT, CY_SECTION, CY_UNUSED, CY_ALIGN
+ * attributes at the first place of declaration/definition.
+ * For example: CY_NOINIT uint32_t noinitVar;
+ */
+ #if (__ARMCC_VERSION >= 6010050)
+ #define CY_NOINIT __attribute__ ((section(".noinit")))
+ #else
+ #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init))
+ #endif /* (__ARMCC_VERSION >= 6010050) */
+ #define CY_SECTION(name) __attribute__ ((section(name)))
+ #define CY_UNUSED __attribute__ ((unused))
+ #define CY_NOINLINE __attribute__ ((noinline))
+ /* Specifies the minimum alignment (in bytes) for variables of the specified type. */
+ #define CY_ALIGN(align) __ALIGNED(align)
+ #define CY_RAMFUNC_BEGIN __attribute__ ((section(".ramfunc")))
+ #define CY_RAMFUNC_END
+#elif defined (__GNUC__)
+ #if defined (__clang__)
+ #define CY_NOINIT __attribute__ ((section("__DATA, __noinit")))
+ #define CY_SECTION(name) __attribute__ ((section("__DATA, "name)))
+ #define CY_RAMFUNC_BEGIN __attribute__ ((section("__DATA, .ramfunc")))
+ #define CY_RAMFUNC_END
+ #else
+ #define CY_NOINIT __attribute__ ((section(".noinit")))
+ #define CY_SECTION(name) __attribute__ ((section(name)))
+ #define CY_RAMFUNC_BEGIN __attribute__ ((section(".ramfunc")))
+ #define CY_RAMFUNC_END
+ #endif
+
+ #define CY_UNUSED __attribute__ ((unused))
+ #define CY_NOINLINE __attribute__ ((noinline))
+ #define CY_ALIGN(align) __ALIGNED(align)
+#elif defined (__ICCARM__)
+ #define CY_PRAGMA(x) _Pragma(#x)
+ #define CY_NOINIT __no_init
+ #define CY_SECTION(name) CY_PRAGMA(location = name)
+ #define CY_UNUSED
+ #define CY_NOINLINE CY_PRAGMA(optimize = no_inline)
+ #define CY_RAMFUNC_BEGIN CY_PRAGMA(diag_suppress = Ta023) __ramfunc
+ #define CY_RAMFUNC_END CY_PRAGMA(diag_default = Ta023)
+ #if (__VER__ < 8010001)
+ #define CY_ALIGN(align) CY_PRAGMA(data_alignment = align)
+ #else
+ #define CY_ALIGN(align) __ALIGNED(align)
+ #endif /* (__VER__ < 8010001) */
+#else
+ #error "An unsupported toolchain"
+#endif /* (__ARMCC_VERSION) */
+
+typedef void (* cy_israddress)(void); /**< Type of ISR callbacks */
+#if defined (__ICCARM__)
+ typedef union { cy_israddress __fun; void * __ptr; } cy_intvec_elem;
+#endif /* defined (__ICCARM__) */
+
+/* MISRA rule 6.3 recommends using specific-length typedef for the basic
+ * numerical types of signed and unsigned variants of char, float, and double.
+ */
+typedef char char_t; /**< Specific-length typedef for the basic numerical types of char */
+typedef float float32_t; /**< Specific-length typedef for the basic numerical types of float */
+typedef double float64_t; /**< Specific-length typedef for the basic numerical types of double */
+
+#if !defined(NDEBUG)
+ /** The max size of the file name which stores the ASSERT location */
+ #define CY_MAX_FILE_NAME_SIZE (24U)
+ extern CY_NOINIT char_t cy_assertFileName[CY_MAX_FILE_NAME_SIZE]; /**< The assert buffer */
+ extern CY_NOINIT uint32_t cy_assertLine; /**< The assert line value */
+#endif /* NDEBUG */
+
+#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
+ #define CY_R0_Pos (0U) /**< The position of the R0 content in a fault structure */
+ #define CY_R1_Pos (1U) /**< The position of the R1 content in a fault structure */
+ #define CY_R2_Pos (2U) /**< The position of the R2 content in a fault structure */
+ #define CY_R3_Pos (3U) /**< The position of the R3 content in a fault structure */
+ #define CY_R12_Pos (4U) /**< The position of the R12 content in a fault structure */
+ #define CY_LR_Pos (5U) /**< The position of the LR content in a fault structure */
+ #define CY_PC_Pos (6U) /**< The position of the PC content in a fault structure */
+ #define CY_PSR_Pos (7U) /**< The position of the PSR content in a fault structure */
+ #if (CY_CPU_CORTEX_M4) && ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)))
+ #define CY_FPSCR_IXC_Msk (0x00000010U) /**< The cumulative exception bit for floating-point exceptions */
+ #define CY_FPSCR_IDC_Msk (0x00000080U) /**< The cumulative exception bit for floating-point exceptions */
+ #define CY_S0_Pos (8U) /**< The position of the FPU S0 content in a fault structure */
+ #define CY_S1_Pos (9U) /**< The position of the FPU S1 content in a fault structure */
+ #define CY_S2_Pos (10U) /**< The position of the FPU S2 content in a fault structure */
+ #define CY_S3_Pos (11U) /**< The position of the FPU S3 content in a fault structure */
+ #define CY_S4_Pos (12U) /**< The position of the FPU S4 content in a fault structure */
+ #define CY_S5_Pos (13U) /**< The position of the FPU S5 content in a fault structure */
+ #define CY_S6_Pos (14U) /**< The position of the FPU S6 content in a fault structure */
+ #define CY_S7_Pos (15U) /**< The position of the FPU S7 content in a fault structure */
+ #define CY_S8_Pos (16U) /**< The position of the FPU S8 content in a fault structure */
+ #define CY_S9_Pos (17U) /**< The position of the FPU S9 content in a fault structure */
+ #define CY_S10_Pos (18U) /**< The position of the FPU S10 content in a fault structure */
+ #define CY_S11_Pos (19U) /**< The position of the FPU S11 content in a fault structure */
+ #define CY_S12_Pos (20U) /**< The position of the FPU S12 content in a fault structure */
+ #define CY_S13_Pos (21U) /**< The position of the FPU S13 content in a fault structure */
+ #define CY_S14_Pos (22U) /**< The position of the FPU S14 content in a fault structure */
+ #define CY_S15_Pos (23U) /**< The position of the FPU S15 content in a fault structure */
+ #define CY_FPSCR_Pos (24U) /**< The position of the FPU FPSCR content in a fault structure */
+ #endif /* CY_CPU_CORTEX_M4 && __FPU_PRESENT */
+
+ extern CY_NOINIT cy_stc_fault_frame_t cy_faultFrame; /**< Fault frame structure */
+#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
+
+
+/*******************************************************************************
+* Macro Name: CY_GET_REG8(addr)
+****************************************************************************//**
+*
+* Reads the 8-bit value from the specified address. This function can't be
+* used to access the Core register, otherwise a fault occurs.
+*
+* \param addr The register address.
+*
+* \return The read value.
+*
+*******************************************************************************/
+#define CY_GET_REG8(addr) (*((const volatile uint8_t *)(addr)))
+
+
+/*******************************************************************************
+* Macro Name: CY_SET_REG8(addr, value)
+****************************************************************************//**
+*
+* Writes an 8-bit value to the specified address. This function can't be
+* used to access the Core register, otherwise a fault occurs.
+*
+* \param addr The register address.
+*
+* \param value The value to write.
+*
+*******************************************************************************/
+#define CY_SET_REG8(addr, value) (*((volatile uint8_t *)(addr)) = (uint8_t)(value))
+
+
+/*******************************************************************************
+* Macro Name: CY_GET_REG16(addr)
+****************************************************************************//**
+*
+* Reads the 16-bit value from the specified address.
+*
+* \param addr The register address.
+*
+* \return The read value.
+*
+*******************************************************************************/
+#define CY_GET_REG16(addr) (*((const volatile uint16_t *)(addr)))
+
+
+/*******************************************************************************
+* Macro Name: CY_SET_REG16(addr, value)
+****************************************************************************//**
+*
+* Writes the 16-bit value to the specified address.
+*
+* \param addr The register address.
+*
+* \param value The value to write.
+*
+*******************************************************************************/
+#define CY_SET_REG16(addr, value) (*((volatile uint16_t *)(addr)) = (uint16_t)(value))
+
+
+/*******************************************************************************
+* Macro Name: CY_GET_REG24(addr)
+****************************************************************************//**
+*
+* Reads the 24-bit value from the specified address.
+*
+* \param addr The register address.
+*
+* \return The read value.
+*
+*******************************************************************************/
+#define CY_GET_REG24(addr) (((uint32_t) (*((const volatile uint8_t *)(addr)))) | \
+ (((uint32_t) (*((const volatile uint8_t *)(addr) + 1))) << 8U) | \
+ (((uint32_t) (*((const volatile uint8_t *)(addr) + 2))) << 16U))
+
+
+/*******************************************************************************
+* Macro Name: CY_SET_REG24(addr, value)
+****************************************************************************//**
+*
+* Writes the 24-bit value to the specified address.
+*
+* \param addr The register address.
+*
+* \param value The value to write.
+*
+*******************************************************************************/
+#define CY_SET_REG24(addr, value) do \
+ { \
+ (*((volatile uint8_t *) (addr))) = (uint8_t)(value); \
+ (*((volatile uint8_t *) (addr) + 1)) = (uint8_t)((value) >> 8U); \
+ (*((volatile uint8_t *) (addr) + 2)) = (uint8_t)((value) >> 16U); \
+ } \
+ while(0)
+
+
+/*******************************************************************************
+* Macro Name: CY_GET_REG32(addr)
+****************************************************************************//**
+*
+* Reads the 32-bit value from the specified register. The address is the little
+* endian order (LSB in lowest address).
+*
+* \param addr The register address.
+*
+* \return The read value.
+*
+*******************************************************************************/
+#define CY_GET_REG32(addr) (*((const volatile uint32_t *)(addr)))
+
+
+/*******************************************************************************
+* Macro Name: CY_SET_REG32(addr, value)
+****************************************************************************//**
+*
+* Writes the 32-bit value to the specified register. The address is the little
+* endian order (LSB in lowest address).
+*
+* \param addr The register address.
+*
+* \param value The value to write.
+*
+*******************************************************************************/
+#define CY_SET_REG32(addr, value) (*((volatile uint32_t *)(addr)) = (uint32_t)(value))
+
+
+/**
+* \defgroup group_syslib_macros_assert Assert Classes and Levels
+* \{
+* Defines for the Assert Classes and Levels
+*/
+
+/**
+* Class 1 - The highest class, safety-critical functions which rely on parameters that could be
+* changed between different PSoC devices
+*/
+#define CY_ASSERT_CLASS_1 (1U)
+
+/** Class 2 - Functions that have fixed limits such as counter periods (16-bits/32-bits etc.) */
+#define CY_ASSERT_CLASS_2 (2U)
+
+/** Class 3 - Functions that accept enums as constant parameters */
+#define CY_ASSERT_CLASS_3 (3U)
+
+#ifndef CY_ASSERT_LEVEL
+ /** The user-definable assert level from compiler command-line argument (similarly to DEBUG / NDEBUG) */
+ #define CY_ASSERT_LEVEL CY_ASSERT_CLASS_3
+#endif /* CY_ASSERT_LEVEL */
+
+#if (CY_ASSERT_LEVEL == CY_ASSERT_CLASS_1)
+ #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
+ #define CY_ASSERT_L2(x) do{} while(0) /**< Assert Level 2 */
+ #define CY_ASSERT_L3(x) do{} while(0) /**< Assert Level 3 */
+#elif (CY_ASSERT_LEVEL == CY_ASSERT_CLASS_2)
+ #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
+ #define CY_ASSERT_L2(x) CY_ASSERT(x) /**< Assert Level 2 */
+ #define CY_ASSERT_L3(x) do{} while(0) /**< Assert Level 3 */
+#else /* Default is Level 3 */
+ #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
+ #define CY_ASSERT_L2(x) CY_ASSERT(x) /**< Assert Level 2 */
+ #define CY_ASSERT_L3(x) CY_ASSERT(x) /**< Assert Level 3 */
+#endif /* CY_ASSERT_LEVEL == CY_ASSERT_CLASS_1 */
+
+/** \} group_syslib_macros_assert */
+
+
+/*******************************************************************************
+* Macro Name: CY_ASSERT
+****************************************************************************//**
+*
+* The macro that evaluates the expression and, if it is false (evaluates to 0),
+* the processor is halted. Cy_SysLib_AssertFailed() is called when the logical
+* expression is false to store the ASSERT location and halt the processor.
+*
+* \param x The logical expression. Asserts if false.
+* \note This macro is evaluated unless NDEBUG is not defined.
+* If NDEBUG is defined, just empty do while cycle is generated for this
+* macro for the sake of consistency and to avoid MISRA violation.
+* NDEBUG is defined by default for a Release build setting and not defined
+* for a Debug build setting.
+*
+*******************************************************************************/
+#if !defined(NDEBUG)
+ #define CY_ASSERT(x) do \
+ { \
+ if(!(x)) \
+ { \
+ Cy_SysLib_AssertFailed((char_t *) __FILE__, (uint32_t) __LINE__); \
+ } \
+ } while(0)
+#else
+ #define CY_ASSERT(x) do \
+ { \
+ } while(0)
+#endif /* !defined(NDEBUG) */
+
+
+/*******************************************************************************
+* Macro Name: _CLR_SET_FLD32U
+****************************************************************************//**
+*
+* The macro for setting a register with a name field and value for providing
+* get-clear-modify-write operations.
+* Returns a resulting value to be assigned to the register.
+*
+*******************************************************************************/
+#define _CLR_SET_FLD32U(reg, field, value) (((reg) & ((uint32_t)(~(field ## _Msk)))) | (_VAL2FLD(field, value)))
+
+
+/*******************************************************************************
+* Macro Name: CY_REG32_CLR_SET
+****************************************************************************//**
+*
+* Uses _CLR_SET_FLD32U macro for providing get-clear-modify-write
+* operations with a name field and value and writes a resulting value
+* to the 32-bit register.
+*
+*******************************************************************************/
+#define CY_REG32_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD32U((reg), field, (value)))
+
+
+/*******************************************************************************
+* Macro Name: _CLR_SET_FLD16U
+****************************************************************************//**
+*
+* The macro for setting a 16-bit register with a name field and value for providing
+* get-clear-modify-write operations.
+* Returns a resulting value to be assigned to the 16-bit register.
+*
+*******************************************************************************/
+#define _CLR_SET_FLD16U(reg, field, value) ((uint16_t)(((reg) & ((uint16_t)(~(field ## _Msk)))) | \
+ ((uint16_t)_VAL2FLD(field, value))))
+
+
+/*******************************************************************************
+* Macro Name: CY_REG16_CLR_SET
+****************************************************************************//**
+*
+* Uses _CLR_SET_FLD16U macro for providing get-clear-modify-write
+* operations with a name field and value and writes a resulting value
+* to the 16-bit register.
+*
+*******************************************************************************/
+#define CY_REG16_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD16U((reg), field, (value)))
+
+
+/*******************************************************************************
+* Macro Name: _CLR_SET_FLD8U
+****************************************************************************//**
+*
+* The macro for setting a 8-bit register with a name field and value for providing
+* get-clear-modify-write operations.
+* Returns a resulting value to be assigned to the 8-bit register.
+*
+*******************************************************************************/
+#define _CLR_SET_FLD8U(reg, field, value) ((uint8_t)(((reg) & ((uint8_t)(~(field ## _Msk)))) | \
+ ((uint8_t)_VAL2FLD(field, value))))
+
+
+/*******************************************************************************
+* Macro Name: CY_REG8_CLR_SET
+****************************************************************************//**
+*
+* Uses _CLR_SET_FLD8U macro for providing get-clear-modify-write
+* operations with a name field and value and writes a resulting value
+* to the 8-bit register.
+*
+*******************************************************************************/
+#define CY_REG8_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD8U((reg), field, (value)))
+
+
+/*******************************************************************************
+* Macro Name: _BOOL2FLD
+****************************************************************************//**
+*
+* Returns a field mask if the value is not false.
+* Returns 0, if the value is false.
+*
+*******************************************************************************/
+#define _BOOL2FLD(field, value) (((value) != false) ? (field ## _Msk) : 0UL)
+
+
+/*******************************************************************************
+* Macro Name: _FLD2BOOL
+****************************************************************************//**
+*
+* Returns true, if the value includes the field mask.
+* Returns false, if the value doesn't include the field mask.
+*
+*******************************************************************************/
+#define _FLD2BOOL(field, value) (((value) & (field ## _Msk)) != 0UL)
+
+
+/*******************************************************************************
+* Macro Name: CY_SYSLIB_DIV_ROUND
+****************************************************************************//**
+*
+* Calculates a / b with rounding to the nearest integer,
+* a and b must have the same sign.
+*
+*******************************************************************************/
+#define CY_SYSLIB_DIV_ROUND(a, b) (((a) + ((b) / 2U)) / (b))
+
+
+/*******************************************************************************
+* Macro Name: CY_SYSLIB_DIV_ROUNDUP
+****************************************************************************//**
+*
+* Calculates a / b with rounding up if remainder != 0,
+* both a and b must be positive.
+*
+*******************************************************************************/
+#define CY_SYSLIB_DIV_ROUNDUP(a, b) ((((a) - 1U) / (b)) + 1U)
+
+
+/******************************************************************************
+* Constants
+*****************************************************************************/
+/** Defines a 32-kHz clock delay */
+#define CY_DELAY_MS_OVERFLOW (0x8000U)
+
+/**
+* \defgroup group_syslib_macros_reset_cause Reset cause
+* \{
+* Define RESET_CAUSE mask values
+*/
+/** A basic WatchDog Timer (WDT) reset has occurred since the last power cycle. */
+#define CY_SYSLIB_RESET_HWWDT (0x0001U)
+/** The fault logging system requested a reset from its Active logic. */
+#define CY_SYSLIB_RESET_ACT_FAULT (0x0002U)
+/** The fault logging system requested a reset from its Deep-Sleep logic. */
+#define CY_SYSLIB_RESET_DPSLP_FAULT (0x0004U)
+/** The CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. */
+#define CY_SYSLIB_RESET_SOFT (0x0010U)
+/** The Multi-Counter Watchdog timer #0 reset has occurred since the last power cycle. */
+#define CY_SYSLIB_RESET_SWWDT0 (0x0020U)
+/** The Multi-Counter Watchdog timer #1 reset has occurred since the last power cycle. */
+#define CY_SYSLIB_RESET_SWWDT1 (0x0040U)
+/** The Multi-Counter Watchdog timer #2 reset has occurred since the last power cycle. */
+#define CY_SYSLIB_RESET_SWWDT2 (0x0080U)
+/** The Multi-Counter Watchdog timer #3 reset has occurred since the last power cycle. */
+#define CY_SYSLIB_RESET_SWWDT3 (0x0100U)
+/** The reset has occurred on a wakeup from Hibernate power mode. */
+#define CY_SYSLIB_RESET_HIB_WAKEUP (0x40000UL)
+
+/** \} group_syslib_macros_reset_cause */
+
+/** Bit[31:24] Opcode = 0x1B (SoftReset)
+ * Bit[7:1] Type = 1 (Only CM4 reset)
+ */
+#define CY_IPC_DATA_FOR_CM4_SOFT_RESET (0x1B000002UL)
+
+/**
+* \defgroup group_syslib_macros_unique_id Unique ID
+* \{
+* Unique ID fields positions
+*/
+#define CY_UNIQUE_ID_DIE_YEAR_Pos (57U) /**< The position of the DIE_YEAR field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_MINOR_Pos (56U) /**< The position of the DIE_MINOR field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_SORT_Pos (48U) /**< The position of the DIE_SORT field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_Y_Pos (40U) /**< The position of the DIE_Y field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_X_Pos (32U) /**< The position of the DIE_X field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_WAFER_Pos (24U) /**< The position of the DIE_WAFER field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_LOT_2_Pos (16U) /**< The position of the DIE_LOT_2 field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_LOT_1_Pos (8U) /**< The position of the DIE_LOT_1 field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_LOT_0_Pos (0U) /**< The position of the DIE_LOT_0 field in the silicon Unique ID */
+
+/** \} group_syslib_macros_unique_id */
+
+/** \} group_syslib_macros */
+
+/******************************************************************************
+* Function prototypes
+******************************************************************************/
+
+/**
+* \addtogroup group_syslib_functions
+* \{
+*/
+
+void Cy_SysLib_Delay(uint32_t milliseconds);
+void Cy_SysLib_DelayUs(uint16_t microseconds);
+/** Delays for the specified number of cycles.
+ * The function is implemented in the assembler for each supported compiler.
+ * \param cycles The number of cycles to delay.
+ */
+void Cy_SysLib_DelayCycles(uint32_t cycles);
+__NO_RETURN void Cy_SysLib_Halt(uint32_t reason);
+void Cy_SysLib_AssertFailed(const char_t * file, uint32_t line);
+void Cy_SysLib_ClearFlashCacheAndBuffer(void);
+cy_en_syslib_status_t Cy_SysLib_ResetBackupDomain(void);
+uint32_t Cy_SysLib_GetResetReason(void);
+void Cy_SysLib_ClearResetReason(void);
+uint64_t Cy_SysLib_GetUniqueId(void);
+#if (CY_CPU_CORTEX_M0P)
+ void Cy_SysLib_SoftResetCM4(void);
+#endif /* CY_CPU_CORTEX_M0P */
+#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN)
+ void Cy_SysLib_FaultHandler(uint32_t const *faultStackAddr);
+ void Cy_SysLib_ProcessingFault(void);
+#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
+void Cy_SysLib_SetWaitStates(bool ulpMode, uint32_t clkHfMHz);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_EnterCriticalSection
+****************************************************************************//**
+*
+* Cy_SysLib_EnterCriticalSection disables interrupts and returns a value
+* indicating whether the interrupts were previously enabled.
+*
+* \return Returns the current interrupt status. Returns 0 if the interrupts
+* were previously enabled or 1 if the interrupts were previously
+* disabled.
+*
+* \note Implementation of Cy_SysLib_EnterCriticalSection manipulates the IRQ
+* enable bit with interrupts still enabled.
+*
+*******************************************************************************/
+uint32_t Cy_SysLib_EnterCriticalSection(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_ExitCriticalSection
+****************************************************************************//**
+*
+* Re-enables the interrupts if they were enabled before
+* Cy_SysLib_EnterCriticalSection() was called. The argument should be the value
+* returned from \ref Cy_SysLib_EnterCriticalSection().
+*
+* \param savedIntrStatus Puts the saved interrupts status returned by
+* the \ref Cy_SysLib_EnterCriticalSection().
+*
+*******************************************************************************/
+void Cy_SysLib_ExitCriticalSection(uint32_t savedIntrStatus);
+
+
+/** \cond INTERNAL */
+#define CY_SYSLIB_DEVICE_REV_0A (0x21U) /**< The device TO *A Revision ID */
+#define CY_SYSLIB_DEVICE_PSOC6ABLE2 (0x100U) /**< The PSoC6 BLE2 device Family ID */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_GetDeviceRevision
+****************************************************************************//**
+*
+* This function returns a device Revision ID.
+*
+* \return A device Revision ID.
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_SysLib_GetDeviceRevision(void)
+{
+ return ((SFLASH_SI_REVISION_ID == 0UL) ? CY_SYSLIB_DEVICE_REV_0A : SFLASH_SI_REVISION_ID);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_GetDevice
+****************************************************************************//**
+*
+* This function returns a device Family ID.
+*
+* \return A device Family ID.
+*
+*******************************************************************************/
+__STATIC_INLINE uint16_t Cy_SysLib_GetDevice(void)
+{
+ return ((SFLASH_FAMILY_ID == 0UL) ? CY_SYSLIB_DEVICE_PSOC6ABLE2 : SFLASH_FAMILY_ID);
+}
+
+
+typedef uint32_t cy_status;
+/** The ARM 32-bit status value for backward compatibility with the UDB components. Do not use it in your code. */
+typedef uint32_t cystatus;
+typedef uint8_t uint8; /**< Alias to uint8_t for backward compatibility */
+typedef uint16_t uint16; /**< Alias to uint16_t for backward compatibility */
+typedef uint32_t uint32; /**< Alias to uint32_t for backward compatibility */
+typedef int8_t int8; /**< Alias to int8_t for backward compatibility */
+typedef int16_t int16; /**< Alias to int16_t for backward compatibility */
+typedef int32_t int32; /**< Alias to int32_t for backward compatibility */
+typedef float float32; /**< Alias to float for backward compatibility */
+typedef double float64; /**< Alias to double for backward compatibility */
+typedef int64_t int64; /**< Alias to int64_t for backward compatibility */
+typedef uint64_t uint64; /**< Alias to uint64_t for backward compatibility */
+/* Signed or unsigned depending on the compiler selection */
+typedef char char8; /**< Alias to char for backward compatibility */
+typedef volatile uint8_t reg8; /**< Alias to uint8_t for backward compatibility */
+typedef volatile uint16_t reg16; /**< Alias to uint16_t for backward compatibility */
+typedef volatile uint32_t reg32; /**< Alias to uint32_t for backward compatibility */
+
+/** The ARM 32-bit Return error / status code for backward compatibility.
+* Do not use them in your code.
+*/
+#define CY_RET_SUCCESS (0x00U) /* Successful */
+#define CY_RET_BAD_PARAM (0x01U) /* One or more invalid parameters */
+#define CY_RET_INVALID_OBJECT (0x02U) /* An invalid object specified */
+#define CY_RET_MEMORY (0x03U) /* A memory-related failure */
+#define CY_RET_LOCKED (0x04U) /* A resource lock failure */
+#define CY_RET_EMPTY (0x05U) /* No more objects available */
+#define CY_RET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */
+#define CY_RET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */
+#define CY_RET_FINISHED (0x08U) /* Operation is completed */
+#define CY_RET_CANCELED (0x09U) /* Operation is canceled */
+#define CY_RET_TIMEOUT (0x10U) /* Operation timed out */
+#define CY_RET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */
+#define CY_RET_UNKNOWN ((cy_status) 0xFFFFFFFFU) /* Unknown failure */
+
+/** ARM 32-bit Return error / status codes for backward compatibility with the UDB components.
+* Do not use them in your code.
+*/
+#define CYRET_SUCCESS (0x00U) /* Successful */
+#define CYRET_BAD_PARAM (0x01U) /* One or more invalid parameters */
+#define CYRET_INVALID_OBJECT (0x02U) /* An invalid object specified */
+#define CYRET_MEMORY (0x03U) /* A memory-related failure */
+#define CYRET_LOCKED (0x04U) /* A resource lock failure */
+#define CYRET_EMPTY (0x05U) /* No more objects available */
+#define CYRET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */
+#define CYRET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */
+#define CYRET_FINISHED (0x08U) /* Operation is completed */
+#define CYRET_CANCELED (0x09U) /* Operation is canceled */
+#define CYRET_TIMEOUT (0x10U) /* Operation timed out */
+#define CYRET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */
+#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFU) /* Unknown failure */
+
+/** A type of ISR callbacks for backward compatibility with the UDB components. Do not use it in your code. */
+typedef void (* cyisraddress)(void);
+#if defined (__ICCARM__)
+ /** A type of ISR callbacks for backward compatibility with the UDB components. Do not use it in your code. */
+ typedef union { cyisraddress __fun; void * __ptr; } intvec_elem;
+#endif /* defined (__ICCARM__) */
+
+/** The backward compatibility define for the CyDelay() API for the UDB components.
+* Do not use it in your code.
+*/
+#define CyDelay Cy_SysLib_Delay
+/** The backward compatibility define for the CyDelayUs() API for the UDB components.
+* Do not use it in your code.
+*/
+#define CyDelayUs Cy_SysLib_DelayUs
+/** The backward compatibility define for the CyDelayCycles() API for the UDB components.
+* Do not use it in your code.
+*/
+#define CyDelayCycles Cy_SysLib_DelayCycles
+/** The backward compatibility define for the CyEnterCriticalSection() API for the UDB components.
+* Do not use it in your code.
+*/
+#define CyEnterCriticalSection() ((uint8_t) Cy_SysLib_EnterCriticalSection())
+/** The backward compatibility define for the CyExitCriticalSection() API for the UDB components.
+* Do not use it in your code.
+*/
+#define CyExitCriticalSection(x) (Cy_SysLib_ExitCriticalSection((uint32_t) (x)))
+/** \endcond */
+
+/** \} group_syslib_functions */
+
+#if defined(__cplusplus)
+}
+#endif /* defined(__cplusplus) */
+
+#endif /* CY_SYSLIB_H */
+
+/** \} group_syslib */
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_syspm.h b/platform/ext/target/psoc64/Native_Driver/include/cy_syspm.h
new file mode 100644
index 0000000000..a762587bf2
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_syspm.h
@@ -0,0 +1,2861 @@
+/***************************************************************************//**
+* \file cy_syspm.h
+* \version 4.40
+*
+* Provides the function definitions for the power management API.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+* \addtogroup group_syspm
+* \{
+*
+* Use the System Power Management (SysPm) driver to change power modes and
+* reduce system power consumption in power sensitive designs.
+*
+* The functions and other declarations used in this driver are in cy_syspm.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions
+* and declarations in the PDL.
+*
+* For multi-CPU devices, this library allows you to individually enter low power
+* modes for each CPU.
+*
+* This document contains the following topics:
+*
+* * \ref group_syspm_power_modes
+* * \ref group_syspm_system_power_modes
+* - \ref group_syspm_switching_into_ulp
+* - \ref group_syspm_ulp_limitations
+* - \ref group_syspm_switching_into_lp
+* - \ref group_syspm_lp_limitations
+* - \ref group_syspm_switching_into_sleep
+* - \ref group_syspm_switching_into_deepsleep
+* - \ref group_syspm_wakingup_from_sleep_deepsleep
+* - \ref group_syspm_switching_into_hibernate
+* - \ref group_syspm_wakingup_from_hibernate
+* * \ref group_syspm_system_reg_curr_mode
+* - \ref group_syspm_system_set_min_reg_curr_mode
+* - \ref group_syspm_system_set_normal_reg_curr_mode
+* * \ref group_syspm_migration_guide_for_syspm_4_0
+* * \ref group_syspm_managing_pmic
+* * \ref group_syspm_managing_backup_domain
+* * \ref group_syspm_cb
+* - \ref group_syspm_cb_example
+* - \ref group_syspm_cb_config_consideration
+* - \ref group_syspm_cb_parameters
+* - \ref group_syspm_cb_structures
+* - \ref group_syspm_cb_function_implementation
+* - \ref group_syspm_cb_flow
+* - \ref group_syspm_cb_registering
+* - \ref group_syspm_cb_unregistering
+* * \ref group_syspm_definitions
+*
+* \section group_syspm_section_configuration Configuration Considerations
+* \subsection group_syspm_power_modes Power Modes
+* PSoC 6 MCUs support four system and three CPU power modes. These power modes
+* are intended to minimize average power consumption in an application.
+* System power modes:
+* * <b>Low Power</b> - All peripheral and CPU power modes
+* are available to be used at maximum device frequency and current
+* consumption.
+* * <b>Ultra Low Power</b> - All peripheral and
+* CPU power modes are available, but the frequency and current consumption
+* are limited to a device specific number.
+* * <b>Deep Sleep</b> - Device and I/O states is retained. Low-frequency
+* peripherals are available. Both CPUs are in CPU Deep Sleep power mode.
+* * <b>Hibernate</b> - The device and I/O states are frozen and the device
+* resets on wakeup.
+*
+* The CPU <b>Active</b>, <b>Sleep</b> and <b>Deep Sleep</b> power modes are
+* Arm-defined power modes supported by the Arm CPU instruction
+* set architecture (ISA).
+*
+* \subsection group_syspm_system_power_modes System Power Modes
+* * <b>LP</b> - In this mode, code is executed and all logic and
+* memories are powered. Firmware may disable/reduce clocks for specific
+* peripherals and power down specific analog power domains.
+*
+* * <b>ULP</b> - This power mode is like LP mode, but
+* with clock restrictions and limited/slower peripherals to achieve lower
+* current consumption. Refer to \ref group_syspm_switching_into_ulp in
+* Configuration considerations.
+*
+* * <b>Deep Sleep</b> - Is a lower power mode where high-frequency clocks are
+* disabled. Refer to \ref group_syspm_switching_into_deepsleep in
+* Configuration considerations. Deep-sleep-capable peripherals are available.
+* A normal wakeup from Deep Sleep returns to either system LP or ULP mode,
+* depending on the previous state and programmed behavior for the configured
+* wakeup interrupt. Likewise, a debug wakes up from system Deep Sleep and
+* woken CPU returns to CPU Sleep. Refer
+* to \ref group_syspm_wakingup_from_sleep_deepsleep in Configuration
+* considerations.
+*
+* * <b>Hibernate</b> - Is the lowest power mode that is entered from
+* firmware. Refer to \ref group_syspm_switching_into_hibernate in
+* Configuration considerations. On wakeup the CPU(s) and all peripherals
+* go through a full reset. The I/O's state is frozen so that the
+* output driver state is held in system Hibernate. Note that in this mode,
+* the CPU(s) and all peripherals lose their states, so the system and firmware
+* reboot on a wakeup event. Backup memory (if present) can be used to store
+* limited system state for use on the next reboot. Refer to
+* \ref group_syspm_wakingup_from_hibernate in Configuration considerations.
+*
+* \subsubsection group_syspm_switching_into_lp Switching the System into Low Power
+* To set system LP mode you need to set LP voltage for the active core
+* regulator:
+* * If active core regulator is the LDO, call:
+* \code{.c}
+* Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
+* \endcode
+* * If active core regulator is the Buck, call:
+* \code{.c}
+* Cy_SysPm_BuckSetVoltage1(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP)
+* \endcode
+*
+* After switching into system LP mode, the operating frequency and current
+* consumption may now be increased up to \ref group_syspm_lp_limitations.
+* The wait states for flash may be changed to increase device performance by
+* calling SysLib function Cy_SysLib_SetWaitStates(true, hfClkFreqMz), where
+* hfClkFreqMz is the frequency of HfClk0 in MHz.
+*
+* \subsubsection group_syspm_lp_limitations LP Limitations
+* When the system is in LP mode, the core regulator voltage is set to
+* <b>1.1 V (nominal)</b> and the following limitations must be met:
+*
+* - The maximum operating frequency for all Clk_HF paths must not exceed
+* <b>150 MHz*</b>, and peripheral and slow clock must
+* not exceed <b>100 MHz *</b>
+*
+* - The total current consumption must be less than or equal to
+* <b>250 mA *</b>
+*
+* \warning * - Numbers shown are approximate and real limit values may be
+* different because they are device specific. You should refer to the device
+* datasheet for exact values of maximum frequency and current in system LP mode.
+*
+* \subsubsection group_syspm_switching_into_ulp Switching the System into Ultra Low Power
+* Before switching into system ULP mode, ensure that the device meets
+* \ref group_syspm_ulp_limitations. Decrease the clock frequencies,
+* and slow or disable peripherals. Also ensure that appropriate wait state
+* values are set for the flash. Flash wait states can be set by calling
+* SysLib function Cy_SysLib_SetWaitStates(true, hfClkFreqMz), where hfClkFreqMz
+* is the frequency of HfClk0 in MHz.
+*
+* After the \ref group_syspm_ulp_limitations are met and appropriate wait
+* states are set, you must set ULP voltage for the active core regulator:
+* * If active core regulator is the LDO Core Voltage Regulator, call
+* Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_ULP)
+* * If active core regulator is the Buck Core Voltage Regulator, then call
+* Cy_SysPm_BuckSetVoltage1(CY_SYSPM_BUCK_OUT1_VOLTAGE_ULP)
+*
+* \subsubsection group_syspm_ulp_limitations ULP Limitations
+* When the system is in ULP mode the core regulator voltage is set to <b>0.9 V
+* (nominal)</b> and the following limitations must be meet:
+*
+* - The maximum operating frequency for all Clk_HF paths must not exceed
+* <b>50 MHz *</b>, whereas the peripheral and slow clock must not exceed
+* <b>25 MHz *</b>.
+*
+* - The total current consumption must be less than or equal
+* to <b>20 mA*</b>
+*
+* - the flash write operations are prohibited. The flash works in the
+* Read-only operation. If Write operations are required, you must switch to
+* the system LP mode.
+*
+* \warning * - Numbers shown are approximate and real limit values may be
+* different because they are device specific. You should refer to the device
+* datasheet for exact values of maximum frequency and current in system
+* ULP mode.
+*
+* \subsubsection group_syspm_switching_into_sleep Switching CPU into Sleep
+* For multi-CPU devices, the Cy_SysPm_CpuEnterSleep() switches only the CPU
+* that calls the function into the CPU Sleep power mode.
+*
+* All pending interrupts must be cleared before the CPU is put into a
+* Sleep mode, even if they are masked.
+*
+* The CPU event register can be set in the past, for example, as a result of
+* internal system calls. So an old event can cause the CPU to not enter
+* Sleep mode upon WFE(). Therefore usually the WFE() is used in an idle loop or
+* polling loop as it might or might not cause entering of CPU Sleep mode. If
+* the idle loop or polling loop is not used, then it is recommended to use
+* WFI() instruction.
+*
+* \subsubsection group_syspm_switching_into_deepsleep Switching the System or CPU into Deep Sleep
+* For multi-CPU devices, the Cy_SysPm_CpuEnterDeepSleep() function switches
+* only the CPU that calls the function into the CPU Deep Sleep power mode.
+* To set the whole system into Deep Sleep power mode, ensure that all CPUs call
+* the Cy_SysPm_CpuEnterDeepSleep() function.
+*
+* There are situations when the system does not switch into the Deep Sleep
+* power mode immediately after the last CPU calls Cy_SysPm_CpuEnterDeepSleep().
+* The system will switch into Deep Sleep mode automatically a short time later,
+* after the low power circuits are ready to switch into Deep Sleep. Refer to
+* the Cy_SysPm_CpuEnterDeepSleep() description for more detail.
+*
+* All pending interrupts must be cleared before the system is put into a
+* Deep Sleep mode, even if they are masked.
+*
+* The CPU event register can be set in the past, for example, as a result of
+* internal system calls. So an old event can cause the CPU to not enter Deep
+* Sleep mode upon WFE(). Therefore usually the WFE() is used in an idle loop or
+* polling loop as it might or might not cause entering of CPU Deep Sleep mode.
+* If the idle loop or polling loop is not used, then it is recommended to use
+* WFI() instruction.
+*
+* For single-CPU devices, SysPm functions that return the status of the
+* unsupported CPU always return CY_SYSPM_STATUS_<CPU>_DEEPSLEEP.
+*
+* \subsubsection group_syspm_wakingup_from_sleep_deepsleep Waking Up from Sleep or Deep Sleep
+* For Arm-based devices, an interrupt is required for the CPU to wake up.
+* For multi-CPU devices, one CPU can wake up the other CPU by sending the
+* event instruction. Use the Cy_SysPm_CpuSendWakeupEvent() function.
+*
+* \subsubsection group_syspm_switching_into_hibernate Switching System to Hibernate
+* If you call Cy_SysPm_SystemEnterHibernate() from either CPU, the system will
+* be switched into the Hibernate power mode directly, because there is no
+* handshake between CPUs.
+*
+* \subsubsection group_syspm_wakingup_from_hibernate Waking Up from Hibernate
+*
+* The system can wake up from Hibernate mode by configuring the following wakeup
+* sources:
+* - Wakeup pin
+* - LP Comparator
+* - RTC alarm
+* - WDT interrupt
+*
+* Wakeup is supported from device specific pin(s) with programmable polarity.
+* Additionally, unregulated peripherals can wake the system under some
+* conditions. For example, a low power comparator can wake the system by
+* comparing two external voltages, but does not support comparison to an
+* internally-generated voltage. The backup power domain remains functional, and
+* if present it can schedule an alarm to wake the system from Hibernate using
+* the RTC. Alternatively, the Watchdog Timer (WDT) can be configured to wake-up
+* the system by WDT interrupt. Refer to \ref Cy_SysPm_SetHibernateWakeupSource()
+* for more detail.
+*
+* \subsection group_syspm_system_reg_curr_mode System Regulator Current Mode
+* In addition to system ULP and LP modes, the five different resource
+* power settings can be configured to reduce current consumption:
+* -# <b>Linear regulator low power mode</b>. Can be used only if core current
+* is below the LDO regulator LP threshold.
+* -# <b>POR/BOD circuit low power mode</b>. Requires compatible power supply
+* stability due to stability increase response time.
+* -# <b>Bandgap reference circuits low power mode</b> (turns on Deep Sleep
+* Bandgap). Requires design to accept reduced Vref accuracy. Active ref can
+* be turned off after this feature is enabled.
+* -# <b>Reference buffer circuit low power mode</b>. Requires design to accept
+* reduced Vref accuracy.
+* -# <b>Current reference circuit low power mode</b>. Require design to accept
+* reduced Iref accuracy.
+*
+* These five sub features can modify both system LP or ULP modes as they are
+* independent from LP/ULP settings.
+* When all five sub features are set to their low power modes, the system
+* operates in regulator minimum current mode. In regulator minimum current mode,
+* the system current consumption is limited to a device-specific value. Refer to
+* the device datasheet for the exact current consumption value in regulator
+* minimum current mode.
+*
+* When all five sub features are set to their normal mode, the system operates
+* in regulator normal current mode. When regulator normal current mode is set,
+* the system may operate at device maximum current.
+*
+* \subsection group_syspm_system_set_min_reg_curr_mode Setting Minimum System Regulator Current Mode
+*
+* Before setting the regulator minimum current mode ensure that current limits
+* are be met. After current limits are met, call the
+* Cy_SysPm_SystemSetMinRegulatorCurrent() function.
+*
+* \subsection group_syspm_system_set_normal_reg_curr_mode Setting Normal System Regulator Current Mode
+*
+* To set regulator normal current mode, call the
+* Cy_SysPm_SystemSetNormalRegulatorCurrent() function. After the function call,
+* the current limits can be increased to a maximum current, depending on what
+* system power mode is set: LP or ULP.
+*
+* \subsection group_syspm_managing_pmic Managing PMIC
+*
+* The SysPm driver also provides an API to configure the internal power
+* management integrated circuit (PMIC) controller for an external PMIC that
+* supplies Vddd. Use the API to enable the internal PMIC controller output that
+* is routed to pmic_wakeup_out pin, and configure the polarity of the PMIC
+* controller input (pmic_wakeup_in) that is used to wake up the PMIC.
+*
+* The PMIC controller is automatically enabled when:
+* * The PMIC is locked by a call to Cy_SysPm_PmicLock()
+* * The configured polarity of the PMIC input and the polarity driven to
+* pmic_wakeup_in pin matches.
+*
+* Because a call to Cy_SysPm_PmicLock() automatically enables the PMIC
+* controller, the PMIC can remain disabled only when it is unlocked. See Cy_SysPm_PmicUnlock()
+* for more detail.
+*
+* Use Cy_SysPm_PmicIsLocked() to read the current PMIC lock status.
+*
+* To enable the PMIC, use these functions in this order:
+* \code{.c}
+* Cy_SysPm_PmicUnlock();
+* Cy_SysPm_PmicEnable();
+* Cy_SysPm_PmicLock();
+* \endcode
+*
+* To disable the PMIC controller, unlock the PMIC. Then call
+* Cy_SysPm_PmicDisable() with the inverted value of the current active state of
+* the pmic_wakeup_in pin.
+* For example, assume the current state of the pmic_wakeup_in pin is active low.
+* To disable the PMIC controller, call these functions in this order:
+* \code{.c}
+* Cy_SysPm_PmicUnlock();
+* Cy_SysPm_PmicDisable(CY_SYSPM_PMIC_POLARITY_HIGH);
+* \endcode
+* Note that you do not call Cy_SysPm_PmicLock(), because that automatically
+* enables the PMIC.
+*
+* While disabled, the PMIC controller is automatically enabled when the
+* pmic_wakeup_in pin state is changed into a high state.
+*
+* To disable the PMIC controller output, call these functions in this order:
+* Cy_SysPm_PmicUnlock();
+* Cy_SysPm_PmicDisableOutput();
+*
+* Do not call Cy_SysPm_PmicLock() (which automatically enables the PMIC
+* controller output).
+*
+* When disabled, the PMIC controller output is enabled when the PMIC is locked,
+* or by calling Cy_SysPm_PmicEnableOutput().
+*
+* \subsection group_syspm_managing_backup_domain Managing the Backup Domain
+* The SysPm driver provide functions to:
+*
+* * Configure Supercapacitor charging
+* * Select power supply source (Vbackup or Vddd) for Vddbackup
+* * Measure Vddbackup using the ADC
+*
+* Refer to the \ref group_syspm_functions_backup functions for more detail.
+*
+* \subsection group_syspm_cb SysPm Callbacks
+* The SysPm driver handles low power callbacks declared in the application.
+*
+* If there are no callbacks registered, the device executes the power mode
+* transition. However, frequently your application firmware must make
+* modifications for low power mode. For example, you may need to disable a
+* peripheral, or ensure that a message is not being transmitted or received.
+*
+* To enable this, the SysPm driver implements a callback mechanism. When a lower
+* power mode transition is about to take place (either entering or exiting
+* \ref group_syspm_system_power_modes), the registered callbacks for that
+* transition are called.
+*
+* The SysPm driver organizes all the callbacks into a linked list. While
+* entering a low power mode, SysPm goes through that linked list from first to
+* last, executing the callbacks one after another. While exiting low power mode,
+* SysPm goes through that linked list again, but in the opposite direction from
+* last to first. This ordering supports prioritization of callbacks relative to
+* the transition event.
+*
+* For example, the picture below shows three callback structures organized into
+* a linked list: myDeepSleep1, myDeepSleep2, myDeepSleep3 (represented with the
+* \ref cy_stc_syspm_callback_t configuration structure). Each structure
+* contains, among other fields, the address of the callback function. The code
+* snippets below set this up so that myDeepSleep1 is called first when entering
+* the low power mode. This also means that myDeepSleep1 will be the last one to
+* execute when exiting the low power mode.
+*
+* The callback structures after registration:
+* \image html syspm_register_eq.png
+*
+* Your application must register each callback, so that SysPm can execute it.
+* Upon registration, the linked list is built by the SysPm driver. Notice
+* the &myDeepSleep1 address in the myDeepSleep1
+* \ref cy_stc_syspm_callback_t structure. This is filled in by the SysPm driver,
+* when you register myDeepSleep1. The cy_stc_syspm_callback_t.order element
+* defines the order of their execution by the SysPm driver.
+* Call \ref Cy_SysPm_RegisterCallback() to register each callback function.
+*
+* A callback function is typically associated with a particular driver that
+* handles the peripheral. So the callback mechanism enables a peripheral to
+* prepare for a low power mode (for instance, shutting down the analog part);
+* or to perform tasks while exiting a low power mode (like enabling the analog
+* part again).
+*
+* With the callback mechanism you can prevent switching into a low power mode if
+* a peripheral is not ready. For example, driver X is in the process of
+* receiving a message. In the callback function implementation simply return
+* CY_SYSPM_FAIL in a response to CY_SYSPM_CHECK_READY.
+*
+* If success is returned while executing a callback, the SysPm driver calls the
+* next callback and so on to the end of the list. If at some point a callback
+* returns CY_SYSPM_FAIL in response to the CY_SYSPM_CHECK_READY step, all the
+* callbacks that have already executed are executed in reverse order, with the
+* CY_SYSPM_CHECK_FAIL mode parameter. This allows each callback to know that
+* entering the low power mode has failed. The callback can then undo whatever it
+* did to prepare for low power mode, if required. For example, if the driver X
+* callback shut down the analog part, it can re-enable the analog part.
+*
+* Let's switch to an example explaining the implementation, setup, and
+* registration of three callbacks (myDeepSleep1, myDeepSleep2, myDeepSleep2) in
+* the application. The \ref group_syspm_cb_config_consideration are provided
+* after the \ref group_syspm_cb_example.
+*
+* \subsection group_syspm_cb_example SysPm Callbacks Example
+*
+* The following code snippets demonstrate how use the SysPm callbacks mechanism.
+* We will build the prototype for an application that registers
+* three callback functions:
+* -# myDeepSleep1 - Handles CPU Deep Sleep.
+* -# myDeepSleep2 - Handles CPU Deep Sleep and is associated with peripheral
+* HW1_address (see <a href="..\..\pdl_user_guide.pdf">PDL Design</a>
+* section to learn about the base hardware address).
+* -# myDeepSleep3 - Handles entering and exiting system Deep Sleep and is
+* associated with peripheral HW2_address.
+*
+* We set things up so that the myDeepSleep1 and myDeepSleep2 callbacks do
+* nothing while entering the low power mode (skip on
+* CY_SYSPM_SKIP_BEFORE_TRANSITION -
+* see \ref group_syspm_cb_function_implementation in
+* \ref group_syspm_cb_config_consideration).
+* Skipping the actions while entering low power might be useful if you need
+* to save time while switching low power modes. This is because the callback
+* function with a skipped mode is not even called avoiding the call and return
+* overhead.
+*
+* Let's first declare the callback functions. Each gets the pointer to the
+* \ref cy_stc_syspm_callback_params_t structure as the argument.
+*
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Func_Declaration
+*
+* Now we setup the \ref cy_stc_syspm_callback_params_t structures that we will
+* pass to the callback functions. Note that for the myDeepSleep2 and
+* myDeepSleep3 callbacks we also pass pointers to the peripherals related to
+* that callback (see <a href="..\..\pdl_user_guide.pdf">PDL Design</a> section
+* to learn about base hardware addresses).
+* The configuration considerations related to this structure are described
+* in \ref group_syspm_cb_parameters in \ref group_syspm_cb_config_consideration.
+*
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Params_Declaration
+*
+* Now we setup the actual callback configuration structures. Each of these
+* contains, among the other fields, the address of the
+* \ref cy_stc_syspm_callback_params_t we just set up. We will use the callback
+* configuration structures later in the code to register the callbacks in the
+* SysPm driver. Again, we set things up so that the myDeepSleep1 and
+* myDeepSleep2 callbacks do nothing while entering the low power mode
+* (skip on CY_SYSPM_SKIP_BEFORE_TRANSITION) - see
+* \ref group_syspm_cb_function_implementation in
+* \ref group_syspm_cb_config_consideration.
+*
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Structure_Declaration
+*
+* Note that in each case the last two fields are NULL. These are fields used by
+* the SysPm driver to set up the linked list of callback functions.
+*
+* The callback structures are now defined and allocated in the user's
+* memory space:
+* \image html syspm_before_registration.png
+*
+* Now we implement the callback functions. See
+* \ref group_syspm_cb_function_implementation in
+* \ref group_syspm_cb_config_consideration for the instructions on how the
+* callback functions should be implemented.
+*
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Func_Implementation
+*
+* Finally, we register the callbacks so that the SysPm driver knows about them.
+* The order in which the callbacks will be called depends upon the order in
+* which the callbacks are registered. If there are no callbacks registered,
+* the device just executes the power mode transition.
+*
+* Callbacks that reconfigure global resources, such as clock frequencies, should
+* be registered last. They then modify global resources as the final step before
+* entering the low power mode, and restore those resources first, as the system
+* returns from low power mode.
+*
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_RegisterCallback
+*
+* We are done configuring three callbacks. Now the SysPm driver will execute the
+* callbacks appropriately whenever there is a call to a power mode transition
+* function: \ref Cy_SysPm_CpuEnterSleep(), \ref Cy_SysPm_CpuEnterDeepSleep(),
+* \ref Cy_SysPm_SystemEnterUlp(), \ref Cy_SysPm_SystemEnterLp(), and
+* \ref Cy_SysPm_SystemEnterHibernate().
+* \note On a wakeup from hibernate the device goes through a reset, so the
+* callbacks with CY_SYSPM_AFTER_TRANSITION are not executed. Refer to
+* \ref Cy_SysPm_SystemEnterHibernate() for more detail.
+*
+* Refer to \ref group_syspm_cb_unregistering in
+* \ref group_syspm_cb_config_consideration to learn what to do if you need to
+* remove the callback from the linked list. You might want to unregister the
+* callback for debug purposes.
+*
+* Refer to \ref group_syspm_cb_flow in \ref group_syspm_cb_config_consideration
+* to learn about how the SysPm processes the callbacks.
+*
+* \subsection group_syspm_cb_config_consideration Callback Configuration Considerations
+*
+* \subsubsection group_syspm_cb_parameters Callback Function Parameters
+*
+* The <b>callbackParams</b> parameter of the callback function is a
+* \ref cy_stc_syspm_callback_params_t structure. The second parameter
+* (<b>mode</b>) is for internal use. In the example code we used a
+* dummy value CY_SYSPM_CHECK_READY to eliminate compilation errors associated
+* with the enumeration. The driver sets the <b>mode</b> field to the correct
+* value when calling the callback functions (the mode is referred to as step in
+* the \ref group_syspm_cb_function_implementation). The callback function reads
+* the value and executes code based on the mode set by the SysPm driver.
+* The <b>base</b> and <b>context</b> fields are optional and can be NULL.
+* Some drivers require a base hardware address and context to store information
+* about the mode transition. If your callback routine requires access to the
+* driver registers or context, provide those values
+* (see <a href="..\..\pdl_user_guide.pdf">PDL Design</a> section
+* to learn about Base Hardware Address). Be aware of MISRA warnings if these
+* parameters are NULL.
+*
+* \subsubsection group_syspm_cb_structures Callback Function Structure
+* For each callback, provide a \ref cy_stc_syspm_callback_t structure. Some
+* fields in this structure are maintained by the driver. Use NULL for
+* cy_stc_syspm_callback_t.prevItm and cy_stc_syspm_callback_t.nextItm.
+* Driver uses these fields to build a linked list of callback functions.
+* The value of cy_stc_syspm_callback_t.order element is used to define the order
+* how the callbacks are put into linked list, and sequentially, how the
+* callbacks are executed. See \ref group_syspm_cb_registering section.
+*
+* \warning The Cy_SysPm_RegisterCallback() function stores a pointer to the
+* cy_stc_syspm_callback_t structure. Do not modify elements of the
+* cy_stc_syspm_callback_t structure after the callback is registered.
+* You are responsible for ensuring that the structure remains in scope.
+* Typically the structure is declared as a global or static variable, or as a
+* local variable in the main() function.
+*
+* \subsubsection group_syspm_cb_function_implementation Callback Function Implementation
+*
+* Every callback function should handle four possible steps (referred to as
+* "mode") defined in \ref cy_en_syspm_callback_mode_t :
+* * CY_SYSPM_CHECK_READY - Check if ready to enter a power mode.
+* * CY_SYSPM_BEFORE_TRANSITION - The actions to be done before entering
+* the low power mode.
+* * CY_SYSPM_AFTER_TRANSITION - The actions to be done after exiting the
+* low power mode.
+* * CY_SYSPM_CHECK_FAIL - Roll back any actions performed in the callback
+* executed previously with CY_SYSPM_CHECK_READY.
+*
+* A callback function can skip steps (see \ref group_syspm_skip_callback_modes).
+* In our example myDeepSleep1 and myDeepSleep2 callbacks do nothing while
+* entering the low power mode (skip on CY_SYSPM_BEFORE_TRANSITION). If there is
+* anything preventing low power mode entry - return CY_SYSPM_FAIL in response to
+* CY_SYSPM_CHECK_READY in your callback implementation. Note that the callback
+* should return CY_SYSPM_FAIL only in response to CY_SYSPM_CHECK_READY. The
+* callback function should always return CY_SYSPM_PASS for other modes:
+* CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION
+* (see \ref group_syspm_cb_flow).
+*
+* \subsubsection group_syspm_cb_flow Callbacks Execution Flow
+*
+* This section explains what happens during a power transition, when callbacks
+* are implemented and set up correctly. The following discussion assumes:
+* * All required callback functions are defined and implemented
+* * All cy_stc_syspm_callback_t structures are filled with required values
+* * All callbacks are successfully registered
+*
+* User calls one of the power mode transition functions: \ref Cy_SysPm_CpuEnterSleep(),
+* \ref Cy_SysPm_CpuEnterDeepSleep(), \ref Cy_SysPm_SystemEnterUlp(),
+* \ref Cy_SysPm_SystemEnterLp(), or \ref Cy_SysPm_SystemEnterHibernate().
+* It calls each callback with the mode set to CY_SYSPM_CHECK_READY. This
+* triggers execution of the code for that mode inside of each user callback.
+*
+* The intent of CY_SYSPM_CHECK_READY is to only signal if the resources is ready
+* to transition. Ideally, no transition changes should be made at this time.
+* In some cases a small change may be required. For example a communication
+* resource callback may set a flag telling firmware not to start any new
+* transition.
+
+* If that process is successful for all callbacks, then
+* \ref Cy_SysPm_ExecuteCallback() calls each callback with the mode set to
+* CY_SYSPM_BEFORE_TRANSITION. This triggers execution of the code for that mode
+* inside each user callback. We then enter the low power mode after all callback
+* are executed.
+*
+* When exiting the low power mode, the SysPm driver executes
+* \ref Cy_SysPm_ExecuteCallback() again. This time it calls each callback in
+* reverse order, with the mode set to CY_SYSPM_AFTER_TRANSITION. This triggers
+* execution of the code for that mode inside each user callback. The final
+* execution of callbacks depends on the low power mode in which callbacks were
+* called:
+* * For CPU Sleep or Deep Sleep power modes, the CY_SYSPM_AFTER_TRANSITION mode
+* is called after the CPU wakes from Sleep or Deep Sleep.
+* * For system Hibernate, the CY_SYSPM_AFTER_TRANSITION mode is not executed
+* because the device reboots after the wakeup from the Hibernate.
+* * For system LP and ULP modes, after the CY_SYSPM_AFTER_TRANSITION mode was
+* called the system remains in the new power mode: LP or ULP.
+*
+* A callback can return CY_SYSPM_FAIL only while executing the
+* CY_SYSPM_CHECK_READY mode. If that happens, then the remaining callbacks are
+* not executed. Any callbacks that have already executed are called again, in
+* reverse order, with CY_SYSPM_CHECK_FAIL. This allows the system to return to
+* the previous state. If a callback returns a fail then any of the functions
+* (\ref Cy_SysPm_CpuEnterSleep(), \ref Cy_SysPm_CpuEnterDeepSleep(),
+* \ref Cy_SysPm_SystemEnterUlp(), \ref Cy_SysPm_SystemEnterLp(), or
+* \ref Cy_SysPm_SystemEnterHibernate()) that attempt to switch the device into
+* a low power mode will also return CY_SYSPM_FAIL.
+*
+* Callbacks that reconfigure global resources, such as clock frequencies,
+* should be registered last. They then modify global resources as the final
+* step before entering the low power mode, and restore those resources first,
+* as the system returns from low power mode.
+*
+* \subsubsection group_syspm_cb_registering Callback Registering
+* While registration the callback is put into the linked list. The
+* place where the callback structure is put into the linked list is based on
+* cy_stc_syspm_callback_t.order. The callback with the lowest
+* cy_stc_syspm_callback_t.order value will be placed at the beginning of linked
+* list. The callback with the highest cy_stc_syspm_callback_t.order value will
+* be placed at the end of the linked list.
+* If there is already a callback structure in the linked list with the same
+* cy_stc_syspm_callback_t.order value as you attend to register, then your
+* callback will be placed right after such a callback.
+*
+* Such a registration order defines how the callbacks are executed:
+* * Callbacks with the lower cy_stc_syspm_callback_t.order are executed first
+* when entering into low power and last when exiting from low power.
+* * Callbacks with the higher cy_stc_syspm_callback_t.order are executed last
+* when entering into low power and first when exiting from low power.
+*
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_RegisterCallback
+*
+* Callbacks with equal cy_stc_syspm_callback_t.order values are
+* registered in the same order as they are registered:
+* \image html syspm_register_eq.png
+
+* Callbacks with a different cy_stc_syspm_callback_t.order value will be
+* stored based on the cy_stc_syspm_callback_t.order value, with no matter when
+* they when registered:
+*
+* \image html syspm_register_dif.png
+*
+* This can be useful to ensure that system resources (clock dividers, etc) are
+* changed right before entering low power mode and immediately after exiting
+* from low power.
+*
+* \subsubsection group_syspm_cb_unregistering Callback Unregistering
+*
+* Unregistering the callback might be useful when you need to dynamically manage
+* the callbacks.
+*
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_UnregisterCallback
+* The callback structures after myDeepSleep2 callback is unregistered:
+* \image html syspm_unregistration.png
+*
+* \section group_syspm_definitions Definitions
+*
+* <table class="doxtable">
+* <tr>
+* <th>Term</th>
+* <th>Definition</th>
+* </tr>
+*
+* <tr>
+* <td>LDO</td>
+* <td>Low dropout linear regulator. The functions that manage this
+* block are grouped as \ref group_syspm_functions_ldo under
+* \ref group_syspm_functions_core_regulators</td>
+* </tr>
+*
+* <tr>
+* <td>SIMO Buck</td>
+* <td>Single inductor multiple Output Buck regulator, referred as
+* "Buck regulator" throughout the documentation. The functions that
+* manage this block are grouped as \ref group_syspm_functions_buck under
+* \ref group_syspm_functions_core_regulators</td>
+* </tr>
+*
+* <tr>
+* <td>SISO Buck</td>
+* <td>Single inductor single output Buck regulator, referred as
+* "Buck regulator" throughout the documentation. The functions that
+* manage this block are grouped as \ref group_syspm_functions_buck under
+* \ref group_syspm_functions_core_regulators</td>
+* </tr>
+
+* <tr>
+* <td>PMIC</td>
+* <td>Power management integrated circuit. The functions that manage this
+* block are grouped as \ref group_syspm_functions_pmic</td>
+* </tr>
+*
+* <tr>
+* <td>LP</td>
+* <td>System low power mode. See the \ref group_syspm_switching_into_lp
+* section for details.</td>
+* </tr>
+*
+* <tr>
+* <td>ULP</td>
+* <td>System ultra low power mode. See the
+* \ref group_syspm_switching_into_ulp section for details.</td>
+* </tr>
+* </table>
+*
+* \section group_syspm_section_more_information More Information
+* For more information on the SysPm driver,
+* refer to the technical reference manual (TRM).
+*
+* \section group_syspm_MISRA MISRA-C Compliance
+* The SysPm driver does not have any specific deviations.
+*
+* \section group_syspm_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>4.40</td>
+* <td>
+* Fixed \ref Cy_SysPm_LdoSetVoltage(), \ref Cy_SysPm_BuckEnable(), and
+* \ref Cy_SysPm_BuckSetVoltage1() functions. Corrected the sequence for
+* setting the RAM trim value. This behavior is applicable for all
+* devices, except CY8C6xx6 and CY8C6xx7.
+* </td>
+* <td>
+* For all devices, except CY8C6xx6 and CY8C6xx7, the trim
+* sequence was setting incorrect trim values for RAM.
+* This could cause a CPU hard fault.
+* </td>
+* </tr>
+* <tr>
+* <td>4.30</td>
+* <td>
+* Corrected the \ref Cy_SysPm_CpuEnterDeepSleep() function.
+* Removed early access to flash values after system Deep Sleep, when
+* flash is not ready to be used. Now the \ref Cy_SysPm_CpuEnterDeepSleep()
+* function does not access flash until the flash is ready.
+* This behavior is applicable only on multi-CPU devices CY8C6xx6 and
+* CY8C6xx7.
+* </td>
+* <td>
+* For CY8C6xx6 and CY8C6xx7 early access to flash values after
+* system Deep Sleep could potentially cause hard fault.
+* Now after system Deep Sleep only ram values are used before
+* flash is ready.
+* </td>
+* </tr>
+* <tr>
+* <td rowspan="3">4.20</td>
+* <td>Updated the \ref Cy_SysPm_RegisterCallback() function.
+* Added a new element to callback structure -
+* cy_stc_syspm_callback_t.order</td>
+* <td>Enhanced the mechanism of callbacks registration and execution. Now
+* callbacks can be ordered during registration. This means the
+* execution flow now is based on cy_stc_syspm_callback_t.order.
+* For more details, see the \ref group_syspm_cb_registering section. </td>
+* </tr>
+* <tr>
+* <td>Updated \ref group_syspm_cb section.
+* Added \ref group_syspm_cb_registering section</td>
+* <td>Added explanations how to use updated callbacks registration
+* mechanism. </td>
+* </tr>
+* <tr>
+* <td>Added new function \ref Cy_SysPm_GetFailedCallback()</td>
+* <td>Added new functionality to support callback debugging</td>
+* </tr>
+* <tr>
+* <td>4.10.1</td>
+* <td>
+* Updated the Cy_SysPm_BackupEnableVoltageMeasurement() description
+* </td>
+* <td>
+* Changed the scale number from 40% to 10% to correctly reflect a real value.
+* </td>
+* </tr>
+* <tr>
+* <td rowspan="3">4.10</td>
+* <td>Updated the \ref Cy_SysPm_CpuEnterDeepSleep() function.</td>
+* <td>
+* Corrected the mechanism for saving/restoring not retained UDB
+* registers in the Cy_SysPm_CpuEnterDeepSleep() function.
+*
+* Now, the \ref Cy_SysPm_CpuEnterDeepSleep() function does not put CM0+ CPU
+* into Deep Sleep and returns \ref CY_SYSPM_SYSCALL_PENDING status, if a
+* syscall operation is pending. This behavior is applicable on multi-CPU
+* devices except CY8C6xx6 and CY8C6xx7.
+* </td>
+* </tr>
+* <tr>
+* <td>Updated the \ref Cy_SysPm_CpuEnterSleep() function.</td>
+* <td>Removed the redundant second call of the WFE() instruction on CM4 CPU.
+* This change is applicable for all devices except CY8C6xx6,
+* CY8C6xx7.
+* </td>
+* </tr>
+* <tr>
+* <td>Added a new \ref CY_SYSPM_SYSCALL_PENDING return status. </td>
+* <td>Expanded driver return statuses for indicating new possible events in
+* the driver.
+* </td>
+* </tr>
+* </tr>
+* <tr>
+* <td rowspan="6">4.0</td>
+* <td>
+* Flattened the organization of the driver source code into the single
+* source directory and the single include directory.
+* </td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>
+* Changed power modes names. See \ref group_syspm_system_power_modes.
+*
+* Renamed the following functions:
+* - Cy_SysPm_Sleep to Cy_SysPm_CpuEnterSleep
+* - Cy_SysPm_DeepSleep to Cy_SysPm_CpuEnterDeepSleep
+* - Cy_SysPm_Hibernate to Cy_SysPm_SystemEnterHibernate
+* - Cy_SysPm_SleepOnExit to Cy_SysPm_CpuSleepOnExit
+* - Cy_SysPm_EnterLowPowerMode to Cy_SysPm_SystemSetMinRegulatorCurrent
+* - Cy_SysPm_ExitLowPowerMode to Cy_SysPm_SystemSetNormalRegulatorCurrent
+* - Cy_SysPm_IsLowPower to Cy_SysPm_IsSystemUlp
+*
+* For all renamed functions, added BWC macros to simplify migration.
+* </td>
+* <td>Device power modes simplification</td>
+* </tr>
+* <tr>
+* <td>
+* Added the following functions:
+* - Cy_SysPm_LdoSetMode
+* - Cy_SysPm_LdoGetMode
+* - Cy_SysPm_WriteVoltageBitForFlash
+* - Cy_SysPm_SaveRegisters
+* - Cy_SysPm_RestoreRegisters
+* - Cy_SysPm_CpuSendWakeupEvent
+* - Cy_SysPm_SystemIsMinRegulatorCurrentSet
+* - Cy_SysPm_SystemEnterLp
+* - Cy_SysPm_SystemEnterUlp
+* - Cy_SysPm_IsSystemLp
+* </td>
+* <td>Added new functionality to configure device power modes</td>
+* </tr>
+* <tr>
+* <td>
+* Callback mechanism changes:
+* - Removed the limitation for numbers of registered callbacks. Previously it
+* was possible to register up to 32 callbacks. Now the maximum registered
+* callbacks is not limited by the SysPm driver.
+* - Internal enhancement in callback execution flow.
+* - <b>Changes with BWC issues</b>:
+* -# Removed the <b>mode</b> element from cy_stc_syspm_callback_params_t
+* structure. Now this element is a separate parameter in the
+* callback function.
+* -# Changed the interface of the callback function,
+* added the cy_en_syspm_callback_mode_t mode parameter:
+* - was cy_en_syspm_status_t FuncName (cy_stc_syspm_callback_params_t *callbackParams);
+* - now cy_en_syspm_status_t FuncName (cy_stc_syspm_callback_params_t *callbackParams,
+* cy_en_syspm_callback_mode_t mode);
+* </td>
+* <td>Callback mechanism enhancements</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>Added \ref group_syspm_migration_guide_for_syspm_4_0.</td>
+* <td>Provided a guidance for migrating to the latest SysPm driver version</td>
+* </tr>
+* <tr>
+* <td rowspan="2">3.0</td>
+* <td>Removed three functions:
+* - Cy_SysPm_Cm4IsLowPower
+* - Cy_SysPm_Cm0IsLowPower
+* - Cy_SysPm_IoFreeze
+*
+* Removed the following macros:
+* - CY_SYSPM_STATUS_CM0_LOWPOWER
+* - CY_SYSPM_STATUS_CM4_LOWPOWER
+* </td>
+* <td>
+* Removed the two functions Cy_SysPm_Cm4IsLowPower,
+* Cy_SysPm_Cm0IsLowPower because low power mode is related to the
+* device and not to the CPU.
+* The function Cy_SysPm_IsSystemUlp must be used instead of these two
+* functions.
+*
+* Removed Cy_SysPm_IoFreeze because the are no known use cases with IOs
+* freeze in power modes, except Hibernate. In Hibernate power mode, the
+* IOs are frozen automatically.
+* </td>
+* </tr>
+* <tr>
+* <td>
+* Corrected the syspm callback mechanism behavior. Now callbacks with
+* CY_SYSPM_AFTER_TRANSITION mode are executed from the last registered
+* to the first registered. Previously callbacks with
+* CY_SYSPM_AFTER_TRANSITION mode were executed from last executed to
+* the first registered.
+* </td>
+* <td>Corrected the syspm callbacks execution sequence</td>
+* </tr>
+* <tr>
+* <td>2.21</td>
+* <td>Removed saving/restoring the SysClk measurement counters while
+* in Deep Sleep routine
+* </td>
+* <td>Removed possible corruption of SysClk measurement counters if the
+* core wakes up from the Deep Sleep.
+* </td>
+* </tr>
+* <tr>
+* <td>2.20</td>
+* <td> \n
+* * Added support for changing core voltage when the protection context
+* is other that zero. Such support is available only for devices
+* that support modifying registers via syscall.
+*
+* * For preproduction PSoC 6 devices the changing core voltage
+* is prohibited when the protection context is other than zero.
+*
+* * Updated the following functions. They now have a
+* \ref cy_en_syspm_status_t return value and use a syscall:
+* - Cy_SysPm_LdoSetVoltage
+* - Cy_SysPm_BuckSetVoltage1
+* - Cy_SysPm_BuckEnable
+*
+* No backward compatibility issues.
+*
+* * Added new CY_SYSPM_CANCELED element in
+* the \ref cy_en_syspm_status_t.
+*
+* * Documentation updates.
+*
+* * Added warning that
+* Cy_SysPm_PmicDisable(CY_SYSPM_PMIC_POLARITY_LOW) is not
+* supported by hardware.
+* </td>
+* <td>Added support for changing the core voltage in protection context
+* higher than zero (PC > 0).
+*
+* Documentation update and clarification
+* </td>
+* </tr>
+* <tr>
+* <td>2.10</td>
+* <td> \n
+* * Changed names for all Backup, Buck-related functions, defines,
+* and enums
+* * Changed next power mode function names:
+* Cy_SysPm_EnterLowPowerMode
+* Cy_SysPm_ExitLpMode
+* Cy_SysPm_SetHibWakeupSource
+* Cy_SysPm_ClearHibWakeupSource
+* Cy_SysPm_GetIoFreezeStatus
+* * Changed following enumeration names:
+* cy_en_syspm_hib_wakeup_source_t
+* cy_en_syspm_simo_buck_voltage1_t
+* cy_en_syspm_simo_buck_voltage2_t
+* * Updated Power Modes documentation section
+* * Added Low Power Callback Managements section
+* * Documentation edits
+* </td>
+* <td> \n
+* * Improvements made based on usability feedback
+* * Documentation update and clarification
+* </td>
+* </tr>
+* <tr>
+* <td>2.0</td>
+* <td>Enhancement and defect fixes:
+* * Added input parameter(s) validation to all public functions
+* * Removed "_SysPm_" prefixes from the internal functions names
+* * Changed the type of elements with limited set of values, from
+* uint32_t to enumeration
+* * Enhanced syspm callback mechanism
+* * Added functions to control:
+* * Power supply for the Vddbackup
+* * Supercapacitor charge
+* * Vddbackup measurement by ADC
+* </td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \subsection group_syspm_migration_guide_for_syspm_4_0 Migration Guide: Moving to SysPm v4.0
+*
+* This section provides a guideline to migrate from v2.21 to v4.0 of the SysPm
+* driver.
+*
+* \subsubsection group_syspm_migration_into_4_0_intro Introduction
+*
+* If your application currently uses SysPm v2.21 APIs, you must
+* migrate to SysPm v4.0 so that your application continues to operate.
+*
+* Take a few minutes to review the following information:
+* - The APIs related to PSoC 6 \ref group_syspm_power_modes are changed. Old
+* power modes APIs function names are now deprecated and should not be used
+* in new applications.
+* - The \ref group_syspm_cb mechanism is changed. The mode element is removed
+* from cy_stc_syspm_callback_params_t structure. Now this element is a
+* separate parameter in the callback function.
+*
+* \subsubsection group_syspm_migration_into_4_0_names Migrating to new power modes APIs.
+* The table below shows the new APIs names that should be used in the
+* application instead of old names:
+*
+* <table class="doxtable">
+* <tr><th>SysPm v2.21 API name</th><th>SysPm v4.0 API name</th><th>Comment</th></tr>
+* <tr>
+* <td>Cy_SysPm_Sleep</td>
+* <td>\ref Cy_SysPm_CpuEnterSleep</td>
+* <td>Renamed, no functional changes</td>
+* </tr>
+* <tr>
+* <td>Cy_SysPm_DeepSleep</td>
+* <td>\ref Cy_SysPm_CpuEnterDeepSleep</td>
+* <td>Renamed, no functional changes</td>
+* </tr>
+* <tr>
+* <td>Cy_SysPm_Hibernate</td>
+* <td>\ref Cy_SysPm_SystemEnterHibernate</td>
+* <td>Renamed, no functional changes</td>
+* </tr>
+* <tr>
+* <td>Cy_SysPm_SleepOnExit</td>
+* <td>\ref Cy_SysPm_CpuSleepOnExit</td>
+* <td>Renamed, no functional changes</td>
+* </tr>
+* <tr>
+* <td>Cy_SysPm_IsLowPower</td>
+* <td>\ref Cy_SysPm_IsSystemUlp</td>
+* <td>Now this function checks whether the device is in ULP mode</td>
+* </tr>
+* <tr>
+* <td>Cy_SysPm_EnterLowPowerMode</td>
+* <td>\ref Cy_SysPm_SystemSetMinRegulatorCurrent</td>
+* <td>The low power active mode does not exist anymore.
+* The \ref group_syspm_system_reg_curr_mode is implemented instead </td>
+* </tr>
+* <tr>
+* <td>Cy_SysPm_ExitLowPowerMode</td>
+* <td>\ref Cy_SysPm_SystemSetNormalRegulatorCurrent</td>
+* <td>The low power active mode does not exist anymore.
+* The \ref group_syspm_system_reg_curr_mode is implemented instead</td>
+* </tr>
+* <tr>
+* <td>Cy_SysPm_Cm4IsLowPower</td>
+* <td>Removed</td>
+* <td>This function is removed because low power mode is related to the system
+* and not to the CPU</td>
+* </tr>
+* <tr>
+* <td>Cy_SysPm_Cm0IsLowPower</td>
+* <td>Removed</td>
+* <td>This function is removed because low power mode is related to the system
+* and not to the CPU</td>
+* </tr>
+* <tr>
+* <td>Cy_SysPm_IoFreeze</td>
+* <td>Removed</td>
+* <td>This function is removed because there are no known use cases to
+* freeze in power modes other than Hibernate</td>
+* </tr>
+* </table>
+*
+* In addition to renamed power modes APIs, the following defines and enum
+* elements names are changed:
+* <table class="doxtable">
+* <tr><th>SysPm v2.21 defines</th><th>SysPm v4.0 defines</th><th>Comment</th></tr>
+* <tr>
+* <td>CY_SYSPM_ENTER_LP_MODE</td>
+* <td>CY_SYSPM_ULP</td>
+* <td>The \ref cy_en_syspm_callback_type_t element is renamed to align
+* callback types names to new power modes names</td>
+* </tr>
+* <tr>
+* <td>CY_SYSPM_EXIT_LP_MODE</td>
+* <td>CY_SYSPM_LP</td>
+* <td>The \ref cy_en_syspm_callback_type_t element is renamed to align
+* callback types names to new power modes names</td>
+* <tr>
+* <td>CY_SYSPM_STATUS_SYSTEM_LOWPOWER</td>
+* <td>CY_SYSPM_STATUS_SYSTEM_ULP</td>
+* <td>Status define, renamed to align new power modes names
+* and abbreviations</td>
+* </tr>
+* </table>
+*
+* \subsubsection group_syspm_migration_into_4_0_callbacks Migrating to SysPm v4.0 callbacks
+*
+* Review this section if your application is using the syspm callback mechanism.
+*
+* To migrate to SysPm v4.0 callbacks you need to perform the following steps:
+* -# Remove mode element from all \ref cy_stc_syspm_callback_params_t
+* structures defined in your application. In SysPm v2.21 this structure is:
+* \code{.c}
+* cy_stc_syspm_callback_params_t deepSleepParam1 =
+* {
+* CY_SYSPM_CHECK_READY,
+* &HW1_address,
+* &context
+* };
+* \endcode
+*
+* In SysPm v4.0 this structure should be:
+* \code{.c}
+* cy_stc_syspm_callback_params_t deepSleepParam1 =
+* {
+* &HW1_address,
+* &context
+* };
+* \endcode
+* -# Update all defined syspm callback function prototypes to have two
+* parameters instead of one. The SysPm v2.21 callback function prototype is:
+* \code{.c}
+* cy_en_syspm_status_t Func1 (cy_stc_syspm_callback_params_t *callbackParams);
+* \endcode
+* The SysPm v4.0 callback function prototype should be:
+* \code{.c}
+* cy_en_syspm_status_t Func1 (cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
+* \endcode
+* -# Change the syspm callback function implementation to not use a mode
+* value as an element of the callbackParams structure, but, as separate
+* function parameter:
+* SysPm v2.21 callback function implementation:
+* \code{.c}
+* cy_en_syspm_status_t Func1(cy_stc_syspm_callback_params_t *callbackParams)
+* {
+* cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
+*
+* switch(callbackParams->mode)
+* {
+* case CY_SYSPM_CHECK_READY:
+* ...
+* }
+*
+* return (retVal);
+* }
+* \endcode
+* SysPm v4.0 callback function implementation:
+* \code{.c}
+* cy_en_syspm_status_t Func1(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode)
+* {
+* cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
+*
+* switch(mode)
+* {
+* case CY_SYSPM_CHECK_READY:
+* ...
+* }
+*
+* return (retVal);
+* }
+* \endcode
+* After the changes above are done, you have successfully migrated to SysPm v4.0.
+*
+* Do not forget to review newly added functionality for SysPm v4.0 in the
+* \ref group_syspm_changelog.
+
+* \defgroup group_syspm_macros Macros
+* \defgroup group_syspm_functions Functions
+* \{
+ \defgroup group_syspm_functions_general General
+* \defgroup group_syspm_functions_power Power Modes
+* \defgroup group_syspm_functions_power_status Power Status
+* \defgroup group_syspm_functions_iofreeze I/Os Freeze
+* \defgroup group_syspm_functions_core_regulators Core Voltage Regulation
+* \{
+* \defgroup group_syspm_functions_ldo LDO
+* \defgroup group_syspm_functions_buck Buck
+* \}
+* \defgroup group_syspm_functions_pmic PMIC
+* \defgroup group_syspm_functions_backup Backup Domain
+* \defgroup group_syspm_functions_callback Low Power Callbacks
+* \}
+* \defgroup group_syspm_data_structures Data Structures
+* \defgroup group_syspm_data_enumerates Enumerated Types
+*/
+
+#if !defined (CY_SYSPM_H)
+#define CY_SYSPM_H
+
+#include <stdbool.h>
+#include <stddef.h>
+
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Register Constants
+*******************************************************************************/
+
+/**
+* \addtogroup group_syspm_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_SYSPM_DRV_VERSION_MAJOR 4
+
+/** Driver minor version */
+#define CY_SYSPM_DRV_VERSION_MINOR 40
+
+/** SysPm driver identifier */
+#define CY_SYSPM_ID (CY_PDL_DRV_ID(0x10U))
+
+
+/*******************************************************************************
+* Internal Defines
+*******************************************************************************/
+
+/** \cond INTERNAL */
+
+/* Macro to validate parameters in Cy_SysPm_SetHibernateWakeupSource() and for Cy_SysPm_ClearHibernateWakeupSource() function */
+#define CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource) (0UL == ((wakeupSource) & \
+ ((uint32_t) ~(CY_SYSPM_HIB_WAKEUP_SOURSE_MASK))))
+
+/* Macro to validate parameters in Cy_SysPm_PmicDisable() function */
+#define CY_SYSPM_IS_POLARITY_VALID(polarity) (((polarity) == CY_SYSPM_PMIC_POLARITY_LOW) || \
+ ((polarity) == CY_SYSPM_PMIC_POLARITY_HIGH))
+
+/* Macro to validate parameters in Cy_SysPm_BuckSetVoltage1() function */
+#define CY_SYSPM_IS_BUCK_VOLTAGE1_VALID(voltage) (((voltage) == CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT1_VOLTAGE_1_1V))
+
+/* Macro to validate parameters in Cy_SysPm_BuckSetVoltage2() function */
+#define CY_SYSPM_IS_BUCK_VOLTAGE2_VALID(voltage) (((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_15V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_2V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_25V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_3V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_35V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_4V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_45V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_5V))
+
+/* Macro to validate parameters in Cy_SysPm_BuckIsOutputEnabled() function */
+#define CY_SYSPM_IS_BUCK_OUTPUT_VALID(output) (((output) == CY_SYSPM_BUCK_VBUCK_1) || \
+ ((output) == CY_SYSPM_BUCK_VRF))
+
+/* Macro to validate parameters in Cy_SysPm_LdoSetVoltage() function */
+#define CY_SYSPM_IS_LDO_VOLTAGE_VALID(voltage) (((voltage) == CY_SYSPM_LDO_VOLTAGE_0_9V) || \
+ ((voltage) == CY_SYSPM_LDO_VOLTAGE_1_1V))
+
+/* Macro to validate parameters in Cy_SysPm_ExecuteCallback() function */
+#define CY_SYSPM_IS_CALLBACK_TYPE_VALID(type) (((type) == CY_SYSPM_SLEEP) || \
+ ((type) == CY_SYSPM_DEEPSLEEP) || \
+ ((type) == CY_SYSPM_HIBERNATE) || \
+ ((type) == CY_SYSPM_ULP) || \
+ ((type) == CY_SYSPM_LP))
+
+/* Macro to validate parameters in Cy_SysPm_ExecuteCallback() function */
+#define CY_SYSPM_IS_CALLBACK_MODE_VALID(mode) (((mode) == CY_SYSPM_CHECK_READY) || \
+ ((mode) == CY_SYSPM_CHECK_FAIL) || \
+ ((mode) == CY_SYSPM_BEFORE_TRANSITION) || \
+ ((mode) == CY_SYSPM_AFTER_TRANSITION))
+
+/* Macro to validate parameters in Cy_SysPm_CpuEnterSleep() and for Cy_SysPm_CpuEnterDeepSleep() function */
+#define CY_SYSPM_IS_WAIT_FOR_VALID(waitFor) (((waitFor) == CY_SYSPM_WAIT_FOR_INTERRUPT) || \
+ ((waitFor) == CY_SYSPM_WAIT_FOR_EVENT))
+
+/* Macro to validate parameters in Cy_SysPm_BackupSetSupply() function */
+#define CY_SYSPM_IS_VDDBACKUP_VALID(vddBackControl) (((vddBackControl) == CY_SYSPM_VDDBACKUP_DEFAULT) || \
+ ((vddBackControl) == CY_SYSPM_VDDBACKUP_VBACKUP))
+
+/* Macro to validate parameters in Cy_SysPm_BackupSuperCapCharge() function */
+#define CY_SYSPM_IS_SC_CHARGE_KEY_VALID(key) (((key) == CY_SYSPM_SC_CHARGE_ENABLE) || \
+ ((key) == CY_SYSPM_SC_CHARGE_DISABLE))
+
+/* Macro to validate parameters in Cy_SysPm_LdoSetMode() function */
+#define CY_SYSPM_IS_LDO_MODE_VALID(key) (((mode) == CY_SYSPM_LDO_MODE_DISABLED) || \
+ ((mode) == CY_SYSPM_LDO_MODE_NORMAL) || \
+ ((mode) == CY_SYSPM_LDO_MODE_MIN))
+
+/* Macro to validate parameters in Cy_SysPm_WriteVoltageBitForFlash() function */
+#define CY_SYSPM_IS_BIT_FOR_FLASH_VALID(value) (((value) == CY_SYSPM_FLASH_VOLTAGE_BIT_ULP) || \
+ ((value) == CY_SYSPM_FLASH_VOLTAGE_BIT_LP))
+
+/** The internal define of the unlock value for the PMIC functions */
+#define CY_SYSPM_PMIC_UNLOCK_KEY (0x3AU)
+
+/** The internal define of the first wakeup pin bit used in the
+* Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_HIB_WAKEUP_PIN0_POS (1UL)
+
+/** The internal define of the second wakeup pin bit
+* used in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_HIB_WAKEUP_PIN1_POS (2UL)
+
+/**
+* The internal define of the first LPComparator bit
+* used in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_HIB_WAKEUP_LPCOMP0_POS (4UL)
+
+/**
+* The internal define for the second LPComparator bit
+* used in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_HIB_WAKEUP_LPCOMP1_POS (8UL)
+
+/**
+* The internal define of the first LPComparator value
+* used in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK (_VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, CY_SYSPM_HIB_WAKEUP_LPCOMP0_POS))
+
+/**
+* The internal define of the second LPComparator value
+* used in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK (_VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, CY_SYSPM_HIB_WAKEUP_LPCOMP1_POS))
+
+/**
+* The internal define of the first wake-up pin value
+* used in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_HIB_WAKEUP_PIN0_MASK (_VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, CY_SYSPM_HIB_WAKEUP_PIN0_POS))
+
+/**
+* The internal define of the second wake-up pin value used
+* in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_HIB_WAKEUP_PIN1_MASK (_VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, CY_SYSPM_HIB_WAKEUP_PIN1_POS))
+
+/** The internal define for the first LPComparator polarity configuration */
+#define CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK \
+ (_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, CY_SYSPM_HIB_WAKEUP_LPCOMP0_POS))
+
+/** The internal define for the second LPComparator polarity configuration */
+#define CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK \
+ (_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, CY_SYSPM_HIB_WAKEUP_LPCOMP1_POS))
+
+/** The internal define for the first wake-up pin polarity configuration */
+#define CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK \
+ (_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, CY_SYSPM_HIB_WAKEUP_PIN0_POS))
+
+/** The internal define for the second wake-up pin polarity configuration */
+#define CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK \
+ (_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, CY_SYSPM_HIB_WAKEUP_PIN1_POS))
+
+/* Internal macro of all possible wakeup sources from hibernate power mode */
+#define CY_SYSPM_HIB_WAKEUP_SOURSE_MASK (CY_SYSPM_HIBERNATE_LPCOMP0_HIGH | CY_SYSPM_HIBERNATE_LPCOMP1_HIGH |\
+ CY_SYSPM_HIBERNATE_RTC_ALARM | CY_SYSPM_HIBERNATE_WDT |\
+ CY_SYSPM_HIBERNATE_PIN0_HIGH | CY_SYSPM_HIBERNATE_PIN1_HIGH)
+
+/* The mask for low power modes the power circuits (POR/BOD, Bandgap
+* reference, Reference buffer, Current reference) when active core regulator is
+* LDO
+*/
+#define CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_LDO_MASK (SRSS_PWR_CTL_LINREG_LPMODE_Msk | CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_BUCK_MASK)
+
+/* The mask for low power modes the power circuits (POR/BOD, Bandgap
+* reference, Reference buffer, Current reference) when active core regulator is
+* Buck
+*/
+#define CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_BUCK_MASK (SRSS_PWR_CTL_PORBOD_LPMODE_Msk |\
+ SRSS_PWR_CTL_ACT_REF_DIS_Msk |\
+ SRSS_PWR_CTL_VREFBUF_LPMODE_Msk |\
+ SRSS_PWR_CTL_IREF_LPMODE_Msk)
+
+/** \endcond */
+
+/**
+* \defgroup group_syspm_return_status The Power Mode Status Defines
+* \{
+* Defines for the CPU and system power modes status.
+*/
+
+/** The CM4 is in CPU Active mode */
+#define CY_SYSPM_STATUS_CM4_ACTIVE (0x01U)
+
+/** The CM4 is in CPU Sleep mode */
+#define CY_SYSPM_STATUS_CM4_SLEEP (0x02U)
+
+/** The CM4 is in CPU Deep Sleep mode */
+#define CY_SYSPM_STATUS_CM4_DEEPSLEEP (0x04U)
+
+/** The CM0p is CPU Active mode */
+#define CY_SYSPM_STATUS_CM0_ACTIVE ((uint32_t) 0x01U << 8U)
+
+/** The CM0p is in CPU Sleep mode */
+#define CY_SYSPM_STATUS_CM0_SLEEP ((uint32_t) 0x02U << 8U)
+
+/** The CM0p is in CPU Deep Sleep mode */
+#define CY_SYSPM_STATUS_CM0_DEEPSLEEP ((uint32_t) 0x04U << 8U)
+
+/** The system is Low Power mode */
+#define CY_SYSPM_STATUS_SYSTEM_LP (0x80U)
+
+/** The system is in Ultra Low Power mode */
+#define CY_SYSPM_STATUS_SYSTEM_ULP ((uint32_t) 0x08U << 8U)
+
+/** \} group_syspm_return_status */
+
+/** \} group_syspm_macros */
+
+/*******************************************************************************
+* Configuration Structures
+*******************************************************************************/
+
+/**
+* \addtogroup group_syspm_data_enumerates
+* \{
+*/
+
+/** The SysPm function return value status definitions. */
+typedef enum
+{
+ CY_SYSPM_SUCCESS = 0x0U, /**< Successful. */
+ CY_SYSPM_BAD_PARAM = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< One or more invalid parameters. */
+ CY_SYSPM_TIMEOUT = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0x02U, /**< A time-out occurred. */
+ CY_SYSPM_INVALID_STATE = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0x03U, /**< The operation is not setup or is in an
+ improper state. */
+ CY_SYSPM_CANCELED = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0x04U, /**< Operation canceled. */
+ CY_SYSPM_SYSCALL_PENDING = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0x05U, /**< Canceled due syscall operation pending. */
+ CY_SYSPM_FAIL = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0xFFU /**< Unknown failure. */
+} cy_en_syspm_status_t;
+
+/**
+* This enumeration is used to initialize the functions wait action. The wait actions can be -
+* an interrupt or an event. Refer to the CMSIS for WFE and WFI instruction explanations.
+*/
+typedef enum
+{
+ CY_SYSPM_WAIT_FOR_INTERRUPT, /**< Wait for an interrupt. */
+ CY_SYSPM_WAIT_FOR_EVENT /**< Wait for an event. */
+} cy_en_syspm_waitfor_t;
+
+/** This enumeration is used to configure wakeup sources for the System Hibernate
+* power mode.
+*/
+typedef enum
+{
+ /** Wake on a low logic level for the LPComp0. */
+ CY_SYSPM_HIBERNATE_LPCOMP0_LOW = CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK,
+
+ /** Wake on a high logic level for the LPComp0. */
+ CY_SYSPM_HIBERNATE_LPCOMP0_HIGH = CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK | CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK,
+
+ /** Wake on a low logic level for the LPComp1. */
+ CY_SYSPM_HIBERNATE_LPCOMP1_LOW = CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK,
+
+ /** Wake on a high logic level for the LPComp1. */
+ CY_SYSPM_HIBERNATE_LPCOMP1_HIGH = CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK | CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK,
+
+ /** Configure the RTC alarm as wakeup source. */
+ CY_SYSPM_HIBERNATE_RTC_ALARM = SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk,
+
+ /** Configure the WDT interrupt as wakeup source. */
+ CY_SYSPM_HIBERNATE_WDT = SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk,
+
+ /** Configure a low logic level for the first wakeup-pin. See device datasheet for specific pin. */
+ CY_SYSPM_HIBERNATE_PIN0_LOW = CY_SYSPM_HIB_WAKEUP_PIN0_MASK,
+
+ /** Configure a high logic level for the first wakeup-pin. See device datasheet for specific pin.*/
+ CY_SYSPM_HIBERNATE_PIN0_HIGH = CY_SYSPM_HIB_WAKEUP_PIN0_MASK | CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK,
+
+ /** Configure a low logic level for the second wakeup-pin. See device datasheet for specific pin.*/
+ CY_SYSPM_HIBERNATE_PIN1_LOW = CY_SYSPM_HIB_WAKEUP_PIN1_MASK,
+
+ /** Configure a high logic level for the second wakeup-pin. See device datasheet for specific pin.*/
+ CY_SYSPM_HIBERNATE_PIN1_HIGH = CY_SYSPM_HIB_WAKEUP_PIN1_MASK | CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK
+} cy_en_syspm_hibernate_wakeup_source_t;
+
+/** This enumeration is used to select LDO regulator output voltage. */
+typedef enum
+{
+ CY_SYSPM_LDO_VOLTAGE_ULP = 0U, /**< System ULP nominal LDO voltage.
+ See device datasheet for specific voltage. */
+ CY_SYSPM_LDO_VOLTAGE_LP = 1U, /**< System LP nominal LDO voltage.
+ See device datasheet for specific voltage. */
+ CY_SYSPM_LDO_VOLTAGE_0_9V = 0U, /**< 0.9 V nominal LDO voltage */
+ CY_SYSPM_LDO_VOLTAGE_1_1V = 1U /**< 1.1 V nominal LDO voltage */
+} cy_en_syspm_ldo_voltage_t;
+
+/** This enumeration is used to select the LDO regulator operating mode. */
+typedef enum
+{
+ CY_SYSPM_LDO_MODE_DISABLED = 0U, /**< Disables the LDO. */
+ CY_SYSPM_LDO_MODE_NORMAL = 1U, /**< Sets normal current mode. See device datasheet for
+ specific maximum current limit. */
+ CY_SYSPM_LDO_MODE_MIN = 2U /**< Sets minimum current mode. See device datasheet for
+ specific current limit. */
+} cy_en_syspm_ldo_mode_t;
+
+/**
+* This enumeration is used to select the output voltage for the Buck regulator output 1.
+*/
+typedef enum
+{
+ CY_SYSPM_BUCK_OUT1_VOLTAGE_ULP = 0x02U, /**< System ULP nominal Buck voltage.
+ See device datasheet for specific voltage. */
+ CY_SYSPM_BUCK_OUT1_VOLTAGE_LP = 0x05U, /**< LP nominal Buck voltage.
+ See device datasheet for specific voltage. */
+ CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V = 0x02U, /**< 0.9 V nominal Buck voltage */
+ CY_SYSPM_BUCK_OUT1_VOLTAGE_1_1V = 0x05U /**< 1.1 V nominal Buck voltage */
+} cy_en_syspm_buck_voltage1_t;
+
+/** This enumeration is used to select the Buck regulator outputs. */
+typedef enum
+{
+ CY_SYSPM_BUCK_VBUCK_1 = 0x0U, /**< Buck output 1 Voltage (Vbuck1). Typically used to
+ supply the PSoC digital core logic. */
+ CY_SYSPM_BUCK_VRF /**< Buck out 2 Voltage (Vbuckrf). Typically used to
+ supply the BLE radio logic. */
+} cy_en_syspm_buck_out_t;
+
+/**
+* This enumeration is used to select the output voltage for the Buck regulator
+* output 2, which can source the BLE radio.
+*/
+typedef enum
+{
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_15V = 0U, /**< 1.15 V nominal voltage. */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_2V = 1U, /**< 1.20 V nominal voltage. */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_25V = 2U, /**< 1.25 V nominal voltage. */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_3V = 3U, /**< 1.3 V nominal voltage. */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_35V = 4U, /**< 1.35 V nominal voltage. */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_4V = 5U, /**< 1.4 V nominal voltage. */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_45V = 6U, /**< 1.45 V nominal voltage. */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_5V = 7U /**< 1.5 V nominal voltage. */
+} cy_en_syspm_buck_voltage2_t;
+
+/**
+* This enumeration is used to set the polarity for the PMIC input. The PMIC output is
+* automatically enabled when the configured polarity of the PMIC input and the logic level
+* driven to the pmic_wakeup_in pin match.
+*
+* \warning
+* Do not use CY_SYSPM_PMIC_POLARITY_LOW as it is not supported by hardware.
+*/
+typedef enum
+{
+ CY_SYSPM_PMIC_POLARITY_LOW = 0U, /**< Set active low logic level for the PMIC input. */
+ CY_SYSPM_PMIC_POLARITY_HIGH = 1U /**< Set active high logic level for the PMIC input. */
+} cy_en_syspm_pmic_wakeup_polarity_t;
+
+/** This enumeration selects Vbackup or Vddd to supply Vddbackup. */
+typedef enum
+{
+ CY_SYSPM_VDDBACKUP_DEFAULT = 0U, /**< Logic automatically selects Vddd if present or
+ Vbackup if Vddd is not present to supply Vddbackup */
+ CY_SYSPM_VDDBACKUP_VBACKUP = 2U /**< Sets only Vbackup to supply Vddbackup */
+} cy_en_syspm_vddbackup_control_t;
+
+/** This enumeration enables supercapacitor charging. */
+typedef enum
+{
+ CY_SYSPM_SC_CHARGE_ENABLE = 0x3CU, /**< Enables supercapacitor charging */
+ CY_SYSPM_SC_CHARGE_DISABLE = 0x00U /**< Disables supercapacitor charging */
+} cy_en_syspm_sc_charge_key_t;
+
+/** This enumeration configures the flash voltage bit for different system power modes. */
+typedef enum
+{
+ CY_SYSPM_FLASH_VOLTAGE_BIT_LP = 0U, /**< Set the flash voltage bit for system LP mode */
+ CY_SYSPM_FLASH_VOLTAGE_BIT_ULP = 1U, /**< Set the flash voltage bit for system ULP mode */
+} cy_en_syspm_flash_voltage_bit_t;
+
+/**
+* This enumeration is used to select the low power mode for which the
+* appropriate registered callback handler will be executed. For example,
+* the registered callback of the type CY_SYSPM_SLEEP will be executed while
+* switching into the Sleep power mode.
+*/
+typedef enum
+{
+ CY_SYSPM_SLEEP = 0U, /**< The Sleep enum callback type */
+ CY_SYSPM_DEEPSLEEP = 1U, /**< The Deep Sleep enum callback type */
+ CY_SYSPM_HIBERNATE = 2U, /**< The Hibernate enum callback type */
+ CY_SYSPM_LP = 3U, /**< The Low Power enum callback type */
+ CY_SYSPM_ULP = 4U /**< The Ultra Low Power enum callback type */
+} cy_en_syspm_callback_type_t;
+
+/** This enumeration specifies the associated callback mode. This enum defines the callback mode. */
+typedef enum
+{
+ CY_SYSPM_CHECK_READY = 0x01U, /**< Callbacks with this mode are executed before entering into the
+ low power mode. The purpose of his callback function is to check
+ if the device is ready to enter the low power mode. */
+ CY_SYSPM_CHECK_FAIL = 0x02U, /**< Callbacks with this mode are executed after the CY_SYSPM_CHECK_READY
+ callbacks execution returns CY_SYSPM_FAIL.
+ The callback with the CY_SYSPM_CHECK_FAIL mode should roll back the
+ actions performed in the previously executed callback with
+ CY_SYSPM_CHECK_READY */
+ CY_SYSPM_BEFORE_TRANSITION = 0x04U, /**< Callbacks with this mode are executed after the CY_SYSPM_CHECK_READY
+ callbacks execution returns CY_SYSPM_SUCCESS.
+ Performs the actions to be done before entering into the
+ low power mode. */
+ CY_SYSPM_AFTER_TRANSITION = 0x08U /**< Performs the actions to be done after exiting the low power mode
+ if entered. */
+} cy_en_syspm_callback_mode_t;
+
+/** \} group_syspm_data_enumerates */
+
+/**
+* \addtogroup group_syspm_macros
+* \{
+*/
+/**
+* \defgroup group_syspm_skip_callback_modes Defines to skip the callbacks modes
+* \{
+* Defines for the SysPm callbacks modes that can be skipped during execution.
+* For more information about callbacks modes, refer
+* to \ref cy_en_syspm_callback_mode_t.
+*/
+#define CY_SYSPM_SKIP_CHECK_READY (0x01U) /**< Define to skip check ready mode in the syspm callback */
+#define CY_SYSPM_SKIP_CHECK_FAIL (0x02U) /**< Define to skip check fail mode in the syspm callback */
+#define CY_SYSPM_SKIP_BEFORE_TRANSITION (0x04U) /**< Define to skip before transition mode in the syspm callback */
+#define CY_SYSPM_SKIP_AFTER_TRANSITION (0x08U) /**< Define to skip after transition mode in the syspm callback */
+/** \} group_syspm_skip_callback_modes */
+/** \} group_syspm_macros */
+
+/**
+* \addtogroup group_syspm_data_structures
+* \{
+*/
+
+/** The structure contains syspm callback parameters */
+typedef struct
+{
+ void *base; /**< Base address of a HW instance, matches name of the driver in
+ the API for the base address. Can be undefined if not required. Base address is not
+ required for the SysPm driver as the device has only one set of power modes */
+ void *context; /**< Context for the handler function. This item can be
+ skipped if not required. Can be undefined if not required. */
+
+} cy_stc_syspm_callback_params_t;
+
+/** The type for syspm callbacks */
+typedef cy_en_syspm_status_t (*Cy_SysPmCallback) (cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
+
+/** Structure with syspm callback configuration elements */
+typedef struct cy_stc_syspm_callback
+{
+ Cy_SysPmCallback callback; /**< The callback handler function. */
+ cy_en_syspm_callback_type_t type; /**< The callback type, see \ref cy_en_syspm_callback_type_t. */
+ uint32_t skipMode; /**< The mask of modes to be skipped during callback
+ execution, see \ref group_syspm_skip_callback_modes. The
+ corresponding callback mode won't execute if the
+ appropriate define is set. These values can be ORed.
+ If all modes are required to be executed this element
+ should be equal to zero. Skipping unneeded callback modes speeds up
+ power mode transitions by skipping unneeded operations. */
+
+ cy_stc_syspm_callback_params_t *callbackParams; /**< The address of a cy_stc_syspm_callback_params_t,
+ the callback is executed with these parameters. */
+
+ struct cy_stc_syspm_callback *prevItm; /**< The previous list item. This element should not be
+ defined, or defined as NULL. It is for internal
+ usage to link this structure to the next registered
+ structure. It will be updated during callback
+ registration. Do not modify this element at run-time. */
+
+ struct cy_stc_syspm_callback *nextItm; /**< The next list item. This element should not be
+ defined, or defined as NULL. It is for internal usage to
+ link this structure to the previous registered structure.
+ It will be updated during callback registration. Do not
+ modify this element at run-time. */
+ uint8_t order; /**< Holds the callback execution order value. Range: 0-255.
+ While entering low power mode, callbacks with lower order values
+ are executed first. While exiting low power mode,
+ the callbacks are executed in the opposite order.
+ Callbacks with the same order value are executed in the
+ order they are registered in the application. */
+} cy_stc_syspm_callback_t;
+
+/** This internal structure stores non-retained registers in the system Deep Sleep
+* power mode. On wakeup from system Deep Sleep, these registers are restored.
+*/
+typedef struct
+{
+ uint32_t CY_SYSPM_UDB_UDBIF_BANK_CTL_REG; /**< UDB interface control register */
+
+ uint32_t CY_SYSPM_UDB_BCTL_MDCLK_EN_REG; /**< UDB bank MDCLK_EN register */
+ uint32_t CY_SYSPM_UDB_BCTL_MBCLK_EN_REG; /**< UDB bank MBCLK_EN register */
+ uint32_t CY_SYSPM_UDB_BCTL_BOTSEL_L_REG; /**< UDB bank BOTSEL_L register */
+ uint32_t CY_SYSPM_UDB_BCTL_BOTSEL_U_REG; /**< UDB bank BOTSEL_U register */
+ uint32_t CY_SYSPM_UDB_BCTL_QCLK_EN0_REG; /**< UDB bank QCLK_EN0 register */
+ uint32_t CY_SYSPM_UDB_BCTL_QCLK_EN1_REG; /**< UDB bank QCLK_EN1 register */
+ uint32_t CY_SYSPM_UDB_BCTL_QCLK_EN2_REG; /**< UDB bank QCLK_EN2 register */
+} cy_stc_syspm_backup_regs_t;
+/** \} group_syspm_data_structures */
+
+/**
+* \addtogroup group_syspm_functions
+* \{
+*/
+
+/**
+* \addtogroup group_syspm_functions_general
+* \{
+*/
+cy_en_syspm_status_t Cy_SysPm_WriteVoltageBitForFlash(cy_en_syspm_flash_voltage_bit_t value);
+void Cy_SysPm_SaveRegisters(cy_stc_syspm_backup_regs_t *regs);
+void Cy_SysPm_RestoreRegisters(cy_stc_syspm_backup_regs_t const *regs);
+/** \} group_syspm_functions_general */
+
+
+/**
+* \addtogroup group_syspm_functions_power_status
+* \{
+*/
+
+__STATIC_INLINE bool Cy_SysPm_Cm4IsActive(void);
+__STATIC_INLINE bool Cy_SysPm_Cm4IsSleep(void);
+__STATIC_INLINE bool Cy_SysPm_Cm4IsDeepSleep(void);
+
+__STATIC_INLINE bool Cy_SysPm_Cm0IsActive(void);
+__STATIC_INLINE bool Cy_SysPm_Cm0IsSleep(void);
+__STATIC_INLINE bool Cy_SysPm_Cm0IsDeepSleep(void);
+__STATIC_INLINE bool Cy_SysPm_IsSystemLp(void);
+__STATIC_INLINE bool Cy_SysPm_IsSystemUlp(void);
+
+uint32_t Cy_SysPm_ReadStatus(void);
+/** \} group_syspm_functions_power_status */
+
+/**
+* \addtogroup group_syspm_functions_power
+* \{
+*/
+cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor);
+cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor);
+cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void);
+cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void);
+cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void);
+
+void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource);
+void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource);
+
+cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void);
+cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void);
+__STATIC_INLINE bool Cy_SysPm_SystemIsMinRegulatorCurrentSet(void);
+
+void Cy_SysPm_CpuSleepOnExit(bool enable);
+
+__STATIC_INLINE void Cy_SysPm_CpuSendWakeupEvent(void);
+/** \} group_syspm_functions_power */
+
+/**
+* \addtogroup group_syspm_functions_iofreeze
+* \{
+*/
+
+void Cy_SysPm_IoUnfreeze(void);
+__STATIC_INLINE bool Cy_SysPm_IoIsFrozen(void);
+/** \} group_syspm_functions_iofreeze */
+
+/**
+* \addtogroup group_syspm_functions_ldo
+* \{
+*/
+cy_en_syspm_status_t Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage);
+__STATIC_INLINE cy_en_syspm_ldo_voltage_t Cy_SysPm_LdoGetVoltage(void);
+__STATIC_INLINE bool Cy_SysPm_LdoIsEnabled(void);
+cy_en_syspm_status_t Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode);
+cy_en_syspm_ldo_mode_t Cy_SysPm_LdoGetMode(void);
+/** \} group_syspm_functions_ldo */
+
+/**
+* \addtogroup group_syspm_functions_pmic
+* \{
+*/
+__STATIC_INLINE void Cy_SysPm_PmicEnable(void);
+__STATIC_INLINE void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity);
+__STATIC_INLINE bool Cy_SysPm_PmicIsEnabled(void);
+__STATIC_INLINE void Cy_SysPm_PmicAlwaysEnable(void);
+__STATIC_INLINE void Cy_SysPm_PmicEnableOutput(void);
+__STATIC_INLINE void Cy_SysPm_PmicDisableOutput(void);
+__STATIC_INLINE bool Cy_SysPm_PmicIsOutputEnabled(void);
+__STATIC_INLINE void Cy_SysPm_PmicLock(void);
+__STATIC_INLINE void Cy_SysPm_PmicUnlock(void);
+__STATIC_INLINE bool Cy_SysPm_PmicIsLocked(void);
+/** \} group_syspm_functions_pmic */
+
+/**
+* \addtogroup group_syspm_functions_backup
+* \{
+*/
+__STATIC_INLINE void Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vddBackControl);
+__STATIC_INLINE cy_en_syspm_vddbackup_control_t Cy_SysPm_BackupGetSupply(void);
+__STATIC_INLINE void Cy_SysPm_BackupEnableVoltageMeasurement(void);
+__STATIC_INLINE void Cy_SysPm_BackupDisableVoltageMeasurement(void);
+__STATIC_INLINE void Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t key);
+/** \} group_syspm_functions_backup */
+
+/**
+* \addtogroup group_syspm_functions_buck
+* \{
+*/
+cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage);
+__STATIC_INLINE bool Cy_SysPm_BuckIsEnabled(void);
+cy_en_syspm_status_t Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltage);
+__STATIC_INLINE cy_en_syspm_buck_voltage1_t Cy_SysPm_BuckGetVoltage1(void);
+void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSettle);
+__STATIC_INLINE cy_en_syspm_buck_voltage2_t Cy_SysPm_BuckGetVoltage2(void);
+void Cy_SysPm_BuckEnableVoltage2(void);
+__STATIC_INLINE void Cy_SysPm_BuckDisableVoltage2(void);
+__STATIC_INLINE void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl);
+__STATIC_INLINE bool Cy_SysPm_BuckIsVoltage2HwControlled(void);
+bool Cy_SysPm_BuckIsOutputEnabled(cy_en_syspm_buck_out_t output);
+/** \} group_syspm_functions_buck */
+
+/**
+* \addtogroup group_syspm_functions_callback
+* \{
+*/
+bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t *handler);
+bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler);
+cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, cy_en_syspm_callback_mode_t mode);
+cy_stc_syspm_callback_t* Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type);
+/** \} group_syspm_functions_callback */
+
+/**
+* \addtogroup group_syspm_functions_power_status
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysPm_Cm4IsActive
+****************************************************************************//**
+*
+* Checks if CM4 is in CPU Active mode.
+*
+* \return
+* - True if CM4 is in CPU Active mode.
+* - False if the CM4 is not in CPU Active mode.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Cm4IsActive
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_Cm4IsActive(void)
+{
+ return ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_ACTIVE) != 0U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_Cm4IsSleep
+****************************************************************************//**
+*
+* Checks if the CM4 is in CPU Sleep mode.
+*
+* \return
+* - True if the CM4 is in CPU Sleep mode.
+* - False if the CM4 is not in CPU Sleep mode.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Cm4IsSleep
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_Cm4IsSleep(void)
+{
+ return ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_SLEEP) != 0U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_Cm4IsDeepSleep
+****************************************************************************//**
+*
+* Checks if the CM4 is in the CPU Deep Sleep mode.
+*
+* \return
+* - True if CM4 is in CPU Deep Sleep mode.
+* - False if the CM4 is not CPU in Deep Sleep mode.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Cm4IsDeepSleep
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_Cm4IsDeepSleep(void)
+{
+ return ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_DEEPSLEEP) != 0U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_Cm0IsActive
+****************************************************************************//**
+*
+* Checks if the CM0+ is in CPU Active mode.
+*
+* \return
+* - True if the CM0+ is in CPU Sleep mode.
+* - False if the CM0+ is not in CPU Sleep mode.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Cm0IsActive
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_Cm0IsActive(void)
+{
+ return ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_ACTIVE) != 0U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_Cm0IsSleep
+****************************************************************************//**
+*
+* Checks if the CM0+ is in CPU Sleep mode.
+*
+* \return
+* - True if the CM0+ is in CPU Sleep mode.
+* - False if the CM0+ is not in CPU Sleep mode.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Cm0IsSleep
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_Cm0IsSleep(void)
+{
+ return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_SLEEP) != 0U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_Cm0IsDeepSleep
+****************************************************************************//**
+*
+* Checks if the CM0+ is in CPU Deep Sleep mode.
+*
+* \return
+* - True if the CM0+ is in CPU Deep Sleep mode
+* - False if the CM0+ is not in CPU Deep Sleep mode
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Cm0IsDeepSleep
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_Cm0IsDeepSleep(void)
+{
+ return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_DEEPSLEEP) != 0U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_IsSystemLp
+****************************************************************************//**
+*
+* Checks if the system is in LP mode.
+*
+* \return
+* - True the system is in LP mode.
+* - False the system is not in LP mode.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_IsSystemLp
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_IsSystemLp(void)
+{
+ return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_LP) != 0U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_IsSystemUlp
+****************************************************************************//**
+*
+* Checks if the system is in ULP mode.
+*
+* \return
+* - True the system is in ULP mode.
+* - False the system is is not ULP mode.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_IsSystemUlp
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_IsSystemUlp(void)
+{
+ return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_ULP) != 0U);
+}
+/** \} group_syspm_functions_power_status */
+
+
+/**
+* \addtogroup group_syspm_functions_power
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysPm_CpuSendWakeupEvent
+****************************************************************************//**
+*
+* Sends the SEV (Send Event) ARM instruction to the system.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_CpuSendWakeupEvent
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_CpuSendWakeupEvent(void)
+{
+ __SEV();
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_SystemIsMinRegulatorCurrentSet
+****************************************************************************//**
+*
+* Check whether the system regulator is set to minimal current mode.
+*
+* \return
+* - True - system is in regulator minimum current mode.
+* - False - system is in normal regulator current mode.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemSetNormalRegulatorCurrent
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_SystemIsMinRegulatorCurrentSet(void)
+{
+ uint32_t regMask = Cy_SysPm_LdoIsEnabled() ? CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_LDO_MASK : CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_BUCK_MASK;
+
+ return ((SRSS_PWR_CTL & regMask) == regMask);
+}
+/** \} group_syspm_functions_power */
+
+
+/**
+* \addtogroup group_syspm_functions_buck
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysPm_BuckIsEnabled
+****************************************************************************//**
+*
+* Get the current status of the Buck regulator.
+*
+* \return
+* - True if the Buck regulator is enabled.
+* - False if it is disabled.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_BuckIsEnabled(void)
+{
+ return (0U != _FLD2VAL(SRSS_PWR_BUCK_CTL_BUCK_EN, SRSS_PWR_BUCK_CTL));
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BuckGetVoltage1
+****************************************************************************//**
+*
+* Gets the current nominal output 1 voltage (Vccbuck1) of
+* the Buck regulator.
+*
+* \note The actual device output 1 voltage (Vccbuck1) can be different from
+* the nominal voltage because the actual voltage value depends on conditions
+* including load current.
+*
+* \return
+* The nominal output voltage 1 (Vccbuck1) of the Buck regulator.
+* See \ref cy_en_syspm_buck_voltage1_t.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_syspm_buck_voltage1_t Cy_SysPm_BuckGetVoltage1(void)
+{
+ uint32_t retVal;
+ retVal = _FLD2VAL(SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, SRSS_PWR_BUCK_CTL);
+
+ return ((cy_en_syspm_buck_voltage1_t) retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BuckGetVoltage2
+****************************************************************************//**
+*
+* Gets the current output 2 nominal voltage (Vbuckrf) of the SIMO
+* Buck regulator.
+*
+* \note The actual device output 2 voltage (Vbuckrf) can be different from the
+* nominal voltage because the actual voltage value depends on conditions
+* including load current.
+*
+* \return
+* The nominal output voltage of the Buck SIMO regulator output 2
+* voltage (Vbuckrf). See \ref cy_en_syspm_buck_voltage2_t.
+*
+* \note
+* Function returns zero for devices without a SIMO Buck regulator.
+* Refer to the device datasheet about information on whether device contains
+* a SIMO Buck.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckGetVoltage2
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_syspm_buck_voltage2_t Cy_SysPm_BuckGetVoltage2(void)
+{
+ uint32_t retVal = 0UL;
+
+ if (0U != cy_device->sysPmSimoPresent)
+ {
+ retVal = _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL, SRSS_PWR_BUCK_CTL2);
+ }
+
+ return ((cy_en_syspm_buck_voltage2_t) retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BuckDisableVoltage2
+****************************************************************************//**
+*
+* Disables the output 2 voltage (Vbuckrf) of the SIMO Buck regulator. The
+* output 2 voltage (Vbuckrf) of the Buck regulator is typically used to supply
+* the BLE radio.
+*
+* \note The function does not have effect, if the Buck regulator is
+* switched off.
+*
+* \note If you are switching the voltage supply source for BLE radio, ensure
+* that the new voltage supply for the BLE HW block is settled
+* and is stable before calling the Cy_SysPm_BuckDisableVoltage2() function.
+*
+* This function is applicable for devices with the SIMO Buck regulator.
+* Refer to the device datasheet for information about whether the device
+* contains a SIMO Buck.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckDisableVoltage2
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_BuckDisableVoltage2(void)
+{
+ if (0U != cy_device->sysPmSimoPresent)
+ {
+ /* Disable the Vbuck2 output */
+ SRSS_PWR_BUCK_CTL2 &= (uint32_t) ~_VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, 1U);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BuckSetVoltage2HwControl
+****************************************************************************//**
+*
+* Sets the hardware control for SIMO Buck output 2 (Vbuckrf).
+*
+* When hardware control is enabled for the Vbuckrf output, the firmware
+* controlled enable register setting is ignored and the hardware signal is used
+* instead. If the product has supporting hardware like BLE radio, it can
+* directly control the enable signal for Vbuckrf.
+*
+* \param hwControl
+* Enables/disables hardware control for the SIMO Buck output 2.
+*
+* Function does not have an effect if SIMO Buck regulator is disabled.
+*
+* The function is applicable for devices with the SIMO Buck regulator.
+* Refer to the device datasheet for information about whether the device
+* contains a SIMO Buck.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckSetVoltage2HwControl
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl)
+{
+ bool isBuckEnabled = Cy_SysPm_BuckIsEnabled();
+
+ if ((0U != cy_device->sysPmSimoPresent) && isBuckEnabled)
+ {
+ if(hwControl)
+ {
+ SRSS_PWR_BUCK_CTL2 |= _VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, 1U);
+ }
+ else
+ {
+ SRSS_PWR_BUCK_CTL2 &= (uint32_t) ~_VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, 1U);
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BuckIsVoltage2HwControlled
+****************************************************************************//**
+*
+* Returns the hardware control state for Buck output 2 (Vbuckrf).
+*
+* When hardware control is enabled for the Vbuckrf output, the firmware
+* controlled enable register setting is ignored and the hardware signal is used
+* instead. If the product has supporting hardware like BLE radio, it can
+* directly control the enable signal for Vbuckrf.
+*
+* \return
+* - True if HW control is set.
+* - False if FW control is set for the Buck output 2.
+*
+* The function is applicable for devices with the SIMO Buck regulator.
+* Refer to device datasheet about information if device contains
+* SIMO Buck.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckIsVoltage2HwControlled
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_BuckIsVoltage2HwControlled(void)
+{
+ bool retVal = false;
+
+ if (0U != cy_device->sysPmSimoPresent)
+ {
+ retVal = (0U != _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, SRSS_PWR_BUCK_CTL2));
+ }
+
+ return retVal;
+}
+/** \} group_syspm_functions_buck */
+
+
+/**
+* \addtogroup group_syspm_functions_ldo
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysPm_LdoGetVoltage
+****************************************************************************//**
+*
+* Gets the current output voltage value of the core LDO regulator.
+*
+* \note The actual device Vccd voltage can be different from the
+* nominal voltage because the actual voltage value depends on conditions
+* including the load current.
+*
+* \return
+* The nominal output voltage of the LDO. See \ref cy_en_syspm_ldo_voltage_t.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_syspm_ldo_voltage_t Cy_SysPm_LdoGetVoltage(void)
+{
+ uint32_t curVoltage;
+
+ curVoltage = _FLD2VAL(SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, SRSS_PWR_TRIM_PWRSYS_CTL);
+
+ return ((curVoltage == (SFLASH_LDO_0P9V_TRIM)) ? CY_SYSPM_LDO_VOLTAGE_ULP : CY_SYSPM_LDO_VOLTAGE_LP);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_LdoIsEnabled
+****************************************************************************//**
+*
+* Reads the current status of the core LDO regulator.
+*
+* \return
+* - True means the LDO is enabled.
+* - False means it is disabled.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_LdoIsEnabled(void)
+{
+ return ((0U != _FLD2VAL(SRSS_PWR_CTL_LINREG_DIS, SRSS_PWR_CTL)) ? false : true);
+}
+/** \} group_syspm_functions_ldo */
+
+
+/**
+* \addtogroup group_syspm_functions_iofreeze
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysPm_IoIsFrozen
+****************************************************************************//**
+*
+* Checks whether IOs are frozen.
+*
+* \return
+* - True if IOs are frozen.
+* - False if IOs are unfrozen.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_IoUnfreeze
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_IoIsFrozen(void)
+{
+ return (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_FREEZE, SRSS_PWR_HIBERNATE));
+}
+/** \} group_syspm_functions_iofreeze */
+
+/**
+* \addtogroup group_syspm_functions_pmic
+* \{
+*/
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicEnable
+****************************************************************************//**
+*
+* Enable the external PMIC controller that supplies Vddd (if present).
+*
+* For information about the PMIC controller input and output pins and their
+* assignment in specific devices, refer to the appropriate device TRM.
+*
+* This function is not effective when the PMIC controller is locked. Call
+* Cy_SysPm_PmicUnlock() before enabling the PMIC.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicEnable(void)
+{
+ if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
+ {
+ BACKUP_PMIC_CTL =
+ _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) |
+ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1U) |
+ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN, 1U);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicDisable
+****************************************************************************//**
+*
+* Disable the external PMIC controller that supplies Vddd (if present).
+* This function does not affect the PMIC controller output pin. The PMIC
+* controller input pin has programmable polarity to
+* enable the external PMIC using different input polarities. The PMIC controller
+* is automatically enabled when the input pin polarity and configured polarity
+* match. This function is not effective when the active level of PMIC controller
+* input pin is equal to the configured PMIC controller polarity.
+*
+* The function is not effective when the PMIC controller is locked. Call
+* Cy_SysPm_PmicUnlock() before enabling the PMIC controller.
+*
+* \param polarity
+* Configures the PMIC controller wakeup input pin to be active low or active
+* high. The PMIC will be automatically enabled when the set polarity and the
+* active level of PMIC input pin match.
+* See \ref cy_en_syspm_pmic_wakeup_polarity_t.
+*
+* The PMIC controller will be enabled automatically by any of RTC alarm or
+* PMIC wakeup events, regardless of the PMIC controller lock state.
+*
+* \note
+* Before disabling the PMIC controller, ensure that PMIC input and PMIC output
+* pins are configured correctly to enable expected PMIC operation.
+*
+* \warning
+* The PMIC is enabled automatically when you call Cy_SysPm_PmicLock().
+* To keep the external PMIC disabled, the PMIC controller must remain unlocked.
+*
+* \warning
+* Do not call Cy_SysPm_PmicDisable(CY_SYSPM_PMIC_POLARITY_LOW) because this
+* is not supported by hardware.
+*
+* For information about the PMIC controller input and output pins and their
+* assignment in the specific devices, refer to the appropriate
+* device TRM.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_POLARITY_VALID(polarity));
+
+ if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
+ {
+ BACKUP_PMIC_CTL =
+ (_VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) |
+ _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_POLARITY, (uint32_t) polarity)) &
+ ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN, 1U));
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicAlwaysEnable
+****************************************************************************//**
+*
+* Enable the external PMIC controller that supplies Vddd (if present) and force
+* active. This is a Write once API. It ensures that the PMIC controller cannot
+* be disabled or polarity changed until a next device reset.
+*
+* For information about the PMIC controller input and output pins and their
+* assignment in the specific devices, refer to the appropriate device TRM.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicAlwaysEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicAlwaysEnable(void)
+{
+ BACKUP_PMIC_CTL |= _VAL2FLD(BACKUP_PMIC_CTL_PMIC_ALWAYSEN, 1U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicEnableOutput
+****************************************************************************//**
+*
+* Enables the PMIC controller output pin.
+*
+* The function is not effective when the PMIC controller is locked. Call
+* Cy_SysPm_PmicUnlock() before enabling the PMIC controller.
+*
+* For information about the PMIC controller output pin and its assignment in
+* specific devices, refer to the appropriate device TRM.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicEnableOutput
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicEnableOutput(void)
+{
+ if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
+ {
+ BACKUP_PMIC_CTL |=
+ _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) | _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1U);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicDisableOutput
+****************************************************************************//**
+*
+* Disables the PMIC controller output pin.
+*
+* When the PMIC controller output pin is disabled and is unlocked, the PMIC
+* controller output pin can be used for the another purpose.
+*
+* The function has no effect when the PMIC is locked. Call
+* Cy_SysPm_PmicUnlock() before enabling the PMIC.
+*
+* For information about the PMIC controller output pin and its assignment in
+* specific devices, refer to the appropriate device TRM.
+*
+* \note
+* After the PMIC controller output is disabled, the PMIC output pin returns to
+* its GPIO configured state.
+*
+* \warning
+* The PMIC controller output is enabled automatically when you call
+* Cy_SysPm_PmicLock(). To keep the PMIC controller output disabled, the PMIC
+* controller must remain unlocked.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicDisableOutput
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicDisableOutput(void)
+{
+ if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
+ {
+ BACKUP_PMIC_CTL =
+ (BACKUP_PMIC_CTL | _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY)) &
+ ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1U));
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicLock
+****************************************************************************//**
+*
+* Locks the PMIC control controller register so that no changes can be made.
+* The changes are related to PMIC enabling/disabling and PMIC output pin
+* enabling/disabling.
+*
+* \warning
+* The PMIC controller and/or the PMIC output are enabled automatically when
+* you call Cy_SysPm_PmicLock(). To keep the PMIC or PMIC controller output
+* disabled, the PMIC controller must remain unlocked.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicLock
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicLock(void)
+{
+ BACKUP_PMIC_CTL = _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, 0U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicUnlock
+****************************************************************************//**
+*
+* Unlocks the PMIC control register so that changes can be made. The changes are
+* related to the PMIC controller enabling/disabling and PMIC output pin
+* enabling/disabling.
+*
+* \warning
+* The PMIC controller and/or the PMIC output are enabled automatically when
+* you call Cy_SysPm_PmicLock(). To keep the PMIC controller or PMIC output
+* disabled, the PMIC must remain unlocked.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicUnlock(void)
+{
+ BACKUP_PMIC_CTL = _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicIsEnabled
+****************************************************************************//**
+*
+* This function returns the status of the PMIC controller.
+*
+* \return
+* - True if the PMIC is enabled.
+* - False if the PMIC is disabled.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicLock
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_PmicIsEnabled(void)
+{
+ return (0U != _FLD2VAL(BACKUP_PMIC_CTL_PMIC_EN, BACKUP_PMIC_CTL));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicIsOutputEnabled
+****************************************************************************//**
+*
+* This function returns the status of the PMIC controller output.
+*
+* \return
+* - True if the PMIC output is enabled.
+* - False if the PMIC output is disabled.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicDisable
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_PmicIsOutputEnabled(void)
+{
+ return (0U != _FLD2VAL(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, BACKUP_PMIC_CTL));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicIsLocked
+****************************************************************************//**
+*
+* Returns the PMIC controller lock status.
+*
+* \return
+* - True if the PMIC is locked.
+* - False if the PMIC is unlocked.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_PmicLock
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_PmicIsLocked(void)
+{
+ return ((_FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL) == CY_SYSPM_PMIC_UNLOCK_KEY) ? false : true);
+}
+/** \} group_syspm_functions_pmic */
+
+
+/**
+* \addtogroup group_syspm_functions_backup
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysPm_BackupSetSupply
+****************************************************************************//**
+*
+* Sets the backup supply (Vddback) operation mode.
+*
+* \param
+* vddBackControl
+* Selects backup supply (Vddback) operation mode.
+* See \ref cy_en_syspm_vddbackup_control_t.
+*
+* Refer to device TRM for more detail about backup supply modes.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BackupSetSupply
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vddBackControl)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_VDDBACKUP_VALID(vddBackControl));
+
+ BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_VDDBAK_CTL, (uint32_t) vddBackControl);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BackupGetSupply
+****************************************************************************//**
+*
+* Returns the current backup supply (Vddback) operation mode.
+*
+* \return
+* The current backup supply (Vddback) operation mode,
+* see \ref cy_en_syspm_status_t.
+*
+* Refer to device TRM for more detail about backup supply modes.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BackupGetSupply
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_syspm_vddbackup_control_t Cy_SysPm_BackupGetSupply(void)
+{
+ uint32_t retVal;
+ retVal = _FLD2VAL(BACKUP_CTL_VDDBAK_CTL, BACKUP_CTL);
+
+ return ((cy_en_syspm_vddbackup_control_t) retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BackupEnableVoltageMeasurement
+****************************************************************************//**
+*
+* This function enables Vbackup supply measurement by the ADC. The function
+* connects the Vbackup supply to AMuxBusA. The ADC input can then be connected
+* to AMuxBusA. Note that the measured signal is scaled by 10% to allow full
+* range measurement by the ADC.
+*
+* Refer to device TRM for more detail about Vbackup supply measurement.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BackupEnableVoltageMeasurement
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_BackupEnableVoltageMeasurement(void)
+{
+ BACKUP_CTL |= BACKUP_CTL_VBACKUP_MEAS_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BackupDisableVoltageMeasurement
+****************************************************************************//**
+*
+* The function disables Vbackup supply measurement by the ADC by disconnecting
+* the Vbackup supply from AMuxBusA.
+*
+* Refer to device TRM for more detail about Vbackup supply measurement.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BackupDisableVoltageMeasurement
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_BackupDisableVoltageMeasurement(void)
+{
+ BACKUP_CTL &= ((uint32_t) ~BACKUP_CTL_VBACKUP_MEAS_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BackupSuperCapCharge
+****************************************************************************//**
+*
+* Configures the supercapacitor charger circuit.
+*
+* \param key
+* Passes the key to enable or disable the supercapacitor charger circuit.
+* See \ref cy_en_syspm_sc_charge_key_t.
+*
+* \warning
+* This function is used only for charging the supercapacitor.
+* Do not use this function to charge a battery. Refer to device TRM for more
+* detail.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BackupSuperCapCharge
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t key)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_SC_CHARGE_KEY_VALID(key));
+
+ if(key == CY_SYSPM_SC_CHARGE_ENABLE)
+ {
+ BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_EN_CHARGE_KEY, (uint32_t) CY_SYSPM_SC_CHARGE_ENABLE);
+ }
+ else
+ {
+ BACKUP_CTL &= ((uint32_t) ~BACKUP_CTL_EN_CHARGE_KEY_Msk);
+ }
+}
+
+/** \} group_syspm_functions_backup */
+/** \} group_syspm_functions*/
+
+/** \cond INTERNAL */
+
+/*******************************************************************************
+* Backward compatibility macro. The following code is DEPRECATED and must
+* not be used in new projects
+*******************************************************************************/
+
+/* BWC defines for Buck related functions */
+typedef cy_en_syspm_buck_voltage1_t cy_en_syspm_simo_buck_voltage1_t;
+typedef cy_en_syspm_buck_voltage2_t cy_en_syspm_simo_buck_voltage2_t;
+
+#define Cy_SysPm_SimoBuckGetVoltage2 Cy_SysPm_BuckGetVoltage2
+#define Cy_SysPm_DisableVoltage2 Cy_SysPm_BuckDisableVoltage2
+#define Cy_SysPm_EnableVoltage2 Cy_SysPm_BuckEnableVoltage2
+#define Cy_SysPm_SimoBuckSetHwControl Cy_SysPm_BuckSetVoltage2HwControl
+#define Cy_SysPm_SimoBuckGetHwControl Cy_SysPm_BuckIsVoltage2HwControlled
+#define Cy_SysPm_SimoBuckSetVoltage2 Cy_SysPm_BuckSetVoltage2
+
+#define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_15V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_15V
+#define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_2V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_2V
+#define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_25V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_25V
+#define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_3V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_3V
+#define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_35V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_35V
+#define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_4V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_4V
+#define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_45V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_45V
+#define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_5V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_5V
+
+#define CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_0_9V CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V
+#define CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_1_1V CY_SYSPM_BUCK_OUT1_VOLTAGE_1_1V
+
+#define Cy_SysPm_SwitchToSimoBuck() (Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V))
+#define Cy_SysPm_SimoBuckGetVoltage1 Cy_SysPm_BuckGetVoltage1
+#define Cy_SysPm_SimoBuckIsEnabled Cy_SysPm_BuckIsEnabled
+#define Cy_SysPm_SimoBuckSetVoltage1 Cy_SysPm_BuckSetVoltage1
+#define Cy_SysPm_SimoBuckOutputIsEnabled Cy_SysPm_BuckIsOutputEnabled
+
+#define CY_SYSPM_LPCOMP0_LOW CY_SYSPM_HIBERNATE_LPCOMP0_LOW
+#define CY_SYSPM_LPCOMP0_HIGH CY_SYSPM_HIBERNATE_LPCOMP0_HIGH
+#define CY_SYSPM_LPCOMP1_LOW CY_SYSPM_HIBERNATE_LPCOMP1_LOW
+#define CY_SYSPM_LPCOMP1_HIGH CY_SYSPM_HIBERNATE_LPCOMP1_HIGH
+#define CY_SYSPM_HIBALARM CY_SYSPM_HIBERNATE_RTC_ALARM
+#define CY_SYSPM_HIBWDT CY_SYSPM_HIBERNATE_WDT
+#define CY_SYSPM_HIBPIN0_LOW CY_SYSPM_HIBERNATE_PIN0_LOW
+#define CY_SYSPM_HIBPIN0_HIGH CY_SYSPM_HIBERNATE_PIN0_HIGH
+#define CY_SYSPM_HIBPIN1_LOW CY_SYSPM_HIBERNATE_PIN1_LOW
+#define CY_SYSPM_HIBPIN1_HIGH CY_SYSPM_HIBERNATE_PIN1_HIGH
+
+#define CY_SYSPM_ENTER_LP_MODE CY_SYSPM_ULP
+#define CY_SYSPM_EXIT_LP_MODE CY_SYSPM_LP
+#define CY_SYSPM_STATUS_SYSTEM_LOWPOWER CY_SYSPM_STATUS_SYSTEM_ULP
+
+typedef cy_en_syspm_hibernate_wakeup_source_t cy_en_syspm_hib_wakeup_source_t;
+
+/* BWC defines related to hibernation functions */
+#define Cy_SysPm_SetHibWakeupSource Cy_SysPm_SetHibernateWakeupSource
+#define Cy_SysPm_ClearHibWakeupSource Cy_SysPm_ClearHibernateWakeupSource
+#define Cy_SysPm_GetIoFreezeStatus Cy_SysPm_IoIsFrozen
+
+/* BWC defines for Backup related functions */
+#define Cy_SysPm_SetBackupSupply Cy_SysPm_BackupSetSupply
+#define Cy_SysPm_GetBackupSupply Cy_SysPm_BackupGetSupply
+#define Cy_SysPm_EnableBackupVMeasure Cy_SysPm_BackupEnableVoltageMeasurement
+#define Cy_SysPm_DisableBackupVMeasure Cy_SysPm_BackupDisableVoltageMeasurement
+
+/* BWC defines for PMIC related functions */
+#define Cy_SysPm_EnablePmic Cy_SysPm_PmicEnable
+#define Cy_SysPm_DisablePmic Cy_SysPm_PmicDisable
+#define Cy_SysPm_AlwaysEnablePmic Cy_SysPm_PmicAlwaysEnable
+#define Cy_SysPm_EnablePmicOutput Cy_SysPm_PmicEnableOutput
+#define Cy_SysPm_DisablePmicOutput Cy_SysPm_PmicDisableOutput
+#define Cy_SysPm_LockPmic Cy_SysPm_PmicLock
+#define Cy_SysPm_UnlockPmic Cy_SysPm_PmicUnlock
+#define Cy_SysPm_IsPmicEnabled Cy_SysPm_PmicIsEnabled
+#define Cy_SysPm_IsPmicOutputEnabled Cy_SysPm_PmicIsOutputEnabled
+#define Cy_SysPm_IsPmicLocked Cy_SysPm_PmicIsLocked
+
+/* BWC defines for functions related to low power transition */
+#define Cy_SysPm_Sleep Cy_SysPm_CpuEnterSleep
+#define Cy_SysPm_DeepSleep Cy_SysPm_CpuEnterDeepSleep
+#define Cy_SysPm_Hibernate Cy_SysPm_SystemEnterHibernate
+
+#define Cy_SysPm_SleepOnExit Cy_SysPm_CpuSleepOnExit
+
+/* BWC defines for functions related to low power transition*/
+#define Cy_SysPm_EnterLpMode Cy_SysPm_EnterLowPowerMode
+#define Cy_SysPm_ExitLpMode Cy_SysPm_ExitLowPowerMode
+#define Cy_SysPm_IsLowPower Cy_SysPm_IsSystemUlp
+
+#define Cy_SysPm_EnterLowPowerMode Cy_SysPm_SystemSetMinRegulatorCurrent
+#define Cy_SysPm_ExitLowPowerMode Cy_SysPm_SystemSetNormalRegulatorCurrent
+
+#define CY_SYSPM_WAKEUP_PIN0_BIT CY_SYSPM_HIB_WAKEUP_PIN0_POS
+#define CY_SYSPM_WAKEUP_PIN1_BIT CY_SYSPM_HIB_WAKEUP_PIN1_POS
+#define CY_SYSPM_WAKEUP_LPCOMP0_BIT CY_SYSPM_HIB_WAKEUP_LPCOMP0_POS
+#define CY_SYSPM_WAKEUP_LPCOMP1_BIT CY_SYSPM_HIB_WAKEUP_LPCOMP1_POS
+
+#define CY_SYSPM_WAKEUP_LPCOMP0 CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK
+#define CY_SYSPM_WAKEUP_LPCOMP1 CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK
+#define CY_SYSPM_WAKEUP_PIN0 CY_SYSPM_HIB_WAKEUP_PIN0_MASK
+#define CY_SYSPM_WAKEUP_PIN1 CY_SYSPM_HIB_WAKEUP_PIN1_MASK
+#define CY_SYSPM_WAKEUP_LPCOMP0_POLARITY_HIGH CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK
+#define CY_SYSPM_WAKEUP_LPCOMP1_POLARITY_HIGH CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK
+#define CY_SYSPM_WAKEUP_PIN0_POLARITY_HIGH CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK
+#define CY_SYSPM_WAKEUP_PIN1_POLARITY_HIGH CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK
+
+#define CY_SYSPM_PWR_TOKEN_HIBERNATE HIBERNATE_TOKEN
+#define CY_SYSPM_PWR_WAKEUP_HIB_MASK HIBERNATE_WAKEUP_MASK
+#define CY_SYSPM_PWR_RETAIN_HIBERNATE_STATUS HIBERNATE_RETAIN_STATUS_MASK
+#define CY_SYSPM_PWR_SET_HIBERNATE SET_HIBERNATE_MODE
+#define CY_SYSPM_PWR_HIBERNATE_UNLOCK HIBERNATE_UNLOCK_VAL
+
+/** \endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CY_SYSPM_H */
+
+/** \} group_syspm */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_systick.h b/platform/ext/target/psoc64/Native_Driver/include/cy_systick.h
new file mode 100644
index 0000000000..a368d26108
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_systick.h
@@ -0,0 +1,313 @@
+/***************************************************************************//**
+* \file cy_systick.h
+* \version 1.10
+*
+* Provides the API declarations of the SysTick driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CY_SYSTICK_H
+#define CY_SYSTICK_H
+
+/**
+* \addtogroup group_arm_system_timer
+* \{
+* Provides vendor-specific SysTick API.
+*
+* The functions and other declarations used in this driver are in cy_systick.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions and declarations in the PDL.
+*
+* The SysTick timer is part of the CPU. The timer is a down counter with a 24-bit reload/tick value that is clocked by
+* the FastClk/SlowClk. The timer has the capability to generate an interrupt when the set number of ticks expires and
+* the counter is reloaded. This interrupt is available as part of the Nested Vectored Interrupt Controller (NVIC) for
+* service by the CPU and can be used for general-purpose timing control in user code.
+*
+* The timer is independent of the CPU (except for the clock), which is useful in applications requiring
+* precise timing that do not have a dedicated timer/counter available for the job.
+*
+* \section group_systick_configuration Configuration Considerations
+*
+* The \ref Cy_SysTick_Init() performs all required driver's initialization and enables the timer. The function accepts
+* two parameters: clock source \ref cy_en_systick_clock_source_t and the timer interval. You must ensure
+* the selected clock source for SysTick is enabled.
+* The callbacks can be registered/unregistered any time after \ref Cy_SysTick_Init() by calling
+* \ref Cy_SysTick_SetCallback().
+*
+* Changing the SysTick clock source and/or its frequency will change the interrupt interval and therefore
+* \ref Cy_SysTick_SetReload() should be called to compensate for this change.
+*
+* \section group_systick_more_information More Information
+*
+* Refer to the SysTick section of the ARM reference guide for complete details on the registers and their use.
+* See also the "CPU Subsystem (CPUSS)" chapter of the device technical reference manual (TRM).
+*
+* \section group_systick_MISRA MISRA-C Compliance
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>8.12</td>
+* <td>Required</td>
+* <td>When an array is declared with external linkage, its size shall be
+* stated explicitly or defined implicitly by initialization.</td>
+* <td>The warning is related to the __ramVectors symbol defined in the assembly startup code.
+* It's size is device-specific and unknown to the SysTick driver.</td>
+* </tr>
+* </table>
+*
+* \section group_systick_changelog Changelog
+*
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td rowspan="2">1.10</td>
+* <td>Flattened the organization of the driver source code into the single
+* source directory and the single include directory.
+* </td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>1.0.1</td>
+* <td>Fixed a warning issued when the compilation of C++ source code was
+* enabled.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_systick_macros Macros
+* \defgroup group_systick_functions Functions
+* \defgroup group_systick_data_structures Data Structures
+*/
+
+#include <stdint.h>
+#include "cy_syslib.h"
+#include "cy_device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \cond */
+extern cy_israddress __ramVectors[];
+typedef void (*Cy_SysTick_Callback)(void);
+/** \endcond */
+
+/**
+* \addtogroup group_systick_data_structures
+* \{
+*/
+/** SysTick clocks sources */
+typedef enum
+{
+ CY_SYSTICK_CLOCK_SOURCE_CLK_LF = 0u, /**< The low frequency clock clk_lf is selected. */
+ CY_SYSTICK_CLOCK_SOURCE_CLK_IMO = 1u, /**< The internal main oscillator (IMO) clock clk_imo is selected. */
+ CY_SYSTICK_CLOCK_SOURCE_CLK_ECO = 2u, /**< The external crystal oscillator (ECO) clock clk_eco is selected. */
+ CY_SYSTICK_CLOCK_SOURCE_CLK_TIMER = 3u, /**< The SRSS clk_timer is selected. */
+ CY_SYSTICK_CLOCK_SOURCE_CLK_CPU = 4u, /**< The CPU clock is selected. */
+} cy_en_systick_clock_source_t;
+
+/** \} group_systick_data_structures */
+
+
+/**
+* \addtogroup group_systick_functions
+* \{
+*/
+
+void Cy_SysTick_Init(cy_en_systick_clock_source_t clockSource, uint32_t interval);
+void Cy_SysTick_Enable(void);
+void Cy_SysTick_Disable(void);
+Cy_SysTick_Callback Cy_SysTick_SetCallback(uint32_t number, Cy_SysTick_Callback function);
+Cy_SysTick_Callback Cy_SysTick_GetCallback(uint32_t number);
+void Cy_SysTick_SetClockSource(cy_en_systick_clock_source_t clockSource);
+cy_en_systick_clock_source_t Cy_SysTick_GetClockSource(void);
+__STATIC_INLINE void Cy_SysTick_EnableInterrupt(void);
+__STATIC_INLINE void Cy_SysTick_DisableInterrupt(void);
+__STATIC_INLINE void Cy_SysTick_SetReload(uint32_t value);
+__STATIC_INLINE uint32_t Cy_SysTick_GetReload(void);
+__STATIC_INLINE uint32_t Cy_SysTick_GetValue(void);
+__STATIC_INLINE uint32_t Cy_SysTick_GetCountFlag(void);
+__STATIC_INLINE void Cy_SysTick_Clear(void);
+
+/** \} group_systick_functions */
+
+
+/**
+* \addtogroup group_systick_macros
+* \{
+*/
+
+/** Driver major version */
+#define SYSTICK_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define SYSTICK_DRV_VERSION_MINOR 10
+
+/** Number of the callbacks assigned to the SysTick interrupt */
+#define CY_SYS_SYST_NUM_OF_CALLBACKS (5u)
+
+/** \} group_systick_macros */
+
+
+/** \cond */
+/** Interrupt number in the vector table */
+#define CY_SYSTICK_IRQ_NUM (15u)
+/** \endcond */
+
+/**
+* \addtogroup group_systick_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_EnableInterrupt
+****************************************************************************//**
+*
+* Enables the SysTick interrupt.
+*
+* \sideeffect Clears the SysTick count flag if it was set
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysTick_EnableInterrupt(void)
+{
+ SYSTICK_CTRL = SYSTICK_CTRL | SysTick_CTRL_TICKINT_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_DisableInterrupt
+****************************************************************************//**
+*
+* Disables the SysTick interrupt.
+*
+* \sideeffect Clears the SysTick count flag if it was set
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysTick_DisableInterrupt(void)
+{
+ SYSTICK_CTRL = SYSTICK_CTRL & ~SysTick_CTRL_TICKINT_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_SetReload
+****************************************************************************//**
+*
+* Sets the value the counter is set to on a startup and after it reaches zero.
+* This function does not change or reset the current sysTick counter value, so
+* it should be cleared using the Cy_SysTick_Clear() API.
+*
+* \param value: The valid range is [0x0-0x00FFFFFF]. The counter reset value.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysTick_SetReload(uint32_t value)
+{
+ SYSTICK_LOAD = (value & SysTick_LOAD_RELOAD_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_GetReload
+****************************************************************************//**
+*
+* Gets the value the counter is set to on a startup and after it reaches zero.
+*
+* \return The counter reset value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysTick_GetReload(void)
+{
+ return (SYSTICK_LOAD);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_GetValue
+****************************************************************************//**
+*
+* Gets the current SysTick counter value.
+*
+* \return The current SysTick counter value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysTick_GetValue(void)
+{
+ return (SYSTICK_VAL);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_Clear
+****************************************************************************//**
+*
+* Clears the SysTick counter for a well-defined startup.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysTick_Clear(void)
+{
+ SYSTICK_VAL = 0u;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_GetCountFlag
+****************************************************************************//**
+*
+* Gets the values of the count flag. The count flag is set once the SysTick
+* counter reaches zero. The flag is cleared on read.
+*
+* \return Returns a non-zero value if a flag is set; otherwise a zero is
+* returned.
+*
+* \sideeffect Clears the SysTick count flag if it was set.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysTick_GetCountFlag(void)
+{
+ return (SYSTICK_CTRL & SysTick_CTRL_COUNTFLAG_Msk);
+}
+
+
+/** \} group_systick_functions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CY_SYSTICK_H */
+
+/** \} group_systick */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_tcpwm.h b/platform/ext/target/psoc64/Native_Driver/include/cy_tcpwm.h
new file mode 100644
index 0000000000..7fbc9830f6
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_tcpwm.h
@@ -0,0 +1,712 @@
+/***************************************************************************//**
+* \file cy_tcpwm.h
+* \version 1.10.1
+*
+* The header file of the TCPWM driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_tcpwm
+* \{
+* \defgroup group_tcpwm_common Common
+* \defgroup group_tcpwm_counter Timer/Counter (TCPWM)
+* \defgroup group_tcpwm_pwm PWM (TCPWM)
+* \defgroup group_tcpwm_quaddec Quadrature Decoder (TCPWM)
+* \} */
+
+/**
+* \addtogroup group_tcpwm
+* \{
+*
+* The TCPWM driver is a multifunction driver that implements Timer Counter,
+* PWM, and Quadrature Decoder functionality using the TCPWM block.
+*
+* The functions and other declarations used in this driver are in cy_tcpwm_counter.h,
+* cy_tcpwm_pwm.h, cy_tcpwm_quaddec.h respectively. Include cy_pdl.h
+* (ModusToolbox only) to get access to all functions and declarations in the PDL.
+*
+* Each TCPWM block is a collection of counters that can all be triggered
+* simultaneously. For each function call, the base register address of
+* the TCPWM being used must be passed first, followed by the index of
+* the counter you want to touch next.
+* For some functions, you can manage multiple counters simultaneously. You
+* provide a bit field representing each counter, rather than the single counter
+* index).
+*
+* The TCPWM supports three operating modes:
+* * Timer/Counter
+* * PWM
+* * Quadrature Decoder
+*
+* \n
+* \b Timer/Counter
+*
+* Use this mode whenever a specific timing interval or measurement is
+* needed. Examples include:
+* * Creating a periodic interrupt for running other system tasks
+* * Measuring frequency of an input signal
+* * Measuring pulse width of an input signal
+* * Measuring time between two external events
+* * Counting events
+* * Triggering other system resources after x number events
+* * Capturing time stamps when events occur
+*
+* The Timer/Counter has the following features:
+* * 16- or 32-bit Timer/Counter
+* * Programmable Period Register
+* * Programmable Compare Register. Compare value can be swapped with a
+* buffered compare value on comparison event
+* * Capture with buffer register
+* * Count Up, Count Down, or Count Up and Down Counting modes
+* * Continuous or One Shot Run modes
+* * Interrupt and Output on Overflow, Underflow, Capture, or Compare
+* * Start, Reload, Stop, Capture, and Count Inputs
+*
+* \n
+* \b PWM
+*
+* Use this mode when an output square wave is needed with a specific
+* period and duty cycle, such as:
+* * Creating arbitrary square wave outputs
+* * Driving an LED (changing the brightness)
+* * Driving Motors (dead time assertion available)
+*
+* The PWM has the following features:
+* * 16- or 32-bit Counter
+* * Two Programmable Period registers that can be swapped
+* * Two Output Compare registers that can be swapped on overflow and/or
+* underflow
+* * Left Aligned, Right Aligned, Center Aligned, and Asymmetric Aligned modes
+* * Continuous or One Shot run modes
+* * Pseudo Random mode
+* * Two PWM outputs with Dead Time insertion, and programmable polarity
+* * Interrupt and Output on Overflow, Underflow, or Compare
+* * Start, Reload, Stop, Swap (Capture), and Count Inputs
+* * Multiple Components can be synchronized together for applications
+* such as three phase motor control
+*
+* \n
+* \b Quadrature \b Decoder
+*
+* A quadrature decoder is used to decode the output of a quadrature encoder.
+* A quadrature encoder senses the position, velocity, and direction of
+* an object (for example a rotating axle, or a spinning mouse ball).
+* A quadrature decoder can also be used for precision measurement of speed,
+* acceleration, and position of a motor's rotor, or with a rotary switch to
+* determine user input. \n
+*
+* The Quadrature Decoder has the following features:
+* * 16- or 32-bit Counter
+* * Counter Resolution of x1, x2, and x4 the frequency of the phiA (Count) and
+* phiB (Start) inputs
+* * Index Input to determine absolute position
+* * A positive edge on phiA increments the counter when phiB is 0 and decrements
+* the counter when phiB is 1
+*
+* \section group_tcpwm_configuration Configuration Considerations
+*
+* For each mode, the TCPWM driver has a configuration structure, an Init
+* function, and an Enable function.
+*
+* Provide the configuration parameters in the appropriate structure (see
+* Counter \ref group_tcpwm_data_structures_counter, PWM
+* \ref group_tcpwm_data_structures_pwm, or QuadDec
+* \ref group_tcpwm_data_structures_quaddec).
+* Then call the appropriate Init function:
+* \ref Cy_TCPWM_Counter_Init, \ref Cy_TCPWM_PWM_Init, or
+* \ref Cy_TCPWM_QuadDec_Init. Provide the address of the filled structure as a
+* parameter. To enable the counter, call the appropriate Enable function:
+* \ref Cy_TCPWM_Counter_Enable, \ref Cy_TCPWM_PWM_Enable, or
+* \ref Cy_TCPWM_QuadDec_Enable).
+*
+* Many functions work with an individual counter. You can also manage multiple
+* counters simultaneously for certain functions. These are listed in the
+* \ref group_tcpwm_functions_common
+* section of the TCPWM. You can enable, disable, or trigger (in various ways)
+* multiple counters simultaneously. For these functions you provide a bit field
+* representing each counter in the TCPWM you want to control. You can
+* represent the bit field as an ORed mask of each counter, like
+* ((1U << cntNumX) | (1U << cntNumX) | (1U << cntNumX)), where X is the counter
+* number from 0 to 31.
+*
+* \note
+* * If none of the input terminals (start, reload(index)) are used, the
+* software event \ref Cy_TCPWM_TriggerStart or
+* \ref Cy_TCPWM_TriggerReloadOrIndex must be called to start the counting.
+* * If count input terminal is not used, the \ref CY_TCPWM_INPUT_LEVEL macro
+* should be set for the countInputMode parameter and the \ref CY_TCPWM_INPUT_1
+* macro should be set for the countInput parameter in the configuration
+* structure of the appropriate mode(Counter
+* \ref group_tcpwm_data_structures_counter, PWM
+* \ref group_tcpwm_data_structures_pwm, or QuadDec
+* \ref group_tcpwm_data_structures_quaddec).
+*
+* \subsection group_tcpwm_pins Assign and Configure Pins
+* The dedicated TCPWM pins can be used. The HSIOM register must be configured to
+* connect the block to the pins. Use the \ref group_gpio driver API to do that.
+*
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Pins
+*
+* \subsection group_tcpwm_clock Assign Clock Divider
+* The clock source must be connected to proper working.
+* Any of the peripheral clock dividers could be used. Use the
+* \ref group_sysclk driver API to do that.
+*
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Clock
+*
+* \section group_tcpwm_more_information More Information
+*
+* For more information on the TCPWM peripheral, refer to the technical
+* reference manual (TRM).
+*
+* \section group_tcpwm_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>14.2</td>
+* <td>R</td>
+* <td>All non-null statements shall either: a) have at least one side-effect
+* however executed, or b) cause control flow to change.</td>
+* <td>The unused function parameters are cast to void. This statement
+* has no side-effect and is used to suppress a compiler warning.</td>
+* </tr>
+* </table>
+*
+* \section group_tcpwm_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Added header guards CY_IP_MXTCPWM.</td>
+* <td>To enable the PDL compilation with wounded out IP blocks.</td>
+* </tr>
+* <tr>
+* <td rowspan="2">1.10</td>
+* <td>Flattened the organization of the driver source code into the single
+* source directory and the single include directory.
+* </td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>1.0.1</td>
+* <td>Added a deviation to the MISRA Compliance section.
+* Added function-level code snippets.</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*/
+
+/** \} group_tcpwm */
+
+/**
+* \addtogroup group_tcpwm_common
+* Common API for the Timer Counter PWM Block.
+*
+* This is the common API that provides an interface to the TCPWM hardware.
+* The Timer Counter, PWM, and Quadrature Decoder drivers use this common API.
+* Most users will use individual drivers and do not need to use the common
+* API for the TCPWM.
+*
+* The functions and other declarations used in this part of the driver are in cy_tcpwm.h.
+* Include either of cy_tcpwm_counter.h, cy_tcpwm_pwm.h, cy_tcpwm_quaddec.h
+* depending on the desired functionality. You can also include cy_pdl.h
+* to get access to all functions and declarations in the PDL.
+*
+* \{
+* \defgroup group_tcpwm_macros_common Macros
+* \defgroup group_tcpwm_functions_common Functions
+* \defgroup group_tcpwm_data_structures_common Data Structures
+* \defgroup group_tcpwm_enums Enumerated Types
+*/
+
+
+#if !defined(CY_TCPWM_H)
+#define CY_TCPWM_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "cy_syslib.h"
+#include "cy_device_headers.h"
+#include "cy_device.h"
+
+#ifdef CY_IP_MXTCPWM
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+* \addtogroup group_tcpwm_macros_common
+* \{
+*/
+
+/** Driver major version */
+#define CY_TCPWM_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_TCPWM_DRV_VERSION_MINOR 10
+
+
+/******************************************************************************
+* API Constants
+******************************************************************************/
+
+/** TCPWM driver identifier */
+#define CY_TCPWM_ID (CY_PDL_DRV_ID(0x2DU))
+
+/** \defgroup group_tcpwm_input_selection TCPWM Input Selection
+* \{
+* Selects which input to use
+*/
+#define CY_TCPWM_INPUT_0 (0U) /**< Input is tied to logic 0 */
+#define CY_TCPWM_INPUT_1 (1U) /**< Input is tied to logic 1 */
+#define CY_TCPWM_INPUT_TRIG_0 (2U) /**< Input is connected to the trigger input 0 */
+#define CY_TCPWM_INPUT_TRIG_1 (3U) /**< Input is connected to the trigger input 1 */
+#define CY_TCPWM_INPUT_TRIG_2 (4U) /**< Input is connected to the trigger input 2 */
+#define CY_TCPWM_INPUT_TRIG_3 (5U) /**< Input is connected to the trigger input 3 */
+#define CY_TCPWM_INPUT_TRIG_4 (6U) /**< Input is connected to the trigger input 4 */
+#define CY_TCPWM_INPUT_TRIG_5 (7U) /**< Input is connected to the trigger input 5 */
+#define CY_TCPWM_INPUT_TRIG_6 (8U) /**< Input is connected to the trigger input 6 */
+#define CY_TCPWM_INPUT_TRIG_7 (9U) /**< Input is connected to the trigger input 7 */
+#define CY_TCPWM_INPUT_TRIG_8 (10U) /**< Input is connected to the trigger input 8 */
+#define CY_TCPWM_INPUT_TRIG_9 (11U) /**< Input is connected to the trigger input 9 */
+#define CY_TCPWM_INPUT_TRIG_10 (12U) /**< Input is connected to the trigger input 10 */
+#define CY_TCPWM_INPUT_TRIG_11 (13U) /**< Input is connected to the trigger input 11 */
+#define CY_TCPWM_INPUT_TRIG_12 (14U) /**< Input is connected to the trigger input 12 */
+#define CY_TCPWM_INPUT_TRIG_13 (15U) /**< Input is connected to the trigger input 13 */
+
+/** Input is defined by Creator, and Init() function does not need to configure input */
+#define CY_TCPWM_INPUT_CREATOR (0xFFFFFFFFU)
+/** \} group_tcpwm_input_selection */
+
+/**
+* \defgroup group_tcpwm_input_modes Input Modes
+* \{
+* Configures how TCPWM inputs behave
+*/
+/** A rising edge triggers the event (Capture, Start, Reload, etc..) */
+#define CY_TCPWM_INPUT_RISINGEDGE (0U)
+/** A falling edge triggers the event (Capture, Start, Reload, etc..) */
+#define CY_TCPWM_INPUT_FALLINGEDGE (1U)
+/** A rising edge or falling edge triggers the event (Capture, Start, Reload, etc..) */
+#define CY_TCPWM_INPUT_EITHEREDGE (2U)
+/** The event is triggered on each edge of the TCPWM clock if the input is high */
+#define CY_TCPWM_INPUT_LEVEL (3U)
+/** \} group_tcpwm_input_modes */
+
+/**
+* \defgroup group_tcpwm_interrupt_sources Interrupt Sources
+* \{
+* Interrupt Sources
+*/
+#define CY_TCPWM_INT_ON_TC (1U) /**< Interrupt on Terminal count(TC) */
+#define CY_TCPWM_INT_ON_CC (2U) /**< Interrupt on Compare/Capture(CC) */
+#define CY_TCPWM_INT_NONE (0U) /**< No Interrupt */
+#define CY_TCPWM_INT_ON_CC_OR_TC (3U) /**< Interrupt on TC or CC */
+/** \} group_tcpwm_interrupt_sources */
+
+
+/***************************************
+* Registers Constants
+***************************************/
+
+/**
+* \defgroup group_tcpwm_reg_const Default registers constants
+* \{
+* Default constants for CNT Registers
+*/
+#define CY_TCPWM_CNT_CTRL_DEFAULT (0x0U) /**< Default value for CTRL register */
+#define CY_TCPWM_CNT_COUNTER_DEFAULT (0x0U) /**< Default value for COUNTER register */
+#define CY_TCPWM_CNT_CC_DEFAULT (0xFFFFFFFFU) /**< Default value for CC register */
+#define CY_TCPWM_CNT_CC_BUFF_DEFAULT (0xFFFFFFFFU) /**< Default value for CC_BUFF register */
+#define CY_TCPWM_CNT_PERIOD_DEFAULT (0xFFFFFFFFU) /**< Default value for PERIOD register */
+#define CY_TCPWM_CNT_PERIOD_BUFF_DEFAULT (0xFFFFFFFFU) /**< Default value for PERIOD_BUFF register */
+#define CY_TCPWM_CNT_TR_CTRL0_DEFAULT (0x10U) /**< Default value for TR_CTRL0 register */
+#define CY_TCPWM_CNT_TR_CTRL1_DEFAULT (0x3FFU) /**< Default value for TR_CTRL1 register */
+#define CY_TCPWM_CNT_TR_CTRL2_DEFAULT (0x3FU) /**< Default value for TR_CTRL2 register */
+#define CY_TCPWM_CNT_INTR_DEFAULT (0x3U) /**< Default value for INTR register */
+#define CY_TCPWM_CNT_INTR_SET_DEFAULT (0x0U) /**< Default value for INTR_SET register */
+#define CY_TCPWM_CNT_INTR_MASK_DEFAULT (0x0U) /**< Default value for INTR_MASK register */
+/** \} group_tcpwm_reg_const */
+
+/** Position of Up counting counter status */
+#define CY_TCPWM_CNT_STATUS_UP_POS (0x1U)
+/** Initial value for the counter in the Up counting mode */
+#define CY_TCPWM_CNT_UP_INIT_VAL (0x0U)
+/** Initial value for the counter in the Up/Down counting modes */
+#define CY_TCPWM_CNT_UP_DOWN_INIT_VAL (0x1U)
+/** \} group_tcpwm_macros_common */
+
+
+/*******************************************************************************
+ * Enumerations
+ ******************************************************************************/
+
+ /**
+* \addtogroup group_tcpwm_enums
+* \{
+*/
+
+/** TCPWM status definitions */
+typedef enum
+{
+ CY_TCPWM_SUCCESS = 0x00U, /**< Successful */
+ CY_TCPWM_BAD_PARAM = CY_TCPWM_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< One or more invalid parameters */
+} cy_en_tcpwm_status_t;
+/** \} group_tcpwm_enums */
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_tcpwm_functions_common
+* \{
+*/
+
+__STATIC_INLINE void Cy_TCPWM_Enable_Multiple(TCPWM_Type *base, uint32_t counters);
+__STATIC_INLINE void Cy_TCPWM_Disable_Multiple(TCPWM_Type *base, uint32_t counters);
+__STATIC_INLINE void Cy_TCPWM_TriggerStart(TCPWM_Type *base, uint32_t counters);
+__STATIC_INLINE void Cy_TCPWM_TriggerReloadOrIndex(TCPWM_Type *base, uint32_t counters);
+__STATIC_INLINE void Cy_TCPWM_TriggerStopOrKill(TCPWM_Type *base, uint32_t counters);
+__STATIC_INLINE void Cy_TCPWM_TriggerCaptureOrSwap(TCPWM_Type *base, uint32_t counters);
+__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatus(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_ClearInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source);
+__STATIC_INLINE void Cy_TCPWM_SetInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source);
+__STATIC_INLINE void Cy_TCPWM_SetInterruptMask(TCPWM_Type *base, uint32_t cntNum, uint32_t mask);
+__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptMask(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatusMasked(TCPWM_Type const *base, uint32_t cntNum);
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Enable_Multiple
+****************************************************************************//**
+*
+* Enables the counter(s) in the TCPWM block. Multiple blocks can be started
+* simultaneously.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param counters
+* A bit field representing each counter in the TCPWM block.
+*
+* \funcusage
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Enable_Multiple
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_Enable_Multiple(TCPWM_Type *base, uint32_t counters)
+{
+ TCPWM_CTRL_SET(base) = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Disable_Multiple
+****************************************************************************//**
+*
+* Disables the counter(s) in the TCPWM block. Multiple TCPWM can be disabled
+* simultaneously.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param counters
+* A bit field representing each counter in the TCPWM block.
+*
+* \funcusage
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Disable_Multiple
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_Disable_Multiple(TCPWM_Type *base, uint32_t counters)
+{
+ TCPWM_CTRL_CLR(base) = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_TriggerStart
+****************************************************************************//**
+*
+* Triggers a software start on the selected TCPWMs.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param counters
+* A bit field representing each counter in the TCPWM block.
+*
+* \funcusage
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Enable_Multiple
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_TriggerStart(TCPWM_Type *base, uint32_t counters)
+{
+ TCPWM_CMD_START(base) = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_TriggerReloadOrIndex
+****************************************************************************//**
+*
+* Triggers a software reload event (or index in QuadDec mode).
+*
+* \param base
+* The pointer to a TCPWM instance
+*
+* \param counters
+* A bit field representing each counter in the TCPWM block.
+*
+* \funcusage
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_TriggerReloadOrIndex
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_TriggerReloadOrIndex(TCPWM_Type *base, uint32_t counters)
+{
+ TCPWM_CMD_RELOAD(base) = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_TriggerStopOrKill
+****************************************************************************//**
+*
+* Triggers a stop in the Timer Counter mode, or a kill in the PWM mode.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param counters
+* A bit field representing each counter in the TCPWM block.
+*
+* \funcusage
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_TriggerStopOrKill
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_TriggerStopOrKill(TCPWM_Type *base, uint32_t counters)
+{
+ TCPWM_CMD_STOP(base) = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_TriggerCaptureOrSwap
+****************************************************************************//**
+*
+* Triggers a Capture in the Timer Counter mode, and a Swap in the PWM mode.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param counters
+* A bit field representing each counter in the TCPWM block.
+*
+* \funcusage
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_Capture
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_TriggerCaptureOrSwap(TCPWM_Type *base, uint32_t counters)
+{
+ TCPWM_CMD_CAPTURE(base) = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_GetInterruptStatus
+****************************************************************************//**
+*
+* Returns which event triggered the interrupt.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* See \ref group_tcpwm_interrupt_sources
+*
+* \funcusage
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_GetInterruptStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatus(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(TCPWM_CNT_INTR(base, cntNum));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_ClearInterrupt
+****************************************************************************//**
+*
+* Clears Active Interrupt Source
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param source
+* source to clear. See \ref group_tcpwm_interrupt_sources
+*
+* \funcusage
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_ClearInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source)
+{
+ TCPWM_CNT_INTR(base, cntNum) = source;
+ (void)TCPWM_CNT_INTR(base, cntNum);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_SetInterrupt
+****************************************************************************//**
+*
+* Triggers an interrupt via a software write.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param source
+* The source to set an interrupt. See \ref group_tcpwm_interrupt_sources.
+*
+* \funcusage
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_SetInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_SetInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source)
+{
+ TCPWM_CNT_INTR_SET(base, cntNum) = source;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_SetInterruptMask
+****************************************************************************//**
+*
+* Sets an interrupt mask. A 1 means that when the event occurs, it will cause an
+* interrupt; a 0 means no interrupt will be triggered.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param mask
+*. See \ref group_tcpwm_interrupt_sources
+*
+* \funcusage
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_SetInterruptMask
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_SetInterruptMask(TCPWM_Type *base, uint32_t cntNum, uint32_t mask)
+{
+ TCPWM_CNT_INTR_MASK(base, cntNum) = mask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_GetInterruptMask
+****************************************************************************//**
+*
+* Returns the interrupt mask.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* Interrupt Mask. See \ref group_tcpwm_interrupt_sources
+*
+* \funcusage
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_SetInterruptMask
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptMask(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(TCPWM_CNT_INTR_MASK(base, cntNum));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns which masked interrupt triggered the interrupt.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* Interrupt Mask. See \ref group_tcpwm_interrupt_sources
+*
+* \funcusage
+* \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatusMasked(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(TCPWM_CNT_INTR_MASKED(base, cntNum));
+}
+
+/** \} group_tcpwm_functions_common */
+
+/** \} group_tcpwm_common */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_IP_MXTCPWM */
+
+#endif /* CY_TCPWM_H */
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_tcpwm_pwm.h b/platform/ext/target/psoc64/Native_Driver/include/cy_tcpwm_pwm.h
new file mode 100644
index 0000000000..b2dafd039e
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_tcpwm_pwm.h
@@ -0,0 +1,633 @@
+/***************************************************************************//**
+* \file cy_tcpwm_pwm.h
+* \version 1.10.1
+*
+* \brief
+* The header file of the TCPWM PWM driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#if !defined(CY_TCPWM_PWM_H)
+#define CY_TCPWM_PWM_H
+
+#include "cy_tcpwm.h"
+
+#ifdef CY_IP_MXTCPWM
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+* \addtogroup group_tcpwm_pwm
+* Driver API for PWM.
+*
+* The functions and other declarations used in this part of the driver are in cy_tcpwm_pwm.h.
+* You can also include cy_pdl.h (ModusToolbox only) to get access to all
+* functions and declarations in the PDL.
+* \{
+*/
+
+/**
+* \defgroup group_tcpwm_macros_pwm Macros
+* \defgroup group_tcpwm_functions_pwm Functions
+* \defgroup group_tcpwm_data_structures_pwm Data Structures
+* \} */
+
+/**
+* \addtogroup group_tcpwm_data_structures_pwm
+* \{
+*/
+
+/** PWM configuration structure */
+typedef struct cy_stc_tcpwm_pwm_config
+{
+ uint32_t pwmMode; /**< Sets the PWM mode. See \ref group_tcpwm_pwm_modes */
+ /** Sets the clock prescaler inside the TCWPM block. See \ref group_tcpwm_pwm_clk_prescalers */
+ uint32_t clockPrescaler;
+ uint32_t pwmAlignment; /**< Sets the PWM alignment. See \ref group_tcpwm_pwm_alignment */
+ uint32_t deadTimeClocks; /**< The number of dead time-clocks if PWM with dead time is chosen */
+ uint32_t runMode; /**< Sets the PWM run mode. See \ref group_tcpwm_pwm_run_modes */
+ uint32_t period0; /**< Sets the period0 of the pwm */
+ uint32_t period1; /**< Sets the period1 of the pwm */
+ bool enablePeriodSwap; /**< Enables swapping of period 0 and period 1 on terminal count */
+ uint32_t compare0; /**< Sets the value for Compare0 */
+ uint32_t compare1; /**< Sets the value for Compare1 */
+ bool enableCompareSwap; /**< If enabled, the compare values are swapped on the terminal count */
+ /** Enables an interrupt on the terminal count, capture or compare. See \ref group_tcpwm_interrupt_sources */
+ uint32_t interruptSources;
+ uint32_t invertPWMOut; /**< Inverts the PWM output */
+ uint32_t invertPWMOutN; /**< Inverts the PWM_n output */
+ uint32_t killMode; /**< Configures the PWM kill modes. See \ref group_tcpwm_pwm_kill_modes */
+ uint32_t swapInputMode; /**< Configures how the swap input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the swap uses. Inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t swapInput;
+ uint32_t reloadInputMode; /**< Configures how the reload input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the reload uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t reloadInput;
+ uint32_t startInputMode; /**< Configures how the start input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the start uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t startInput;
+ uint32_t killInputMode; /**< Configures how the kill input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the kill uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t killInput;
+ uint32_t countInputMode; /**< Configures how the count input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the count uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t countInput;
+}cy_stc_tcpwm_pwm_config_t;
+/** \} group_tcpwm_data_structures_pwm */
+
+/**
+* \addtogroup group_tcpwm_macros_pwm
+* \{
+* \defgroup group_tcpwm_pwm_run_modes PWM run modes
+* \{
+* Run modes for the pwm timer.
+*/
+#define CY_TCPWM_PWM_ONESHOT (1U) /**< Counter runs once and then stops */
+#define CY_TCPWM_PWM_CONTINUOUS (0U) /**< Counter runs forever */
+/** \} group_tcpwm_pwm_run_modes */
+
+/** \defgroup group_tcpwm_pwm_modes PWM modes
+* \{
+* Sets the PWM modes.
+*/
+#define CY_TCPWM_PWM_MODE_PWM (4U) /**< Standard PWM Mode*/
+#define CY_TCPWM_PWM_MODE_DEADTIME (5U) /**< PWM with deadtime mode*/
+#define CY_TCPWM_PWM_MODE_PSEUDORANDOM (6U) /**< Pseudo Random PWM */
+/** \} group_tcpwm_pwm_modes */
+
+/** \defgroup group_tcpwm_pwm_alignment PWM Alignment
+* Sets the alignment of the PWM.
+* \{
+*/
+#define CY_TCPWM_PWM_LEFT_ALIGN (0U) /**< PWM is left aligned, meaning it starts high */
+#define CY_TCPWM_PWM_RIGHT_ALIGN (1U) /**< PWM is right aligned, meaning it starts low */
+/** PWM is centered aligned, terminal count only occurs on underflow */
+#define CY_TCPWM_PWM_CENTER_ALIGN (2U)
+/** PWM is asymmetrically aligned, terminal count occurs on overflow and underflow */
+#define CY_TCPWM_PWM_ASYMMETRIC_ALIGN (3U)
+/** \} group_tcpwm_pwm_alignment */
+
+/** \defgroup group_tcpwm_pwm_kill_modes PWM kill modes
+* Sets the kill mode for the PWM.
+* \{
+*/
+#define CY_TCPWM_PWM_STOP_ON_KILL (2U) /**< PWM stops counting on kill */
+#define CY_TCPWM_PWM_SYNCH_KILL (1U) /**< PWM output is killed after next TC*/
+#define CY_TCPWM_PWM_ASYNC_KILL (0U) /**< PWM output is killed instantly */
+/** \} group_tcpwm_pwm_kill_modes */
+
+/** \defgroup group_tcpwm_pwm_clk_prescalers PWM CLK Prescaler values
+* \{
+* Clock prescaler values.
+*/
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_1 (0U) /**< Divide by 1 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_2 (1U) /**< Divide by 2 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_4 (2U) /**< Divide by 4 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_8 (3U) /**< Divide by 8 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_16 (4U) /**< Divide by 16 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_32 (5U) /**< Divide by 32 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_64 (6U) /**< Divide by 64 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_128 (7U) /**< Divide by 128 */
+/** \} group_tcpwm_pwm_clk_prescalers */
+
+/** \defgroup group_tcpwm_pwm_output_invert PWM output invert
+* \{
+* Output invert modes.
+*/
+#define CY_TCPWM_PWM_INVERT_ENABLE (1U) /**< Invert the output mode */
+#define CY_TCPWM_PWM_INVERT_DISABLE (0U) /**< Do not invert the output mode */
+/** \} group_tcpwm_pwm_output_invert */
+
+/** \defgroup group_tcpwm_pwm_status PWM Status
+* \{
+* The counter status.
+*/
+#define CY_TCPWM_PWM_STATUS_DOWN_COUNTING (0x1UL) /**< PWM is down counting */
+#define CY_TCPWM_PWM_STATUS_UP_COUNTING (0x2UL) /**< PWM is up counting */
+#define CY_TCPWM_PWM_STATUS_COUNTER_RUNNING (TCPWM_CNT_STATUS_RUNNING_Msk) /**< PWM counter is running */
+/** \} group_tcpwm_pwm_status */
+/** \} group_tcpwm_macros_pwm */
+
+
+/***************************************
+* Registers Constants
+***************************************/
+
+/** \cond INTERNAL */
+#define CY_TCPWM_PWM_CTRL_SYNC_KILL_OR_STOP_ON_KILL_POS (2U)
+#define CY_TCPWM_PWM_CTRL_SYNC_KILL_OR_STOP_ON_KILL_MASK (0x3UL << CY_TCPWM_PWM_CTRL_SYNC_KILL_OR_STOP_ON_KILL_POS)
+
+#define CY_TCPWM_PWM_TR_CTRL2_SET (0UL) /**< Set define for PWM output signal configuration */
+#define CY_TCPWM_PWM_TR_CTRL2_CLEAR (1UL) /**< Clear define for PWM output signal configuration */
+#define CY_TCPWM_PWM_TR_CTRL2_INVERT (2UL) /**< Invert define for PWM output signal configuration */
+#define CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE (3UL) /**< No change define for PWM output signal configuration */
+
+/** The configuration of PWM output signal in Pseudo Random Mode */
+#define CY_TCPWM_PWM_MODE_PR (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE))
+
+/** The configuration of PWM output signal for Left alignment */
+#define CY_TCPWM_PWM_MODE_LEFT (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_CLEAR) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_SET) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE))
+
+/** The configuration of PWM output signal for Right alignment */
+#define CY_TCPWM_PWM_MODE_RIGHT (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_SET) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_CLEAR))
+
+/** The configuration of PWM output signal for Center and Asymmetric alignment */
+#define CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_INVERT) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_SET) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_CLEAR))
+/** \endcond */
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_tcpwm_functions_pwm
+* \{
+*/
+
+cy_en_tcpwm_status_t Cy_TCPWM_PWM_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config);
+void Cy_TCPWM_PWM_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config);
+__STATIC_INLINE void Cy_TCPWM_PWM_Enable(TCPWM_Type *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_Disable(TCPWM_Type *base, uint32_t cntNum);
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetStatus(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_SetCompare0(TCPWM_Type *base, uint32_t cntNum, uint32_t compare0);
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare0(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_SetCompare1(TCPWM_Type *base, uint32_t cntNum, uint32_t compare1);
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare1(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_EnableCompareSwap(TCPWM_Type *base, uint32_t cntNum, bool enable);
+__STATIC_INLINE void Cy_TCPWM_PWM_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count);
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCounter(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod0(TCPWM_Type *base, uint32_t cntNum, uint32_t period0);
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod0(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod1(TCPWM_Type *base, uint32_t cntNum, uint32_t period1);
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod1(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_EnablePeriodSwap(TCPWM_Type *base, uint32_t cntNum, bool enable);
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_Enable
+****************************************************************************//**
+*
+* Enables the counter in the TCPWM block for the PWM operation.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_Init
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_Enable(TCPWM_Type *base, uint32_t cntNum)
+{
+ TCPWM_CTRL_SET(base) = (1UL << cntNum);
+}
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_Disable
+****************************************************************************//**
+*
+* Disables the counter in the TCPWM block.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_DeInit
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_Disable(TCPWM_Type *base, uint32_t cntNum)
+{
+ TCPWM_CTRL_CLR(base) = (1UL << cntNum);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_GetStatus
+****************************************************************************//**
+*
+* Returns the status of the PWM.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The status. See \ref group_tcpwm_pwm_status
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_GetStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetStatus(TCPWM_Type const *base, uint32_t cntNum)
+{
+ uint32_t status = TCPWM_CNT_STATUS(base, cntNum);
+
+ /* Generates proper up counting status, does not generated by HW */
+ status &= ~CY_TCPWM_PWM_STATUS_UP_COUNTING;
+ status |= ((~status & CY_TCPWM_PWM_STATUS_DOWN_COUNTING & (status >> TCPWM_CNT_STATUS_RUNNING_Pos)) <<
+ CY_TCPWM_CNT_STATUS_UP_POS);
+
+ return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_SetCompare0
+****************************************************************************//**
+*
+* Sets the compare value for Compare0 when the compare mode enabled.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param compare0
+* The Compare0 value.
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetCompare0
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_SetCompare0(TCPWM_Type *base, uint32_t cntNum, uint32_t compare0)
+{
+ TCPWM_CNT_CC(base, cntNum) = compare0;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_GetCompare0
+****************************************************************************//**
+*
+* Returns compare value 0.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* Compare value 0.
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetCompare0
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare0(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(TCPWM_CNT_CC(base, cntNum));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_SetCompare1
+****************************************************************************//**
+*
+* Sets the compare value for Compare1 when the compare mode is enabled.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param compare1
+* The Compare1 value.
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetCompare1
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_SetCompare1(TCPWM_Type *base, uint32_t cntNum, uint32_t compare1)
+{
+ TCPWM_CNT_CC_BUFF(base, cntNum) = compare1;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_GetCompare1
+****************************************************************************//**
+*
+* Returns compare value 1.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* Compare value 1.
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetCompare1
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare1(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(TCPWM_CNT_CC_BUFF(base, cntNum));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_EnableCompareSwap
+****************************************************************************//**
+*
+* Enables the comparison swap on OV and/or UN, depending on the PWM alignment.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param enable
+* true = swap enabled; false = swap disabled
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_EnableCompareSwap
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_EnableCompareSwap(TCPWM_Type *base, uint32_t cntNum, bool enable)
+{
+ if (enable)
+ {
+ TCPWM_CNT_CTRL(base, cntNum) |= TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk;
+ }
+ else
+ {
+ TCPWM_CNT_CTRL(base, cntNum) &= ~TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_SetCounter
+****************************************************************************//**
+*
+* Sets the value of the counter.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param count
+* The value to write into the counter.
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetCounter
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count)
+{
+ TCPWM_CNT_COUNTER(base, cntNum) = count;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_GetCounter
+****************************************************************************//**
+*
+* Returns the value in the counter.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The current counter value.
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_GetCounter
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCounter(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(TCPWM_CNT_COUNTER(base, cntNum));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_SetPeriod0
+****************************************************************************//**
+*
+* Sets the value of the period register.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param period0
+* The value to write into a period.
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetPeriod0
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod0(TCPWM_Type *base, uint32_t cntNum, uint32_t period0)
+{
+ TCPWM_CNT_PERIOD(base, cntNum) = period0;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_GetPeriod0
+****************************************************************************//**
+*
+* Returns the value in the period register.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The current period value.
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetPeriod0
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod0(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(TCPWM_CNT_PERIOD(base, cntNum));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_SetPeriod1
+****************************************************************************//**
+*
+* Sets the value of the period register.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param period1
+* The value to write into a period1.
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetPeriod1
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod1(TCPWM_Type *base, uint32_t cntNum, uint32_t period1)
+{
+ TCPWM_CNT_PERIOD_BUFF(base, cntNum) = period1;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_GetPeriod1
+****************************************************************************//**
+*
+* Returns the value in the period register.
+*
+* \param base
+* The pointer to a COUNTER PWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The current period value.
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_SetPeriod1
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod1(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(TCPWM_CNT_PERIOD_BUFF(base, cntNum));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_EnablePeriodSwap
+****************************************************************************//**
+*
+* Enables a period swap on OV and/or UN, depending on the PWM alignment
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param enable
+* true = swap enabled; false = swap disabled
+*
+* \funcusage
+* \snippet tcpwm/pwm/snippet/main.c snippet_Cy_TCPWM_PWM_EnablePeriodSwap
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_EnablePeriodSwap(TCPWM_Type *base, uint32_t cntNum, bool enable)
+{
+ if (enable)
+ {
+ TCPWM_CNT_CTRL(base, cntNum) |= TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk;
+ }
+ else
+ {
+ TCPWM_CNT_CTRL(base, cntNum) &= ~TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk;
+ }
+}
+
+/** \} group_tcpwm_functions_pwm */
+
+/** \} group_tcpwm_pwm */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_IP_MXTCPWM */
+
+#endif /* CY_TCPWM_PWM_H */
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_trigmux.h b/platform/ext/target/psoc64/Native_Driver/include/cy_trigmux.h
new file mode 100644
index 0000000000..f6a68c2d04
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_trigmux.h
@@ -0,0 +1,314 @@
+/*******************************************************************************
+* \file cy_trigmux.h
+* \version 1.20
+*
+* This file provides constants and parameter values for the Trigger multiplexer driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_trigmux
+* \{
+* The trigger multiplexer provides access to the multiplexer that selects a set
+* of trigger output signals from different peripheral blocks to route them to the
+* specific trigger input of another peripheral block.
+*
+* The functions and other declarations used in this driver are in cy_trigmux.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions
+* and declarations in the PDL.
+*
+* The TrigMux driver is based on the trigger multiplexer's hardware block.
+* The Trigger multiplexer block consists of multiple trigger multiplexers.
+* These trigger multiplexers are grouped in trigger groups. All the trigger
+* multiplexers in the trigger group share similar input options.
+*
+* For PERI_ver1:
+* The trigger multiplexer groups are either reduction multiplexers or distribution
+* multiplexers. The figure below illustrates a generic trigger multiplexer block
+* implementation with a reduction multiplexer layer of N trigger groups and a
+* distribution multiplexer layer of M trigger groups.
+* \image html trigmux_architecture.png
+* The reduction multiplexer groups have input options that are the trigger outputs
+* coming from the different peripheral blocks and the reduction multiplexer groups
+* route them to intermediate signals. The distribution multiplexer groups have input
+* options from these intermediate signals and route them back to multiple peripheral
+* blocks as their trigger inputs.
+*
+* For PERI_ver2:
+* The trigger multiplexer groups structure is flat - all the groups are essentially
+* distribution multiplexers (there are no any intermediate trigger signals), so the
+* structure is simpler in comparison with PERI_ver1, however a bit less flexible.
+* Additionally there are another type of trigger interconnections: one-to-one
+* trigger lines. These are not multiplexers, only single trigger wires from/to
+* the dedicated peripherals. Multiple groups of one-to-one trigger lines
+* significantly improve the whole triggering interconnect system flexibility.
+*
+* The trigger architecture of the PSoC device is explained in the technical reference
+* manual (TRM). Refer to the TRM to better understand the trigger multiplexer routing
+* architecture available.
+*
+* \section group_trigmux_section_Configuration_Considerations Configuration Considerations
+*
+* For PERI_ver1:
+* To route a trigger signal from one peripheral in the PSoC
+* to another, the user must configure a reduction multiplexer and a distribution
+* multiplexer. The \ref Cy_TrigMux_Connect is used to configure a trigger multiplexer connection.
+* The user will need two calls of this API, one for the reduction multiplexer and another
+* for the distribution multiplexer, to achieve the trigger connection from a source
+* peripheral to a destination peripheral.
+*
+* For PERI_ver2:
+* To route a trigger signal from one peripheral in the PSoC device to another, the user can configure
+* either a trigger multiplexer using \ref Cy_TrigMux_Connect or a one-to-one trigger line
+* using \ref Cy_TrigMux_Select. Only one function call is required to connect one peripheral
+* to another (unlike for PERI_ver1).
+*
+* The Cy_TrigMux_Connect() function has two main parameters, inTrig and outTrig that
+* refer to the input and output trigger lines connected using the multiplexer.
+* These parameters are represented in the following format:<br>
+* For PERI_ver1:
+* \image html trigmux_parameter_30.png
+* For PERI_ver2:
+* \image html trigmux_parameter_30_2.png
+* In addition, the \ref Cy_TrigMux_Connect function also has an invert and trigger type parameter.
+* Refer to the API reference for a detailed description of this parameter.
+* All the constants associated with the different trigger signals in the system
+* (input and output) are defined as constants in the device configuration header file.
+*
+* For PERI_ver1:
+* The constants for TrigMux in the device configuration header file are divided into four
+* types based on the signal being input/output and being part of a reduction/distribution
+* trigger multiplexer.
+*
+* The four types of the input/output parameters are:
+* 1) The parameters for the reduction multiplexer's inputs (input signals of TrigMux);
+* 2) The parameters for the reduction multiplexer's outputs (intermediate signals);
+* 3) The parameters for the distribution multiplexer's inputs (intermediate signals);
+* 4) The parameters for the distribution multiplexer's outputs (output signals of TrigMux).
+*
+* For PERI_ver2:
+* There are two types of TrigMux signal definitions in the device configuration header:
+* 1) The parameters for the trigger interconnection system input signals.
+* 2) The parameters for the trigger interconnection system output signals.
+* Also there are separate groups of trigger multiplexer input/outputs and groups of
+* trigger one-to-one line input/outputs.
+*
+* Refer to the TRM for a more detailed description of this architecture and different options.
+*
+* The steps to connect one peripheral block to the other:
+*
+* For PERI_ver1:
+* Step 1. Find the trigger group number in the Trigger Group Inputs section of the device
+* configuration header file that corresponds to the output of the first peripheral block.
+* For example, TRIG11_IN_TCPWM0_TR_OVERFLOW0 input of the reduction multiplexers belongs
+* to Trigger Group 11.
+*
+* Step 2. Find the trigger group number in the Trigger Group Outputs section of the device
+* configuration header file that corresponds to the input of the second peripheral block.
+* For example, TRIG0_OUT_CPUSS_DW0_TR_IN0 output of the distribution multiplexer belongs to
+* Trigger Group 0.
+*
+* Step 3. Find the same trigger group number in the Trigger Group Inputs section of the
+* device configuration header file that corresponds to the trigger group number found in
+* Step 1. Select the reduction multiplexer output that can be connected to the trigger group
+* found in Step 2. For example, TRIG0_IN_TR_GROUP11_OUTPUT0 means that Reduction Multiplexer
+* Output 15 of Trigger Group 13 can be connected to Trigger Group 0.
+*
+* Step 4. Find the same trigger group number in the Trigger Group Outputs section of the
+* device configuration header file that corresponds to the trigger group number found in Step 2.
+* Select the distribution multiplexer input that can be connected to the trigger group found
+* in Step 1. For example, TRIG11_OUT_TR_GROUP0_INPUT9 means that the Distribution Multiplexer
+* Input 42 of Trigger Group 0 can be connected to the output of the reduction multiplexer
+* in Trigger Group 13 found in Step 3.
+*
+* Step 5. Call Cy_TrigMux_Connect() API twice: the first call - with the constants for the
+* inTrig and outTrig parameters found in Steps 1 and Step 4, the second call - with the
+* constants for the inTrig and outTrig parameters found in Steps 2 and Step 3.
+* For example,
+* Cy_TrigMux_Connect(TRIG11_IN_TCPWM0_TR_OVERFLOW0, TRIG11_OUT_TR_GROUP0_INPUT9,
+* false, TRIGGER_TYPE_LEVEL);
+* Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP11_OUTPUT0, TRIG0_OUT_CPUSS_DW0_TR_IN0,
+* false, TRIGGER_TYPE_EDGE);
+*
+* For PERI_ver2:
+* Step 1. Find the trigger group number in the Trigger Group Inputs section of the device
+* configuration header file that corresponds to the output of the first peripheral block.
+* For example, TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW0 TrigMux input belongs to Trigger Group 0.
+* It is the same TCPWM0 counter 0 overflow output (as in the example for PERI_ver1).
+*
+* Step 2. Find the same trigger group number in the Trigger Group Outputs section of the
+* device configuration header file that corresponds to the trigger group number found in
+* Step 1. Select the TrigMux output that can be connected to the second peripheral block.
+* For example, TRIG_OUT_MUX_0_PDMA0_TR_IN0 means that the trigger multiplexer
+* Output 0 of Trigger Group 0 can be connected to the DW0 channel 0 trigger input
+* (the same DMA channel as mentioned in the example for PERI_ver1).
+*
+* Step 3. Call Cy_TrigMux_Connect() API once:
+* Cy_TrigMux_Connect(TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW0, TRIG_OUT_MUX_0_PDMA0_TR_IN0,
+* false, TRIGGER_TYPE_EDGE);
+*
+* \section group_trigmux_more_information More Information
+* For more information on the TrigMux peripheral, refer to the technical reference manual (TRM).
+*
+* \section group_trigmux_MISRA MISRA-C Compliance
+* The TrigMux driver does not have any specific deviations.
+*
+* \section group_trigmux_Changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td rowspan="3">1.20</td>
+* <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td>Added new API functions:
+* - \ref Cy_TrigMux_Select
+* - \ref Cy_TrigMux_Deselect
+* - \ref Cy_TrigMux_SetDebugFreeze
+*
+* Modified the \ref Cy_TrigMux_SwTrigger API function logic.
+* </td>
+* <td>New devices support.</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Renamed the internal macro in Cy_TrigMux_Connect()
+* function to CY_TRIGMUX_IS_TRIGTYPE_VALID.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.10</td>
+* <td>The input/output bit in the trigLine parameter of the
+* Cy_TrigMux_SwTrigger() function is changed to 30.<br>
+* The invert parameter type is changed to bool.<br>
+* Added input parameter validation to the API functions.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_trigmux_macros Macros
+* \defgroup group_trigmux_functions Functions
+* \defgroup group_trigmux_enums Enumerated Types
+*/
+
+#if !defined(CY_TRIGMUX_H)
+#define CY_TRIGMUX_H
+
+
+#include "cy_syslib.h"
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/******************************************************************************
+ * Macros
+ *****************************************************************************/
+
+/**
+* \addtogroup group_trigmux_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_TRIGMUX_DRV_VERSION_MAJOR 1
+
+/** The driver minor version */
+#define CY_TRIGMUX_DRV_VERSION_MINOR 20
+
+/** TRIGMUX PDL ID */
+#define CY_TRIGMUX_ID CY_PDL_DRV_ID(0x33UL) /**< The trigger multiplexer driver identifier */
+
+/** Values for the cycles parameter in the \ref Cy_TrigMux_SwTrigger() function */
+#define CY_TRIGGER_INFINITE (255UL) /**< The trigger will be active until the user clears it or a hardware deactivates it. */
+#define CY_TRIGGER_DEACTIVATE (0UL) /**< Use this parameter value to deactivate the trigger. */
+#define CY_TRIGGER_TWO_CYCLES (2UL) /**< The only valid cycles number value for PERI_ver2. */
+
+/** \} group_trigmux_macros */
+
+/** \cond BWC macros */
+#define CY_TR_MUX_TR_INV_ENABLE (0x01u)
+#define CY_TR_MUX_TR_INV_DISABLE (0x00u)
+#define CY_TR_ACTIVATE_DISABLE (0x00u)
+#define CY_TR_ACTIVATE_ENABLE (0x01u)
+#define CY_TR_GROUP_MASK (0x0F00u)
+#define CY_TR_MASK (0x007Fu)
+#define CY_TR_GROUP_SHIFT (0x08u)
+#define CY_TR_OUT_CTL_MASK (0x40000000uL)
+#define CY_TR_OUT_CTL_SHIFT (30u)
+#define CY_TR_PARAM_MASK (CY_TR_OUT_CTL_MASK | CY_TR_GROUP_MASK | CY_TR_MASK)
+#define CY_TR_CYCLES_MIN (0u)
+#define CY_TR_CYCLES_MAX (255u)
+/** \endcond */
+
+
+/**
+* \addtogroup group_trigmux_enums
+* \{
+*/
+
+/******************************************************************************
+ * Enumerations
+ *****************************************************************************/
+
+/** The TRIGMUX error codes. */
+typedef enum
+{
+ CY_TRIGMUX_SUCCESS = 0x0UL, /**< Successful */
+ CY_TRIGMUX_BAD_PARAM = CY_TRIGMUX_ID | CY_PDL_STATUS_ERROR | 0x1UL, /**< One or more invalid parameters */
+ CY_TRIGMUX_INVALID_STATE = CY_TRIGMUX_ID | CY_PDL_STATUS_ERROR | 0x2UL /**< Operation not set up or is in an improper state */
+} cy_en_trigmux_status_t;
+
+/** \} group_trigmux_enums */
+
+/**
+* \addtogroup group_trigmux_functions
+* \{
+*/
+
+cy_en_trigmux_status_t Cy_TrigMux_Connect(uint32_t inTrig, uint32_t outTrig, bool invert, en_trig_type_t trigType);
+cy_en_trigmux_status_t Cy_TrigMux_SwTrigger(uint32_t trigLine, uint32_t cycles);
+cy_en_trigmux_status_t Cy_TrigMux_Select(uint32_t outTrig, bool invert, en_trig_type_t trigType);
+cy_en_trigmux_status_t Cy_TrigMux_Deselect(uint32_t outTrig);
+cy_en_trigmux_status_t Cy_TrigMux_SetDebugFreeze(uint32_t outTrig, bool enable);
+
+/** \} group_trigmux_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_TRIGMUX_H */
+
+/** \} group_trigmux */
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_usbfs_dev_drv.h b/platform/ext/target/psoc64/Native_Driver/include/cy_usbfs_dev_drv.h
new file mode 100644
index 0000000000..ef485ccf9d
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_usbfs_dev_drv.h
@@ -0,0 +1,2414 @@
+/***************************************************************************//**
+* \file cy_usbfs_dev_drv.h
+* \version 2.20
+*
+* Provides API declarations of the USBFS driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+
+/**
+* \addtogroup group_usbfs_dev_drv
+* \{
+* The USBFS driver provides an API to interact with a fixed-function USB block.
+*
+* The functions and other declarations used in this driver are in cy_usbfs_dev_drv.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions
+* and declarations in the PDL.
+*
+* The USB block supports Host and Device modes of operation. This version of the
+* driver supports only Device mode.
+*
+* <b>Features:</b>
+* * Complies with USB Specification 2.0
+* * Supports full-speed peripheral device operation with a signaling bit
+* rate of 12 Mbps.
+* * Supports eight data endpoints and one control endpoint.
+* * Provides a shared 512-byte buffer for data endpoints.
+* * Provides dedicated 8-byte memory for control endpoint (EP0).
+* * Supports four types of transfers: bulk, interrupt, isochronous, and control
+* * Supports bus- and self-powered configurations
+* * Supports USB suspend, resume, and remove wakeup.
+* * Supports three types of logical transfer modes:
+* * CPU (No DMA) mode (Mode 1).
+* * Manual DMA mode (Mode 2).
+* * Automatic DMA mode (Mode 3).
+* * Supports the maximum packet size:
+* * 512 bytes using Mode 1 and Mode 2.
+* * 1023 bytes for isochronous transfer using Mode 3.
+* * Provides integrated 22 Ohm USB termination resistors on D+ and D- lines,
+* and 1.5 kOhm pull-up resistor on the D+ line.
+* * Supports USB 2.0 Link Power Management (LPM).
+*
+*
+********************************************************************************
+* \section group_usbfs_dev_drv_use_cases Common Use Cases
+********************************************************************************
+*
+* <b>The primary usage model for the USBFS driver is to provide a defined API
+* interface to
+* <a href="https://cypresssemiconductorco.github.io/usbdev/usbfs_dev_api_reference_manual/html/index.html" target="_blank">
+* USB Device Middleware</a> component that works on top of it.</b> \n
+* The driver also provides an API interface for the application to implement the required
+* functionality:
+* * \ref group_usbfs_dev_drv_callbacks
+* * \ref group_usbfs_dev_drv_low_power
+* * \ref group_usbfs_dev_drv_lpm
+* * \ref group_usbfs_dev_drv_vbus
+*
+********************************************************************************
+* \section group_usbfs_dev_drv_configuration Configuration Considerations
+********************************************************************************
+*
+* This section explains how to configure the USBFS driver and system resources to
+* enable USB Device operation. The pointers to the populated \ref cy_stc_usbfs_dev_drv_config_t configuration
+* structure and allocated context are passed in the middleware initialization.
+* function Cy_USB_Dev_Init. After middleware initialization, it calls
+* \ref Cy_USBFS_Dev_Drv_Init to initialize the USBFS driver for Device operation.
+
+********************************************************************************
+* \subsection group_usbfs_dev_drv_config Configure Driver
+********************************************************************************
+*
+* To configure the USBFS driver in Device mode, the configuration structure
+* \ref cy_stc_usbfs_dev_drv_config_t parameters must be populated.
+* The configuration structure content significantly depends on the selected
+* endpoints management mode parameter:
+*
+* * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU \n
+* The <i>epAccess, intrLevelSel and enableLpm</i> must be provided. All
+* other parameters are do not cares for this mode. Refer to section
+* \ref group_usbfs_dev_drv_intr to get information about <i>intrLevelSel</i>
+* configuration.
+*
+* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgCpu
+*
+* * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA \n
+* To enable DMA operation, the DMA channels must be assigned for each endpoint
+* to be used. Each DMA channel needs a single DMA descriptor to
+* operate. The USBFS driver defines the DMA configuration structure
+* \ref cy_stc_usbfs_dev_drv_dma_config_t to be populated for each DMA
+* channel.
+* The code example below provides an initialized USBFS driver DMA configuration
+* structure:
+*
+* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDma_DmaInit
+*
+* The pointers to the DMA configuration structure are required into the
+* \ref cy_stc_usbfs_dev_drv_config_t USBFS driver configuration structure
+* to allow the USBFS driver to use DMA channels for used endpoints.
+* The <i>dmaConfig[0]</i> field expects a pointer to the DMA configuration for
+* data endpoint 1, the <i>dmaConfig[1]</i> field pointer to the DMA configuration
+* for data endpoint 2, and so on up to data endpoint 8.
+* The code example below provides an initialized USBFS driver configuration
+* structure which uses endpoint 1:
+*
+* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDma
+*
+* * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO \n
+* DMA Automatic mode needs a DMA channels configuration similar to the described
+* above. But it also requires one more DMA descriptor for each DMA channel and
+* DMA output trigger multiplexer. Refer to the \ref group_usbfs_dev_drv_dma section,
+* for more detail about the trigger multiplexer .
+* The code example below provides an initialized USBFS driver DMA configuration
+* structure:
+*
+* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDmaAuto_DmaInit
+*
+* The driver requires a buffer for data endpoints to operate. This buffer must be
+* allocated by the user. The buffer size is equal to the sum of all used
+* endpoints maximum packet sizes. If an endpoint belongs to more than
+* one alternate setting, select the greatest maximum packet size for this
+* endpoint. The driver configuration structure \ref cy_stc_usbfs_dev_drv_config_t
+* parameters <i>epBuffer and epBufferSize</i> pass the buffer to the driver.
+*
+* The code example below provides an initialized USBFS driver configuration
+* structure that uses data endpoint 1 with a maximum packet size of 63 bytes and
+* set 16-bit access:
+*
+* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDmaAuto
+*
+*
+* \note
+* The endpoint buffer allocation depends on the access type used: 8-bit or 16-bit.
+* Refer to \ref group_usbfs_dev_drv_ep_management_buf_access for more information.
+*
+********************************************************************************
+* \subsection group_usbfs_dev_drv_pins Assign and Configure Pins
+********************************************************************************
+*
+* Only dedicated USB pins can be used for USB operation. Keep the default
+* USB pins configuration because after the USBFS driver initializes, the
+* USB block takes control over the pins and drives them properly.
+*
+********************************************************************************
+* \subsection group_usbfs_dev_drv_clock Assign and Configure Clocks
+********************************************************************************
+*
+* The USB hardware block requires two clock sources for operation:
+* * Clk_HF3 (USB clock) must be 48 MHz. The accuracy of the USB clock must be
+* within -/+ 0.25%. Note that Clk_HF3 has an integer divider so the input
+* clock can be a multiple of 48. The valid options to get an internal USB
+* clock are PLL or ECO.\n
+* <b>The typical configuration is:</b> the IMO output is used by the PLL to
+* generate Clk_HF3 (USB clock). To meet USB clock accuracy requirements
+* the IMO must be trimmed with USB SOF signal. Therefore, the driver
+* \ref Cy_USBFS_Dev_Drv_Init function enables the IMO trim from USB.
+*
+* * Divided Clk_Peri clock (PCLK_USB_CLOCK_DEV_BRS) equal to 100 kHz
+* used to detect a Bus Reset event. Use one of the 8-bit or 16-bit dividers
+* to provide required clock frequency.
+*
+* The code example below shows the connection source path 1
+* (which expected provide 48 MHz -/+ 0.25% clock) to Clk_HF3 and Bus Reset clock
+* (Clk_Peri assumed to be 50 MHz):
+*
+* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_ClockInit
+*
+* Refer to \ref group_sysclk driver API for more detail about clock
+* configuration.
+*
+* The FLL (Clock Path 0) with ECO also can be used as an alternative USB source
+* with the next configuration settings, for 48 MHz:
+* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_fllConfig48MHz
+* And for 96 MHz:
+* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_fllConfig96MHz
+* Use these structures with \ref Cy_SysClk_FllManualConfigure
+*
+********************************************************************************
+* \subsection group_usbfs_dev_drv_dma Assign and Route DMA Channels
+********************************************************************************
+*
+* The USBFS driver requires a DMA controller to operate in DMA Manual and Automatic modes.
+* The USB hardware block supports the DMA request and feedback lines for each
+* data endpoint. Therefore, up to eight DMA channels serve eight data endpoints.
+* The connection between the USB block and the DMA channels is set using the trigger
+* muxes infrastructure. The USB block output DMA request line is connected to
+* the DMA channel trigger input. This allows the USB block to request a DMA transfer.
+* The DMA completion output is connected to the USB block burst end input.
+* This allows the USB block to get notification that a DMA transfer has been completed
+* and a next DMA request can be sent. The USBFS driver DMA configuration
+* structure requires the <i>outTrigMux</i> field to provide the trigger mux that
+* performs DMA completion and USB block burst end connection.
+*
+* Refer to \ref group_trigmux for more detail on the routing capabilities.
+*
+* The code examples below shows a connection DMA channel and USB block and the define
+* for <i>outTrigMux</i> field initialization for the CY8C6xx6 or CY8C6xx7 devices.
+*
+* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_DmaConnect
+*
+********************************************************************************
+* \subsection group_usbfs_dev_drv_intr Configure Interrupts
+********************************************************************************
+*
+* <b>The interrupts are mandatory for the USBFS driver operation.</b>
+* The USBFS block provides multiple interrupt sources to be assigned to
+* trigger one of the three interrupts: Low, Medium, or High. This allows to
+* assign different priority to the interrupt sources handling.
+* The \ref cy_stc_usbfs_dev_drv_config_t structure provides the
+* <i>intrLevelSel</i> field which initializes the INTR_LVL_SEL
+* register. This register configures which interrupt the interrupt source will trigger.
+*
+* \note
+* The interrupt name (Low, Medium, or High) does not specify the interrupt
+* priority. The interrupt priority is configured in NVIC.
+*
+* The recommended/default configuration is:
+* * Interrupt Low: Bus Reset, Control Endpoint and SOF.
+* * Interrupt Medium: Endpoint 1-8 Completion.
+* * Interrupt High: Arbiter and LPM.
+*
+* However, the final configuration must be defined by the application.
+*
+* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_UserLvlSel
+*
+* The \ref Cy_USBFS_Dev_Drv_Interrupt function must be called in the interrupt
+* handler for the selected USB block instance. Note that
+* the \ref Cy_USBFS_Dev_Drv_Interrupt has the parameter <i>intrCause</i> that
+* must be assigned by calling the appropriate interrupt cause function:
+* * \ref Cy_USBFS_Dev_Drv_GetInterruptCauseHi
+* * \ref Cy_USBFS_Dev_Drv_GetInterruptCauseMed
+* * \ref Cy_USBFS_Dev_Drv_GetInterruptCauseLo
+*
+* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_IntrHandlers
+*
+* Finally, the interrupts must be configured and interrupt handler routines
+* hook up to NVIC. The code below assigns the interrupt priorities accordingly
+* to interrupt names. The priorities among the USBFS interrupts are as follows:
+* High - the greatest; Medium - the middle; Low - the lowest.
+*
+* \note
+* For proper operation in Manual DMA mode (Mode 2) the Arbiter interrupt source
+* must be assigned to interrupt which priority is greater than interrupt
+* triggered by Data Endpoint 1-8 Completion interrupt sources. \n
+* For Automatic DMA mode (Mode 3) the rule above is recommend to follow.
+*
+* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_IntrCfg
+* \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_IntrCfgHook
+*
+********************************************************************************
+* \section group_usbfs_dev_drv_ep_management Endpoint Buffer Management Modes
+********************************************************************************
+*
+* The USBFS hardware block supports three endpoint buffer management modes:
+* CPU (No DMA) mode (Mode 1), Manual DMA mode (Mode 2), and Automatic DMA mode (Mode 3).
+* These modes are listed using enum \ref cy_en_usbfs_dev_drv_ep_management_mode_t.
+* The following sub-sections provide more information about the endpoint buffer
+* management.
+*
+********************************************************************************
+* \subsection group_usbfs_dev_drv_ep_management_buff Hardware buffers
+********************************************************************************
+*
+* The USBFS block has a 512-byte hardware buffer that is divided between all
+* data endpoints used in the selected configuration. How the hardware buffer
+* is divided between endpoints depends on the selected endpoint buffer management
+* modes:
+*
+* * \ref group_usbfs_dev_drv_ep_management_mode1 and \ref group_usbfs_dev_drv_ep_management_mode2
+* Each data endpoint consumes space (number of bytes) in the hardware buffer
+* that is equal to the endpoint maximum packet size defined in the endpoint
+* descriptor. The total space consumed by all endpoints is restricted
+* by the size of hardware buffer (512 bytes). When an endpoint appears in the
+* different alternate settings and has a different maximum packet size, the greatest
+* value is selected to the allocate space of the endpoint in the
+* hardware buffer. This is to ensure correct USB Device operation when interface
+* alternate settings are changed. Note that endpoint can consume extra byte in
+* the hardware buffer when 16-bit access is used (See \ref
+* group_usbfs_dev_drv_ep_management_buf_access for more information).
+*
+* * \ref group_usbfs_dev_drv_ep_management_mode3
+* Each data endpoint consumes 32 bytes in the hardware buffer (if all eight
+* endpoints are used, the consumed buffer space is 32 * 8 = 256 byte).
+* This buffer is called "dedicated endpoint buffer". It acts as an endpoint
+* FIFO. The remaining space (256 bytes, if all eight endpoints are
+* used) in the hardware buffer is used by any endpoint that currently
+* communicates. This part of the buffer is called "common area". This hardware
+* buffer configuration gives a sufficient dedicated buffer size for each used
+* endpoint and common area for operation. The total space consumed by all
+* endpoints is not restricted by the size of the hardware buffer.
+*
+* To access the hardware buffer, the endpoint data register is read or written by
+* CPU or DMA. On each read or write, buffer pointers are updated to access
+* a next data element.
+*
+********************************************************************************
+* \subsection group_usbfs_dev_drv_ep_management_buf_access Hardware Buffer Access
+********************************************************************************
+*
+* The USBFS block provides two sets of data registers: 8-bit and 16-bit. Either
+* the 8-bit endpoint data register or the 16-bit endpoint data register can
+* be used to read/write to the endpoint buffer. The buffer access is controlled
+* by the <i>epAccess</i> field of the driver configuration structure
+* \ref cy_stc_usbfs_dev_drv_config_t.
+* The endpoint hardware buffer and SRAM buffer must be allocated using the
+* rules below when the 16-bit access is used:
+* * The buffer size must be even. If the endpoint maximum packet size is odd
+* the allocated buffer size must be equal to (maximum packet size + 1).
+* * The buffer must be aligned to the 2-byte boundary.
+*
+* The driver provides the \ref CY_USBFS_DEV_DRV_ALLOC_ENDPOINT_BUFFER macro that
+* applies the rules above to allocate the SRAM buffer for an endpoint. This macro
+* should be used by application to hide configuration differences.
+* <b>However, in this case the application must ignore extra bytes in the buffer.</b>
+* Alternately, apply the rules above only for the 16-bits access type configuration.
+*
+* The driver firmware allocates an endpoint hardware buffer (dividing hardware buffer
+* between utilized endpoints). Therefore, for \ref group_usbfs_dev_drv_ep_management_mode1
+* and \ref group_usbfs_dev_drv_ep_management_mode2, an endpoint whose
+* maximum packet size is odd, consumes an extra byte in the hardware buffer
+* when the 16-bit access is used. This is not applicable for \ref group_usbfs_dev_drv_ep_management_mode3
+* because endpoints dedicated buffer are even and aligned.
+*
+* In addition, to operate in \ref group_usbfs_dev_drv_ep_management_mode3,
+* the driver needs an internal SRAM buffer for endpoints. The buffer size is a
+* sum of all endpoint buffers. When the 16-bit access is used, each endpoint buffer
+* must be allocated using the rules above. The driver configuration structure
+* \ref cy_stc_usbfs_dev_drv_config_t has <i>epBuffer and epBufferSize</i> fields
+* to pass the allocated buffer to the driver. \n
+* For example: the USB Device uses three data endpoints whose max packets are
+* 63 bytes, 63 bytes, and 8 bytes. The endpoints buffer for the driver must be
+* allocated as follows:
+* * 8-bits: uint8_t endpointsBuffer[63 + 63 + 8];
+* * 16-bits: uint8_t endpointsBuffer[(63+1) + (63+1) + 8] CY_ALLIGN(2); or
+* CY_USBFS_DEV_DRV_ALLOC_ENDPOINT_BUFFER((63+1) + (63+1) + 8);
+*
+********************************************************************************
+* \subsection group_usbfs_dev_drv_ep_management_mode1 CPU mode (Mode 1)
+********************************************************************************
+*
+* CPU handles data transfers between the user-provided SRAM endpoint-buffer
+* and the USB block hardware-buffer when \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint
+* or \ref Cy_USBFS_Dev_Drv_LoadInEndpoint is called.
+*
+* \image html usbfs_ep_mngmnt_mode1.png
+*
+********************************************************************************
+* \subsection group_usbfs_dev_drv_ep_management_mode2 Manual DMA mode (Mode 2)
+********************************************************************************
+*
+* DMA handles data transfers between the user-provided SRAM endpoint
+* buffer and the USB block hardware buffer. The DMA request is issued by CPU
+* to execute a data transfer when \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint or
+* \ref Cy_USBFS_Dev_Drv_LoadInEndpoint.
+*
+* \image html usbfs_ep_mngmnt_mode2.png
+*
+********************************************************************************
+* \subsection group_usbfs_dev_drv_ep_management_mode3 Automatic DMA mode (Mode 3)
+********************************************************************************
+*
+* DMA handles data transfers between the driver SRAM endpoints buffer and
+* the USB block hardware buffer. The USB block generates DMA requests
+* automatically. When USB transfer starts, the USB block triggers DMA
+* requests to transfer data between the driver endpoint buffer and the hardware
+* buffer until transfer completion. The common area acts as a FIFO to (and keeps
+* data that does not fit into) the endpoint dedicated buffer. For IN endpoints,
+* the dedicated buffer is pre-loaded before enabling USB Host access to the endpoint.
+* This gives time for the DMA to provide remaining data before underflow
+* occurs. The USB block hardware has a feedback connection with the DMA
+* and does not issue new DMA request until it receives notification that the
+* previous DMA transfer completed.
+* When the \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint or \ref Cy_USBFS_Dev_Drv_LoadInEndpoint
+* function is called, the memcpy function is used to copy data from/into the
+* driver endpoints buffer to the user-provided endpoint buffer.
+* The driver provides the \ref Cy_USBFS_Dev_Drv_OverwriteMemcpy function to
+* replace memcpy function by one that has been custom implemented (the DMA can be used for data copy).
+*
+* \image html usbfs_ep_mngmnt_mode3.png
+*
+* \warning
+* When DMA data transfer is not fast enough, an overflow or underflow
+* interrupt triggers for the impacted endpoint. This must never happen
+* because this error condition indicates a system failure with no recovery.
+* To fix this, get the DMA channel assigned to this endpoint greater priority or
+* increase the clock the DMA operates at.
+*
+********************************************************************************
+* \section group_usbfs_dev_drv_callbacks Callbacks Usage
+********************************************************************************
+*
+* The driver provides the following callbacks that can be used by the application:
+* 1. Data endpoint 1-8 completion. This callback is invoked when the USB Host
+* completed communication with the endpoint. For IN endpoints, it means that data has
+* been read by the USB Host. For OUT endpoints, it means that data has been written
+* by the USB Host. Call \ref Cy_USBFS_Dev_Drv_RegisterEndpointCallback to
+* register callback function.
+*
+* 2. Start Of Frame packet received. This can be used in the application to
+* synchronize with SOF packets or for monitoring the bus activity.
+* Call \ref Cy_USBFS_Dev_Drv_RegisterSofCallback to register callback function.
+*
+* 3. LPM (Link Power Management) packet received. This must be used to implement
+* LPM power optimization. Call \ref Cy_USBFS_Dev_Drv_RegisterLpmCallback to
+* register callback function.
+*
+* Also, the driver provides callbacks for a Bus Reset event and Control Endpoint 0
+* communication events (setup packet, in packet, out packet). But these
+* callbacks are used by middleware and must not be used by the application directly.
+* The middleware provides appropriate hooks for these events.
+*
+********************************************************************************
+* \section group_usbfs_dev_drv_vbus VBUS Detection
+********************************************************************************
+*
+* The USB specification requires that no device supplies current on VBUS at its
+* upstream facing port at any time. To meet this requirement, the device must
+* monitors for the presence or absence of VBUS and removes power from the Dp/Dm
+* pull-up resistor if VBUS is absent. The USBFS driver does not provide any
+* support of VBUS monitoring or detection. The application firmware must implement
+* the required functionality using a VDDUSB power pad or GPIO. Refer to the
+* Universal Serial Bus (USB) Device Mode section, sub-section VBUS Detection
+* in the technical reference manual (TRM).
+*
+* Connect the VBUS through a resistive network when the
+* regular GPIO is used for VBUS detection to save the pin from voltage picks on VBUS,
+* or use GPIO tolerant over the voltage. An example schematic is shown below.
+*
+* \image html usbfs_vbus_connect_schem.png
+*
+* \note Power is removed when the USB cable is removed from the USB Host
+* for bus-powered USB Device. Therefore, such a USB Device complies with
+* specification requirement above.
+*
+********************************************************************************
+* \section group_usbfs_dev_drv_low_power Low Power Support
+********************************************************************************
+*
+* The USBFS driver supports the USB Suspend, Resume, and Remote Wakeup functionality.
+* This functionality is tightly related with the user application. The USBFS
+* driver provides only the API interface which helps the user achieve the desired
+* low-power behavior. The additional processing is required from the user application.
+* The description of application processing is provided below.
+*
+* Normally, the USB Host sends an SOF packet every 1 ms (at full speed), and this
+* keeps the USB Device awake. The USB Host suspends the USB Device by not
+* sending anything to the USB Device for 3 ms. To recognize this condition, the bus
+* activity must be checked. This can be done using the \ref Cy_USBFS_Dev_Drv_CheckActivity
+* function or by monitoring the SOF interrupt. A suspended device may draw no
+* more than 0.5 mA from VBUS. Therefore, put the device into low-power
+* mode to consume less current.
+* The \ref Cy_USBFS_Dev_Drv_Suspend function must be called before entering
+* low-power mode. When the USB Host wants to wake the device after a suspend,
+* it does so by reversing the polarity of the signal on the data lines for at
+* least 20 ms. The resume signaling is completed with a low-speed end-of-packet
+* signal. The USB block is disabled during Deep Sleep or Hibernate low-power modes.
+* To exit a low-power mode when USB Host drives resume, a falling edge interrupt
+* on Dp must be configured before entering these modes. The \ref Cy_USBFS_Dev_Drv_Resume
+* function must be called after exiting the low-power mode. To resume communication with
+* the USB Host, the data endpoints must be managed: the OUT endpoints must be
+* enabled and IN endpoints must be loaded with data.
+*
+* \note After entering low-power mode, the data which was left in the IN or OUT
+* endpoint buffers is not restored after the device's wake-up and is lost.
+* Therefore, it must be stored in the SRAM for OUT endpoint or read by the Host for
+* the IN endpoint before entering Low-power mode.
+*
+* If the USB Device supports remote wakeup functionality, the application has
+* to use middleware function Cy_USB_Dev_IsRemoteWakeupEnabled to determine whether
+* remote wakeup was enabled by the USB Host. When the device is suspended and
+* it determines the conditions to initiate a remote wakeup are met,
+* the application must call the \ref Cy_USBFS_Dev_Drv_Force
+* function to force the appropriate J and K states onto the USB bus, signaling a
+* remote wakeup condition. Note that \ref Cy_USBFS_Dev_Drv_Resume must be called
+* first to restore the condition.
+*
+********************************************************************************
+* \section group_usbfs_dev_drv_lpm Link Power Management (LPM)
+********************************************************************************
+*
+* Link Power Management is a USB low-power mode feature that provides more
+* flexibility in terms of features than the existing resume mode. This feature
+* is similar to the existing Suspend/Resume, but has transitional latencies of
+* tens of microseconds between power states (instead of 3 to greater than 20
+* millisecond latencies of the USB 2.0 Suspend/Resume).
+*
+* USB2.0 Power states are re-arranged as below with the introduction of LPM.
+* The existing power states are re-named with LPM:
+* * L0 (On)
+* * L1 (Sleep) -- Newly Introduced State in LPM
+* * L2 (Suspend)
+* * L3 (Powered-Off)
+*
+* LPM state transitions between is shown below:
+*
+* \image html usbfs_lpm_state_transition.png
+*
+* For example, a USB Host must transition a link from L1 (Sleep) to L0 before
+* transitioning it to L2 (Suspend), and similarly when transitioning from L2 to L1.
+*
+* When a USB Host is ready to transition a USB Device from L0 to a deeper power
+* savings state, it issues an LPM transaction to the USB Device. The USB Device
+* function responds with an ACK if it is ready to make the transition or a NYET
+* (Not Yet) if it is not ready (usually because it is has data pending for the
+* USB Host). A USB Device will transmit a STALL handshake if it does not support
+* the requested link state. If the USB Device detects errors in either of the
+* token packets or does not understand the protocol extension transaction,
+* no handshake is returned.
+*
+* \image html usbfs_lpm_responses.png
+*
+* After USB Device is initialized, the LPM transaction is to be acknowledged (ACKed)
+* meaning that the device is ready to enter the requested low-power mode. To override this
+* behavior, use \ref Cy_USBFS_Dev_Drv_Lpm_SetResponse. \n
+*
+* The USB block provides an interrupt source to define that an LPM transaction was
+* received and acknowledged (ACKed). Use the \ref Cy_USBFS_Dev_Drv_RegisterLpmCallback
+* function to register the application level callback function to serve the LPM
+* transaction. The callback function can notify the application about an LPM transaction
+* and can use \ref Cy_USBFS_Dev_Drv_Lpm_GetBeslValue read to read Best Effort Service
+* Latency (BESL) values provided as part of an LPM transaction. The BESL value
+* indicates the amount of time from the start of a resume to when the USB Host
+* attempts to begin issuing transactions to the USB Device. The
+* application must use the value BESL to decide which low-power mode is entered
+* to meet wakeup timing. The LPM transaction also contains the field that allows a
+* remote to wake up. Use \ref Cy_USBFS_Dev_Drv_Lpm_RemoteWakeUpAllowed to get its
+* value.
+*
+* LPM related USB 2.0 Extension Descriptor provides attributes fields named
+* baseline BESL and deep BESL to provide a range of values for different low-power
+* optimization. The recommended use of these fields is that the
+* baseline BESL field will have a value less than the deep BESL field. The
+* expected use is the baseline BESL value communicates a nominal power savings
+* design point and the deep BESL value communicates a significant power saving
+* design point.
+* For example, when the received BESL is less than baseline BESL, leave the device in
+* Active mode. When it is between baseline BESL and deep BESL, put the device into
+* Deep Sleep mode. When it is greater than deep BESL, put the device into
+* Hibernate mode.
+*
+* \note
+* The driver implements the USB Full-Speed device which does not support the LPM
+* NYET response.
+*
+* \note
+* The device will restart after Hibernate mode and the USB Device must
+* be initialized at the application level. Call the initialization functions
+* instead of \ref Cy_USBFS_Dev_Drv_Resume. The application must ensure that
+* the device will resume within the time defined in the BESL value of LPM request.
+*
+********************************************************************************
+* \section group_usbfs_drv_more_information More Information
+********************************************************************************
+*
+* For more detail on the USB Full-Speed Device peripheral, refer to the
+* section Universal Serial Bus (USB) Device Mode in the technical reference
+* manual (TRM).
+*
+********************************************************************************
+* \section group_usbfs_drv_MISRA MISRA-C Compliance
+********************************************************************************
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to object type and
+* a different pointer to object type.</td>
+* <td>The function \ref Cy_USBFS_Dev_Drv_LoadInEndpoint and
+* \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint cast buffer parameters from
+* (uint8_t *) to (uint16_t *) when 16-bit access is enabled.
+* To handle alignment issues the macro
+* \ref CY_USBFS_DEV_DRV_ALLOC_ENDPOINT_BUFFER must be used to
+* allocate the buffer for the endpoint.</td>
+* </tr>
+* <tr>
+* <td>11.5</td>
+* <td>R</td>
+* <td>A cast shall not be performed that removes any const or volatile
+* qualification from the type addressed by a pointer.</td>
+* <td>
+* 1. The register access-macros cast base-pointers to the USBFS peripheral
+* registers lose the const qualification. Despite the qualification being
+* lost, the driver ensures the proper registers access.
+* 2. The volatile qualification is lost when a register address is passed
+* as a source or destination to the DMA channel. This does not cause any
+* negative impact because the DMA does not optimize any memory access.
+* </td>
+* </tr>
+* <tr>
+* <td>14.7</td>
+* <td>R</td>
+* <td>A function shall have a single point of exit at the end of the
+* function.</td>
+* <td>The functions can return from several points. This is typically
+* done to improve code clarity when returning error status code if
+* input parameters validation fail.</td>
+* </tr>
+* <tr>
+* <td>16.7</td>
+* <td>A</td>
+* <td>A pointer parameter in a function prototype should be declared as
+* pointer to const if the pointer is not used to modify the addressed
+* object.</td>
+* <td>The middleware and USBFS driver define the general function
+* prototypes and pointers to the function types but the function's
+* implementation depends on the configuration. Therefore,
+* some functions' implementations require parameters to be a pointer to
+* const but this is not met because of the generalized implementation
+* approach.</td>
+* </tr>
+* </table>
+*
+********************************************************************************
+* \section group_usbfs_drv_changelog Changelog
+********************************************************************************
+*
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td rowspan="2">2.20</td>
+* <td>Fix configuration register value restoring in resume routine after
+* Deep Sleep.
+* </td>
+* <td>Fix issue that USB Device stops working in DMA modes after wake up
+* from Deep Sleep.
+* </td>
+* </tr>
+* <tr>
+* <td>The LPM requests are ignored after wake up from Deep Sleep and the
+* host starts sending SOFs.</td>
+* <td>Updated \ref Cy_USBFS_Dev_Drv_Resume function to restore LPM control
+* register after exit Deep Sleep.
+* </td>
+* </tr>
+* <tr>
+* <td>2.10</td>
+* <td>Returns the data toggle bit into the previous state after detecting
+* that the host is retrying an OUT transaction.</td>
+* <td>The device was not able to recover the data toggle bit and
+* continues communication through the endpoint after the host retried
+* the OUT transaction (the retried transaction has the same toggle bit
+* as the previous had).
+* </td>
+* </tr>
+* <tr>
+* <td>2.0</td>
+* <td>The list of changes to support the MBED-OS USB Device stack is provided below:
+* - Changed the processing of the control transfers.
+* - Updated the endpoint 0 service functions to update the endpoint 0 registers
+* before the function returns.
+* - Moved the set-device-address processing into the driver from the middleware.
+* - Changed the flow to configure endpoints after configuration change:
+* unconfigure the device or remove all endpoints, add endpoints, configure
+* the device. Updated the functions:
+* \ref Cy_USBFS_Dev_Drv_UnConfigureDevice, \ref Cy_USBFS_Dev_Drv_AddEndpoint
+* and \ref Cy_USBFS_Dev_Drv_ConfigDevice.
+* Removed the Cy_USBFS_Dev_Drv_ConfigDeviceComplete function because it is no needed anymore.
+* - Added the functions: \ref Cy_USBFS_Dev_Drv_Ep0ReadResult(), \ref Cy_USBFS_Dev_Drv_SetAddress()
+* and \ref Cy_USBFS_Dev_Drv_GetEp0MaxPacket().
+* - Changed the function signature \ref Cy_USBFS_Dev_Drv_Ep0Stall().
+* - Obsolete function Cy_USBFS_Dev_Drv_GetEndpointStallState; the \ref
+* Cy_USBFS_Dev_Drv_GetEndpointState() updated to be used instead of the obsolete function.
+* - Reduced the time required to complete abort operation in function \ref Cy_USBFS_Dev_Drv_Abort.
+* Obsolete function Cy_USBFS_Dev_Drv_AbortComplete because entire abort operation is handled by
+* \ref Cy_USBFS_Dev_Drv_Abort.
+* - Added the endpoint address argument to the \ref cy_cb_usbfs_dev_drv_ep_callback_t to simplify
+* endpoint transfer complete event processing for the MBED-OS USB Device stack.
+* </td>
+* <td>Updated the driver to support the MBED-OS USB Device stack and Cypress
+* USB Device middleware.</td>
+* </tr>
+* <tr>
+* <td rowspan="2">1.10</td>
+* <td>Fixed the \ref Cy_USBFS_Dev_Drv_Disable function to not disable DMA
+* in CPU mode.</td>
+* <td>Calling this function triggers assert because DMA for endpoints is not
+* initialized/used in the CPU mode.</td>
+* </tr>
+* <tr>
+* <td>Updated the condition statement in the \ref CY_USBFS_DEV_DRV_ALLOC_ENDPOINT_BUFFER
+* macro to explicitly check against non-zero.</td>
+* <td>Fixed MISRA 13.2 violation in the macro.</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>The initial version.</td>
+* <td></td>
+* </tr>
+* </table>
+*
+********************************************************************************
+*
+* \defgroup group_usbfs_dev_drv_macros Macros
+* \{
+ \defgroup group_usbfs_dev_drv_macros_intr_level Interrupt Level
+* \defgroup group_usbfs_dev_drv_macros_intr_cause Interrupt Cause
+* \defgroup group_usbfs_dev_drv_macros_ep_xfer_err Transfer Errors
+* \}
+* \defgroup group_usbfs_dev_drv_functions Functions
+* \{
+* \defgroup group_usbfs_dev_hal_functions_common Initialization Functions
+* \defgroup group_usbfs_dev_drv_functions_interrupts Interrupt Functions
+* \defgroup group_usbfs_dev_hal_functions_ep0_service Endpoint 0 Service Functions
+* \defgroup group_usbfs_dev_hal_functions_endpoint_config Data Endpoint Configuration Functions
+* \defgroup group_usbfs_dev_hal_functions_data_xfer Data Endpoint Transfer Functions
+* \defgroup group_usbfs_dev_drv_functions_low_power Low Power Functions
+* \defgroup group_usbfs_dev_drv_functions_lpm LPM (Link Power Management) Functions
+* \}
+* \defgroup group_usbfs_dev_drv_data_structures Data Structures
+* \defgroup group_usbfs_dev_drv_enums Enumerated Types
+* \}
+*/
+
+
+#if !defined(CY_USBFS_DEV_DRV_H)
+#define CY_USBFS_DEV_DRV_H
+
+#include "cy_dma.h"
+#include "cy_trigmux.h"
+#include "cy_usbfs_dev_drv_reg.h"
+
+#ifdef CY_IP_MXUSBFS
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Driver version and ID
+*******************************************************************************/
+
+/**
+* \addtogroup group_usbfs_dev_drv_macros
+* \{
+*/
+
+/** USBFS Driver major version */
+#define CY_USBFS_VERSION_MAJOR (2)
+
+/** USBFS Driver minor version */
+#define CY_USBFS_VERSION_MINOR (20)
+
+/** USBFS Driver identifier */
+#define CY_USBFS_ID CY_PDL_DRV_ID(0x3BU)
+
+/** USBFS Driver mode position in STATUS CODE: 0 - Device, 1 - Host */
+#define CY_USBFS_MODE_POS (15UL)
+
+/** USBFS Driver status code Device */
+#define CY_USBFS_DEV_DRV_STATUS_CODE (0U)
+/** \} group_usbfs_dev_drv_macros */
+
+
+/*******************************************************************************
+* Enumerated Types
+*******************************************************************************/
+
+/**
+* \addtogroup group_usbfs_dev_drv_enums
+* \{
+*/
+/** USBFS Device Driver return codes */
+typedef enum
+{
+ /** Operation completed successfully */
+ CY_USBFS_DEV_DRV_SUCCESS = 0U,
+
+ /** One or more input parameters are invalid */
+ CY_USBFS_DEV_DRV_BAD_PARAM = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 1U),
+
+ /** There is not enough space in the buffer to be allocated for the endpoint (hardware or RAM) */
+ CY_USBFS_DEV_DRV_BUF_ALLOC_FAILED = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 2U),
+
+ /** Failure during DMA configuration */
+ CY_USBFS_DEV_DRV_DMA_CFG_FAILED = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 3U),
+
+ /** Timeout during dynamic reconfiguration */
+ CY_USBFS_DEV_DRV_EP_DYN_RECONFIG_TIMEOUT = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 4U),
+
+ /** Timeout during execution of the DMA read request for the OUT endpoint
+ * (only applicable in \ref group_usbfs_dev_drv_ep_management_mode2)
+ */
+ CY_USBFS_DEV_DRV_EP_DMA_READ_TIMEOUT = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 5U),
+
+ /** Timeout during execution of the DMA read request for the OUT endpoint
+ * (only applicable in \ref group_usbfs_dev_drv_ep_management_mode2)
+ */
+ CY_USBFS_DEV_DRV_EP_DMA_WRITE_TIMEOUT = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 6U),
+
+} cy_en_usbfs_dev_drv_status_t;
+
+
+/** Data Endpoints Buffer Management Mode */
+typedef enum
+{
+ /** CPU manages a data transfer between the hardware endpoints buffer
+ * and the user SRAM
+ */
+ CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU = 0,
+
+ /** DMA manages data transfer between the hardware endpoints buffer and
+ * the user SRAM
+ */
+ CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA = 1,
+
+ /** The DMA automatically manages a data transfer between the hardware endpoints
+ * FIFO buffer and the user SRAM
+ */
+ CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO = 2,
+} cy_en_usbfs_dev_drv_ep_management_mode_t;
+
+/** Data Endpoint Register Access Type */
+typedef enum
+{
+ CY_USBFS_DEV_DRV_USE_8_BITS_DR, /**< Use 8-bits registers to access the data endpoints */
+ CY_USBFS_DEV_DRV_USE_16_BITS_DR, /**< Use 16-bits registers to access the data endpoints */
+} cy_en_usbfs_dev_ep_access_t;
+
+/** Service Callback Events (this enumerated type is used by middleware) */
+typedef enum
+{
+ CY_USB_DEV_BUS_RESET = 0U, /**< Callback hooked to the bus reset interrupt */
+ CY_USB_DEV_EP0_SETUP = 1U, /**< Callback hooked to the endpoint 0 SETUP packet interrupt */
+ CY_USB_DEV_EP0_IN = 2U, /**< Callback hooked to the endpoint 0 IN packet interrupt */
+ CY_USB_DEV_EP0_OUT = 3U, /**< Callback hooked to the endpoint 0 OUT packet interrupt */
+} cy_en_usb_dev_service_cb_t;
+
+/** Callback Sources */
+typedef enum
+{
+ CY_USBFS_DEV_DRV_EP1 = 0U, /**< Callback hooked to the Data Endpoint 1 completion interrupt */
+ CY_USBFS_DEV_DRV_EP2 = 1U, /**< Callback hooked to the Data Endpoint 2 completion interrupt */
+ CY_USBFS_DEV_DRV_EP3 = 2U, /**< Callback hooked to the Data Endpoint 3 completion interrupt */
+ CY_USBFS_DEV_DRV_EP4 = 3U, /**< Callback hooked to the Data Endpoint 4 completion interrupt */
+ CY_USBFS_DEV_DRV_EP5 = 4U, /**< Callback hooked to the Data Endpoint 5 completion interrupt */
+ CY_USBFS_DEV_DRV_EP6 = 5U, /**< Callback hooked to the Data Endpoint 6 completion interrupt */
+ CY_USBFS_DEV_DRV_EP7 = 6U, /**< Callback hooked to the Data Endpoint 7 completion interrupt */
+ CY_USBFS_DEV_DRV_EP8 = 7U, /**< Callback hooked to the Data Endpoint 8 completion interrupt */
+ CY_USBFS_DEV_DRV_SOF = 8U, /**< Callback hooked to the SOF packet received interrupt */
+ CY_USBFS_DEV_DRV_LPM = 9U, /**< Callback hooked to the LPM request received interrupt */
+} cy_en_usbfs_dev_drv_cb_source_t;
+
+/** Data Endpoint States (this enumerated type is used by middleware) */
+typedef enum
+{
+ CY_USB_DEV_EP_IDLE, /**< The endpoint is in an idle state after the configuration is set */
+ CY_USB_DEV_EP_PENDING, /**< The transfer targeted at an endpoint is in progress */
+ CY_USB_DEV_EP_COMPLETED, /**< The transfer targeted at an endpoint is completed */
+ CY_USB_DEV_EP_STALLED, /**< The endpoint is stalled */
+ CY_USB_DEV_EP_DISABLED, /**< The endpoint is disabled (not used in this configuration) */
+ CY_USB_DEV_EP_INVALID, /**< The endpoint is not supported by the hardware */
+} cy_en_usb_dev_ep_state_t;
+
+/** USB Lines Control */
+typedef enum
+{
+ CY_USBFS_DEV_DRV_FORCE_STATE_J = 0xA0U, /**< Force a J State onto the USB lines */
+ CY_USBFS_DEV_DRV_FORCE_STATE_K = 0x80U, /**< Force a K State onto the USB lines */
+ CY_USBFS_DEV_DRV_FORCE_STATE_SE0 = 0xC0U, /**< Force a Single Ended 0 onto the USB lines */
+ CY_USBFS_DEV_DRV_FORCE_STATE_NONE = 0x00U /**< Return the bus to the SIE control */
+} cy_en_usbfs_dev_drv_force_bus_state_t;
+
+/** LPM (Link Power Management) Responses */
+typedef enum
+{
+ /** The next LPM request will be responded with NACK */
+ CY_USBFS_DEV_DRV_LPM_REQ_NACK = 0x0U,
+
+ /** The next LPM request will be responded with ACK */
+ CY_USBFS_DEV_DRV_LPM_REQ_ACK = 0x1U,
+} cy_en_usbfs_dev_drv_lpm_req_t;
+
+/** USB Control EP0 transfer state */
+typedef enum
+{
+ CY_USBFS_DEV_DRV_EP0_CTRL_STATE_IDLE,
+ CY_USBFS_DEV_DRV_EP0_CTRL_STATE_SETUP,
+ CY_USBFS_DEV_DRV_EP0_CTRL_STATE_DATA,
+ CY_USBFS_DEV_DRV_EP0_CTRL_STATE_STATUS_IN,
+ CY_USBFS_DEV_DRV_EP0_CTRL_STATE_STATUS_OUT,
+} cy_en_usbfs_dev_drv_ep0_ctrl_state_t;
+
+/** \} group_usbfs_dev_drv_enums */
+
+
+/*******************************************************************************
+* Type Definitions
+*******************************************************************************/
+
+/**
+* \addtogroup group_usbfs_dev_drv_data_structures
+* \{
+*/
+
+/** Data Endpoint Configuration Structure */
+typedef struct
+{
+ bool enableEndpoint; /**< Defines if the endpoint becomes active after configuration */
+ bool allocBuffer; /**< Defines if the endpoint needs buffer allocation */
+ uint16_t maxPacketSize; /**< The endpoint max packet size */
+ uint16_t bufferSize; /**< The endpoint buffer size (the biggest max packet size
+ across all alternate for this endpoint) */
+ uint8_t endpointAddr; /**< The endpoint address (number plus direction bit) */
+ uint8_t attributes; /**< The endpoint attributes */
+} cy_stc_usb_dev_ep_config_t;
+
+/**
+* Driver context structure prototype.
+* The driver define this structure type \ref cy_stc_usbfs_dev_drv_context_t.
+*/
+struct cy_stc_usbfs_dev_drv_context;
+
+/**
+* Provides the typedef for the callback function called in the
+* \ref Cy_USBFS_Dev_Drv_Interrupt to notify the user interrupt events.
+*/
+typedef void (* cy_cb_usbfs_dev_drv_callback_t)(USBFS_Type *base,
+ struct cy_stc_usbfs_dev_drv_context *context);
+
+/**
+* Provides the typedef for the callback function called in the
+* \ref Cy_USBFS_Dev_Drv_Interrupt to notify the user about endpoint transfer
+* completion event.
+*/
+typedef void (* cy_cb_usbfs_dev_drv_ep_callback_t)(USBFS_Type *base,
+ uint32_t endpointAddr,
+ uint32_t errorType,
+ struct cy_stc_usbfs_dev_drv_context *context);
+
+/**
+* Provides the typedef for the user defined function to replace library provided
+* memcpy function to copy data from endpoint buffer to the user buffer.
+*/
+typedef uint8_t * (* cy_fn_usbfs_dev_drv_memcpy_ptr_t)(uint8_t *dest,
+ const uint8_t *src,
+ uint32_t size);
+
+/** \cond INTERNAL*/
+
+/**
+* Specifies the typedef for the pointer to the function that adds a data endpoint
+*/
+typedef cy_en_usbfs_dev_drv_status_t (* cy_fn_usbfs_dev_drv_add_ep_ptr_t)
+ (USBFS_Type *base,
+ cy_stc_usb_dev_ep_config_t const *config,
+ struct cy_stc_usbfs_dev_drv_context *context);
+
+/**
+* Specifies the typedef for the pointer to the function that loads data into
+* the data endpoint.
+*/
+typedef cy_en_usbfs_dev_drv_status_t (* cy_fn_usbfs_dev_drv_load_ep_ptr_t)
+ (USBFS_Type *base,
+ uint32_t endpoint,
+ const uint8_t *buffer,
+ uint32_t size,
+ struct cy_stc_usbfs_dev_drv_context *context);
+
+/**
+* Specifies the typedef for the pointer to the function that reads data from
+* the data endpoint.
+*/
+typedef cy_en_usbfs_dev_drv_status_t (* cy_fn_usbfs_dev_drv_read_ep_ptr_t)
+ (USBFS_Type *base,
+ uint32_t endpoint,
+ uint8_t *buffer,
+ uint32_t size,
+ uint32_t *actSize,
+ struct cy_stc_usbfs_dev_drv_context *context);
+/** \endcond */
+
+/** DMA Channel Configuration Structure */
+typedef struct
+{
+ DW_Type *base; /**< Pointer to the DMA base */
+ uint32_t chNum; /**< Channel number */
+ uint32_t priority; /**< Channel's priority */
+ bool preemptable; /**< Specifies whether the channel is preempt-able by another higher-priority channel */
+
+ /** DMA out trigger mux (applicable only when mode is
+ * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO)
+ */
+ uint32_t outTrigMux;
+
+ /** The pointer to the 1st allocated DMA descriptor (required for DMA operation) */
+ cy_stc_dma_descriptor_t *descr0;
+
+ /** The pointer to the 2nd allocated DMA descriptor (required when mode is
+ * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO)
+ */
+ cy_stc_dma_descriptor_t *descr1;
+
+} cy_stc_usbfs_dev_drv_dma_config_t;
+
+/** Driver Configuration Structure */
+typedef struct cy_stc_usbfs_dev_drv_config
+{
+ /** Endpoints management mode */
+ cy_en_usbfs_dev_drv_ep_management_mode_t mode;
+
+ /** DMA channels configuration for the endpoints.
+ * Only DMChannels for active endpoints must be configured. Provide NULL
+ * pointer if endpoint is not used. Applicable when \ref mode is
+ * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA or \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO.
+ */
+ const cy_stc_usbfs_dev_drv_dma_config_t *dmaConfig[CY_USBFS_DEV_DRV_NUM_EPS_MAX];
+
+ /**
+ * The pointer to the buffer allocated for the OUT endpoints (applicable only when \ref mode
+ * is \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO)
+ */
+ uint8_t *epBuffer;
+
+ /**
+ * The size of the buffer for the OUT endpoints (applicable only when \ref mode
+ * is \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO)
+ */
+ uint16_t epBufferSize;
+
+ /** The mask that assigns interrupt sources to trigger: Low, Medium, or High interrupt.
+ * Use the macros provided in group_usbfs_dev_drv_macros_intr_level to initialize the
+ * intrLevelSel mask.
+ */
+ uint32_t intrLevelSel;
+
+ /** Enables LPM (Link Power Management) response */
+ bool enableLpm;
+
+ /** Data endpoints access type */
+ cy_en_usbfs_dev_ep_access_t epAccess;
+
+} cy_stc_usbfs_dev_drv_config_t;
+
+/** \cond INTERNAL: Endpoint Structure */
+typedef struct
+{
+ volatile uint8_t address; /**< Endpoint address (include direction bit) */
+ volatile uint8_t toggle; /**< Toggle bit in SIE_EP_CNT1 register */
+ volatile uint8_t sieMode; /**< SIE mode to arm endpoint on the bus */
+
+ uint8_t *buffer; /**< The pointer to the buffer */
+ volatile uint16_t bufferSize; /**< Endpoint buffer size */
+ volatile uint16_t startBuf; /**< Start of the buffer */
+
+ volatile bool isPending; /**< Save the pending state before stall endpoint */
+ volatile cy_en_usb_dev_ep_state_t state; /**< Endpoint state */
+
+ /** Completes an event notification callback */
+ cy_cb_usbfs_dev_drv_ep_callback_t epComplete;
+
+ DW_Type *base; /**< The pointer to the DMA base */
+ uint32_t chNum; /**< DMA Channel number */
+ uint32_t outTrigMux; /**< Out trigger mux for DMA channel number */
+
+ cy_stc_dma_descriptor_t* descr0; /**< The pointer to the descriptor 0 */
+ cy_stc_dma_descriptor_t* descr1; /**< The pointer to the descriptor 1 */
+
+ cy_fn_usbfs_dev_drv_memcpy_ptr_t copyData; /**< The pointer to the user memcpy function */
+
+} cy_stc_usbfs_dev_drv_endpoint_data_t;
+/** \endcond */
+
+/** USBFS Device context structure.
+* All fields for the context structure are internal. The firmware never reads or
+* writes these values. The firmware allocates a structure and provides the
+* address of the structure to the middleware in HID function calls. The firmware
+* must ensure that the defined instance of this structure remains in scope while
+* the middleware is in use.
+*/
+typedef struct cy_stc_usbfs_dev_drv_context
+{
+ /** \cond INTERNAL */
+ /** Stores the Endpoint 0 buffer to put the read operation results */
+ uint8_t *ep0Buffer;
+
+ /** Stores the Endpoint 0 buffer size */
+ uint8_t ep0BufferSize;
+
+ /** Endpoint 0 data toggle bit: 0 or USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk */
+ uint8_t ep0DataToggle;
+
+ /** Active endpoint mask */
+ uint8_t activeEpMask;
+
+ /** The device address to set */
+ uint8_t address;
+
+ /** Defines the list of endpoints that waits for abort completion */
+ volatile uint8_t epAbortMask;
+
+ /** Endpoints management mode */
+ cy_en_usbfs_dev_drv_ep_management_mode_t mode;
+
+ /** Stores the control transfer state */
+ cy_en_usbfs_dev_drv_ep0_ctrl_state_t ep0CtrlState;
+
+ /* Status to set or not the device address after the status state of the control transfer */
+ bool setAddress;
+
+ /** Defines which endpoint registers to use: 8-bits or 16-bits */
+ bool useReg16;
+
+ /** Bus reset callback notification */
+ cy_cb_usbfs_dev_drv_callback_t busReset;
+
+ /** Endpoint 0: Setup packet has received callback notification */
+ cy_cb_usbfs_dev_drv_callback_t ep0Setup;
+
+ /** Endpoint 0: IN data packet has received callback notification */
+ cy_cb_usbfs_dev_drv_callback_t ep0In;
+
+ /** Endpoint 0: OUT data packet has received callback notification */
+ cy_cb_usbfs_dev_drv_callback_t ep0Out;
+
+ /** SOF frame has received callback notification */
+ cy_cb_usbfs_dev_drv_callback_t cbSof;
+
+ /** LPM request has received callback notification */
+ cy_cb_usbfs_dev_drv_callback_t cbLpm;
+
+ /** Pointer to addEndpoint function: depends on operation mode */
+ cy_fn_usbfs_dev_drv_add_ep_ptr_t addEndpoint;
+
+ /** Pointer to loadInEndpoint function: depends on operation mode */
+ cy_fn_usbfs_dev_drv_load_ep_ptr_t loadInEndpoint;
+
+ /** Pointer to readOutEndpoint function: depends on operation mode */
+ cy_fn_usbfs_dev_drv_read_ep_ptr_t readOutEndpoint;
+
+ uint8_t *epSharedBuf; /**< Buffer for OUT endpoints */
+ uint16_t epSharedBufSize; /**< Buffer size */
+
+ uint16_t curBufAddr; /** Current position in endpoint buffer (HW or SRAM) */
+
+ /** Stores endpoints information */
+ cy_stc_usbfs_dev_drv_endpoint_data_t epPool[CY_USBFS_DEV_DRV_NUM_EPS_MAX];
+
+ /** The pointer to the device context structure */
+ void *devConext;
+ /** \endcond */
+} cy_stc_usbfs_dev_drv_context_t;
+/** \} group_usbfs_dev_drv_data_structures */
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_usbfs_dev_hal_functions_common
+* \{
+* The Initialization functions provide an API to begin the USBFS driver operation
+* (configure and enable) and to stop operation (disable and de-initialize).
+*/
+cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Init(USBFS_Type *base,
+ cy_stc_usbfs_dev_drv_config_t const *config,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+void Cy_USBFS_Dev_Drv_DeInit(USBFS_Type *base,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+void Cy_USBFS_Dev_Drv_Enable(USBFS_Type *base,
+ cy_stc_usbfs_dev_drv_context_t const *context);
+
+void Cy_USBFS_Dev_Drv_Disable(USBFS_Type *base,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetAddress(USBFS_Type *base, uint8_t address,
+ cy_stc_usbfs_dev_drv_context_t *context);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDeviceAddress(USBFS_Type *base, uint8_t address);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetDeviceAddress(USBFS_Type const *base);
+
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDevContext(USBFS_Type const *base,
+ void *devContext,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+__STATIC_INLINE void* Cy_USBFS_Dev_Drv_GetDevContext(USBFS_Type const *base,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+void Cy_USBFS_Dev_Drv_ConfigDevice(USBFS_Type *base,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+void Cy_USBFS_Dev_Drv_UnConfigureDevice(USBFS_Type *base,
+ cy_stc_usbfs_dev_drv_context_t *context);
+/** \} group_usbfs_dev_hal_functions_common */
+
+/**
+* \addtogroup group_usbfs_dev_hal_functions_ep0_service
+* \{
+* The Endpoint 0 Service functions provide an API to establish communication with
+* the USB Host using control endpoint 0.
+*/
+void Cy_USBFS_Dev_Drv_Ep0GetSetup(USBFS_Type const *base,
+ uint8_t *buffer,
+ cy_stc_usbfs_dev_drv_context_t const *context);
+
+uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base,
+ uint8_t const *buffer,
+ uint32_t size,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+void Cy_USBFS_Dev_Drv_Ep0Read(USBFS_Type *base,
+ uint8_t *buffer,
+ uint32_t size,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+uint32_t Cy_USBFS_Dev_Drv_Ep0ReadResult(USBFS_Type const *base,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_Ep0Stall(USBFS_Type *base);
+
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEp0MaxPacket(USBFS_Type const *base);
+/** \} group_usbfs_dev_hal_functions_ep0_service */
+
+
+/**
+* \addtogroup group_usbfs_dev_hal_functions_endpoint_config
+* \{
+* The Data Endpoint Configuration Functions provide an API to allocate and release
+* hardware resources and override the memcpy function for the data endpoints.
+*/
+__STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_AddEndpoint(USBFS_Type *base,
+ cy_stc_usb_dev_ep_config_t const *config,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_RemoveEndpoint(USBFS_Type *base,
+ uint32_t endpointAddr,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_OverwriteMemcpy(USBFS_Type const *base,
+ uint32_t endpoint,
+ cy_fn_usbfs_dev_drv_memcpy_ptr_t memcpyFunc,
+ cy_stc_usbfs_dev_drv_context_t *context);
+/** \} group_usbfs_dev_hal_functions_endpoint_config */
+
+/**
+* \addtogroup group_usbfs_dev_hal_functions_data_xfer
+* The Data Endpoint Transfer functions provide an API to establish
+* communication with the USB Host using data endpoint.
+* \{
+*/
+__STATIC_INLINE cy_en_usb_dev_ep_state_t Cy_USBFS_Dev_Drv_GetEndpointState(USBFS_Type const *base,
+ uint32_t endpoint,
+ cy_stc_usbfs_dev_drv_context_t const *context);
+
+__STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_LoadInEndpoint(USBFS_Type *base,
+ uint32_t endpoint,
+ uint8_t const *buffer,
+ uint32_t size,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+void Cy_USBFS_Dev_Drv_EnableOutEndpoint(USBFS_Type *base,
+ uint32_t endpoint,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+__STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_ReadOutEndpoint(USBFS_Type *base,
+ uint32_t endpoint,
+ uint8_t *buffer,
+ uint32_t size,
+ uint32_t *actSize,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Abort(USBFS_Type *base,
+ uint32_t endpoint,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+__STATIC_INLINE bool Cy_USBFS_Dev_Drv_GetEndpointAckState(USBFS_Type const *base, uint32_t endpoint);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEndpointCount (USBFS_Type const *base, uint32_t endpoint);
+
+cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_StallEndpoint(USBFS_Type *base,
+ uint32_t endpoint,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_UnStallEndpoint(USBFS_Type *base,
+ uint32_t endpoint,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+/** \} group_usbfs_dev_hal_functions_data_xfer */
+
+/**
+* \addtogroup group_usbfs_dev_drv_functions_interrupts
+* The Functions Interrupt functions provide an API to register callbacks
+* for interrupt events provided by the USB block, interrupt handler, and configuration functions.
+* \{
+*/
+void Cy_USBFS_Dev_Drv_Interrupt(USBFS_Type *base, uint32_t intrCause, cy_stc_usbfs_dev_drv_context_t *context);
+
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetInterruptCauseHi (USBFS_Type const *base);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetInterruptCauseMed(USBFS_Type const *base);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetInterruptCauseLo (USBFS_Type const *base);
+
+void Cy_USBFS_Dev_Drv_RegisterServiceCallback(USBFS_Type const *base,
+ cy_en_usb_dev_service_cb_t source,
+ cy_cb_usbfs_dev_drv_callback_t callback,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterSofCallback(USBFS_Type *base,
+ cy_cb_usbfs_dev_drv_callback_t callback,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterLpmCallback(USBFS_Type *base,
+ cy_cb_usbfs_dev_drv_callback_t callback,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterEndpointCallback(USBFS_Type const *base,
+ uint32_t endpoint,
+ cy_cb_usbfs_dev_drv_ep_callback_t callback,
+ cy_stc_usbfs_dev_drv_context_t *context);
+
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetInterruptsLevel(USBFS_Type *base, uint32_t intrLevel);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetInterruptsLevel(USBFS_Type const *base);
+
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_DisableEp0Interrupt(USBFS_Type *base);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_EnableEp0Interrupt(USBFS_Type *base);
+/** \} group_usbfs_dev_drv_functions_interrupts */
+
+/**
+* \addtogroup group_usbfs_dev_drv_functions_low_power
+* The Low-power functions provide an API to implement Low-power callback at the application level.
+* \{
+*/
+__STATIC_INLINE bool Cy_USBFS_Dev_Drv_CheckActivity(USBFS_Type *base);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_Force (USBFS_Type *base, cy_en_usbfs_dev_drv_force_bus_state_t state);
+ void Cy_USBFS_Dev_Drv_Suspend(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context);
+ void Cy_USBFS_Dev_Drv_Resume (USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context);
+/** \} group_usbfs_dev_drv_functions_low_power */
+
+/**
+* \addtogroup group_usbfs_dev_drv_functions_lpm
+* The LPM functions provide an API to use the LPM feature available in the USB block.
+* \{
+*/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_Lpm_GetBeslValue (USBFS_Type const *base);
+__STATIC_INLINE bool Cy_USBFS_Dev_Drv_Lpm_RemoteWakeUpAllowed(USBFS_Type const *base);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_Lpm_SetResponse (USBFS_Type *base, cy_en_usbfs_dev_drv_lpm_req_t response);
+__STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(USBFS_Type const *base);
+/** \} group_usbfs_dev_drv_functions_lpm */
+
+
+/*******************************************************************************
+* Driver Constants
+*******************************************************************************/
+
+/**
+* \addtogroup group_usbfs_dev_drv_macros
+* \{
+*/
+/** Allocates a static buffer for the data endpoint. The size parameter must be a constant.
+* The allocated buffer is aligned to a 2-byte boundary. <b>An odd buffer size is
+* converted to even, consuming 1 extra byte. The application must discard this
+* extra byte</b> to support different 8-bit and 16-bit hardware buffer access types
+* in the driver. For more detail, refer to \ref group_usbfs_dev_drv_ep_management_buf_access.
+*/
+#define CY_USBFS_DEV_DRV_ALLOC_ENDPOINT_BUFFER(buf, size) uint8_t buf[(0U != ((size) & 0x1U)) ? ((size) + 1U) : (size)] CY_ALIGN(2)
+/** \} group_usbfs_dev_drv_macros */
+
+/**
+* \addtogroup group_usbfs_dev_drv_macros_intr_level
+* \{
+*/
+/** The interrupt source is assigned to a trigger High interrupt */
+#define CY_USBFS_DEV_DRV_LVL_HIGH (0U)
+/** The interrupt source is assigned to a trigger Medium interrupt */
+#define CY_USBFS_DEV_DRV_LVL_MEDIUM (1U)
+/** The interrupt source is assigned to a trigger Low interrupt */
+#define CY_USBFS_DEV_DRV_LVL_LOW (2U)
+
+/** Assigns the SOF interrupt source to a trigger interrupt: Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_SOF_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_SOF_LVL_SEL, level)
+/** Assigns the Bus Reset interrupt source to a trigger interrupt: Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_BUS_RESET_LVL_SEL, level)
+/** Assigns the Endpoint 0 interrupt source to a trigger interrupt Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_EP0_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP0_LVL_SEL, level)
+/** Assigns the LPM interrupt source to a trigger interrupt: Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_LPM_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_LPM_LVL_SEL, level)
+/** Assigns the Resume interrupt source to a trigger interrupt: Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_RESUME_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_RESUME_LVL_SEL, level)
+/** Assigns the Arbiter interrupt source to a trigger interrupt: Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_ARB_EP_LVL_SEL, level)
+/** Assigns the Endpoint 1 interrupt source to a trigger interrupt: Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_EP1_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP1_LVL_SEL, level)
+/** Assigns the Endpoint 2 interrupt source to a trigger interrupt: Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_EP2_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP2_LVL_SEL, level)
+/** Assigns the Endpoint 3 interrupt source to a trigger interrupt: Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_EP3_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP3_LVL_SEL, level)
+/** Assigns the Endpoint 4 interrupt source to a trigger interrupt: Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_EP4_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP4_LVL_SEL, level)
+/** Assigns the Endpoint 5 interrupt source to a trigger interrupt: Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_EP5_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP5_LVL_SEL, level)
+/** Assigns the Endpoint 6 interrupt source to a trigger interrupt: Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_EP6_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP6_LVL_SEL, level)
+/** Assigns the Endpoint 7 interrupt source to a trigger interrupt: Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_EP7_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP7_LVL_SEL, level)
+/** Assigns the Endpoint 8 interrupt source to a trigger interrupt: Low, Medium, or High */
+#define CY_USBFS_DEV_DRV_SET_EP8_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP8_LVL_SEL, level)
+/** \} group_usbfs_dev_drv_macros_intr_level */
+
+/**
+* \addtogroup group_usbfs_dev_drv_macros_intr_cause
+* \{
+*/
+#define CY_USBFS_DEV_DRV_LPM_INTR USBFS_USBLPM_INTR_CAUSE_HI_LPM_INTR_Msk /**< Link Power Management request interrupt */
+#define CY_USBFS_DEV_DRV_ARBITER_INTR USBFS_USBLPM_INTR_CAUSE_HI_ARB_EP_INTR_Msk /**< Arbiter interrupt */
+#define CY_USBFS_DEV_DRV_EP0_INTR USBFS_USBLPM_INTR_CAUSE_HI_EP0_INTR_Msk /**< Endpoint 0 interrupt */
+#define CY_USBFS_DEV_DRV_SOF_INTR USBFS_USBLPM_INTR_CAUSE_HI_SOF_INTR_Msk /**< SOF interrupt */
+#define CY_USBFS_DEV_DRV_BUS_RESET_INTR USBFS_USBLPM_INTR_CAUSE_HI_BUS_RESET_INTR_Msk /**< Bus Reset interrupt */
+#define CY_USBFS_DEV_DRV_EP1_INTR USBFS_USBLPM_INTR_CAUSE_HI_EP1_INTR_Msk /**< Data endpoint 1 interrupt */
+#define CY_USBFS_DEV_DRV_EP2_INTR USBFS_USBLPM_INTR_CAUSE_HI_EP2_INTR_Msk /**< Data endpoint 2 interrupt */
+#define CY_USBFS_DEV_DRV_EP3_INTR USBFS_USBLPM_INTR_CAUSE_HI_EP3_INTR_Msk /**< Data endpoint 3 interrupt */
+#define CY_USBFS_DEV_DRV_EP4_INTR USBFS_USBLPM_INTR_CAUSE_HI_EP4_INTR_Msk /**< Data endpoint 4 interrupt */
+#define CY_USBFS_DEV_DRV_EP5_INTR USBFS_USBLPM_INTR_CAUSE_HI_EP5_INTR_Msk /**< Data endpoint 5 interrupt */
+#define CY_USBFS_DEV_DRV_EP6_INTR USBFS_USBLPM_INTR_CAUSE_HI_EP6_INTR_Msk /**< Data endpoint 6 interrupt */
+#define CY_USBFS_DEV_DRV_EP7_INTR USBFS_USBLPM_INTR_CAUSE_HI_EP7_INTR_Msk /**< Data endpoint 7 interrupt */
+#define CY_USBFS_DEV_DRV_EP8_INTR USBFS_USBLPM_INTR_CAUSE_HI_EP8_INTR_Msk /**< Data endpoint 8 interrupt */
+/** \} group_usbfs_dev_drv_macros_intr_cause */
+
+/**
+* \addtogroup group_usbfs_dev_drv_macros_ep_xfer_err
+* \{
+*/
+/**
+* An error occurred during a USB transfer.
+* For an IN transaction, this indicates a "no response" from the HOST scenario.
+* For an OUT transaction, this represents a "PID or CRC error" or the bit-stuff
+* error scenario.
+*/
+#define CY_USBFS_DEV_ENDPOINT_TRANSFER_ERROR (0x1U)
+
+/**
+* The data toggle bit remains the same.
+* The received OUT packet has the same data toggle bit that the previous
+* packet had. This indicates that the Host retransmitted the packet.
+*/
+#define CY_USBFS_DEV_ENDPOINT_SAME_DATA_TOGGLE (0x2U)
+/** \} group_usbfs_dev_drv_macros_ep_xfer_err */
+
+
+/*******************************************************************************
+* Internal Constants
+*******************************************************************************/
+
+/** \cond INTERNAL */
+/* The start position of the data endpoints SIE interrupt sources */
+#define USBFS_USBLPM_INTR_CAUSE_LPM_INTR_Msk USBFS_USBLPM_INTR_CAUSE_HI_LPM_INTR_Msk
+#define USBFS_USBLPM_INTR_CAUSE_ARB_EP_INTR_Msk USBFS_USBLPM_INTR_CAUSE_HI_ARB_EP_INTR_Msk
+#define USBFS_USBLPM_INTR_CAUSE_EP0_INTR_Msk USBFS_USBLPM_INTR_CAUSE_HI_EP0_INTR_Msk
+#define USBFS_USBLPM_INTR_CAUSE_SOF_INTR_Msk USBFS_USBLPM_INTR_CAUSE_HI_SOF_INTR_Msk
+#define USBFS_USBLPM_INTR_CAUSE_BUS_RESET_INTR_Msk USBFS_USBLPM_INTR_CAUSE_HI_BUS_RESET_INTR_Msk
+#define USBFS_USBLPM_INTR_CAUSE_EP1_INTR_Pos USBFS_USBLPM_INTR_CAUSE_HI_EP1_INTR_Pos
+
+/* Validation macros */
+#define CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint) (((endpoint) > 0U) && ((endpoint) <= CY_USBFS_DEV_DRV_NUM_EPS_MAX))
+#define CY_USBFS_DEV_DRV_EP2PHY(endpoint) ((uint32_t) (endpoint) - 1U)
+#define CY_USBFS_DEV_DRV_EP2MASK(endpont) ((uint32_t) (0x1UL << endpoint))
+
+#define CY_USBFS_DEV_DRV_EPADDR2EP(endpointAddr) ((uint32_t) (endpointAddr) & 0x0FU)
+#define CY_USBFS_DEV_DRV_IS_EP_DIR_IN(endpointAddr) (0U != ((endpointAddr) & 0x80U))
+#define CY_USBFS_DEV_DRV_IS_EP_DIR_OUT(endpointAddr) (0U == ((endpointAddr) & 0x80U))
+#define CY_USBFS_DEV_DRV_EPADDR2PHY(endpointAddr) CY_USBFS_DEV_DRV_EP2PHY(CY_USBFS_DEV_DRV_EPADDR2EP(endpointAddr))
+
+#define CY_USBFS_DEV_DRV_IS_MODE_VALID(mode) (((mode) == CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU) || \
+ ((mode) == CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA) || \
+ ((mode) == CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO))
+
+/* Obsolete function */
+#define Cy_USBFS_Dev_Drv_GetEndpointStallState Cy_USBFS_Dev_Drv_GetEndpointState
+/** \endcond */
+/** \} group_usbfs_drv_macros */
+
+
+/*******************************************************************************
+* In-line Function Implementation
+*******************************************************************************/
+
+/**
+* \addtogroup group_usbfs_dev_hal_functions_common
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetAddress
+****************************************************************************//**
+*
+* Posts a request to set the device address after the completion status stage of
+* the control transfer. This function must be used if a higher level requests
+* to set an address before the status stage of the control transfer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param address
+* The device address.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t
+* allocated by the user. The structure is used during the USBFS Device
+* operation for internal configuration and data retention. The user must not
+* modify anything in this structure.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetAddress(USBFS_Type *base, uint8_t address,
+ cy_stc_usbfs_dev_drv_context_t *context)
+{
+ (void)base; /* Suppress warning */
+ /* Stores the address to set later after the status stage of setup request completed */
+ context->address = address;
+ context->setAddress = true;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetDeviceAddress
+****************************************************************************//**
+*
+* Sets the device address (writes the address directly into the register).
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param address
+* Device address.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDeviceAddress(USBFS_Type *base, uint8_t address)
+{
+ base->USBDEV.CR0 = _CLR_SET_FLD32U(base->USBDEV.CR0, USBFS_USBDEV_CR0_DEVICE_ADDRESS, address);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetDeviceAddress
+****************************************************************************//**
+*
+* Returns the device address (reads the address directly from the register).
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* The device address.
+* The device address is assigned by the Host during device enumeration.
+* Zero means that the device address is not assigned.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetDeviceAddress(USBFS_Type const *base)
+{
+ return _FLD2VAL(USBFS_USBDEV_CR0_DEVICE_ADDRESS, base->USBDEV.CR0);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetDevContext
+****************************************************************************//**
+*
+* Stores a pointer to the USB Device context in the driver context.
+*
+* \param base
+* The pointer to the USBFS instance
+*
+* \param devContext
+* The pointer to the USB Device context structure.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t
+* allocated by the user. The structure is used during the USBFS Device
+* operation for internal configuration and data retention. The user must not
+* modify anything in this structure.
+*
+* \note
+* This function is intended for the USB Device middleware operation.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDevContext(USBFS_Type const *base,
+ void *devContext,
+ cy_stc_usbfs_dev_drv_context_t *context)
+{
+ /* Suppresses a compiler warning about unused variables. */
+ (void) base;
+
+ context->devConext = devContext;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetDevContext
+****************************************************************************//**
+*
+* Returns a pointer to the USB Device context.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t
+* allocated by the user. The structure is used during USBFS Device
+* operation for internal configuration and data retention. The user must not
+* modify anything in this structure.
+*
+* \return
+* The pointer to the USB Device context.
+*
+* \note
+* This function is intended for the USB Device middleware operation.
+*
+*******************************************************************************/
+__STATIC_INLINE void* Cy_USBFS_Dev_Drv_GetDevContext(USBFS_Type const *base,
+ cy_stc_usbfs_dev_drv_context_t *context)
+{
+ /* Suppresses a compiler warning about unused variables */
+ (void) base;
+
+ return (context->devConext);
+}
+/** \} group_usbfs_dev_hal_functions_common */
+
+
+/**
+* \addtogroup group_usbfs_dev_drv_functions_interrupts
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_RegisterSofCallback
+****************************************************************************//**
+*
+* Registers a callback function to notify about an SOF event in
+* \ref Cy_USBFS_Dev_Drv_Interrupt. The SOF interrupt source is enabled after
+* registration. To remove callback function, pass NULL as the function pointer.
+* When the callback is removed, the interrupt source is disabled.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param callback
+* The pointer to a callback function.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t
+* allocated by the user. The structure is used during the USBFS Device
+* operation for internal configuration and data retention. The user must not
+* modify anything in this structure.
+*
+* \note
+* To remove the callback, pass NULL as the pointer to a callback function.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterSofCallback(USBFS_Type *base,
+ cy_cb_usbfs_dev_drv_callback_t callback,
+ cy_stc_usbfs_dev_drv_context_t *context)
+{
+ uint32_t mask;
+
+ context->cbSof = callback;
+
+ /* Enables/Disables SOF interrupt */
+ mask = Cy_USBFS_Dev_Drv_GetSieInterruptMask(base);
+
+ if (NULL != callback)
+ {
+ mask |= CY_USBFS_DEV_DRV_INTR_SIE_SOF;
+ }
+ else
+ {
+ mask &= ~CY_USBFS_DEV_DRV_INTR_SIE_SOF;
+ }
+
+ Cy_USBFS_Dev_Drv_ClearSieInterrupt(base, CY_USBFS_DEV_DRV_INTR_SIE_SOF);
+ Cy_USBFS_Dev_Drv_SetSieInterruptMask(base, mask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_RegisterLpmCallback
+****************************************************************************//**
+*
+* Registers a callback function to notify about an LPM event in
+* \ref Cy_USBFS_Dev_Drv_Interrupt. The LPM interrupt source is enabled after
+* registration. To remove the callback function, pass NULL as the function pointer.
+* When the callback is removed, the interrupt source is disabled.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param callback
+* The pointer to a callback function.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t
+* allocated by the user. The structure is used during the USBFS Device
+* operation for internal configuration and data retention. The user must not
+* modify anything in this structure.
+*
+* \note
+* To remove the callback, pass NULL as the pointer to the callback function.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterLpmCallback(USBFS_Type *base,
+ cy_cb_usbfs_dev_drv_callback_t callback,
+ cy_stc_usbfs_dev_drv_context_t *context)
+
+{
+ uint32_t mask;
+
+ context->cbLpm = callback;
+
+ /* Enables/Disables the LPM interrupt source */
+ mask = Cy_USBFS_Dev_Drv_GetSieInterruptMask(base);
+
+ if (NULL != callback)
+ {
+ mask |= CY_USBFS_DEV_DRV_INTR_SIE_LPM;
+ }
+ else
+ {
+ mask &= ~CY_USBFS_DEV_DRV_INTR_SIE_LPM;
+ }
+
+ Cy_USBFS_Dev_Drv_ClearSieInterrupt(base, CY_USBFS_DEV_DRV_INTR_SIE_LPM);
+ Cy_USBFS_Dev_Drv_SetSieInterruptMask(base, mask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_RegisterEndpointCallback
+****************************************************************************//**
+*
+* Registers a callback function to notify of an endpoint transfer completion
+* event in \ref Cy_USBFS_Dev_Drv_Interrupt.
+* * IN endpoint - The Host read data from the endpoint and new data can be
+* loaded.
+* * OUT endpoint - The Host has written data into the endpoint and the data is
+* ready to be read.
+* To remove the callback function, pass NULL as function pointer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* The data endpoint number.
+*
+* \param callback
+* The pointer to a callback function.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t
+* allocated by the user. The structure is used during the USBFS Device
+* operation for internal configuration and data retention. The user must not
+* modify anything in this structure.
+*
+* \note
+* To remove the callback, pass NULL as the pointer to the callback function.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterEndpointCallback(USBFS_Type const *base,
+ uint32_t endpoint,
+ cy_cb_usbfs_dev_drv_ep_callback_t callback,
+ cy_stc_usbfs_dev_drv_context_t *context)
+
+{
+ /* Suppresses a compiler warning about unused variables */
+ (void) base;
+
+ CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint));
+
+ endpoint = CY_USBFS_DEV_DRV_EP2PHY(endpoint);
+ context->epPool[endpoint].epComplete = callback;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetInterruptCauseHi
+****************************************************************************//**
+*
+* Returns the mask of bits showing the source of the current triggered
+* interrupt. This is useful for modes of operation where an interrupt can
+* be generated by conditions in multiple interrupt source registers.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* The mask with the OR of the following conditions that have been triggered.
+* See \ref group_usbfs_dev_drv_macros_intr_cause for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetInterruptCauseHi(USBFS_Type const *base)
+{
+ return USBFS_DEV_LPM_INTR_CAUSE_HI(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetInterruptCauseMed
+****************************************************************************//**
+*
+* Returns the mask of bits showing the source of the current triggered
+* interrupt. This is useful for modes of operation where an interrupt can
+* be generated by conditions in multiple interrupt source registers.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* The mask with the OR of the following conditions that have been triggered.
+* See \ref group_usbfs_dev_drv_macros_intr_cause for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetInterruptCauseMed(USBFS_Type const *base)
+{
+ return USBFS_DEV_LPM_INTR_CAUSE_MED(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetInterruptCauseLo
+****************************************************************************//**
+*
+* Returns the mask of bits showing the source of the current triggered
+* interrupt. This is useful for modes of operation where an interrupt can
+* be generated by conditions in multiple interrupt source registers.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* The mask with the OR of the following conditions that have been triggered.
+* See \ref group_usbfs_dev_drv_macros_intr_cause for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetInterruptCauseLo(USBFS_Type const *base)
+{
+ return USBFS_DEV_LPM_INTR_CAUSE_LO(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetInterruptsLevel
+****************************************************************************//**
+*
+* Writes INTR_LVL_SEL register which contains groups for all interrupt sources.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param intrLevel
+* INTR_LVL_SEL register value.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetInterruptsLevel(USBFS_Type *base, uint32_t intrLevel)
+{
+ USBFS_DEV_LPM_INTR_LVL_SEL(base) = intrLevel;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetInterruptsLevel
+****************************************************************************//**
+*
+* Returns the INTR_LVL_SEL register that contains groups for all interrupt sources.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* Returns the INTR_LVL_SEL register that contains groups for all interrupt sources.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetInterruptsLevel(USBFS_Type const *base)
+{
+ return base->USBLPM.INTR_LVL_SEL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_DisableEp0Interrupt
+****************************************************************************//**
+*
+* Enables the Control Endpoint 0 interrupt source.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_DisableEp0Interrupt(USBFS_Type *base)
+{
+ uint32_t mask = (Cy_USBFS_Dev_Drv_GetSieInterruptMask(base) & ~CY_USBFS_DEV_DRV_INTR_SIE_EP0);
+ Cy_USBFS_Dev_Drv_SetSieInterruptMask(base, mask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_EnableEp0Interrupt
+****************************************************************************//**
+*
+* Enables the Control Endpoint 0 interrupt.
+*
+* \param base
+* The pointer to the USBFS instance source.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_EnableEp0Interrupt(USBFS_Type *base)
+{
+ uint32_t mask = (Cy_USBFS_Dev_Drv_GetSieInterruptMask(base) | CY_USBFS_DEV_DRV_INTR_SIE_EP0);
+ Cy_USBFS_Dev_Drv_SetSieInterruptMask(base, mask);
+}
+/** \} group_usbfs_dev_drv_functions_interrupts */
+
+/**
+* \addtogroup group_usbfs_dev_drv_functions_low_power
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_CheckActivity
+****************************************************************************//**
+*
+* Returns the activity status of the bus.
+* It clears the hardware status to provide an updated status on the next call of
+* this function. This function is useful to determine whether there is any USB bus
+* activity between function calls. A typical use case is to determine whether
+* the USB suspend conditions are met.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* The bus activity since the last call.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_USBFS_Dev_Drv_CheckActivity(USBFS_Type *base)
+{
+ uint32_t tmpReg = base->USBDEV.CR1;
+
+ /* Clear hardware status */
+ base->USBDEV.CR1 &= (tmpReg & ~USBFS_USBDEV_CR1_BUS_ACTIVITY_Msk);
+ (void) base->USBDEV.CR1;
+
+ return (0U != (tmpReg & USBFS_USBDEV_CR1_BUS_ACTIVITY_Msk));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_Force
+****************************************************************************//**
+*
+* Forces a USB J, K, or SE0 state on the USB lines.
+* A typical use case is to signal a Remote Wakeup condition on the USB bus.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param state
+* The desired bus state.
+* See \ref cy_en_usbfs_dev_drv_force_bus_state_t for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_Force(USBFS_Type *base, cy_en_usbfs_dev_drv_force_bus_state_t state)
+{
+ base->USBDEV.USBIO_CR0 = (uint32_t) state;
+ (void) base->USBDEV.USBIO_CR0;
+}
+/** \} group_usbfs_dev_drv_functions_low_power */
+
+
+/**
+* \addtogroup group_usbfs_dev_drv_functions_lpm
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_Lpm_GetBeslValue
+****************************************************************************//**
+*
+* Returns the Best Effort Service Latency (BESL) value sent by the host as
+* part of the LPM token transaction.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* BESL value (4-bits)
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_Lpm_GetBeslValue(USBFS_Type const *base)
+{
+ return _FLD2VAL(USBFS_USBLPM_LPM_STAT_LPM_BESL, USBFS_DEV_LPM_LPM_STAT(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_Lpm_RemoteWakeUpAllowed
+****************************************************************************//**
+*
+* Returns the remote wakeup permission set by the Host as part of the
+* LPM token transaction.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* Remote wakeup permission: true - allowed, false - not allowed.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_USBFS_Dev_Drv_Lpm_RemoteWakeUpAllowed(USBFS_Type const *base)
+{
+ return _FLD2BOOL(USBFS_USBLPM_LPM_STAT_LPM_REMOTEWAKE, USBFS_DEV_LPM_LPM_STAT(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_Lpm_SetResponse
+****************************************************************************//**
+*
+* Configures the response in the handshake packet that the device sends when
+* an LPM token packet is received.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param response
+* The response to return for an LPM token packet.
+* See \ref cy_en_usbfs_dev_drv_lpm_req_t for the set of options.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_Lpm_SetResponse(USBFS_Type *base, cy_en_usbfs_dev_drv_lpm_req_t response)
+{
+ USBFS_DEV_LPM_LPM_CTL(base) = _CLR_SET_FLD32U(USBFS_DEV_LPM_LPM_CTL(base),
+ USBFS_USBLPM_LPM_CTL_LPM_RESP, ((uint32_t) response));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_Lpm_GetResponse
+****************************************************************************//**
+*
+* Returns the response value that the device sends as part of the handshake
+* packet when an LPM token packet is received.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* The response to return for an LPM token packet.
+* See \ref cy_en_usbfs_dev_drv_lpm_req_t for the set of options.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(USBFS_Type const *base)
+{
+ uint32_t retValue = _FLD2VAL(USBFS_USBLPM_LPM_CTL_LPM_RESP, USBFS_DEV_LPM_LPM_CTL(base));
+ return (cy_en_usbfs_dev_drv_lpm_req_t) retValue;
+}
+/** \} group_usbfs_dev_drv_functions_lpm */
+
+
+/**
+* \addtogroup group_usbfs_dev_hal_functions_endpoint_config
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_AddEndpoint
+****************************************************************************//**
+*
+* Configures a data endpoint for the following operation (allocates hardware
+* resources for data endpoint).
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param config
+* The pointer to data endpoint configuration \ref cy_stc_usb_dev_ep_config_t.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t
+* allocated by the user. The structure is used during the USBFS Device
+* operation for internal configuration and data retention. The user must not
+* modify anything in this structure.
+*
+* \return
+* The status code of the function execution \ref cy_en_usbfs_dev_drv_status_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_AddEndpoint(USBFS_Type *base,
+ cy_stc_usb_dev_ep_config_t const *config,
+ cy_stc_usbfs_dev_drv_context_t *context)
+{
+ cy_en_usbfs_dev_drv_status_t retStatus = CY_USBFS_DEV_DRV_BAD_PARAM;
+
+ uint32_t endpoint = CY_USBFS_DEV_DRV_EPADDR2EP(config->endpointAddr);
+
+ /* Checks if the endpoint is supported by the driver */
+ if (CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint))
+ {
+ retStatus = context->addEndpoint(base, config, context);
+ }
+
+ return retStatus;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_OverwriteMemcpy
+****************************************************************************//**
+*
+* Overwrites the memory copy (memcpy) function used to copy data with the user-
+* implemented:
+* * \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint copies data from from the internal
+* buffer to the application buffer for OUT endpoint.
+* * \ref Cy_USBFS_Dev_Drv_LoadInEndpoint copies data from the application buffer
+* for IN endpoint to the the internal buffer.
+* Only applicable when endpoint management mode is
+* \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* The data endpoint number.
+*
+* \param memcpyFunc
+* The pointer to the function that copies data.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t
+* allocated by the user. The structure is used during the USBFS Device
+* operation for internal configuration and data retention. The user must not
+* modify anything in this structure.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_OverwriteMemcpy(USBFS_Type const *base,
+ uint32_t endpoint,
+ cy_fn_usbfs_dev_drv_memcpy_ptr_t memcpyFunc,
+ cy_stc_usbfs_dev_drv_context_t *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint));
+
+ endpoint = CY_USBFS_DEV_DRV_EP2PHY(endpoint);
+ context->epPool[endpoint].copyData = memcpyFunc;
+}
+/** \} group_usbfs_dev_hal_functions_endpoint_config */
+
+
+/**
+* \addtogroup group_usbfs_dev_hal_functions_data_xfer
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetEndpointState
+****************************************************************************//**
+*
+* Returns the state of the endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* The data endpoint number.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t
+* allocated by the user. The structure is used during the USBFS Device
+* operation for internal configuration and data retention. The user must not
+* modify anything in this structure.
+*
+* \return
+* Data endpoint state \ref cy_en_usb_dev_ep_state_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_usb_dev_ep_state_t Cy_USBFS_Dev_Drv_GetEndpointState(
+ USBFS_Type const *base,
+ uint32_t endpoint,
+ cy_stc_usbfs_dev_drv_context_t const *context)
+
+{
+ cy_en_usb_dev_ep_state_t retState = CY_USB_DEV_EP_INVALID;
+
+ (void)base; /* Suppress warning */
+
+ if (CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint))
+ {
+ retState = context->epPool[CY_USBFS_DEV_DRV_EP2PHY(endpoint)].state;
+ }
+
+ return retState;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_LoadInEndpoint
+****************************************************************************//**
+*
+* Loads data into the IN endpoint buffer. After data loads, the
+* endpoint is ready to be read by the host.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* The IN data endpoint number.
+*
+* \param buffer
+* The pointer to the buffer containing data bytes to load.
+*
+* \param size
+* The number of bytes to load into the endpoint.
+* This value must be less than or equal to endpoint maximum packet size.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t
+* allocated by the user. The structure is used during the USBFS Device
+* operation for internal configuration and data retention. The user must not
+* modify anything in this structure.
+*
+* \return
+* The status code of the function execution \ref cy_en_usbfs_dev_drv_status_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_LoadInEndpoint(
+ USBFS_Type *base,
+ uint32_t endpoint,
+ uint8_t const *buffer,
+ uint32_t size,
+ cy_stc_usbfs_dev_drv_context_t *context)
+{
+ CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint));
+ CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_DIR_IN(context->epPool[CY_USBFS_DEV_DRV_EP2PHY(endpoint)].address));
+
+ return context->loadInEndpoint(base, CY_USBFS_DEV_DRV_EP2PHY(endpoint), buffer, size, context);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_ReadOutEndpoint
+****************************************************************************//**
+*
+* Reads data from the OUT endpoint buffer.
+* Before executing a next read, the \ref Cy_USBFS_Dev_Drv_EnableOutEndpoint must be
+* called to allow the Host to write data into the endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* The OUT data endpoint number.
+*
+* \param buffer
+* The pointer to the buffer that stores read data.
+*
+* \param size
+* The number of bytes to read from the endpoint.
+* This value must be less than or equal to the endpoint maximum packet size.
+*
+* \param actSize
+* The number of actually read bytes.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t
+* allocated by the user. The structure is used during the USBFS Device
+* operation for internal configuration and data retention. The user must not
+* modify anything in this structure.
+*
+* \return
+* The status code of the function execution \ref cy_en_usbfs_dev_drv_status_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_ReadOutEndpoint(
+ USBFS_Type *base,
+ uint32_t endpoint,
+ uint8_t *buffer,
+ uint32_t size,
+ uint32_t *actSize,
+ cy_stc_usbfs_dev_drv_context_t *context)
+{
+ CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint));
+ CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_DIR_OUT(context->epPool[CY_USBFS_DEV_DRV_EP2PHY(endpoint)].address));
+
+ return context->readOutEndpoint(base, CY_USBFS_DEV_DRV_EP2PHY(endpoint), buffer, size, actSize, context);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetEndpointAckState
+****************************************************************************//**
+*
+* Returns whether the transaction completed with ACK for a certain endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* The data endpoint number.
+*
+* \return
+* ACK state: true - transaction completed with ACK, false - otherwise.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_USBFS_Dev_Drv_GetEndpointAckState(USBFS_Type const *base, uint32_t endpoint)
+{
+ CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint));
+
+ endpoint = CY_USBFS_DEV_DRV_EP2PHY(endpoint);
+ return _FLD2BOOL(USBFS_USBDEV_SIE_EP1_CR0_ACKED_TXN, USBFS_DEV_SIE_EP_CR0(base, endpoint));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetEndpointCount
+****************************************************************************//**
+*
+* Returns the number of data bytes in the transaction for a certain endpoint.
+* Before calling this function, ensure the Host has written data into the
+* endpoint. The returned value is updated after the Host access to the
+* endpoint but remains unchanged after data has been read from the endpoint
+* buffer.
+* A typical use case is to read the number of bytes that the Host wrote into the
+* OUT endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* The data endpoint number.
+*
+* \return
+* The number of data bytes in the transaction.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEndpointCount(USBFS_Type const *base, uint32_t endpoint)
+{
+ CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint));
+
+ return Cy_USBFS_Dev_Drv_GetSieEpCount(base, CY_USBFS_DEV_DRV_EP2PHY(endpoint));
+}
+/** \} group_usbfs_dev_hal_functions_data_xfer */
+
+
+/**
+* \addtogroup group_usbfs_dev_hal_functions_ep0_service
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_Ep0Stall
+****************************************************************************//**
+*
+* Stalls endpoint 0.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_Ep0Stall(USBFS_Type *base)
+{
+ /* Updates the CR registers to STALL a request (CNT register does not care) */
+ Cy_USBFS_Dev_Drv_WriteEp0Mode(base, CY_USBFS_DEV_DRV_EP_CR_STALL_INOUT);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetEp0MaxPacket
+****************************************************************************//**
+*
+* Returns the endpoint 0 maximum packet size that can be for read or write from
+* the endpoint 0 buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* The endpoint 0 maximum packet size (endpoint 0 has a dedicated hardware buffer).
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEp0MaxPacket(USBFS_Type const *base)
+{
+ /* Suppresses a compiler warning about unused variables */
+ (void) base;
+
+ return (CY_USBFS_DEV_DRV_EP0_BUFFER_SIZE);
+}
+
+
+/** \} group_usbfs_dev_hal_functions_ep0_service */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_IP_MXUSBFS */
+
+#endif /* (CY_USBFS_DEV_DRV_H) */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_usbfs_dev_drv_reg.h b/platform/ext/target/psoc64/Native_Driver/include/cy_usbfs_dev_drv_reg.h
new file mode 100644
index 0000000000..3f87d10b22
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_usbfs_dev_drv_reg.h
@@ -0,0 +1,1536 @@
+/***************************************************************************//**
+* \file cy_usbfs_dev_drv_reg.h
+* \version 2.20
+*
+* Provides register access API implementation of the USBFS driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+
+/** \cond INTERNAL */
+
+/**
+* \addtogroup group_usbfs_dev_drv_reg
+* \{
+*
+* Register access API for the USBFS Device block.
+*
+* This is the API that provides an interface to the USBFS Device hardware.
+* These API are intended to be used by the USBFS Device driver to access
+* hardware. You can use these API to implement a custom driver based on
+* the USBFS Device hardware.
+*
+* \defgroup group_usbfs_dev_drv_reg_macros Macros
+* \{
+* \defgroup group_usbfs_dev_drv_reg_macros_hardware Hardware-specific Constants
+* \defgroup group_usbfs_dev_drv_reg_macros_sie_intr SIE Interrupt Sources
+* \defgroup group_usbfs_dev_drv_reg_macros_sie_mode SIE Endpoint Modes
+* \defgroup group_usbfs_dev_drv_reg_macros_arb_ep_intr Arbiter Endpoint Interrupt Sources
+* \}
+*
+* \defgroup group_usbfs_drv_drv_reg_functions Functions
+* \{
+* \defgroup group_usbfs_drv_drv_reg_interrupt_sources SIE Interrupt Sources Registers Access
+* \defgroup group_usbfs_drv_drv_reg_ep0_access Endpoint 0 Registers Access
+* \defgroup group_usbfs_drv_drv_reg_sie_access SIE Data Endpoint Registers Access
+* \defgroup group_usbfs_drv_drv_reg_arbiter Arbiter Endpoint Registers Access
+* \defgroup group_usbfs_drv_drv_reg_arbiter_data Arbiter Endpoint Data Registers Access
+* \defgroup group_usbfs_drv_drv_reg_misc Miscellaneous Functions
+* \}
+*
+* \}
+*/
+
+
+#if !defined(CY_USBFS_DEV_DRV_REG_H)
+#define CY_USBFS_DEV_DRV_REG_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+
+#ifdef CY_IP_MXUSBFS
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Hardware-specific Constants
+*******************************************************************************/
+
+/**
+* \addtogroup group_usbfs_dev_drv_reg_macros_hardware
+* \{
+*/
+/** Number of data endpoints supported by the hardware */
+#define CY_USBFS_DEV_DRV_NUM_EPS_MAX (8U)
+
+/** The hardware buffer size used for data endpoint buffers */
+#define CY_USBFS_DEV_DRV_HW_BUFFER_SIZE (512U)
+
+/** The hardware buffer for endpoint 0 */
+#define CY_USBFS_DEV_DRV_EP0_BUFFER_SIZE (8U)
+/** \} group_usbfs_dev_drv_reg_macros_hardware */
+
+
+/*******************************************************************************
+* Functions
+*******************************************************************************/
+
+/**
+* \addtogroup group_usbfs_drv_drv_reg_interrupt_sources
+* \{
+*/
+/* Access to LPM SIE interrupt sources */
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieInterruptStatus(USBFS_Type const *base);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieInterruptMask (USBFS_Type *base, uint32_t mask);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieInterruptMask (USBFS_Type const *base);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieInterruptStatusMasked(USBFS_Type const *base);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearSieInterrupt (USBFS_Type *base, uint32_t mask);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieInterrupt (USBFS_Type *base, uint32_t mask);
+/** \} group_usbfs_drv_drv_reg_interrupt_sources */
+
+
+/**
+* \addtogroup group_usbfs_drv_drv_reg_ep0_access
+* \{
+*/
+/* Access control endpoint CR0.Mode registers */
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteEp0Mode(USBFS_Type *base, uint32_t mode);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_ReadEp0Mode(USBFS_Type const *base);
+
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetEp0Count(USBFS_Type *base, uint32_t count, uint32_t toggle);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEp0Count(USBFS_Type const *base);
+
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteEp0Data(USBFS_Type *base, uint32_t idx, uint32_t value);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_ReadEp0Data(USBFS_Type const *base, uint32_t idx);
+/** \} group_usbfs_drv_drv_reg_ep0_access */
+
+/**
+* \addtogroup group_usbfs_drv_drv_reg_sie_access
+* \{
+*/
+/* Access SIE data endpoints CR0.Mode registers */
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieEpMode (USBFS_Type *base, uint32_t endpoint, uint32_t mode);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpMode (USBFS_Type const *base, uint32_t endpoint);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieEpStall (USBFS_Type *base, bool inDirection, uint32_t endpoint);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearSieEpStall(USBFS_Type *base, uint32_t endpoint, uint32_t mode);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpError (USBFS_Type const *base, uint32_t endpoint);
+
+/* Access SIE data endpoints CNT0 and CNT1 registers */
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpToggle (USBFS_Type const *base, uint32_t endpoint);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearSieEpToggle(USBFS_Type *base, uint32_t endpoint);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpCount(USBFS_Type const *base, uint32_t endpoint);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieEpCount(USBFS_Type *base, uint32_t endpoint, uint32_t count, uint32_t toggle);
+
+/* Access SIE data endpoints interrupt source registers */
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieAllEpsInterruptStatus(USBFS_Type const *base);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_EnableSieEpInterrupt (USBFS_Type *base, uint32_t endpoint);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_DisableSieEpInterrupt(USBFS_Type *base, uint32_t endpoint);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearSieEpInterrupt (USBFS_Type *base, uint32_t endpoint);
+/** \} group_usbfs_drv_drv_reg_sie_access */
+
+/**
+* \addtogroup group_usbfs_drv_drv_reg_arbiter
+* \{
+*/
+/* Access Arbiter data endpoints interrupt sources registers */
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbAllEpsInterruptStatus(USBFS_Type const *base);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_EnableArbEpInterrupt (USBFS_Type *base, uint32_t endpoint);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_DisableArbEpInterrupt(USBFS_Type *base, uint32_t endpoint);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbEpInterruptMask(USBFS_Type *base, uint32_t endpoint, uint32_t mask);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbEpInterruptMask(USBFS_Type const *base, uint32_t endpoint);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbEpInterruptStatusMasked(USBFS_Type const *base, uint32_t endpoint);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearArbEpInterrupt(USBFS_Type *base, uint32_t endpoint, uint32_t mask);
+
+/* Access Arbiter data endpoints configuration register */
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbEpConfig (USBFS_Type *base, uint32_t endpoint, uint32_t cfg);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbCfgEpInReady (USBFS_Type *base, uint32_t endpoint);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearArbCfgEpInReady (USBFS_Type *base, uint32_t endpoint);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_TriggerArbCfgEpDmaReq(USBFS_Type *base, uint32_t endpoint);
+
+/* Access Arbiter data endpoints WA (Write Address and RA(Read Address) registers */
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbWriteAddr(USBFS_Type *base, uint32_t endpoint, uint32_t wa);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbReadAddr (USBFS_Type *base, uint32_t endpoint, uint32_t ra);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbWriteAddr(USBFS_Type const *base, uint32_t endpoint);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbReadAddr (USBFS_Type const *base, uint32_t endpoint);
+/** \} group_usbfs_drv_drv_reg_arbiter */
+
+/**
+* \addtogroup group_usbfs_drv_drv_reg_arbiter_data
+* \{
+*/
+/* Access data endpoints data registers. Used to get/put data into endpoint buffer */
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteData (USBFS_Type *base, uint32_t endpoint, uint8_t byte);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteData16(USBFS_Type *base, uint32_t endpoint, uint16_t halfword);
+__STATIC_INLINE uint8_t Cy_USBFS_Dev_Drv_ReadData (USBFS_Type const *base, uint32_t endpoint);
+__STATIC_INLINE uint16_t Cy_USBFS_Dev_Drv_ReadData16 (USBFS_Type const *base, uint32_t endpoint);
+__STATIC_INLINE volatile uint32_t * Cy_USBFS_Dev_Drv_GetDataRegAddr (USBFS_Type *base, uint32_t endpoint);
+__STATIC_INLINE volatile uint32_t * Cy_USBFS_Dev_Drv_GetDataReg16Addr(USBFS_Type *base, uint32_t endpoint);
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_FlushInBuffer (USBFS_Type *base, uint32_t endpoint);
+/** \} group_usbfs_drv_drv_reg_arbiter_data */
+
+/**
+* \addtogroup group_usbfs_drv_drv_reg_misc
+* \{
+*/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetEpType (USBFS_Type *base, bool inDirection, uint32_t endpoint);
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSofNubmer(USBFS_Type const *base);
+/** \} group_usbfs_drv_drv_reg_misc */
+
+
+/*******************************************************************************
+* API Constants
+*******************************************************************************/
+
+/** /cond INTERNAL */
+/* Macro to access ODD offset registers: Cypress ID# 299773 */
+#define CY_USBFS_DEV_DRV_WRITE_ODD(val) ( (val) | ((uint32_t) (val) << 8U) )
+#define CY_USBFS_DEV_READ_ODD(reg) ( (uint32_t) (CY_LO8((reg) | ((reg) >> 8U))) )
+/** /endcond */
+
+/**
+* \addtogroup group_usbfs_dev_drv_reg_macros_sie_intr
+* \{
+*/
+#define CY_USBFS_DEV_DRV_INTR_SIE_SOF USBFS_USBLPM_INTR_SIE_SOF_INTR_Msk /**< SOF frame detected */
+#define CY_USBFS_DEV_DRV_INTR_SIE_BUS_RESET USBFS_USBLPM_INTR_SIE_BUS_RESET_INTR_Msk /**< Bus Reset detected */
+#define CY_USBFS_DEV_DRV_INTR_SIE_EP0 USBFS_USBLPM_INTR_SIE_EP0_INTR_Msk /**< EP0 access detected */
+#define CY_USBFS_DEV_DRV_INTR_SIE_LPM USBFS_USBLPM_INTR_SIE_LPM_INTR_Msk /**< Link Power Management request detected */
+#define CY_USBFS_DEV_DRV_INTR_SIE_RESUME USBFS_USBLPM_INTR_SIE_RESUME_INTR_Msk /**< Resume condition detected */
+/** \} group_usbfs_dev_drv_reg_macros_sie_intr */
+
+/**
+* \addtogroup group_usbfs_dev_drv_reg_macros_sie_mode
+* \{
+*/
+/* Modes for endpoint 0 (control endpoint) */
+#define CY_USBFS_DEV_DRV_EP_CR_DISABLE (0U) /**< Data endpoint disabled */
+#define CY_USBFS_DEV_DRV_EP_CR_NAK_INOUT (1U) /**< Data endpoint NAK IN and OUT requests */
+#define CY_USBFS_DEV_DRV_EP_CR_STALL_INOUT (3U) /**< Data endpoint STALL IN and OUT requests */
+#define CY_USBFS_DEV_DRV_EP_CR_STATUS_OUT_ONLY (2U) /**< Data endpoint ACK only Status OUT requests */
+#define CY_USBFS_DEV_DRV_EP_CR_STATUS_IN_ONLY (6U) /**< Data endpoint ACK only Status IN requests */
+#define CY_USBFS_DEV_DRV_EP_CR_ACK_OUT_STATUS_IN (11U) /**< Data endpoint ACK only Data and Status OUT requests */
+#define CY_USBFS_DEV_DRV_EP_CR_ACK_IN_STATUS_OUT (15U) /**< Data endpoint ACK only Data and Status IN requests */
+
+/* Modes for ISO data endpoints */
+#define CY_USBFS_DEV_DRV_EP_CR_ISO_OUT (5U) /**< Data endpoint is ISO OUT */
+#define CY_USBFS_DEV_DRV_EP_CR_ISO_IN (7U) /**< Data endpoint is ISO IN */
+
+/* Modes for Control/Bulk/Interrupt OUT data endpoints */
+#define CY_USBFS_DEV_DRV_EP_CR_NAK_OUT (8U) /**< Data endpoint NAK OUT requests */
+#define CY_USBFS_DEV_DRV_EP_CR_ACK_OUT (9U) /**< Data endpoint ACK OUT requests */
+
+/* Modes for Control/Bulk/Interrupt IN data endpoints */
+#define CY_USBFS_DEV_DRV_EP_CR_NAK_IN (12U) /**< Data endpoint NAK IN requests */
+#define CY_USBFS_DEV_DRV_EP_CR_ACK_IN (13U) /**< Data endpoint ACK IN requests */
+/** \} group_usbfs_dev_drv_reg_macros_sie_mode */
+
+/**
+* \addtogroup group_usbfs_dev_drv_reg_macros_arb_ep_intr ARB_EP_SR/INT_EN 1-8 registers
+* \{
+*/
+
+/** Data endpoint IN buffer full interrupt source */
+#define USBFS_USBDEV_ARB_EP_IN_BUF_FULL_Msk USBFS_USBDEV_ARB_EP1_INT_EN_IN_BUF_FULL_EN_Msk
+/** Data endpoint grant interrupt source (DMA complete read/write) */
+#define USBFS_USBDEV_ARB_EP_DMA_GNT_Msk USBFS_USBDEV_ARB_EP1_INT_EN_DMA_GNT_EN_Msk
+/** Data endpoint overflow interrupt source (applicable only for Automatic DMA mode) */
+#define USBFS_USBDEV_ARB_EP_BUF_OVER_Msk USBFS_USBDEV_ARB_EP1_INT_EN_BUF_OVER_EN_Msk
+/** Data endpoint underflow interrupt source (applicable only for Automatic DMA mode) */
+#define USBFS_USBDEV_ARB_EP_BUF_UNDER_Msk USBFS_USBDEV_ARB_EP1_INT_EN_BUF_UNDER_EN_Msk
+/** Endpoint Error in Transaction interrupt source */
+#define USBFS_USBDEV_ARB_EP_ERR_Msk USBFS_USBDEV_ARB_EP1_INT_EN_ERR_INT_EN_Msk
+/** Data endpoint terminate interrupt source (DMA complete reading) */
+#define USBFS_USBDEV_ARB_EP_DMA_TERMIN_Msk USBFS_USBDEV_ARB_EP1_SR_DMA_TERMIN_Msk
+/** \} group_usbfs_dev_drv_reg_macros_arb_ep_intr */
+
+/**
+* \addtogroup group_usbfs_dev_drv_reg_macros
+* \{
+*/
+/** Data toggle mask in CNT0 register */
+#define USBFS_USBDEV_SIE_EP_DATA_TOGGLE_Msk USBFS_USBDEV_SIE_EP1_CNT0_DATA_TOGGLE_Msk
+/** \} group_usbfs_dev_drv_reg_macros */
+
+/** /cond INTERNAL */
+
+/* Extended cyip_usbfs.h */
+
+/* Count registers includes CRC size (2 bytes) */
+#define CY_USBFS_DEV_DRV_EP_CRC_SIZE (2U)
+
+/* DYN_RECONFIG register */
+#define USBFS_USBDEV_DYN_RECONFIG_EN_Msk USBFS_USBDEV_DYN_RECONFIG_DYN_CONFIG_EN_Msk
+#define USBFS_USBDEV_DYN_RECONFIG_EPNO_Pos USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_EPNO_Pos
+#define USBFS_USBDEV_DYN_RECONFIG_EPNO_Msk USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_EPNO_Msk
+#define USBFS_USBDEV_DYN_RECONFIG_RDY_STS_Msk USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_RDY_STS_Msk
+
+/* LPM_CTL register */
+#define USBFS_USBLPM_LPM_CTL_LPM_RESP_Pos (USBFS_USBLPM_LPM_CTL_LPM_ACK_RESP_Pos)
+#define USBFS_USBLPM_LPM_CTL_LPM_RESP_Msk (USBFS_USBLPM_LPM_CTL_LPM_ACK_RESP_Msk | \
+ USBFS_USBLPM_LPM_CTL_NYET_EN_Msk)
+
+/* ARB_EP_CFG 1-8 registers (default configuration) */
+#define USBFS_USBDEV_ARB_EP_CFG_CRC_BYPASS_Msk USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Msk
+#define USBFS_USBDEV_ARB_EP_CFG_RESET_PTR_Msk USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Msk
+/** /endcond */
+
+
+/*******************************************************************************
+* In-line Function Implementation
+*******************************************************************************/
+
+/**
+* \addtogroup group_usbfs_drv_drv_reg_interrupt_sources
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetSieInterruptStatus
+****************************************************************************//**
+*
+* Returns the SIE interrupt request register.
+* This register contains the current status of the SIE interrupt sources.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* The current status of the SIE interrupt sources.
+* Each constant is a bit field value. The value returned may have multiple
+* bits set to indicate the current status.
+* See \ref group_usbfs_dev_drv_reg_macros_sie_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieInterruptStatus(USBFS_Type const *base)
+{
+ return USBFS_DEV_LPM_INTR_SIE(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetSieInterruptMask
+****************************************************************************//**
+*
+* Writes the SIE interrupt mask register.
+* This register configures which bits from the SIE interrupt request register
+* can trigger an interrupt event.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param mask
+* Enabled SIE interrupt sources.
+* See \ref group_usbfs_dev_drv_reg_macros_sie_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieInterruptMask(USBFS_Type *base, uint32_t mask)
+{
+ USBFS_DEV_LPM_INTR_SIE_MASK(base) = mask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetSieInterruptMask
+****************************************************************************//**
+*
+* Returns the SIE interrupt mask register.
+* This register specifies which bits from the SIE interrupt request register
+* trigger can an interrupt event.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* Enabled SIE interrupt sources.
+* See \ref group_usbfs_dev_drv_reg_macros_sie_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieInterruptMask(USBFS_Type const *base)
+{
+ return USBFS_DEV_LPM_INTR_SIE_MASK(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetSieInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the SIE interrupt masked request register.
+* This register contains a logical AND of corresponding bits from the SIE
+* interrupt request and mask registers.
+* This function is intended to be used in the interrupt service routine to
+* identify which of the enabled SIE interrupt sources caused the interrupt
+* event.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* The current status of enabled SIE interrupt sources.
+* See \ref group_usbfs_dev_drv_reg_macros_sie_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieInterruptStatusMasked(USBFS_Type const *base)
+{
+ return USBFS_DEV_LPM_INTR_SIE_MASKED(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_ClearSieInterrupt
+****************************************************************************//**
+*
+* Clears the SIE interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param mask
+* The SIE interrupt sources to be cleared.
+* See \ref group_usbfs_dev_drv_reg_macros_sie_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearSieInterrupt(USBFS_Type *base, uint32_t mask)
+{
+ USBFS_DEV_LPM_INTR_SIE(base) = mask;
+ (void) USBFS_DEV_LPM_INTR_SIE(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetSieInterrupt
+****************************************************************************//**
+*
+* Sets the SIE interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param mask
+* The SIE interrupt sources to be set in the SIE interrupt request register.
+* See \ref group_usbfs_dev_drv_reg_macros_sie_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieInterrupt(USBFS_Type *base, uint32_t mask)
+{
+ USBFS_DEV_LPM_INTR_SIE_SET(base) = mask;
+}
+/** \} group_usbfs_drv_drv_reg_interrupt_sources */
+
+
+/**
+* \addtogroup group_usbfs_drv_drv_reg_ep0_access
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_WriteEp0Mode
+****************************************************************************//**
+*
+* Sets a mode in the CR0 register of endpoint 0 (clears all other bits in the
+* register).
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param mode
+* SIE mode defines the data endpoint 0 response to a host request.
+* See \ref group_usbfs_dev_drv_reg_macros_sie_mode for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteEp0Mode(USBFS_Type *base, uint32_t mode)
+{
+ USBFS_DEV_EP0_CR(base) = mode;
+ (void) USBFS_DEV_EP0_CR(base);
+}
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_ReadEp0Mode
+****************************************************************************//**
+*
+* Returns a mode in the CR0 register of endpoint 0.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* SIE mode (defines the endpoint 0 response to a host request).
+* See \ref group_usbfs_dev_drv_reg_macros_sie_mode for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_ReadEp0Mode(USBFS_Type const *base)
+{
+ return USBFS_DEV_EP0_CR(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetSieEpCount
+****************************************************************************//**
+*
+* Configures the number of bytes and toggle bit to return to a host read request
+* to endpoint 0.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param count
+* The number of bytes to return to a host read request.
+*
+* \param toggle
+* The data toggle bit.
+* The range of valid values: 0 and \ref USBFS_USBDEV_SIE_EP_DATA_TOGGLE_Msk.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetEp0Count(USBFS_Type *base, uint32_t count, uint32_t toggle)
+{
+ count = _VAL2FLD(USBFS_USBDEV_EP0_CNT_BYTE_COUNT, count);
+ USBFS_DEV_EP0_CNT(base) = CY_USBFS_DEV_DRV_WRITE_ODD(count | toggle);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetEp0Count
+****************************************************************************//**
+*
+* Returns the number of data bytes written into endpoint 0 by the host.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* The number of bytes written by the host into the endpoint.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEp0Count(USBFS_Type const *base)
+{
+ uint32_t ep0Cnt = CY_USBFS_DEV_READ_ODD(USBFS_DEV_EP0_CNT(base));
+
+ /* Excludes the CRC size */
+ return (_FLD2VAL(USBFS_USBDEV_EP0_CNT_BYTE_COUNT, ep0Cnt) - CY_USBFS_DEV_DRV_EP_CRC_SIZE);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_WriteEp0Data
+****************************************************************************//**
+*
+* Writes an 8-bit byte into the endpoint 0 hardware buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param idx
+* The index of the endpoint 0 hardware buffer entry.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_EP0_BUFFER_SIZE - 1 ).
+*
+* \param value
+* The value to be written into the endpoint 0 hardware buffer.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteEp0Data(USBFS_Type *base, uint32_t idx, uint32_t value)
+{
+ if (0U == (idx & 0x1U))
+ {
+ USBFS_DEV_EP0_DR(base, idx) = value;
+ }
+ else
+ {
+ /* Applies a special write for odd offset registers */
+ USBFS_DEV_EP0_DR(base, idx) = CY_USBFS_DEV_DRV_WRITE_ODD(value);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_ReadEp0Data
+****************************************************************************//**
+*
+* Reads an 8-bit byte from the endpoint 0 hardware buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param idx
+* The index of the endpoint 0 hardware buffer entry.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_EP0_BUFFER_SIZE - 1 ).
+*
+* \return
+* The byte of data to read from the hardware buffer.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_ReadEp0Data(USBFS_Type const *base, uint32_t idx)
+{
+ uint32_t value;
+
+ if (0U == (idx & 0x1U))
+ {
+ value = USBFS_DEV_EP0_DR(base, idx);
+ }
+ else
+ {
+ /* Applies a special write for odd offset registers */
+ value = CY_USBFS_DEV_READ_ODD(USBFS_DEV_EP0_DR(base, idx));
+ }
+
+ return (value);
+}
+/** \} group_usbfs_drv_drv_reg_ep0_access */
+
+
+/**
+* \addtogroup group_usbfs_drv_drv_reg_sie_access
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetSieEpMode
+****************************************************************************//**
+*
+* Sets SIE mode in the CR0 register of the endpoint (does not touch other bits).
+* All other bits except NAK_INT_EN are cleared by the hardware on any write
+* in the register.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \param mode
+* SIE mode defines data endpoint response to host request.
+* See \ref group_usbfs_dev_drv_reg_macros_sie_mode for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieEpMode(USBFS_Type *base, uint32_t endpoint, uint32_t mode)
+{
+ USBFS_DEV_SIE_EP_CR0(base, endpoint) = _CLR_SET_FLD32U(USBFS_DEV_SIE_EP_CR0(base, endpoint),
+ USBFS_USBDEV_SIE_EP1_CR0_MODE, mode);
+ (void) USBFS_DEV_SIE_EP_CR0(base, endpoint);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetSieEpMode
+****************************************************************************//**
+*
+* Returns SIE mode in the CR0 register of the endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \return
+* SIE mode (defines data endpoint response to host request).
+* See \ref group_usbfs_dev_drv_reg_macros_sie_mode for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpMode(USBFS_Type const *base, uint32_t endpoint)
+{
+ return (USBFS_DEV_SIE_EP_CR0(base, endpoint) & USBFS_USBDEV_SIE_EP1_CR0_MODE_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetSieEpStall
+****************************************************************************//**
+*
+* Configures endpoint to STALL requests.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param inDirection
+* Defines whether endpoint direction is IN (true) or OUT (false).
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieEpStall(USBFS_Type *base, bool inDirection, uint32_t endpoint)
+{
+ /* STALL endpoint */
+ USBFS_DEV_SIE_EP_CR0(base, endpoint) = USBFS_USBDEV_SIE_EP1_CR0_STALL_Msk |
+ (inDirection ? CY_USBFS_DEV_DRV_EP_CR_ACK_IN :
+ CY_USBFS_DEV_DRV_EP_CR_ACK_OUT);
+ (void) USBFS_DEV_SIE_EP_CR0(base, endpoint);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_ClearSieEpStall
+****************************************************************************//**
+*
+* Writes SIE mode register of the data endpoint and clears other bits in this
+* register.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \param mode
+* SIE mode defines data endpoint response to host request.
+* See \ref group_usbfs_dev_drv_reg_macros_sie_mode for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearSieEpStall(USBFS_Type *base, uint32_t endpoint, uint32_t mode)
+{
+ /* Set mode bits */
+ uint32_t regVal = _CLR_SET_FLD32U(USBFS_DEV_SIE_EP_CR0(base, endpoint),
+ USBFS_USBDEV_SIE_EP1_CR0_MODE, mode);
+
+ /* Clear STALL condition */
+ regVal &= ~USBFS_USBDEV_SIE_EP1_CR0_STALL_Msk;
+
+ /* Clear STALL condition and set mode */
+ USBFS_DEV_SIE_EP_CR0(base, endpoint) = regVal;
+ (void) USBFS_DEV_SIE_EP_CR0(base, endpoint);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetSieEpError
+****************************************************************************//**
+*
+* Returns value of data endpoint error in transaction bit.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \return
+* Value of data endpoint error in transaction bit.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpError(USBFS_Type const *base, uint32_t endpoint)
+{
+ return (USBFS_DEV_SIE_EP_CR0(base, endpoint) & USBFS_USBDEV_SIE_EP1_CR0_ERR_IN_TXN_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetSieEpToggle
+****************************************************************************//**
+*
+* Returns current value of data endpoint toggle bit.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \return
+* Value of data endpoint toggle bit.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpToggle(USBFS_Type const *base, uint32_t endpoint)
+{
+ /* Return data toggle bit */
+ return (USBFS_DEV_SIE_EP_CNT0(base, endpoint) & USBFS_USBDEV_SIE_EP1_CNT0_DATA_TOGGLE_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_ClearSieEpToggle
+****************************************************************************//**
+*
+* Resets to zero data endpoint toggle bit.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \return
+* Number of bytes written by the host into the endpoint.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearSieEpToggle(USBFS_Type *base, uint32_t endpoint)
+{
+ /* Clear data toggle bit */
+ USBFS_DEV_SIE_EP_CNT0(base, endpoint) &= ~USBFS_USBDEV_SIE_EP1_CNT0_DATA_TOGGLE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetSieEpCount
+****************************************************************************//**
+*
+* Returns the number of data bytes written into the OUT data endpoint
+* by the host.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \return
+* Number of bytes written by the host into the endpoint.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpCount(USBFS_Type const *base, uint32_t endpoint)
+{
+ uint32_t size;
+
+ /* Get number of bytes transmitted or received by SIE */
+ size = _FLD2VAL(USBFS_USBDEV_SIE_EP1_CNT0_DATA_COUNT_MSB, USBFS_DEV_SIE_EP_CNT0(base, endpoint));
+ size = (size << 8U) | CY_USBFS_DEV_READ_ODD(USBFS_DEV_SIE_EP_CNT1(base, endpoint));
+
+ /* Exclude CRC size */
+ return (size - CY_USBFS_DEV_DRV_EP_CRC_SIZE);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetSieEpCount
+****************************************************************************//**
+*
+* Configures number of bytes and toggle bit to return on the host read request
+* to the IN data endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \param count
+* The number of bytes to return on the host read request.
+*
+* \param toggle
+* The data toggle bit.
+* The range of valid values: 0 and \ref USBFS_USBDEV_SIE_EP_DATA_TOGGLE_Msk.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieEpCount(USBFS_Type *base, uint32_t endpoint,
+ uint32_t count, uint32_t toggle)
+{
+ USBFS_DEV_SIE_EP_CNT1(base, endpoint) = (uint32_t) CY_USBFS_DEV_DRV_WRITE_ODD(CY_LO8(count));
+ USBFS_DEV_SIE_EP_CNT0(base, endpoint) = (uint32_t) CY_HI8(count) | toggle;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetSieAllEpsInterruptStatus
+****************************************************************************//**
+*
+* Returns the SIE data endpoints interrupt request register.
+* This register contains the current status of the SIE data endpoints transfer
+* completion interrupt.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* The current status of the SIE interrupt sources.
+* The returned status specifies for which endpoint interrupt is active as
+* follows: bit 0 corresponds to data endpoint 1, bit 1 data endpoint 2 and so
+* on up to \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieAllEpsInterruptStatus(USBFS_Type const *base)
+{
+ return USBFS_DEV_SIE_EP_INT_SR(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_EnableSieEpInterrupt
+****************************************************************************//**
+*
+* Enables SIE data endpoint transfer completion interrupt.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_EnableSieEpInterrupt(USBFS_Type *base, uint32_t endpoint)
+{
+ USBFS_DEV_SIE_EP_INT_EN(base) |= (uint32_t)(1UL << endpoint);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_DisableSieEpInterrupt
+****************************************************************************//**
+*
+* Disables SIE data endpoint transfer completion interrupt.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_DisableSieEpInterrupt(USBFS_Type *base, uint32_t endpoint)
+{
+ USBFS_DEV_SIE_EP_INT_EN(base) &= ~ (uint32_t)(1UL << endpoint);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_ClearSieEpInterrupt
+****************************************************************************//**
+*
+* Clears the SIE EP interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearSieEpInterrupt(USBFS_Type *base, uint32_t endpoint)
+{
+ USBFS_DEV_SIE_EP_INT_SR(base) = (uint32_t)(1UL << endpoint);
+ (void) USBFS_DEV_SIE_EP_INT_SR(base);
+}
+/** \} group_usbfs_drv_drv_reg_sie_access */
+
+
+/**
+* \addtogroup group_usbfs_drv_drv_reg_arbiter
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetArbAllEpsInterruptStatus
+****************************************************************************//**
+*
+* Returns the arbiter interrupt request register.
+* This register contains the current status of the data endpoints arbiter
+* interrupt.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* The current status of the SIE interrupt sources.
+* The returned status specifies for which endpoint interrupt is active as
+* follows: bit 0 corresponds to data endpoint 1, bit 1 data endpoint 2, and so
+* on up to \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbAllEpsInterruptStatus(USBFS_Type const *base)
+{
+ return CY_USBFS_DEV_READ_ODD(USBFS_DEV_ARB_INT_SR(base));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_EnableArbEpInterrupt
+****************************************************************************//**
+*
+* Enables the arbiter interrupt for the specified data endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_EnableArbEpInterrupt(USBFS_Type *base, uint32_t endpoint)
+{
+ USBFS_DEV_ARB_INT_EN(base) |= (uint32_t)(1UL << endpoint);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_DisableArbEpInterrupt
+****************************************************************************//**
+*
+* Disabled arbiter interrupt for the specified data endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_DisableArbEpInterrupt(USBFS_Type *base, uint32_t endpoint)
+{
+ USBFS_DEV_ARB_INT_EN(base) &= ~(uint32_t)(1UL << endpoint);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetArbEpInterruptMask
+****************************************************************************//**
+*
+* Enables the arbiter interrupt sources which trigger the arbiter interrupt for
+* the specified data endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \param mask
+* The arbiter interrupt sources.
+* See \ref group_usbfs_dev_drv_reg_macros_arb_ep_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbEpInterruptMask(USBFS_Type *base, uint32_t endpoint, uint32_t mask)
+{
+ USBFS_DEV_ARB_EP_INT_EN(base, endpoint) = mask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetArbEpInterruptMask
+****************************************************************************//**
+*
+* Returns the arbiter interrupt sources which trigger the arbiter interrupt for
+* the specified data endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \return
+* The arbiter interrupt sources.
+* See \ref group_usbfs_dev_drv_reg_macros_arb_ep_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbEpInterruptMask(USBFS_Type const *base, uint32_t endpoint)
+{
+ return USBFS_DEV_ARB_EP_INT_EN(base, endpoint);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetArbEpInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the current status of the enabled arbiter interrupt sources for
+* the specified data endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \return
+* The current status of the enabled arbiter interrupt sources
+* See \ref group_usbfs_dev_drv_reg_macros_arb_ep_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbEpInterruptStatusMasked(USBFS_Type const *base, uint32_t endpoint)
+{
+ uint32_t mask = CY_USBFS_DEV_READ_ODD(USBFS_DEV_ARB_EP_INT_EN(base, endpoint));
+ return (USBFS_DEV_ARB_EP_SR(base, endpoint) & mask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_ClearArbEpInterrupt
+****************************************************************************//**
+*
+* Clears the current status of the arbiter interrupt sources for the specified
+* data endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \param mask
+* The arbiter interrupt sources to be cleared.
+* See \ref group_usbfs_dev_drv_reg_macros_arb_ep_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearArbEpInterrupt(USBFS_Type *base, uint32_t endpoint, uint32_t mask)
+{
+ USBFS_DEV_ARB_EP_SR(base, endpoint) = mask;
+ (void) USBFS_DEV_ARB_EP_SR(base, endpoint);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetArbEpConfig
+****************************************************************************//**
+*
+* Writes the configuration register for the specified data endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \param cfg
+* The value written into the data endpoint configuration register.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbEpConfig(USBFS_Type *base, uint32_t endpoint, uint32_t cfg)
+{
+ USBFS_DEV_ARB_EP_CFG(base, endpoint) = cfg;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetArbCfgEpInReady
+****************************************************************************//**
+*
+* Notifies hardware that IN endpoint data buffer is read to be loaded in
+* the hardware buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbCfgEpInReady(USBFS_Type *base, uint32_t endpoint)
+{
+ USBFS_DEV_ARB_EP_CFG(base, endpoint) |= USBFS_USBDEV_ARB_EP1_CFG_IN_DATA_RDY_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_ClearArbCfgEpInReady
+****************************************************************************//**
+*
+* Clears hardware notification that IN endpoint data buffer is read to be loaded
+* in the hardware buffer. This function needs to be called after buffer was
+* copied into the hardware buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearArbCfgEpInReady(USBFS_Type *base, uint32_t endpoint)
+{
+ USBFS_DEV_ARB_EP_CFG(base, endpoint) &= ~USBFS_USBDEV_ARB_EP1_CFG_IN_DATA_RDY_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_TriggerArbCfgEpDmaReq
+****************************************************************************//**
+*
+* Triggers a DMA request to read from or write data into the hardware buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_TriggerArbCfgEpDmaReq(USBFS_Type *base, uint32_t endpoint)
+{
+ /* Generates DMA request */
+ USBFS_DEV_ARB_EP_CFG(base, endpoint) |= USBFS_USBDEV_ARB_EP1_CFG_DMA_REQ_Msk;
+ (void) USBFS_DEV_ARB_EP_CFG(base, endpoint);
+ USBFS_DEV_ARB_EP_CFG(base, endpoint) &= ~USBFS_USBDEV_ARB_EP1_CFG_DMA_REQ_Msk;
+ (void) USBFS_DEV_ARB_EP_CFG(base, endpoint);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetArbWriteAddr
+****************************************************************************//**
+*
+* Sets write address in the hardware buffer for the specified endpoint.
+* This is the start address of the endpoint buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \param wa
+* Write address value.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbWriteAddr(USBFS_Type *base, uint32_t endpoint, uint32_t wa)
+{
+ USBFS_DEV_ARB_RW_WA16(base, endpoint) = wa;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetArbReadAddr
+****************************************************************************//**
+*
+* Sets read address in the hardware buffer for the specified endpoint.
+* This is the start address of the endpoint buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \param ra
+* Read address value.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbReadAddr(USBFS_Type *base, uint32_t endpoint, uint32_t ra)
+{
+ USBFS_DEV_ARB_RW_RA16(base, endpoint) = ra;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetArbWriteAddr
+****************************************************************************//**
+*
+* Returns write address in the hardware buffer for the specified endpoint.
+* This is the start address of the endpoint buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \return
+* Write address in the hardware buffer for the specified endpoint.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbWriteAddr(USBFS_Type const *base, uint32_t endpoint)
+{
+ return (USBFS_DEV_ARB_RW_WA16(base, endpoint));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetArbReadAddr
+****************************************************************************//**
+*
+* Returns read address in the hardware buffer for the specified endpoint.
+* This is the start address of the endpoint buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \return
+* Read address in the hardware buffer for the specified endpoint.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbReadAddr(USBFS_Type const *base, uint32_t endpoint)
+{
+ return (USBFS_DEV_ARB_RW_RA16(base, endpoint));
+}
+/** \} group_usbfs_drv_drv_reg_arbiter */
+
+
+/**
+* \addtogroup group_usbfs_drv_drv_reg_arbiter_data
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_WriteData
+****************************************************************************//**
+*
+* Writes a byte (8-bit) into the hardware buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \param byte
+* The byte of data to be written into the hardware buffer.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteData(USBFS_Type *base, uint32_t endpoint, uint8_t byte)
+{
+ USBFS_DEV_ARB_RW_DR(base, endpoint) = (uint32_t) byte;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_WriteData16
+****************************************************************************//**
+*
+* Writes a half-word (16-bit) into the hardware buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \param halfword
+* The half-word of data to be written into the hardware buffer.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteData16(USBFS_Type *base, uint32_t endpoint, uint16_t halfword)
+{
+ USBFS_DEV_ARB_RW_DR16(base, endpoint) = (uint32_t) halfword;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_ReadData
+****************************************************************************//**
+*
+* Reads a byte (8-bit) from the hardware buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \return
+* The byte of data to be read from the hardware buffer.
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_USBFS_Dev_Drv_ReadData(USBFS_Type const *base, uint32_t endpoint)
+{
+ return ((uint8_t) USBFS_DEV_ARB_RW_DR(base, endpoint));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_ReadData16
+****************************************************************************//**
+*
+* Reads a half-word (16-bit) from the hardware buffer.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \return
+* The half-word of data to be read from the hardware buffer.
+*
+*******************************************************************************/
+__STATIC_INLINE uint16_t Cy_USBFS_Dev_Drv_ReadData16(USBFS_Type const *base, uint32_t endpoint)
+{
+ return ((uint16_t) USBFS_DEV_ARB_RW_DR16(base, endpoint));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetDataRegAddr
+****************************************************************************//**
+*
+* Returns pointer to the 8-bit data register for the specified endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+* \return
+* The pointer to the 8-bit data register for the specified endpoint.
+*
+*******************************************************************************/
+__STATIC_INLINE volatile uint32_t * Cy_USBFS_Dev_Drv_GetDataRegAddr(USBFS_Type *base, uint32_t endpoint)
+{
+ return (&USBFS_DEV_ARB_RW_DR(base, endpoint));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetDataReg16Addr
+****************************************************************************//**
+*
+* Returns pointer to the 16-bit data register for the specified endpoint.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range (0 - \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1).
+*
+* \return
+* The pointer to the 16-bit data register for the specified endpoint.
+*
+*******************************************************************************/
+__STATIC_INLINE volatile uint32_t * Cy_USBFS_Dev_Drv_GetDataReg16Addr(USBFS_Type *base, uint32_t endpoint)
+{
+ return (&USBFS_DEV_ARB_RW_DR16(base, endpoint));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_FlushInBuffer
+****************************************************************************//**
+*
+* Flushes IN endpoint buffer: sets WA pointer (controlled by CPU/DMA) to equal
+* RA (controlled by SIE; gets automatically reset on transfer completion).
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_FlushInBuffer(USBFS_Type *base, uint32_t endpoint)
+{
+ Cy_USBFS_Dev_Drv_SetArbWriteAddr(base, endpoint,
+ Cy_USBFS_Dev_Drv_GetArbReadAddr(base, endpoint));
+}
+/** \} group_usbfs_drv_drv_reg_arbiter_data */
+
+
+/**
+* \addtogroup group_usbfs_drv_drv_reg_misc
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_SetEpType
+****************************************************************************//**
+*
+* Sets the data endpoint direction.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \param inDirection
+* Defines whether endpoint direction is IN (true) or OUT (false).
+*
+* \param endpoint
+* Physical endpoint number.
+* Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetEpType(USBFS_Type *base, bool inDirection, uint32_t endpoint)
+{
+ uint32_t mask = (uint32_t) (0x1UL << endpoint);
+ uint32_t regValue = CY_USBFS_DEV_READ_ODD(USBFS_DEV_EP_TYPE(base));
+
+ if (inDirection)
+ {
+ /* IN direction: clear bit */
+ regValue &= ~mask;
+ }
+ else
+ {
+ /* OUT direction: set bit */
+ regValue |= mask;
+ }
+
+ USBFS_DEV_EP_TYPE(base) = CY_USBFS_DEV_DRV_WRITE_ODD(regValue);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_USBFS_Dev_Drv_GetSofNubmer
+****************************************************************************//**
+*
+* Returns the SOF frame number.
+*
+* \param base
+* The pointer to the USBFS instance.
+*
+* \return
+* The SOF frame number.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSofNubmer(USBFS_Type const *base)
+{
+ return _FLD2VAL(USBFS_USBDEV_SOF16_FRAME_NUMBER16, USBFS_DEV_SOF16(base));
+}
+/** \} group_usbfs_drv_drv_reg_misc */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_IP_MXUSBFS */
+
+#endif /* (CY_USBFS_DEV_DRV_REG_H) */
+
+/** \endcond */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/include/cy_wdt.h b/platform/ext/target/psoc64/Native_Driver/include/cy_wdt.h
new file mode 100644
index 0000000000..8bba1d06b5
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/include/cy_wdt.h
@@ -0,0 +1,450 @@
+/***************************************************************************//**
+* \file cy_wdt.h
+* \version 1.10.1
+*
+* This file provides constants and parameter values for the WDT driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+* \addtogroup group_wdt
+* \{
+*
+* The Watchdog timer (WDT) has a 16-bit free-running up-counter.
+*
+* The functions and other declarations used in this driver are in cy_wdt.h.
+* You can include cy_pdl.h (ModusToolbox only) to get access to all functions
+* and declarations in the PDL.
+*
+* The WDT can issue counter match interrupts, and a device reset if its interrupts are not
+* handled. Use the Watchdog timer for two main purposes:
+*
+* The <b> First use case </b> is recovering from a CPU or firmware failure.
+* A timeout period is set up in the Watchdog timer, and if a timeout occurs, the
+* device is reset (WRES). <br>
+* The <b>Second use case</b> is to generate periodic interrupts.
+* It is strongly recommended not to use the WDT for periodic interrupt
+* generation. However, if absolutely required, see information below.
+*
+* A "reset cause" register exists, and the firmware should check this register
+* at a start-up. An appropriate action can be taken if a WRES reset is detected.
+*
+* The user's firmware periodically resets the timeout period (clears or "feeds"
+* the watchdog) before a timeout occurs. If the firmware fails to do so, that is
+* considered to be a CPU crash or a firmware failure, and the reason for a
+* device reset.
+* The WDT can generate an interrupt instead of a device reset. The Interrupt
+* Service Routine (ISR) can handle the interrupt either as a periodic interrupt,
+* or as an early indication of a firmware failure and respond accordingly.
+* However, it is not recommended to use the WDT for periodic interrupt
+* generation. The Multi-counter Watchdog Timers (MCWDT) can be used to generate
+* periodic interrupts if such are presented in the device.
+*
+* <b> Functional Description </b>
+*
+* The WDT generates an interrupt when the count value in the counter equals the
+* configured match value.
+*
+* Note that the counter is not reset on a match. In such case the WDT
+* reset period is:
+* WDT_Reset_Period = ILO_Period * (2*2^(16-IgnoreBits) + MatchValue);
+* When the counter reaches a match value, it generates an interrupt and then
+* keeps counting up until it overflows and rolls back to zero and reaches the
+* match value again, at which point another interrupt is generated.
+*
+* To use a WDT to generate a periodic interrupt, the match value should be
+* incremented in the ISR. As a result, the next WDT interrupt is generated when
+* the counter reaches a new match value.
+*
+* You can also reduce the entire WDT counter period by
+* specifying the number of most significant bits that are ignored in the WDT
+* counter. For example, if the Cy_WDT_SetIgnoreBits() function is called with
+* parameter 3, the WDT counter becomes a 13-bit free-running up-counter.
+*
+* <b> Power Modes </b>
+*
+* WDT can operate in all possible low power modes.
+* Operation during Hibernate mode is possible because the logic and
+* high-voltage internal low oscillator (ILO) are supplied by the external
+* high-voltage supply (Vddd). The WDT can be configured to wake the device from
+* Hibernate mode.
+*
+* In CPU Active mode, an interrupt request from the WDT is sent to the
+* CPU. In CPU Sleep, CPU Deep Sleep mode, the CPU subsystem
+* is powered down, so the interrupt request from the WDT is sent directly to the
+* WakeUp Interrupt Controller (WIC) which will then wake up the CPU. The
+* CPU then acknowledges the interrupt request and executes the ISR.
+*
+* <b> Clock Source </b>
+*
+* The WDT is clocked by the ILO. The WDT must be disabled before disabling
+* the ILO. According to the device datasheet, the ILO accuracy is +/-30% over
+* voltage and temperature. This means that the timeout period may vary by 30%
+* from the configured value. Appropriate margins should be added while
+* configuring WDT intervals to make sure that unwanted device resets do not
+* occur on some devices.
+*
+* Refer to the device datasheet for more information on the oscillator accuracy.
+*
+* <b> Register Locking </b>
+*
+* You can prevent accidental corruption of the WDT configuration by calling
+* the Cy_WDT_Lock() function. When the WDT is locked, any writing to the WDT_*,
+* CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers is
+* ignored.
+* Call the Cy_WDT_Unlock() function to allow registers modification, mentioned
+* above.
+*
+* Note that the WDT lock state is not retained during system Deep Sleep. After
+* the wakeup from system Deep Sleep the WDT is locked.
+*
+* <b> Clearing WDT </b>
+*
+* The ILO clock is asynchronous to the SysClk. Therefore it generally
+* takes three ILO cycles for WDT register changes to come into effect. It is
+* important to remember that a WDT should be cleared at least four cycles
+* (3 + 1 for sure) before a timeout occurs, especially when small
+* match values / low-toggle bit numbers are used.
+*
+* \warning It may happen that a WDT reset can be generated
+* faster than a device start-up. To prevent this, calculate the
+* start-up time and WDT reset time. The WDT reset time should be always greater
+* than device start-up time.
+*
+* <b> Reset Detection </b>
+*
+* Use the Cy_SysLib_GetResetReason() function to detect whether the WDT has
+* triggered a device reset.
+*
+* <b> Interrupt Configuration </b>
+*
+* If the WDT is configured to generate an interrupt, pending
+* interrupts must be cleared within the ISR (otherwise, the interrupt will be
+* generated continuously).
+* A pending interrupt to the WDT block must be cleared by calling the
+* Cy_WDT_ClearInterrupt() function. The call to the function will clear the
+* unhandled WDT interrupt counter.
+*
+* Use the WDT ISR as a timer to trigger certain actions
+* and to change a next WDT match value.
+*
+* Ensure that the interrupts from the WDT are passed to the CPU to avoid
+* unregistered interrupts. Unregistered WDT interrupts result in a continuous
+* device reset. To avoid this, call Cy_WDT_UnmaskInterrupt().
+* After that, call the WDT API functions for interrupt
+* handling/clearing.
+*
+* \section group_wdt_configuration Configuration Considerations
+*
+* To start the WDT, make sure that ILO is enabled.
+* After the ILO is enabled, ensure that the WDT is unlocked and disabled by
+* calling the Cy_WDT_Unlock() and Cy_WDT_Disable() functions. Set the WDT match
+* value by calling Cy_WDT_SetMatch() with the required match value. If needed,
+* set the ignore bits for reducing the WDT counter period by calling
+* Cy_WDT_SetIgnoreBits() function. After the WDT configuration is set,
+* call Cy_WDT_Enable().
+*
+* \note Enable a WDT if the power supply can produce
+* sudden brownout events that may compromise the CPU functionality. This
+* ensures that the system can recover after a brownout.
+*
+* When the WDT is used to protect against system crashes, the
+* WDT interrupt should be cleared by a portion of the code that is not directly
+* associated with the WDT interrupt.
+* Otherwise, it is possible that the main firmware loop has crashed or is in an
+* endless loop, but the WDT interrupt vector continues to operate and service
+* the WDT. The user should:
+* * Feed the watchdog by clearing the interrupt bit regularly in the main body
+* of the firmware code.
+*
+* * Guarantee that the interrupt is cleared at least once every WDT period.
+*
+* * Use the WDT ISR only as a timer to trigger certain actions and to change the
+* next match value.
+*
+* \section group_wdt_section_more_information More Information
+*
+* For more information on the WDT peripheral, refer to the technical reference
+* manual (TRM).
+*
+* \section group_wdt_MISRA MISRA-C Compliance
+* The WDT driver does not have any specific deviations.
+*
+* \section group_wdt_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Added info that the WDT lock state is not retained during
+* system Deep Sleep power mode.
+* </td>
+* <td>Documentation updates.</td>
+* </tr>
+* <tr>
+* <td rowspan="4">1.10</td>
+* <td>Flattened the organization of the driver source code into the single
+* source directory and the single include directory.
+* </td>
+* <td>Driver library directory-structure simplification.</td>
+* </tr>
+* <tr>
+* <td> Removed critical section usage in the following functions:
+* - \ref Cy_WDT_Init()
+* - \ref Cy_WDT_Lock()
+* - \ref Cy_WDT_Unlock()
+* </td>
+* <td>Driver functions simplification</td>
+* </tr>
+* <tr>
+* <td>Updated the \ref Cy_WDT_Init(), \ref Cy_WDT_Enable() to clear WDT interrupt.</td>
+* <td>Corner case reliability improvements</td>
+* </tr>
+* <tr>
+* <td>Added register access layer. Use register access macros instead
+* of direct register access using dereferenced pointers.</td>
+* <td>Makes register access device-independent, so that the PDL does
+* not need to be recompiled for each supported part number.</td>
+* </tr>
+* <tr>
+* <td>1.0.2</td>
+* <td>Minor documentation updates</td>
+* <td>Corrected info about a reset generation</td>
+* </tr>
+* <tr>
+* <td>1.0.1</td>
+* <td>General documentation updates</td>
+* <td>Added info about periodic interrupt generation use case</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_wdt_macros Macros
+* \defgroup group_wdt_functions Functions
+*
+*/
+
+#if !defined(CY_WDT_H)
+#define CY_WDT_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "cy_device_headers.h"
+#include "cy_device.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Function Constants
+*******************************************************************************/
+
+/**
+* \addtogroup group_wdt_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_WDT_DRV_VERSION_MAJOR 1
+
+/** The driver minor version */
+#define CY_WDT_DRV_VERSION_MINOR 10
+
+/** The internal define for the first iteration of WDT unlocking */
+#define CY_SRSS_WDT_LOCK_BIT0 ((uint32_t)0x01U << 30U)
+
+/** The internal define for the second iteration of WDT unlocking */
+#define CY_SRSS_WDT_LOCK_BIT1 ((uint32_t)0x01U << 31U)
+
+/** The WDT default match value */
+#define CY_SRSS_WDT_DEFAULT_MATCH_VALUE ((uint32_t) 4096U)
+
+/** The default match value of the WDT ignore bits */
+#define CY_SRSS_WDT_DEFAULT_IGNORE_BITS (0U)
+
+/** The default match value of the WDT ignore bits */
+#define CY_SRSS_WDT_LOCK_BITS (3U)
+
+/** The WDT driver identifier */
+#define CY_WDT_ID CY_PDL_DRV_ID(0x34U)
+
+/** \} group_wdt_macros */
+
+/** \cond Internal */
+
+/** The WDT maximum match value */
+#define WDT_MAX_MATCH_VALUE (0xFFFFuL)
+
+/** The WDT maximum match value */
+#define WDT_MAX_IGNORE_BITS (0xFuL)
+
+/* Internal macro to validate match value */
+#define CY_WDT_IS_MATCH_VAL_VALID(match) ((match) <= WDT_MAX_MATCH_VALUE)
+
+/* Internal macro to validate match value */
+#define CY_WDT_IS_IGNORE_BITS_VALID(bitsNum) ((bitsNum) <= WDT_MAX_IGNORE_BITS)
+
+/** \endcond */
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+/**
+* \addtogroup group_wdt_functions
+* @{
+*/
+/* WDT API */
+void Cy_WDT_Init(void);
+__STATIC_INLINE void Cy_WDT_Enable(void);
+__STATIC_INLINE void Cy_WDT_Disable(void);
+void Cy_WDT_Lock(void);
+void Cy_WDT_Unlock(void);
+__STATIC_INLINE uint32_t Cy_WDT_GetCount(void);
+void Cy_WDT_SetMatch(uint32_t match);
+__STATIC_INLINE uint32_t Cy_WDT_GetMatch(void);
+void Cy_WDT_SetIgnoreBits(uint32_t bitsNum);
+__STATIC_INLINE uint32_t Cy_WDT_GetIgnoreBits(void);
+__STATIC_INLINE void Cy_WDT_MaskInterrupt(void);
+__STATIC_INLINE void Cy_WDT_UnmaskInterrupt(void);
+void Cy_WDT_ClearInterrupt(void);
+void Cy_WDT_ClearWatchdog(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_Enable
+****************************************************************************//**
+*
+* Enables the Watchdog timer.
+*
+* \sideeffect
+* This function clears the WDT interrupt.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_WDT_Enable(void)
+{
+ SRSS_WDT_CTL |= _VAL2FLD(SRSS_WDT_CTL_WDT_EN, 1U);
+ Cy_WDT_ClearInterrupt();
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_Disable
+****************************************************************************//**
+*
+* Disables the Watchdog timer. The Watchdog timer should be unlocked before being
+* disabled. Call the Cy_WDT_Unlock() API to unlock the WDT.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_WDT_Disable(void)
+{
+ SRSS_WDT_CTL &= ((uint32_t) ~(_VAL2FLD(SRSS_WDT_CTL_WDT_EN, 1U)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_GetMatch
+****************************************************************************//**
+*
+* Reads the WDT counter match comparison value.
+*
+* \return The counter match value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_WDT_GetMatch(void)
+{
+ return ((uint32_t) _FLD2VAL(SRSS_WDT_MATCH_MATCH, SRSS_WDT_MATCH));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_GetCount
+****************************************************************************//**
+*
+* Reads the current WDT counter value.
+*
+* \return A live counter value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_WDT_GetCount(void)
+{
+ return ((uint32_t) _FLD2VAL(SRSS_WDT_CNT_COUNTER, SRSS_WDT_CNT));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_GetIgnoreBits
+****************************************************************************//**
+*
+* Reads the number of the most significant bits of the Watchdog timer that are
+* not checked against the match.
+*
+* \return The number of the most significant bits.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_WDT_GetIgnoreBits(void)
+{
+ return((uint32_t) _FLD2VAL(SRSS_WDT_MATCH_IGNORE_BITS, SRSS_WDT_MATCH));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_MaskInterrupt
+****************************************************************************//**
+*
+* After masking interrupts from the WDT, they are not passed to the CPU.
+* This function does not disable the WDT-reset generation.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_WDT_MaskInterrupt(void)
+{
+ SRSS_SRSS_INTR_MASK &= (uint32_t)(~ _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_UnmaskInterrupt
+****************************************************************************//**
+*
+* After unmasking interrupts from the WDT, they are passed to CPU.
+* This function does not impact the reset generation.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_WDT_UnmaskInterrupt(void)
+{
+ SRSS_SRSS_INTR_MASK |= _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U);
+}
+/** \} group_wdt_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_WDT_H */
+
+/** \} group_wdt */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_device.c b/platform/ext/target/psoc64/Native_Driver/source/cy_device.c
new file mode 100644
index 0000000000..c89104a36d
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_device.c
@@ -0,0 +1,381 @@
+/***************************************************************************//**
+* \file cy_device.c
+* \version 2.10
+*
+* This file provides the definitions for core and peripheral block HW base
+* addresses, versions, and parameters.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_device.h"
+
+/*******************************************************************************
+* Global Variables
+*******************************************************************************/
+
+/* This is set in Cy_PDL_Init() to the device information relevant
+ * for the current target.
+ */
+const cy_stc_device_t * cy_device;
+
+/* Platform and peripheral block configuration */
+const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01 =
+{
+ /* Base HW addresses */
+ /* cpussBase */ 0x40210000UL,
+ /* flashcBase */ 0x40250000UL,
+ /* periBase */ 0x40010000UL,
+ /* udbBase */ 0x40340000UL,
+ /* protBase */ 0x40240000UL,
+ /* hsiomBase */ 0x40310000UL,
+ /* gpioBase */ 0x40320000UL,
+ /* passBase */ 0x411F0000UL,
+ /* ipcBase */ 0x40230000UL,
+ /* cryptoBase */ 0x40110000UL,
+
+ /* IP block versions [7:4] major, [3:0] minor */
+ /* cpussVersion */ 0x10U,
+ /* cryptoVersion */ 0x10U,
+ /* dwVersion */ 0x10U,
+ /* ipcVersion */ 0x10U,
+ /* periVersion */ 0x10U,
+ /* srssVersion */ 0x10U,
+
+ /* Parameters */
+ /* cpussIpcNr */ 16U,
+ /* cpussIpcIrqNr */ 16U,
+ /* cpussDw0ChNr */ 16U,
+ /* cpussDw1ChNr */ 16U,
+ /* cpussFlashPaSize */ 128U,
+ /* cpussIpc0Irq */ 25,
+ /* cpussFmIrq */ 85,
+ /* cpussNotConnectedIrq */ 240,
+ /* srssNumClkpath */ 5U,
+ /* srssNumPll */ 1U,
+ /* srssNumHfroot */ 5U,
+ /* periClockNr */ 59U,
+ /* smifDeviceNr */ 4U,
+ /* passSarChannels */ 16U,
+ /* epMonitorNr */ 28u,
+ /* udbPresent */ 1U,
+ /* sysPmSimoPresent */ 1U,
+ /* protBusMasterMask */ 0xC00FUL,
+ /* cryptoMemSize */ 1024u,
+ /* flashRwwRequired */ 1U,
+ /* flashPipeRequired */ 1U,
+ /* flashWriteDelay */ 1U,
+ /* flashProgramDelay */ 1U,
+ /* flashEraseDelay */ 1U,
+ /* flashCtlMainWs0Freq */ 29U,
+ /* flashCtlMainWs1Freq */ 58U,
+ /* flashCtlMainWs2Freq */ 87U,
+ /* flashCtlMainWs3Freq */ 120U,
+ /* flashCtlMainWs4Freq */ 150U,
+
+ /* Peripheral register offsets */
+
+ /* DW registers */
+ /* dwChOffset */ (uint16_t)offsetof(DW_V1_Type, CH_STRUCT),
+ /* dwChSize */ sizeof(DW_CH_STRUCT_V1_Type),
+ /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_CH_CTL_PRIO_Pos,
+ /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos,
+ /* dwStatusChIdxPos */ (uint8_t)DW_STATUS_CH_IDX_Pos,
+ /* dwStatusChIdxMsk */ DW_STATUS_CH_IDX_Msk,
+
+ /* PERI registers */
+ /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V1_Type, TR_CMD),
+ /* periTrCmdGrSelMsk */ (uint16_t)PERI_TR_CMD_GROUP_SEL_Msk,
+ /* periTrGrOffset */ (uint16_t)offsetof(PERI_V1_Type, TR_GR),
+ /* periTrGrSize */ sizeof(PERI_TR_GR_V1_Type),
+
+ /* periDivCmdDivSelMsk */ (uint8_t)PERI_DIV_CMD_DIV_SEL_Msk,
+ /* periDivCmdTypeSelPos */ (uint8_t)PERI_DIV_CMD_TYPE_SEL_Pos,
+ /* periDivCmdPaDivSelPos */ (uint8_t)PERI_DIV_CMD_PA_DIV_SEL_Pos,
+ /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_DIV_CMD_PA_TYPE_SEL_Pos,
+
+ /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_8_CTL),
+ /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_16_CTL),
+ /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_16_5_CTL),
+ /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_24_5_CTL),
+
+ /* GPIO registers */
+ /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, INTR_CFG),
+ /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG),
+ /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG_IN),
+ /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG_OUT),
+ /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG_SIO),
+
+ /* CPUSS registers */
+ /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V1_Type, CM0_CLOCK_CTL),
+ /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V1_Type, CM4_CLOCK_CTL),
+ /* cpussCm4StatusOffset */ offsetof(CPUSS_V1_Type, CM4_STATUS),
+ /* cpussCm0StatusOffset */ offsetof(CPUSS_V1_Type, CM0_STATUS),
+ /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V1_Type, CM4_PWR_CTL),
+ /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V1_Type, TRIM_RAM_CTL),
+ /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V1_Type, TRIM_ROM_CTL),
+ /* cpussSysTickCtlOffset */ offsetof(CPUSS_V1_Type, SYSTICK_CTL),
+
+ /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V1_Type, CM0_NMI_CTL),
+ /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V1_Type, CM4_NMI_CTL),
+ /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V1_Type, ROM_CTL),
+ /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V1_Type, RAM0_CTL0),
+ /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V1_Type, RAM1_CTL0),
+ /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V1_Type, RAM2_CTL0),
+
+ /* IPC registers */
+ /* ipcStructSize */ sizeof(IPC_STRUCT_V1_Type),
+ /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V1_Type, LOCK_STATUS),
+};
+
+const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02 =
+{
+ /* Base HW addresses */
+ /* cpussBase */ 0x40200000UL,
+ /* flashcBase */ 0x40240000UL,
+ /* periBase */ 0x40000000UL,
+ /* udbBase */ 0UL,
+ /* protBase */ 0x40230000UL,
+ /* hsiomBase */ 0x40300000UL,
+ /* gpioBase */ 0x40310000UL,
+ /* passBase */ 0x409F0000UL,
+ /* ipcBase */ 0x40220000UL,
+ /* cryptoBase */ 0x40100000UL,
+
+ /* IP block versions [7:4] major, [3:0] minor */
+ /* cpussVersion */ 0x20U,
+ /* cryptoVersion */ 0x20U,
+ /* dwVersion */ 0x20U,
+ /* ipcVersion */ 0x20U,
+ /* periVersion */ 0x20U,
+ /* srssVersion */ 0x10U,
+
+ /* Parameters */
+ /* cpussIpcNr */ 16U,
+ /* cpussIpcIrqNr */ 16U,
+ /* cpussDw0ChNr */ 29U,
+ /* cpussDw1ChNr */ 29U,
+ /* cpussFlashPaSize */ 128U,
+ /* cpussIpc0Irq */ 23,
+ /* cpussFmIrq */ 117,
+ /* cpussNotConnectedIrq */ 1023,
+ /* srssNumClkpath */ 6U,
+ /* srssNumPll */ 2U,
+ /* srssNumHfroot */ 6U,
+ /* periClockNr */ 54U,
+ /* smifDeviceNr */ 4U,
+ /* passSarChannels */ 16U,
+ /* epMonitorNr */ 32u,
+ /* udbPresent */ 0U,
+ /* sysPmSimoPresent */ 0U,
+ /* protBusMasterMask */ 0xC07FUL,
+ /* cryptoMemSize */ 1024u,
+ /* flashRwwRequired */ 0U,
+ /* flashPipeRequired */ 0U,
+ /* flashWriteDelay */ 0U,
+ /* flashProgramDelay */ 0U,
+ /* flashEraseDelay */ 0U,
+ /* flashCtlMainWs0Freq */ 25U,
+ /* flashCtlMainWs1Freq */ 50U,
+ /* flashCtlMainWs2Freq */ 75U,
+ /* flashCtlMainWs3Freq */ 100U,
+ /* flashCtlMainWs4Freq */ 125U,
+
+ /* Peripheral register offsets */
+
+ /* DW registers */
+ /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT),
+ /* dwChSize */ sizeof(DW_CH_STRUCT_V2_Type),
+ /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos,
+ /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos,
+ /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos,
+ /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk,
+
+ /* PERI registers */
+ /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD),
+ /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk,
+ /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR),
+ /* periTrGrSize */ sizeof(PERI_TR_GR_V2_Type),
+
+ /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk,
+ /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos,
+ /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos,
+ /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos,
+
+ /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL),
+ /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL),
+ /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL),
+ /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL),
+
+ /* GPIO registers */
+ /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG),
+ /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
+ /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN),
+ /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT),
+ /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO),
+
+ /* CPUSS registers */
+ /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL),
+ /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
+ /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS),
+ /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS),
+ /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL),
+ /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL),
+ /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL),
+ /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
+ /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL),
+ /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL),
+ /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL),
+ /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0),
+ /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
+ /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
+
+ /* IPC registers */
+ /* ipcStructSize */ sizeof(IPC_STRUCT_V2_Type),
+ /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS),
+};
+
+const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03 =
+{
+ /* Base HW addresses */
+ /* cpussBase */ 0x40200000UL,
+ /* flashcBase */ 0x40240000UL,
+ /* periBase */ 0x40000000UL,
+ /* udbBase */ 0UL,
+ /* protBase */ 0x40230000UL,
+ /* hsiomBase */ 0x40300000UL,
+ /* gpioBase */ 0x40310000UL,
+ /* passBase */ 0x409F0000UL,
+ /* ipcBase */ 0x40220000UL,
+ /* cryptoBase */ 0x40100000UL,
+
+ /* IP block versions [7:4] major, [3:0] minor */
+ /* cpussVersion */ 0x20U,
+ /* cryptoVersion */ 0x20U,
+ /* dwVersion */ 0x20U,
+ /* ipcVersion */ 0x20U,
+ /* periVersion */ 0x20U,
+ /* srssVersion */ 0x13U,
+
+ /* Parameters */
+ /* cpussIpcNr */ 16U,
+ /* cpussIpcIrqNr */ 16U,
+ /* cpussDw0ChNr */ 29U,
+ /* cpussDw1ChNr */ 32U,
+ /* cpussFlashPaSize */ 128U,
+ /* cpussIpc0Irq */ 23,
+ /* cpussFmIrq */ 117,
+ /* cpussNotConnectedIrq */ 1023,
+ /* srssNumClkpath */ 5U,
+ /* srssNumPll */ 1U,
+ /* srssNumHfroot */ 5U,
+ /* periClockNr */ 28U,
+ /* smifDeviceNr */ 3U,
+ /* passSarChannels */ 16U,
+ /* epMonitorNr */ 0u,
+ /* udbPresent */ 0U,
+ /* sysPmSimoPresent */ 1U,
+ /* protBusMasterMask */ 0xC03FUL,
+ /* cryptoMemSize */ 1024u,
+ /* flashRwwRequired */ 0U,
+ /* flashPipeRequired */ 0U,
+ /* flashWriteDelay */ 0U,
+ /* flashProgramDelay */ 0U,
+ /* flashEraseDelay */ 0U,
+ /* flashCtlMainWs0Freq */ 25U,
+ /* flashCtlMainWs1Freq */ 50U,
+ /* flashCtlMainWs2Freq */ 75U,
+ /* flashCtlMainWs3Freq */ 100U,
+ /* flashCtlMainWs4Freq */ 125U,
+
+ /* Peripheral register offsets */
+
+ /* DW registers */
+ /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT),
+ /* dwChSize */ sizeof(DW_CH_STRUCT_V2_Type),
+ /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos,
+ /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos,
+ /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos,
+ /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk,
+
+ /* PERI registers */
+ /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD),
+ /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk,
+ /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR),
+ /* periTrGrSize */ sizeof(PERI_TR_GR_V2_Type),
+
+ /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk,
+ /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos,
+ /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos,
+ /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos,
+
+ /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL),
+ /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL),
+ /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL),
+ /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL),
+
+ /* GPIO registers */
+ /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG),
+ /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
+ /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN),
+ /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT),
+ /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO),
+
+ /* CPUSS registers */
+ /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL),
+ /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
+ /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS),
+ /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS),
+ /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL),
+ /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL),
+ /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL),
+ /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
+ /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL),
+ /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL),
+ /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL),
+ /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0),
+ /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
+ /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
+
+ /* IPC registers */
+ /* ipcStructSize */ sizeof(IPC_STRUCT_V2_Type),
+ /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS),
+};
+
+
+/******************************************************************************
+* Function Name: Cy_PDL_Init
+****************************************************************************//**
+*
+* \brief Initializes the platform and peripheral block configuration for the
+* given target device.
+*
+* \param device
+* Pointer to the platform and peripheral block configuration
+*
+* \note
+* This function must be called prior calling any function in PDL.
+*
+*******************************************************************************/
+void Cy_PDL_Init(const cy_stc_device_t * device)
+{
+ cy_device = device;
+}
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_flash.c b/platform/ext/target/psoc64/Native_Driver/source/cy_flash.c
new file mode 100644
index 0000000000..e1a44a3ab1
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_flash.c
@@ -0,0 +1,1569 @@
+/***************************************************************************//**
+* \file cy_flash.c
+* \version 3.30.2
+*
+* \brief
+* Provides the public functions for the API for the PSoC 6 Flash Driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#include "cy_flash.h"
+#include "cy_sysclk.h"
+#include "cy_sysint.h"
+#include "cy_ipc_drv.h"
+#include "cy_ipc_sema.h"
+#include "cy_ipc_pipe.h"
+#include "cy_device.h"
+#include "cy_syslib.h"
+#ifdef TFM_MULTI_CORE_TOPOLOGY
+ #include "region_defs.h"
+#endif
+
+/***************************************
+* Data Structure definitions
+***************************************/
+
+/* Flash driver context */
+typedef struct
+{
+ uint32_t opcode; /**< Specifies the code of flash operation */
+ uint32_t arg1; /**< Specifies the configuration of flash operation */
+ uint32_t arg2; /**< Specifies the configuration of flash operation */
+ uint32_t arg3; /**< Specifies the configuration of flash operation */
+} cy_stc_flash_context_t;
+
+
+/***************************************
+* Macro definitions
+***************************************/
+
+/** \cond INTERNAL */
+/** Set SROM API in blocking mode */
+#define CY_FLASH_BLOCKING_MODE ((0x01UL) << 8UL)
+/** Set SROM API in non blocking mode */
+#define CY_FLASH_NON_BLOCKING_MODE (0UL)
+
+/** SROM API flash region ID shift for flash row information */
+#define CY_FLASH_REGION_ID_SHIFT (16U)
+#define CY_FLASH_REGION_ID_MASK (3U)
+#define CY_FLASH_ROW_ID_MASK (0xFFFFU)
+/** SROM API flash region IDs */
+#define CY_FLASH_REGION_ID_MAIN (0UL)
+#define CY_FLASH_REGION_ID_EM_EEPROM (1UL)
+#define CY_FLASH_REGION_ID_SFLASH (2UL)
+
+/** SROM API opcode mask */
+#define CY_FLASH_OPCODE_Msk ((0xFFUL) << 24UL)
+/** SROM API opcode for flash write operation */
+#define CY_FLASH_OPCODE_WRITE_ROW ((0x05UL) << 24UL)
+/** SROM API opcode for flash program operation */
+#define CY_FLASH_OPCODE_PROGRAM_ROW ((0x06UL) << 24UL)
+/** SROM API opcode for row erase operation */
+#define CY_FLASH_OPCODE_ERASE_ROW ((0x1CUL) << 24UL)
+/** SROM API opcode for sub sector erase operation */
+#define CY_FLASH_OPCODE_ERASE_SUB_SECTOR ((0x1DUL) << 24UL)
+/** SROM API opcode for sector erase operation */
+#define CY_FLASH_OPCODE_ERASE_SECTOR ((0x14UL) << 24UL)
+/** SROM API opcode for flash checksum operation */
+#define CY_FLASH_OPCODE_CHECKSUM ((0x0BUL) << 24UL)
+/** SROM API opcode for flash hash operation */
+#define CY_FLASH_OPCODE_HASH ((0x0DUL) << 24UL)
+/** SROM API flash row shift for flash checksum operation */
+#define CY_FLASH_OPCODE_CHECKSUM_ROW_SHIFT (8UL)
+/** SROM API flash row shift for flash checksum operation */
+#define CY_FLASH_OPCODE_CHECKSUM_REGION_SHIFT (22UL)
+/** Data to be programmed to flash is located in SRAM memory region */
+#define CY_FLASH_DATA_LOC_SRAM (0x100UL)
+/** SROM API flash verification option for flash write operation */
+#define CY_FLASH_CONFIG_VERIFICATION_EN ((0x01UL) << 16u)
+
+/** Command completed with no errors */
+#define CY_FLASH_ROMCODE_SUCCESS (0xA0000000UL)
+/** Invalid device protection state */
+#define CY_FLASH_ROMCODE_INVALID_PROTECTION (0xF0000001UL)
+/** Invalid flash page latch address */
+#define CY_FLASH_ROMCODE_INVALID_FM_PL (0xF0000003UL)
+/** Invalid flash address */
+#define CY_FLASH_ROMCODE_INVALID_FLASH_ADDR (0xF0000004UL)
+/** Row is write protected */
+#define CY_FLASH_ROMCODE_ROW_PROTECTED (0xF0000005UL)
+/** Comparison between Page Latches and FM row failed */
+#define CY_FLASH_ROMCODE_PL_ROW_COMP_FA (0xF0000022UL)
+/** Command in progress; no error */
+#define CY_FLASH_ROMCODE_IN_PROGRESS_NO_ERROR (0xA0000009UL)
+/** Flash operation is successfully initiated */
+#define CY_FLASH_IS_OPERATION_STARTED (0x00000010UL)
+/** Flash is under operation */
+#define CY_FLASH_IS_BUSY (0x00000040UL)
+/** IPC structure is already locked by another process */
+#define CY_FLASH_IS_IPC_BUSY (0x00000080UL)
+/** Input parameters passed to Flash API are not valid */
+#define CY_FLASH_IS_INVALID_INPUT_PARAMETERS (0x00000100UL)
+
+/** Result mask */
+#define CY_FLASH_RESULT_MASK (0x0FFFFFFFUL)
+/** Error shift */
+#define CY_FLASH_ERROR_SHIFT (28UL)
+/** No error */
+#define CY_FLASH_ERROR_NO_ERROR (0xAUL)
+
+/** CM4 Flash Proxy address */
+#define CY_FLASH_CM4_FLASH_PROXY_ADDR (*(Cy_Flash_Proxy *)(0x00000D1CUL))
+typedef cy_en_flashdrv_status_t (*Cy_Flash_Proxy)(cy_stc_flash_context_t *context);
+
+/** IPC notify bit for IPC0 structure (dedicated to flash operation) */
+#define CY_FLASH_IPC_NOTIFY_STRUCT0 (0x1UL << CY_IPC_INTR_SYSCALL1)
+
+/** Disable delay */
+#define CY_FLASH_NO_DELAY (0U)
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ /** Number of ticks to wait 1 uS */
+ #define CY_FLASH_TICKS_FOR_1US (8U)
+ /** Define to set the IMO to perform a delay after the flash operation started */
+ #define CY_FLASH_TST_DDFT_SLOW_CTL_MASK (0x00001F1EUL)
+ /** Fast control register */
+ #define CY_FLASH_TST_DDFT_FAST_CTL_MASK (62U)
+ /** Slow output register - output disabled */
+ #define CY_FLASH_CLK_OUTPUT_DISABLED (0U)
+
+ /* The default delay time value */
+ #define CY_FLASH_DEFAULT_DELAY (150UL)
+ /* Calculates the time in microseconds to wait for the number of the CM0P ticks */
+ #define CY_FLASH_DELAY_CORRECTIVE(ticks) ((((uint32)Cy_SysClk_ClkPeriGetDivider() + 1UL) * \
+ (Cy_SysClk_ClkSlowGetDivider() + 1UL) * (ticks) * 1000UL)\
+ / ((uint32_t)cy_Hfclk0FreqHz / 1000UL))
+
+ /* Number of the CM0P ticks for StartProgram function delay corrective time */
+ #define CY_FLASH_START_PROGRAM_DELAY_TICKS (6000UL)
+ /* Delay time for StartProgram function in us */
+ #define CY_FLASH_START_PROGRAM_DELAY_TIME (900UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_PROGRAM_DELAY_TICKS))
+ /* Number of the CM0P ticks for StartErase functions delay corrective time */
+ #define CY_FLASH_START_ERASE_DELAY_TICKS (9500UL)
+ /* Delay time for StartErase functions in us */
+ #define CY_FLASH_START_ERASE_DELAY_TIME (2200UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_ERASE_DELAY_TICKS))
+ /* Number of the CM0P ticks for StartWrite function delay corrective time */
+ #define CY_FLASH_START_WRITE_DELAY_TICKS (19000UL)
+ /* Delay time for StartWrite function in us */
+ #define CY_FLASH_START_WRITE_DELAY_TIME (9800UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_WRITE_DELAY_TICKS))
+
+ /** Delay time for Start Write function in us with corrective time */
+ #define CY_FLASH_START_WRITE_DELAY (CY_FLASH_START_WRITE_DELAY_TIME)
+ /** Delay time for Start Program function in us with corrective time */
+ #define CY_FLASH_START_PROGRAM_DELAY (CY_FLASH_START_PROGRAM_DELAY_TIME)
+ /** Delay time for Start Erase function in uS with corrective time */
+ #define CY_FLASH_START_ERASE_DELAY (CY_FLASH_START_ERASE_DELAY_TIME)
+
+ #define CY_FLASH_ENTER_WAIT_LOOP (0xFFU)
+ #define CY_FLASH_IPC_CLIENT_ID (2U)
+
+ /** Semaphore number reserved for flash driver */
+ #define CY_FLASH_WAIT_SEMA (0UL)
+ /* Semaphore check timeout (in tries) */
+ #define CY_FLASH_SEMA_WAIT_MAX_TRIES (150000UL)
+
+ static void Cy_Flash_RAMDelay(uint32_t microseconds);
+
+ #if (CY_CPU_CORTEX_M0P)
+ #define IS_CY_PIPE_FREE(...) (!Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_CYPIPE_EP1)))
+ #define NOTIFY_PEER_CORE(a) Cy_IPC_Pipe_SendMessage(CY_IPC_EP_CYPIPE_CM4_ADDR, CY_IPC_EP_CYPIPE_CM0_ADDR, (a), NULL)
+ #else
+ #define IS_CY_PIPE_FREE(...) (!Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_CYPIPE_EP0)))
+ #define NOTIFY_PEER_CORE(a) Cy_IPC_Pipe_SendMessage(CY_IPC_EP_CYPIPE_CM0_ADDR, CY_IPC_EP_CYPIPE_CM4_ADDR, (a), NULL)
+ #endif
+
+ static void Cy_Flash_NotifyHandler(uint32_t * msgPtr);
+
+ static cy_stc_flash_notify_t * ipcWaitMessage;
+
+#else
+ /** Delay time for Start Write function in us with corrective time */
+ #define CY_FLASH_START_WRITE_DELAY (CY_FLASH_NO_DELAY)
+ /** Delay time for Start Program function in us with corrective time */
+ #define CY_FLASH_START_PROGRAM_DELAY (CY_FLASH_NO_DELAY)
+ /** Delay time for Start Erase function in uS with corrective time */
+ #define CY_FLASH_START_ERASE_DELAY (CY_FLASH_NO_DELAY)
+
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+/** \endcond */
+
+/* Static functions */
+static bool Cy_Flash_BoundsCheck(uint32_t flashAddr);
+static uint32_t Cy_Flash_GetRowNum(uint32_t flashAddr);
+static cy_en_flashdrv_status_t Cy_Flash_ProcessOpcode(uint32_t opcode);
+static cy_en_flashdrv_status_t Cy_Flash_OperationStatus(void);
+static cy_en_flashdrv_status_t Cy_Flash_SendCmd(uint32_t mode, uint32_t microseconds);
+
+static volatile cy_stc_flash_context_t flashContext;
+
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ /*******************************************************************************
+ * Function Name: Cy_Flash_InitExt
+ ****************************************************************************//**
+ *
+ * Initiates all needed prerequisites to support flash erase/write.
+ * Should be called from each core. Defines the address of the message structure.
+ *
+ * Requires a call to Cy_IPC_Sema_Init(), Cy_IPC_Pipe_Config() and
+ * Cy_IPC_Pipe_Init() functions before use.
+ *
+ * This function is called in the Cy_Flash_Init() function - see the
+ * \ref Cy_Flash_Init usage considerations.
+ *
+ *******************************************************************************/
+ void Cy_Flash_InitExt(cy_stc_flash_notify_t *ipcWaitMessageAddr)
+ {
+ ipcWaitMessage = ipcWaitMessageAddr;
+
+ if(ipcWaitMessage != NULL)
+ {
+ ipcWaitMessage->clientID = CY_FLASH_IPC_CLIENT_ID;
+ ipcWaitMessage->pktType = CY_FLASH_ENTER_WAIT_LOOP;
+ ipcWaitMessage->intrRelMask = 0U;
+ }
+
+ if (cy_device->flashRwwRequired != 0U)
+ {
+ #if (CY_CPU_CORTEX_M4)
+ cy_stc_sysint_t flashIntConfig =
+ {
+ (IRQn_Type)cy_device->cpussFmIrq, /* .intrSrc */
+ 0U /* .intrPriority */
+ };
+
+ (void)Cy_SysInt_Init(&flashIntConfig, &Cy_Flash_ResumeIrqHandler);
+ NVIC_EnableIRQ(flashIntConfig.intrSrc);
+ #endif
+
+ if (cy_device->flashPipeRequired != 0U)
+ {
+ (void)Cy_IPC_Pipe_RegisterCallback(CY_IPC_EP_CYPIPE_ADDR, &Cy_Flash_NotifyHandler,
+ (uint32_t)CY_FLASH_IPC_CLIENT_ID);
+ }
+ }
+ }
+
+
+ /*******************************************************************************
+ * Function Name: Cy_Flash_NotifyHandler
+ ****************************************************************************//**
+ *
+ * This is the interrupt service routine for the pipe notifications.
+ *
+ *******************************************************************************/
+ CY_RAMFUNC_BEGIN
+ #if !defined (__ICCARM__)
+ CY_NOINLINE
+ #endif
+ static void Cy_Flash_NotifyHandler(uint32_t * msgPtr)
+ {
+ uint32_t intr;
+ static uint32_t semaIndex;
+ static uint32_t semaMask;
+ static volatile uint32_t *semaPtr;
+ static cy_stc_ipc_sema_t *semaStruct;
+
+ cy_stc_flash_notify_t *ipcMsgPtr = (cy_stc_flash_notify_t *)msgPtr;
+
+ if (CY_FLASH_ENTER_WAIT_LOOP == ipcMsgPtr->pktType)
+ {
+ intr = Cy_SysLib_EnterCriticalSection();
+
+ /* Get pointer to structure */
+ semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SEMA));
+
+ /* Get the index into the semaphore array and calculate the mask */
+ semaIndex = CY_FLASH_WAIT_SEMA / CY_IPC_SEMA_PER_WORD;
+ semaMask = (uint32_t)(1ul << (CY_FLASH_WAIT_SEMA - (semaIndex * CY_IPC_SEMA_PER_WORD) ));
+ semaPtr = &semaStruct->arrayPtr[semaIndex];
+
+ /* Notification to the Flash driver to start the current operation */
+ *semaPtr |= semaMask;
+
+ /* Check a notification from other core to end of waiting */
+ while (((*semaPtr) & semaMask) != 0ul)
+ {
+ }
+
+ Cy_SysLib_ExitCriticalSection(intr);
+ }
+ }
+ CY_RAMFUNC_END
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_Init
+****************************************************************************//**
+*
+* Initiates all needed prerequisites to support flash erase/write.
+* Should be called from each core.
+*
+* Requires a call to Cy_IPC_Sema_Init(), Cy_IPC_Pipe_Config() and
+* Cy_IPC_Pipe_Init() functions before use.
+*
+* This function is called in the SystemInit() function, for proper flash write
+* and erase operations. If the default startup file is not used, or the function
+* SystemInit() is not called in your project, ensure to perform the following steps
+* before any flash or EmEEPROM write/erase operations:
+* \snippet flash/snippet/main.c Flash Initialization
+*
+*******************************************************************************/
+void Cy_Flash_Init(void)
+{
+ #if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ #if defined TFM_MULTI_CORE_TOPOLOGY && CY_CPU_CORTEX_M0P
+ cy_stc_flash_notify_t *ipcWaitMessageStc =
+ (cy_stc_flash_notify_t *)IPC_WAIT_MESSAGE_STC_ADDR;
+
+ Cy_Flash_InitExt(ipcWaitMessageStc);
+ #else
+ CY_ALIGN(4) static cy_stc_flash_notify_t ipcWaitMessageStc;
+
+ Cy_Flash_InitExt(&ipcWaitMessageStc);
+ #endif
+ #endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_SendCmd
+****************************************************************************//**
+*
+* Sends a command to the SROM via the IPC channel. The function is placed to the
+* SRAM memory to guarantee successful operation. After an IPC message is sent,
+* the function waits for a defined time before exiting the function.
+*
+* \param mode
+* Sets the blocking or non-blocking Flash operation.
+*
+* \param microseconds
+* The number of microseconds to wait before exiting the functions
+* in range 0-65535 us.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+CY_RAMFUNC_BEGIN
+#if !defined (__ICCARM__)
+ CY_NOINLINE
+#endif
+static cy_en_flashdrv_status_t Cy_Flash_SendCmd(uint32_t mode, uint32_t microseconds)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_IPC_BUSY;
+ IPC_STRUCT_Type * locIpcBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL);
+ volatile uint32_t *ipcLockStatus = &REG_IPC_STRUCT_LOCK_STATUS(locIpcBase);
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ uint32_t intr;
+ uint32_t semaTryCount = 0uL;
+
+ if (cy_device->flashRwwRequired != 0U)
+ {
+ /* Check for active core is CM0+, or CM4 on single core device */
+ #if (CY_CPU_CORTEX_M0P)
+ bool isPeerCoreEnabled = (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status());
+ #else
+ bool isPeerCoreEnabled = false;
+
+ if (SFLASH_SINGLE_CORE == 0U)
+ {
+ isPeerCoreEnabled = true;
+ }
+ #endif
+
+ if (!isPeerCoreEnabled)
+ {
+ result = CY_FLASH_DRV_SUCCESS;
+ }
+ else
+ {
+ if (IS_CY_PIPE_FREE())
+ {
+ if (CY_IPC_SEMA_STATUS_LOCKED != Cy_IPC_Sema_Status(CY_FLASH_WAIT_SEMA))
+ {
+ if (CY_IPC_PIPE_SUCCESS == NOTIFY_PEER_CORE(ipcWaitMessage))
+ {
+ /* Wait for SEMA lock by peer core */
+ while ((CY_IPC_SEMA_STATUS_LOCKED != Cy_IPC_Sema_Status(CY_FLASH_WAIT_SEMA)) && ((semaTryCount < CY_FLASH_SEMA_WAIT_MAX_TRIES)))
+ {
+ /* check for timeout (as maximum tries count) */
+ ++semaTryCount;
+ }
+
+ if (semaTryCount < CY_FLASH_SEMA_WAIT_MAX_TRIES)
+ {
+ result = CY_FLASH_DRV_SUCCESS;
+ }
+ }
+ }
+ }
+ }
+
+ if (CY_FLASH_DRV_SUCCESS == result)
+ {
+ /* Notifier is ready, start of the operation */
+ intr = Cy_SysLib_EnterCriticalSection();
+
+ if (0UL != _FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS_CLK_CAL_CNT1))
+ {
+ /* Tries to acquire the IPC structure and pass the arguments to SROM API */
+ if (Cy_IPC_Drv_SendMsgPtr(locIpcBase, CY_FLASH_IPC_NOTIFY_STRUCT0, (void*)&flashContext) == CY_IPC_DRV_SUCCESS)
+ {
+ Cy_Flash_RAMDelay(microseconds);
+
+ if (mode == CY_FLASH_NON_BLOCKING_MODE)
+ {
+ /* The Flash operation is successfully initiated */
+ result = CY_FLASH_DRV_OPERATION_STARTED;
+ }
+ else
+ {
+ while (0U != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, *ipcLockStatus))
+ {
+ /* Polls whether the IPC is released and the Flash operation is performed */
+ }
+ result = Cy_Flash_OperationStatus();
+ }
+ }
+ else
+ {
+ /* The IPC structure is already locked by another process */
+ result = CY_FLASH_DRV_IPC_BUSY;
+ }
+ }
+ else
+ {
+ /* SysClk measurement counter is busy */
+ result = CY_FLASH_DRV_IPC_BUSY;
+ }
+
+ if (isPeerCoreEnabled)
+ {
+ while (CY_IPC_SEMA_SUCCESS != Cy_IPC_Sema_Clear(CY_FLASH_WAIT_SEMA, true))
+ {
+ /* Clear SEMA lock */
+ }
+ }
+
+ Cy_SysLib_ExitCriticalSection(intr);
+ /* End of the flash operation */
+ }
+ }
+ else
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+ {
+ #if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ intr = Cy_SysLib_EnterCriticalSection();
+ #endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+ /* Tries to acquire the IPC structure and pass the arguments to SROM API */
+ if (Cy_IPC_Drv_SendMsgPtr(locIpcBase, CY_FLASH_IPC_NOTIFY_STRUCT0, (void*)&flashContext) == CY_IPC_DRV_SUCCESS)
+ {
+ if (mode == CY_FLASH_NON_BLOCKING_MODE)
+ {
+ /* The Flash operation is successfully initiated */
+ result = CY_FLASH_DRV_OPERATION_STARTED;
+ }
+ else
+ {
+ while (0U != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, *ipcLockStatus))
+ {
+ /* Polls whether the IPC is released and the Flash operation is performed */
+ }
+
+ result = Cy_Flash_OperationStatus();
+ }
+ }
+ else
+ {
+ /* The IPC structure is already locked by another process */
+ result = CY_FLASH_DRV_IPC_BUSY;
+ }
+ #if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ Cy_SysLib_ExitCriticalSection(intr);
+ #endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+ }
+
+ return (result);
+}
+CY_RAMFUNC_END
+
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ /*******************************************************************************
+ * Function Name: Cy_Flash_RAMDelay
+ ****************************************************************************//**
+ *
+ * Wait for a defined time in the SRAM memory region.
+ *
+ * \param microseconds
+ * Delay time in microseconds in range 0-65535 us.
+ *
+ *******************************************************************************/
+ CY_RAMFUNC_BEGIN
+ #if !defined (__ICCARM__)
+ CY_NOINLINE
+ #endif
+ static void Cy_Flash_RAMDelay(uint32_t microseconds)
+ {
+ uint32_t ticks = (microseconds & 0xFFFFUL) * CY_FLASH_TICKS_FOR_1US;
+ if (ticks != CY_FLASH_NO_DELAY)
+ {
+ /* Acquire the IPC to prevent changing of the shared resources at the same time */
+ while(0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT))))
+ {
+ /* Wait until the IPC structure is released by another process */
+ }
+
+ SRSS_TST_DDFT_FAST_CTL_REG = SRSS_TST_DDFT_FAST_CTL_MASK;
+ SRSS_TST_DDFT_SLOW_CTL_REG = SRSS_TST_DDFT_SLOW_CTL_MASK;
+
+ SRSS_CLK_OUTPUT_SLOW = _VAL2FLD(SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0, CY_SYSCLK_MEAS_CLK_IMO) |
+ _VAL2FLD(SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1, CY_FLASH_CLK_OUTPUT_DISABLED);
+
+ /* Load the down-counter without status bit value */
+ SRSS_CLK_CAL_CNT1 = _VAL2FLD(SRSS_CLK_CAL_CNT1_CAL_COUNTER1, ticks);
+
+ /* Make sure that the counter is started */
+ ticks = _FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS_CLK_CAL_CNT1);
+
+ /* Release the IPC */
+ REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0U;
+
+ while (0UL == _FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS_CLK_CAL_CNT1))
+ {
+ /* Wait until the counter stops counting */
+ }
+ }
+ }
+ CY_RAMFUNC_END
+
+ #if (CY_CPU_CORTEX_M4)
+
+ /* Based on bookmark codes of mxs40srompsoc BROS,002-03298 */
+ #define CY_FLASH_PROGRAM_ROW_BOOKMARK (0x00000001UL)
+ #define CY_FLASH_ERASE_ROW_BOOKMARK (0x00000002UL)
+ #define CY_FLASH_WRITE_ROW_ERASE_BOOKMARK (0x00000003UL)
+ #define CY_FLASH_WRITE_ROW_PROGRAM_BOOKMARK (0x00000004UL)
+
+ /* Number of the CM0P ticks for function delay corrective time at final stage */
+ #define CY_FLASH_FINAL_STAGE_DELAY_TICKS (1000UL)
+ #define CY_FLASH_FINAL_STAGE_DELAY (130UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_FINAL_STAGE_DELAY_TICKS))
+
+
+ /*******************************************************************************
+ * Function Name: Cy_Flash_ResumeIrqHandler
+ ****************************************************************************//**
+ *
+ * This is the interrupt service routine to make additional processing of the
+ * flash operations resume phase.
+ *
+ *******************************************************************************/
+ CY_RAMFUNC_BEGIN
+ #if !defined (__ICCARM__)
+ CY_NOINLINE
+ #endif
+ void Cy_Flash_ResumeIrqHandler(void)
+ {
+ IPC_STRUCT_Type * locIpcBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_CYPIPE_EP0);
+
+ uint32_t bookmark;
+ bookmark = FLASHC_FM_CTL_BOOKMARK & 0xffffUL;
+
+ uint32_t intr = Cy_SysLib_EnterCriticalSection();
+
+ uint32_t cm0s = CPUSS_CM0_STATUS;
+
+ if ((bookmark == CY_FLASH_PROGRAM_ROW_BOOKMARK) || (bookmark == CY_FLASH_ERASE_ROW_BOOKMARK) ||
+ (bookmark == CY_FLASH_WRITE_ROW_ERASE_BOOKMARK) || (bookmark == CY_FLASH_WRITE_ROW_PROGRAM_BOOKMARK))
+ {
+ if ((cm0s == (CPUSS_CM0_STATUS_SLEEPING_Msk | CPUSS_CM0_STATUS_SLEEPDEEP_Msk)) && (0U == SFLASH_SINGLE_CORE))
+ {
+ REG_IPC_STRUCT_NOTIFY(locIpcBase) = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, (1UL << CY_IPC_INTR_CYPIPE_EP0));
+ while (CPUSS_CM0_STATUS == (CPUSS_CM0_STATUS_SLEEPING_Msk | CPUSS_CM0_STATUS_SLEEPDEEP_Msk))
+ {
+ /* Wait until the core is active */
+ }
+ }
+ Cy_Flash_RAMDelay(CY_FLASH_FINAL_STAGE_DELAY);
+ }
+
+ Cy_SysLib_ExitCriticalSection(intr);
+ }
+ CY_RAMFUNC_END
+ #endif /* (CY_CPU_CORTEX_M4) */
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_EraseRow
+****************************************************************************//**
+*
+* This function erases a single row of flash. Reports success or
+* a reason for failure. Does not return until the Write operation is
+* complete. Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in
+* the case when another process is writing to flash or erasing the row.
+* User firmware should not enter the Hibernate or Deep Sleep mode until flash Erase
+* is complete. The Flash operation is allowed in Sleep mode.
+* During the Flash operation, the device should not be reset, including the
+* XRES pin, a software reset, and watchdog reset sources. Also, low-voltage
+* detect circuits should be configured to generate an interrupt instead of a
+* reset. Otherwise, portions of flash may undergo unexpected changes.
+*
+* \param rowAddr Address of the flash row number.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash write operation is
+* performing. Refer to the device datasheet for the details.
+* Address must match row start address.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ /* Prepares arguments to be passed to SROM API */
+ if (Cy_Flash_BoundsCheck(rowAddr) != false)
+ {
+ SystemCoreClockUpdate();
+
+ flashContext.opcode = CY_FLASH_OPCODE_ERASE_ROW | CY_FLASH_BLOCKING_MODE;
+ flashContext.arg1 = rowAddr;
+ flashContext.arg2 = 0UL;
+ flashContext.arg3 = 0UL;
+
+ if (cy_device->flashEraseDelay != 0U)
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_START_ERASE_DELAY);
+ }
+ else
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_NO_DELAY);
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_StartEraseRow
+****************************************************************************//**
+*
+* Starts erasing a single row of flash. Returns immediately
+* and reports a successful start or reason for failure.
+* Reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case when IPC structure is locked
+* by another process. User firmware should not enter the Hibernate or Deep Sleep mode until
+* flash Erase is complete. The Flash operation is allowed in Sleep mode.
+* During the flash operation, the device should not be reset, including the
+* XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage
+* detect circuits should be configured to generate an interrupt instead of a reset.
+* Otherwise, portions of flash may undergo unexpected changes.
+* \note Before reading data from previously programmed/erased flash rows, the
+* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer()
+* function.
+*
+* \param rowAddr Address of the flash row number.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash erase operation is
+* performing. Refer to the device datasheet for the details.
+* Address must match row start address.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_StartEraseRow(uint32_t rowAddr)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ if (Cy_Flash_BoundsCheck(rowAddr) != false)
+ {
+ SystemCoreClockUpdate();
+
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_ERASE_ROW;
+ if (SFLASH_SINGLE_CORE != 0U)
+ {
+ flashContext.opcode |= CY_FLASH_BLOCKING_MODE;
+ }
+
+ flashContext.arg1 = rowAddr;
+ flashContext.arg2 = 0UL;
+ flashContext.arg3 = 0UL;
+
+ if (cy_device->flashEraseDelay != 0U)
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_START_ERASE_DELAY);
+ }
+ else
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_NO_DELAY);
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_EraseSector
+****************************************************************************//**
+*
+* This function erases a 256KB sector of flash. Reports success or
+* a reason for failure. Does not return until the Erase operation is
+* complete. Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in
+* the case when another process is writing to flash or erasing the row.
+* User firmware should not enter the Hibernate or Deep Sleep mode until flash Erase
+* is complete. The Flash operation is allowed in Sleep mode.
+* During the Flash operation, the device should not be reset, including the
+* XRES pin, a software reset, and watchdog reset sources. Also, low-voltage
+* detect circuits should be configured to generate an interrupt instead of a
+* reset. Otherwise, portions of flash may undergo unexpected changes.
+*
+* \param sectorAddr Address of the flash row number.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash write operation is
+* performing. Refer to the device datasheet for the details.
+* Address must match row start address.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_EraseSector(uint32_t sectorAddr)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ /* Prepares arguments to be passed to SROM API */
+ if (Cy_Flash_BoundsCheck(sectorAddr) != false)
+ {
+ SystemCoreClockUpdate();
+
+ flashContext.opcode = CY_FLASH_OPCODE_ERASE_SECTOR | CY_FLASH_BLOCKING_MODE;
+ flashContext.arg1 = sectorAddr;
+ flashContext.arg2 = 0UL;
+ flashContext.arg3 = 0UL;
+
+ if (cy_device->flashEraseDelay != 0U)
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_START_ERASE_DELAY);
+ }
+ else
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_NO_DELAY);
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_StartEraseSector
+****************************************************************************//**
+*
+* Starts erasing a 256KB sector of flash. Returns immediately
+* and reports a successful start or reason for failure.
+* Reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case when IPC structure is locked
+* by another process. User firmware should not enter the Hibernate or Deep Sleep mode until
+* flash Erase is complete. The Flash operation is allowed in Sleep mode.
+* During the flash operation, the device should not be reset, including the
+* XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage
+* detect circuits should be configured to generate an interrupt instead of a reset.
+* Otherwise, portions of flash may undergo unexpected changes.
+* \note Before reading data from previously programmed/erased flash rows, the
+* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer()
+* function.
+*
+* \param sectorAddr Address of the flash row number.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash erase operation is
+* performing. Refer to the device datasheet for the details.
+* Address must match row start address.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_StartEraseSector(uint32_t sectorAddr)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ if (Cy_Flash_BoundsCheck(sectorAddr) != false)
+ {
+ SystemCoreClockUpdate();
+
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_ERASE_SECTOR;
+ if (SFLASH_SINGLE_CORE != 0U)
+ {
+ flashContext.opcode |= CY_FLASH_BLOCKING_MODE;
+ }
+
+ flashContext.arg1 = sectorAddr;
+ flashContext.arg2 = 0UL;
+ flashContext.arg3 = 0UL;
+
+ if (cy_device->flashEraseDelay != 0U)
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_START_ERASE_DELAY);
+ }
+ else
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_NO_DELAY);
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_EraseSubsector
+****************************************************************************//**
+*
+* This function erases an 8-row subsector of flash. Reports success or
+* a reason for failure. Does not return until the Write operation is
+* complete. Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in
+* the case when another process is writing to flash or erasing the row.
+* User firmware should not enter the Hibernate or Deep-Sleep mode until flash Erase
+* is complete. The Flash operation is allowed in Sleep mode.
+* During the Flash operation, the device should not be reset, including the
+* XRES pin, a software reset, and watchdog reset sources. Also, low-voltage
+* detect circuits should be configured to generate an interrupt instead of a
+* reset. Otherwise, portions of flash may undergo unexpected changes.
+*
+* \param subSectorAddr Address of the flash row number.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash write operation is
+* performing. Refer to the device datasheet for the details.
+* Address must match row start address.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_EraseSubsector(uint32_t subSectorAddr)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ /* Prepares arguments to be passed to SROM API */
+ if (Cy_Flash_BoundsCheck(subSectorAddr) != false)
+ {
+ SystemCoreClockUpdate();
+
+ flashContext.opcode = CY_FLASH_OPCODE_ERASE_SUB_SECTOR | CY_FLASH_BLOCKING_MODE;
+ flashContext.arg1 = subSectorAddr;
+ flashContext.arg2 = 0UL;
+ flashContext.arg3 = 0UL;
+
+ if (cy_device->flashEraseDelay != 0U)
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_START_ERASE_DELAY);
+ }
+ else
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_NO_DELAY);
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_StartEraseSubsector
+****************************************************************************//**
+*
+* Starts erasing an 8-row subsector of flash. Returns immediately
+* and reports a successful start or reason for failure.
+* Reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case when IPC structure is locked
+* by another process. User firmware should not enter the Hibernate or Deep-Sleep mode until
+* flash Erase is complete. The Flash operation is allowed in Sleep mode.
+* During the flash operation, the device should not be reset, including the
+* XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage
+* detect circuits should be configured to generate an interrupt instead of a reset.
+* Otherwise, portions of flash may undergo unexpected changes.
+* \note Before reading data from previously programmed/erased flash rows, the
+* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer()
+* function.
+*
+* \param subSectorAddr Address of the flash row number.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash erase operation is
+* performing. Refer to the device datasheet for the details.
+* Address must match row start address.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_StartEraseSubsector(uint32_t subSectorAddr)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ if (Cy_Flash_BoundsCheck(subSectorAddr) != false)
+ {
+ SystemCoreClockUpdate();
+
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_ERASE_SUB_SECTOR;
+ if (SFLASH_SINGLE_CORE != 0U)
+ {
+ flashContext.opcode |= CY_FLASH_BLOCKING_MODE;
+ }
+
+ flashContext.arg1 = subSectorAddr;
+ flashContext.arg2 = 0UL;
+ flashContext.arg3 = 0UL;
+
+ if (cy_device->flashEraseDelay != 0U)
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_START_ERASE_DELAY);
+ }
+ else
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_NO_DELAY);
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_ProgramRow
+****************************************************************************//**
+*
+* This function writes an array of data to a single row of flash. Reports
+* success or a reason for failure. Does not return until the Program operation
+* is complete.
+* Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case
+* when another process is writing to flash. User firmware should not enter the
+* Hibernate or Deep-sleep mode until flash Write is complete. The Flash operation
+* is allowed in Sleep mode. During the Flash operation, the device should not be
+* reset, including the XRES pin, a software reset, and watchdog reset sources.
+* Also, low-voltage detect circuits should be configured to generate an interrupt
+* instead of a reset. Otherwise, portions of flash may undergo unexpected
+* changes.\n
+* Before calling this function, the target flash region must be erased by
+* the StartErase/EraseRow function.\n
+* Data to be programmed must be located in the SRAM memory region.
+* \note Before reading data from previously programmed/erased flash rows, the
+* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer()
+* function.
+*
+* \param rowAddr Address of the flash row number.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash write operation is
+* performing. Refer to the device datasheet for the details.
+* Address must match row start address.
+*
+* \param data The pointer to the data which has to be written to flash. The size
+* of the data array must be equal to the flash row size. The flash row size for
+* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to
+* the device datasheet for the details.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_ProgramRow(uint32_t rowAddr, const uint32_t* data)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ /* Checks whether the input parameters are valid */
+ if ((Cy_Flash_BoundsCheck(rowAddr) != false) && (NULL != data))
+ {
+ SystemCoreClockUpdate();
+
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_PROGRAM_ROW | CY_FLASH_BLOCKING_MODE;
+ flashContext.arg1 = CY_FLASH_DATA_LOC_SRAM;
+ flashContext.arg2 = rowAddr;
+ flashContext.arg3 = (uint32_t)data;
+
+ if (cy_device->flashProgramDelay != 0U)
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_START_PROGRAM_DELAY);
+ }
+ else
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_NO_DELAY);
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_WriteRow
+****************************************************************************//**
+*
+* This function writes an array of data to a single row of flash. This is done
+* in three steps - pre-program, erase and then program flash row with the input
+* data. Reports success or a reason for failure. Does not return until the Write
+* operation is complete.
+* Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case
+* when another process is writing to flash. User firmware should not enter the
+* Hibernate or Deep-sleep mode until flash Write is complete. The Flash operation
+* is allowed in Sleep mode. During the Flash operation, the
+* device should not be reset, including the XRES pin, a software
+* reset, and watchdog reset sources. Also, low-voltage detect
+* circuits should be configured to generate an interrupt
+* instead of a reset. Otherwise, portions of flash may undergo
+* unexpected changes.
+*
+* \param rowAddr Address of the flash row number.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash write operation is
+* performing. Refer to the device datasheet for the details.
+* Address must match row start address.
+*
+* \param data The pointer to the data which has to be written to flash. The size
+* of the data array must be equal to the flash row size. The flash row size for
+* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to
+* the device datasheet for the details.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ /* Checks whether the input parameters are valid */
+ if ((Cy_Flash_BoundsCheck(rowAddr) != false) && (NULL != data))
+ {
+ SystemCoreClockUpdate();
+
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_WRITE_ROW | CY_FLASH_BLOCKING_MODE;
+ flashContext.arg1 = 0UL;
+ flashContext.arg2 = rowAddr;
+ flashContext.arg3 = (uint32_t)data;
+
+ if (cy_device->flashWriteDelay != 0U)
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_START_WRITE_DELAY);
+ }
+ else
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_NO_DELAY);
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_StartWrite
+****************************************************************************//**
+*
+* Performs pre-program, erase and then starts programming the flash row with
+* the input data. Returns immediately and reports a successful start
+* or reason for failure. Reports a \ref CY_FLASH_DRV_IPC_BUSY error
+* in the case when another process is writing to flash. User
+* firmware should not enter the Hibernate or Deep-Sleep mode until
+* flash Write is complete. The Flash operation is allowed in Sleep mode.
+* During the flash operation, the device should not be reset, including the
+* XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage
+* detect circuits should be configured to generate an interrupt instead of a reset.
+* Otherwise, portions of flash may undergo unexpected changes.
+* \note Before reading data from previously programmed/erased flash rows, the
+* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer()
+* function.
+*
+* \param rowAddr Address of the flash row number.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash write operation is
+* performing. Refer to the device datasheet for the details.
+* Address must match row start address.
+*
+* \param data The pointer to the data to be written to flash. The size
+* of the data array must be equal to the flash row size. The flash row size for
+* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to
+* the device datasheet for the details.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ /* Checks whether the input parameters are valid */
+ if ((Cy_Flash_BoundsCheck(rowAddr) != false) && (NULL != data))
+ {
+ result = Cy_Flash_StartEraseRow(rowAddr);
+
+ if (CY_FLASH_DRV_OPERATION_STARTED == result)
+ {
+ /* Polls whether the IPC is released and the Flash operation is performed */
+ do
+ {
+ result = Cy_Flash_OperationStatus();
+ }
+ while (result == CY_FLASH_DRV_OPCODE_BUSY);
+
+ if (CY_FLASH_DRV_SUCCESS == result)
+ {
+ result = Cy_Flash_StartProgram(rowAddr, data);
+ }
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_IsOperationComplete
+****************************************************************************//**
+*
+* Reports a successful operation result, reason of failure or busy status
+* ( \ref CY_FLASH_DRV_OPCODE_BUSY ).
+*
+* \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t).
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_IsOperationComplete(void)
+{
+ return (Cy_Flash_OperationStatus());
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_StartProgram
+****************************************************************************//**
+*
+* Starts writing an array of data to a single row of flash. Returns immediately
+* and reports a successful start or reason for failure.
+* Reports a \ref CY_FLASH_DRV_IPC_BUSY error if another process is writing
+* to flash. The user firmware should not enter Hibernate or Deep-Sleep mode until flash
+* Program is complete. The Flash operation is allowed in Sleep mode.
+* During the Flash operation, the device should not be reset, including the
+* XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage
+* detect circuits should be configured to generate an interrupt instead of a reset.
+* Otherwise, portions of flash may undergo unexpected changes.\n
+* Before calling this function, the target flash region must be erased by
+* the StartEraseRow/EraseRow function.\n
+* Data to be programmed must be located in the SRAM memory region.
+* \note Before reading data from previously programmed/erased flash rows, the
+* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer()
+* function.
+*
+* \param rowAddr The address of the flash row number.
+* The Read-while-Write violation occurs when the Flash Write operation is
+* performing. Refer to the device datasheet for the details.
+* The address must match the row start address.
+*
+* \param data The pointer to the data to be written to flash. The size
+* of the data array must be equal to the flash row size. The flash row size for
+* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to
+* the device datasheet for the details.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_StartProgram(uint32_t rowAddr, const uint32_t* data)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ if ((Cy_Flash_BoundsCheck(rowAddr) != false) && (NULL != data))
+ {
+ SystemCoreClockUpdate();
+
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_PROGRAM_ROW;
+
+ if (SFLASH_SINGLE_CORE != 0U)
+ {
+ flashContext.opcode |= CY_FLASH_BLOCKING_MODE;
+ }
+
+ flashContext.arg1 = CY_FLASH_DATA_LOC_SRAM;
+ flashContext.arg2 = rowAddr;
+ flashContext.arg3 = (uint32_t)data;
+
+ if (cy_device->flashProgramDelay != 0U)
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_START_PROGRAM_DELAY);
+ }
+ else
+ {
+ result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_NO_DELAY);
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_RowChecksum
+****************************************************************************//**
+*
+* Returns a checksum value of the specified flash row.
+*
+* \note Now Cy_Flash_RowChecksum() requires the row <b>address</b> (rowAddr)
+* as a parameter. In previous versions of the driver, this function used
+* the row <b>number</b> (rowNum) for this parameter.
+*
+* \param rowAddr The address of the flash row.
+*
+* \param checksumPtr The pointer to the address where checksum is to be stored
+*
+* \return Returns the status of the Flash operation.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_RowChecksum (uint32_t rowAddr, uint32_t* checksumPtr)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+ uint32_t resTmp;
+ uint32_t rowID;
+
+ /* Checks whether the input parameters are valid */
+ if ((Cy_Flash_BoundsCheck(rowAddr)) && (NULL != checksumPtr))
+ {
+ rowID = Cy_Flash_GetRowNum(rowAddr);
+
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_CHECKSUM |
+ (((rowID >> CY_FLASH_REGION_ID_SHIFT) & CY_FLASH_REGION_ID_MASK) << CY_FLASH_OPCODE_CHECKSUM_REGION_SHIFT) |
+ ((rowID & CY_FLASH_ROW_ID_MASK) << CY_FLASH_OPCODE_CHECKSUM_ROW_SHIFT);
+
+ /* Tries to acquire the IPC structure and pass the arguments to SROM API */
+ if (Cy_IPC_Drv_SendMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL), CY_FLASH_IPC_NOTIFY_STRUCT0,
+ (void*)&flashContext) == CY_IPC_DRV_SUCCESS)
+ {
+ /* Polls whether IPC is released and the Flash operation is performed */
+ while (Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) != false)
+ {
+ /* Wait till IPC is released */
+ }
+
+ resTmp = flashContext.opcode >> CY_FLASH_ERROR_SHIFT;
+
+ if (resTmp == CY_FLASH_ERROR_NO_ERROR)
+ {
+ result = CY_FLASH_DRV_SUCCESS;
+
+ if (CY_IPC_V1)
+ {
+ *checksumPtr = flashContext.opcode & CY_FLASH_RESULT_MASK;
+ }
+ else
+ {
+ *checksumPtr = REG_IPC_STRUCT_DATA1(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL));
+ }
+ }
+ else
+ {
+ result = Cy_Flash_ProcessOpcode(flashContext.opcode);
+ }
+
+ }
+ else
+ {
+ /* The IPC structure is already locked by another process */
+ result = CY_FLASH_DRV_IPC_BUSY;
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_CalculateHash
+****************************************************************************//**
+*
+* Returns a hash value of the specified region of flash.
+*
+* \param data Start the data address.
+*
+* \param numberOfBytes The hash value is calculated for the number of bytes after the
+* start data address (0 - 1 byte, 1- 2 bytes etc).
+*
+* \param hashPtr The pointer to the address where hash is to be stored
+*
+* \return Returns the status of the Flash operation.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_CalculateHash (const uint32_t* data, uint32_t numberOfBytes, uint32_t* hashPtr)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+ volatile uint32_t resTmp;
+
+ /* Checks whether the input parameters are valid */
+ if ((data != NULL) && (0ul != numberOfBytes))
+ {
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_HASH;
+ flashContext.arg1 = (uint32_t)data;
+ flashContext.arg2 = numberOfBytes;
+
+ /* Tries to acquire the IPC structure and pass the arguments to SROM API */
+ if (Cy_IPC_Drv_SendMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL), CY_FLASH_IPC_NOTIFY_STRUCT0,
+ (void*)&flashContext) == CY_IPC_DRV_SUCCESS)
+ {
+ /* Polls whether IPC is released and the Flash operation is performed */
+ while (Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) != false)
+ {
+ /* Wait till IPC is released */
+ }
+
+ resTmp = flashContext.opcode;
+
+ if ((resTmp >> CY_FLASH_ERROR_SHIFT) == CY_FLASH_ERROR_NO_ERROR)
+ {
+ result = CY_FLASH_DRV_SUCCESS;
+ *hashPtr = flashContext.opcode & CY_FLASH_RESULT_MASK;
+ }
+ else
+ {
+ result = Cy_Flash_ProcessOpcode(flashContext.opcode);
+ }
+ }
+ else
+ {
+ /* The IPC structure is already locked by another process */
+ result = CY_FLASH_DRV_IPC_BUSY;
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_GetRowNum
+****************************************************************************//**
+*
+* Returns flash region ID and row number of the Flash address.
+*
+* \param flashAddr Address to be checked
+*
+* \return
+* The valid return value is encoded as follows
+* <table>
+* <tr><th>Field <th>Value
+* <tr><td>Flash row number <td>[15:0] bits
+* <tr><td>Flash region ID <td>[31:16] bits
+* </table>
+*
+*******************************************************************************/
+static uint32_t Cy_Flash_GetRowNum(uint32_t flashAddr)
+{
+ uint32_t result;
+
+ if ((flashAddr >= CY_EM_EEPROM_BASE) && (flashAddr < (CY_EM_EEPROM_BASE + CY_EM_EEPROM_SIZE)))
+ {
+ result = (CY_FLASH_REGION_ID_EM_EEPROM << CY_FLASH_REGION_ID_SHIFT) |
+ ((flashAddr - CY_EM_EEPROM_BASE) / CY_FLASH_SIZEOF_ROW);
+ }
+ else
+ if ((flashAddr >= SFLASH_BASE) && (flashAddr < (SFLASH_BASE + SFLASH_SECTION_SIZE)))
+ {
+ result = (CY_FLASH_REGION_ID_SFLASH << CY_FLASH_REGION_ID_SHIFT) |
+ ((flashAddr - SFLASH_BASE) / CY_FLASH_SIZEOF_ROW);
+ }
+ else
+ {
+ result = (CY_FLASH_REGION_ID_MAIN << CY_FLASH_REGION_ID_SHIFT) |
+ ((flashAddr - CY_FLASH_BASE) / CY_FLASH_SIZEOF_ROW);
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_BoundsCheck
+****************************************************************************//**
+*
+* The function checks the following conditions:
+* - if Flash address is equal to start address of the row
+*
+* \param flashAddr Address to be checked
+*
+* \return false - out of bound, true - in flash bounds
+*
+*******************************************************************************/
+static bool Cy_Flash_BoundsCheck(uint32_t flashAddr)
+{
+ return ((flashAddr % CY_FLASH_SIZEOF_ROW) == 0UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_ProcessOpcode
+****************************************************************************//**
+*
+* Converts System Call returns to the Flash driver return defines.
+*
+* \param opcode The value returned by the System Call.
+*
+* \return Flash driver return.
+*
+*******************************************************************************/
+static cy_en_flashdrv_status_t Cy_Flash_ProcessOpcode(uint32_t opcode)
+{
+ cy_en_flashdrv_status_t result;
+
+ switch (opcode)
+ {
+ case 0UL:
+ {
+ result = CY_FLASH_DRV_SUCCESS;
+ break;
+ }
+ case CY_FLASH_ROMCODE_SUCCESS:
+ {
+ result = CY_FLASH_DRV_SUCCESS;
+ break;
+ }
+ case CY_FLASH_ROMCODE_INVALID_PROTECTION:
+ {
+ result = CY_FLASH_DRV_INV_PROT;
+ break;
+ }
+ case CY_FLASH_ROMCODE_INVALID_FM_PL:
+ {
+ result = CY_FLASH_DRV_INVALID_FM_PL;
+ break;
+ }
+ case CY_FLASH_ROMCODE_INVALID_FLASH_ADDR:
+ {
+ result = CY_FLASH_DRV_INVALID_FLASH_ADDR;
+ break;
+ }
+ case CY_FLASH_ROMCODE_ROW_PROTECTED:
+ {
+ result = CY_FLASH_DRV_ROW_PROTECTED;
+ break;
+ }
+ case CY_FLASH_ROMCODE_IN_PROGRESS_NO_ERROR:
+ {
+ result = CY_FLASH_DRV_PROGRESS_NO_ERROR;
+ break;
+ }
+ case (uint32_t)CY_FLASH_DRV_INVALID_INPUT_PARAMETERS:
+ {
+ result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+ break;
+ }
+ case CY_FLASH_IS_OPERATION_STARTED :
+ {
+ result = CY_FLASH_DRV_OPERATION_STARTED;
+ break;
+ }
+ case CY_FLASH_IS_BUSY :
+ {
+ result = CY_FLASH_DRV_OPCODE_BUSY;
+ break;
+ }
+ case CY_FLASH_IS_IPC_BUSY :
+ {
+ result = CY_FLASH_DRV_IPC_BUSY;
+ break;
+ }
+ case CY_FLASH_IS_INVALID_INPUT_PARAMETERS :
+ {
+ result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+ break;
+ }
+ default:
+ {
+ result = CY_FLASH_DRV_ERR_UNC;
+ break;
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_OperationStatus
+****************************************************************************//**
+*
+* Checks the status of the Flash Operation, and returns it.
+*
+* \return Returns the status of the Flash operation
+* (see \ref cy_en_flashdrv_status_t).
+*
+*******************************************************************************/
+static cy_en_flashdrv_status_t Cy_Flash_OperationStatus(void)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_OPCODE_BUSY;
+
+ /* Checks if the IPC structure is not locked */
+ if (Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) == false)
+ {
+ /* The result of SROM API calling is returned to the driver context */
+ result = Cy_Flash_ProcessOpcode(flashContext.opcode);
+
+ /* Clear pre-fetch cache after flash operation */
+ FLASHC_FLASH_CMD = FLASHC_FLASH_CMD_INV_Msk;
+
+ while (FLASHC_FLASH_CMD != 0U)
+ {
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_GetExternalStatus
+****************************************************************************//**
+*
+* This function handles the case where a module such as security image captures
+* a system call from this driver and reports its own status or error code,
+* for example protection violation. In that case, a function from this
+* driver returns an unknown error (see \ref cy_en_flashdrv_status_t). After receipt
+* of an unknown error, the user may call this function to get the status
+* of the capturing module.
+*
+* The user is responsible for parsing the content of the returned value
+* and casting it to the appropriate enumeration.
+*
+* \return
+* The error code that was stored in the opcode variable.
+*
+*******************************************************************************/
+uint32_t Cy_Flash_GetExternalStatus(void)
+{
+ return (flashContext.opcode);
+}
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_gpio.c b/platform/ext/target/psoc64/Native_Driver/source/cy_gpio.c
new file mode 100644
index 0000000000..938875698a
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_gpio.c
@@ -0,0 +1,363 @@
+/***************************************************************************//**
+* \file cy_gpio.c
+* \version 1.20
+*
+* Provides an API implementation of the GPIO driver
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_gpio.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/* Define for AMUX A splitters */
+#define GPIO_AMUXA_SPLITTER_MASK (uint32_t)(HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk \
+ | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk \
+ | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk)
+
+/* Define for AMUX B splitters */
+#define GPIO_AMUXB_SPLITTER_MASK (uint32_t)(HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk \
+ | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk \
+ | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk)
+
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Pin_Init
+****************************************************************************//**
+*
+* Initializes all pin configuration settings for the specified pin.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param config
+* Pointer to the pin config structure base address
+*
+* \return
+* Initialization status
+*
+* \note
+* This function modifies port registers in read-modify-write operations. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_Pin_Init
+*
+*******************************************************************************/
+cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config)
+{
+ cy_en_gpio_status_t status = CY_GPIO_BAD_PARAM;
+
+ if ((NULL != base) && (NULL != config))
+ {
+ uint32_t maskCfgOut;
+ uint32_t tempReg;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->outVal));
+ CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(config->driveMode));
+ CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(config->hsiom));
+ CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(config->intEdge));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->intMask));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtrip));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->slewRate));
+ CY_ASSERT_L2(CY_GPIO_IS_DRIVE_SEL_VALID(config->driveSel));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vregEn));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->ibufMode));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtripSel));
+ CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(config->vrefSel));
+ CY_ASSERT_L2(CY_GPIO_IS_VOH_SEL_VALID(config->vohSel));
+
+ Cy_GPIO_Write(base, pinNum, config->outVal);
+ Cy_GPIO_SetDrivemode(base, pinNum, config->driveMode);
+ Cy_GPIO_SetHSIOM(base, pinNum, config->hsiom);
+
+ Cy_GPIO_SetInterruptEdge(base, pinNum, config->intEdge);
+ Cy_GPIO_SetInterruptMask(base, pinNum, config->intMask);
+ Cy_GPIO_SetVtrip(base, pinNum, config->vtrip);
+
+ /* Slew rate and Driver strength */
+ maskCfgOut = (CY_GPIO_CFG_OUT_SLOW_MASK << pinNum)
+ | (CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << ((uint32_t)(pinNum << 1U) + CY_GPIO_CFG_OUT_DRIVE_OFFSET));
+ tempReg = GPIO_PRT_CFG_OUT(base) & ~(maskCfgOut);
+
+ GPIO_PRT_CFG_OUT(base) = tempReg | ((config->slewRate & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum)
+ | ((config->driveSel & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << ((uint32_t)(pinNum << 1U) + CY_GPIO_CFG_OUT_DRIVE_OFFSET));
+
+ /* SIO specific configuration */
+ tempReg = GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_SIO_PIN_MASK);
+ GPIO_PRT_CFG_SIO(base) = tempReg | (((config->vregEn & CY_GPIO_VREG_EN_MASK)
+ | ((config->ibufMode & CY_GPIO_IBUF_MASK) << CY_GPIO_IBUF_SHIFT)
+ | ((config->vtripSel & CY_GPIO_VTRIP_SEL_MASK) << CY_GPIO_VTRIP_SEL_SHIFT)
+ | ((config->vrefSel & CY_GPIO_VREF_SEL_MASK) << CY_GPIO_VREF_SEL_SHIFT)
+ | ((config->vohSel & CY_GPIO_VOH_SEL_MASK) << CY_GPIO_VOH_SEL_SHIFT))
+ << ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET));
+
+ status = CY_GPIO_SUCCESS;
+ }
+
+ return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Port_Init
+****************************************************************************//**
+*
+* Initialize a complete port of pins from a single init structure.
+*
+* The configuration structure used in this function has a 1:1 mapping to the
+* GPIO and HSIOM registers. Refer to the device Technical Reference Manual (TRM)
+* for the register details on how to populate them.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param config
+* Pointer to the pin config structure base address
+*
+* \return
+* Initialization status
+*
+* \note
+* If using the PSoC Creator IDE, there is no need to initialize the pins when
+* using the GPIO component on the schematic. Ports are configured in
+* Cy_SystemInit() before main() entry.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_Port_Init
+*
+*******************************************************************************/
+cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config)
+{
+ cy_en_gpio_status_t status = CY_GPIO_BAD_PARAM;
+
+ if ((NULL != base) && (NULL != config))
+ {
+ uint32_t portNum;
+ HSIOM_PRT_V1_Type* baseHSIOM;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->out));
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->cfgIn));
+ CY_ASSERT_L2(CY_GPIO_IS_INTR_CFG_VALID(config->intrCfg));
+ CY_ASSERT_L2(CY_GPIO_IS_INTR_MASK_VALID(config->intrMask));
+ CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel0Active));
+ CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel1Active));
+
+ portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
+ baseHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
+
+ GPIO_PRT_OUT(base) = config->out;
+ GPIO_PRT_CFG(base) = config->cfg;
+ GPIO_PRT_CFG_IN(base) = config->cfgIn;
+ GPIO_PRT_CFG_OUT(base) = config->cfgOut;
+ GPIO_PRT_INTR_CFG(base) = config->intrCfg;
+ GPIO_PRT_INTR_MASK(base) = config->intrMask;
+ GPIO_PRT_CFG_SIO(base) = config->cfgSIO;
+ HSIOM_PRT_PORT_SEL0(baseHSIOM) = config->sel0Active;
+ HSIOM_PRT_PORT_SEL1(baseHSIOM) = config->sel1Active;
+
+ status = CY_GPIO_SUCCESS;
+ }
+
+ return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Pin_FastInit
+****************************************************************************//**
+*
+* Initialize the most common configuration settings for all pin types.
+*
+* These include, drive mode, initial output value, and HSIOM connection.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param driveMode
+* Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
+*
+* \param outVal
+* Logic state of the output buffer driven to the pin (1 or 0)
+*
+* \param hsiom
+* HSIOM input selection
+*
+* \note
+* This function modifies port registers in read-modify-write operations. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+* You can use the Cy_SysLib_EnterCriticalSection() and
+* Cy_SysLib_ExitCriticalSection() functions to ensure that
+* Cy_GPIO_Pin_FastInit() function execution is not interrupted.
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_Pin_FastInit
+*
+*******************************************************************************/
+void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode,
+ uint32_t outVal, en_hsiom_sel_t hsiom)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(driveMode));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(outVal));
+ CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(hsiom));
+
+ uint32_t tempReg;
+
+ tempReg = (GPIO_PRT_OUT(base) & ~(CY_GPIO_OUT_MASK << pinNum));
+ GPIO_PRT_OUT(base) = tempReg | ((outVal & CY_GPIO_OUT_MASK) << pinNum);
+
+ tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
+ GPIO_PRT_CFG(base) = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
+
+ Cy_GPIO_SetHSIOM(base, pinNum, hsiom);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Port_Deinit
+****************************************************************************//**
+*
+* Reset a complete port of pins back to power on reset defaults.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \funcusage
+* \snippet gpio/snippet/main.c snippet_Cy_GPIO_Port_Deinit
+*
+*******************************************************************************/
+void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base)
+{
+ uint32_t portNum;
+ HSIOM_PRT_V1_Type* baseHSIOM;
+
+ portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
+ baseHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
+
+ GPIO_PRT_OUT(base) = CY_GPIO_PRT_DEINIT;
+ GPIO_PRT_CFG(base) = CY_GPIO_PRT_DEINIT;
+ GPIO_PRT_CFG_IN(base) = CY_GPIO_PRT_DEINIT;
+ GPIO_PRT_CFG_OUT(base) = CY_GPIO_PRT_DEINIT;
+ GPIO_PRT_INTR_CFG(base) = CY_GPIO_PRT_DEINIT;
+ GPIO_PRT_INTR_MASK(base) = CY_GPIO_PRT_DEINIT;
+ GPIO_PRT_CFG_SIO(base) = CY_GPIO_PRT_DEINIT;
+ HSIOM_PRT_PORT_SEL0(baseHSIOM) = CY_GPIO_PRT_DEINIT;
+ HSIOM_PRT_PORT_SEL1(baseHSIOM) = CY_GPIO_PRT_DEINIT;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetAmuxSplit
+****************************************************************************//**
+*
+* Configure a specific AMux bus splitter switch cell into a specific
+* configuration.
+*
+* \param switchCtrl
+* Selects specific AMux bus splitter cell between two segments.
+* The cy_en_amux_split_t enumeration can be found in the GPIO header file
+* for the device package.
+*
+* \param amuxConnect
+* Selects configuration of the three switches within the splitter cell
+*
+* \param amuxBus
+* Selects which AMux bus within the splitter is being configured
+*
+*******************************************************************************/
+void Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_t amuxConnect,
+ cy_en_gpio_amuxselect_t amuxBus)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_AMUX_SPLIT_VALID(switchCtrl));
+ CY_ASSERT_L3(CY_GPIO_IS_AMUX_CONNECT_VALID(amuxConnect));
+ CY_ASSERT_L3(CY_GPIO_IS_AMUX_SELECT_VALID(amuxBus));
+
+ uint32_t tmpReg;
+
+ if (amuxBus != CY_GPIO_AMUXBUSB)
+ {
+ tmpReg = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXB_SPLITTER_MASK;
+ HSIOM_AMUX_SPLIT_CTL(switchCtrl) = tmpReg | ((uint32_t) amuxConnect & GPIO_AMUXA_SPLITTER_MASK);
+ }
+ else
+ {
+ tmpReg = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXA_SPLITTER_MASK;
+ HSIOM_AMUX_SPLIT_CTL(switchCtrl) =
+ tmpReg | (((uint32_t) amuxConnect << HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos) & GPIO_AMUXB_SPLITTER_MASK);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetAmuxSplit
+****************************************************************************//**
+*
+* Returns the configuration of a specific AMux bus splitter switch cell.
+*
+* \param switchCtrl
+* Selects specific AMux bus splitter cell between two segments.
+* The cy_en_amux_split_t enumeration can be found in the GPIO header file
+* for the device package.
+*
+* \param amuxBus
+* Selects which AMux bus within the splitter is being configured
+*
+* \return
+* Returns configuration of the three switches in the selected splitter cell
+*
+*******************************************************************************/
+cy_en_gpio_amuxconnect_t Cy_GPIO_GetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxselect_t amuxBus)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_AMUX_SPLIT_VALID(switchCtrl));
+ CY_ASSERT_L3(CY_GPIO_IS_AMUX_SELECT_VALID(amuxBus));
+
+ uint32_t retVal;
+
+ if (amuxBus != CY_GPIO_AMUXBUSB)
+ {
+ retVal = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXA_SPLITTER_MASK;
+ }
+ else
+ {
+ retVal = ((uint32_t) ((HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXB_SPLITTER_MASK)
+ >> HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos));
+ }
+
+ return ((cy_en_gpio_amuxconnect_t) retVal);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_ipc_drv.c b/platform/ext/target/psoc64/Native_Driver/source/cy_ipc_drv.c
new file mode 100644
index 0000000000..c70eed7b77
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_ipc_drv.c
@@ -0,0 +1,181 @@
+/***************************************************************************//**
+* \file cy_ipc_drv.c
+* \version 1.40
+*
+* \brief
+* IPC Driver - This source file contains the low-level driver code for
+* the IPC hardware.
+*
+********************************************************************************
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_ipc_drv.h"
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_LockRelease
+****************************************************************************//**
+*
+* The function is used to release an IPC channel from the locked state.
+* The function also has a way to specify through a parameter which IPC
+* interrupts must be notified during the release event.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param releaseEventIntr
+* Bit encoded list of IPC interrupt lines that are triggered by a release event.
+*
+* \return Status of the operation
+* \retval CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC channel
+* was released.
+* \retval CY_IPC_DRV_ERROR: The IPC channel was not acquired before the
+* function call.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_ReadMsgPtr
+*
+*******************************************************************************/
+cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type* base, uint32_t releaseEventIntr)
+{
+ cy_en_ipcdrv_status_t retStatus;
+
+ /* Check to make sure the IPC is Acquired */
+ if( Cy_IPC_Drv_IsLockAcquired(base) )
+ {
+ /* The IPC was acquired, release the IPC channel */
+ Cy_IPC_Drv_ReleaseNotify(base, releaseEventIntr);
+
+ retStatus = CY_IPC_DRV_SUCCESS;
+ }
+ else /* The IPC channel was already released (not acquired) */
+ {
+ retStatus = CY_IPC_DRV_ERROR;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_SendMsgWord
+****************************************************************************//**
+*
+* This function is used to send a 32-bit word message through an IPC channel.
+* The function also has an associated notification field that will let the
+* message notify one or multiple IPC interrupts. The IPC channel is locked and
+* remains locked after the function returns. The receiver of the message should
+* release the channel.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param notifyEventIntr
+* Bit encoded list of IPC interrupt lines that are triggered by a notification.
+*
+* \param message
+* The message word that is the data placed in the IPC data register.
+*
+* \return Status of the operation:
+* \retval CY_IPC_DRV_SUCCESS: The send operation was successful.
+* \retval CY_IPC_DRV_ERROR: The IPC channel is unavailable because it is already locked.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_SendMsgWord
+*
+*******************************************************************************/
+cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type* base, uint32_t notifyEventIntr, uint32_t message)
+{
+ cy_en_ipcdrv_status_t retStatus;
+
+ if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire(base) )
+ {
+ /* If the channel was acquired, send the message. */
+ Cy_IPC_Drv_WriteDataValue(base, message);
+
+ Cy_IPC_Drv_AcquireNotify(base, notifyEventIntr);
+
+ retStatus = CY_IPC_DRV_SUCCESS;
+ }
+ else
+ {
+ /* Channel was already acquired, return Error */
+ retStatus = CY_IPC_DRV_ERROR;
+ }
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ReadMsgWord
+****************************************************************************//**
+*
+* This function is used to read a 32-bit word message through an IPC channel.
+* This function assumes that the channel is locked (for a valid message).
+* If the channel is not locked, the message is invalid. The user must call
+* Cy_IPC_Drv_Release() function after reading the message to release the
+* IPC channel.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param message
+* A variable where the read data is copied.
+*
+* \return Status of the operation
+* \retval CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC
+* was acquired.
+* \retval CY_IPC_DRV_ERROR: The function encountered an error because the IPC
+* channel was already in a released state, meaning the data
+* may be invalid.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Drv_ReadMsgWord
+*
+*******************************************************************************/
+cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgWord (IPC_STRUCT_Type const * base, uint32_t * message)
+{
+ cy_en_ipcdrv_status_t retStatus;
+
+ CY_ASSERT_L1(NULL != message);
+
+ if ( Cy_IPC_Drv_IsLockAcquired(base) )
+ {
+ /* The channel is locked; message is valid. */
+ *message = Cy_IPC_Drv_ReadDataValue(base);
+
+ retStatus = CY_IPC_DRV_SUCCESS;
+ }
+ else
+ {
+ /* The channel is not locked so channel is invalid. */
+ retStatus = CY_IPC_DRV_ERROR;
+ }
+ return(retStatus);
+}
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_ipc_pipe.c b/platform/ext/target/psoc64/Native_Driver/source/cy_ipc_pipe.c
new file mode 100644
index 0000000000..5800baa614
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_ipc_pipe.c
@@ -0,0 +1,608 @@
+/***************************************************************************//**
+* \file cy_ipc_pipe.c
+* \version 1.40
+*
+* Description:
+* IPC Pipe Driver - This source file includes code for the Pipe layer on top
+* of the IPC driver.
+*
+********************************************************************************
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_ipc_pipe.h"
+
+/* Define a pointer to array of endPoints. */
+static cy_stc_ipc_pipe_ep_t * cy_ipc_pipe_epArray = NULL;
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_Config
+****************************************************************************//**
+*
+* This function stores a copy of a pointer to the array of endpoints. All
+* access to endpoints will be via the index of the endpoint in this array.
+*
+* \note In general case, this function is called in the default startup code,
+* so user doesn't need to call it anywhere.
+* However, it may be useful in case of some pipe customizations.
+*
+* \param theEpArray
+* This is the pointer to an array of endpoint structures that the designer
+* created and will be used to reference all endpoints.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_myIpcPipeEpArray
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_Config
+*
+*******************************************************************************/
+void Cy_IPC_Pipe_Config(cy_stc_ipc_pipe_ep_t * theEpArray)
+{
+ /* Keep copy of this endpoint */
+ if (cy_ipc_pipe_epArray == NULL)
+ {
+ cy_ipc_pipe_epArray = theEpArray;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_Init
+****************************************************************************//**
+*
+* Initializes the system pipes. The system pipes are used by BLE.
+* \note The function should be called on all CPUs.
+*
+* \note In general case, this function is called in the default startup code,
+* so user doesn't need to call it anywhere.
+* However, it may be useful in case of some pipe customizations.
+*
+* \param config
+* This is the pointer to the pipe configuration structure
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_myIpcPipeCbArray
+* \snippet ipc/snippet/main.c snippet_myIpcPipeEpConfig
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_Init
+*
+*******************************************************************************/
+void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config)
+{
+ /* Create the interrupt structures and arrays needed */
+
+ cy_stc_sysint_t ipc_intr_cypipeConfig;
+
+ cy_stc_ipc_pipe_ep_config_t epConfigDataA;
+ cy_stc_ipc_pipe_ep_config_t epConfigDataB;
+
+ /* Parameters checking begin */
+ CY_ASSERT_L1(NULL != config);
+ #if (CY_CPU_CORTEX_M0P)
+ CY_ASSERT_L2((uint32_t)(1UL << __NVIC_PRIO_BITS) > config->ep0ConfigData.ipcNotifierPriority);
+ #else
+ CY_ASSERT_L2((uint32_t)(1UL << __NVIC_PRIO_BITS) > config->ep1ConfigData.ipcNotifierPriority);
+ #endif
+ CY_ASSERT_L1(NULL != config->endpointsCallbacksArray);
+ CY_ASSERT_L1(NULL != config->userPipeIsrHandler);
+ /* Parameters checking end */
+
+#if (CY_CPU_CORTEX_M0P)
+
+ /* Receiver endpoint = EP0, Sender endpoint = EP1 */
+ epConfigDataA = config->ep0ConfigData;
+ epConfigDataB = config->ep1ConfigData;
+
+ /* Configure CM0 interrupts */
+ ipc_intr_cypipeConfig.intrSrc = (IRQn_Type)epConfigDataA.ipcNotifierMuxNumber;
+ ipc_intr_cypipeConfig.cm0pSrc = (cy_en_intr_t)((int32_t)cy_device->cpussIpc0Irq + (int32_t)epConfigDataA.ipcNotifierNumber);
+ ipc_intr_cypipeConfig.intrPriority = epConfigDataA.ipcNotifierPriority;
+
+#else
+
+ /* Receiver endpoint = EP1, Sender endpoint = EP0 */
+ epConfigDataA = config->ep1ConfigData;
+ epConfigDataB = config->ep0ConfigData;
+
+ /* Configure interrupts */
+ ipc_intr_cypipeConfig.intrSrc = (IRQn_Type)((int32_t)cy_device->cpussIpc0Irq + (int32_t)epConfigDataA.ipcNotifierNumber);
+ ipc_intr_cypipeConfig.intrPriority = epConfigDataA.ipcNotifierPriority;
+
+#endif
+
+ /* Initialize the pipe endpoints */
+ Cy_IPC_Pipe_EndpointInit(epConfigDataA.epAddress,
+ config->endpointsCallbacksArray,
+ config->endpointClientsCount,
+ epConfigDataA.epConfig,
+ &ipc_intr_cypipeConfig);
+
+ /* Create the endpoints for the CM4 just for reference */
+ Cy_IPC_Pipe_EndpointInit(epConfigDataB.epAddress, NULL, 0ul, epConfigDataB.epConfig, NULL);
+
+ (void)Cy_SysInt_Init(&ipc_intr_cypipeConfig, config->userPipeIsrHandler);
+
+ /* Enable the interrupts */
+ NVIC_EnableIRQ(ipc_intr_cypipeConfig.intrSrc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_EndpointInit
+****************************************************************************//**
+*
+* This function initializes the endpoint of a pipe for the current CPU. The
+* current CPU is the CPU that is executing the code. An endpoint of a pipe
+* is for the IPC channel that receives a message for the current CPU.
+*
+* After this function is called, the callbackArray needs to be populated
+* with the callback functions for that endpoint using the
+* Cy_IPC_Pipe_RegisterCallback() function.
+*
+* \note In general case, this function is called within \ref Cy_IPC_Pipe_Init,
+* so user doesn't need to call it anywhere.
+* However, it may be useful in case of some pipe/endpoint customizations.
+*
+* \param epAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* that designates the endpoint you want to initialize.
+*
+* \param cbArray
+* This is a pointer to the callback function array. Based on the client ID, one
+* of the functions in this array is called to process the message.
+*
+* \param cbCnt
+* This is the size of the callback array, or the number of defined clients.
+*
+* \param epConfig
+* This value defines the IPC channel, IPC interrupt number, and the interrupt
+* mask for the entire pipe.
+* The format of the endpoint configuration
+* Bits[31:16] Interrupt Mask
+* Bits[15:8 ] IPC interrupt
+* Bits[ 7:0 ] IPC channel
+*
+* \param epInterrupt
+* This is a pointer to the endpoint interrupt description structure.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_myIpcPipeCbArray
+* \snippet ipc/snippet/main.c snippet_myIpcPipeEpConfig
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_EndpointInit
+*
+*******************************************************************************/
+void Cy_IPC_Pipe_EndpointInit(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t cbArray,
+ uint32_t cbCnt, uint32_t epConfig, cy_stc_sysint_t const *epInterrupt)
+{
+ cy_stc_ipc_pipe_ep_t * endpoint;
+
+ CY_ASSERT_L1(NULL != cy_ipc_pipe_epArray);
+
+ endpoint = &cy_ipc_pipe_epArray[epAddr];
+
+ /* Extract the channel, interrupt and interrupt mask */
+ endpoint->ipcChan = _FLD2VAL(CY_IPC_PIPE_CFG_CHAN, epConfig);
+ endpoint->intrChan = _FLD2VAL(CY_IPC_PIPE_CFG_INTR, epConfig);
+ endpoint->pipeIntMask = _FLD2VAL(CY_IPC_PIPE_CFG_IMASK, epConfig);
+
+ /* Assign IPC channel to this endpoint */
+ endpoint->ipcPtr = Cy_IPC_Drv_GetIpcBaseAddress (endpoint->ipcChan);
+
+ /* Assign interrupt structure to endpoint and Initialize the interrupt mask for this endpoint */
+ endpoint->ipcIntrPtr = Cy_IPC_Drv_GetIntrBaseAddr(endpoint->intrChan);
+
+ /* Only allow notify and release interrupts from endpoints in this pipe. */
+ Cy_IPC_Drv_SetInterruptMask(endpoint->ipcIntrPtr, endpoint->pipeIntMask, endpoint->pipeIntMask);
+
+ /* Save the Client count and the callback array pointer */
+ endpoint->clientCount = cbCnt;
+ endpoint->callbackArray = cbArray;
+ endpoint->busy = CY_IPC_PIPE_ENDPOINT_NOTBUSY;
+
+ if (NULL != epInterrupt)
+ {
+ endpoint->pipeIntrSrc = epInterrupt->intrSrc;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_SendMessage
+****************************************************************************//**
+*
+* This function is used to send a message from one endpoint to another. It
+* generates an interrupt on the endpoint that receives the message and a
+* release interrupt to the sender to acknowledge the message has been processed.
+*
+* \param toAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* of the endpoint to which you are sending the message.
+*
+* \param fromAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* of the endpoint from which the message is being sent.
+*
+* \param msgPtr
+* Pointer to the message structure to be sent.
+*
+* \param callBackPtr
+* Pointer to the Release callback function.
+*
+* \return
+* CY_IPC_PIPE_SUCCESS: Message was sent to the other end of the pipe
+* CY_IPC_PIPE_ERROR_BAD_HANDLE: The handle provided for the pipe was not valid
+* CY_IPC_PIPE_ERROR_SEND_BUSY: The pipe is already busy sending a message
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_myReleaseCallback
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_SendMessage
+*
+*******************************************************************************/
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAddr,
+ void * msgPtr, cy_ipc_pipe_relcallback_ptr_t callBackPtr)
+{
+ cy_en_ipc_pipe_status_t returnStatus;
+ uint32_t releaseMask;
+ uint32_t notifyMask;
+
+ cy_stc_ipc_pipe_ep_t * fromEp;
+ cy_stc_ipc_pipe_ep_t * toEp;
+
+ CY_ASSERT_L1(NULL != msgPtr);
+ CY_ASSERT_L1(NULL != cy_ipc_pipe_epArray);
+
+ toEp = &(cy_ipc_pipe_epArray[toAddr]);
+ fromEp = &cy_ipc_pipe_epArray[fromAddr];
+
+ /* Create the release mask for the "fromAddr" channel's interrupt channel */
+ releaseMask = (uint32_t)(1ul << (fromEp->intrChan));
+
+ /* Shift into position */
+ releaseMask = _VAL2FLD(CY_IPC_PIPE_MSG_RELEASE, releaseMask);
+
+ /* Create the notify mask for the "toAddr" channel's interrupt channel */
+ notifyMask = (uint32_t)(1ul << (toEp->intrChan));
+
+ /* Check if IPC channel valid */
+ if( toEp->ipcPtr != NULL)
+ {
+ if(fromEp->busy == CY_IPC_PIPE_ENDPOINT_NOTBUSY)
+ {
+ /* Attempt to acquire the channel */
+ if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire(toEp->ipcPtr) )
+ {
+ /* Mask out the release mask area */
+ * (uint32_t *) msgPtr &= ~(CY_IPC_PIPE_MSG_RELEASE_Msk);
+
+ * (uint32_t *) msgPtr |= releaseMask;
+
+ /* If the channel was acquired, write the message. */
+ Cy_IPC_Drv_WriteDataValue(toEp->ipcPtr, (uint32_t) msgPtr);
+
+ /* Set the busy flag. The ISR clears this after the release */
+ fromEp->busy = CY_IPC_PIPE_ENDPOINT_BUSY;
+
+ /* Setup release callback function */
+ fromEp->releaseCallbackPtr = callBackPtr;
+
+ /* Cause notify event/interrupt */
+ Cy_IPC_Drv_AcquireNotify(toEp->ipcPtr, notifyMask);
+
+ returnStatus = CY_IPC_PIPE_SUCCESS;
+ }
+ else
+ {
+ /* Channel was already acquired, return Error */
+ returnStatus = CY_IPC_PIPE_ERROR_SEND_BUSY;
+ }
+ }
+ else
+ {
+ /* Channel may not be acquired, but the release interrupt has not executed yet */
+ returnStatus = CY_IPC_PIPE_ERROR_SEND_BUSY;
+ }
+ }
+ else
+ {
+ /* Null pipe handle. */
+ returnStatus = CY_IPC_PIPE_ERROR_BAD_HANDLE;
+ }
+ return (returnStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_RegisterCallback
+****************************************************************************//**
+*
+* This function registers a callback that is called when a message is received
+* on a pipe.
+* The client_ID is the same as the index of the callback function array.
+* The callback may be a real function pointer or NULL if no callback is required.
+*
+* \param epAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* that designates the endpoint to which you want to add callback functions.
+*
+* \param callBackPtr
+* Pointer to the callback function called when the endpoint has received a message.
+* If this parameters is NULL current callback will be unregistered.
+*
+* \param clientId
+* The index in the callback array (Client ID) where the function pointer is saved.
+*
+* \return
+* CY_IPC_PIPE_SUCCESS: Callback registered successfully
+* CY_IPC_PIPE_ERROR_BAD_CLIENT: Client ID out of range, callback not registered.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_myAcquireCallback
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_RegisterCallback
+*
+*******************************************************************************/
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_RegisterCallback(uint32_t epAddr, cy_ipc_pipe_callback_ptr_t callBackPtr, uint32_t clientId)
+{
+ cy_en_ipc_pipe_status_t returnStatus;
+ cy_stc_ipc_pipe_ep_t * thisEp;
+
+ CY_ASSERT_L1(NULL != cy_ipc_pipe_epArray);
+
+ thisEp = &cy_ipc_pipe_epArray[epAddr];
+
+ CY_ASSERT_L1(NULL != thisEp->callbackArray);
+
+ /* Check if clientId is between 0 and less than client count */
+ if (clientId < thisEp->clientCount)
+ {
+ /* Copy callback function into callback function pointer array */
+ thisEp->callbackArray[clientId] = callBackPtr;
+
+ returnStatus = CY_IPC_PIPE_SUCCESS;
+ }
+ else
+ {
+ returnStatus = CY_IPC_PIPE_ERROR_BAD_CLIENT;
+ }
+ return (returnStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_RegisterCallbackRel
+****************************************************************************//**
+*
+* This function registers a default callback if a release interrupt
+* is generated but the current release callback function is null.
+*
+*
+* \param epAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* that designates the endpoint to which you want to add a release callback function.
+*
+* \param callBackPtr
+* Pointer to the callback executed when the endpoint has received a message.
+* If this parameters is NULL current callback will be unregistered.
+*
+* \return
+* None
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_myDefaultReleaseCallback
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_RegisterCallbackRel
+*
+*******************************************************************************/
+void Cy_IPC_Pipe_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_ptr_t callBackPtr)
+{
+ cy_stc_ipc_pipe_ep_t * endpoint;
+
+ CY_ASSERT_L1(NULL != cy_ipc_pipe_epArray);
+
+ endpoint = &cy_ipc_pipe_epArray[epAddr];
+
+ /* Copy callback function into callback function pointer array */
+ endpoint->defaultReleaseCallbackPtr = callBackPtr;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_ExecuteCallback
+****************************************************************************//**
+*
+* This function is called by the ISR for a given pipe endpoint to dispatch
+* the appropriate callback function based on the client ID for that endpoint.
+*
+* \param epAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* that designates the endpoint to process.
+*
+* \note This function should be used instead of obsolete
+* Cy_IPC_Pipe_ExecCallback() function because it will be removed in the
+* next releases.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_myIpcPipeEpArray
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_ExecuteCallback
+*
+*******************************************************************************/
+void Cy_IPC_Pipe_ExecuteCallback(uint32_t epAddr)
+{
+ cy_stc_ipc_pipe_ep_t * endpoint;
+
+ CY_ASSERT_L1(NULL != cy_ipc_pipe_epArray);
+
+ endpoint = &cy_ipc_pipe_epArray[epAddr];
+
+ Cy_IPC_Pipe_ExecCallback(endpoint);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_ExecCallback
+****************************************************************************//**
+*
+* This function is called by the ISR for a given pipe endpoint to dispatch
+* the appropriate callback function based on the client ID for that endpoint.
+*
+* \param endpoint
+* Pointer to endpoint structure.
+*
+* \note This function is obsolete and will be removed in the next releases.
+* Please use Cy_IPC_Pipe_ExecuteCallback() instead.
+*
+*******************************************************************************/
+void Cy_IPC_Pipe_ExecCallback(cy_stc_ipc_pipe_ep_t * endpoint)
+{
+ uint32_t *msgPtr = NULL;
+ uint32_t clientID;
+ uint32_t shadowIntr;
+ uint32_t releaseMask = (uint32_t)0;
+
+ cy_ipc_pipe_callback_ptr_t callbackPtr;
+
+ /* Parameters checking begin */
+ CY_ASSERT_L1(NULL != endpoint);
+ CY_ASSERT_L1(NULL != endpoint->ipcPtr);
+ CY_ASSERT_L1(NULL != endpoint->ipcIntrPtr);
+ CY_ASSERT_L1(NULL != endpoint->callbackArray);
+ /* Parameters checking end */
+
+ shadowIntr = Cy_IPC_Drv_GetInterruptStatusMasked(endpoint->ipcIntrPtr);
+
+ /* Check to make sure the interrupt was a notify interrupt */
+ if (0ul != Cy_IPC_Drv_ExtractAcquireMask(shadowIntr))
+ {
+ /* Clear the notify interrupt. */
+ Cy_IPC_Drv_ClearInterrupt(endpoint->ipcIntrPtr, CY_IPC_NO_NOTIFICATION, Cy_IPC_Drv_ExtractAcquireMask(shadowIntr));
+
+ if ( Cy_IPC_Drv_IsLockAcquired (endpoint->ipcPtr) )
+ {
+ /* Extract Client ID */
+ if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_ReadMsgPtr (endpoint->ipcPtr, (void **)&msgPtr))
+ {
+ /* Get release mask */
+ releaseMask = _FLD2VAL(CY_IPC_PIPE_MSG_RELEASE, *msgPtr);
+ clientID = _FLD2VAL(CY_IPC_PIPE_MSG_CLIENT, *msgPtr);
+
+ /* Make sure client ID is within valid range */
+ if (endpoint->clientCount > clientID)
+ {
+ callbackPtr = endpoint->callbackArray[clientID]; /* Get the callback function */
+
+ if (callbackPtr != NULL)
+ {
+ callbackPtr(msgPtr); /* Call the function pointer for "clientID" */
+ }
+ }
+ }
+
+ /* Must always release the IPC channel */
+ (void)Cy_IPC_Drv_LockRelease (endpoint->ipcPtr, releaseMask);
+ }
+ }
+
+ /* Check to make sure the interrupt was a release interrupt */
+ if (0ul != Cy_IPC_Drv_ExtractReleaseMask(shadowIntr)) /* Check for a Release interrupt */
+ {
+ /* Clear the release interrupt */
+ Cy_IPC_Drv_ClearInterrupt(endpoint->ipcIntrPtr, Cy_IPC_Drv_ExtractReleaseMask(shadowIntr), CY_IPC_NO_NOTIFICATION);
+
+ if (endpoint->releaseCallbackPtr != NULL)
+ {
+ endpoint->releaseCallbackPtr();
+
+ /* Clear the pointer after it was called */
+ endpoint->releaseCallbackPtr = NULL;
+ }
+ else
+ {
+ if (endpoint->defaultReleaseCallbackPtr != NULL)
+ {
+ endpoint->defaultReleaseCallbackPtr();
+ }
+ }
+
+ /* Clear the busy flag when release is detected */
+ endpoint->busy = CY_IPC_PIPE_ENDPOINT_NOTBUSY;
+ }
+
+ (void)Cy_IPC_Drv_GetInterruptStatus(endpoint->ipcIntrPtr);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_EndpointPause
+****************************************************************************//**
+*
+* This function sets the receiver endpoint to paused state.
+*
+* \param epAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* that designates the endpoint to pause.
+*
+* \return
+* CY_IPC_PIPE_SUCCESS: Callback registered successfully
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_EndpointPauseResume
+*
+*******************************************************************************/
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointPause(uint32_t epAddr)
+{
+ cy_stc_ipc_pipe_ep_t * endpoint;
+
+ CY_ASSERT_L1(NULL != cy_ipc_pipe_epArray);
+
+ endpoint = &cy_ipc_pipe_epArray[epAddr];
+
+ /* Disable the interrupts */
+ NVIC_DisableIRQ(endpoint->pipeIntrSrc);
+
+ return (CY_IPC_PIPE_SUCCESS);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_EndpointResume
+****************************************************************************//**
+*
+* This function sets the receiver endpoint to active state.
+*
+* \param epAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* that designates the endpoint to resume.
+*
+* \return
+* CY_IPC_PIPE_SUCCESS: Callback registered successfully
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Pipe_EndpointPauseResume
+*
+*******************************************************************************/
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointResume(uint32_t epAddr)
+{
+ cy_stc_ipc_pipe_ep_t * endpoint;
+
+ CY_ASSERT_L1(NULL != cy_ipc_pipe_epArray);
+
+ endpoint = &cy_ipc_pipe_epArray[epAddr];
+
+ /* Enable the interrupts */
+ NVIC_EnableIRQ(endpoint->pipeIntrSrc);
+
+ return (CY_IPC_PIPE_SUCCESS);
+}
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_ipc_sema.c b/platform/ext/target/psoc64/Native_Driver/source/cy_ipc_sema.c
new file mode 100644
index 0000000000..b5120d15d6
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_ipc_sema.c
@@ -0,0 +1,445 @@
+/***************************************************************************//**
+* \file cy_ipc_sema.c
+* \version 1.40
+*
+* Description:
+* IPC Semaphore Driver - This source file contains the source code for the
+* semaphore level APIs for the IPC interface.
+*
+********************************************************************************
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_ipc_drv.h"
+#include "cy_ipc_sema.h"
+#include "cy_syslib.h"
+#include <string.h> /* The memset() definition */
+
+/* Defines a mask to Check if semaphore count is a multiple of 32 */
+#define CY_IPC_SEMA_PER_WORD_MASK (CY_IPC_SEMA_PER_WORD - 1ul)
+
+/* Pointer to IPC structure used for semaphores */
+static IPC_STRUCT_Type* cy_semaIpcStruct;
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Sema_Init
+****************************************************************************//**
+*
+* This function initializes the semaphores subsystem. The user must create an
+* array of unsigned 32-bit words to hold the semaphore bits. The number
+* of semaphores will be the size of the array * 32. The total semaphores count
+* will always be a multiple of 32.
+*
+* \note In a multi-CPU system this init function should be called with all
+* initialized parameters on one CPU only to provide a pointer to SRAM that can
+* be shared between all the CPUs in the system that will use semaphores.
+* On other CPUs user must specify the IPC semaphores channel and pass 0 / NULL
+* to count and memPtr parameters correspondingly.
+*
+* \param ipcChannel
+* The IPC channel number used for semaphores
+*
+* \param count
+* The maximum number of semaphores to be supported (multiple of 32).
+*
+* \param memPtr
+* This points to the array of (count/32) words that contain the semaphore data.
+*
+* \return Status of the operation
+* \retval CY_IPC_SEMA_SUCCESS: Successfully initialized
+* \retval CY_IPC_SEMA_BAD_PARAM: Memory pointer is NULL and count is not zero,
+* or count not multiple of 32
+* \retval CY_IPC_SEMA_ERROR_LOCKED: Could not acquire semaphores IPC channel
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Sema_Init
+*
+*******************************************************************************/
+cy_en_ipcsema_status_t Cy_IPC_Sema_Init(uint32_t ipcChannel,
+ uint32_t count, uint32_t memPtr[])
+{
+ /* Structure containing semaphores control data */
+ CY_SECTION(".cy_sharedmem")
+ static cy_stc_ipc_sema_t cy_semaData;
+
+ cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_BAD_PARAM;
+
+ if( (NULL == memPtr) && (0u == count))
+ {
+ cy_semaIpcStruct = Cy_IPC_Drv_GetIpcBaseAddress(ipcChannel);
+
+ retStatus = CY_IPC_SEMA_SUCCESS;
+ }
+
+ /* Check for non Null pointers and count value */
+ else if ((NULL != memPtr) && (0u != count))
+ {
+ cy_semaData.maxSema = count;
+ cy_semaData.arrayPtr = memPtr;
+
+ retStatus = Cy_IPC_Sema_InitExt(ipcChannel, &cy_semaData);
+ }
+
+ else
+ {
+ retStatus = CY_IPC_SEMA_BAD_PARAM;
+ }
+
+ return(retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Sema_InitExt
+****************************************************************************//**
+* This function initializes the semaphores subsystem. The user must create an
+* array of unsigned 32-bit words to hold the semaphore bits. The number
+* of semaphores will be the size of the array * 32. The total semaphores count
+* will always be a multiple of 32.
+*
+* \note In a multi-CPU system this init function should be called with all
+* initialized parameters on one CPU only to provide a pointer to SRAM that can
+* be shared between all the CPUs in the system that will use semaphores.
+* On other CPUs user must specify the IPC semaphores channel and pass 0 / NULL
+* to count and memPtr parameters correspondingly.
+*
+* \param ipcChannel
+* The IPC channel number used for semaphores
+*
+* \param ipcSema
+* This is configuration structure of the IPC semaphore.
+* See \ref cy_stc_ipc_sema_t.
+*
+* \return Status of the operation
+* \retval CY_IPC_SEMA_SUCCESS: Successfully initialized
+* \retval CY_IPC_SEMA_BAD_PARAM: Memory pointer is NULL and count is not zero,
+* or count not multiple of 32
+* \retval CY_IPC_SEMA_ERROR_LOCKED: Could not acquire semaphores IPC channel
+*
+*******************************************************************************/
+cy_en_ipcsema_status_t Cy_IPC_Sema_InitExt(uint32_t ipcChannel, cy_stc_ipc_sema_t *ipcSema)
+{
+ cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_BAD_PARAM;
+
+ if (ipcChannel >= CY_IPC_CHANNELS)
+ {
+ retStatus = CY_IPC_SEMA_BAD_PARAM;
+ }
+ else
+ {
+ if(NULL != ipcSema)
+ {
+ /* Check if semaphore count is a multiple of 32 */
+ if( 0ul == (ipcSema->maxSema & CY_IPC_SEMA_PER_WORD_MASK))
+ {
+ cy_semaIpcStruct = Cy_IPC_Drv_GetIpcBaseAddress(ipcChannel);
+
+ /* Initialize all semaphores to released */
+ (void)memset(ipcSema->arrayPtr, 0, (ipcSema->maxSema /8u));
+
+ /* Make sure semaphores start out released. */
+ /* Ignore the return value since it is OK if it was already released. */
+ (void) Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION);
+
+ /* Set the IPC Data with the pointer to the array. */
+ if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_SendMsgPtr (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION, ipcSema))
+ {
+ if(CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION))
+ {
+ retStatus = CY_IPC_SEMA_SUCCESS;
+ }
+ else
+ {
+ /* IPC channel not released, still semaphored */
+ retStatus = CY_IPC_SEMA_ERROR_LOCKED;
+ }
+ }
+ else
+ {
+ /* Could not acquire semaphore channel */
+ retStatus = CY_IPC_SEMA_ERROR_LOCKED;
+ }
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_BAD_PARAM;
+ }
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_BAD_PARAM;
+ }
+ }
+
+ return(retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Sema_Set
+****************************************************************************//**
+*
+* This function tries to acquire a semaphore. If the
+* semaphore is not available, this function returns immediately with
+* CY_IPC_SEMA_LOCKED.
+*
+* It first acquires the IPC channel that is used for all the semaphores, sets
+* the semaphore if it is cleared, then releases the IPC channel used for the
+* semaphore.
+*
+* \param semaNumber
+* The semaphore number to acquire.
+*
+* \param preemptable
+* When this parameter is enabled the function can be preempted by another
+* task or other forms of context switching in an RTOS environment.
+*
+* \note
+* If <b>preemptable</b> is enabled (true), the user must ensure that there are
+* no deadlocks in the system, which can be caused by an interrupt that occurs
+* after the IPC channel is locked. Unless the user is ready to handle IPC
+* channel locks correctly at the application level, set <b>preemptable</b> to
+* false.
+*
+* \return Status of the operation
+* \retval CY_IPC_SEMA_SUCCESS: The semaphore was set successfully
+* \retval CY_IPC_SEMA_LOCKED: The semaphore channel is busy or locked
+* by another process
+* \retval CY_IPC_SEMA_NOT_ACQUIRED: Semaphore was already set
+* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Sema_Set
+*
+*******************************************************************************/
+cy_en_ipcsema_status_t Cy_IPC_Sema_Set(uint32_t semaNumber, bool preemptable)
+{
+ uint32_t semaIndex;
+ uint32_t semaMask;
+ uint32_t interruptState = 0ul;
+
+ cy_stc_ipc_sema_t *semaStruct;
+ cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_LOCKED;
+
+ /* Get pointer to structure */
+ semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct);
+
+ if (semaNumber < semaStruct->maxSema)
+ {
+ semaIndex = semaNumber / CY_IPC_SEMA_PER_WORD;
+ semaMask = (uint32_t)(1ul << (semaNumber - (semaIndex * CY_IPC_SEMA_PER_WORD) ));
+
+ if (!preemptable)
+ {
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ }
+
+ /* Check to make sure the IPC channel is released
+ If so, check if specific channel can be locked. */
+ if(CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire (cy_semaIpcStruct))
+ {
+ if((semaStruct->arrayPtr[semaIndex] & semaMask) == 0ul)
+ {
+ semaStruct->arrayPtr[semaIndex] |= semaMask;
+ retStatus = CY_IPC_SEMA_SUCCESS;
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_NOT_ACQUIRED;
+ }
+
+ /* Release, but do not trigger a release event */
+ (void) Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION);
+ }
+
+ if (!preemptable)
+ {
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_OUT_OF_RANGE;
+ }
+
+ return(retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Sema_Clear
+****************************************************************************//**
+*
+* This functions tries to releases a semaphore.
+*
+* It first acquires the IPC channel that is used for all the semaphores, clears
+* the semaphore if it is set, then releases the IPC channel used for the
+* semaphores.
+*
+* \param semaNumber
+* The index of the semaphore to release.
+*
+* \param preemptable
+* When this parameter is enabled the function can be preempted by another
+* task or other forms of context switching in an RTOS environment.
+*
+* \note
+* If <b>preemptable</b> is enabled (true), the user must ensure that there are
+* no deadlocks in the system, which can be caused by an interrupt that occurs
+* after the IPC channel is locked. Unless the user is ready to handle IPC
+* channel locks correctly at the application level, set <b>preemptable</b> to
+* false.
+*
+* \return Status of the operation
+* \retval CY_IPC_SEMA_SUCCESS: The semaphore was cleared successfully
+* \retval CY_IPC_SEMA_NOT_ACQUIRED: The semaphore was already cleared
+* \retval CY_IPC_SEMA_LOCKED: The semaphore channel was semaphored or busy
+* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Sema_Clear
+*
+*******************************************************************************/
+cy_en_ipcsema_status_t Cy_IPC_Sema_Clear(uint32_t semaNumber, bool preemptable)
+{
+ uint32_t semaIndex;
+ uint32_t semaMask;
+ uint32_t interruptState = 0ul;
+
+ cy_stc_ipc_sema_t *semaStruct;
+ cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_LOCKED;
+
+ /* Get pointer to structure */
+ semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct);
+
+ if (semaNumber < semaStruct->maxSema)
+ {
+ semaIndex = semaNumber / CY_IPC_SEMA_PER_WORD;
+ semaMask = (uint32_t)(1ul << (semaNumber - (semaIndex * CY_IPC_SEMA_PER_WORD) ));
+
+ if (!preemptable)
+ {
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ }
+
+ /* Check to make sure the IPC channel is released
+ If so, check if specific channel can be locked. */
+ if(CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire (cy_semaIpcStruct))
+ {
+ if((semaStruct->arrayPtr[semaIndex] & semaMask) != 0ul)
+ {
+ semaStruct->arrayPtr[semaIndex] &= ~semaMask;
+ retStatus = CY_IPC_SEMA_SUCCESS;
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_NOT_ACQUIRED;
+ }
+
+ /* Release, but do not trigger a release event */
+ (void) Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION);
+ }
+
+ if (!preemptable)
+ {
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_OUT_OF_RANGE;
+ }
+ return(retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Sema_Status
+****************************************************************************//**
+*
+* This function returns the status of the semaphore.
+*
+* \param semaNumber
+* The index of the semaphore to return status.
+*
+* \return Status of the operation
+* \retval CY_IPC_SEMA_STATUS_LOCKED: The semaphore is in the set state.
+* \retval CY_IPC_SEMA_STATUS_UNLOCKED: The semaphore is in the cleared state.
+* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Sema_Status
+*
+*******************************************************************************/
+cy_en_ipcsema_status_t Cy_IPC_Sema_Status(uint32_t semaNumber)
+{
+ cy_en_ipcsema_status_t retStatus;
+ uint32_t semaIndex;
+ uint32_t semaMask;
+ cy_stc_ipc_sema_t *semaStruct;
+
+ /* Get pointer to structure */
+ semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct);
+
+ if (semaNumber < semaStruct->maxSema)
+ {
+ /* Get the index into the semaphore array and calculate the mask */
+ semaIndex = semaNumber / CY_IPC_SEMA_PER_WORD;
+ semaMask = (uint32_t)(1ul << (semaNumber - (semaIndex * CY_IPC_SEMA_PER_WORD) ));
+
+ if((semaStruct->arrayPtr[semaIndex] & semaMask) != 0ul)
+ {
+ retStatus = CY_IPC_SEMA_STATUS_LOCKED;
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_STATUS_UNLOCKED;
+ }
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_OUT_OF_RANGE;
+ }
+ return(retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Sema_GetMaxSems
+****************************************************************************//**
+*
+* This function returns the number of semaphores in the semaphores subsystem.
+*
+* \return
+* Returns the semaphores quantity.
+*
+* \funcusage
+* \snippet ipc/snippet/main.c snippet_Cy_IPC_Sema_GetMaxSems
+*
+*******************************************************************************/
+uint32_t Cy_IPC_Sema_GetMaxSems(void)
+{
+ cy_stc_ipc_sema_t *semaStruct;
+
+ /* Get pointer to structure */
+ semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct);
+
+ return (semaStruct->maxSema);
+}
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_prot.c b/platform/ext/target/psoc64/Native_Driver/source/cy_prot.c
new file mode 100644
index 0000000000..4731fa7402
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_prot.c
@@ -0,0 +1,2812 @@
+/***************************************************************************//**
+* \file cy_prot.c
+* \version 1.30.1
+*
+* \brief
+* Provides an API implementation of the Protection Unit driver
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_prot.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+static bool Prot_IsSmpuStructDisabled(uint32_t smpuStcIndex);
+static bool Prot_IsPpuProgStructDisabled(uint32_t ppuStcIndex);
+static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t pcMask,
+ cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure);
+
+/* Define to enable all attributes for SMPU slave structure */
+#define PROT_SMPU_STRUCT_ATT0_ENABLE_ALL_MASK (PROT_SMPU_SMPU_STRUCT_ATT0_UR_Msk | \
+ PROT_SMPU_SMPU_STRUCT_ATT0_UW_Msk | \
+ PROT_SMPU_SMPU_STRUCT_ATT0_UX_Msk | \
+ PROT_SMPU_SMPU_STRUCT_ATT0_PR_Msk | \
+ PROT_SMPU_SMPU_STRUCT_ATT0_PW_Msk | \
+ PROT_SMPU_SMPU_STRUCT_ATT0_PX_Msk | \
+ PROT_SMPU_SMPU_STRUCT_ATT0_NS_Msk)
+
+ /* Define to enable all attributes for programmable PPU slave structure */
+#define PROT_PERI_PPU_PR_ATT0_ENABLE_ALL_MASK (PERI_PPU_PR_ATT0_UR_Msk | \
+ PERI_PPU_PR_ATT0_UW_Msk | \
+ PERI_PPU_PR_ATT0_UX_Msk | \
+ PERI_PPU_PR_ATT0_PR_Msk | \
+ PERI_PPU_PR_ATT0_PW_Msk | \
+ PERI_PPU_PR_ATT0_PX_Msk | \
+ PERI_PPU_PR_ATT0_NS_Msk)
+
+#define PROT_PERI_PPU_PROG_PC1_PC3_MASK (0xffffffe0UL) /* PC1 - PC3 bits mask */
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigBusMaster
+****************************************************************************//**
+*
+* Configures the allowed protection contexts, security (secure/non-secure)
+* and privilege level of the bus transaction created by the specified master.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param busMaster
+* Indicates which master needs to be configured. Refer to the CPUSS_MS_ID_X
+* defines in the device config header file.
+*
+* \param privileged
+* Boolean to define the privilege level of all subsequent bus transfers.
+* True - privileged, False - not privileged.
+* Note that this is an inherited value. If not inherited, then this bit will
+* be used.
+*
+* \param secure
+* Security setting for the master. True - Secure, False - Not secure.
+*
+* \param pcMask
+* This is a 16 bit value of the allowed contexts, it is an OR'ed (|) field of the
+* provided defines in cy_prot.h. For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4)
+* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15.
+* But each device has its own number of available protection contexts.
+* That number is defined by PERI_PC_NR in the config file.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The function completed successfully.
+* CY_PROT_FAILURE | The resource is locked.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigBusMaster
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool privileged, bool secure, uint32_t pcMask)
+{
+ cy_en_prot_status_t status = CY_PROT_SUCCESS;
+ uint32_t regVal;
+ volatile uint32_t *addrMsCtl; /* addrMsCtl is pointer to a register that is volatile by
+ * nature as can be changed outside of firmware control.
+ */
+
+ CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster));
+ CY_ASSERT_L2(CY_PROT_IS_PC_MASK_VALID(pcMask));
+
+ /* Get the address of Master x protection context control register (MSx_CTL) */
+ addrMsCtl = (uint32_t *)(CY_PROT_BASE + (uint32_t)((uint32_t)busMaster << CY_PROT_MSX_CTL_SHIFT));
+
+ /* Get bitfields for MSx_CTL */
+ regVal = _VAL2FLD(PROT_SMPU_MS0_CTL_NS, !secure) /* Security setting */
+ | _VAL2FLD(PROT_SMPU_MS0_CTL_P, privileged) /* Privileged setting */
+ | _VAL2FLD(PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1, pcMask); /* Protection context mask */
+
+ /* Set the value of MSx_CTL */
+ *addrMsCtl = regVal;
+
+ /* Check if the MSx_CTL register is successfully updated with the new register value.
+ * The register will not be updated for the invalid master-protection context.
+ */
+ status = (*addrMsCtl != regVal) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_SetActivePC
+****************************************************************************//**
+*
+* Sets the current/active protection context of the specified bus master.
+*
+* Allowed PC values are 1-15. If this value is not inherited from another bus
+* master, the value set through this function is used.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param busMaster
+* The bus master to configure. Refer to the CPUSS_MS_ID_X defines in the device
+* config header file.
+*
+* \param pc
+* Active protection context of the specified master \ref cy_en_prot_pc_t.
+* \note that only those protection contexts allowed by the pcMask (which was
+* configured in \ref Cy_Prot_ConfigBusMaster) will take effect.
+* \note The function accepts pcMask values from CY_PROT_PC1 to CY_PROT_PC15.
+* But each device has its own number of available protection contexts.
+* That number is defined by PERI_PC_NR in the config file.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The function completed successfully.
+* CY_PROT_FAILURE | The resource is locked.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_SetActivePC
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc)
+{
+ cy_en_prot_status_t status;
+
+ CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster));
+ CY_ASSERT_L2(CY_PROT_IS_PC_VALID(pc));
+
+ PROT_MPU_MS_CTL(busMaster) = _VAL2FLD(PROT_MPU_MS_CTL_PC, pc) | _VAL2FLD(PROT_MPU_MS_CTL_PC_SAVED, pc);
+ status = (_FLD2VAL(PROT_MPU_MS_CTL_PC, PROT_MPU_MS_CTL(busMaster)) != pc) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_GetActivePC
+****************************************************************************//**
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* Returns the active protection context of a master.
+*
+* \param busMaster
+* The bus master, whose protection context is being read. Refer to the
+* CPUSS_MS_ID_X defines in the device config header file.
+*
+* \return
+* Active protection context of the master \ref cy_en_prot_pc_t.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_SetActivePC
+*
+*******************************************************************************/
+uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster)
+{
+
+ CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster));
+
+ return ((uint32_t)_FLD2VAL(PROT_MPU_MS_CTL_PC, PROT_MPU_MS_CTL(busMaster)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigMpuStruct
+****************************************************************************//**
+*
+* This function configures a memory protection unit (MPU) struct with its
+* protection attributes.
+*
+* The protection structs act like the gatekeepers for a master's accesses to
+* memory, allowing only the permitted transactions to go through.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param base
+* The base address for the MPU struct being configured.
+*
+* \param config
+* Initialization structure containing all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The MPU struct was configured.
+* CY_PROT_FAILURE | Configuration failed due to a protection violation.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigMpuStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, const cy_stc_mpu_cfg_t* config)
+{
+ cy_en_prot_status_t status;
+ uint32_t addrReg;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_MPU_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_MPU_PERM_VALID(config->privPermission));
+ CY_ASSERT_L3(CY_PROT_IS_REGION_SIZE_VALID(config->regionSize));
+
+ addrReg = _VAL2FLD(PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE, config->subregions)
+ | _VAL2FLD(PROT_MPU_MPU_STRUCT_ADDR_ADDR24, (uint32_t)((uint32_t)config->address >> CY_PROT_ADDR_SHIFT));
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_NS, !(config->secure))
+ | _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE, config->regionSize);
+ PROT_MPU_MPU_STRUCT_ATT(base) = attReg;
+ PROT_MPU_MPU_STRUCT_ADDR(base) = addrReg;
+ status = ((PROT_MPU_MPU_STRUCT_ADDR(base) != addrReg) || (PROT_MPU_MPU_STRUCT_ATT(base) != attReg)) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnableMpuStruct
+****************************************************************************//**
+*
+* Enables the MPU struct, which allows the MPU protection attributes to
+* take effect.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param base
+* The base address of the MPU struct being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The MPU struct was enabled.
+* CY_PROT_FAILURE | The MPU struct is disabled and possibly locked.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_EnableMpuStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ CY_ASSERT_L1(NULL != base);
+
+ PROT_MPU_MPU_STRUCT_ATT(base) |= _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PROT_MPU_MPU_STRUCT_ATT_ENABLED, PROT_MPU_MPU_STRUCT_ATT(base)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisableMpuStruct
+****************************************************************************//**
+*
+* Disables the MPU struct, which prevents the MPU protection attributes
+* from taking effect.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param base
+* The base address of the MPU struct being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The MPU struct was disabled.
+* CY_PROT_FAILURE | The MPU struct is enabled and possibly locked.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisableMpuStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ CY_ASSERT_L1(NULL != base);
+
+ PROT_MPU_MPU_STRUCT_ATT(base) &= ~_VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PROT_MPU_MPU_STRUCT_ATT_ENABLED, PROT_MPU_MPU_STRUCT_ATT(base)) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigSmpuMasterStruct
+****************************************************************************//**
+*
+* Configures a Shared Memory Protection Unit (SMPU) master protection
+* struct with its protection attributes.
+*
+* This function configures the master struct governing the corresponding slave
+* struct pair. It is a mechanism to protect the slave SMPU struct. Since the
+* memory location of the slave struct is known, the address, regionSize and
+* subregions of the configuration struct are not applicable.
+*
+* Note that only the user/privileged write permissions are configurable. The
+* read and execute permissions are read-only and cannot be configured.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param base
+* The register base address of the protection struct being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | SMPU master struct was successfully configured.
+* CY_PROT_FAILURE | The resource is locked.
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigSmpuMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config)
+{
+ cy_en_prot_status_t status;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L2(CY_PROT_IS_PC_MASK_VALID(config->pcMask));
+ CY_ASSERT_L3(CY_PROT_IS_SMPU_MS_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_SMPU_MS_PERM_VALID(config->privPermission));
+
+ if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR1 is read only. Only configure ATT1 */
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_NS, !(config->secure))
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only for master structs */
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_SMPU_ATT1_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ PROT_SMPU_SMPU_STRUCT_ATT1(base) = attReg;
+ status = ((PROT_SMPU_SMPU_STRUCT_ATT1(base) & CY_PROT_SMPU_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigSmpuSlaveStruct
+****************************************************************************//**
+*
+* Configures a Shared Memory Protection Unit (SMPU) slave protection
+* struct with its protection attributes.
+*
+* This function configures the slave struct of an SMPU pair, which can protect
+* any memory region in a device from invalid bus master accesses.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param base
+* The register base address of the protection structure being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | SMPU slave struct was successfully configured.
+* CY_PROT_FAILURE | The resource is locked.
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigSmpuSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config)
+{
+ cy_en_prot_status_t status = CY_PROT_SUCCESS;
+ uint32_t addrReg;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L2(CY_PROT_IS_PC_MASK_VALID(config->pcMask));
+ CY_ASSERT_L3(CY_PROT_IS_SMPU_SL_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_SMPU_SL_PERM_VALID(config->privPermission));
+ CY_ASSERT_L3(CY_PROT_IS_REGION_SIZE_VALID(config->regionSize));
+
+ if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ addrReg= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE, config->subregions)
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24, (uint32_t)((uint32_t)config->address >> CY_PROT_ADDR_SHIFT));
+ attReg= ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_NS, !(config->secure))
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1, config->pcMask)
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE, config->regionSize)
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH, config->pcMatch);
+ PROT_SMPU_SMPU_STRUCT_ATT0(base) = attReg;
+ PROT_SMPU_SMPU_STRUCT_ADDR0(base) = addrReg;
+ status = ((PROT_SMPU_SMPU_STRUCT_ADDR0(base) != addrReg) || ((PROT_SMPU_SMPU_STRUCT_ATT0(base) & CY_PROT_SMPU_ATT0_MASK) != attReg))
+ ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnableSmpuMasterStruct
+****************************************************************************//**
+*
+* Enables the Master SMPU structure.
+*
+* This is an SMPU master struct enable function. The SMPU protection settings
+* will take effect after successful completion of this function call.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was enabled.
+* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_EnableSmpuMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ CY_ASSERT_L1(NULL != base);
+
+ PROT_SMPU_SMPU_STRUCT_ATT1(base) |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, PROT_SMPU_SMPU_STRUCT_ATT1(base)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisableSmpuMasterStruct
+****************************************************************************//**
+*
+* Disables the Master SMPU structure.
+*
+* This is an SMPU master struct disable function. The SMPU protection settings
+* will seize to take effect after successful completion of this function call.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was disabled.
+* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisableSmpuMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ CY_ASSERT_L1(NULL != base);
+
+ PROT_SMPU_SMPU_STRUCT_ATT1(base) &= ~_VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, PROT_SMPU_SMPU_STRUCT_ATT1(base)) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnableSmpuSlaveStruct
+****************************************************************************//**
+*
+* Enables the Slave SMPU structure.
+*
+* This is an SMPU slave struct enable function. The SMPU protection settings
+* will take effect after successful completion of this function call.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was enabled.
+* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_EnableSmpuSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ CY_ASSERT_L1(NULL != base);
+
+ PROT_SMPU_SMPU_STRUCT_ATT0(base) |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, PROT_SMPU_SMPU_STRUCT_ATT0(base)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisableSmpuSlaveStruct
+****************************************************************************//**
+*
+* Disables the Slave SMPU structure.
+*
+* This is an SMPU slave struct disable function. The SMPU protection settings
+* will seize to take effect after successful completion of this function call.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was disabled.
+* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisableSmpuSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ CY_ASSERT_L1(NULL != base);
+
+ PROT_SMPU_SMPU_STRUCT_ATT0(base) &= ~_VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, PROT_SMPU_SMPU_STRUCT_ATT0(base)) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_GetSmpuStruct
+****************************************************************************//**
+*
+* Functions returns a pointer of the requested unused SMPU structure. It
+* searches the SMPU structures until it finds one that both the slave and master
+* sections are disabled. After an available structure is located, function
+* enables the slave structure and set the ATT0[7:0] bits to 0xFF, to make sure
+* that a subsequent call will not see this as an available (unused) SMPU.
+*
+* It is up to the user to implement, if needed, a system in which a semaphore
+* will lock-out all but one CPU from calling this function at once.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param base
+* The base address for the SMPU structure returned if an unused structure was
+* found. If an empty structure was not found, the returned pointer is NULL.
+*
+* \param reqMode
+* This parameter (request mode) selects how the user wants to select a SMPU
+* structure.
+*
+* reqMode | Description
+* --------------------------| -----------------------------
+* CY_PROT_REQMODE_HIGHPRIOR | Return the SMPU structure with the highest priority.
+* CY_PROT_REQMODE_LOWPRIOR | Return the SMPU structure with the lowest priority.
+* CY_PROT_REQMODE_INDEX | Return the SMPU structure with the specific index.
+*
+* \param smpuIndex
+* This is the index of the requested SMPU structure. It is only used if the
+* request mode is reqMode = CY_PROT_REQMODE_INDEX.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ----------------------| ---------------------------------------
+* CY_PROT_SUCCESS | The Slave PU struct was disabled.
+* CY_PROT_FAILURE | The Master or Slave SMPU struct is disabled and possibly locked.
+* CY_PROT_UNAVAILABLE | The requested structure in use or there were no unused structures.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_GetSmpuStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base,
+ cy_en_prot_req_mode_t reqMode, uint32_t smpuIndex)
+{
+ CY_ASSERT_L3(CY_PROT_IS_SMPU_REQ_MODE_VALID(reqMode));
+ CY_ASSERT_L2(CY_PROT_IS_SMPU_IDX_VALID(smpuIndex));
+
+ cy_en_prot_status_t status = CY_PROT_UNAVAILABLE;
+ int32_t stcIdx = (int32_t)smpuIndex;
+
+ *base = NULL;
+
+ switch (reqMode)
+ {
+ /* The SMPU priority goes from PROT_SMPU_STRUCT_HIGHEST_PR
+ * (highest priority) to 0 (lowest priority)
+ */
+ case CY_PROT_REQMODE_HIGHPRIOR:
+
+ stcIdx = PROT_SMPU_STRUCT_WTH_HIGHEST_PR;
+ do
+ {
+ if (Prot_IsSmpuStructDisabled((uint32_t)stcIdx))
+ {
+ status = CY_PROT_SUCCESS;
+ }
+ else
+ {
+ --stcIdx;
+ }
+ } while ((stcIdx >= 0) && (CY_PROT_SUCCESS != status));
+ break;
+
+ case CY_PROT_REQMODE_LOWPRIOR:
+ stcIdx = 0;
+ do
+ {
+ if (Prot_IsSmpuStructDisabled((uint32_t)stcIdx))
+ {
+ status = CY_PROT_SUCCESS;
+ }
+ else
+ {
+ ++stcIdx;
+ }
+ } while ((stcIdx <= PROT_SMPU_STRUCT_WTH_HIGHEST_PR) && (CY_PROT_SUCCESS != status));
+ break;
+
+ case CY_PROT_REQMODE_INDEX:
+ if (Prot_IsSmpuStructDisabled((uint32_t)stcIdx))
+ {
+ status = CY_PROT_SUCCESS;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Proceed if required structure is found */
+ if (CY_PROT_SUCCESS == status)
+ {
+ /* Enable Slave SMPU struct */
+ PROT_SMPU_SMPU_STRUCT_IDX_ATT0(stcIdx) |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+
+ status =
+ (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, PROT_SMPU_SMPU_STRUCT_IDX_ATT0(stcIdx)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ /* Enable all attributes only if Slave struct was enabled */
+ if (CY_PROT_SUCCESS == status)
+ {
+ *base = (PROT_SMPU_SMPU_STRUCT_Type* ) PROT_SMPU_SMPU_STRUCT_IDX(stcIdx);
+ PROT_SMPU_SMPU_STRUCT_IDX_ATT0(stcIdx) |= PROT_SMPU_STRUCT_ATT0_ENABLE_ALL_MASK;
+ }
+ }
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Prot_ConfigPpuAtt
+********************************************************************************
+*
+* An internal function to hold the common code for
+* Cy_Prot_ConfigPpu[Prog/Fixed][Master/Slave]Att API functions
+*
+* \note This function is applicable for CPUSS ver_2 only.
+*
+* \param reg
+* The register to update attributes in.
+*
+* \param pcMask
+* The protection context mask. This is a 16-bit value of the allowed contexts.
+* It is an OR'ed (|) field of the * provided defines in cy_prot.h.
+* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4).
+* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK5.
+* But each device has its own number of available protection contexts.
+* That number is defined by PERI_PC_NR in the config file.
+*
+* \param userPermission
+* The user permissions for the region.
+*
+* \param privPermission
+* The privileged permissions for the region.
+*
+* \param secure
+* Non Secure = false, Secure = true
+*
+* \return
+* The status of the function call.
+*
+* Status | Description
+* ----------------------| ---------------------------------------
+* CY_PROT_SUCCESS | The attributes were set up.
+* CY_PROT_FAILURE | The attributes were not set up because the structure is possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+*******************************************************************************/
+static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t pcMask,
+ cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ if (!CY_PERI_V1)
+ {
+ uint32_t tmpMask = (uint32_t)pcMask << CY_PROT_PCMASK_CHECK;
+ uint32_t attReg;
+ uint32_t regIdx;
+ uint32_t fldIdx;
+
+ status = CY_PROT_SUCCESS;
+
+ /* Populate the ATT values */
+ for(regIdx = 0U; regIdx < CY_PROT_ATT_REGS_MAX; regIdx++)
+ {
+ if (0UL == tmpMask)
+ {
+ break;
+ }
+
+ /* Get the attributes register value */
+ attReg = reg[regIdx];
+
+ for(fldIdx = 0UL; fldIdx < CY_PROT_ATT_PC_MAX; fldIdx++)
+ {
+ if((tmpMask & CY_PROT_PCMASK_CHECK) == CY_PROT_STRUCT_ENABLE)
+ {
+ /* Reset the bitfield for the PCx attributes */
+ attReg &= ~((_VAL2FLD(CY_PROT_ATT_PERI_USER_PERM, CY_PROT_PERM_RW) |
+ _VAL2FLD(CY_PROT_ATT_PERI_PRIV_PERM, CY_PROT_PERM_RW) |
+ _BOOL2FLD(PERI_MS_PPU_PR_V2_MS_ATT0_PC0_NS, true)) <<
+ (PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UR_Pos * fldIdx));
+
+ /* Set the bitfield for the PCx attributes */
+ attReg |= (_VAL2FLD(CY_PROT_ATT_PERI_USER_PERM, userPermission) |
+ _VAL2FLD(CY_PROT_ATT_PERI_PRIV_PERM, privPermission) |
+ _BOOL2FLD(PERI_MS_PPU_PR_V2_MS_ATT0_PC0_NS, !secure)) <<
+ (PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UR_Pos * fldIdx);
+ }
+ tmpMask = tmpMask >> CY_PROT_PCMASK_CHECK;
+ }
+
+ /* Update the attributes register */
+ reg[regIdx] = attReg;
+
+ /* Check the result */
+ if ((0UL == regIdx) &&
+ ((reg[regIdx] & PROT_PERI_PPU_PROG_PC1_PC3_MASK) != (attReg & PROT_PERI_PPU_PROG_PC1_PC3_MASK)))
+ {
+ status = CY_PROT_FAILURE;
+ }
+ else if (reg[regIdx] != attReg)
+ {
+ status = CY_PROT_FAILURE;
+ }
+ else
+ {
+ /* CY_PROT_SUCCESS */
+ }
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuProgMasterAtt
+****************************************************************************//**
+*
+* Configures the protection-structure attributes of the
+* Programmable Peripheral Protection Unit (PPU PROG) master.
+*
+* This function configures the master structure governing the corresponding slave
+* structure pair. It is a mechanism to protect the slave PPU PROG structure.
+* The memory location of the slave structure is known, so the address, regionSize, and
+* sub-regions of the configuration structure are not applicable.
+*
+* \note This function is applicable for CPUSS ver_2 only.
+*
+* \param base
+* The register base address of the protection structure is being configured.
+*
+* \param pcMask
+* The protection context mask. This is a 16-bit value of the allowed contexts,
+* it is an OR'ed (|) field of the * provided defines in cy_prot.h.
+* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4).
+* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15.
+* But each device has its own number of available protection contexts.
+* That number is defined by PERI_PC_NR in the config file.
+*
+* \param userPermission
+* The user permission setting. The CY_PROT_PERM_R or CY_PROT_PERM_RW values
+* are valid for the master.
+*
+* \param privPermission
+* The privileged permission setting. CY_PROT_PERM_R or CY_PROT_PERM_RW values
+* are valid for the master.
+*
+* \param secure
+* The secure flag.
+*
+* \return
+* The status of the function call.
+*
+* Status | Description
+* ----------------------| ---------------------------------------
+* CY_PROT_SUCCESS | The attributes were set up.
+* CY_PROT_FAILURE | The attributes were not set up because the structure is possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \note Only the user's/privileged Write permissions are configurable. The
+* Read permissions are read-only and cannot be configured.
+*
+* \note PC0 accesses are read-only and are always enabled.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuProgMasterAtt
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterAtt(PERI_MS_PPU_PR_Type* base, uint16_t pcMask,
+ cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure)
+{
+ /* The parameter checks */
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_PROG_MS_PERM_VALID(userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_PROG_MS_PERM_VALID(privPermission));
+
+ return (Prot_ConfigPpuAtt(PERI_MS_PPU_PR_MS_ATT(base), pcMask, userPermission, privPermission, secure));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuProgSlaveAddr
+****************************************************************************//**
+*
+* Configures the protection-structure address settings of the
+* Programmable Peripheral Protection Unit (PPU PROG) slave.
+*
+* This function configures the slave structure of the PPU PROG pair, which can
+* protect any peripheral memory region in a device from an invalid bus-master
+* access.
+*
+* \note This function is applicable for CPUSS ver_2 only.
+*
+* \param base
+* The register base address of the protection structure is being configured.
+*
+* \param address
+* The address.
+*
+* \param regionSize
+* The region size.
+*
+* \return
+* The status of the function call.
+*
+* Status | Description
+* ----------------------| ---------------------------------------
+* CY_PROT_SUCCESS | The address settings were set up.
+* CY_PROT_FAILURE | The address settings were not set up because the structure is possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \note PC0 accesses are Read-only and are always enabled.
+*
+* \funcusage
+* \ref Cy_Prot_ConfigPpuProgSlaveAtt
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAddr(PERI_MS_PPU_PR_Type* base, uint32_t address,
+ cy_en_prot_size_t regionSize)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ /* The parameter checks */
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_PPU_V2_SIZE_VALID(regionSize));
+
+ if (!CY_PERI_V1)
+ {
+ PERI_MS_PPU_PR_SL_ADDR(base) = address & PERI_MS_PPU_PR_V2_SL_ADDR_ADDR30_Msk;
+ PERI_MS_PPU_PR_SL_SIZE(base) = _CLR_SET_FLD32U((PERI_MS_PPU_PR_SL_SIZE(base)), PERI_MS_PPU_PR_V2_SL_SIZE_REGION_SIZE, regionSize);
+
+ status = ((PERI_MS_PPU_PR_SL_ADDR(base) != (address & PERI_MS_PPU_PR_V2_SL_ADDR_ADDR30_Msk)) ||
+ (_FLD2VAL(PERI_MS_PPU_PR_V2_SL_SIZE_REGION_SIZE, PERI_MS_PPU_PR_SL_SIZE(base)) != (uint32_t)regionSize)) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuProgSlaveAtt
+****************************************************************************//**
+*
+* Configures the protection structure with its protection attributes of the
+* Programmable Peripheral Protection Unit (PPU PROG) slave.
+*
+* This function configures the slave structure of the PPU PROG pair, which can
+* protect any peripheral memory region in a device from invalid bus-master
+* access.
+*
+* \note This function is applicable for CPUSS ver_2 only.
+*
+* \param base
+* The register base address of the protection structure is being configured.
+*
+* \param pcMask
+* The protection context mask. This is a 16-bit value of the allowed contexts,
+* it is an OR'ed (|) field of the * provided defines in cy_prot.h.
+* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4).
+* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15.
+* But each device has its own number of available protection contexts.
+* That number is defined by PERI_PC_NR in the config file.
+*
+* \param userPermission
+* The user permission setting.
+*
+* \param privPermission
+* The privileged permission setting.
+*
+* \param secure
+* The secure flag.
+*
+* \return
+* The status of the function call.
+*
+* Status | Description
+* ----------------------| ---------------------------------------
+* CY_PROT_SUCCESS | The attributes were set up.
+* CY_PROT_FAILURE | The attributes were not set up because the structure is possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \note PC0 accesses are read-only and are always enabled.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuProgSlaveAtt
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAtt(PERI_MS_PPU_PR_Type* base, uint16_t pcMask,
+ cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure)
+{
+ /* The parameter checks */
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_PROG_SL_PERM_VALID(userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_PROG_SL_PERM_VALID(privPermission));
+
+ return (Prot_ConfigPpuAtt(PERI_MS_PPU_PR_SL_ATT(base), pcMask, userPermission, privPermission, secure));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuProgSlaveRegion
+****************************************************************************//**
+*
+* Enables the Slave PPU PROG structure.
+*
+* This is the PPU PROG slave-structure enable function. The PPU PROG protection
+* settings will take effect after a successful completion of this function call.
+*
+* \note This function is applicable for CPUSS ver_2 only.
+*
+* \param base
+* The base address for the protection unit structure is being configured.
+*
+* \return
+* The status of the function call.
+*
+* Status | Description
+* ----------------------| ---------------------------------------
+* CY_PROT_SUCCESS | The structure was enabled.
+* CY_PROT_FAILURE | The structure is disabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \ref Cy_Prot_ConfigPpuProgSlaveAtt
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (!CY_PERI_V1)
+ {
+ PERI_MS_PPU_PR_SL_SIZE(base) =
+ _CLR_SET_FLD32U((PERI_MS_PPU_PR_SL_SIZE(base)), PERI_MS_PPU_PR_V2_SL_SIZE_VALID, CY_PROT_STRUCT_ENABLE);
+
+ status = (_FLD2VAL(PERI_MS_PPU_PR_V2_SL_SIZE_VALID, PERI_MS_PPU_PR_SL_SIZE(base)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuProgSlaveRegion
+****************************************************************************//**
+*
+* Disables the Slave PPU PROG structure.
+*
+* This is the PPU PROG slave-structure disable function. The PPU PROG protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \note This function is applicable for CPUSS ver_2 only.
+*
+* \param base
+* The base address for the protection unit structure is being configured.
+*
+* \return
+* The status of the function call.
+*
+* Status | Description
+* ----------------------| ---------------------------------------
+* CY_PROT_SUCCESS | The slave PPU PROG structure was disabled.
+* CY_PROT_FAILURE | The structure is enabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuProgSlaveRegion
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (!CY_PERI_V1)
+ {
+ PERI_MS_PPU_PR_SL_SIZE(base) =
+ _CLR_SET_FLD32U((PERI_MS_PPU_PR_SL_SIZE(base)), PERI_MS_PPU_PR_V2_SL_SIZE_VALID, CY_PROT_STRUCT_DISABLE);
+
+ status = (_FLD2VAL(PERI_MS_PPU_PR_V2_SL_SIZE_VALID, PERI_MS_PPU_PR_SL_SIZE(base)) != CY_PROT_STRUCT_DISABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedMasterAtt
+****************************************************************************//**
+*
+* Configures the protection structure with its protection attributes of the
+* Fixed Peripheral Protection Unit (PPU FIXED) master.
+*
+* This function configures the master structure governing the corresponding slave
+* structure pair. It is a mechanism to protect the slave PPU FIXED structure.
+* The memory location of the slave structure is known, so the address, region size
+* and sub-regions of the configuration structure are not applicable.
+*
+* \note This function is applicable for CPUSS ver_2 only.
+*
+* \param base
+* The register base address of the protection structure is being configured.
+*
+* \param pcMask
+* The protection context mask. This is a 16-bit value of the allowed contexts,
+* it is an OR'ed (|) field of the * provided defines in cy_prot.h.
+* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4).
+* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15.
+* But each device has its own number of available protection contexts.
+* That number is defined by PERI_PC_NR in the config file.
+*
+* \param userPermission
+* The user permission setting. The CY_PROT_PERM_R or CY_PROT_PERM_RW values
+* are valid for the master.
+*
+* \param privPermission
+* The privileged permission setting. The CY_PROT_PERM_R or CY_PROT_PERM_RW values
+* are valid for the master.
+*
+* \param secure
+* The secure flag.
+*
+* \return
+* The status of the function call.
+*
+* Status | Description
+* ----------------------| ---------------------------------------
+* CY_PROT_SUCCESS | The attributes were set up.
+* CY_PROT_FAILURE | The attributes were not setup and the structure is possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \note Only the user/privileged write permissions are configurable. The
+* read permissions are read-only and cannot be configured.
+*
+* \note PC0 accesses are read-only and are always enabled.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedMasterAtt
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedMasterAtt(PERI_MS_PPU_FX_Type* base, uint16_t pcMask,
+ cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure)
+{
+ /* The parameter checks */
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_MS_PERM_VALID(userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_MS_PERM_VALID(privPermission));
+
+ return (Prot_ConfigPpuAtt(PERI_MS_PPU_FX_MS_ATT(base), pcMask, userPermission, privPermission, secure));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedSlaveAtt
+****************************************************************************//**
+*
+* Configures the protection structure with its protection attributes of
+* the Fixed Peripheral Protection Unit (PPU FIXED) slave.
+*
+* This function configures the slave structure of the PPU FIXED pair, which can
+* protect any peripheral memory region in a device from invalid bus-master
+* access.
+*
+* \note This function is applicable for CPUSS ver_2 only.
+*
+* \param base
+* The register base address of the protection structure is being configured.
+*
+* \param pcMask
+* The protection context mask. This is a 16-bit value of the allowed contexts,
+* it is an OR'ed (|) field of the * provided defines in cy_prot.h.
+* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4).
+* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15.
+* But each device has its own number of available protection contexts.
+* That number is defined by PERI_PC_NR in the config file.
+*
+* \param userPermission
+* The user permission setting.
+*
+* \param privPermission
+* The privileged permission setting.
+*
+* \param secure
+* The secure flag.
+*
+* \return
+* The status of the function call.
+*
+* Status | Description
+* ----------------------| ---------------------------------------
+* CY_PROT_SUCCESS | The attributes were set up.
+* CY_PROT_FAILURE | The attributes were not setup and the structure is possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \note PC0 accesses are read-only and are always enabled.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedSlaveAtt
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlaveAtt(PERI_MS_PPU_FX_Type* base, uint16_t pcMask,
+ cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure)
+{
+ /* The parameter checks */
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(privPermission));
+
+ return (Prot_ConfigPpuAtt(PERI_MS_PPU_FX_SL_ATT(base), pcMask, userPermission, privPermission, secure));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuProgMasterStruct
+****************************************************************************//**
+*
+* Configures a Programmable Peripheral Protection Unit (PPU PROG) master
+* protection struct with its protection attributes.
+*
+* This function configures the master struct governing the corresponding slave
+* struct pair. It is a mechanism to protect the slave PPU PROG struct. Since
+* the memory location of the slave struct is known, the address, regionSize and
+* subregions of the configuration struct are not applicable.
+*
+* Note that only the user/privileged write permissions are configurable. The
+* read and execute permissions are read-only and cannot be configured.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The register base address of the protection struct being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU PROG master struct was successfully configured.
+* CY_PROT_FAILURE | The resource is locked.
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuProgMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_PROG_MS_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_PROG_MS_PERM_VALID(config->privPermission));
+
+ if (CY_PERI_V1)
+ {
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR1 is read only. Only configure ATT1 */
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_PPU_PR_ATT1_NS, !(config->secure))
+ | _VAL2FLD(PERI_PPU_PR_ATT1_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only for master structs */
+ | _VAL2FLD(PERI_PPU_PR_ATT1_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_PROG_ATT1_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ PERI_PPU_PR_ATT1(base) = attReg;
+ status = ((PERI_PPU_PR_ATT1(base) & CY_PROT_PPU_PROG_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuProgSlaveStruct
+****************************************************************************//**
+*
+* Configures a Programmable Peripheral Protection Unit (PPU PROG) slave
+* protection struct with its protection attributes.
+*
+* This function configures the slave struct of a PPU PROG pair, which can
+* protect any peripheral memory region in a device from invalid bus master
+* accesses.
+*
+* Note that the user/privileged execute accesses are read-only and are always
+* enabled.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The register base address of the protection structure being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU PROG slave struct was successfully configured.
+* CY_PROT_FAILURE | The resource is locked.
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuProgSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+ uint32_t addrReg;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_PROG_SL_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_PROG_SL_PERM_VALID(config->privPermission));
+ CY_ASSERT_L3(CY_PROT_IS_REGION_SIZE_VALID(config->regionSize));
+
+ if (CY_PERI_V1)
+ {
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ addrReg= _VAL2FLD(PERI_PPU_PR_ADDR0_SUBREGION_DISABLE, config->subregions)
+ | _VAL2FLD(PERI_PPU_PR_ADDR0_ADDR24, (uint32_t)((uint32_t)config->address >> CY_PROT_ADDR_SHIFT));
+ attReg= ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_PPU_PR_ATT0_NS, !(config->secure))
+ | _VAL2FLD(PERI_PPU_PR_ATT0_PC_MASK_15_TO_1, config->pcMask)
+ | _VAL2FLD(PERI_PPU_PR_ATT0_REGION_SIZE, config->regionSize)
+ | _VAL2FLD(PERI_PPU_PR_ATT0_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_PROG_ATT0_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ PERI_PPU_PR_ATT0(base) = attReg;
+ PERI_PPU_PR_ADDR0(base) = addrReg;
+ status = ((PERI_PPU_PR_ADDR0(base) != addrReg) || ((PERI_PPU_PR_ATT0(base) & CY_PROT_PPU_PROG_ATT0_MASK) != attReg))
+ ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuProgMasterStruct
+****************************************************************************//**
+*
+* Enables the Master PPU PROG structure.
+*
+* This is a PPU PROG master struct enable function. The PPU PROG protection
+* settings will take effect after successful completion of this function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was enabled.
+* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuProgMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (CY_PERI_V1)
+ {
+ PERI_PPU_PR_ATT1(base) |= _VAL2FLD(PERI_PPU_PR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_PR_ATT1_ENABLED, PERI_PPU_PR_ATT1(base)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuProgMasterStruct
+****************************************************************************//**
+*
+* Disables the Master PPU PROG structure.
+*
+* This is a PPU PROG master struct disable function. The PPU PROG protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was disabled.
+* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuProgMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (CY_PERI_V1)
+ {
+ PERI_PPU_PR_ATT1(base) &= ~_VAL2FLD(PERI_PPU_PR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_PR_ATT1_ENABLED, PERI_PPU_PR_ATT1(base)) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuProgSlaveStruct
+****************************************************************************//**
+*
+* Enables the Slave PPU PROG structure.
+*
+* This is a PPU PROG slave struct enable function. The PPU PROG protection
+* settings will take effect after successful completion of this function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was enabled.
+* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuProgSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (CY_PERI_V1)
+ {
+ PERI_PPU_PR_ATT0(base) |= _VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_PR_ATT0_ENABLED, PERI_PPU_PR_ATT0(base)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuProgSlaveStruct
+****************************************************************************//**
+*
+* Disables the Slave PPU PROG structure.
+*
+* This is a PPU PROG slave struct disable function. The PPU PROG protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was disabled.
+* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuProgSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (CY_PERI_V1)
+ {
+ PERI_PPU_PR_ATT0(base) &= ~_VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_PR_ATT0_ENABLED, PERI_PPU_PR_ATT0(base)) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_GetPpuProgStruct
+****************************************************************************//**
+*
+* Functions returns a pointer of the requested unused Programmable PPU
+* structure. Function searches the Programmable PPU structure until it finds
+* one that both the slave and master sections are disabled. After an available
+* structure is located, function enables the slave structure and enables all
+* attributes, to make sure that a subsequent call will not see this
+* as an available (unused) Programmable PPU.
+*
+* It is up to the user to implement, if needed, a system in which a semaphore
+* will lock-out all but one CPU from calling this function at once.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the Programmable PPU structure returned if an unused
+* structure was found. If an empty structure was not found, the returned
+* pointer is NULL.
+*
+* \param reqMode
+* This parameter (request mode) selects how the user wants to select a
+* Programmable PPU structure.
+*
+* reqMode | Description
+* --------------------------| -----------------------------
+* CY_PROT_REQMODE_HIGHPRIOR | Return the Programmable PPU structure with the highest priority.
+* CY_PROT_REQMODE_LOWPRIOR | Return the Programmable PPU structure with the lowest priority.
+* CY_PROT_REQMODE_INDEX | Return the Programmable PPU structure with the specific index.
+*
+* \param ppuProgIndex
+* This is the index of the requested Programmable PPU structure. It is only
+* used if the request mode is reqMode = CY_PROT_REQMODE_INDEX.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ----------------------| ---------------------------------------
+* CY_PROT_SUCCESS | The Slave PU struct was disabled.
+* CY_PROT_FAILURE | The Master or Slave Programmable PPU struct is disabled and possibly locked.
+* CY_PROT_UNAVAILABLE | The requested structure in use or there were no unused structures.
+* CY_PROT_INVALID_STATE | Function was called on unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_GetPpuProgStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_GetPpuProgStruct(PERI_PPU_PR_Type** base, cy_en_prot_req_mode_t reqMode, uint32_t ppuProgIndex)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ if (CY_PERI_V1)
+ {
+ CY_ASSERT_L3(CY_PROT_IS_PPU_PROG_REQ_MODE_VALID(reqMode));
+ CY_ASSERT_L2(CY_PROT_IS_PPU_PROG_IDX_VALID(ppuProgIndex));
+
+ status = CY_PROT_UNAVAILABLE;
+ int32_t stcIdx = (int32_t) ppuProgIndex;
+
+ *base = NULL;
+
+ switch (reqMode)
+ {
+ /* Programmed structures priority goes from 0 (highest) to
+ * PROT_PPU_PROG_STRUCT_WTH_LOWEST_PR (lowest)
+ */
+ case CY_PROT_REQMODE_LOWPRIOR:
+
+ stcIdx = PROT_PPU_PROG_STRUCT_WTH_LOWEST_PR;
+ do
+ {
+ if (Prot_IsPpuProgStructDisabled((uint32_t)stcIdx))
+ {
+ status = CY_PROT_SUCCESS;
+ }
+ else
+ {
+ --stcIdx;
+ }
+ } while ((stcIdx >= 0) && (CY_PROT_SUCCESS != status));
+ break;
+
+ /* Programmed structures priority goes from 0 (highest) to
+ * PROT_PPU_PROG_STRUCT_WTH_LOWEST_PR (lowest)
+ */
+ case CY_PROT_REQMODE_HIGHPRIOR:
+ stcIdx = 0;
+ do
+ {
+ if (Prot_IsPpuProgStructDisabled((uint32_t)stcIdx))
+ {
+ status = CY_PROT_SUCCESS;
+ }
+ else
+ {
+ ++stcIdx;
+ }
+ } while ((stcIdx <= PROT_PPU_PROG_STRUCT_WTH_LOWEST_PR) && (CY_PROT_SUCCESS != status));
+ break;
+
+ case CY_PROT_REQMODE_INDEX:
+
+ if (Prot_IsPpuProgStructDisabled((uint32_t)stcIdx))
+ {
+ status = CY_PROT_SUCCESS;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable Programmable PPU struct */
+ if (CY_PROT_SUCCESS == status)
+ {
+ PROT_PERI_PPU_PR_STRUCT_IDX_ATT0(stcIdx) |= _VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+
+ status =
+ (_FLD2VAL(PERI_PPU_PR_ATT0_ENABLED, PROT_PERI_PPU_PR_STRUCT_IDX_ATT0(stcIdx)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ /* Enable all attributes only if Slave struct was enabled */
+ if (CY_PROT_SUCCESS == status)
+ {
+ *base = (PERI_PPU_PR_Type*) PROT_PERI_PPU_PR_STRUCT_IDX(stcIdx);
+ PROT_PERI_PPU_PR_STRUCT_IDX_ATT0(stcIdx) |= PROT_PERI_PPU_PR_ATT0_ENABLE_ALL_MASK;
+ }
+ }
+ }
+
+ return status;
+}
+
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedGrMasterStruct
+****************************************************************************//**
+*
+* Configures a Fixed Peripheral Group Protection Unit (PPU GR) master
+* protection struct with its protection attributes.
+*
+* This function configures the master struct governing the corresponding slave
+* struct pair. It is a mechanism to protect the slave PPU GR struct. Since
+* the memory location of the slave struct is known, the address, regionSize and
+* subregions of the configuration struct are not applicable.
+*
+* Note that only the user/privileged write permissions are configurable. The
+* read and execute permissions are read-only and cannot be configured.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The register base address of the protection struct being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU GR master struct was successfully configured.
+* CY_PROT_FAILURE | The resource is locked.
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedGrMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->privPermission));
+
+ if (CY_PERI_V1)
+ {
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR1 is read only. Only configure ATT1 */
+ attReg = (((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK))
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_PPU_GR_ATT1_NS, !(config->secure))
+ | _VAL2FLD(PERI_PPU_GR_ATT1_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only for master structs */
+ | _VAL2FLD(PERI_PPU_GR_ATT1_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_GR_ATT1_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ PERI_PPU_GR_ATT1(base) = attReg;
+ status = ((PERI_PPU_GR_ATT1(base) & CY_PROT_PPU_GR_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedGrSlaveStruct
+****************************************************************************//**
+*
+* Configures a Fixed Peripheral Group Protection Unit (PPU GR) slave
+* protection struct with its protection attributes.
+*
+* This function configures the slave struct of a PPU GR pair, which can
+* protect an entire peripheral MMIO group from invalid bus master accesses.
+* Refer to the device Technical Reference manual for details on peripheral
+* MMIO grouping and which peripherals belong to which groups.
+*
+* Each fixed PPU GR is devoted to a defined MMIO group. Hence the address,
+* regionSize and subregions of the configuration struct are not applicable.
+*
+* Note that the user/privileged execute accesses are read-only and are always
+* enabled.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The register base address of the protection structure being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU GR slave struct was successfully configured.
+* CY_PROT_FAILURE | The resource is locked.
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedGrSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->privPermission));
+
+ if (CY_PERI_V1)
+ {
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR0 is read only. Only configure ATT0 */
+ attReg = (uint32_t)(((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK))
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_PPU_GR_ATT0_NS, !(config->secure))
+ | _VAL2FLD(PERI_PPU_GR_ATT0_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only */
+ | _VAL2FLD(PERI_PPU_GR_ATT0_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_GR_ATT0_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ PERI_PPU_GR_ATT0(base) = attReg;
+ status = ((PERI_PPU_GR_ATT0(base) & CY_PROT_PPU_GR_ATT0_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuFixedGrMasterStruct
+****************************************************************************//**
+*
+* Enables the Master PPU GR structure.
+*
+* This is a PPU GR master struct enable function. The PPU GR protection
+* settings will take effect after successful completion of this function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was enabled.
+* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuFixedGrMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (CY_PERI_V1)
+ {
+ PERI_PPU_GR_ATT1(base) |= _VAL2FLD(PERI_PPU_GR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_GR_ATT1_ENABLED, PERI_PPU_GR_ATT1(base)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuFixedGrMasterStruct
+****************************************************************************//**
+*
+* Disables the Master PPU GR structure.
+*
+* This is a PPU GR master struct disable function. The PPU GR protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was disabled.
+* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuFixedGrMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (CY_PERI_V1)
+ {
+ PERI_PPU_GR_ATT1(base) &= ~_VAL2FLD(PERI_PPU_GR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_GR_ATT1_ENABLED, PERI_PPU_GR_ATT1(base)) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuFixedGrSlaveStruct
+****************************************************************************//**
+*
+* Enables the Slave PPU GR structure.
+*
+* This is a PPU GR slave struct enable function. The PPU GR protection
+* settings will take effect after successful completion of this function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was enabled.
+* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuFixedGrSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (CY_PERI_V1)
+ {
+ PERI_PPU_GR_ATT0(base) |= _VAL2FLD(PERI_PPU_GR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_GR_ATT0_ENABLED, PERI_PPU_GR_ATT0(base)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuFixedGrSlaveStruct
+****************************************************************************//**
+*
+* Disables the Slave PPU GR structure.
+*
+* This is a PPU GR slave struct disable function. The PPU GR protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was disabled.
+* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuFixedGrSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (CY_PERI_V1)
+ {
+ PERI_PPU_GR_ATT0(base) &= ~_VAL2FLD(PERI_PPU_GR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_GR_ATT0_ENABLED, PERI_PPU_GR_ATT0(base)) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedSlMasterStruct
+****************************************************************************//**
+*
+* Configures a Fixed Peripheral Slave Protection Unit (PPU SL) master
+* protection struct with its protection attributes.
+*
+* This function configures the master struct governing the corresponding slave
+* struct pair. It is a mechanism to protect the slave PPU SL struct. Since
+* the memory location of the slave struct is known, the address, regionSize and
+* subregions of the configuration struct are not applicable.
+*
+* Note that only the user/privileged write permissions are configurable. The
+* read and execute permissions are read-only and cannot be configured.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The register base address of the protection struct being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU SL master struct was successfully configured.
+* CY_PROT_FAILURE | The resource is locked.
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedSlMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->privPermission));
+
+ if (CY_PERI_V1)
+ {
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR1 is read only. Only configure ATT1 */
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_GR_PPU_SL_ATT1_NS, !(config->secure))
+ | _VAL2FLD(PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only for master structs */
+ | _VAL2FLD(PERI_GR_PPU_SL_ATT1_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_SL_ATT1_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ PERI_GR_PPU_SL_ATT1(base) = attReg;
+ status = ((PERI_GR_PPU_SL_ATT1(base) & CY_PROT_PPU_SL_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedSlSlaveStruct
+****************************************************************************//**
+*
+* Configures a Fixed Peripheral Slave Protection Unit (PPU SL) slave
+* protection struct with its protection attributes.
+*
+* This function configures the slave struct of a PPU SL pair, which can
+* protect an entire peripheral slave instance from invalid bus master accesses.
+* For example, TCPWM0, TCPWM1, SCB0 and SCB1 etc.
+*
+* Each fixed PPU SL is devoted to a defined peripheral slave. Hence the address,
+* regionSize and subregions of the configuration struct are not applicable.
+*
+* Note that the user/privileged execute accesses are read-only and are always
+* enabled.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The register base address of the protection structure being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU SL slave struct was successfully configured.
+* CY_PROT_FAILURE | The resource is locked.
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedSlSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->privPermission));
+
+ if (CY_PERI_V1)
+ {
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR0 is read only. Only configure ATT0 */
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_GR_PPU_SL_ATT0_NS, !(config->secure))
+ | _VAL2FLD(PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only */
+ | _VAL2FLD(PERI_GR_PPU_SL_ATT0_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_SL_ATT0_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ PERI_GR_PPU_SL_ATT0(base) = attReg;
+ status = ((PERI_GR_PPU_SL_ATT0(base) & CY_PROT_PPU_SL_ATT0_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuFixedSlMasterStruct
+****************************************************************************//**
+*
+* Enables the Master PPU SL structure.
+*
+* This is a PPU SL master struct enable function. The PPU SL protection
+* settings will take effect after successful completion of this function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was enabled.
+* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuFixedSlMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (CY_PERI_V1)
+ {
+ PERI_GR_PPU_SL_ATT1(base) |= _VAL2FLD(PERI_GR_PPU_SL_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_SL_ATT1_ENABLED, PERI_GR_PPU_SL_ATT1(base)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuFixedSlMasterStruct
+****************************************************************************//**
+*
+* Disables the Master PPU SL structure.
+*
+* This is a PPU SL master struct disable function. The PPU SL protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was disabled.
+* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuFixedSlMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (CY_PERI_V1)
+ {
+ PERI_GR_PPU_SL_ATT1(base) &= ~_VAL2FLD(PERI_GR_PPU_SL_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_SL_ATT1_ENABLED, PERI_GR_PPU_SL_ATT1(base)) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuFixedSlSlaveStruct
+****************************************************************************//**
+*
+* Enables the Slave PPU SL structure.
+*
+* This is a PPU SL slave struct enable function. The PPU SL protection
+* settings will take effect after successful completion of this function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was enabled.
+* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuFixedSlSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (CY_PERI_V1)
+ {
+ PERI_GR_PPU_SL_ATT0(base) |= _VAL2FLD(PERI_GR_PPU_SL_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_SL_ATT0_ENABLED, PERI_GR_PPU_SL_ATT0(base)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuFixedSlSlaveStruct
+****************************************************************************//**
+*
+* Disables the Slave PPU SL structure.
+*
+* This is a PPU SL slave struct disable function. The PPU SL protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was enabled.
+* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuFixedSlSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ CY_ASSERT_L1(NULL != base);
+
+ if (CY_PERI_V1)
+ {
+ PERI_GR_PPU_SL_ATT0(base) &= ~_VAL2FLD(PERI_GR_PPU_SL_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_SL_ATT0_ENABLED, PERI_GR_PPU_SL_ATT0(base)) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedRgMasterStruct
+****************************************************************************//**
+*
+* Configures a Fixed Peripheral Region Protection Unit (PPU RG) master
+* protection struct with its protection attributes.
+*
+* This function configures the master struct governing the corresponding slave
+* struct pair. It is a mechanism to protect the slave PPU RG struct. Since
+* the memory location of the slave struct is known, the address, regionSize and
+* subregions of the configuration struct are not applicable.
+*
+* Note that only the user/privileged write permissions are configurable. The
+* read and execute permissions are read-only and cannot be configured.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The register base address of the protection struct being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU RG master struct was successfully configured.
+* CY_PROT_FAILURE | The resource is locked.
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedRgMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->privPermission));
+
+ if (CY_PERI_V1)
+ {
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR1 is read only. Only configure ATT1 */
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_GR_PPU_RG_ATT1_NS, !(config->secure))
+ | _VAL2FLD(PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only for master structs */
+ | _VAL2FLD(PERI_GR_PPU_RG_ATT1_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_RG_ATT1_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ PERI_GR_PPU_RG_ATT1(base) = attReg;
+ status = ((PERI_GR_PPU_RG_ATT1(base) & CY_PROT_PPU_RG_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedRgSlaveStruct
+****************************************************************************//**
+*
+* Configures a Fixed Peripheral Region Protection Unit (PPU RG) slave
+* protection struct with its protection attributes.
+*
+* This function configures the slave struct of a PPU RG pair, which can
+* protect specified regions of peripheral instances. For example, individual
+* DW channel structs, SMPU structs, and IPC structs etc.
+*
+* Each fixed PPU RG is devoted to a defined peripheral region. Hence the address,
+* regionSize and subregions of the configuration struct are not applicable.
+*
+* Note that the user/privileged execute accesses are read-only and are always
+* enabled.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The register base address of the protection structure being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU RG slave struct was successfully configured.
+* CY_PROT_FAILURE | The resource is locked.
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedRgSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->privPermission));
+
+ if (CY_PERI_V1)
+ {
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR0 is read only. Only configure ATT0 */
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_GR_PPU_RG_ATT0_NS, !(config->secure))
+ | _VAL2FLD(PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only */
+ | _VAL2FLD(PERI_GR_PPU_RG_ATT0_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_RG_ATT0_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ PERI_GR_PPU_RG_ATT0(base) = attReg;
+ status = ((PERI_GR_PPU_RG_ATT0(base) & CY_PROT_PPU_RG_ATT0_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuFixedRgMasterStruct
+****************************************************************************//**
+*
+* Enables the Master PPU RG structure.
+*
+* This is a PPU RG master struct enable function. The PPU RG protection
+* settings will take effect after successful completion of this function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was enabled.
+* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuFixedRgMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ if (CY_PERI_V1)
+ {
+ PERI_GR_PPU_RG_ATT1(base) |= _VAL2FLD(PERI_GR_PPU_RG_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_RG_ATT1_ENABLED, PERI_GR_PPU_RG_ATT1(base)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuFixedRgMasterStruct
+****************************************************************************//**
+*
+* Disables the Master PPU RG structure.
+*
+* This is a PPU RG master struct disable function. The PPU RG protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was disabled.
+* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuFixedRgMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ if (CY_PERI_V1)
+ {
+ PERI_GR_PPU_RG_ATT1(base) &= ~_VAL2FLD(PERI_GR_PPU_RG_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_RG_ATT1_ENABLED, PERI_GR_PPU_RG_ATT1(base)) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuFixedRgSlaveStruct
+****************************************************************************//**
+*
+* Enables the Slave PPU RG structure.
+*
+* This is a PPU RG slave struct enable function. The PPU RG protection
+* settings will take effect after successful completion of this function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was enabled.
+* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_EnablePpuFixedRgSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ if (CY_PERI_V1)
+ {
+ PERI_GR_PPU_RG_ATT0(base) |= _VAL2FLD(PERI_GR_PPU_RG_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_RG_ATT0_ENABLED, PERI_GR_PPU_RG_ATT0(base)) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuFixedRgSlaveStruct
+****************************************************************************//**
+*
+* Disables the Slave PPU RG structure.
+*
+* This is a PPU RG slave struct disable function. The PPU RG protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \note This function is applicable for CPUSS ver_1 only.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was disabled.
+* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked.
+* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
+*
+* \funcusage
+* \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuFixedRgSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base)
+{
+ cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
+
+ if (CY_PERI_V1)
+ {
+ PERI_GR_PPU_RG_ATT0(base) &= ~_VAL2FLD(PERI_GR_PPU_RG_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_RG_ATT0_ENABLED, PERI_GR_PPU_RG_ATT0(base)) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Prot_IsSmpuStructDisabled
+****************************************************************************//**
+*
+* This function returns the SMPU disabled status.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param smpuStcIndex
+* index of the SMPU structure.
+*
+* \return
+* true if both Slave and Master structures are disabled.
+* false if Master or/and Slave structure is/are enabled.
+*
+*******************************************************************************/
+static bool Prot_IsSmpuStructDisabled(uint32_t smpuStcIndex)
+{
+ return ((!_FLD2BOOL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, PROT_SMPU_SMPU_STRUCT_IDX_ATT0(smpuStcIndex))) &&
+ (!_FLD2BOOL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, PROT_SMPU_SMPU_STRUCT_IDX_ATT1(smpuStcIndex))));
+}
+
+
+/*******************************************************************************
+* Function Name: Prot_IsPpoProgStructDisabled
+****************************************************************************//**
+*
+* This function returns the Peripheral PPU disabled status.
+*
+* \note This function is applicable for both CPUSS ver_1 and ver_2.
+*
+* \param ppuStcIndex
+* index of the Prot_IsPpoProgStructDisabled structure.
+*
+* \return
+* true if both Slave and Master structures are disabled.
+* false if Master or/and Slave structure is/are enabled.
+*
+*******************************************************************************/
+static bool Prot_IsPpuProgStructDisabled(uint32_t ppuStcIndex)
+{
+ return ((!_FLD2BOOL(PERI_PPU_PR_ATT0_ENABLED, PROT_PERI_PPU_PR_STRUCT_IDX_ATT0(ppuStcIndex))) &&
+ (!_FLD2BOOL(PERI_PPU_PR_ATT1_ENABLED, PROT_PERI_PPU_PR_STRUCT_IDX_ATT1(ppuStcIndex))));
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_scb_common.c b/platform/ext/target/psoc64/Native_Driver/source/cy_scb_common.c
new file mode 100644
index 0000000000..8cfb4dba11
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_scb_common.c
@@ -0,0 +1,427 @@
+/***************************************************************************//**
+* \file cy_scb_common.c
+* \version 2.30.1
+*
+* Provides common API implementation of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_scb_common.h"
+
+#ifdef CY_IP_MXSCB
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ReadArrayNoCheck
+****************************************************************************//**
+*
+* Reads an array of data out of the SCB receive FIFO without checking if the
+* receive FIFO has enough data elements.
+* Before calling this function, make sure that the receive FIFO has enough data
+* elements to be read.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param buffer
+* The pointer to location to place data read from the receive FIFO.
+* The size of the data element defined by the configured data width.
+*
+* \param size
+* The number of data elements read from the receive FIFO.
+*
+*******************************************************************************/
+void Cy_SCB_ReadArrayNoCheck(CySCB_Type const *base, void *buffer, uint32_t size)
+{
+ uint32_t idx;
+
+ if (Cy_SCB_IsRxDataWidthByte(base))
+ {
+ uint8_t *buf = (uint8_t *) buffer;
+
+ /* Get data available in RX FIFO */
+ for (idx = 0UL; idx < size; ++idx)
+ {
+ buf[idx] = (uint8_t) Cy_SCB_ReadRxFifo(base);
+ }
+ }
+ else
+ {
+ uint16_t *buf = (uint16_t *) buffer;
+
+ /* Get data available in RX FIFO */
+ for (idx = 0UL; idx < size; ++idx)
+ {
+ buf[idx] = (uint16_t) Cy_SCB_ReadRxFifo(base);
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ReadArray
+****************************************************************************//**
+*
+* Reads an array of data out of the SCB receive FIFO.
+* This function does not block; it returns how many data elements are
+* read from the receive FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param buffer
+* The pointer to location to place data read from receive FIFO.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to read from the receive FIFO.
+*
+* \return
+* The number of data elements read from the receive FIFO.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_ReadArray(CySCB_Type const *base, void *buffer, uint32_t size)
+{
+ /* Get available items in RX FIFO */
+ uint32_t numToCopy = Cy_SCB_GetNumInRxFifo(base);
+
+ /* Adjust items that will be read */
+ if (numToCopy > size)
+ {
+ numToCopy = size;
+ }
+
+ /* Get data available in RX FIFO */
+ Cy_SCB_ReadArrayNoCheck(base, buffer, numToCopy);
+
+ return (numToCopy);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ReadArrayBlocking
+****************************************************************************//**
+*
+* Reads an array of data out of the SCB receive FIFO.
+* This function blocks until the number of data elements specified by the
+* size has been read from the receive FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param buffer
+* The pointer to the location to place data read from the receive FIFO.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to read from receive FIFO.
+*
+*******************************************************************************/
+void Cy_SCB_ReadArrayBlocking(CySCB_Type const *base, void *buffer, uint32_t size)
+{
+ uint32_t numCopied;
+ uint8_t *buf = (uint8_t *) buffer;
+ bool byteMode = Cy_SCB_IsRxDataWidthByte(base);
+
+ /* Get data from RX FIFO. Stop when the requested size is read. */
+ while (size > 0UL)
+ {
+ numCopied = Cy_SCB_ReadArray(base, (void *) buf, size);
+
+ buf = &buf[(byteMode ? (numCopied) : (2UL * numCopied))];
+ size -= numCopied;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_Write
+****************************************************************************//**
+*
+* Places a single data element in the SCB transmit FIFO.
+* This function does not block. It returns how many data elements are placed
+* in the transmit FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param data
+* Data to put in the transmit FIFO.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \return
+* The number of data elements placed in the transmit FIFO: 0 or 1.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_Write(CySCB_Type *base, uint32_t data)
+{
+ uint32_t numCopied = 0UL;
+
+ if (Cy_SCB_GetFifoSize(base) != Cy_SCB_GetNumInTxFifo(base))
+ {
+ Cy_SCB_WriteTxFifo(base, data);
+
+ numCopied = 1UL;
+ }
+
+ return (numCopied);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteArrayNoCheck
+****************************************************************************//**
+*
+* Places an array of data in the SCB transmit FIFO without checking whether the
+* transmit FIFO has enough space.
+* Before calling this function, make sure that the transmit FIFO has enough
+* space to put all requested data elements.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param buffer
+* The pointer to data to place in the transmit FIFO.
+* The item size is defined by the data type, which depends on the configured
+* TX data width.
+*
+* \param size
+* The number of data elements to transmit.
+*
+* \return
+* The number of data elements placed in the transmit FIFO.
+*
+*******************************************************************************/
+void Cy_SCB_WriteArrayNoCheck(CySCB_Type *base, void *buffer, uint32_t size)
+{
+ uint32_t idx;
+
+ if (Cy_SCB_IsTxDataWidthByte(base))
+ {
+ uint8_t *buf = (uint8_t *) buffer;
+
+ /* Put data into TX FIFO */
+ for (idx = 0UL; idx < size; ++idx)
+ {
+ Cy_SCB_WriteTxFifo(base, (uint32_t) buf[idx]);
+ }
+ }
+ else
+ {
+ uint16_t *buf = (uint16_t *) buffer;
+
+ /* Put data into TX FIFO */
+ for (idx = 0UL; idx < size; ++idx)
+ {
+ Cy_SCB_WriteTxFifo(base, (uint32_t) buf[idx]);
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteArray
+****************************************************************************//**
+*
+* Places an array of data in the SCB transmit FIFO.
+* This function does not block. It returns how many data elements were
+* placed in the transmit FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param buffer
+* The pointer to data to place in the transmit FIFO.
+* The item size is defined by the data type which depends on the configured
+* TX data width.
+*
+* \param size
+* The number of data elements to transmit.
+*
+* \return
+* The number of data elements placed in the transmit FIFO.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_WriteArray(CySCB_Type *base, void *buffer, uint32_t size)
+{
+ /* Get free entries in TX FIFO */
+ uint32_t numToCopy = Cy_SCB_GetFifoSize(base) - Cy_SCB_GetNumInTxFifo(base);
+
+ /* Adjust the data elements to write */
+ if (numToCopy > size)
+ {
+ numToCopy = size;
+ }
+
+ Cy_SCB_WriteArrayNoCheck(base, buffer, numToCopy);
+
+ return (numToCopy);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteArrayBlocking
+****************************************************************************//**
+*
+* Places an array of data in the transmit FIFO.
+* This function blocks until the number of data elements specified by the size
+* is placed in the transmit FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param buffer
+* The pointer to data to place in transmit FIFO.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to write into the transmit FIFO.
+*
+*******************************************************************************/
+void Cy_SCB_WriteArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size)
+{
+ uint32_t numCopied;
+ uint8_t *buf = (uint8_t *) buffer;
+ bool byteMode = Cy_SCB_IsTxDataWidthByte(base);
+
+ /* Get data from RX FIFO. Stop when the requested size is read. */
+ while (size > 0UL)
+ {
+ numCopied = Cy_SCB_WriteArray(base, (void *) buf, size);
+
+ buf = &buf[(byteMode ? (numCopied) : (2UL * numCopied))];
+ size -= numCopied;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteString
+****************************************************************************//**
+*
+* Places a NULL terminated string in the transmit FIFO.
+* This function blocks until the entire string is placed in the transmit FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param string
+* The pointer to the null terminated string array.
+*
+*******************************************************************************/
+void Cy_SCB_WriteString(CySCB_Type *base, char_t const string[])
+{
+ uint32_t idx = 0UL;
+ uint32_t fifoSize = Cy_SCB_GetFifoSize(base);
+
+ /* Put data from TX FIFO. Stop when string is terminated */
+ while (((char_t) 0) != string[idx])
+ {
+ /* Wait for free space to be available */
+ while (fifoSize == Cy_SCB_GetNumInTxFifo(base))
+ {
+ }
+
+ Cy_SCB_WriteTxFifo(base, (uint32_t) string[idx]);
+ ++idx;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteDefaultArrayNoCheck
+****************************************************************************//**
+*
+* Places a number of the same data elements in the SCB transmit FIFO without
+* checking whether the transmit FIFO has enough space. The data elements is equal
+* to txData parameter.
+* Before calling this function, make sure that transmit FIFO has enough space
+* to put all requested data elements.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param txData
+* The data element to transmit repeatedly.
+*
+* \param size
+* The number of data elements to transmit.
+*
+*******************************************************************************/
+void Cy_SCB_WriteDefaultArrayNoCheck(CySCB_Type *base, uint32_t txData, uint32_t size)
+{
+ while (size > 0UL)
+ {
+ Cy_SCB_WriteTxFifo(base, txData);
+ --size;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteDefaultArray
+****************************************************************************//**
+*
+* Places a number of the same data elements in the SCB transmit FIFO.
+* The data elements is equal to the txData parameter.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param txData
+* The data element to transmit repeatedly.
+*
+* \param size
+* The number of data elements to transmit.
+*
+* \return
+* The number of data elements placed in the transmit FIFO.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_WriteDefaultArray(CySCB_Type *base, uint32_t txData, uint32_t size)
+{
+ /* Get free entries in TX FIFO */
+ uint32_t numToCopy = Cy_SCB_GetFifoSize(base) - Cy_SCB_GetNumInTxFifo(base);
+
+ /* Adjust data elements to write */
+ if (numToCopy > size)
+ {
+ numToCopy = size;
+ }
+
+ Cy_SCB_WriteDefaultArrayNoCheck(base, txData, numToCopy);
+
+ return (numToCopy);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_IP_MXSCB */
+
+/* [] END OF FILE */
+
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_scb_uart.c b/platform/ext/target/psoc64/Native_Driver/source/cy_scb_uart.c
new file mode 100644
index 0000000000..02babb2603
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_scb_uart.c
@@ -0,0 +1,1435 @@
+/***************************************************************************//**
+* \file cy_scb_uart.c
+* \version 2.30.1
+*
+* Provides UART API implementation of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_scb_uart.h"
+
+#ifdef CY_IP_MXSCB
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/* Static functions */
+static void HandleDataReceive (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+static void HandleRingBuffer (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Init
+****************************************************************************//**
+*
+* Initializes the SCB for UART operation.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param config
+* The pointer to configuration structure \ref cy_stc_scb_uart_config_t.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+* If only UART \ref group_scb_uart_ll will be used pass NULL as pointer to
+* context.
+*
+* \return
+* \ref cy_en_scb_uart_status_t
+*
+* \note
+* Ensure that the SCB block is disabled before calling this function.
+*
+*******************************************************************************/
+cy_en_scb_uart_status_t Cy_SCB_UART_Init(CySCB_Type *base, cy_stc_scb_uart_config_t const *config, cy_stc_scb_uart_context_t *context)
+{
+ if ((NULL == base) || (NULL == config))
+ {
+ return CY_SCB_UART_BAD_PARAM;
+ }
+
+ CY_ASSERT_L3(CY_SCB_UART_IS_MODE_VALID (config->uartMode));
+ CY_ASSERT_L3(CY_SCB_UART_IS_STOP_BITS_VALID(config->stopBits));
+ CY_ASSERT_L3(CY_SCB_UART_IS_PARITY_VALID (config->parity));
+ CY_ASSERT_L3(CY_SCB_UART_IS_POLARITY_VALID (config->ctsPolarity));
+ CY_ASSERT_L3(CY_SCB_UART_IS_POLARITY_VALID (config->rtsPolarity));
+
+ CY_ASSERT_L2(CY_SCB_UART_IS_OVERSAMPLE_VALID (config->oversample, config->uartMode, config->irdaEnableLowPowerReceiver));
+ CY_ASSERT_L2(CY_SCB_UART_IS_DATA_WIDTH_VALID (config->dataWidth));
+ CY_ASSERT_L2(CY_SCB_UART_IS_ADDRESS_VALID (config->receiverAddress));
+ CY_ASSERT_L2(CY_SCB_UART_IS_ADDRESS_MASK_VALID(config->receiverAddressMask));
+ CY_ASSERT_L2(CY_SCB_UART_IS_MUTLI_PROC_VALID (config->enableMutliProcessorMode, config->uartMode, config->dataWidth,
+ config->parity));
+
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->rxFifoIntEnableMask, CY_SCB_UART_RX_INTR_MASK));
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->txFifoIntEnableMask, CY_SCB_UART_TX_INTR_MASK));
+
+ uint32_t ovs;
+
+ if ((CY_SCB_UART_IRDA == config->uartMode) && (!config->irdaEnableLowPowerReceiver))
+ {
+ /* For Normal IrDA mode oversampling is always zero */
+ ovs = 0UL;
+ }
+ else
+ {
+ ovs = (config->oversample - 1UL);
+ }
+
+ /* Configure the UART interface */
+ SCB_CTRL(base) = _BOOL2FLD(SCB_CTRL_ADDR_ACCEPT, config->acceptAddrInFifo) |
+ _BOOL2FLD(SCB_CTRL_BYTE_MODE, (config->dataWidth <= CY_SCB_BYTE_WIDTH)) |
+ _VAL2FLD(SCB_CTRL_OVS, ovs) |
+ _VAL2FLD(SCB_CTRL_MODE, CY_SCB_CTRL_MODE_UART);
+
+ /* Configure SCB_CTRL.BYTE_MODE then verify levels */
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->rxFifoTriggerLevel));
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->txFifoTriggerLevel));
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->rtsRxFifoLevel));
+
+ SCB_UART_CTRL(base) = _VAL2FLD(SCB_UART_CTRL_MODE, (uint32_t) config->uartMode);
+
+ /* Configure the RX direction */
+ SCB_UART_RX_CTRL(base) = _BOOL2FLD(SCB_UART_RX_CTRL_POLARITY, config->irdaInvertRx) |
+ _BOOL2FLD(SCB_UART_RX_CTRL_MP_MODE, config->enableMutliProcessorMode) |
+ _BOOL2FLD(SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR, config->dropOnParityError) |
+ _BOOL2FLD(SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR, config->dropOnFrameError) |
+ _VAL2FLD(SCB_UART_RX_CTRL_BREAK_WIDTH, (config->breakWidth - 1UL)) |
+ _VAL2FLD(SCB_UART_RX_CTRL_STOP_BITS, ((uint32_t) config->stopBits) - 1UL) |
+ _VAL2FLD(CY_SCB_UART_RX_CTRL_SET_PARITY, (uint32_t) config->parity);
+
+ SCB_RX_CTRL(base) = _BOOL2FLD(SCB_RX_CTRL_MSB_FIRST, config->enableMsbFirst) |
+ _BOOL2FLD(SCB_RX_CTRL_MEDIAN, ((config->enableInputFilter) || \
+ (config->uartMode == CY_SCB_UART_IRDA))) |
+ _VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, (config->dataWidth - 1UL));
+
+ SCB_RX_MATCH(base) = _VAL2FLD(SCB_RX_MATCH_ADDR, config->receiverAddress) |
+ _VAL2FLD(SCB_RX_MATCH_MASK, config->receiverAddressMask);
+
+ /* Configure SCB_CTRL.RX_CTRL then verify break width */
+ CY_ASSERT_L2(CY_SCB_UART_IS_RX_BREAK_WIDTH_VALID(base, config->breakWidth));
+
+ /* Configure the TX direction */
+ SCB_UART_TX_CTRL(base) = _BOOL2FLD(SCB_UART_TX_CTRL_RETRY_ON_NACK, ((config->smartCardRetryOnNack) && \
+ (config->uartMode == CY_SCB_UART_SMARTCARD))) |
+ _VAL2FLD(SCB_UART_TX_CTRL_STOP_BITS, ((uint32_t) config->stopBits) - 1UL) |
+ _VAL2FLD(CY_SCB_UART_TX_CTRL_SET_PARITY, (uint32_t) config->parity);
+
+ SCB_TX_CTRL(base) = _BOOL2FLD(SCB_TX_CTRL_MSB_FIRST, config->enableMsbFirst) |
+ _VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, (config->dataWidth - 1UL)) |
+ _BOOL2FLD(SCB_TX_CTRL_OPEN_DRAIN, (config->uartMode == CY_SCB_UART_SMARTCARD));
+
+ SCB_RX_FIFO_CTRL(base) = _VAL2FLD(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, config->rxFifoTriggerLevel);
+
+ /* Configure the flow control */
+ SCB_UART_FLOW_CTRL(base) = _BOOL2FLD(SCB_UART_FLOW_CTRL_CTS_ENABLED, config->enableCts) |
+ _BOOL2FLD(SCB_UART_FLOW_CTRL_CTS_POLARITY, (CY_SCB_UART_ACTIVE_HIGH == config->ctsPolarity)) |
+ _BOOL2FLD(SCB_UART_FLOW_CTRL_RTS_POLARITY, (CY_SCB_UART_ACTIVE_HIGH == config->rtsPolarity)) |
+ _VAL2FLD(SCB_UART_FLOW_CTRL_TRIGGER_LEVEL, config->rtsRxFifoLevel);
+
+ SCB_TX_FIFO_CTRL(base) = _VAL2FLD(SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, config->txFifoTriggerLevel);
+
+ /* Set up interrupt sources */
+ SCB_INTR_RX_MASK(base) = (config->rxFifoIntEnableMask & CY_SCB_UART_RX_INTR_MASK);
+ SCB_INTR_TX_MASK(base) = (config->txFifoIntEnableMask & CY_SCB_UART_TX_INTR_MASK);
+
+ /* Initialize context */
+ if (NULL != context)
+ {
+ context->rxStatus = 0UL;
+ context->txStatus = 0UL;
+
+ context->rxRingBuf = NULL;
+ context->rxRingBufSize = 0UL;
+
+ context->rxBufIdx = 0UL;
+ context->txLeftToTransmit = 0UL;
+
+ context->cbEvents = NULL;
+
+ #if !defined(NDEBUG)
+ /* Put an initialization key into the initKey variable to verify
+ * context initialization in the transfer API.
+ */
+ context->initKey = CY_SCB_UART_INIT_KEY;
+ #endif /* !(NDEBUG) */
+ }
+
+ return CY_SCB_UART_SUCCESS;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_DeInit
+****************************************************************************//**
+*
+* De-initializes the SCB block. Returns the register values to default.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \note
+* Ensure that the SCB block is disabled before calling this function.
+*
+*******************************************************************************/
+void Cy_SCB_UART_DeInit(CySCB_Type *base)
+{
+ /* De-initialize the UART interface */
+ SCB_CTRL(base) = CY_SCB_CTRL_DEF_VAL;
+ SCB_UART_CTRL(base) = CY_SCB_UART_CTRL_DEF_VAL;
+
+ /* De-initialize the RX direction */
+ SCB_UART_RX_CTRL(base) = 0UL;
+ SCB_RX_CTRL(base) = CY_SCB_RX_CTRL_DEF_VAL;
+ SCB_RX_FIFO_CTRL(base) = 0UL;
+ SCB_RX_MATCH(base) = 0UL;
+
+ /* De-initialize the TX direction */
+ SCB_UART_TX_CTRL(base) = 0UL;
+ SCB_TX_CTRL(base) = CY_SCB_TX_CTRL_DEF_VAL;
+ SCB_TX_FIFO_CTRL(base) = 0UL;
+
+ /* De-initialize the flow control */
+ SCB_UART_FLOW_CTRL(base) = 0UL;
+
+ /* De-initialize the interrupt sources */
+ SCB_INTR_SPI_EC_MASK(base) = 0UL;
+ SCB_INTR_I2C_EC_MASK(base) = 0UL;
+ SCB_INTR_RX_MASK(base) = 0UL;
+ SCB_INTR_TX_MASK(base) = 0UL;
+ SCB_INTR_M_MASK(base) = 0UL;
+ SCB_INTR_S_MASK(base) = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Disable
+****************************************************************************//**
+*
+* Disables the SCB block and clears context statuses.
+* Note that after the block is disabled, the TX and RX FIFOs and
+* hardware statuses are cleared. Also, the hardware stops driving the
+* output and ignores the input. Refer to section \ref group_scb_uart_lp for more
+* information about UART pins when SCB disabled.
+
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+* If only UART functions that do not require context will be used to pass NULL
+* as pointer to context.
+*
+* \note
+* Calling this function when the UART is busy (transmitter preforms data
+* transfer or receiver is in the middle of data reception) may result transfer
+* corruption because the hardware stops driving the outputs and ignores
+* the inputs.
+* Ensure that the UART is not busy before calling this function.
+*
+*******************************************************************************/
+void Cy_SCB_UART_Disable(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ SCB_CTRL(base) &= (uint32_t) ~SCB_CTRL_ENABLED_Msk;
+
+ if (NULL != context)
+ {
+ context->rxStatus = 0UL;
+ context->txStatus = 0UL;
+
+ context->rxBufIdx = 0UL;
+ context->txLeftToTransmit = 0UL;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_DeepSleepCallback
+****************************************************************************//**
+*
+* This function handles the transition of the SCB UART into and out of
+* Deep Sleep mode. It prevents the device from entering Deep Sleep
+* mode if the UART is transmitting data or has any data in the RX FIFO. If the
+* UART is ready to enter Deep Sleep mode, it is disabled. The UART is enabled
+* when the device fails to enter Deep Sleep mode or it is awakened from
+* Deep Sleep mode. While the UART is disabled, it stops driving the outputs
+* and ignores the inputs. Any incoming data is ignored. Refer to section
+* \ref group_scb_uart_lp for more information about UART pins when SCB disabled.
+*
+* This function must be called during execution of \ref Cy_SysPm_CpuEnterDeepSleep,
+* to do it, register this function as a callback before calling
+* \ref Cy_SysPm_CpuEnterDeepSleep : specify \ref CY_SYSPM_DEEPSLEEP as the callback
+* type and call \ref Cy_SysPm_RegisterCallback.
+*
+* \param callbackParams
+* The pointer to the callback parameters structure
+* \ref cy_stc_syspm_callback_params_t.
+*
+* \param mode
+* Callback mode, see \ref cy_en_syspm_callback_mode_t
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SCB_UART_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode)
+{
+ cy_en_syspm_status_t retStatus = CY_SYSPM_FAIL;
+
+ CySCB_Type *locBase = (CySCB_Type *) callbackParams->base;
+ cy_stc_scb_uart_context_t *locContext = (cy_stc_scb_uart_context_t *) callbackParams->context;
+
+ switch(mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ /* Check whether the High-level API is not busy executing the transmit
+ * or receive operation.
+ */
+ if ((0UL == (CY_SCB_UART_TRANSMIT_ACTIVE & Cy_SCB_UART_GetTransmitStatus(locBase, locContext))) &&
+ (0UL == (CY_SCB_UART_RECEIVE_ACTIVE & Cy_SCB_UART_GetReceiveStatus (locBase, locContext))))
+ {
+ /* If all data elements are transmitted from the TX FIFO and
+ * shifter and the RX FIFO is empty: the UART is ready to enter
+ * Deep Sleep mode.
+ */
+ if (Cy_SCB_UART_IsTxComplete(locBase))
+ {
+ if (0UL == Cy_SCB_UART_GetNumInRxFifo(locBase))
+ {
+ /* Disable the UART. The transmitter stops driving the
+ * lines and the receiver stops receiving data until
+ * the UART is enabled.
+ * This happens when the device failed to enter Deep
+ * Sleep or it is awaken from Deep Sleep mode.
+ */
+ Cy_SCB_UART_Disable(locBase, locContext);
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ }
+ }
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ /* The other driver is not ready for Deep Sleep mode. Restore the
+ * Active mode configuration.
+ */
+
+ /* Enable the UART to operate */
+ Cy_SCB_UART_Enable(locBase);
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ /* Do noting: the UART is not capable of waking up from
+ * Deep Sleep mode.
+ */
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ /* Enable the UART to operate */
+ Cy_SCB_UART_Enable(locBase);
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_HibernateCallback
+****************************************************************************//**
+*
+* This function handles the transition of the SCB UART into Hibernate mode.
+* It prevents the device from entering Hibernate mode if the UART is
+* transmitting data or has any data in the RX FIFO. If the UART is ready
+* to enter Hibernate mode, it is disabled. If the device fails to enter
+* Hibernate mode, the UART is enabled. While the UART is disabled, it stops
+* driving the outputs and ignores the inputs. Any incoming data is ignored.
+* Refer to section \ref group_scb_uart_lp for more information about UART pins
+* when SCB disabled.
+*
+* This function must be called during execution of \ref Cy_SysPm_SystemEnterHibernate.
+* To do it, register this function as a callback before calling
+* \ref Cy_SysPm_SystemEnterHibernate : specify \ref CY_SYSPM_HIBERNATE as the callback type
+* and call \ref Cy_SysPm_RegisterCallback.
+*
+* \param callbackParams
+* The pointer to the callback parameters structure
+* \ref cy_stc_syspm_callback_params_t.
+*
+* \param mode
+* Callback mode, see \ref cy_en_syspm_callback_mode_t
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SCB_UART_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode)
+{
+ return Cy_SCB_UART_DeepSleepCallback(callbackParams, mode);
+}
+
+
+/************************* High-Level Functions ********************************
+* The following functions are considered high-level. They provide the layer of
+* intelligence to the SCB. These functions require interrupts.
+* Low-level and high-level functions must not be mixed because low-level API
+* can adversely affect the operation of high-level functions.
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_StartRingBuffer
+****************************************************************************//**
+*
+* Starts the receive ring buffer operation.
+* The RX interrupt source is configured to get data from the RX
+* FIFO and put into the ring buffer.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* Pointer to the user defined ring buffer.
+* The element size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The size of the receive ring buffer.
+* Note that one data element is used for internal use, so if the size is 32,
+* then only 31 data elements are used for data storage.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* * The buffer must not be modified and stay allocated while the ring buffer
+* operates.
+* * This function overrides the RX interrupt sources and changes the
+* RX FIFO level.
+*
+*******************************************************************************/
+void Cy_SCB_UART_StartRingBuffer(CySCB_Type *base, void *buffer, uint32_t size, cy_stc_scb_uart_context_t *context)
+{
+ CY_ASSERT_L1(NULL != context);
+ CY_ASSERT_L1(CY_SCB_UART_INIT_KEY == context->initKey);
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ if ((NULL != buffer) && (size > 0UL))
+ {
+ uint32_t halfFifoSize = (Cy_SCB_GetFifoSize(base) / 2UL);
+
+ context->rxRingBuf = buffer;
+ context->rxRingBufSize = size;
+ context->rxRingBufHead = 0UL;
+ context->rxRingBufTail = 0UL;
+
+ /* Set up an RX interrupt to handle the ring buffer */
+ Cy_SCB_SetRxFifoLevel(base, (size >= halfFifoSize) ? (halfFifoSize - 1UL) : (size - 1UL));
+
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_StopRingBuffer
+****************************************************************************//**
+*
+* Stops receiving data into the ring buffer and clears the ring buffer.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+void Cy_SCB_UART_StopRingBuffer(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ Cy_SCB_SetRxInterruptMask (base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ Cy_SCB_UART_ClearRingBuffer(base, context);
+
+ context->rxRingBuf = NULL;
+ context->rxRingBufSize = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetNumInRingBuffer
+****************************************************************************//**
+*
+* Returns the number of data elements in the ring buffer.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* The number of data elements in the receive ring buffer.
+*
+* \note
+* One data element is used for internal use, so when the buffer is full,
+* this function returns (Ring Buffer size - 1).
+*
+*******************************************************************************/
+uint32_t Cy_SCB_UART_GetNumInRingBuffer(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context)
+{
+ uint32_t size;
+ uint32_t locHead = context->rxRingBufHead;
+
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ if (locHead >= context->rxRingBufTail)
+ {
+ size = (locHead - context->rxRingBufTail);
+ }
+ else
+ {
+ size = (locHead + (context->rxBufSize - context->rxRingBufTail));
+ }
+
+ return (size);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_ClearRingBuffer
+****************************************************************************//**
+*
+* Clears the ring buffer.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+void Cy_SCB_UART_ClearRingBuffer(CySCB_Type const *base, cy_stc_scb_uart_context_t *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ context->rxRingBufHead = context->rxRingBufTail;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Receive
+****************************************************************************//**
+*
+* This function starts a UART receive operation.
+* It configures the receive interrupt sources to get data available in the
+* receive FIFO and returns. The \ref Cy_SCB_UART_Interrupt manages the further
+* data transfer.
+*
+* If the ring buffer is enabled, this function first reads data from the ring
+* buffer. If there is more data to receive, it configures the receive interrupt
+* sources to copy the remaining bytes from the RX FIFO when they arrive.
+*
+* When the receive operation is completed (requested number of data elements
+* received) the \ref CY_SCB_UART_RECEIVE_ACTIVE status is cleared and
+* the \ref CY_SCB_UART_RECEIVE_DONE_EVENT event is generated.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* Pointer to buffer to store received data.
+* The element size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to receive.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_uart_status_t
+*
+* \note
+* * The buffer must not be modified and stay allocated until end of the
+* receive operation.
+* * This function overrides the RX interrupt sources and changes the
+* RX FIFO level.
+*
+*******************************************************************************/
+cy_en_scb_uart_status_t Cy_SCB_UART_Receive(CySCB_Type *base, void *buffer, uint32_t size, cy_stc_scb_uart_context_t *context)
+{
+ CY_ASSERT_L1(NULL != context);
+ CY_ASSERT_L1(CY_SCB_UART_INIT_KEY == context->initKey);
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ cy_en_scb_uart_status_t retStatus = CY_SCB_UART_RECEIVE_BUSY;
+
+ /* check whether there are no active transfer requests */
+ if (0UL == (context->rxStatus & CY_SCB_UART_RECEIVE_ACTIVE))
+ {
+ uint8_t *tmpBuf = (uint8_t *) buffer;
+ uint32_t numToCopy = 0UL;
+
+ /* Disable the RX interrupt source to stop the ring buffer update */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ if (NULL != context->rxRingBuf)
+ {
+ /* Get the items available in the ring buffer */
+ numToCopy = Cy_SCB_UART_GetNumInRingBuffer(base, context);
+
+ if (numToCopy > 0UL)
+ {
+ uint32_t idx;
+ uint32_t locTail = context->rxRingBufTail;
+ bool byteMode = Cy_SCB_IsRxDataWidthByte(base);
+
+ /* Adjust the number of items to be read */
+ if (numToCopy > size)
+ {
+ numToCopy = size;
+ }
+
+ /* Copy the data elements from the ring buffer */
+ for (idx = 0UL; idx < numToCopy; ++idx)
+ {
+ ++locTail;
+
+ if (locTail == context->rxRingBufSize)
+ {
+ locTail = 0UL;
+ }
+
+ if (byteMode)
+ {
+ uint8_t *buf = (uint8_t *) buffer;
+ buf[idx] = ((uint8_t *) context->rxRingBuf)[locTail];
+ }
+ else
+ {
+ uint16_t *buf = (uint16_t *) buffer;
+ buf[idx] = ((uint16_t *) context->rxRingBuf)[locTail];
+ }
+ }
+
+ /* Update the ring buffer tail after data has been copied */
+ context->rxRingBufTail = locTail;
+
+ /* Update with the copied bytes */
+ size -= numToCopy;
+ context->rxBufIdx = numToCopy;
+
+ /* Check whether all requested data has been read from the ring buffer */
+ if (0UL == size)
+ {
+ /* Enable the RX-error interrupt sources to update the error status */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_UART_RECEIVE_ERR);
+
+ /* Call a completion callback if there was no abort receive called
+ * in the interrupt. The abort clears the number of the received bytes.
+ */
+ if (context->rxBufIdx > 0UL)
+ {
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_RECEIVE_DONE_EVENT);
+ }
+ }
+
+ /* Continue receiving data in the ring buffer */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL);
+ }
+ else
+ {
+ tmpBuf = &tmpBuf[(byteMode) ? (numToCopy) : (2UL * numToCopy)];
+ }
+ }
+ }
+
+ /* Set up a direct RX FIFO receive */
+ if (size > 0UL)
+ {
+ uint32_t halfFifoSize = Cy_SCB_GetFifoSize(base) / 2UL;
+
+ /* Set up context */
+ context->rxStatus = CY_SCB_UART_RECEIVE_ACTIVE;
+
+ context->rxBuf = (void *) tmpBuf;
+ context->rxBufSize = size;
+ context->rxBufIdx = numToCopy;
+
+ /* Set the RX FIFO level to the trigger interrupt */
+ Cy_SCB_SetRxFifoLevel(base, (size > halfFifoSize) ? (halfFifoSize - 1UL) : (size - 1UL));
+
+ /* Enable the RX interrupt sources to continue data reading */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_UART_RX_INTR);
+ }
+
+ retStatus = CY_SCB_UART_SUCCESS;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_AbortReceive
+****************************************************************************//**
+*
+* Abort the current receive operation by clearing the receive status.
+* * If the ring buffer is disabled, the receive interrupt sources are disabled.
+* * If the ring buffer is enabled, the receive interrupt source is configured
+* to get data from the receive FIFO and put it into the ring buffer.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* * The RX FIFO and ring buffer are not cleared after abort of receive
+* operation.
+* * If after the abort of the receive operation the transmitter continues
+* sending data, it gets into the RX FIFO. To drop this data, the RX FIFO
+* and ring buffer (if enabled) must be cleared when the transmitter
+* stops sending data. Otherwise, received data will be kept and copied
+* to the buffer when \ref Cy_SCB_UART_Receive is called.
+*
+*******************************************************************************/
+void Cy_SCB_UART_AbortReceive(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ if (NULL == context->rxRingBuf)
+ {
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+
+ context->rxBufSize = 0UL;
+ context->rxBufIdx = 0UL;
+
+ context->rxStatus = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetNumReceived
+****************************************************************************//**
+*
+* Returns the number of data elements received since the last call to \ref
+* Cy_SCB_UART_Receive.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* The number of data elements received.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_UART_GetNumReceived(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->rxBufIdx);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetReceiveStatus
+****************************************************************************//**
+*
+* Returns the status of the receive operation.
+* This status is a bit mask and the value returned may have multiple bits set.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref group_scb_uart_macros_receive_status.
+*
+* \note
+* The status is only cleared by calling \ref Cy_SCB_UART_Receive again.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_UART_GetReceiveStatus(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->rxStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Transmit
+****************************************************************************//**
+*
+* This function starts a UART transmit operation.
+* It configures the transmit interrupt sources and returns.
+* The \ref Cy_SCB_UART_Interrupt manages the further data transfer.
+*
+* When the transmit operation is completed (requested number of data elements
+* sent on the bus), the \ref CY_SCB_UART_TRANSMIT_ACTIVE status is cleared and
+* the \ref CY_SCB_UART_TRANSMIT_DONE_EVENT event is generated.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* Pointer to user data to place in transmit buffer.
+* The element size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to transmit.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_uart_status_t
+*
+* \note
+* * The buffer must not be modified and must stay allocated until its content is
+* copied into the TX FIFO.
+* * This function overrides the TX FIFO interrupt sources and changes the
+* TX FIFO level.
+*
+*******************************************************************************/
+cy_en_scb_uart_status_t Cy_SCB_UART_Transmit(CySCB_Type *base, void *buffer, uint32_t size, cy_stc_scb_uart_context_t *context)
+{
+ CY_ASSERT_L1(NULL != context);
+ CY_ASSERT_L1(CY_SCB_UART_INIT_KEY == context->initKey);
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ cy_en_scb_uart_status_t retStatus = CY_SCB_UART_TRANSMIT_BUSY;
+
+ /* Check whether there are no active transfer requests */
+ if (0UL == (CY_SCB_UART_TRANSMIT_ACTIVE & context->txStatus))
+ {
+ /* Set up context */
+ context->txStatus = CY_SCB_UART_TRANSMIT_ACTIVE;
+
+ context->txBuf = buffer;
+ context->txBufSize = size;
+
+ /* Set the level in TX FIFO to start a transfer */
+ Cy_SCB_SetTxFifoLevel(base, (Cy_SCB_GetFifoSize(base) / 2UL));
+
+ /* Enable the interrupt sources */
+ if (((uint32_t) CY_SCB_UART_SMARTCARD) == _FLD2VAL(SCB_UART_CTRL_MODE, SCB_UART_CTRL(base)))
+ {
+ /* Transfer data into TX FIFO and track SmartCard-specific errors */
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_UART_TX_INTR);
+ }
+ else
+ {
+ /* Transfer data into TX FIFO */
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL);
+ }
+
+ retStatus = CY_SCB_UART_SUCCESS;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_AbortTransmit
+****************************************************************************//**
+*
+* Aborts the current transmit operation.
+* It disables the transmit interrupt sources and clears the transmit FIFO
+* and status.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \sideeffect
+* The transmit FIFO clear operation also clears the shift register, so that
+* the shifter can be cleared in the middle of a data element transfer,
+* corrupting it. The data element corruption means that all bits that have
+* not been transmitted are transmitted as "ones" on the bus.
+*
+*******************************************************************************/
+void Cy_SCB_UART_AbortTransmit(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ Cy_SCB_UART_ClearTxFifo(base);
+
+ context->txBufSize = 0UL;
+ context->txLeftToTransmit = 0UL;
+
+ context->txStatus = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetNumLeftToTransmit
+****************************************************************************//**
+*
+* Returns the number of data elements left to transmit since the last call to
+* \ref Cy_SCB_UART_Transmit.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* The number of data elements left to transmit.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_UART_GetNumLeftToTransmit(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->txLeftToTransmit);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetTransmitStatus
+****************************************************************************//**
+*
+* Returns the status of the transmit operation.
+* This status is a bit mask and the value returned may have multiple bits set.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref group_scb_uart_macros_transmit_status.
+*
+* \note
+* The status is only cleared by calling \ref Cy_SCB_UART_Transmit or
+* \ref Cy_SCB_UART_AbortTransmit.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_UART_GetTransmitStatus(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->txStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_SendBreakBlocking
+****************************************************************************//**
+*
+* Sends a break condition (logic low) of specified width on UART TX line.
+* Blocks until break is completed. Only call this function when UART TX FIFO
+* and shifter are empty.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param breakWidth
+* Width of break condition. Valid range is the TX data width (4 to 16 bits)
+*
+* \note
+* Before sending break all UART TX interrupt sources are disabled. The state
+* of UART TX interrupt sources is restored before function returns.
+*
+* \sideeffect
+* If this function is called while there is data in the TX FIFO or shifter that
+* data will be shifted out in packets the size of breakWidth.
+*
+*******************************************************************************/
+void Cy_SCB_UART_SendBreakBlocking(CySCB_Type *base, uint32_t breakWidth)
+{
+ uint32_t txCtrlReg;
+ uint32_t txIntrReg;
+
+ CY_ASSERT_L2(CY_SCB_UART_IS_TX_BREAK_WIDTH_VALID(breakWidth));
+
+ /* Disable all UART TX interrupt sources and clear UART TX Done history */
+ txIntrReg = Cy_SCB_GetTxInterruptMask(base);
+ Cy_SCB_SetTxInterruptMask(base, 0UL);
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UART_DONE);
+
+ /* Store TX_CTRL configuration */
+ txCtrlReg = SCB_TX_CTRL(base);
+
+ /* Set break width: start bit adds one 0 bit */
+ CY_REG32_CLR_SET(SCB_TX_CTRL(base), SCB_TX_CTRL_DATA_WIDTH, (breakWidth - 1UL));
+
+ /* Generate break */
+ Cy_SCB_WriteTxFifo(base, 0UL);
+
+ /* Wait for break completion */
+ while (0UL == (Cy_SCB_GetTxInterruptStatus(base) & CY_SCB_TX_INTR_UART_DONE))
+ {
+ }
+
+ /* Clear all UART TX interrupt sources */
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_MASK);
+
+ /* Restore TX data width and interrupt sources */
+ SCB_TX_CTRL(base) = txCtrlReg;
+ Cy_SCB_SetTxInterruptMask(base, txIntrReg);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Interrupt
+****************************************************************************//**
+*
+* This is the interrupt function for the SCB configured in the UART mode.
+* This function must be called inside a user-defined interrupt service
+* routine to make \ref Cy_SCB_UART_Transmit and \ref Cy_SCB_UART_Receive
+* work. The ring buffer operation that enabled by calling \ref Cy_SCB_UART_StartRingBuffer
+* also requires interrupt processing.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+void Cy_SCB_UART_Interrupt(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ if (0UL != (CY_SCB_RX_INTR & Cy_SCB_GetInterruptCause(base)))
+ {
+ /* Get RX error events: a frame error, parity error, and overflow */
+ uint32_t locRxErr = (CY_SCB_UART_RECEIVE_ERR & Cy_SCB_GetRxInterruptStatusMasked(base));
+
+ /* Handle the error conditions */
+ if (0UL != locRxErr)
+ {
+ context->rxStatus |= locRxErr;
+
+ Cy_SCB_ClearRxInterrupt(base, locRxErr);
+
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_RECEIVE_ERR_EVENT);
+ }
+ }
+
+ /* Break the detect */
+ if (0UL != (CY_SCB_RX_INTR_UART_BREAK_DETECT & Cy_SCB_GetRxInterruptStatusMasked(base)))
+ {
+ context->rxStatus |= CY_SCB_UART_RECEIVE_BREAK_DETECT;
+
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_UART_BREAK_DETECT);
+ }
+
+ /* Copy the received data */
+ if (0UL != (CY_SCB_RX_INTR_LEVEL & Cy_SCB_GetRxInterruptStatusMasked(base)))
+ {
+ if (context->rxBufSize > 0UL)
+ {
+ HandleDataReceive(base, context);
+ }
+ else
+ {
+ if (NULL != context->rxRingBuf)
+ {
+ HandleRingBuffer(base, context);
+ }
+ }
+
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL);
+ }
+
+ if (0UL != (CY_SCB_RX_INTR_NOT_EMPTY & Cy_SCB_GetRxInterruptStatusMasked(base)))
+ {
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_RECEIVE_NOT_EMTPY);
+ }
+
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_NOT_EMPTY);
+ }
+
+ }
+
+ if (0UL != (CY_SCB_TX_INTR & Cy_SCB_GetInterruptCause(base)))
+ {
+ uint32_t locTxErr = (CY_SCB_UART_TRANSMIT_ERR & Cy_SCB_GetTxInterruptStatusMasked(base));
+
+ /* Handle the TX error conditions */
+ if (0UL != locTxErr)
+ {
+ context->txStatus |= locTxErr;
+ Cy_SCB_ClearTxInterrupt(base, locTxErr);
+
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_TRANSMIT_ERR_EVENT);
+ }
+ }
+
+ /* Load data to transmit */
+ if (0UL != (CY_SCB_TX_INTR_LEVEL & Cy_SCB_GetTxInterruptStatusMasked(base)))
+ {
+ HandleDataTransmit(base, context);
+
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL);
+ }
+
+ /* Handle the TX complete */
+ if (0UL != (CY_SCB_TX_INTR_UART_DONE & Cy_SCB_GetTxInterruptStatusMasked(base)))
+ {
+ /* Disable all TX interrupt sources */
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ context->txStatus &= (uint32_t) ~CY_SCB_UART_TRANSMIT_ACTIVE;
+ context->txLeftToTransmit = 0UL;
+
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_TRANSMIT_DONE_EVENT);
+ }
+ }
+
+ if (0UL != (CY_SCB_UART_TX_EMPTY & Cy_SCB_GetTxInterruptStatusMasked(base)))
+ {
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_TRANSMIT_EMTPY);
+ }
+
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_UART_TX_EMPTY);
+ }
+
+ }
+}
+
+
+
+/*******************************************************************************
+* Function Name: HandleDataReceive
+****************************************************************************//**
+*
+* Reads data from the receive FIFO into the buffer provided by
+* \ref Cy_SCB_UART_Receive.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void HandleDataReceive(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ uint32_t numCopied;
+ uint32_t halfFifoSize = Cy_SCB_GetFifoSize(base) / 2UL;
+
+ /* Get data from RX FIFO */
+ numCopied = Cy_SCB_UART_GetArray(base, context->rxBuf, context->rxBufSize);
+
+ /* Move the buffer */
+ context->rxBufIdx += numCopied;
+ context->rxBufSize -= numCopied;
+
+ if (0UL == context->rxBufSize)
+ {
+ if (NULL != context->rxRingBuf)
+ {
+ /* Adjust the level to proceed with the ring buffer */
+ Cy_SCB_SetRxFifoLevel(base, (context->rxRingBufSize >= halfFifoSize) ?
+ (halfFifoSize - 1UL) : (context->rxRingBufSize - 1UL));
+
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL);
+ }
+ else
+ {
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+
+ /* Update the status */
+ context->rxStatus &= (uint32_t) ~CY_SCB_UART_RECEIVE_ACTIVE;
+
+ /* Notify that receive is done in a callback */
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_RECEIVE_DONE_EVENT);
+ }
+ }
+ else
+ {
+ uint8_t *buf = (uint8_t *) context->rxBuf;
+
+ buf = &buf[(Cy_SCB_IsRxDataWidthByte(base) ? (numCopied) : (2UL * numCopied))];
+ context->rxBuf = (void *) buf;
+
+ if (context->rxBufSize < halfFifoSize)
+ {
+ /* Set the RX FIFO level to trigger an interrupt */
+ Cy_SCB_SetRxFifoLevel(base, (context->rxBufSize - 1UL));
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: HandleRingBuffer
+****************************************************************************//**
+*
+* Reads data from the receive FIFO into the receive ring buffer.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void HandleRingBuffer(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ uint32_t halfFifoSize = Cy_SCB_GetFifoSize(base) / 2UL;
+ uint32_t numToCopy = Cy_SCB_GetNumInRxFifo(base);
+ uint32_t locHead = context->rxRingBufHead;
+ uint32_t rxData;
+
+ /* Get data into the ring buffer */
+ while (numToCopy > 0UL)
+ {
+ ++locHead;
+
+ if (locHead == context->rxRingBufSize)
+ {
+ locHead = 0UL;
+ }
+
+ if (locHead == context->rxRingBufTail)
+ {
+ /* The ring buffer is full, trigger a callback */
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_RB_FULL_EVENT);
+ }
+
+ /* The ring buffer is still full. Disable the RX interrupt not to put data into the ring buffer.
+ * The data is stored in the RX FIFO until it overflows. Revert the head index.
+ */
+ if (locHead == context->rxRingBufTail)
+ {
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ locHead = (locHead > 0UL) ? (locHead - 1UL) : (context->rxRingBufSize - 1UL);
+ break;
+ }
+ }
+
+ /* Get data from RX FIFO. */
+ rxData = Cy_SCB_ReadRxFifo(base);
+
+ /* Put a data item in the ring buffer */
+ if (Cy_SCB_IsRxDataWidthByte(base))
+ {
+ ((uint8_t *) context->rxRingBuf)[locHead] = (uint8_t) rxData;
+ }
+ else
+ {
+ ((uint16_t *) context->rxRingBuf)[locHead] = (uint16_t) rxData;
+ }
+
+ --numToCopy;
+ }
+
+ /* Update the head index */
+ context->rxRingBufHead = locHead;
+
+ /* Get free entries in the ring buffer */
+ numToCopy = context->rxRingBufSize - Cy_SCB_UART_GetNumInRingBuffer(base, context);
+
+ if (numToCopy < halfFifoSize)
+ {
+ /* Adjust the level to copy to the ring buffer */
+ uint32_t level = (numToCopy > 0UL) ? (numToCopy - 1UL) : 0UL;
+ Cy_SCB_SetRxFifoLevel(base, level);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: HandleDataTransmit
+****************************************************************************//**
+*
+* Loads the transmit FIFO with data provided by \ref Cy_SCB_UART_Transmit.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ uint32_t numToCopy;
+ uint32_t fifoSize = Cy_SCB_GetFifoSize(base);
+ bool byteMode = Cy_SCB_IsTxDataWidthByte(base);
+
+ if (context->txBufSize > 1UL)
+ {
+ uint8_t *buf = (uint8_t *) context->txBuf;
+
+ /* Get the number of items left for transmission */
+ context->txLeftToTransmit = context->txBufSize;
+
+ /* Put data into TX FIFO */
+ numToCopy = Cy_SCB_UART_PutArray(base, context->txBuf, (context->txBufSize - 1UL));
+
+ /* Move the buffer */
+ context->txBufSize -= numToCopy;
+
+ buf = &buf[(byteMode) ? (numToCopy) : (2UL * numToCopy)];
+ context->txBuf = (void *) buf;
+ }
+
+ /* Put the last data item into TX FIFO */
+ if ((fifoSize != Cy_SCB_GetNumInTxFifo(base)) && (1UL == context->txBufSize))
+ {
+ uint32_t txData;
+ uint32_t intrStatus;
+
+ context->txBufSize = 0UL;
+
+ /* Get the last item from the buffer */
+ txData = (uint32_t) ((byteMode) ? ((uint8_t *) context->txBuf)[0UL] :
+ ((uint16_t *) context->txBuf)[0UL]);
+
+ /* Put the last data element and make sure that "TX done" will happen for it */
+ intrStatus = Cy_SysLib_EnterCriticalSection();
+
+ Cy_SCB_WriteTxFifo(base, txData);
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UART_DONE);
+
+ Cy_SysLib_ExitCriticalSection(intrStatus);
+
+ /* Disable the level interrupt source and enable "transfer done" */
+ Cy_SCB_SetTxInterruptMask(base, (CY_SCB_TX_INTR_UART_DONE |
+ (Cy_SCB_GetTxInterruptMask(base) & (uint32_t) ~CY_SCB_TX_INTR_LEVEL)));
+
+ /* Data is copied into TX FIFO */
+ context->txStatus |= CY_SCB_UART_TRANSMIT_IN_FIFO;
+
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_TRANSMIT_IN_FIFO_EVENT);
+ }
+ }
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_IP_MXSCB */
+
+/* [] END OF FILE */
+
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_sysclk.c b/platform/ext/target/psoc64/Native_Driver/source/cy_sysclk.c
new file mode 100644
index 0000000000..6d49d85fc7
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_sysclk.c
@@ -0,0 +1,1976 @@
+/***************************************************************************//**
+* \file cy_sysclk.c
+* \version 1.40.2
+*
+* Provides an API implementation of the sysclk driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+
+#include "cy_sysclk.h"
+#include "cy_syslib.h"
+#include <stdlib.h>
+
+
+/* ========================================================================== */
+/* ========================= EXTCLK SECTION =========================== */
+/* ========================================================================== */
+
+/** \cond INTERNAL */
+static uint32_t extFreq = 0UL; /* Internal storage for external clock frequency user setting */
+
+#define CY_SYSCLK_EXTCLK_MAX_FREQ (100000000UL) /* 100 MHz */
+/** \endcond */
+
+/**
+* \addtogroup group_sysclk_ext_funcs
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ExtClkSetFrequency
+****************************************************************************//**
+*
+* Sets the signal frequency of the External Clock Source (EXTCLK) into the
+* internal storage to be used in \ref Cy_SysClk_ClkHfGetFrequency.
+*
+* \param freq The frequency of the External Clock Source.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ExtClkSetFrequency
+*
+*******************************************************************************/
+void Cy_SysClk_ExtClkSetFrequency(uint32_t freq)
+{
+ if (freq <= CY_SYSCLK_EXTCLK_MAX_FREQ)
+ {
+ extFreq = freq;
+ }
+}
+/** \} group_sysclk_ext_funcs */
+
+
+/* ========================================================================== */
+/* =========================== ECO SECTION ============================ */
+/* ========================================================================== */
+/** \cond INTERNAL */
+#define CY_SYSCLK_TRIM_ECO_Pos (SRSS_CLK_TRIM_ECO_CTL_WDTRIM_Pos)
+#define CY_SYSCLK_TRIM_ECO_Msk (SRSS_CLK_TRIM_ECO_CTL_WDTRIM_Msk | \
+ SRSS_CLK_TRIM_ECO_CTL_ATRIM_Msk | \
+ SRSS_CLK_TRIM_ECO_CTL_FTRIM_Msk | \
+ SRSS_CLK_TRIM_ECO_CTL_RTRIM_Msk | \
+ SRSS_CLK_TRIM_ECO_CTL_GTRIM_Msk)
+
+
+/*******************************************************************************
+* Function Name: cy_sqrt
+* Calculates square root.
+*******************************************************************************/
+static uint32_t cy_sqrt(uint64_t x);
+static uint32_t cy_sqrt(uint64_t x)
+{
+ uint32_t i;
+ uint32_t res = 0UL;
+ uint32_t add = 0x80000000UL;
+
+ for(i = 0UL; i < 32UL; i++)
+ {
+ uint32_t tmp = res | add;
+
+ if (x >= ((uint64_t)tmp * tmp))
+ {
+ res = tmp;
+ }
+
+ add >>= 1U;
+ }
+
+ return (res);
+}
+
+
+static uint32_t ecoFreq = 0UL; /* Internal storage for ECO frequency user setting */
+/** \endcond */
+
+/**
+* \addtogroup group_sysclk_eco_funcs
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysClk_EcoConfigure
+****************************************************************************//**
+*
+* Configures the external crystal oscillator (ECO) trim bits based on crystal
+* characteristics. This function should be called only when the ECO is disabled.
+*
+* \param freq Operating frequency of the crystal in Hz.
+*
+* \param cLoad Crystal load capacitance in pF.
+*
+* \param esr Effective series resistance of the crystal in ohms.
+*
+* \param driveLevel Crystal drive level in uW.
+*
+* \return Error / status code: \n
+* CY_SYSCLK_SUCCESS - ECO configuration completed successfully \n
+* CY_SYSCLK_BAD_PARAM - One or more invalid parameters \n
+* CY_SYSCLK_INVALID_STATE - ECO already enabled
+*
+* \note
+* The following calculations are implemented, generally in floating point:
+*
+* \verbatim
+* freqMHz = freq / 1000000
+* max amplitude Vpp = 1000 * sqrt(drivelevel / 2 / esr) / 3.14 / freqMHz / cLoad
+* gm_min mA/V = 5 * 4 * 3.14 * 3.14 * freqMhz^2 * cLoad^2 * 4 * esr / 1000000000
+* Number of amplifier sections = INT(gm_min / 4.5)
+*
+* As a result of the above calculations, max amplitude must be >= 0.5, and the
+* number of amplifier sections must be <= 3, otherwise this function returns with
+* a parameter error.
+*
+* atrim = if (max amplitude < 0.5) then error
+* else 2 * the following:
+* max amplitude < 0.6: 0
+* max amplitude < 0.7: 1
+* max amplitude < 0.8: 2
+* max amplitude < 0.9: 3
+* max amplitude < 1.15: 5
+* max amplitude < 1.275: 6
+* max amplitude >= 1.275: 7
+* wdtrim = if (max amplitude < 0.5) then error
+* else 2 * the following:
+* max amplitude < 1.2: INT(5 * max amplitude) - 2
+* max amplitude >= 1.2: 3
+* gtrim = if (number of amplifier sections > 3) then error
+* else the following:
+* number of amplifier sections > 1: number of amplifier sections
+* number of amplifier sections = 1: 0
+* number of amplifier sections < 1: 1
+* rtrim = if (gtrim = error) then error
+* else the following:
+* freqMHz > 26.8: 0
+* freqMHz > 23.33: 1
+* freqMHz > 16.5: 2
+* freqMHz <= 16.5: 3
+* ftrim = if (atrim = error) then error
+* else INT(atrim / 2)
+* \endverbatim
+*
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoConfigure
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint32_t esr, uint32_t driveLevel)
+{
+ /* error if ECO is not disabled - any of the 3 enable bits are set */
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_INVALID_STATE;
+ if (0UL == (SRSS_CLK_ECO_CONFIG_ECO_EN_Msk & SRSS_CLK_ECO_CONFIG))
+ {
+ /* calculate intermediate values */
+ uint32_t maxAmplitude = (uint32_t)CY_SYSLIB_DIV_ROUND((1000000000000ULL * /* 1000000.0f * 1000.0f * 10^3 */
+ cy_sqrt(CY_SYSLIB_DIV_ROUND(500000ULL * (uint64_t)driveLevel, (uint64_t)esr))),
+ (3141ULL * (uint64_t)freq * (uint64_t)cLoad)); /* The result is scaled by 10^3 */
+
+ uint32_t nAmpSections = (uint32_t)CY_SYSLIB_DIV_ROUND((uint64_t)freq *
+ (uint64_t)freq *
+ (uint64_t)cLoad *
+ (uint64_t)cLoad, 5704868154158ULL); /* (4.5 * (10^15) / 788.8), the result is scaled by 10^6 */
+
+ if ((maxAmplitude < 500UL) && (nAmpSections > 3000000UL))
+ {
+ /* Error if input parameters cause erroneous intermediate values */
+ retVal = CY_SYSCLK_BAD_PARAM;
+ }
+ else
+ {
+ uint32_t atrim = (maxAmplitude < 600UL) ? 0UL :
+ ((maxAmplitude < 700UL) ? 2UL :
+ ((maxAmplitude < 800UL) ? 4UL :
+ ((maxAmplitude < 900UL) ? 6UL :
+ ((maxAmplitude < 1150UL) ? 10UL :
+ ((maxAmplitude < 1275UL) ? 12UL : 14UL)))));
+
+ uint32_t wdtrim = (maxAmplitude < 1200UL) ? ((maxAmplitude / 100UL) - 4UL) : 6UL;
+
+ uint32_t gtrim = ((nAmpSections > 1000000UL) ? CY_SYSLIB_DIV_ROUND(nAmpSections, 1000000UL) :
+ ((nAmpSections == 1000000UL) ? 0UL : 1UL));
+
+ uint32_t rtrim = ((freq > 26800000UL) ? 0UL :
+ ((freq > 23330000UL) ? 1UL :
+ ((freq > 16500000UL) ? 2UL : 3UL)));
+
+ /* Update all fields of trim control register with one write, without changing the ITRIM field */
+ uint32_t reg = _VAL2FLD(SRSS_CLK_TRIM_ECO_CTL_WDTRIM, wdtrim) |
+ _VAL2FLD(SRSS_CLK_TRIM_ECO_CTL_ATRIM, atrim) |
+ _VAL2FLD(SRSS_CLK_TRIM_ECO_CTL_FTRIM, atrim / 2UL)|
+ _VAL2FLD(SRSS_CLK_TRIM_ECO_CTL_RTRIM, rtrim) |
+ _VAL2FLD(SRSS_CLK_TRIM_ECO_CTL_GTRIM, gtrim);
+
+ CY_REG32_CLR_SET(SRSS_CLK_TRIM_ECO_CTL, CY_SYSCLK_TRIM_ECO, reg);
+
+ ecoFreq = freq; /* Store ECO frequency */
+
+ retVal = CY_SYSCLK_SUCCESS;
+ } /* if valid parameters */
+ } /* if ECO not enabled */
+
+ return (retVal);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_EcoEnable
+****************************************************************************//**
+*
+* Enables the external crystal oscillator (ECO). This function should be called
+* after \ref Cy_SysClk_EcoConfigure.
+*
+* \param timeoutus Amount of time in microseconds to wait for the ECO to stabilize.
+* To avoid waiting for stabilization, set this parameter to 0.
+*
+* \return Error / status code: \n
+* CY_SYSCLK_SUCCESS - ECO locked \n
+* CY_SYSCLK_TIMEOUT - ECO timed out and did not lock \n
+* CY_SYSCLK_INVALID_STATE - ECO already enabled
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling
+* if it affects the CLK_HF0 frequency.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoEnable
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_INVALID_STATE;
+ bool zeroTimeout = (0UL == timeoutus);
+
+ /* Invalid state error if ECO is already enabled */
+ if (0UL == (SRSS_CLK_ECO_CONFIG_ECO_EN_Msk & SRSS_CLK_ECO_CONFIG))
+ {
+ /* Set ECO enable */
+ SRSS_CLK_ECO_CONFIG |= SRSS_CLK_ECO_CONFIG_ECO_EN_Msk;
+
+ /* Wait for CY_SYSCLK_ECOSTAT_STABLE */
+ for (; (CY_SYSCLK_ECOSTAT_STABLE != Cy_SysClk_EcoGetStatus()) && (0UL != timeoutus); timeoutus--)
+ {
+ Cy_SysLib_DelayUs(1U);
+ }
+
+ retVal = (zeroTimeout || (0UL != timeoutus)) ? CY_SYSCLK_SUCCESS : CY_SYSCLK_TIMEOUT;
+ }
+
+ return (retVal);
+}
+/** \} group_sysclk_eco_funcs */
+
+
+/* ========================================================================== */
+/* ==================== INPUT MULTIPLEXER SECTION ===================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_path_src_funcs
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPathSetSource
+****************************************************************************//**
+*
+* Configures the source for the specified clock path.
+*
+* \param clkPath Selects which clock path to configure; 0 is the first clock
+* path, which is the FLL.
+*
+* \param source \ref cy_en_clkpath_in_sources_t
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \note
+* If calling this function changes an FLL or PLL input frequency, disable the FLL
+* or PLL before calling this function. After calling this function, call the FLL
+* or PLL configure function, for example \ref Cy_SysClk_FllConfigure().
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling
+* if it affects the CLK_HF0 frequency.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates before calling this function if
+* it affects the CLK_HF0 frequency and the frequency is increasing.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates after calling this function if
+* it affects the CLK_HF0 frequency and the frequency is decreasing.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ if ((clkPath < CY_SRSS_NUM_CLKPATH) &&
+ ((source <= CY_SYSCLK_CLKPATH_IN_DSIMUX) ||
+ ((CY_SYSCLK_CLKPATH_IN_DSI <= source) && (source <= CY_SYSCLK_CLKPATH_IN_PILO))))
+ {
+ if (source >= CY_SYSCLK_CLKPATH_IN_DSI)
+ {
+ SRSS_CLK_DSI_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_DSI_SELECT_DSI_MUX, (uint32_t)source);
+ SRSS_CLK_PATH_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_PATH_SELECT_PATH_MUX, (uint32_t)CY_SYSCLK_CLKPATH_IN_DSIMUX);
+ }
+ else
+ {
+ SRSS_CLK_PATH_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_PATH_SELECT_PATH_MUX, (uint32_t)source);
+ }
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ return (retVal);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPathGetSource
+****************************************************************************//**
+*
+* Reports which source is selected for the path mux.
+*
+* \param clkPath Selects which clock path to report; 0 is the first clock path,
+* which is the FLL.
+*
+* \return \ref cy_en_clkpath_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathGetSource
+*
+*******************************************************************************/
+cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath)
+{
+ CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH);
+ cy_en_clkpath_in_sources_t retVal =
+ (cy_en_clkpath_in_sources_t )_FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS_CLK_PATH_SELECT[clkPath]);
+ if (retVal == CY_SYSCLK_CLKPATH_IN_DSIMUX)
+ {
+ retVal = (cy_en_clkpath_in_sources_t)(CY_SYSCLK_CLKPATH_IN_DSI |
+ (_FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS_CLK_DSI_SELECT[clkPath])));
+ }
+ return (retVal);
+}
+/** \} group_sysclk_path_src_funcs */
+
+
+/* ========================================================================== */
+/* =========================== FLL SECTION ============================ */
+/* ========================================================================== */
+/* min and max FLL output frequencies, in Hz */
+#define CY_SYSCLK_FLL_MIN_CCO_OUTPUT_FREQ (48000000UL)
+#define CY_SYSCLK_FLL_MIN_OUTPUT_FREQ (CY_SYSCLK_FLL_MIN_CCO_OUTPUT_FREQ / 2U)
+#define CY_SYSCLK_FLL_MAX_OUTPUT_FREQ (100000000UL)
+
+#define CY_SYSCLK_FLL_IS_CCO_RANGE_VALID(range) (((range) == CY_SYSCLK_FLL_CCO_RANGE0) || \
+ ((range) == CY_SYSCLK_FLL_CCO_RANGE1) || \
+ ((range) == CY_SYSCLK_FLL_CCO_RANGE2) || \
+ ((range) == CY_SYSCLK_FLL_CCO_RANGE3) || \
+ ((range) == CY_SYSCLK_FLL_CCO_RANGE4))
+/** \cond INTERNAL */
+#define CY_SYSCLK_FLL_INT_COEF (327680000UL)
+#define CY_SYSCLK_FLL_GAIN_IDX (11U)
+#define CY_SYSCLK_FLL_GAIN_VAL (8UL * CY_SYSCLK_FLL_INT_COEF)
+
+#define TRIM_STEPS_SCALE (100000000ULL) /* 10 ^ 8 */
+#define MARGIN_SCALE (100000ULL) /* 10 ^ 5 */
+/** \endcond */
+
+
+/**
+* \addtogroup group_sysclk_fll_funcs
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllConfigure
+****************************************************************************//**
+*
+* Configures the FLL, for best accuracy optimization.
+*
+* \param inputFreq frequency of input source, in Hz
+*
+* \param outputFreq Desired FLL output frequency, in Hz. Allowable range is
+* 24 MHz to 100 MHz. In all cases, FLL_OUTPUT_DIV must be set; the output divide
+* by 2 option is required.
+*
+* \param outputMode \ref cy_en_fll_pll_output_mode_t
+* If output mode is bypass, then the output frequency equals the input source
+* frequency regardless of the frequency parameter values.
+*
+* \return Error / status code: \n
+* CY_SYSCLK_SUCCESS - FLL successfully configured \n
+* CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled \n
+* CY_SYSCLK_BAD_PARAM - desired output frequency is out of valid range
+*
+* \note
+* Call this function after changing the FLL input frequency, for example if
+* \ref Cy_SysClk_ClkPathSetSource() is called.
+*
+* \note
+* Do not call this function when the FLL is enabled. If it is called, then this function
+* returns with an CY_SYSCLK_INVALID_STATE return value and no register updates.
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling
+* if it affects the CLK_HF0 frequency.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates before calling this function if
+* the FLL is the source of CLK_HF0 and the FLL frequency is increasing.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates after calling this function if
+* the FLL is the source of CLK_HF0 and the FLL frequency is decreasing.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllConfigure
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_SUCCESS;
+
+ /* check for errors */
+ if ((outputFreq < CY_SYSCLK_FLL_MIN_OUTPUT_FREQ) || (CY_SYSCLK_FLL_MAX_OUTPUT_FREQ < outputFreq) || /* invalid output frequency */
+ (((outputFreq * 5UL) / inputFreq) < 11UL)) /* check output/input frequency ratio */
+ {
+ retVal = CY_SYSCLK_BAD_PARAM;
+ }
+ else /* no errors */
+ {
+ /* If output mode is bypass (input routed directly to output), then done.
+ The output frequency equals the input frequency regardless of the
+ frequency parameters. */
+ if (outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)
+ {
+ cy_stc_fll_manual_config_t config;
+ uint32_t ccoFreq;
+ bool wcoSource = (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(0UL/*FLL*/)) ? true : false;
+
+ config.outputMode = outputMode;
+ /* 1. Output division by 2 is always required */
+ config.enableOutputDiv = true;
+ /* 2. Compute the target CCO frequency from the target output frequency and output division */
+ ccoFreq = outputFreq * 2UL;
+ /* 3. Compute the CCO range value from the CCO frequency */
+ config.ccoRange = ((ccoFreq >= 150339200UL) ? CY_SYSCLK_FLL_CCO_RANGE4 :
+ ((ccoFreq >= 113009380UL) ? CY_SYSCLK_FLL_CCO_RANGE3 :
+ ((ccoFreq >= 84948700UL) ? CY_SYSCLK_FLL_CCO_RANGE2 :
+ ((ccoFreq >= 63855600UL) ? CY_SYSCLK_FLL_CCO_RANGE1 : CY_SYSCLK_FLL_CCO_RANGE0))));
+
+ /* 4. Compute the FLL reference divider value.
+ refDiv is a constant if the WCO is the FLL source, otherwise the formula is
+ refDiv = ROUNDUP((inputFreq / outputFreq) * 250) */
+ config.refDiv = wcoSource ? 19U : (uint16_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)inputFreq * 250ULL, (uint64_t)outputFreq);
+
+ /* 5. Compute the FLL multiplier value.
+ Formula is fllMult = ccoFreq / (inputFreq / refDiv) */
+ config.fllMult = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)ccoFreq * (uint64_t)config.refDiv, (uint64_t)inputFreq);
+ /* 6. Compute the lock tolerance.
+ Formula is lock tolerance = 1.5 * fllMult * (((1 + CCO accuracy) / (1 - source clock accuracy)) - 1)
+ We assume CCO accuracy is 0.25%.
+ We assume the source clock accuracy = 1%. This is the accuracy of the IMO.
+ Therefore the formula is lock tolerance = 1.5 * fllMult * 0.012626 = 0.018939 * fllMult */
+ config.lockTolerance = (uint16_t)CY_SYSLIB_DIV_ROUNDUP(config.fllMult * 18939UL, 1000000UL);
+
+ {
+ /* constants indexed by ccoRange */
+ const uint32_t trimSteps[] = {110340UL, 110200UL, 110000UL, 110000UL, 117062UL}; /* Scaled by 10^8 */
+ const uint32_t margin[] = {436UL, 581UL, 772UL, 1030UL, 1320UL}; /* Scaled by 10^5 */
+ /* 7. Compute the CCO igain and pgain */
+ {
+ /* intermediate parameters */
+ uint32_t kcco = (trimSteps[config.ccoRange] * margin[config.ccoRange]);
+ uint32_t ki_p = (uint32_t)CY_SYSLIB_DIV_ROUND(850ULL * CY_SYSCLK_FLL_INT_COEF * inputFreq, (uint64_t)kcco * (uint64_t)config.refDiv);
+
+ /* find the largest IGAIN value that is less than or equal to ki_p */
+ uint32_t locigain = CY_SYSCLK_FLL_GAIN_VAL;
+ uint32_t locpgain = CY_SYSCLK_FLL_GAIN_VAL;
+
+ /* find the largest IGAIN value that is less than or equal to ki_p */
+ for(config.igain = CY_SYSCLK_FLL_GAIN_IDX; (locigain > ki_p) && (config.igain != 0UL); config.igain--)
+ {
+ locigain >>= 1U;
+ }
+ /* decrement igain if the WCO is the FLL source */
+ if (wcoSource && (config.igain > 0U))
+ {
+ config.igain--;
+ locigain >>= 1U;
+ }
+
+ /* then find the largest PGAIN value that is less than or equal to ki_p - igain */
+ for(config.pgain = CY_SYSCLK_FLL_GAIN_IDX; (locpgain > (ki_p - locigain)) && (config.pgain != 0UL); config.pgain--)
+ {
+ locpgain >>= 1U;
+ }
+ /* decrement pgain if the WCO is the FLL source */
+ if (wcoSource && (config.pgain > 0U))
+ {
+ config.pgain--;
+ }
+ }
+
+ /* 8. Compute the CCO_FREQ bits in CLK_FLL_CONFIG4 register */
+ {
+ uint64_t cmp = CY_SYSLIB_DIV_ROUND(((TRIM_STEPS_SCALE / MARGIN_SCALE) * (uint64_t)ccoFreq), (uint64_t)margin[config.ccoRange]);
+ uint64_t mlt = TRIM_STEPS_SCALE + (uint64_t)trimSteps[config.ccoRange];
+ uint64_t res = mlt;
+
+ config.cco_Freq = 0U;
+
+ while(res < cmp)
+ {
+ res *= mlt;
+ res /= TRIM_STEPS_SCALE;
+ config.cco_Freq++;
+ }
+ }
+ }
+
+ /* 9. Compute the settling count, using a 1 usec settling time. Use a constant if the WCO is the FLL source */
+ {
+ uint64_t fref = CY_SYSLIB_DIV_ROUND(6000ULL * (uint64_t)inputFreq, (uint64_t)config.refDiv);
+ uint32_t divval = CY_SYSLIB_DIV_ROUNDUP(inputFreq, 1000000UL);
+ uint32_t altval = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)divval * fref, 6000000ULL) + 1UL;
+
+ config.settlingCount = wcoSource ? 200U : (uint16_t)
+ ((outputFreq < fref) ? divval :
+ ((divval > altval) ? divval : altval));
+ }
+ /* Configure FLL based on calculated values */
+ retVal = Cy_SysClk_FllManualConfigure(&config);
+ }
+ else /* if not, bypass output mode */
+ {
+ CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT);
+ }
+ }
+
+ return (retVal);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllManualConfigure
+****************************************************************************//**
+*
+* Manually configures the FLL based on user inputs.
+*
+* \param config \ref cy_stc_fll_manual_config_t
+*
+* \return Error / status code: \n
+* CY_SYSCLK_SUCCESS - FLL successfully configured \n
+* CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled
+*
+* \note
+* Call this function after changing the FLL input frequency, for example if
+* \ref Cy_SysClk_ClkPathSetSource() is called.
+*
+* \note
+* Do not call this function when the FLL is enabled. If it is called, then this function
+* returns immediately with an CY_SYSCLK_INVALID_STATE return value and no register updates.
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling
+* if it affects the CLK_HF0 frequency.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates before calling this function if
+* the FLL is the source of CLK_HF0 and the FLL frequency is increasing.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates after calling this function if
+* the FLL is the source of CLK_HF0 and the FLL frequency is decreasing.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllManualConfigure
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_INVALID_STATE;
+
+ /* Check for errors */
+ CY_ASSERT_L1(config != NULL);
+
+ if (!Cy_SysClk_FllIsEnabled()) /* If disabled */
+ {
+ /* update CLK_FLL_CONFIG register with 2 parameters; FLL_ENABLE is already 0 */
+ /* asserts just check for bitfield overflow */
+ CY_ASSERT_L1(config->fllMult <= (SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk >> SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos));
+
+ SRSS_CLK_FLL_CONFIG = _VAL2FLD(SRSS_CLK_FLL_CONFIG_FLL_MULT, config->fllMult) |
+ _BOOL2FLD(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, config->enableOutputDiv);
+
+ /* update CLK_FLL_CONFIG2 register with 2 parameters */
+ /* asserts just check for bitfield overflow */
+ CY_ASSERT_L1(config->refDiv <= (SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk >> SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos));
+ CY_ASSERT_L1(config->lockTolerance <= (SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk >> SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos));
+
+ SRSS_CLK_FLL_CONFIG2 = _VAL2FLD(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, config->refDiv) |
+ _VAL2FLD(SRSS_CLK_FLL_CONFIG2_LOCK_TOL, config->lockTolerance);
+
+ /* update CLK_FLL_CONFIG3 register with 4 parameters */
+ /* asserts just check for bitfield overflow */
+ CY_ASSERT_L1(config->igain <= (SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk >> SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos));
+ CY_ASSERT_L1(config->pgain <= (SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk >> SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos));
+ CY_ASSERT_L1(config->settlingCount <= (SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk >> SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos));
+
+ SRSS_CLK_FLL_CONFIG3 = _VAL2FLD(SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN, config->igain) |
+ _VAL2FLD(SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN, config->pgain) |
+ _VAL2FLD(SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT, config->settlingCount) |
+ _VAL2FLD(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, config->outputMode);
+
+ /* update CLK_FLL_CONFIG4 register with 1 parameter; preserve other bits */
+ /* asserts just check for bitfield overflow */
+ CY_ASSERT_L1(CY_SYSCLK_FLL_IS_CCO_RANGE_VALID(config->ccoRange));
+ CY_ASSERT_L1(config->cco_Freq <= (SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk >> SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos));
+
+ CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_RANGE, (uint32_t)(config->ccoRange));
+ CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_FREQ, (uint32_t)(config->cco_Freq));
+
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+
+ return (retVal);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllGetConfiguration
+****************************************************************************//**
+*
+* Reports the FLL configuration settings.
+*
+* \param config \ref cy_stc_fll_manual_config_t
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllGetConfiguration
+*
+*******************************************************************************/
+void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config)
+{
+ CY_ASSERT_L1(config != NULL);
+ /* read 2 parameters from CLK_FLL_CONFIG register */
+ uint32_t tempReg = SRSS_CLK_FLL_CONFIG;
+ config->fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, tempReg);
+ config->enableOutputDiv = _FLD2BOOL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, tempReg);
+ /* read 2 parameters from CLK_FLL_CONFIG2 register */
+ tempReg = SRSS_CLK_FLL_CONFIG2;
+ config->refDiv = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, tempReg);
+ config->lockTolerance = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG2_LOCK_TOL, tempReg);
+ /* read 4 parameters from CLK_FLL_CONFIG3 register */
+ tempReg = SRSS_CLK_FLL_CONFIG3;
+ config->igain = (uint8_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN, tempReg);
+ config->pgain = (uint8_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN, tempReg);
+ config->settlingCount = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT, tempReg);
+ config->outputMode = (cy_en_fll_pll_output_mode_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, tempReg);
+ /* read 2 parameters from CLK_FLL_CONFIG4 register */
+ tempReg = SRSS_CLK_FLL_CONFIG4;
+ config->ccoRange = (cy_en_fll_cco_ranges_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG4_CCO_RANGE, tempReg);
+ config->cco_Freq = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG4_CCO_FREQ, tempReg);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllEnable
+****************************************************************************//**
+*
+* Enables the FLL. The FLL should be configured before calling this function.
+*
+* \param timeoutus Amount of time in micro seconds to wait for FLL to lock.
+* If lock doesn't occur, the FLL is stopped. To avoid waiting for lock, set this to 0
+* and manually check for lock using \ref Cy_SysClk_FllLocked.
+*
+* \return Error / status code: \n
+* CY_SYSCLK_SUCCESS - FLL successfully enabled \n
+* CY_SYSCLK_TIMEOUT - Timeout waiting for FLL lock
+*
+* \note
+* While waiting for the FLL to lock, the FLL bypass mode is set to \ref CY_SYSCLK_FLLPLL_OUTPUT_INPUT.
+* After the FLL is locked, the FLL bypass mdoe is then set to \ref CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT.
+*
+* \note
+* Call \ref SystemCoreClockUpdate after calling this function
+* if it affects the CLK_HF0 frequency.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates before calling this function if
+* the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllEnable
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus)
+{
+ bool zeroTimeout = (0UL == timeoutus);
+
+ /* first set the CCO enable bit */
+ SRSS_CLK_FLL_CONFIG4 |= SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk;
+
+ /* Wait until CCO is ready */
+ for (; (!_FLD2BOOL(SRSS_CLK_FLL_STATUS_CCO_READY, SRSS_CLK_FLL_STATUS)) && /* if cco_ready == 0 */
+ (0UL != timeoutus);
+ timeoutus--)
+ {
+ Cy_SysLib_DelayUs(1U);
+ }
+
+ /* Set the FLL bypass mode to FLL_REF */
+ CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT);
+
+ /* Set the FLL enable bit, if CCO is ready */
+ if (zeroTimeout || (0UL != timeoutus))
+ {
+ SRSS_CLK_FLL_CONFIG |= SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
+ }
+
+ /* now do the timeout wait for FLL_STATUS, bit LOCKED */
+ for (; (!Cy_SysClk_FllLocked()) && /* if locked == 0 */
+ (0UL != timeoutus);
+ timeoutus--)
+ {
+ Cy_SysLib_DelayUs(1U);
+ }
+
+ if (zeroTimeout || (0UL != timeoutus))
+ {
+ /* Set the FLL bypass mode to FLL_OUT (ignoring lock indicator) */
+ CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT);
+ }
+ else
+ {
+ /* If lock doesn't occur, FLL is stopped */
+ (void)Cy_SysClk_FllDisable();
+ }
+
+ return ((zeroTimeout || (0UL != timeoutus)) ? CY_SYSCLK_SUCCESS : CY_SYSCLK_TIMEOUT);
+}
+/** \} group_sysclk_fll_funcs */
+
+
+/* ========================================================================== */
+/* =========================== PLL SECTION ============================ */
+/* ========================================================================== */
+
+/* PLL OUTPUT_DIV bitfield allowable range */
+#define CY_SYSCLK_PLL_MIN_OUTPUT_DIV (2UL)
+#define CY_SYSCLK_PLL_MAX_OUTPUT_DIV (16UL)
+
+/* PLL REFERENCE_DIV bitfield allowable range */
+#define CY_SYSCLK_PLL_MIN_REF_DIV (1UL)
+#define CY_SYSCLK_PLL_MAX_REF_DIV (18UL)
+
+/* PLL FEEDBACK_DIV bitfield allowable ranges, LF and normal modes */
+#define CY_SYSCLK_PLL_MIN_FB_DIV_LF (19UL)
+#define CY_SYSCLK_PLL_MAX_FB_DIV_LF (56UL)
+#define CY_SYSCLK_PLL_MIN_FB_DIV_NORM (22UL)
+#define CY_SYSCLK_PLL_MAX_FB_DIV_NORM (112UL)
+
+/* PLL FEEDBACK_DIV bitfield allowable range selection */
+#define CY_SYSCLK_PLL_MIN_FB_DIV ((config->lfMode) ? CY_SYSCLK_PLL_MIN_FB_DIV_LF : CY_SYSCLK_PLL_MIN_FB_DIV_NORM)
+#define CY_SYSCLK_PLL_MAX_FB_DIV ((config->lfMode) ? CY_SYSCLK_PLL_MAX_FB_DIV_LF : CY_SYSCLK_PLL_MAX_FB_DIV_NORM)
+
+/* PLL Fvco range allowable ranges, LF and normal modes */
+#define CY_SYSCLK_PLL_MIN_FVCO_LF (170000000UL)
+#define CY_SYSCLK_PLL_MAX_FVCO_LF (200000000UL)
+#define CY_SYSCLK_PLL_MIN_FVCO_NORM (200000000UL)
+#define CY_SYSCLK_PLL_MAX_FVCO_NORM (400000000UL)
+/* PLL Fvco range selection */
+#define CY_SYSCLK_PLL_MIN_FVCO ((config->lfMode) ? CY_SYSCLK_PLL_MIN_FVCO_LF : CY_SYSCLK_PLL_MIN_FVCO_NORM)
+#define CY_SYSCLK_PLL_MAX_FVCO ((config->lfMode) ? CY_SYSCLK_PLL_MAX_FVCO_LF : CY_SYSCLK_PLL_MAX_FVCO_NORM)
+
+/* PLL input and output frequency limits */
+#define CY_SYSCLK_PLL_MIN_IN_FREQ (4000000UL)
+#define CY_SYSCLK_PLL_MAX_IN_FREQ (64000000UL)
+#define CY_SYSCLK_PLL_MIN_OUT_FREQ (CY_SYSCLK_PLL_MIN_FVCO / CY_SYSCLK_PLL_MAX_OUTPUT_DIV)
+#define CY_SYSCLK_PLL_MAX_OUT_FREQ (150000000UL)
+
+/**
+* \addtogroup group_sysclk_pll_funcs
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllConfigure
+****************************************************************************//**
+*
+* Configures a given PLL.
+* The configuration formula used is:
+* Fout = pll_clk * (P / Q / div_out), where:
+* Fout is the desired output frequency
+* pll_clk is the frequency of the input source
+* P is the feedback divider. Its value is in bitfield FEEDBACK_DIV.
+* Q is the reference divider. Its value is in bitfield REFERENCE_DIV.
+* div_out is the reference divider. Its value is in bitfield OUTPUT_DIV.
+*
+* \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid.
+*
+* \param config \ref cy_stc_pll_config_t
+*
+* \return Error / status code: \n
+* CY_SYSCLK_SUCCESS - PLL successfully configured \n
+* CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled \n
+* CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range
+*
+* \note
+* Call this function after changing the PLL input frequency, for example if
+* \ref Cy_SysClk_ClkPathSetSource() is called.
+*
+* \note
+* Do not call this function when the PLL is enabled. If it is called, then this function
+* returns immediately with an error return value and no register updates.
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling
+* if it affects the CLK_HF0 frequency.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates before calling this function if
+* the PLL is the source of CLK_HF0 and the PLL frequency is increasing.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates after calling this function if
+* the PLL is the source of CLK_HF0 and the PLL frequency is decreasing.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllConfigure
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_config_t *config)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_SUCCESS;
+
+ if (((config->inputFreq) < CY_SYSCLK_PLL_MIN_IN_FREQ) || (CY_SYSCLK_PLL_MAX_IN_FREQ < (config->inputFreq)) ||
+ ((config->outputFreq) < CY_SYSCLK_PLL_MIN_OUT_FREQ) || (CY_SYSCLK_PLL_MAX_OUT_FREQ < (config->outputFreq)))
+ {
+ retVal = CY_SYSCLK_BAD_PARAM;
+ }
+ else
+ {
+ cy_stc_pll_manual_config_t manualConfig = {0U, 0U, 0U, false, CY_SYSCLK_FLLPLL_OUTPUT_AUTO};
+
+ /* If output mode is not bypass (input routed directly to output), then
+ calculate new parameters. */
+ if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)
+ {
+ /* for each possible value of OUTPUT_DIV and REFERENCE_DIV (Q), try
+ to find a value for FEEDBACK_DIV (P) that gives an output frequency
+ as close as possible to the desired output frequency. */
+ uint32_t p, q, out;
+ uint32_t foutBest = 0UL; /* to ensure at least one pass through the for loops below */
+
+ /* REFERENCE_DIV (Q) selection */
+ for (q = CY_SYSCLK_PLL_MIN_REF_DIV; (q <= CY_SYSCLK_PLL_MAX_REF_DIV) && (foutBest != (config->outputFreq)); q++)
+ {
+ /* FEEDBACK_DIV (P) selection */
+ for (p = CY_SYSCLK_PLL_MIN_FB_DIV; (p <= CY_SYSCLK_PLL_MAX_FB_DIV) && (foutBest != (config->outputFreq)); p++)
+ {
+ /* Calculate the intermediate Fvco, and make sure that it's in range */
+ uint32_t fvco = (uint32_t)(((uint64_t)(config->inputFreq) * (uint64_t)p) / (uint64_t)q);
+ if ((CY_SYSCLK_PLL_MIN_FVCO <= fvco) && (fvco <= CY_SYSCLK_PLL_MAX_FVCO))
+ {
+ /* OUTPUT_DIV selection */
+ for (out = CY_SYSCLK_PLL_MIN_OUTPUT_DIV; (out <= CY_SYSCLK_PLL_MAX_OUTPUT_DIV) && (foutBest != (config->outputFreq)); out++)
+ {
+ /* Calculate what output frequency will actually be produced.
+ If it's closer to the target than what we have so far, then save it. */
+ uint32_t fout = ((p * config->inputFreq) / q) / out;
+ if ((uint32_t)abs((int32_t)fout - (int32_t)(config->outputFreq)) <
+ (uint32_t)abs((int32_t)foutBest - (int32_t)(config->outputFreq)))
+ {
+ foutBest = fout;
+ manualConfig.feedbackDiv = (uint8_t)p;
+ manualConfig.referenceDiv = (uint8_t)q;
+ manualConfig.outputDiv = (uint8_t)out;
+ }
+ }
+ }
+ }
+ }
+ /* exit loops if foutBest equals outputFreq */
+
+ manualConfig.lfMode = config->lfMode;
+ } /* if not, bypass output mode */
+
+ /* If output mode is bypass (input routed directly to output), then
+ use old parameters. */
+ else
+ {
+ (void)Cy_SysClk_PllGetConfiguration(clkPath, &manualConfig);
+ }
+ /* configure PLL based on calculated values */
+
+ manualConfig.outputMode = config->outputMode;
+ retVal = Cy_SysClk_PllManualConfigure(clkPath, &manualConfig);
+
+ } /* if no error */
+
+ return (retVal);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllManualConfigure
+****************************************************************************//**
+*
+* Manually configures a PLL based on user inputs.
+*
+* \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid.
+*
+* \param config \ref cy_stc_pll_manual_config_t
+*
+* \return Error / status code: \n
+* CY_SYSCLK_SUCCESS - PLL successfully configured \n
+* CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled \n
+* CY_SYSCLK_BAD_PARAM - invalid clock path number
+*
+* \note
+* Call this function after changing the PLL input frequency; for example if
+* \ref Cy_SysClk_ClkPathSetSource() is called.
+*
+* \note
+* Do not call this function when the PLL is enabled. If it is called, then this function
+* returns immediately with an error return value and no register updates.
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling
+* if it affects the CLK_HF0 frequency.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates before calling this function if
+* the PLL is the source of CLK_HF0 and the PLL frequency is increasing.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates after calling this function if
+* the PLL is the source of CLK_HF0 and the PLL frequency is decreasing.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllManualConfigure
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t *config)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_SUCCESS;
+
+ /* check for errors */
+ if (clkPath > CY_SRSS_NUM_PLL) /* invalid clock path number */
+ {
+ retVal = CY_SYSCLK_BAD_PARAM;
+ }
+ else if (Cy_SysClk_PllIsEnabled(clkPath))
+ {
+ retVal = CY_SYSCLK_INVALID_STATE;
+ }
+ /* valid divider bitfield values */
+ else if ((config->outputDiv < CY_SYSCLK_PLL_MIN_OUTPUT_DIV) || (CY_SYSCLK_PLL_MAX_OUTPUT_DIV < config->outputDiv) ||
+ (config->referenceDiv < CY_SYSCLK_PLL_MIN_REF_DIV) || (CY_SYSCLK_PLL_MAX_REF_DIV < config->referenceDiv) ||
+ (config->feedbackDiv < CY_SYSCLK_PLL_MIN_FB_DIV) || (CY_SYSCLK_PLL_MAX_FB_DIV < config->feedbackDiv))
+ {
+ retVal = CY_SYSCLK_BAD_PARAM;
+ }
+ else /* no errors */
+ {
+ clkPath--; /* to correctly access PLL config registers structure */
+ /* If output mode is bypass (input routed directly to output), then done.
+ The output frequency equals the input frequency regardless of the frequency parameters. */
+ if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)
+ {
+ SRSS_CLK_PLL_CONFIG[clkPath] =
+ _VAL2FLD(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, config->feedbackDiv) |
+ _VAL2FLD(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, config->referenceDiv) |
+ _VAL2FLD(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, config->outputDiv) |
+ _VAL2FLD(SRSS_CLK_PLL_CONFIG_PLL_LF_MODE, config->lfMode);
+ }
+
+ CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, (uint32_t)config->outputMode);
+ }
+
+ return (retVal);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllGetConfiguration
+****************************************************************************//**
+*
+* Reports configuration settings for a PLL.
+*
+* \param clkPath Selects which PLL to report. 1 is the first PLL; 0 is invalid.
+*
+* \param config \ref cy_stc_pll_manual_config_t
+*
+* \return Error / status code: \n
+* CY_SYSCLK_SUCCESS - PLL data successfully reported \n
+* CY_SYSCLK_BAD_PARAM - invalid clock path number
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllGetConfiguration
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll_manual_config_t *config)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ clkPath--; /* to correctly access PLL config and status register structures */
+ if (clkPath < CY_SRSS_NUM_PLL)
+ {
+ uint32_t tempReg = SRSS_CLK_PLL_CONFIG[clkPath];
+ config->feedbackDiv = (uint8_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, tempReg);
+ config->referenceDiv = (uint8_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, tempReg);
+ config->outputDiv = (uint8_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, tempReg);
+ config->lfMode = _FLD2BOOL(SRSS_CLK_PLL_CONFIG_PLL_LF_MODE, tempReg);
+ config->outputMode = (cy_en_fll_pll_output_mode_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, tempReg);
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+ return (retVal);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllEnable
+****************************************************************************//**
+*
+* Enables the PLL. The PLL should be configured before calling this function.
+*
+* \param clkPath Selects which PLL to enable. 1 is the first PLL; 0 is invalid.
+*
+* \param timeoutus amount of time in microseconds to wait for the PLL to lock.
+* If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0
+* and manually check for lock using \ref Cy_SysClk_PllLocked.
+*
+* \return Error / status code: \n
+* CY_SYSCLK_SUCCESS - PLL successfully enabled \n
+* CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock \n
+* CY_SYSCLK_BAD_PARAM - invalid clock path number
+*
+* \note
+* Call \ref SystemCoreClockUpdate after this function calling
+* if it affects the CLK_HF0 frequency.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates before calling this function if
+* the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.
+*
+* \note
+* Call \ref Cy_SysLib_SetWaitStates after calling this function if
+* the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllEnable
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+ bool nonZeroTimeout = (timeoutus != 0ul);
+ clkPath--; /* to correctly access PLL config and status registers structures */
+ if (clkPath < CY_SRSS_NUM_PLL)
+ {
+ /* first set the PLL enable bit */
+ SRSS_CLK_PLL_CONFIG[clkPath] |= SRSS_CLK_PLL_CONFIG_ENABLE_Msk;
+
+ /* now do the timeout wait for PLL_STATUS, bit LOCKED */
+ for (; (0UL == (SRSS_CLK_PLL_STATUS_LOCKED_Msk & SRSS_CLK_PLL_STATUS[clkPath])) &&
+ (0UL != timeoutus);
+ timeoutus--)
+ {
+ Cy_SysLib_DelayUs(1U);
+ }
+ retVal = ((nonZeroTimeout && (timeoutus == 0ul)) ? CY_SYSCLK_TIMEOUT : CY_SYSCLK_SUCCESS);
+ }
+ return (retVal);
+}
+/** \} group_sysclk_pll_funcs */
+
+
+/* ========================================================================== */
+/* ==================== Clock Measurement section ===================== */
+/* ========================================================================== */
+/* Slow control register default value */
+#define TST_DDFT_SLOW_CTL_DEFAULT_VAL (0x00001F1FUL)
+
+/* Fast control register */
+#define TST_DDFT_FAST_CTL_REG (*(volatile uint32_t *) 0x40260104U)
+
+/* Slow control register default value */
+#define TST_DDFT_FAST_CTL_DEFAULT_VAL (0x00003D3DUL)
+
+/* Define for select signal outputs in slow clock */
+#define SRSS_CLK_OUTPUT_SLOW_MASK ((uint32_t) SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk | \
+ SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk)
+
+/* Define for select signal outputs in fast clock */
+#define SRSS_CLK_OUTPUT_FAST_MASK ((uint32_t) SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk | \
+ SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk | \
+ SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk | \
+ SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk | \
+ SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk | \
+ SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk)
+
+/* Cy_SysClk_StartClkMeasurementCounters() input parameter saved for use later in other functions */
+static uint32_t clk1Count1;
+
+/* These variables act as locks to prevent collisions between clock measurement and entry into
+ Deep Sleep mode. See Cy_SysClk_DeepSleep(). */
+static bool clkCounting = false;
+static bool preventCounting = false;
+
+/**
+* \addtogroup group_sysclk_calclk_funcs
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysClk_StartClkMeasurementCounters
+****************************************************************************//**
+*
+* Assigns clocks to the clock measurement counters, and starts counting. The counters
+* let you measure a clock frequency using another clock as a reference. There are two
+* counters.
+*
+* - One counter (counter1), which is clocked by clock1, is loaded with an initial
+* value and counts down to zero.
+* - The second counter (counter2), which is clocked by clock2, counts up until
+* the first counter reaches zero.
+*
+* Either clock1 or clock2 can be a reference clock; the other clock becomes the
+* measured clock. The reference clock frequency is always known. \n
+* After calling this function, call \ref Cy_SysClk_ClkMeasurementCountersDone()
+* to determine when counting is done; that is, counter1 has counted down to zero.
+* Then call \ref Cy_SysClk_ClkMeasurementCountersGetFreq() to calculate the frequency
+* of the measured clock.
+*
+* \param clock1 The clock for counter1
+*
+* \param count1 The initial value for counter1, from which counter1 counts down to zero.
+*
+* \param clock2 The clock for counter2
+*
+* \return Error / status code: \n
+* CY_SYSCLK_INVALID_STATE if already doing a measurement \n
+* CY_SYSCLK_BAD_PARAM if invalid clock input parameter \n
+* else CY_SYSCLK_SUCCESS
+*
+* \note The counters are both 24-bit, so the maximum value of count1 is 0xFFFFFF.
+* If clock2 frequency is greater than clock1, make sure that count1 is low enough
+* that counter2 does not overflow before counter1 reaches zero.
+* \note The time to complete a measurement is count1 / clock1 frequency.
+* \note The clocks for both counters must have a nonzero frequency, or
+* \ref Cy_SysClk_ClkMeasurementCountersGetFreq() incorrectly reports the result of the
+* previous measurement.
+* \note Do not enter a device low power mode (Sleep, Deep Sleep) while doing a measurement;
+* the measured clock frequency may not be accurate.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_StartClkMeasurementCounters
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t count1, cy_en_meas_clks_t clock2)
+{
+ cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM;
+
+ uint32_t clkOutputSlowVal = 0UL;
+ uint32_t clkOutputFastVal = 0UL;
+
+ uint32_t clkOutputSlowMask = 0UL;
+ uint32_t clkOutputFastMask = 0UL;
+
+ /* Prepare values for measurement control registers */
+
+ /* Connect the indicated clocks to the respective counters:
+
+ if clock1 is a slow clock,
+ select it in SRSS_CLK_OUTPUT_SLOW.SLOW_SEL0, and SRSS_CLK_OUTPUT_FAST.FAST_SEL0 = SLOW_SEL0
+ else if clock1 is a fast clock,
+ select it in SRSS_CLK_OUTPUT_FAST.FAST_SEL0,
+ else error, do nothing and return.
+
+ if clock2 is a slow clock,
+ select it in SRSS_CLK_OUTPUT_SLOW.SLOW_SEL1, and SRSS_CLK_OUTPUT_FAST.FAST_SEL1 = SLOW_SEL1
+ else if clock2 is a fast clock,
+ select it in SRSS_CLK_OUTPUT_FAST.FAST_SEL1,
+ else error, do nothing and return.
+ */
+ if ((clock1 < CY_SYSCLK_MEAS_CLK_LAST_CLK) && (clock2 < CY_SYSCLK_MEAS_CLK_LAST_CLK) &&
+ (count1 <= (SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk >> SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos)))
+ {
+ /* Disallow entry into Deep Sleep mode while counting */
+ clkCounting = true;
+
+ if (clock1 < CY_SYSCLK_MEAS_CLK_FAST_CLKS)
+ { /* slow clock */
+ clkOutputSlowVal |= _VAL2FLD(SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0, (uint32_t)clock1);
+ clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_FAST_SEL0, 7UL/*slow_sel0 output*/);
+
+ clkOutputSlowMask |= SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk;
+ clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk;
+ }
+ else
+ { /* fast clock */
+ if (clock1 < CY_SYSCLK_MEAS_CLK_PATH_CLKS)
+ { /* ECO, EXT, ALTHF */
+ clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_FAST_SEL0, (uint32_t)clock1);
+ clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk;
+ }
+ else
+ { /* PATH or CLKHF */
+ clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_FAST_SEL0, (((uint32_t)clock1 >> 8) & 0xFUL) /*use enum bits [11:8]*/);
+ clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk;
+
+ if (clock1 < CY_SYSCLK_MEAS_CLK_CLKHFS)
+ { /* PATH select */
+ clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_PATH_SEL0, ((uint32_t)clock1 & 0xFUL) /*use enum bits [3:0]*/);
+ clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk;
+ }
+ else
+ { /* CLKHF select */
+ clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0, ((uint32_t)clock1 & 0xFUL) /*use enum bits [3:0]*/);
+ clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk;
+ }
+ }
+ } /* clock1 fast clock */
+
+ if (clock2 < CY_SYSCLK_MEAS_CLK_FAST_CLKS)
+ { /* slow clock */
+ clkOutputSlowVal |= _VAL2FLD(SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1, (uint32_t)clock2);
+ clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_FAST_SEL1, 7UL/*slow_sel1 output*/);
+
+ clkOutputSlowMask |= SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk;
+ clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk;
+ }
+ else
+ { /* fast clock */
+ if (clock2 < CY_SYSCLK_MEAS_CLK_PATH_CLKS)
+ { /* ECO, EXT, ALTHF */
+ clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_FAST_SEL1, (uint32_t)clock2);
+ clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk;
+ }
+ else
+ { /* PATH or CLKHF */
+ clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_FAST_SEL1, (((uint32_t)clock2 >> 8) & 0xFUL) /*use enum bits [11:8]*/);
+ clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk;
+
+ if (clock2 < CY_SYSCLK_MEAS_CLK_CLKHFS)
+ { /* PATH select */
+ clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_PATH_SEL1, ((uint32_t)clock2 & 0xFUL) /*use enum bits [3:0]*/);
+ clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk;
+ }
+ else
+ { /* CLKHF select */
+ clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1, ((uint32_t)clock2 & 0xFUL) /*use enum bits [3:0]*/);
+ clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk;
+ }
+ }
+ } /* clock2 fast clock */
+
+ /* Acquire the IPC to prevent changing of the shared resources at the same time */
+ while(0U == (IPC_STRUCT_ACQUIRE_SUCCESS_Msk & REG_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT))))
+ {
+ /* Wait until the IPC structure is released by another process */
+ }
+
+ if ((!preventCounting) /* don't start a measurement if about to enter Deep Sleep mode */ ||
+ (_FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS_CLK_CAL_CNT1) != 0ul/*1 = done*/))
+ {
+ /* Set default values for counters measurement control registers */
+ SRSS_TST_DDFT_SLOW_CTL_REG = TST_DDFT_SLOW_CTL_DEFAULT_VAL;
+ SRSS_TST_DDFT_FAST_CTL_REG = TST_DDFT_FAST_CTL_DEFAULT_VAL;
+
+ SRSS_CLK_OUTPUT_SLOW = ((SRSS_CLK_OUTPUT_SLOW & ((uint32_t) ~clkOutputSlowMask)) | clkOutputSlowVal);
+ SRSS_CLK_OUTPUT_FAST = ((SRSS_CLK_OUTPUT_FAST & ((uint32_t) ~clkOutputFastMask)) | clkOutputFastVal);
+
+ /* Save this input parameter for use later, in other functions.
+ No error checking is done on this parameter */
+ clk1Count1 = count1;
+
+ /* Counting starts when counter1 is written with a nonzero value */
+ SRSS_CLK_CAL_CNT1 = clk1Count1;
+
+ retVal = CY_SYSCLK_SUCCESS;
+ }
+
+ /* Release the IPC */
+ REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0U;
+ }
+
+ return (retVal);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkMeasurementCountersGetFreq
+****************************************************************************//**
+*
+* Calculates the frequency of the indicated measured clock (clock1 or clock2).
+* - If clock1 is the measured clock, its frequency is: clock1 frequency = (count1 / count2) * clock2 frequency
+* - If clock2 is the measured clock, its frequency is: clock2 frequency = (count2 / count1) * clock1 frequency
+*
+* Call this function only after counting is done; see \ref Cy_SysClk_ClkMeasurementCountersDone().
+*
+* \param measuredClock False (0) if the measured clock is clock1; true (1)
+* if the measured clock is clock2.
+*
+* \param refClkFreq The reference clock frequency (clock1 or clock2).
+*
+* \return The frequency of the measured clock, in Hz.
+* \warning The function returns zero, if during measurement device was in the
+* Deep Sleep or partially blocking flash operation occurred. It means that
+* current measurement is not valid and you should call the
+* Cy_SysClk_StartClkMeasurementCounters() function once again.
+*
+* \funcusage
+* Refer to the Cy_SysClk_StartClkMeasurementCounters() function usage.
+*
+*******************************************************************************/
+uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t refClkFreq)
+{
+ uint32_t retVal = 0UL;
+ bool isMeasurementValid = false;
+
+ /* Done counting; allow entry into Deep Sleep mode */
+ clkCounting = false;
+
+ /* Acquire the IPC to prevent changing of the shared resources at the same time */
+ while(0U == (IPC_STRUCT_ACQUIRE_SUCCESS_Msk & REG_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT))))
+ {
+ /* Wait until the IPC structure is released by another process */
+ }
+
+ /* Check whether the device was in the Deep Sleep mode or the flash partially blocked while the
+ * operation was done
+ */
+ isMeasurementValid = ((SRSS_TST_DDFT_SLOW_CTL_REG == TST_DDFT_SLOW_CTL_DEFAULT_VAL) &&
+ (SRSS_TST_DDFT_FAST_CTL_REG == TST_DDFT_FAST_CTL_DEFAULT_VAL));
+
+ retVal = _FLD2VAL(SRSS_CLK_CAL_CNT2_CAL_COUNTER2, SRSS_CLK_CAL_CNT2);
+ /* Release the IPC */
+ REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0U;
+
+ if (isMeasurementValid && (0UL != retVal))
+ {
+ if (!measuredClock)
+ { /* clock1 is the measured clock */
+ retVal = (uint32_t)CY_SYSLIB_DIV_ROUND((uint64_t)clk1Count1 * (uint64_t)refClkFreq, (uint64_t)retVal);
+ }
+ else
+ { /* clock2 is the measured clock */
+ retVal = (uint32_t)CY_SYSLIB_DIV_ROUND((uint64_t)retVal * (uint64_t)refClkFreq, (uint64_t)clk1Count1);
+ }
+ }
+ else
+ {
+ /* Return zero value to indicate invalid measurement */
+ retVal = 0UL;
+ }
+
+ return (retVal);
+}
+/** \} group_sysclk_calclk_funcs */
+
+
+/* ========================================================================== */
+/* ========================== TRIM SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_trim_funcs
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_IloTrim
+****************************************************************************//**
+*
+* Trims the ILO to be as close to 32,768 Hz as possible.
+*
+* \param iloFreq current ILO frequency. Call \ref Cy_SysClk_StartClkMeasurementCounters
+* and other measurement functions to obtain the current frequency of the ILO.
+*
+* \return Change in trim value - 0 if done; that is, no change in trim value.
+*
+* \note The watchdog timer (WDT) must be unlocked before calling this function.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloTrim
+*
+*******************************************************************************/
+/** \cond INTERNAL */
+/* target frequency */
+#define CY_SYSCLK_ILO_TARGET_FREQ (32768UL)
+/* Nominal trim step size is 1.5% of "the frequency". Using the target frequency */
+#define CY_SYSCLK_ILO_TRIM_STEP (CY_SYSLIB_DIV_ROUND(CY_SYSCLK_ILO_TARGET_FREQ * 15UL, 1000UL))
+/** \endcond */
+
+int32_t Cy_SysClk_IloTrim(uint32_t iloFreq)
+{
+ uint32_t diff;
+ bool sign = false;
+
+ if(iloFreq > (CY_SYSCLK_ILO_TARGET_FREQ + CY_SYSCLK_ILO_TRIM_STEP))
+ {
+ diff = iloFreq - CY_SYSCLK_ILO_TARGET_FREQ;
+ }
+ else if (iloFreq < (CY_SYSCLK_ILO_TARGET_FREQ - CY_SYSCLK_ILO_TRIM_STEP))
+ {
+ diff = CY_SYSCLK_ILO_TARGET_FREQ - iloFreq;
+ sign = true;
+ }
+ else
+ {
+ diff = 0UL;
+ }
+
+ /* Do nothing if iloFreq is already within one trim step from the target */
+ if(0UL != diff)
+ {
+ /* Get current trim value */
+ uint32_t trim = _FLD2VAL(SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM, SRSS_CLK_TRIM_ILO_CTL);
+
+ diff = CY_SYSLIB_DIV_ROUND(diff, CY_SYSCLK_ILO_TRIM_STEP);
+
+ if(sign)
+ {
+ trim += diff;
+ }
+ else
+ {
+ trim -= diff;
+ }
+
+ /* Update the trim value */
+ CY_REG32_CLR_SET(SRSS_CLK_TRIM_ILO_CTL, SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM, trim);
+ }
+
+ return (sign ? (int32_t)diff : (0L - (int32_t)diff));
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PiloTrim
+****************************************************************************//**
+*
+* Trims the PILO to be as close to 32,768 Hz as possible.
+*
+* \param piloFreq current PILO frequency. Call \ref Cy_SysClk_StartClkMeasurementCounters
+* and other measurement functions to obtain the current frequency of the PILO.
+*
+* \return Change in trim value; 0 if done, that is, no change in trim value.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloTrim
+*
+*******************************************************************************/
+/** \cond INTERNAL */
+/* target frequency */
+#define CY_SYSCLK_PILO_TARGET_FREQ (32768UL)
+/* nominal trim step size */
+#define CY_SYSCLK_PILO_TRIM_STEP (5UL)
+/** \endcond */
+
+int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq)
+{
+ uint32_t diff;
+ bool sign = false;
+
+ if(piloFreq > (CY_SYSCLK_PILO_TARGET_FREQ + CY_SYSCLK_PILO_TRIM_STEP))
+ {
+ diff = piloFreq - CY_SYSCLK_PILO_TARGET_FREQ;
+ }
+ else if (piloFreq < (CY_SYSCLK_PILO_TARGET_FREQ - CY_SYSCLK_PILO_TRIM_STEP))
+ {
+ diff = CY_SYSCLK_PILO_TARGET_FREQ - piloFreq;
+ sign = true;
+ }
+ else
+ {
+ diff = 0UL;
+ }
+
+ /* Do nothing if piloFreq is already within one trim step from the target */
+ if(0UL != diff)
+ {
+ /* Get current trim value */
+ uint32_t trim = Cy_SysClk_PiloGetTrim();
+
+ diff = CY_SYSLIB_DIV_ROUND(diff, CY_SYSCLK_PILO_TRIM_STEP);
+
+ if(sign)
+ {/* piloFreq too low. Increase the trim value */
+ trim += diff;
+ if (trim >= SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Msk) /* limit overflow */
+ {
+ trim = SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Msk;
+ }
+ }
+ else
+ {/* piloFreq too high. Decrease the trim value */
+ trim -= diff;
+ if ((int32_t)trim < 0) /* limit underflow */
+ {
+ trim = 0UL;
+ }
+ }
+
+ /* Update the trim value */
+ Cy_SysClk_PiloSetTrim(trim);
+ }
+
+ return (sign ? (int32_t)diff : (0L - (int32_t)diff));
+}
+/** \} group_sysclk_trim_funcs */
+
+
+/* ========================================================================== */
+/* ====================== POWER MANAGEMENT SECTION ==================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_pm_funcs
+* \{
+*/
+/** \cond INTERNAL */
+/* Timeout count for use in function Cy_SysClk_DeepSleepCallback() is sufficiently large for ~1 second */
+#define TIMEOUT (1000000UL)
+/** \endcond */
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_DeepSleepCallback
+****************************************************************************//**
+*
+* Callback function to be used when entering system Deep Sleep mode.
+* This function is applicable if:
+* - The FLL is enabled
+* - The PLL is enabled and is driven by ECO
+*
+* This function performs the following:
+*
+* 1. Before entering Deep Sleep, the clock configuration is saved in SRAM.
+* If the FLL/PLL source is the ECO, then the FLL/PLL is bypassed and the
+* source is changed to IMO. \n
+* If the FLL is enabled - it is just bypassed.
+* 2. Upon wakeup from Deep Sleep, the function waits for ECO stabilization,
+* then restores the configuration and waits for the FLL/PLL to regain their
+* frequency locks. \n
+* If ECO is not used and FLL is enabled - it waits for FLL lock and unbypasses it.
+*
+* The function prevents entry into Deep Sleep mode if the measurement counters
+* are currently counting; see \ref Cy_SysClk_StartClkMeasurementCounters.
+*
+* This function can be called during execution of \ref Cy_SysPm_CpuEnterDeepSleep.
+* To do so, register this function as a callback before calling
+* \ref Cy_SysPm_CpuEnterDeepSleep - specify \ref CY_SYSPM_DEEPSLEEP as the callback
+* type and call \ref Cy_SysPm_RegisterCallback.
+*
+* \note
+* This function is recommended to be the last callback that is registered.
+* Doing so minimizes the time spent on low power mode entry and exit. \n
+* This function implements all four SysPm callback modes \ref cy_en_syspm_callback_mode_t.
+* So the \ref cy_stc_syspm_callback_t::skipMode must be set to 0UL. \n
+* This function does not support such cases as, for example, FLL is enabled
+* but bypassed by user code before entering Deep Sleep. \n
+* You can use this callback implementation as an example to design custom low-power
+* callbacks for certain user application.
+*
+* \param callbackParams
+* structure with the syspm callback parameters,
+* see \ref cy_stc_syspm_callback_params_t.
+*
+* \param mode
+* Callback mode, see \ref cy_en_syspm_callback_mode_t
+*
+* \return Error / status code; see \ref cy_en_syspm_status_t. Pass if not doing
+* a clock measurement, otherwise Fail. Timeout if timeout waiting for ECO, FLL
+* or PLL to get stable / regain its frequency lock.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_DeepSleepCallback
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams, cy_en_syspm_callback_mode_t mode)
+{
+ /* Bitmapped paths with enabled FLL/PLL sourced by ECO */
+ static uint16_t changedSourcePaths;
+ static uint16_t pllAutoModes;
+
+ cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
+
+ (void)callbackParams; /* Suppress "not used" warning */
+
+ switch (mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ /* Don't allow entry into Deep Sleep mode if currently measuring a frequency */
+ if (!clkCounting)
+ {
+ /* Indicating that we can go into Deep Sleep.
+ * Prevent starting a new clock measurement until
+ * after we've come back from Deep Sleep.
+ */
+ preventCounting = true;
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ /* Cancellation of going into Deep Sleep, therefore allow a new clock measurement */
+ preventCounting = false;
+ retVal = CY_SYSPM_SUCCESS;
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ {
+ uint32_t fllpll; /* 0 = FLL, all other values = a PLL */
+
+ /* Initialize the storage of changed paths */
+ changedSourcePaths = 0U;
+ pllAutoModes = 0U;
+
+ /* For FLL and each PLL */
+ for (fllpll = 0UL; fllpll <= CY_SRSS_NUM_PLL; fllpll++)
+ {
+ /* If FLL or PLL is enabled */
+ if ((0UL == fllpll) ? Cy_SysClk_FllIsEnabled() : Cy_SysClk_PllIsEnabled(fllpll))
+ {
+ /* And the FLL/PLL has ECO as a source */
+ if (Cy_SysClk_ClkPathGetSource(fllpll) == CY_SYSCLK_CLKPATH_IN_ECO)
+ {
+ /* Bypass the FLL/PLL */
+ if (0UL == fllpll)
+ {
+ CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT);
+ }
+ else
+ {
+ if (((uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_AUTO == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS_CLK_PLL_CONFIG[fllpll - 1UL])) ||
+ ((uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS_CLK_PLL_CONFIG[fllpll - 1UL])))
+ {
+ pllAutoModes |= (uint16_t)(1UL << fllpll);
+ }
+
+ CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllpll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT);
+ }
+
+ /* Change this path source to IMO */
+ (void)Cy_SysClk_ClkPathSetSource(fllpll, CY_SYSCLK_CLKPATH_IN_IMO);
+
+ /* Store a record that this path source was changed from ECO */
+ changedSourcePaths |= (uint16_t)(1UL << fllpll);
+ }
+ else if (0UL == fllpll)
+ {
+ CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT);
+ }
+ else
+ {
+ /* Do nothing */
+ }
+ }
+ }
+
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ /* After return from Deep Sleep, for each FLL/PLL, if needed, restore the source to ECO.
+ * And block until the FLL/PLL has regained its frequency lock.
+ */
+ uint32_t timeout = TIMEOUT;
+ retVal = CY_SYSPM_TIMEOUT;
+
+ if (0U != changedSourcePaths)
+ {
+ /* If any FLL/PLL was sourced by the ECO, timeout wait for the ECO to become fully stabilized again */
+ while ((CY_SYSCLK_ECOSTAT_STABLE != Cy_SysClk_EcoGetStatus()) && (0UL != timeout))
+ {
+ timeout--;
+ }
+
+ if (0UL != timeout)
+ {
+ uint32_t fllpll; /* 0 = FLL, all other values = PLL */
+
+ for (fllpll = 0UL; fllpll <= CY_SRSS_NUM_PLL; fllpll++)
+ {
+ /* If there is a correspondent record about a changed clock source */
+ if (0U != (changedSourcePaths & (uint16_t)(1UL << fllpll)))
+ {
+ /* Change this path source back to ECO */
+ (void)Cy_SysClk_ClkPathSetSource(fllpll, CY_SYSCLK_CLKPATH_IN_ECO);
+
+ /* Timeout wait for FLL/PLL to regain lock.
+ * Split FLL and PLL lock polling loops into two separate threads to minimize one polling loop duration.
+ */
+ if (0UL == fllpll)
+ {
+ while ((!Cy_SysClk_FllLocked()) && (0UL != timeout))
+ {
+ timeout--;
+ }
+ }
+ else
+ {
+ while ((!Cy_SysClk_PllLocked(fllpll)) && (0UL != timeout))
+ {
+ timeout--;
+ }
+ }
+
+ if (0UL != timeout)
+ {
+ /* Undo bypass the FLL/PLL */
+ if (0UL == fllpll)
+ {
+ CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT);
+ }
+ else
+ {
+ if (0U != (pllAutoModes & (uint16_t)(1UL << fllpll)))
+ {
+ CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllpll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_AUTO);
+ }
+ else
+ {
+ CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllpll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT);
+ }
+ }
+
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ }
+ }
+ }
+ }
+ else if (Cy_SysClk_FllIsEnabled())
+ {
+ /* Timeout wait for FLL to regain lock */
+ while ((!Cy_SysClk_FllLocked()) && (0UL != timeout))
+ {
+ timeout--;
+ }
+
+ if (0UL != timeout)
+ {
+ /* Undo bypass the FLL */
+ CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT);
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ }
+ else
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ }
+
+ preventCounting = false; /* Allow clock measurement */
+ }
+ break;
+
+ default: /* Unsupported mode, return CY_SYSPM_FAIL */
+ break;
+ }
+
+ return (retVal);
+}
+/** \} group_sysclk_pm_funcs */
+
+/* ========================================================================== */
+/* ========================= clkHf[n] SECTION ========================= */
+/* ========================================================================== */
+
+/** \cond INTERNAL */
+uint32_t altHfFreq = 0UL; /* Internal storage for BLE ECO frequency user setting */
+/** \endcond */
+
+/**
+* \addtogroup group_sysclk_clk_hf_funcs
+* \{
+*/
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfGetFrequency
+****************************************************************************//**
+*
+* Reports the frequency of the selected clkHf
+*
+* \param clkHf Selects the clkHf
+*
+* \return The frequency, in Hz.
+*
+* \note
+* The reported frequency may be zero, which indicates unknown. This happens if
+* the source input is dsi_out or clk_altlf.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider
+*
+*******************************************************************************/
+uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf)
+{
+ /* variables holding intermediate clock frequencies, dividers and FLL/PLL settings */
+ bool enabled = false; /* FLL or PLL enable status; n/a for direct */
+ uint32_t freq = 0UL; /* path (FLL, PLL, or direct) frequency, in Hz, 0 = unknown frequency */
+ uint32_t fDiv = 0UL; /* FLL/PLL multiplier/feedback divider */
+ uint32_t rDiv = 0UL; /* FLL/PLL reference divider */
+ uint32_t oDiv = 0UL; /* FLL/PLL output divider */
+ uint32_t pDiv = 1UL << (uint32_t)Cy_SysClk_ClkHfGetDivider(clkHf); /* root prescaler (1/2/4/8) */
+ uint32_t path = (uint32_t) Cy_SysClk_ClkHfGetSource(clkHf); /* path input for root 0 (clkHf[0]) */
+ cy_en_clkpath_in_sources_t source = Cy_SysClk_ClkPathGetSource((uint32_t)path); /* source input for path (FLL, PLL, or direct) */
+
+ /* get the frequency of the source, i.e., the path mux input */
+ switch(source)
+ {
+ case CY_SYSCLK_CLKPATH_IN_IMO: /* IMO frequency is fixed at 8 MHz */
+ freq = CY_SYSCLK_IMO_FREQ;
+ break;
+
+ case CY_SYSCLK_CLKPATH_IN_EXT:
+ freq = extFreq;
+ break;
+
+ case CY_SYSCLK_CLKPATH_IN_ECO:
+ freq = (CY_SYSCLK_ECOSTAT_STABLE == Cy_SysClk_EcoGetStatus()) ? ecoFreq : 0UL;
+ break;
+
+ case CY_SYSCLK_CLKPATH_IN_ALTHF:
+ freq = altHfFreq;
+ break;
+
+ case CY_SYSCLK_CLKPATH_IN_ILO:
+ freq = (0UL != (SRSS_CLK_ILO_CONFIG & SRSS_CLK_ILO_CONFIG_ENABLE_Msk)) ? CY_SYSCLK_ILO_FREQ : 0UL;
+ break;
+
+ case CY_SYSCLK_CLKPATH_IN_WCO:
+ freq = (Cy_SysClk_WcoOkay()) ? CY_SYSCLK_WCO_FREQ : 0UL;
+ break;
+
+ case CY_SYSCLK_CLKPATH_IN_PILO:
+ freq = (0UL != (SRSS_CLK_PILO_CONFIG & SRSS_CLK_PILO_CONFIG_PILO_EN_Msk)) ? CY_SYSCLK_PILO_FREQ : 0UL;
+ break;
+
+ default:
+ /* don't know the frequency of dsi_out, or clk_altlf */
+ freq = 0UL; /* unknown frequency */
+ break;
+ }
+
+ if (path == (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */
+ {
+ cy_stc_fll_manual_config_t fllCfg = {0UL,0U,CY_SYSCLK_FLL_CCO_RANGE0,false,0U,0U,0U,0U,CY_SYSCLK_FLLPLL_OUTPUT_AUTO,0U};
+ Cy_SysClk_FllGetConfiguration(&fllCfg);
+ enabled = (Cy_SysClk_FllIsEnabled()) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != fllCfg.outputMode);
+ fDiv = fllCfg.fllMult;
+ rDiv = fllCfg.refDiv;
+ oDiv = (fllCfg.enableOutputDiv) ? 2UL : 1UL;
+ }
+ else if (path <= CY_SRSS_NUM_PLL) /* PLL? (always path 1...N)*/
+ {
+ cy_stc_pll_manual_config_t pllcfg = {0U,0U,0U,false,CY_SYSCLK_FLLPLL_OUTPUT_AUTO};
+ (void)Cy_SysClk_PllGetConfiguration(path, &pllcfg);
+ enabled = (Cy_SysClk_PllIsEnabled(path)) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != pllcfg.outputMode);
+ fDiv = pllcfg.feedbackDiv;
+ rDiv = pllcfg.referenceDiv;
+ oDiv = pllcfg.outputDiv;
+ }
+ else
+ {
+ /* Direct select path */
+ }
+
+ if (enabled) /* if FLL or PLL enabled and not bypassed */
+ {
+ freq = (uint32_t)CY_SYSLIB_DIV_ROUND(((uint64_t)freq * (uint64_t)fDiv),
+ ((uint64_t)rDiv * (uint64_t)oDiv));
+ }
+
+ /* Divide the path input frequency down and return the result */
+ return (CY_SYSLIB_DIV_ROUND(freq, pDiv));
+}
+
+/** \} group_sysclk_clk_hf_funcs */
+
+
+
+/* ========================================================================== */
+/* ===================== clk_peripherals SECTION ====================== */
+/* ========================================================================== */
+
+
+/**
+* \addtogroup group_sysclk_clk_peripheral_funcs
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphGetFrequency
+****************************************************************************//**
+*
+* Reports the frequency of the output of a given peripheral divider.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum specifies which divider of the selected type to configure
+*
+* \return The frequency, in Hz.
+*
+* \note
+* The reported frequency may be zero, which indicates unknown. This happens if
+* the source input is dsi_out or clk_altlf.
+*
+* \funcusage
+* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphGetFrequency
+*
+*******************************************************************************/
+uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_t dividerNum)
+{
+ uint32_t integer = 0UL; /* Integer part of peripheral divider */
+ uint32_t freq = Cy_SysClk_ClkPeriGetFrequency(); /* Get Peri frequency */
+
+ CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR)));
+
+ /* get the divider value for clk_peri to the selected peripheral clock */
+ switch(dividerType)
+ {
+ case CY_SYSCLK_DIV_8_BIT:
+ case CY_SYSCLK_DIV_16_BIT:
+ integer = 1UL + Cy_SysClk_PeriphGetDivider(dividerType, dividerNum);
+ freq = CY_SYSLIB_DIV_ROUND(freq, integer);
+ break;
+
+ case CY_SYSCLK_DIV_16_5_BIT:
+ case CY_SYSCLK_DIV_24_5_BIT:
+ {
+ uint32_t locFrac;
+ uint32_t locDiv;
+ uint64_t locFreq = freq * 32ULL;
+ Cy_SysClk_PeriphGetFracDivider(dividerType, dividerNum, &integer, &locFrac);
+ /* For fractional dividers, the divider is (int + 1) + frac/32 */
+ locDiv = ((1UL + integer) * 32UL) + locFrac;
+ freq = (uint32_t) CY_SYSLIB_DIV_ROUND(locFreq, (uint64_t)locDiv);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return (freq);
+}
+/** \} group_sysclk_clk_peripheral_funcs */
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_sysint.c b/platform/ext/target/psoc64/Native_Driver/source/cy_sysint.c
new file mode 100644
index 0000000000..834b111aff
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_sysint.c
@@ -0,0 +1,376 @@
+/***************************************************************************//**
+* \file cy_sysint.c
+* \version 1.30
+*
+* \brief
+* Provides an API implementation of the SysInt driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_sysint.h"
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_Init
+****************************************************************************//**
+*
+* \brief Initializes the referenced interrupt by setting the priority and the
+* interrupt vector.
+*
+* Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) to enable the interrupt.
+*
+* \param config
+* Interrupt configuration structure
+*
+* \param userIsr
+* Address of the ISR
+*
+* \return
+* Initialization status
+*
+* \note The interrupt vector will be relocated only if the vector table was
+* moved to __ramVectors in SRAM. Otherwise it is ignored.
+*
+* \funcusage
+* \snippet sysint/snippet/main.c snippet_Cy_SysInt_Init
+*
+*******************************************************************************/
+cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr)
+{
+ cy_en_sysint_status_t status = CY_SYSINT_SUCCESS;
+
+ if(NULL != config)
+ {
+ CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority));
+
+ #if (CY_CPU_CORTEX_M0P)
+ if (config->intrSrc > SysTick_IRQn)
+ {
+ Cy_SysInt_SetInterruptSource(config->intrSrc, config->cm0pSrc);
+ }
+ else
+ {
+ status = CY_SYSINT_BAD_PARAM;
+ }
+ #endif
+
+ NVIC_SetPriority(config->intrSrc, config->intrPriority);
+
+ /* Set the new vector only if it was moved to __ramVectors */
+ if (SCB->VTOR == (uint32_t)&__ramVectors)
+ {
+ (void)Cy_SysInt_SetVector(config->intrSrc, userIsr);
+ }
+ }
+ else
+ {
+ status = CY_SYSINT_BAD_PARAM;
+ }
+
+ return(status);
+}
+
+
+#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_SetInterruptSource
+****************************************************************************//**
+*
+* \brief Configures the interrupt selection for the specified NVIC channel.
+*
+* To disconnect the interrupt source from the NVIC channel
+* use the \ref Cy_SysInt_DisconnectInterruptSource.
+*
+* \param IRQn
+* NVIC channel number connected to the CPU core.
+*
+* \param devIntrSrc
+* Device interrupt to be routed to the NVIC channel.
+*
+* \note This function is available for CM0+ core only.
+*
+* \funcusage
+* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource
+*
+*******************************************************************************/
+void Cy_SysInt_SetInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc)
+{
+ if (CY_CPUSS_V1)
+ {
+ uint32_t regPos = ((uint32_t)IRQn >> CY_SYSINT_CM0P_MUX_SHIFT);
+ if(0UL == (regPos & (uint32_t)~CY_SYSINT_MUX_REG_MSK))
+ {
+ uint32_t bitfield_Pos = (uint32_t)((uint32_t)IRQn - (uint32_t)(regPos << CY_SYSINT_CM0P_MUX_SHIFT)) << CY_SYSINT_CM0P_MUX_SCALE;
+ uint32_t bitfield_Msk = (uint32_t)(CY_SYSINT_CM0P_MUX_MASK << bitfield_Pos);
+
+ CY_REG32_CLR_SET(CPUSS_CM0_INT_CTL[regPos], bitfield, devIntrSrc);
+ }
+ }
+ else /* CPUSS_V2 */
+ {
+ CY_ASSERT_L1(CY_CPUSS_DISCONNECTED_IRQN != devIntrSrc); /* Disconnection feature doesn't work for CPUSS_V2 */
+
+ CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc] = _VAL2FLD(CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX, IRQn)
+ | CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_DisconnectInterruptSource
+****************************************************************************//**
+*
+* \brief Disconnect the interrupt source from the specified NVIC channel.
+*
+* \param IRQn
+* NVIC channel number connected to the CPU core.
+* This parameter is ignored for devices using CPUSS_ver2.
+*
+* \param devIntrSrc
+* Device interrupt routed to the NVIC channel.
+* This parameter is ignored for devices using CPUSS_ver1.
+*
+* \note This function is available for CM0+ core only.
+*
+* \funcusage
+* \snippet sysint/snippet/main.c snippet_Cy_SysInt_DisconnectInterruptSource
+*
+*******************************************************************************/
+void Cy_SysInt_DisconnectInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc)
+{
+ if (CY_CPUSS_V1)
+ {
+ Cy_SysInt_SetInterruptSource(IRQn, CY_CPUSS_DISCONNECTED_IRQN);
+ }
+ else /* CPUSS_V2 */
+ {
+ CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc] &= (uint32_t)~ CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_GetInterruptSource
+****************************************************************************//**
+*
+* \brief Gets the interrupt source of the NVIC channel.
+*
+* \param IRQn
+* NVIC channel number connected to the CPU core
+*
+* \return
+* Device interrupt connected to the NVIC channel. A returned value of
+* "disconnected_IRQn" indicates that the interrupt source is disconnected.
+*
+* \note This function is available for CM0+ core only.
+*
+* \note This function supports only devices using CPUSS_ver1. For all
+* other devices, use the Cy_SysInt_GetNvicConnection() function.
+*
+* \funcusage
+* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource
+*
+*******************************************************************************/
+cy_en_intr_t Cy_SysInt_GetInterruptSource(IRQn_Type IRQn)
+{
+ uint32_t tempReg = CY_CPUSS_NOT_CONNECTED_IRQN;
+
+ if (CY_CPUSS_V1)
+ {
+ uint32_t regPos = ((uint32_t)IRQn >> CY_SYSINT_CM0P_MUX_SHIFT);
+ if(0UL == (regPos & (uint32_t)~CY_SYSINT_MUX_REG_MSK))
+ {
+ uint32_t bitfield_Pos = ((uint32_t)IRQn - (regPos << CY_SYSINT_CM0P_MUX_SHIFT)) << CY_SYSINT_CM0P_MUX_SCALE;
+ uint32_t bitfield_Msk = (uint32_t)(CY_SYSINT_CM0P_MUX_MASK << bitfield_Pos);
+
+ tempReg = _FLD2VAL(bitfield, CPUSS_CM0_INT_CTL[regPos]);
+ }
+ }
+
+ return ((cy_en_intr_t)tempReg);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_GetNvicConnection
+****************************************************************************//**
+*
+* \brief Gets the NVIC channel to which the interrupt source is connected.
+*
+* \param devIntrSrc
+* Device interrupt that is potentially connected to the NVIC channel.
+*
+* \return
+* NVIC channel number connected to the CPU core. A returned value of
+* "unconnected_IRQn" indicates that the interrupt source is disabled.
+*
+* \note This function is available for CM0+ core only.
+*
+* \note This function supports only devices using CPUSS_ver2 or higher.
+*
+* \funcusage
+* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource
+*
+*******************************************************************************/
+IRQn_Type Cy_SysInt_GetNvicConnection(cy_en_intr_t devIntrSrc)
+{
+ uint32_t tempReg = CY_CPUSS_NOT_CONNECTED_IRQN;
+
+ if ((!CY_CPUSS_V1) && (CY_SYSINT_ENABLE == _FLD2VAL(CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID, CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc])))
+ {
+ tempReg = _FLD2VAL(CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX, CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc]);
+ }
+ return ((IRQn_Type)tempReg);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_GetInterruptActive
+****************************************************************************//**
+*
+* \brief Gets the highest priority active interrupt for the selected NVIC channel.
+*
+* The priority of the interrupt in a given channel is determined by the index
+* value of the interrupt in the cy_en_intr_t enum. The lower the index, the
+* higher the priority. E.g. Consider a case where an interrupt source with value
+* 29 and an interrupt source with value 46 both source the same NVIC channel. If
+* both are active (triggered) at the same time, calling Cy_SysInt_GetInterruptActive()
+* will return 29 as the active interrupt.
+*
+* \param IRQn
+* NVIC channel number connected to the CPU core
+*
+* \return
+* Device interrupt connected to the NVIC channel. A returned value of
+* "disconnected_IRQn" indicates that there are no active (pending) interrupts
+* on this NVIC channel.
+*
+* \note This function is available for CM0+ core only.
+*
+* \note This function supports only devices using CPUSS_ver2 or higher.
+*
+* \funcusage
+* \snippet sysint/snippet/main.c snippet_Cy_SysInt_GetInterruptActive
+*
+*******************************************************************************/
+cy_en_intr_t Cy_SysInt_GetInterruptActive(IRQn_Type IRQn)
+{
+ uint32_t tempReg = CY_CPUSS_NOT_CONNECTED_IRQN;
+ uint32_t locIdx = (uint32_t)IRQn & CY_SYSINT_INT_STATUS_MSK;
+
+ if ((!CY_CPUSS_V1) && (CY_SYSINT_ENABLE == _FLD2VAL(CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID, CPUSS_CM0_INT_STATUS[locIdx])))
+ {
+ tempReg = _FLD2VAL(CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX, CPUSS_CM0_INT_STATUS[locIdx]);
+ }
+ return ((cy_en_intr_t)tempReg);
+}
+
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_SetVector
+****************************************************************************//**
+*
+* \brief Changes the ISR vector for the interrupt.
+*
+* This function relies on the assumption that the vector table is
+* relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will
+* return the address of the default ISR location in the flash vector table.
+*
+* \param IRQn
+* Interrupt source
+*
+* \param userIsr
+* Address of the ISR to set in the interrupt vector table
+*
+* \return
+* Previous address of the ISR in the interrupt vector table
+*
+* \note For CM0+, this function sets the interrupt vector for the interrupt
+* channel on the NVIC.
+*
+* \funcusage
+* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetVector
+*
+*******************************************************************************/
+cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr)
+{
+ cy_israddress prevIsr;
+
+ /* Set the new vector only if it was moved to __ramVectors */
+ if (SCB->VTOR == (uint32_t)&__ramVectors)
+ {
+ CY_ASSERT_L1(CY_SYSINT_IS_VECTOR_VALID(userIsr));
+
+ prevIsr = __ramVectors[CY_INT_IRQ_BASE + IRQn];
+ __ramVectors[CY_INT_IRQ_BASE + IRQn] = userIsr;
+ }
+ else
+ {
+ prevIsr = __Vectors[CY_INT_IRQ_BASE + IRQn];
+ }
+
+ return (prevIsr);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_GetVector
+****************************************************************************//**
+*
+* \brief Gets the address of the current ISR vector for the interrupt.
+*
+* This function relies on the assumption that the vector table is
+* relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will
+* return the address of the default ISR location in the flash vector table.
+*
+* \param IRQn
+* Interrupt source
+*
+* \return
+* Address of the ISR in the interrupt vector table
+*
+* \note For CM0+, this function returns the interrupt vector for the interrupt
+* channel on the NVIC.
+*
+* \funcusage
+* \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetVector
+*
+*******************************************************************************/
+cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn)
+{
+ cy_israddress currIsr;
+
+ /* Return the SRAM ISR address only if it was moved to __ramVectors */
+ if (SCB->VTOR == (uint32_t)&__ramVectors)
+ {
+ currIsr = __ramVectors[CY_INT_IRQ_BASE + IRQn];
+ }
+ else
+ {
+ currIsr = __Vectors[CY_INT_IRQ_BASE + IRQn];
+ }
+
+ return (currIsr);
+}
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_syslib.c b/platform/ext/target/psoc64/Native_Driver/source/cy_syslib.c
new file mode 100644
index 0000000000..fbbab869c0
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_syslib.c
@@ -0,0 +1,567 @@
+/***************************************************************************//**
+* \file cy_syslib.c
+* \version 2.40.1
+*
+* Description:
+* Provides system API implementation for the SysLib driver.
+*
+********************************************************************************
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_syslib.h"
+#include "cy_ipc_drv.h"
+#if !defined(NDEBUG)
+ #include <string.h>
+#endif /* NDEBUG */
+
+/* Flash wait states (ULP mode at 0.9v) */
+#define CY_SYSLIB_FLASH_ULP_WS_0_FREQ_MAX ( 16UL)
+#define CY_SYSLIB_FLASH_ULP_WS_1_FREQ_MAX ( 33UL)
+#define CY_SYSLIB_FLASH_ULP_WS_2_FREQ_MAX ( 50UL)
+
+/* ROM and SRAM wait states for the slow clock domain (LP mode at 1.1v) */
+#define CY_SYSLIB_LP_SLOW_WS_0_FREQ_MAX (100UL)
+#define CY_SYSLIB_LP_SLOW_WS_1_FREQ_MAX (120UL)
+
+/* ROM and SRAM wait states for the slow clock domain (ULP mode at 0.9v) */
+#define CY_SYSLIB_ULP_SLOW_WS_0_FREQ_MAX ( 25UL)
+#define CY_SYSLIB_ULP_SLOW_WS_1_FREQ_MAX ( 50UL)
+
+
+#if !defined(NDEBUG)
+ CY_NOINIT char_t cy_assertFileName[CY_MAX_FILE_NAME_SIZE];
+ CY_NOINIT uint32_t cy_assertLine;
+#endif /* NDEBUG */
+
+#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
+ CY_NOINIT cy_stc_fault_frame_t cy_faultFrame;
+#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ static void Cy_SysLib_AsmInfiniteLoop(void) { __ASM (" b . "); };
+ #else
+ static __ASM void Cy_SysLib_AsmInfiniteLoop(void) { b . };
+ #endif /* (__ARMCC_VERSION >= 6010050) */
+#endif /* (__ARMCC_VERSION) */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_Delay
+****************************************************************************//**
+*
+* The function delays by the specified number of milliseconds.
+* By default, the number of cycles to delay is calculated based on the
+* \ref SystemCoreClock.
+*
+* \param milliseconds The number of milliseconds to delay.
+*
+* \note The function calls \ref Cy_SysLib_DelayCycles() API to generate a delay.
+* If the function parameter (milliseconds) is bigger than
+* CY_DELAY_MS_OVERFLOW constant, then an additional loop runs to prevent
+* an overflow in parameter passed to \ref Cy_SysLib_DelayCycles() API.
+*
+*******************************************************************************/
+void Cy_SysLib_Delay(uint32_t milliseconds)
+{
+ while(milliseconds > CY_DELAY_MS_OVERFLOW)
+ {
+ /* This loop prevents an overflow in value passed to Cy_SysLib_DelayCycles() API.
+ * At 100 MHz, (milliseconds * cy_delayFreqKhz) product overflows
+ * in case if milliseconds parameter is more than 42 seconds.
+ */
+ Cy_SysLib_DelayCycles(cy_delay32kMs);
+ milliseconds -= CY_DELAY_MS_OVERFLOW;
+ }
+
+ Cy_SysLib_DelayCycles(milliseconds * cy_delayFreqKhz);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_DelayUs
+****************************************************************************//**
+*
+* The function delays by the specified number of microseconds.
+* By default, the number of cycles to delay is calculated based on the
+* \ref SystemCoreClock.
+*
+* \param microseconds The number of microseconds to delay.
+*
+* \note If the CPU frequency is a small non-integer number, the actual delay
+* can be up to twice as long as the nominal value. The actual delay
+* cannot be shorter than the nominal one.
+*
+*******************************************************************************/
+void Cy_SysLib_DelayUs(uint16_t microseconds)
+{
+ Cy_SysLib_DelayCycles((uint32_t) microseconds * cy_delayFreqMhz);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_Halt
+****************************************************************************//**
+*
+* This function halts the CPU but only the CPU which calls the function.
+* It doesn't affect other CPUs.
+*
+* \param reason The value to be used during debugging.
+*
+* \note The function executes the BKPT instruction for halting CPU and is
+* intended to be used for the debug purpose. A regular use case requires
+* Debugger attachment before the function call.
+* The BKPT instruction causes the CPU to enter the Debug state. Debug
+* tools can use this to investigate the system state, when the
+* instruction at a particular address is reached.
+*
+* \note Execution of a BKPT instruction without a debugger attached produces
+* a fault. The fault results in the HardFault exception being taken
+* or causes a Lockup state if it occurs in the NMI or HardFault handler.
+* The default HardFault handler make a software reset if the build option
+* is the release mode (NDEBUG). If the build option is the debug mode,
+* the system will stay in the infinite loop of the
+* \ref Cy_SysLib_ProcessingFault() function.
+*
+*******************************************************************************/
+__NO_RETURN void Cy_SysLib_Halt(uint32_t reason)
+{
+ if(0U != reason)
+ {
+ /* To remove an unreferenced local variable warning */
+ }
+
+ #if defined (__ARMCC_VERSION)
+ __breakpoint(0x0);
+ #elif defined(__GNUC__)
+ __asm(" bkpt 1");
+ #elif defined (__ICCARM__)
+ __asm(" bkpt 1");
+ #else
+ #error "An unsupported toolchain"
+ #endif /* (__ARMCC_VERSION) */
+
+ while(1) {}
+}
+
+
+/*******************************************************************************
+* Macro Name: Cy_SysLib_AssertFailed
+****************************************************************************//**
+*
+* This function stores the ASSERT location of the file name (including path
+* to file) and line number in a non-zero init area for debugging. Also it calls
+* the \ref Cy_SysLib_Halt() function to halt the processor.
+*
+* \param file The file name of the ASSERT location.
+* \param line The line number of the ASSERT location.
+*
+* \note A stored file name and line number could be accessed by
+* cy_assertFileName and cy_assertLine global variables.
+* \note This function has the WEAK option, so the user can redefine
+* the function for a custom processing.
+*
+*******************************************************************************/
+__WEAK void Cy_SysLib_AssertFailed(const char_t * file, uint32_t line)
+{
+#if !defined(NDEBUG) || defined(CY_DOXYGEN)
+ (void) strncpy(cy_assertFileName, file, CY_MAX_FILE_NAME_SIZE);
+ cy_assertLine = line;
+ Cy_SysLib_Halt(0UL);
+#else
+ (void) file;
+ (void) line;
+#endif /* !defined(NDEBUG) || defined(CY_DOXYGEN) */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_ClearFlashCacheAndBuffer
+****************************************************************************//**
+*
+* This function invalidates the flash cache and buffer. It ensures the valid
+* data is read from flash instead of using outdated data from the cache.
+* The caches' LRU structure is also reset to their default state.
+*
+* \note The operation takes a maximum of three clock cycles on the slowest of
+* the clk_slow and clk_fast clocks.
+*
+*******************************************************************************/
+void Cy_SysLib_ClearFlashCacheAndBuffer(void)
+{
+ FLASHC_FLASH_CMD = FLASHC_FLASH_CMD_INV_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_ResetBackupDomain
+****************************************************************************//**
+*
+* This function resets the backup domain power to avoid the ILO glitch. The
+* glitch can occur when the device is reset due to POR/BOD/XRES while
+* the backup voltage is supplied into the system.
+*
+* \note Writing 1 to BACKUP->RESET resets the backup logic. Hardware clears it
+* when the reset is complete. After setting the register, this function
+* reads the register immediately for returning the result of the backup
+* domain reset state. The reading register is important because the Read
+* itself takes multiple AHB clock cycles, and the reset is actually
+* finishing during that time.
+*
+* \return CY_SYSLIB_SUCCESS, if BACKUP->RESET read-back is 0.
+* Otherwise returns CY_SYSLIB_INVALID_STATE.
+*
+*******************************************************************************/
+cy_en_syslib_status_t Cy_SysLib_ResetBackupDomain(void)
+{
+ BACKUP_RESET = BACKUP_RESET_RESET_Msk;
+
+ return ( ((BACKUP_RESET & BACKUP_RESET_RESET_Msk) == 0UL) ? CY_SYSLIB_SUCCESS : CY_SYSLIB_INVALID_STATE );
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_GetResetReason
+****************************************************************************//**
+*
+* The function returns the cause for the latest reset(s) that occurred in
+* the system. The reset causes include an HFCLK error, system faults, and
+* device reset on a wakeup from Hibernate mode.
+* The return results are consolidated reset causes from reading RES_CAUSE,
+* RES_CAUSE2 and PWR_HIBERNATE token registers.
+*
+* \return The cause of a system reset.
+*
+* | Name | Value
+* |-------------------------------|---------------------
+* | CY_SYSLIB_RESET_HWWDT | 0x00001 (bit0)
+* | CY_SYSLIB_RESET_ACT_FAULT | 0x00002 (bit1)
+* | CY_SYSLIB_RESET_DPSLP_FAULT | 0x00004 (bit2)
+* | CY_SYSLIB_RESET_CSV_WCO_LOSS | 0x00008 (bit3)
+* | CY_SYSLIB_RESET_SOFT | 0x00010 (bit4)
+* | CY_SYSLIB_RESET_SWWDT0 | 0x00020 (bit5)
+* | CY_SYSLIB_RESET_SWWDT1 | 0x00040 (bit6)
+* | CY_SYSLIB_RESET_SWWDT2 | 0x00080 (bit7)
+* | CY_SYSLIB_RESET_SWWDT3 | 0x00100 (bit8)
+* | CY_SYSLIB_RESET_HFCLK_LOSS | 0x10000 (bit16)
+* | CY_SYSLIB_RESET_HFCLK_ERR | 0x20000 (bit17)
+* | CY_SYSLIB_RESET_HIB_WAKEUP | 0x40000 (bit18)
+*
+* \note CY_SYSLIB_RESET_CSV_WCO_LOSS, CY_SYSLIB_RESET_HFCLK_LOSS and
+* CY_SYSLIB_RESET_HFCLK_ERR causes of a system reset available only if
+* WCO CSV present in the device.
+*
+*******************************************************************************/
+uint32_t Cy_SysLib_GetResetReason(void)
+{
+ uint32_t retVal = SRSS_RES_CAUSE;
+
+ if(0U != _FLD2VAL(SRSS_PWR_HIBERNATE_TOKEN, SRSS_PWR_HIBERNATE))
+ {
+ retVal |= CY_SYSLIB_RESET_HIB_WAKEUP;
+ }
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_ClearResetReason
+****************************************************************************//**
+*
+* This function clears the values of RES_CAUSE and RES_CAUSE2. Also it clears
+* PWR_HIBERNATE token, which indicates reset event on waking up from HIBERNATE.
+*
+*******************************************************************************/
+void Cy_SysLib_ClearResetReason(void)
+{
+ /* RES_CAUSE and RES_CAUSE2 register's bits are RW1C (every bit is cleared upon writing 1),
+ * so write all ones to clear all the reset reasons.
+ */
+ SRSS_RES_CAUSE = 0xFFFFFFFFU;
+ SRSS_RES_CAUSE2 = 0xFFFFFFFFU;
+
+ if(0U != _FLD2VAL(SRSS_PWR_HIBERNATE_TOKEN, SRSS_PWR_HIBERNATE))
+ {
+ /* Clears PWR_HIBERNATE token */
+ SRSS_PWR_HIBERNATE &= ~SRSS_PWR_HIBERNATE_TOKEN_Msk;
+ }
+}
+
+
+#if (CY_CPU_CORTEX_M0P) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Function Name: Cy_SysLib_SoftResetCM4
+****************************************************************************//**
+*
+* This function performs a CM4 Core software reset using the CM4_PWR_CTL
+* register. The register is accessed by CM0 Core by using a command transferred
+* to SROM API through the IPC channel. When the command is sent, the API waits
+* for the IPC channel release.
+*
+* \note This function should be called only when the CM4 core is in Deep
+* Sleep mode.
+* \note This function will not reset CM0+ Core.
+* \note This function waits for an IPC channel release state.
+*
+*******************************************************************************/
+void Cy_SysLib_SoftResetCM4(void)
+{
+ static uint32_t msg = CY_IPC_DATA_FOR_CM4_SOFT_RESET;
+
+ /* Tries to acquire the IPC structure and pass the arguments to SROM API.
+ * SROM API parameters:
+ * ipcPtr: IPC Structure 0 reserved for M0+ Secure Access.
+ * notifyEvent_Intr: 1U - IPC Interrupt Structure 1 is used for Releasing IPC 0 (M0+ NMI Handler).
+ * msgPtr: &msg - The address of SRAM with the API's parameters.
+ */
+ if(CY_IPC_DRV_SUCCESS != Cy_IPC_Drv_SendMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL_CM0), 1U, (void *) &msg))
+ {
+ CY_ASSERT(0U != 0U);
+ }
+
+ while(Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL_CM0)))
+ {
+ /* Waits until SROM API runs the command (sent over the IPC channel) and releases the IPC0 structure. */
+ }
+}
+#endif /* CY_CPU_CORTEX_M0P || defined(CY_DOXYGEN) */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_GetUniqueId
+****************************************************************************//**
+*
+* This function returns the silicon unique ID.
+* The ID includes Die lot[3]#, Die Wafer#, Die X, Die Y, Die Sort#, Die Minor
+* and Die Year.
+*
+* \return A combined 64-bit unique ID.
+* [63:57] - DIE_YEAR
+* [56:56] - DIE_MINOR
+* [55:48] - DIE_SORT
+* [47:40] - DIE_Y
+* [39:32] - DIE_X
+* [31:24] - DIE_WAFER
+* [23:16] - DIE_LOT[2]
+* [15: 8] - DIE_LOT[1]
+* [ 7: 0] - DIE_LOT[0]
+*
+*******************************************************************************/
+uint64_t Cy_SysLib_GetUniqueId(void)
+{
+ uint32_t uniqueIdHi;
+ uint32_t uniqueIdLo;
+
+ uniqueIdHi = ((uint32_t) SFLASH_DIE_YEAR << (CY_UNIQUE_ID_DIE_YEAR_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
+ (((uint32_t)SFLASH_DIE_MINOR & 1U) << (CY_UNIQUE_ID_DIE_MINOR_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
+ ((uint32_t) SFLASH_DIE_SORT << (CY_UNIQUE_ID_DIE_SORT_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
+ ((uint32_t) SFLASH_DIE_Y << (CY_UNIQUE_ID_DIE_Y_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
+ ((uint32_t) SFLASH_DIE_X);
+
+ uniqueIdLo = ((uint32_t) SFLASH_DIE_WAFER << CY_UNIQUE_ID_DIE_WAFER_Pos) |
+ ((uint32_t) SFLASH_DIE_LOT(2U) << CY_UNIQUE_ID_DIE_LOT_2_Pos) |
+ ((uint32_t) SFLASH_DIE_LOT(1U) << CY_UNIQUE_ID_DIE_LOT_1_Pos) |
+ ((uint32_t) SFLASH_DIE_LOT(0U));
+
+ return (((uint64_t) uniqueIdHi << CY_UNIQUE_ID_DIE_X_Pos) | uniqueIdLo);
+}
+
+
+#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Function Name: Cy_SysLib_FaultHandler
+****************************************************************************//**
+*
+* This function stores the ARM Cortex registers into a non-zero init area for
+* debugging. This function calls Cy_SysLib_ProcessingFault() after storing all
+* information.
+*
+* \param faultStackAddr The address of the stack pointer, indicates the lowest
+* address in the fault stack frame to be stored.
+* \note This function stores the fault stack frame only for the first occurred
+* fault.
+* \note The PDL doesn't provide an API to analyze the stored register
+* values. The user has to add additional functions for the analysis,
+* if necessary.
+* \note The CY_ARM_FAULT_DEBUG macro defines if the Fault Handler is enabled.
+* By default it is set to CY_ARM_FAULT_DEBUG_ENABLED and enables the
+* Fault Handler.
+* If there is a necessity to save memory or have some specific custom
+* handler, etc. then CY_ARM_FAULT_DEBUG should be redefined as
+* CY_ARM_FAULT_DEBUG_DISABLED. To do this, the following definition should
+* be added to the compiler Command Line (through the project Build
+* Settings): "-D CY_ARM_FAULT_DEBUG=0".
+*
+*******************************************************************************/
+void Cy_SysLib_FaultHandler(uint32_t const *faultStackAddr)
+{
+ /* Stores general registers */
+ cy_faultFrame.r0 = faultStackAddr[CY_R0_Pos];
+ cy_faultFrame.r1 = faultStackAddr[CY_R1_Pos];
+ cy_faultFrame.r2 = faultStackAddr[CY_R2_Pos];
+ cy_faultFrame.r3 = faultStackAddr[CY_R3_Pos];
+ cy_faultFrame.r12 = faultStackAddr[CY_R12_Pos];
+ cy_faultFrame.lr = faultStackAddr[CY_LR_Pos];
+ cy_faultFrame.pc = faultStackAddr[CY_PC_Pos];
+ cy_faultFrame.psr = faultStackAddr[CY_PSR_Pos];
+
+ #if (CY_CPU_CORTEX_M4)
+ /* Stores the Configurable Fault Status Register state with the fault cause */
+ cy_faultFrame.cfsr.cfsrReg = SCB->CFSR;
+ /* Stores the Hard Fault Status Register */
+ cy_faultFrame.hfsr.hfsrReg = SCB->HFSR;
+ /* Stores the System Handler Control and State Register */
+ cy_faultFrame.shcsr.shcsrReg = SCB->SHCSR;
+ /* Store MemMange fault address */
+ cy_faultFrame.mmfar = SCB->MMFAR;
+ /* Store Bus fault address */
+ cy_faultFrame.bfar = SCB->BFAR;
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)))
+ /* Checks cumulative exception bits for floating-point exceptions */
+ if(0U != (__get_FPSCR() & (CY_FPSCR_IXC_Msk | CY_FPSCR_IDC_Msk)))
+ {
+ cy_faultFrame.s0 = faultStackAddr[CY_S0_Pos];
+ cy_faultFrame.s1 = faultStackAddr[CY_S1_Pos];
+ cy_faultFrame.s2 = faultStackAddr[CY_S2_Pos];
+ cy_faultFrame.s3 = faultStackAddr[CY_S3_Pos];
+ cy_faultFrame.s4 = faultStackAddr[CY_S4_Pos];
+ cy_faultFrame.s5 = faultStackAddr[CY_S5_Pos];
+ cy_faultFrame.s6 = faultStackAddr[CY_S6_Pos];
+ cy_faultFrame.s7 = faultStackAddr[CY_S7_Pos];
+ cy_faultFrame.s8 = faultStackAddr[CY_S8_Pos];
+ cy_faultFrame.s9 = faultStackAddr[CY_S9_Pos];
+ cy_faultFrame.s10 = faultStackAddr[CY_S10_Pos];
+ cy_faultFrame.s11 = faultStackAddr[CY_S11_Pos];
+ cy_faultFrame.s12 = faultStackAddr[CY_S12_Pos];
+ cy_faultFrame.s13 = faultStackAddr[CY_S13_Pos];
+ cy_faultFrame.s14 = faultStackAddr[CY_S14_Pos];
+ cy_faultFrame.s15 = faultStackAddr[CY_S15_Pos];
+ cy_faultFrame.fpscr = faultStackAddr[CY_FPSCR_Pos];
+ }
+ #endif /* __FPU_PRESENT */
+ #endif /* CY_CPU_CORTEX_M4 */
+
+ Cy_SysLib_ProcessingFault();
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_ProcessingFault
+****************************************************************************//**
+*
+* This function determines how to process the current fault state. By default
+* in case of exception the system will stay in the infinite loop of this
+* function.
+*
+* \note This function has the WEAK option, so the user can redefine the function
+* behavior for a custom processing.
+* For example, the function redefinition could be constructed from fault
+* stack processing and NVIC_SystemReset() function call.
+*
+*******************************************************************************/
+__WEAK void Cy_SysLib_ProcessingFault(void)
+{
+ #if defined(__ARMCC_VERSION)
+ /* Assembly implementation of an infinite loop
+ * is used for the armcc compiler to preserve the call stack.
+ * Otherwise, the compiler destroys the call stack,
+ * because treats this API as a no return function.
+ */
+ Cy_SysLib_AsmInfiniteLoop();
+ #else
+ while(1) {}
+ #endif /* (__ARMCC_VERSION) */
+}
+#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN) */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_SetWaitStates
+****************************************************************************//**
+*
+* Sets the number of clock cycles the cache will wait for, before it samples
+* data coming back from ROM, SRAM, and Flash.
+*
+* Call this function before increasing the HFClk0 High Frequency clock.
+* Call this function optionally after lowering the HFClk0 High Frequency clock
+* in order to improve the CPU performance.
+*
+* Also, call this function before switching the core supply regulator voltage
+* (LDO or SIMO Buck) from 1.1V to 0.9V.
+* Call this function optionally after switching the core supply regulator
+* voltage from 0.9V to 1.1V in order to improve the CPU performance.
+*
+* \param ulpMode The device power mode.
+* true if the device should be switched to the ULP mode (nominal
+* voltage of the core supply regulator should be switched to 0.9V);
+* false if the device should be switched to the LP mode (nominal
+* voltage of the core supply regulator should be switched to 1.1V).
+*
+* \note Refer to the device TRM for the low power modes description.
+*
+* \param clkHfMHz The HFClk0 clock frequency in MHz. Specifying a frequency
+* above the supported maximum will set the wait states as for
+* the maximum frequency.
+*
+*******************************************************************************/
+void Cy_SysLib_SetWaitStates(bool ulpMode, uint32_t clkHfMHz)
+{
+ uint32_t waitStates;
+ uint32_t freqMax;
+
+ freqMax = ulpMode ? CY_SYSLIB_ULP_SLOW_WS_0_FREQ_MAX : CY_SYSLIB_LP_SLOW_WS_0_FREQ_MAX;
+ waitStates = (clkHfMHz <= freqMax) ? 0UL : 1UL;
+
+ /* ROM */
+ CPUSS_ROM_CTL = _CLR_SET_FLD32U(CPUSS_ROM_CTL, CPUSS_ROM_CTL_SLOW_WS, waitStates);
+ CPUSS_ROM_CTL = _CLR_SET_FLD32U(CPUSS_ROM_CTL, CPUSS_ROM_CTL_FAST_WS, 0UL);
+
+ /* SRAM */
+ CPUSS_RAM0_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM0_CTL0, CPUSS_RAM0_CTL0_SLOW_WS, waitStates);
+ CPUSS_RAM0_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM0_CTL0, CPUSS_RAM0_CTL0_FAST_WS, 0UL);
+ #if defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL)
+ CPUSS_RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM1_CTL0, CPUSS_RAM1_CTL0_SLOW_WS, waitStates);
+ CPUSS_RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM1_CTL0, CPUSS_RAM1_CTL0_FAST_WS, 0UL);
+ #endif /* defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL) */
+ #if defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL)
+ CPUSS_RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM2_CTL0, CPUSS_RAM2_CTL0_SLOW_WS, waitStates);
+ CPUSS_RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM2_CTL0, CPUSS_RAM2_CTL0_FAST_WS, 0UL);
+ #endif /* defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL) */
+
+ /* Flash */
+ if (ulpMode)
+ {
+ waitStates = (clkHfMHz <= CY_SYSLIB_FLASH_ULP_WS_0_FREQ_MAX) ? 0UL :
+ ((clkHfMHz <= CY_SYSLIB_FLASH_ULP_WS_1_FREQ_MAX) ? 1UL : 2UL);
+ }
+ else
+ {
+ waitStates = (clkHfMHz <= cy_device->flashCtlMainWs0Freq) ? 0UL :
+ ((clkHfMHz <= cy_device->flashCtlMainWs1Freq) ? 1UL :
+ ((clkHfMHz <= cy_device->flashCtlMainWs2Freq) ? 2UL :
+ ((clkHfMHz <= cy_device->flashCtlMainWs3Freq) ? 3UL :
+ ((clkHfMHz <= cy_device->flashCtlMainWs4Freq) ? 4UL : 5UL))));
+ }
+
+ FLASHC_FLASH_CTL = _CLR_SET_FLD32U(FLASHC_FLASH_CTL, FLASHC_FLASH_CTL_MAIN_WS, waitStates);
+}
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_syspm.c b/platform/ext/target/psoc64/Native_Driver/source/cy_syspm.c
new file mode 100644
index 0000000000..8368020b88
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_syspm.c
@@ -0,0 +1,3222 @@
+/***************************************************************************//**
+* \file cy_syspm.c
+* \version 4.40
+*
+* This driver provides the source code for API power management.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#include "cy_syspm.h"
+#include "cy_ipc_drv.h"
+#include "cy_ipc_sema.h"
+#include "cy_ipc_pipe.h"
+#include "cy_prot.h"
+
+
+/*******************************************************************************
+* Internal Functions
+*******************************************************************************/
+static bool EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor);
+
+static void SetReadMarginTrimUlp(void);
+static void SetReadMarginTrimLp(void);
+static void SetWriteAssistTrimUlp(void);
+static void SetWriteAssistTrimLp(void);
+static bool IsVoltageChangePossible(void);
+
+
+/*******************************************************************************
+* Internal Defines
+*******************************************************************************/
+#ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE
+
+ /** The internal define for clock divider */
+ #define SYSPM_CLK_DIVIDER (9U)
+
+ /* Mask for the fast clock divider value */
+ #define SYSPM_FAST_CLK_DIV_Msk (0xFF000000UL)
+
+ /* Position for the fast clock divider value */
+ #define SYSPM_FAST_CLK_DIV_Pos (24UL)
+
+ /* Mask for the slow clock divider value */
+ #define SYSPM_SLOW_CLK_DIV_Msk (0x00FF0000UL)
+
+ /* Position for the slow clock divider value */
+ #define SYSPM_SLOW_CLK_DIV_Pos (16UL)
+
+ /* Mask for both slow and fast mask clock dividers */
+ #define SYSPM_CLK_DIV_MASK (SYSPM_FAST_CLK_DIV_Msk | SYSPM_SLOW_CLK_DIV_Msk)
+
+ #if (CY_CPU_CORTEX_M4)
+ #define CUR_CORE_DP_MASK (0x01UL)
+ #define OTHER_CORE_DP_MASK (0x02UL)
+ #else
+ #define CUR_CORE_DP_MASK (0x02UL)
+ #define OTHER_CORE_DP_MASK (0x01UL)
+ #endif
+
+#endif /* #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE */
+
+/* The define for the current active bus master */
+#if (CY_CPU_CORTEX_M0P)
+ #define ACTIVE_BUS_MASTER CPUSS_MS_ID_CM0
+#else
+ #define ACTIVE_BUS_MASTER CPUSS_MS_ID_CM4
+#endif /* (CY_CPU_CORTEX_M0P) */
+
+/* Define of MMIO group where UDB is located */
+#define MMIO_UDB_GROUP_NR (4U)
+
+/* Define of MMIO group where UDB is located */
+#define MMIO_UDB_SLAVE_NR (3U)
+
+/* The UDB placement on MMIO slave level */
+#define PERI_UDB_SLAVE_ENABLED ((uint32_t) 1UL << MMIO_UDB_GROUP_NR)
+
+/* The definition for the delay of the LDO after its output
+* voltage is changed
+*/
+#define LDO_STABILIZATION_DELAY_US (9U)
+
+/* Define to indicate that a 10 us delay is needed */
+#define NEED_DELAY (0x0U)
+
+/* Slow output register */
+#define CLK_OUTPUT_SLOW_MASK (0x06U)
+
+/* Slow control register */
+#define TST_DDFT_FAST_CTL_MASK (62U)
+
+/* Load value for the timer to count delay after exiting Deep Sleep */
+#define IMO_10US_DELAY (68U)
+
+/* Define to indicate that a 10 us delay was done after exiting Deep Sleep */
+#define DELAY_DONE (0xAAAAAAAAU)
+
+/* Define for transitional 0.95 V for the LDO regulator */
+#define LDO_OUT_VOLTAGE_0_95V (0x0BU)
+
+/* Define for transitional 1.1 V for the LDO regulator */
+#define LDO_OUT_VOLTAGE_1_1V (0x17U)
+
+/* Define for transitional 1.15 V for the LDO regulator */
+#define LDO_OUT_VOLTAGE_1_15V (0x1BU)
+
+/* The definition for the delay of the Buck supply regulator
+* stabilization after it is configured with enabled Buck output 1 */
+#define BUCK_INIT_STABILIZATION_US (900U)
+
+/* The definition for the delay of the Buck supply regulator
+* stabilization after it is configured with enabled Buck
+* output 2 only
+*/
+#define BUCK_OUT2_INIT_DELAY_US (600U)
+
+/* The definition for the delay of the Buck regulator after its output
+* voltage is changed
+*/
+#define BUCK_OUT2_STABILIZATION_DELAY_US (200U)
+
+/* Define for transitional 0.95 V for buck regulator */
+#define BUCK_OUT1_VOLTAGE_0_95V (3U)
+
+/* Define for a Buck regulator stabilization delay from 0.9 V to 0.95 V */
+#define BUCK_OUT1_0_9V_TO_0_95V_DELAY_US (52U)
+
+/* Define for a Buck regulator stabilization delay from 0.95 V to 1.1 V */
+#define BUCK_OUT1_0_95V_TO_1_1V_DELAY_US (145U)
+
+/* Define for an LDO stabilization delay from 0.9 V to 0.95 V */
+#define LDO_0_9V_TO_0_95V_DELAY_US (3U)
+
+/* Define for an LDO regulator stabilization delay from 0.95 V to 1.1 V */
+#define LDO_0_95V_TO_1_1V_DELAY_US (7U)
+
+/* Define for ROM trim in LP mode */
+#define CPUSS_TRIM_ROM_LP (0x00000013U)
+
+/* Define for RAM trim in LP mode */
+#define CPUSS_TRIM_RAM_LP (0x00004013U)
+
+/* Define for ROM trim in ULP mode */
+#define CPUSS_TRIM_ROM_ULP (0x00000012U)
+
+/* Define for trim RAM in ULP mode */
+#define CPUSS_TRIM_RAM_ULP (0x00006012U)
+
+/* Define for IPC0 notification */
+#define SYSPM_IPC_NOTIFY_STRUCT0 ((uint32_t) 0x1UL << CY_IPC_INTR_SYSCALL1)
+
+/* The define of bit positions of the syscall return status */
+#define SYSCALL_STATUS_MASK (0xFF000000U)
+
+/* The define for the success return status of the syscall */
+#define SYSCALL_STATUS_SUCCESS (0xA0000000U)
+
+/* The define for device TO *B Revision ID */
+#define SYSPM_DEVICE_PSOC6ABLE2_REV_0B (0x22U)
+
+/* The pointer to the Cy_EnterDeepSleep() function in the ROM */
+#define ROM_ENTER_DEEP_SLEEP_ADDR (*(uint32_t *) 0x00000D30UL)
+
+/* The define to call the ROM Cy_EnterDeepSleep() function.
+* The ROM Cy_EnterDeepSleep() function prepares the system for the Deep Sleep
+* and restores the system after wakeup from the Deep Sleep. */
+typedef void (*cy_cb_syspm_deep_sleep_t)(cy_en_syspm_waitfor_t waitFor, bool *wasEventSent);
+
+#define EnterDeepSleepSrom(waitFor, wasEventSent) \
+ ((cy_cb_syspm_deep_sleep_t) ROM_ENTER_DEEP_SLEEP_ADDR)((waitFor), &(wasEventSent))
+
+/* Mask for the RAM read assist bits */
+#define CPUSS_TRIM_RAM_CTL_RA_MASK ((uint32_t) 0x3U << 8U)
+
+/* The define for SROM opcode to set the flash voltage bit */
+#define FLASH_VOLTAGE_BIT_ULP_OPCODE (0x0C000003U)
+
+/* The define for SROM opcode to clear the flash voltage bit */
+#define FLASH_VOLTAGE_BIT_LP_OPCODE (0x0C000001U)
+
+/* The define for SROM opcode to set the flash voltage bit */
+#define FLASH_VOLTAGE_BIT_ULP_PSOC6ABLE2_OPCODE (0x30000101U)
+
+/* The define for SROM to clear the flash voltage bit */
+#define FLASH_VOLTAGE_BIT_LP_PSOC6ABLE2_OPCODE (0x30000001U)
+
+/* The wait time for transition into the minimum regulator current mode
+*/
+#define SET_MIN_CURRENT_MODE_DELAY_US (1U)
+
+/* The wait delay time that occurs before the active reference is settled.
+* Intermediate delay is used in transition into the normal regulator current
+* mode
+*/
+#define ACT_REF_SETTLE_DELAY_US (8U)
+
+/* The wait delay time that occurs after the active reference is settled.
+* Final delay is used in transition into the normal regulator current mode
+*/
+#define SET_NORMAL_CURRENT_MODE_DELAY_US (1U)
+
+/* The internal define of the tries number in the
+* Cy_SysPm_SystemSetMinRegulatorCurrent() function
+*/
+#define WAIT_DELAY_TRYES (100U)
+
+/* The define of retained power mode of the CM4 */
+#define CM4_PWR_STS_RETAINED (2UL)
+
+/* The define for number of callback roots */
+#define CALLBACK_ROOT_NR (5U)
+
+/* Mask for checking the CM4 Deep Sleep status */
+#define CM4_DEEPSLEEP_MASK (CPUSS_CM4_STATUS_SLEEPING_Msk | CPUSS_CM4_STATUS_SLEEPDEEP_Msk)
+
+/* Mask for checking the CM0P Deep Sleep status */
+#define CM0_DEEPSLEEP_MASK (CPUSS_CM0_STATUS_SLEEPING_Msk | CPUSS_CM0_STATUS_SLEEPDEEP_Msk)
+
+/* The mask to unlock the Hibernate power mode */
+#define HIBERNATE_UNLOCK_VAL ((uint32_t) 0x3Au << SRSS_PWR_HIBERNATE_UNLOCK_Pos)
+
+/* The mask to set the Hibernate power mode */
+#define SET_HIBERNATE_MODE ((HIBERNATE_UNLOCK_VAL |\
+ SRSS_PWR_HIBERNATE_FREEZE_Msk |\
+ SRSS_PWR_HIBERNATE_HIBERNATE_Msk))
+
+/* The mask to retain the Hibernate power mode status */
+#define HIBERNATE_RETAIN_STATUS_MASK ((SRSS_PWR_HIBERNATE_TOKEN_Msk |\
+ SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\
+ SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\
+ SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\
+ SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk))
+
+/** The mask for the Hibernate wakeup sources */
+#define HIBERNATE_WAKEUP_MASK ((SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\
+ SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\
+ SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\
+ SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk))
+
+/** The define to update the token to indicate the transition into Hibernate */
+#define HIBERNATE_TOKEN ((uint32_t) 0x1BU << SRSS_PWR_HIBERNATE_TOKEN_Pos)
+
+
+/* The mask for low power modes the power circuits (POR/BOD, Bandgap reference,
+* Reference buffer, Current reference) when active core regulator is LDO
+*/
+#define PWR_CIRCUITS_SET_LPMODE_LDO_MASK (SRSS_PWR_CTL_LINREG_LPMODE_Msk | PWR_CIRCUITS_SET_LPMODE_BUCK_MASK)
+
+/* The mask for low power modes the power circuits (POR/BOD, Bandgap reference,
+* Reference buffer, Current reference) when active core regulator is Buck
+*/
+#define PWR_CIRCUITS_SET_LPMODE_BUCK_MASK (SRSS_PWR_CTL_PORBOD_LPMODE_Msk |\
+ SRSS_PWR_CTL_BGREF_LPMODE_Msk |\
+ SRSS_PWR_CTL_VREFBUF_LPMODE_Msk |\
+ SRSS_PWR_CTL_IREF_LPMODE_Msk)
+
+/*******************************************************************************
+* Internal Variables
+*******************************************************************************/
+
+/* Array of the callback roots */
+static cy_stc_syspm_callback_t* pmCallbackRoot[CALLBACK_ROOT_NR] = {NULL, NULL, NULL, NULL, NULL};
+
+/* The array of the pointers to failed callback */
+static cy_stc_syspm_callback_t* failedCallback[CALLBACK_ROOT_NR] = {NULL, NULL, NULL, NULL, NULL};
+
+/* Structure for registers that should retain while Deep Sleep mode */
+static cy_stc_syspm_backup_regs_t bkpRegs;
+
+#if (CY_CPU_CORTEX_M4)
+ /* Global boolean variable used to clear the Event Register of the CM4 core */
+ static bool wasEventSent = false;
+#endif /* (CY_CPU_CORTEX_M4) */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_ReadStatus
+****************************************************************************//**
+*
+* Reads the power modes status of the system and CPU(s).
+*
+* \return
+* The current power mode. See \ref group_syspm_return_status.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_ReadStatus
+*
+*******************************************************************************/
+uint32_t Cy_SysPm_ReadStatus(void)
+{
+ uint32_t pmStatus = 0UL;
+
+ /* Check whether CM4 is in Deep Sleep mode */
+ if ((CPUSS_CM4_STATUS & CM4_DEEPSLEEP_MASK) == CM4_DEEPSLEEP_MASK)
+ {
+ pmStatus |= CY_SYSPM_STATUS_CM4_DEEPSLEEP;
+ }
+ /* Check whether CM4 is in Sleep mode */
+ else if(0U != _FLD2VAL(CPUSS_CM4_STATUS_SLEEPING, CPUSS_CM4_STATUS))
+ {
+ pmStatus |= CY_SYSPM_STATUS_CM4_SLEEP;
+ }
+ else
+ {
+ pmStatus |= CY_SYSPM_STATUS_CM4_ACTIVE;
+ }
+
+ /* Check whether CM0p is in Deep Sleep mode */
+ if ((CPUSS_CM0_STATUS & CM0_DEEPSLEEP_MASK) == CM0_DEEPSLEEP_MASK)
+ {
+ pmStatus |= CY_SYSPM_STATUS_CM0_DEEPSLEEP;
+ }
+ /* Check whether CM0p is in Sleep mode*/
+ else if (0U != _FLD2VAL(CPUSS_CM0_STATUS_SLEEPING, CPUSS_CM0_STATUS))
+ {
+ pmStatus |= CY_SYSPM_STATUS_CM0_SLEEP;
+ }
+ else
+ {
+ pmStatus |= CY_SYSPM_STATUS_CM0_ACTIVE;
+ }
+
+ /* Check whether the device is in LP mode by reading
+ * the core voltage:
+ * - 0.9V (nominal) - System ULP mode
+ * - 1.1V (nominal) - System LP mode
+ */
+
+ /* Read current active regulator */
+ if (Cy_SysPm_LdoIsEnabled())
+ {
+ /* Current active regulator is LDO */
+ if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_ULP)
+ {
+ pmStatus |= CY_SYSPM_STATUS_SYSTEM_LP;
+ }
+ else
+ {
+ pmStatus |= CY_SYSPM_STATUS_SYSTEM_ULP;
+ }
+ }
+ else
+ {
+ /* Current active regulator is Buck */
+ if (Cy_SysPm_BuckGetVoltage1() != CY_SYSPM_BUCK_OUT1_VOLTAGE_ULP)
+ {
+ pmStatus |= CY_SYSPM_STATUS_SYSTEM_LP;
+ }
+ else
+ {
+ pmStatus |= CY_SYSPM_STATUS_SYSTEM_ULP;
+ }
+ }
+
+ return pmStatus;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_CpuEnterSleep
+****************************************************************************//**
+*
+* Sets executing CPU to Sleep mode.
+*
+* Puts the CPU executing this function into CPU Sleep power mode. If callback
+* functions were registered they are also executed.
+*
+* For more detail about switching into CPU Sleep power mode and debug,
+* refer to the device technical reference manual (TRM).
+*
+* If at least one callback function with the CY_SYSPM_SLEEP type was registered,
+* the following algorithm is executed:
+* Prior to entering CPU Sleep mode, all callback functions of the CY_SYSPM_SLEEP
+* type with the CY_SYSPM_CHECK_READY parameter are called. This allows the
+* driver to signal whether it is ready to enter the low power mode. If any of
+* the callbacks of the CY_SYSPM_SLEEP type with the CY_SYSPM_CHECK_READY
+* parameter returns CY_SYSPM_FAIL, the remaining callbacks of the
+* CY_SYSPM_SLEEP type with the CY_SYSPM_CHECK_READY parameter are skipped.
+* After the first CY_SYSPM_FAIL, all the CY_SYSPM_SLEEP callbacks that were
+* previously executed before getting the CY_SYSPM_CHECK_FAIL are executed with
+* the CY_SYSPM_CHECK_FAIL parameter. The CPU Sleep mode is not entered and the
+* Cy_SysPm_CpuEnterSleep() function returns CY_SYSPM_FAIL.
+*
+* If all of the callbacks of the CY_SYSPM_SLEEP type with the
+* CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS, then all
+* callbacks of the CY_SYSPM_SLEEP type with the CY_SYSPM_CHECK_FAIL parameters
+* calls are skipped. All callbacks of the CY_SYSPM_SLEEP type and then
+* CY_SYSPM_BEFORE_TRANSITION parameter calls are executed, allowing the
+* peripherals to prepare for CPU Sleep. The CPU then enters Sleep mode.
+* This is a CPU-centric power mode. This means that the CPU has entered Sleep
+* mode and its main clock is removed. Any enabled interrupt can cause a CPU
+* wakeup from Sleep mode.
+*
+* For multi-core devices, CPU wakeup can also be performed using the Send Event
+* (SEV) assembly instruction executed from the other active CPU. Such wakeup is
+* expected only if the CPU Sleep power mode is done with WFE assembly
+* instruction.
+*
+* After a wakeup from CPU Sleep, all of the registered callbacks of the
+* CY_SYSPM_SLEEP type and with the CY_SYSPM_AFTER_TRANSITION parameter are
+* executed to return the peripherals to CPU active operation.
+* The Cy_SysPm_CpuEnterSleep() function returns CY_SYSPM_SUCCESS.
+* No callbacks of the CY_SYSPM_SLEEP type with the CY_SYSPM_BEFORE_TRANSITION
+* parameter or callbacks of the CY_SYSPM_SLEEP type and
+* CY_SYSPM_AFTER_TRANSITION parameter callbacks are executed if CPU Sleep mode
+* is not entered.
+*
+* \note The last callback that returns CY_SYSPM_FAIL is not executed with the
+* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating
+* CY_SYSPM_FAIL is expected to not make any changes that require being undone.
+*
+* To support control of callback execution order th following method is
+* implemented. Callback function with the CY_SYSPM_CHECK_READY and
+* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are
+* registered. Callback function with the CY_SYSPM_CHECK_FAIL and
+* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they
+* are registered.
+
+* The return value from executed callback functions with the
+* CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION
+* modes are ignored.
+*
+* \ref cy_en_syspm_callback_mode_t, except the CY_SYSPM_CHECK_READY, are ignored
+*
+* \note The Arm BSD assembly instruction is not required in this function
+* because the function implementation ensures the SLEEPDEEP bit of SCS register
+* is settled prior executing WFI/WFE instruction.
+*
+* \param waitFor
+* Selects wait for action. See \ref cy_en_syspm_waitfor_t.
+*
+* \return
+* Entered status, see \ref cy_en_syspm_status_t.
+*
+* \sideeffect
+* For CY8C6xx6, CY8C6xx7 devices this function clears the Event Register of the
+* CM4 CPU after wakeup from WFE.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_CpuEnterSleep
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor)
+{
+ uint32_t interruptState;
+ uint32_t cbSleepRootIdx = (uint32_t) CY_SYSPM_SLEEP;
+ cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
+
+ CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
+
+ /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */
+ if (pmCallbackRoot[cbSleepRootIdx] != NULL)
+ {
+ retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_READY);
+ }
+
+ /* The CPU can switch into the Sleep power mode only when
+ * all executed registered callback functions with the CY_SYSPM_CHECK_READY
+ * parameter return CY_SYSPM_SUCCESS.
+ */
+ if(retVal == CY_SYSPM_SUCCESS)
+ {
+ /* Call the registered callback functions with
+ * CY_SYSPM_BEFORE_TRANSITION parameter
+ */
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ if (pmCallbackRoot[cbSleepRootIdx] != NULL)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_BEFORE_TRANSITION);
+ }
+
+ /* The CPU enters the Sleep power mode upon execution of WFI/WFE */
+ SCB_SCR &= (uint32_t) ~SCB_SCR_SLEEPDEEP_Msk;
+
+ if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
+ {
+ __WFI();
+ }
+ else
+ {
+ __WFE();
+
+ #if (CY_CPU_CORTEX_M4)
+ if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2)
+ {
+ /* For the CM4 CPU, the WFE instruction is called twice.
+ * The second WFE call clears the Event Register of CM4 CPU.
+ * Cypress ID #279077.
+ */
+ if(wasEventSent)
+ {
+ __WFE();
+ }
+
+ wasEventSent = true;
+ }
+ #endif /* (CY_CPU_CORTEX_M4) */
+ }
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ /* Call the registered callback functions with the
+ * CY_SYSPM_AFTER_TRANSITION parameter
+ */
+ if (pmCallbackRoot[cbSleepRootIdx] != NULL)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_AFTER_TRANSITION);
+ }
+ }
+ else
+ {
+ /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
+ * undo everything done in the callback with the CY_SYSPM_CHECK_READY
+ * parameter
+ */
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_FAIL);
+ retVal = CY_SYSPM_FAIL;
+ }
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_CpuEnterDeepSleep
+****************************************************************************//**
+*
+* Sets executing CPU to the Deep Sleep mode.
+*
+* Puts the CPU executing the function into CPU Deep Sleep. For a single CPU
+* devices the device will immediately transition to system Deep Sleep. For a
+* dual CPU devices the device will transition to system Deep Sleep only after
+* both CPUs are in CPU Deep Sleep power mode.
+*
+* Prior to entering the CPU Deep Sleep mode, all callbacks of the
+* CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_READY parameter registered
+* callbacks are called, allowing the driver to signal whether it is ready to
+* enter the power mode. If any CY_SYSPM_DEEPSLEEP type with the
+* CY_SYSPM_CHECK_READY parameter call returns CY_SYSPM_FAIL, the remaining
+* callback CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_READY parameter are
+* skipped. After the first CY_SYSPM_FAIL, all the CY_SYSPM_DEEPSLEEP callbacks
+* that were previously executed before getting the CY_SYSPM_CHECK_FAIL are
+* executed with the CY_SYSPM_CHECK_FAIL parameter. The CPU Deep Sleep mode is
+* not entered and the Cy_SysPm_CpuEnterDeepSleep() function returns
+* CY_SYSPM_FAIL.
+*
+* If all callbacks of the CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_READY
+* parameter return CY_SYSPM_SUCCESS, then all callbacks of the
+* CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_FAIL parameter calls are
+* skipped. All callbacks of the CY_SYSPM_DEEPSLEEP type with the
+* CY_SYSPM_BEFORE_TRANSITION parameter calls are then executed, allowing the
+* peripherals to prepare for CPU Deep Sleep. The Deep Sleep mode is then
+* entered. Any enabled interrupt can cause a wakeup from the Deep Sleep mode.
+*
+* \note The last callback that returns CY_SYSPM_FAIL is not executed with the
+* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating
+* CY_SYSPM_FAIL is expected to not make any changes that require being undone.
+*
+* For multi-CPU devices (except CY8C6xx6 and CY8C6xx7) there is a possible
+* situation when a syscall operation (for example during flash read or write)
+* is executing. If the CM0+ CPU tries to enter Deep Sleep, it will fail. All
+* the CY_SYSPM_DEEPSLEEP callbacks that were previously executed, are executed
+* with the CY_SYSPM_CHECK_FAIL parameter. Deep Sleep mode is not entered and
+* the Cy_SysPm_CpuEnterDeepSleep() function returns CY_SYSPM_SYSCALL_PENDING.
+*
+* The return value from executed callback functions with the
+* CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION
+* modes are ignored.
+*
+* If the firmware attempts to enter this mode before the system is ready (that
+* is, when PWR_CONTROL.LPM_READY = 0), then the CPU(s) will go into the CPU
+* Sleep mode instead and automatically enter system Deep Sleep mode when the
+* system is ready. On dual CPU devices, if one CPU enters CPU Deep Sleep and the
+* other CPU remains active or is in CPU Sleep the first CPU will remain in CPU
+* Deep Sleep. A CPU Deep Sleep is functionally identical to CPU Sleep.
+*
+* The device enters system Deep Sleep mode when all the CPU(s) are in CPU
+* Deep Sleep, there are no busy peripherals, the debugger is not active, and the
+* Deep Sleep power and reference are ready (PWR_CONTROL.LPM_READY=1).
+*
+* The peripherals that do not need a clock or that receive a clock from their
+* external interface (e.g. I2C/SPI) may continue operating in system Deep Sleep.
+* All circuits using current from Vccdpslp supply are limited by its maximum
+* current specification of the Deep Sleep regulator.
+*
+* Wakeup occurs when an interrupt asserts from a Deep Sleep active peripheral.
+* For more detail, see the corresponding peripheral's datasheet.
+*
+* For multi-core devices, CPU wakeup can also be performed using the Send Event
+* (SEV) assembly instruction executed from the other active CPU. Such wakeup is
+* expected only if the CPU Sleep power mode is done with WFE assembly
+* instruction.
+*
+* \note
+* For multi-CPU devices, the second CPU, if it did not participate in
+* system wakeup, remains in CPU Deep Sleep mode. Any Deep Sleep capable
+* interrupt routed to this CPU can also wake it.
+*
+* For more detail about switching into the system Deep Sleep power mode and
+* debug, refer to the device TRM.
+*
+* A normal wakeup from the Deep Sleep power mode returns to either ULP or LP
+* mode, depending on the previous state and programmed behavior for the
+* particular wakeup interrupt. As soon as the system resumes LP or ULP mode the
+* CPU(s) return to CPU Active or CPU Deep Sleep mode, depending on their
+* configured wakeup settings.
+*
+* After wakeup from CPU Deep Sleep, all of the registered callbacks with
+* CY_SYSPM_DEEPSLEEP type with CY_SYSPM_AFTER_TRANSITION are executed to return
+* peripherals to active operation. The Cy_SysPm_CpuEnterDeepSleep() function
+* returns CY_SYSPM_SUCCESS. No callbacks are executed with CY_SYSPM_DEEPSLEEP
+* type with CY_SYSPM_BEFORE_TRANSITION or CY_SYSPM_AFTER_TRANSITION parameter,
+* if Deep Sleep mode was not entered.
+*
+* To support control of callback execution order th following method is
+* implemented. Callback function with the CY_SYSPM_CHECK_READY and
+* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are
+* registered. Callback function with the CY_SYSPM_CHECK_FAIL and
+* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they
+* are registered.
+*
+* \param waitFor
+* Selects wait for action. See \ref cy_en_syspm_waitfor_t.
+*
+* \sideeffect
+* This side effect is applicable only for devices with a UDBs.
+* You can obtain unpredictable behavior of the UDB block after the device wakeup
+* from system Deep Sleep.
+* Unpredictable behavior scenario:
+* * The first CPU saves non-retained UDB configuration registers and goes into
+* the CPU Deep Sleep (Cy_SysPm_CpuEnterDeepSleep() function).
+* * These non-retained UDB configuration registers are modified in runtime by
+* another (second) active CPU.
+* * The second CPU saves non-retained UDB configuration registers and goes into
+* the CPU Deep Sleep (Cy_SysPm_CpuEnterDeepSleep() function).
+* These conditions save different values of the non-retained UDB configuration
+* registers. On the first CPU wakeup (system wakeup from Deep Sleep), these
+* registers are restored by the values saved on the first CPU. After the
+* second CPU wakeup, these registers are "reconfigured" by the values saved on
+* the second CPU.
+* Be aware of this situation.
+*
+* \sideeffect
+* For CY8C6xx6, CY8C6xx7 devices this function clears the Event Register of the
+* CM4 CPU after wakeup from WFE.
+*
+* \sideeffect
+* This side effect is applicable only for rev-08 of the CY8CKIT-062.
+* This function changes the slow and fast clock dividers to
+* SYSPM_CLK_DIVIDER right before entering into system Deep Sleep and restores
+* these dividers after wakeup.
+*
+* \return
+* Entered status, see \ref cy_en_syspm_status_t.
+*
+* \note
+* The FLL/PLL are not restored right before the CPU(s) start executing the
+* instructions after system Deep Sleep. This can affect the peripheral that is
+* driven by PLL/FLL. Ensure that the PLL/FLL are properly restored (locked)
+* after wakeup from System Deep Sleep. Refer to the
+* \ref group_sysclk driver documentation for information about how to
+* read the PLL/FLL lock statuses.
+*
+* \note The Arm BSD assembly instruction is not required in this function
+* because the function implementation ensures the SLEEPDEEP bit of SCS register
+* is settled prior executing the WFI/WFE instruction.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_CpuEnterDeepSleep
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor)
+{
+ uint32_t interruptState;
+ uint32_t cbDeepSleepRootIdx = (uint32_t) CY_SYSPM_DEEPSLEEP;
+ cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
+
+ CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
+
+ /* Call the registered callback functions with the CY_SYSPM_CHECK_READY
+ * parameter
+ */
+ if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
+ {
+ retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_CHECK_READY);
+ }
+
+ /* The CPU can switch into the Deep Sleep power mode only when
+ * all executed registered callback functions with the CY_SYSPM_CHECK_READY
+ * parameter return CY_SYSPM_SUCCESS
+ */
+ if (retVal == CY_SYSPM_SUCCESS)
+ {
+ /* System Deep Sleep indicator */
+ bool wasSystemDeepSleep = false;
+
+ /* Call the registered callback functions with the
+ * CY_SYSPM_BEFORE_TRANSITION parameter
+ */
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_BEFORE_TRANSITION);
+ }
+
+ if (0U != cy_device->udbPresent)
+ {
+ /* Check whether the UDB disabled on MMIO level */
+ if (0UL != (PERI_GR_SL_CTL(MMIO_UDB_SLAVE_NR) & PERI_UDB_SLAVE_ENABLED))
+ {
+ /* Save non-retained registers */
+ Cy_SysPm_SaveRegisters(&bkpRegs);
+ }
+ }
+
+ /* Different device families and revisions have a different Deep Sleep entries */
+ if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2)
+ {
+ /* The CPU enters Deep Sleep and wakes up in the RAM */
+ wasSystemDeepSleep = EnterDeepSleepRam(waitFor);
+ }
+ else
+ {
+
+ #if (CY_CPU_CORTEX_M0P)
+
+ /* Check if there is a pending syscall */
+ if (Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) != false)
+ {
+ /* Do not put the CPU into Deep Sleep and return pending status */
+ retVal = CY_SYSPM_SYSCALL_PENDING;
+ }
+ else
+ #endif /* (CY_CPU_CORTEX_M0P) */
+
+ {
+ #if (CY_CPU_CORTEX_M4)
+ /* Repeat the WFI/WFE instruction if a wake up was not intended.
+ * Cypress ID #272909
+ */
+ do
+ {
+ #endif /* (CY_CPU_CORTEX_M4) */
+
+ /* The CPU enters Deep Sleep mode upon execution of WFI/WFE */
+ SCB_SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
+ {
+ __WFI();
+ }
+ else
+ {
+ __WFE();
+ }
+
+ #if (CY_CPU_CORTEX_M4)
+ } while (_FLD2VAL(CPUSS_CM4_PWR_CTL_PWR_MODE, CPUSS_CM4_PWR_CTL) == CM4_PWR_STS_RETAINED);
+ #endif /* (CY_CPU_CORTEX_M4) */
+ }
+ }
+
+ if (0U != cy_device->udbPresent)
+ {
+ /* Do not restore the UDBs if there was no system Deep Sleep mode or
+ * UDBs are disabled on MMIO level
+ */
+ if (wasSystemDeepSleep && (0UL != (PERI_GR_SL_CTL(MMIO_UDB_SLAVE_NR) & PERI_UDB_SLAVE_ENABLED)))
+ {
+ cy_stc_syspm_backup_regs_t *ptrRegs;
+
+ #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE
+ if (Cy_SysLib_GetDeviceRevision() == CY_SYSLIB_DEVICE_REV_0A)
+ {
+ ptrRegs = &bkpRegs;
+ }
+ else
+ #endif /* #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE */
+ {
+ ptrRegs = (cy_stc_syspm_backup_regs_t *) REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT));
+ }
+
+ /* Restore non-retained registers */
+ Cy_SysPm_RestoreRegisters(ptrRegs);
+ }
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+
+ if (retVal == CY_SYSPM_SUCCESS)
+ {
+ /* Call the registered callback functions with the CY_SYSPM_AFTER_TRANSITION
+ * parameter
+ */
+ if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_AFTER_TRANSITION);
+ }
+ }
+ else
+ {
+ /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
+ * undo everything done in the callback with the CY_SYSPM_CHECK_READY
+ * parameter
+ */
+ if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_CHECK_FAIL);
+ }
+
+ /* Rewrite return value to indicate fail */
+ if (retVal != CY_SYSPM_SYSCALL_PENDING)
+ {
+ retVal = CY_SYSPM_FAIL;
+ }
+ }
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_SystemEnterHibernate
+****************************************************************************//**
+*
+* Sets the device into system Hibernate mode.
+*
+* Puts the device into the system Hibernate power mode. Prior to entering
+* Hibernate mode, all callbacks of the CY_SYSPM_HIBERNATE type are executed.
+*
+* First, callbacks of the CY_SYSPM_HIBERNATE type are called with the
+* CY_SYSPM_CHECK_READY parameter. This allows the callback to signal that the
+* driver is not ready to enter the system Hibernate power mode. If any of the
+* callback return CY_SYSPM_FAIL, the remaining CY_SYSPM_HIBERNATE callbacks are
+* skipped. In this case, all of the callbacks that have already been called are
+* called again with the CY_SYSPM_CHECK_FAIL parameter. System Hibernate mode is
+* not entered and the Cy_SysPm_SystemEnterHibernate() function returns
+* CY_SYSPM_FAIL.
+*
+* If all CY_SYSPM_HIBERNATE callbacks with the CY_SYSPM_CHECK_READY parameter
+* return CY_SYSPM_SUCCESS, then all CY_SYSPM_HIBERNATE callbacks with
+* CY_SYSPM_CHECK_FAIL calls are skipped and all CY_SYSPM_HIBERNATE callbacks
+* with CY_SYSPM_BEFORE_TRANSITION parameter are executed allowing the
+* peripherals to prepare for system Hibernate.
+*
+* The I/O output state is automatically frozen by hardware system and Hibernate
+* mode is then entered. In Hibernate mode, all internal supplies are off and no
+* internal state is retained. The only exception is resources powered by the
+* Vbackup domain continue to operate, if enabled. For multi-CPU devices, there
+* is no handshake with the CPUs and the chip will enter Hibernate power
+* mode immediately.
+*
+* \note The last callback that returns CY_SYSPM_FAIL is not executed with the
+* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating
+* CY_SYSPM_FAIL is expected to not make any changes that require being undone.
+*
+* The return value from executed callback functions with the
+* CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION
+* modes are ignored.
+*
+* Wakeup from system Hibernate is triggered by toggling the wakeup pin(s), WDT
+* match, or back-up domain RTC alarm expiration, depending on how the they are
+* configured. A wakeup causes a normal boot procedure.
+* To configure the wakeup pin(s), a digital input pin must be configured, and
+* resistively pulled up or down to the inverse state of the wakeup polarity. To
+* distinguish a Hibernate mode from a general reset wakeup event, the
+* Cy_SysLib_GetResetReason() function can be used. The wakeup pin and low-power
+* comparators are active-low by default. The wakeup pin or the LPComparators
+* polarity can be changed with the \ref Cy_SysPm_SetHibernateWakeupSource()
+* function.
+* This function call will not return if system Hibernate mode is entered.
+* The CY_SYSPM_HIBERNATE callbacks with the CY_SYSPM_AFTER_TRANSITION parameter
+* are never executed.
+*
+* This function freezes the I/O pins implicitly. Entering system Hibernate mode
+* before freezing the I/O pins is not possible. The I/O pins remain frozen after
+* waking from Hibernate mode until the firmware unfreezes them with
+* a \ref Cy_SysPm_IoUnfreeze() function call.
+*
+* Boot firmware should reconfigure the I/O pins as required by the application
+* prior unfreezing them.
+*
+* To support control of callback execution order th following method is
+* implemented. Callback function with the CY_SYSPM_CHECK_READY and
+* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are
+* registered. Callback function with the CY_SYSPM_CHECK_FAIL and
+* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they
+* are registered.
+*
+* \return
+* Entered status, see \ref cy_en_syspm_status_t.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemEnterHibernate
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void)
+{
+ cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
+ uint32_t cbHibernateRootIdx = (uint32_t) CY_SYSPM_HIBERNATE;
+ /* Call the registered callback functions with the
+ * CY_SYSPM_CHECK_READY parameter
+ */
+ if (pmCallbackRoot[cbHibernateRootIdx] != NULL)
+ {
+ retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_READY);
+ }
+
+ /* The system can switch into Hibernate power mode only when
+ * all executed registered callback functions with CY_SYSPM_CHECK_READY
+ * parameter return CY_SYSPM_SUCCESS.
+ */
+ if(retVal == CY_SYSPM_SUCCESS)
+ {
+ /* Call registered callback functions with CY_SYSPM_BEFORE_TRANSITION
+ * parameter
+ */
+ (void) Cy_SysLib_EnterCriticalSection();
+ if (pmCallbackRoot[cbHibernateRootIdx] != NULL)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_BEFORE_TRANSITION);
+ }
+
+ /* Preserve the token that will be retained through a wakeup sequence.
+ * This could be used by Cy_SysLib_GetResetReason() to differentiate
+ * Wakeup from a general reset event.
+ * Preserve the wakeup source(s) configuration.
+ */
+ SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_WAKEUP_MASK) | HIBERNATE_TOKEN;
+
+ /* Disable overriding by the peripherals the next pin-freeze command */
+ SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
+
+ /* The second write causes freezing of I/O cells to save the I/O-cell state */
+ SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
+
+ /* Third write cause system to enter Hibernate */
+ SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
+
+ /* Read register to make sure it is settled */
+ (void) SRSS_PWR_HIBERNATE;
+
+ /* Wait for transition */
+ __WFI();
+
+ /* The callback function calls with the CY_SYSPM_AFTER_TRANSITION
+ * parameter in the Hibernate power mode are not applicable as system
+ * wake-up was made on system reboot.
+ */
+
+ /* A wakeup from Hibernate is performed by toggling of the wakeup
+ * pins, or WDT matches, or Backup domain alarm expires. This depends on
+ * what item is configured in the Hibernate register. After a wakeup
+ * event, a normal Boot procedure occurs.
+ * There is no need to exit from the critical section.
+ */
+ }
+ else
+ {
+ /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
+ * undo everything done in the callback with the CY_SYSPM_CHECK_READY
+ * parameter. The return value should be CY_SYSPM_SUCCESS.
+ */
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_FAIL);
+ retVal = CY_SYSPM_FAIL;
+ }
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_SystemEnterLp
+****************************************************************************//**
+*
+* Sets device into system Low Power mode.
+*
+* Returns the system to the default LP mode by raising the core voltage.
+* In the LP mode, the clock frequencies can be increased to t
+he LP mode
+* limitations. Refer to the device datasheet for frequency limitations in the
+* LP mode. Approximate LP limit values - \ref group_syspm_lp_limitations.
+*
+* Prior to entering the system LP mode, all the registered CY_SYSPM_LP callbacks
+* with CY_SYSPM_CHECK_READY parameter are called. This allows the driver to
+* signal that it is not ready to enter the system LP mode. If any CY_SYSPM_LP
+* callbacks with the CY_SYSPM_CHECK_READY parameter call return CY_SYSPM_FAIL,
+* the remaining CY_SYSPM_LP callbacks with the
+* CY_SYSPM_CHECK_READY parameter calls are skipped.
+*
+* After a CY_SYSPM_FAIL, all of the CY_SYSPM_LP callbacks with
+* CY_SYSPM_CHECK_FAIL parameter are executed that correspond to the
+* CY_SYSPM_LP callbacks with CY_SYSPM_CHECK_READY parameter that occurred up to
+* the point of failure. System LP mode is not entered and the
+* Cy_SysPm_SystemEnterLp() function returns CY_SYSPM_FAIL.
+*
+* If all CY_SYSPM_LP callbacks with the CY_SYSPM_CHECK_READY
+* parameter return CY_SYSPM_SUCCESS, then all CY_SYSPM_LP callbacks with
+* CY_SYSPM_CHECK_FAIL are skipped and all CY_SYSPM_LP callbacks with the
+* CY_SYSPM_BEFORE_TRANSITION parameter are executed. This allows the
+* peripherals to prepare for LP mode. The system LP mode is then entered.
+*
+* After entering the system LP mode, all of the registered
+* CY_SYSPM_LP callbacks with the CY_SYSPM_AFTER_TRANSITION parameter
+* are executed to complete preparing the peripherals for low power operation.
+* The Cy_SysPm_SystemEnterLp() function returns CY_SYSPM_SUCCESS.
+* No CY_SYSPM_LP callbacks with the CY_SYSPM_BEFORE_TRANSITION or
+* CY_SYSPM_AFTER_TRANSITION parameter are executed if the system LP mode is not
+* entered.
+*
+* \note The last callback that returns CY_SYSPM_FAIL is not executed with the
+* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating
+* CY_SYSPM_FAIL is expected to not make any changes that require being undone.
+*
+* The return value from executed callback functions with the
+* CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION
+* modes are ignored.
+*
+* To support control of callback execution order th following method is
+* implemented. Callback function with the CY_SYSPM_CHECK_READY and
+* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are
+* registered. Callback function with the CY_SYSPM_CHECK_FAIL and
+* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they
+* are registered.
+*
+* \return
+* - CY_SYSPM_SUCCESS - Entered the system LP mode.
+* - CY_SYSPM_INVALID_STATE - The system LP mode was not set. The system LP mode
+* was not set because the protection context value is higher than zero
+* (PC > 0) or the device revision does not support modifying registers
+* (to enter LP mode) via syscall.
+* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until
+* the function returns CY_SYSPM_SUCCESS.
+* - CY_SYSPM_FAIL - The system LP mode is not entered.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemEnterLp
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void)
+{
+ uint32_t interruptState;
+ uint32_t cbLpRootIdx = (uint32_t) CY_SYSPM_LP;
+ cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
+
+ /* Call the registered callback functions with the
+ * CY_SYSPM_CHECK_READY parameter
+ */
+ if (pmCallbackRoot[cbLpRootIdx] != NULL)
+ {
+ retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_CHECK_READY);
+ }
+
+ /* The system can switch into LP only when
+ * all executed registered callback functions with the
+ * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS
+ */
+ if (retVal == CY_SYSPM_SUCCESS)
+ {
+
+ /* Call the registered callback functions with the
+ * CY_SYSPM_BEFORE_TRANSITION parameter
+ */
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ if (pmCallbackRoot[cbLpRootIdx] != NULL)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_BEFORE_TRANSITION);
+ }
+
+ /* Read current active regulator and set LP voltage*/
+ if (Cy_SysPm_LdoIsEnabled())
+ {
+ /* Current active regulator is LDO */
+ if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_LP)
+ {
+ retVal = Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
+ }
+ }
+ else
+ {
+ /* Current active regulator is Buck */
+ if (Cy_SysPm_BuckGetVoltage1() != CY_SYSPM_BUCK_OUT1_VOLTAGE_LP)
+ {
+ retVal = Cy_SysPm_BuckSetVoltage1(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
+ }
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ /* Call the registered callback functions with the
+ * CY_SYSPM_AFTER_TRANSITION parameter
+ */
+ if (pmCallbackRoot[cbLpRootIdx] != NULL)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_AFTER_TRANSITION);
+ }
+ }
+ else
+ {
+ /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
+ * undo everything done in the callback with the CY_SYSPM_CHECK_READY
+ * parameter
+ */
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_CHECK_FAIL);
+ retVal = CY_SYSPM_FAIL;
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_SystemEnterUlp
+****************************************************************************//**
+*
+* Sets device into system Ultra Low Power mode.
+*
+* System ULP mode is similar to system LP mode. The difference is that the
+* system is put under \ref group_syspm_ulp_limitations.
+*
+* Before entering system ULP mode, the user must configure the system so
+* the maximum clock frequencies are less than the ULP mode specifications
+* presented in the device datasheet. Refer to the device datasheet for
+* the maximum clock limitations in the ULP mode with reduced core supply
+* regulator voltages.
+*
+* Prior to entering system ULP mode, all the registered CY_SYSPM_ULP callbacks
+* with CY_SYSPM_CHECK_READY parameter are called. This allows the driver to
+* signal if it is not ready to enter system ULP mode. If any CY_SYSPM_ULP
+* callback with the CY_SYSPM_CHECK_READY parameter call returns CY_SYSPM_FAIL,
+* the remaining CY_SYSPM_ULP callbacks with the CY_SYSPM_CHECK_READY parameter
+* are skipped.
+*
+* After a CY_SYSPM_FAIL, all of the CY_SYSPM_ULP callbacks with the
+* CY_SYSPM_CHECK_FAIL parameter are executed that correspond to the
+* CY_SYSPM_ULP callback with CY_SYSPM_CHECK_READY parameter that occurred up to
+* the point of failure. System ULP mode is not entered
+* and the Cy_SysPm_SystemEnterUlp() function returns CY_SYSPM_FAIL.
+*
+* If all CY_SYSPM_ULP callbacks with the CY_SYSPM_CHECK_READY
+* parameter return CY_SYSPM_SUCCESS, then all CY_SYSPM_ULP
+* callbacks with CY_SYSPM_CHECK_FAIL calls are skipped and all CY_SYSPM_ULP
+* callbacks with the CY_SYSPM_BEFORE_TRANSITION parameter are executed. This
+* allows preparation for ULP. The system ULP mode is then entered.
+*
+* After entering system ULP, all of the registered CY_SYSPM_ULP callbacks with
+* the CY_SYSPM_AFTER_TRANSITION parameter are executed to complete preparing the
+* peripherals for ULP operation. The Cy_SysPm_SystemEnterUlp() function
+* returns CY_SYSPM_SUCCESS. No CY_SYSPM_ULP callbacks with the
+* CY_SYSPM_BEFORE_TRANSITION or CY_SYSPM_AFTER_TRANSITION parameter are
+* executed, if ULP mode is not entered.
+*
+* \note The last callback that returns CY_SYSPM_FAIL is not executed with the
+* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating
+* CY_SYSPM_FAIL is expected to not make any changes that require being undone.
+*
+* The return value from executed callback functions with the
+* CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION
+* modes are ignored.
+*
+* To support control of callback execution order th following method is
+* implemented. Callback function with the CY_SYSPM_CHECK_READY and
+* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are
+* registered. Callback function with the CY_SYSPM_CHECK_FAIL and
+* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they
+* are registered.
+*
+* \return
+* - CY_SYSPM_SUCCESS - Entered system ULP mode.
+* - CY_SYSPM_INVALID_STATE - System ULP mode was not set. The ULP mode was not
+* set because the protection context value is higher than zero (PC > 0) or the
+* device revision does not support modifying registers (to enter system
+* ULP mode) via syscall.
+* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until
+* the function returns CY_SYSPM_SUCCESS.
+* - CY_SYSPM_FAIL - The system ULP mode is not entered.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemEnterUlp
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void)
+{
+ uint32_t interruptState;
+ cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
+ uint32_t cbUlpRootIdx = (uint32_t) CY_SYSPM_ULP;
+
+ /* Call the registered callback functions with the
+ * CY_SYSPM_CHECK_READY parameter
+ */
+ if (pmCallbackRoot[cbUlpRootIdx] != NULL)
+ {
+ retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_CHECK_READY);
+ }
+
+ /* The system can switch into the ULP only when
+ * all executed registered callback functions with the
+ * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS
+ */
+ if (retVal == CY_SYSPM_SUCCESS)
+ {
+ /* Call the registered callback functions with the
+ * CY_SYSPM_BEFORE_TRANSITION parameter
+ */
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ if (pmCallbackRoot[cbUlpRootIdx] != NULL)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_BEFORE_TRANSITION);
+ }
+
+ /* Read current active regulator and set ULP voltage*/
+ if (Cy_SysPm_LdoIsEnabled())
+ {
+ /* Current active regulator is LDO */
+ if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_ULP)
+ {
+ retVal = Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_ULP);
+ }
+ }
+ else
+ {
+ /* Current active regulator is Buck */
+ if (Cy_SysPm_BuckGetVoltage1() != CY_SYSPM_BUCK_OUT1_VOLTAGE_ULP)
+ {
+ retVal = Cy_SysPm_BuckSetVoltage1(CY_SYSPM_BUCK_OUT1_VOLTAGE_ULP);
+ }
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ /* Call the registered callback functions with the
+ * CY_SYSPM_AFTER_TRANSITION parameter
+ */
+ if (pmCallbackRoot[cbUlpRootIdx] != NULL)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_AFTER_TRANSITION);
+ }
+ }
+ else
+ {
+ /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
+ * undo everything done in the callback with the CY_SYSPM_CHECK_READY
+ * parameter
+ */
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_CHECK_FAIL);
+ retVal = CY_SYSPM_FAIL;
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_SystemSetMinRegulatorCurrent
+****************************************************************************//**
+*
+* Sets the system into minimum core regulator current mode. This mode limits
+* maximum current available for the system core logic.
+*
+* Minimum regulator current mode modifies operation of the system in LP or ULP
+* modes to further reduce current consumption. If the system current is below
+* datasheet current limits for the active core voltage regulator (LDO or Buck),
+* this mode may be entered. The user is responsible for ensuring the
+* regulator current limit is met in their application.
+*
+* When in minimum regulator current mode, the following system resources are
+* also set to their LP mode:
+* - Linear regulator (If LDO is active regulator)
+* - POR/BOD circuit
+* - Bandgap reference circuit
+* - Reference buffer circuit
+* - Current reference circuit
+*
+* The LDO and Buck current limits must be met prior to entering this
+* mode. If these are not met, the device may brown out, resulting in an
+* exception or reset. These changes also reduce power supply rejection of
+* the affected system resources, which can result in increased noise or response
+* time. These effects must be evaluated in each application.
+*
+* \return
+* See \ref cy_en_syspm_status_t.
+* - CY_SYSPM_SUCCESS - Minimum regulator current mode was set
+* - CY_SYSPM_CANCELED - The power circuits were not ready to enter into
+* minimum current mode. You should call the function again.
+*
+* Refer to device datasheet for maximum current value in regulator minimum
+* current mode.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemSetMinRegulatorCurrent
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void)
+{
+ cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED;
+
+ /* Check are the power circuits are ready to enter into regulator minimum
+ * current mode
+ */
+ if (0U != _FLD2VAL(SRSS_PWR_CTL_LPM_READY, SRSS_PWR_CTL))
+ {
+ /* Configure the minimum current mode for LDO regulator */
+ if(Cy_SysPm_LdoIsEnabled())
+ {
+ SRSS_PWR_CTL |= PWR_CIRCUITS_SET_LPMODE_LDO_MASK;
+ }
+ else
+ {
+ /* Configure the minimum current mode for Buck regulator */
+ SRSS_PWR_CTL |= PWR_CIRCUITS_SET_LPMODE_BUCK_MASK;
+ }
+
+ /* This wait time allows the circuits to remove their dependence on
+ * the Active mode circuits, such as active Reference
+ */
+ Cy_SysLib_DelayUs(SET_MIN_CURRENT_MODE_DELAY_US);
+
+ /* Disable active reference */
+ SRSS_PWR_CTL |= SRSS_PWR_CTL_ACT_REF_DIS_Msk;
+
+ retVal = CY_SYSPM_SUCCESS;
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_SystemSetNormalRegulatorCurrent
+****************************************************************************//**
+*
+* Sets the system to normal regulator current mode.
+*
+* Normal regulator current mode modifies operation of the system in LP or ULP
+* modes to provide maximum core current consumption. If the LDO core regulator
+* is in use, the normal mode output current limits may be used. If the buck
+* regulator is in use, its reduced current output limits still apply.
+*
+* When in normal regulator current mode, the following system resources are set
+* to their normal mode:
+* - Linear regulator (If LDO is active regulator)
+* - POR/BOD circuit
+* - Bandgap reference circuit
+* - Reference buffer circuit
+* - Current reference circuit
+*
+* \return
+* - CY_SYSPM_SUCCESS - Normal regulator current mode was set
+* - CY_SYSPM_TIMEOUT - The timeout occurred because device was not
+* ready to enter into the normal regulator current mode
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemSetNormalRegulatorCurrent
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void)
+{
+ uint32_t timeOut = WAIT_DELAY_TRYES;
+ cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
+
+ /* Configure the regulator normal current mode for the POR/BOD circuits
+ * and for the Bandgap Voltage and Current References
+ */
+ if (Cy_SysPm_LdoIsEnabled())
+ {
+ SRSS_PWR_CTL &= (uint32_t) ~CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_LDO_MASK;
+ }
+ else
+ {
+ SRSS_PWR_CTL &= (uint32_t) ~CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_BUCK_MASK;
+ }
+
+ /* This wait time allows setting active Reference */
+ Cy_SysLib_DelayUs(ACT_REF_SETTLE_DELAY_US);
+
+ while ((0U == _FLD2VAL(SRSS_PWR_CTL_ACT_REF_OK, SRSS_PWR_CTL)) && (0U != timeOut))
+ {
+ timeOut--;
+ }
+
+ if (0U != timeOut)
+ {
+ /* Disable the low-power for Bandgap reference circuit */
+ SRSS_PWR_CTL &= (uint32_t) ~SRSS_PWR_CTL_BGREF_LPMODE_Msk;
+
+ /* Delay to finally set the normal current mode */
+ Cy_SysLib_DelayUs(SET_NORMAL_CURRENT_MODE_DELAY_US);
+
+ retVal= CY_SYSPM_SUCCESS;
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_CpuSleepOnExit
+****************************************************************************//**
+*
+* This function configures the sleep-on-exit feature of the CPU.
+*
+* This API sets the SLEEPONEXIT bit of the SCR register.
+*
+* When the sleep-on-exit feature is enabled (the SLEEPONEXIT bit is set),
+* the CPU wakes up to service the interrupt and then immediately goes
+* back to sleep. Because of this, the unstacking process is not carried out, so
+* this feature is useful for interrupt driven application and helps to
+* reduce unnecessary stack push and pop operations.
+* The CPU does not go to sleep if the interrupt handler returns to
+* another interrupt handler (nested interrupt).
+* You can use this feature in applications that require the CPU to only run
+* when an interrupt occurs.
+*
+* When the sleep-on-exit feature is disabled (the SLEEPONEXIT bit is cleared),
+* the CPU returns back to the main thread after servicing the interrupt
+* without going back to sleep.
+*
+* Refer to the Arm documentation about the sleep-on-exit feature and
+* SLEEPONEXIT in the SCR register.
+*
+* \param enable
+* - True if enable sleep-on-exit feature.
+* - False if disable sleep-on-exit feature.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_CpuSleepOnExit
+*
+*******************************************************************************/
+void Cy_SysPm_CpuSleepOnExit(bool enable)
+{
+ if(enable)
+ {
+ /* Enable sleep-on-exit feature */
+ SCB_SCR |= SCB_SCR_SLEEPONEXIT_Msk;
+ }
+ else
+ {
+ /* Disable sleep-on-exit feature */
+ SCB_SCR &= (uint32_t) ~(SCB_SCR_SLEEPONEXIT_Msk);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_SetHibernateWakeupSource
+****************************************************************************//**
+*
+* This function configures sources to wake up the device from the system
+* Hibernate power mode. Sources can be wakeup pins, LPComparators, Watchdog (WDT)
+* interrupt, or a Real-Time clock (RTC) alarm (interrupt). Wakeup from system
+* Hibernate always results in a device reset and normal boot process.
+*
+* Wakeup pins:
+*
+* A wakeup is supported by up to two pins with programmable polarity. These pins
+* are typically connected to the GPIO pins or on-chip peripherals under some
+* conditions. See device datasheet for specific pin connections.
+* Setting the wakeup pin to this level will cause a wakeup from system Hibernate
+* mode. The wakeup pins are active-low by default.
+*
+* LPComparators:
+*
+* A wakeup is supported by up to two LPComps with programmable polarity.
+* Setting the LPComp to this level will cause a wakeup from system Hibernate
+* mode. The wakeup LPComps are active-low by default.
+*
+* \note The low-power comparators should be configured and enabled before
+* switching to system Hibernate mode. Refer to the LPComp
+* driver description for more detail.
+*
+* Watchdog Timer:
+*
+* \note The WDT should be configured and enabled before entering to system
+* Hibernate mode.
+*
+* A wakeup is performed by a WDT interrupt.
+*
+* Real-time Clock:
+*
+* A wakeup is performed by the RTC alarm.
+* Refer to the Real-Time Clock (RTC) driver description for more detail.
+*
+* For information about wakeup sources and their assignment in specific
+* devices, refer to the appropriate device TRM.
+*
+* \param wakeupSource
+* The source to be configured as a wakeup source from
+* the system Hibernate power mode, see \ref cy_en_syspm_hibernate_wakeup_source_t.
+* The input parameter values can be ORed. For example, if you want to enable
+* LPComp0 (active high) and WDT, call this function:
+* Cy_SysPm_SetHibernateWakeupSource(CY_SYSPM_HIBERNATE_LPCOMP0_HIGH | CY_SYSPM_HIBERNATE_WDT).
+*
+* \warning Do not call this function with different polarity levels for the same
+* wakeup source. For example, do not call a function like this:
+* Cy_SysPm_SetHibernateWakeupSource(CY_SYSPM_HIBERNATE_LPCOMP0_LOW, CY_SYSPM_HIBERNATE_LPCOMP0_HIGH);
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SetHibernateWakeupSource
+*
+*******************************************************************************/
+void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
+
+ uint32_t polarityMask = 0U;
+
+ if (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, wakeupSource))
+ {
+ /* Reconfigure the wakeup pins and LPComp polarity based on the input */
+ if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK))
+ {
+ polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK;
+ }
+
+ if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK))
+ {
+ polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK;
+ }
+
+ if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_PIN0_MASK))
+ {
+ polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK;
+ }
+
+ if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_PIN1_MASK))
+ {
+ polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK;
+ }
+ }
+
+ SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & (uint32_t) ~polarityMask) | wakeupSource;
+
+ /* Read register to make sure it is settled */
+ (void) SRSS_PWR_HIBERNATE;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_ClearHibernateWakeupSource
+****************************************************************************//**
+*
+* This function disables a wakeup source that was previously configured to
+* wake up the device from the system Hibernate mode.
+*
+* \param wakeupSource
+* For the source to be disabled, see \ref cy_en_syspm_hibernate_wakeup_source_t.
+* The input parameters values can be ORed. For example, if you want to disable
+* LPComp0 (active high) and WDT call this function:
+* Cy_SysPm_ClearHibernateWakeupSource(CY_SYSPM_HIBERNATE_LPCOMP0_HIGH | CY_SYSPM_HIBERNATE_WDT).
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_ClearHibernateWakeupSource
+*
+*******************************************************************************/
+void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
+
+ uint32_t clearWakeupSourceMask = wakeupSource & (uint32_t) ~SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk;
+
+ if (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, wakeupSource))
+ {
+ /* Clear the high active level of the requested sources */
+ if ((uint32_t) CY_SYSPM_HIBERNATE_LPCOMP0_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_LPCOMP0_HIGH))
+ {
+ clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK;
+ }
+
+ if ((uint32_t) CY_SYSPM_HIBERNATE_LPCOMP1_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_LPCOMP1_HIGH))
+ {
+ clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK;
+ }
+
+ if ((uint32_t) CY_SYSPM_HIBERNATE_PIN0_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_PIN0_HIGH))
+ {
+ clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK;
+ }
+
+ if ((uint32_t) CY_SYSPM_HIBERNATE_PIN1_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_PIN1_HIGH))
+ {
+ clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK;
+ }
+ }
+
+ SRSS_PWR_HIBERNATE &= (uint32_t) ~clearWakeupSourceMask;
+
+ /* Read register to make sure it is settled */
+ (void) SRSS_PWR_HIBERNATE;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BuckEnable
+****************************************************************************//**
+*
+* Switch the core supply regulator to Buck core regulator instead of the LDO
+* regulator.
+* The Buck core regulator provides output voltage(s) using one external
+* inductor and can supply Vccd with higher efficiency than the LDO under some
+* conditions, such as high external supply voltage.
+*
+* Before changing from LDO to Buck, ensure that the circuit board has
+* connected Vccbuck1 to Vccd and also populated the
+* necessary external components for the Buck regulator, including an
+* inductor and a capacitor for each output.
+* Refer to the device TRM for more detail.
+*
+* When changing from a higher voltage to a lower voltage
+* (from system LP = LDO 1.1 V (nominal) to system ULP = Buck 0.9 V (nominal)),
+* ensure that:
+* * The device maximum operating frequency for all the Clk_HF paths, peripheral,
+* and slow clock are under the \ref group_syspm_ulp_limitations.
+* * The total current consumption is under the \ref group_syspm_ulp_limitations.
+*
+* * The appropriate wait states values are set for the flash using
+* the Cy_SysLib_SetWaitStates() function as explained below.
+*
+* <b>Setting wait states values for flash</b>
+*
+* The flash access time when the core output voltage is 0.9 V (nominal) is
+* longer than at 1.1 V (nominal). Therefore, the number of the wait states must
+* be adjusted. Use the Cy_SysLib_SetWaitStates() function to set the appropriate
+* wait state values for flash.
+*
+* To change from a higher voltage (LDO 1.1 V) to a lower voltage (Buck 0.9 V),
+* call the Cy_SysLib_SetWaitStates(true, hfClkFreqMz) function before changing
+* the voltage, where hfClkFreqMz is the frequency of HfClk0 in MHz.
+*
+* To change from a lower voltage (LDO 0.9 V (nominal) to a higher voltage
+* (Buck 1.1 V (nominal)), call the Cy_SysLib_SetWaitStates(false,
+* hfClkFreqMz) function to set the wait states after the voltage change.
+* It is optional, but can be done to improve performance. The clock frequency
+* may now be increased up to system LP mode limits for the new voltage.
+*
+* \note 1. If the final Buck output is set to 0.9 V (nominal) - the system is in
+* ULP mode and flash allows read-only operations.
+* \note 2. If the final Buck output is set to 1.1 V (nominal) - the system is in
+* LP mode flash allows the read and write operations.
+* \note 3. The actual device Vccd voltage can be different from the nominal
+* voltage because the actual voltage value depends on conditions
+* including the load current.
+*
+* \warning There is no safe way to go back to the LDO after the
+* Buck regulator supplies a core. The function enabling the BUck regulator
+* switches off the LDO.
+*
+* For more detail, refer to the \ref group_syspm_switching_into_ulp and
+* \ref group_syspm_switching_into_lp sections.
+* Refer to the \ref group_syslib driver for more detail about setting wait
+* states.
+*
+* \param voltage
+* The desired output 1 regulator voltage (Vccbuck1).
+* See \ref cy_en_syspm_buck_voltage1_t.
+*
+* \return
+* - CY_SYSPM_SUCCESS - The voltage is set.
+* - CY_SYSPM_INVALID_STATE - The voltage was not set. The voltage cannot be set
+* because the protection context value is higher than zero (PC > 0) or the
+* device revision does not support modifying registers via syscall.
+* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until
+* the function returns CY_SYSPM_SUCCESS. See \ref cy_en_syspm_status_t.
+*
+* \note
+* The function is applicable only for devices with a Buck regulator.
+*
+* Function uses a critical section to prevent interrupting the regulators
+* switch.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckEnable
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_BUCK_VOLTAGE1_VALID(voltage));
+
+ cy_en_syspm_status_t retVal = CY_SYSPM_INVALID_STATE;
+
+ /* Enable the Buck regulator only if it was not enabled previously.
+ * If the LDO is disabled, the device is sourced by the Buck regulator
+ */
+ if (Cy_SysPm_LdoIsEnabled())
+ {
+ uint32_t interruptState;
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ /* Update the RAM and ROM trim values when final target Buck 0.9 V */
+ if (CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V == voltage)
+ {
+ if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_0_9V)
+ {
+ retVal = Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_0_9V);
+ }
+ else
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ }
+
+ if (CY_SYSPM_SUCCESS == retVal)
+ {
+ /* Increase LDO output voltage to 0.95 V nominal */
+ SRSS_PWR_TRIM_PWRSYS_CTL = _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL),
+ SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_0_95V);
+ }
+ }
+
+ /* Update the RAM and ROM trim values when the final target Buck 1.1 V */
+ if (CY_SYSPM_BUCK_OUT1_VOLTAGE_1_1V == voltage)
+ {
+ if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_1_1V)
+ {
+ retVal = Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_1_1V);
+ }
+ else
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ }
+
+ if (CY_SYSPM_SUCCESS == retVal)
+ {
+ /* Set the LDO 1.15 V as final Buck output is 1.1 V */
+ SRSS_PWR_TRIM_PWRSYS_CTL = _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL),
+ SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_1_15V);
+ }
+ }
+
+ /* Proceed only if previous settings were done successfully */
+ if (CY_SYSPM_SUCCESS == retVal)
+ {
+ /* A delay for the supply to stabilize at the new voltage */
+ Cy_SysLib_DelayUs(LDO_STABILIZATION_DELAY_US);
+
+ /* Disable the Deep Sleep, nWell, and Retention regulators */
+ SRSS_PWR_CTL |= (_VAL2FLD(SRSS_PWR_CTL_DPSLP_REG_DIS, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_RET_REG_DIS, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_NWELL_REG_DIS, 1U));
+
+ /* Configure the Buck regulator */
+ SRSS_PWR_BUCK_CTL =
+ _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, (uint32_t) voltage);
+
+ SRSS_PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_EN, 1U);
+
+ SRSS_PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN, 1U);
+
+ /* Wait until Buck output 1 is stable */
+ Cy_SysLib_DelayUs(BUCK_INIT_STABILIZATION_US);
+
+ /* Disable the LDO, because Vbuckout1 and LDO are shorted */
+ SRSS_PWR_CTL |= _VAL2FLD(SRSS_PWR_CTL_LINREG_DIS, 1U);
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+ else
+ {
+ /* The Buck is already enabled, so just update the Buck voltage */
+ cy_en_syspm_buck_voltage1_t curBuckVoltage = Cy_SysPm_BuckGetVoltage1();
+
+ if (voltage != curBuckVoltage)
+ {
+ retVal = Cy_SysPm_BuckSetVoltage1(voltage);
+ }
+ else
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BuckSetVoltage1
+****************************************************************************//**
+*
+* Sets the output 1 voltage for the Buck regulator that can supply the device
+* core. This output can supply the device core instead of the LDO regulator.
+*
+* When changing from a higher voltage 1.1 V (nominal) to a lower voltage 0.9 V
+* (nominal), ensure that:
+* * The device maximum operating frequency for all the Clk_HF paths, peripheral,
+* and slow clock are under the \ref group_syspm_ulp_limitations.
+* * The total current consumption is under the \ref group_syspm_ulp_limitations.
+* * The appropriate wait states values are set for the flash using
+* the Cy_SysLib_SetWaitStates() function as explained below.
+*
+* <b>Setting wait states values for flash</b>
+*
+* The flash access time when the core output voltage is 0.9 V (nominal) is
+* longer than at 1.1 V (nominal). Therefore, the number of the wait states must
+* be adjusted. Use the Cy_SysLib_SetWaitStates() function to set the appropriate
+* wait state values for flash.
+*
+* To change from a higher voltage to a lower voltage 0.9 V (nominal),
+* call the Cy_SysLib_SetWaitStates(true, hfClkFreqMz) function before changing
+* the voltage, where hfClkFreqMz is the frequency of HfClk0 in MHz.
+*
+* To change from a lower voltage to a higher voltage 1.1 V (nominal), call
+* the Cy_SysLib_SetWaitStates(false, hfClkFreqMz) function to set the
+* wait states. It is optional, but can be done to improve the performance.
+* The clock frequency may now be increased up to
+* \ref group_syspm_lp_limitations for a new voltage.
+*
+* \note 1. The output is set to 0.9 V (nominal) - the system is in ULP mode
+* flash allows read-only operations.
+* \note 2. The output is set to 1.1 V (nominal) - the system is in LP mode and
+* flash allows the read and write operations.
+* \note 3. The actual device Vccd voltage can be different from the nominal
+* voltage because the actual voltage value depends on the conditions
+* including the load current.
+*
+* For more detail, refer to the \ref group_syspm_switching_into_ulp and
+* \ref group_syspm_switching_into_lp sections.
+* Refer to the \ref group_syslib driver for more detail about setting the
+* wait states.
+*
+* \param voltage
+* The desired output 1 regulator voltage (Vccbuck1).
+* See \ref cy_en_syspm_buck_voltage1_t
+*
+* \return
+* - CY_SYSPM_SUCCESS - The voltage is set.
+* - CY_SYSPM_INVALID_STATE - The voltage was not set. The voltage cannot be set
+* because the protection context value is higher than zero (PC > 0) or the
+* device revision does not support modifying registers via syscall.
+* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until
+* the function returns CY_SYSPM_SUCCESS. See \ref cy_en_syspm_status_t.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltage)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_BUCK_VOLTAGE1_VALID(voltage));
+
+ cy_en_syspm_status_t retVal = CY_SYSPM_INVALID_STATE;
+
+ /* Change the voltage only if protection context is set to zero (PC = 0)
+ * or the device revision supports modifying registers via syscall
+ */
+ if (IsVoltageChangePossible())
+ {
+ uint32_t interruptState;
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ if (CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V == voltage)
+ {
+ /* Set bit of the flash voltage control register before ULP mode is set */
+ retVal = Cy_SysPm_WriteVoltageBitForFlash(CY_SYSPM_FLASH_VOLTAGE_BIT_ULP);
+
+ if (CY_SYSPM_SUCCESS == retVal)
+ {
+ /* Update read-write margin value for the ULP mode */
+ SetReadMarginTrimUlp();
+ }
+ }
+ else
+ {
+ /* Increase Buck output voltage to 0.95 V nominal */
+ SRSS_PWR_BUCK_CTL =
+ _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, BUCK_OUT1_VOLTAGE_0_95V);
+
+ /* Wait until regulator is stable on higher intermediate voltage */
+ Cy_SysLib_DelayUs(BUCK_OUT1_0_9V_TO_0_95V_DELAY_US);
+
+ /* Update write assist value for the LP mode */
+ SetWriteAssistTrimLp();
+
+ retVal = CY_SYSPM_SUCCESS;
+ }
+
+ /* Proceed only if previous settings were done successfully */
+ if (CY_SYSPM_SUCCESS == retVal)
+ {
+ /* The system may continue operating while the voltage on Vccd
+ * discharges to the new voltage. The time it takes to reach the
+ * new voltage depends on the conditions, including the load current
+ * on Vccd and the external capacitor size.
+ */
+ SRSS_PWR_BUCK_CTL =
+ _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, (uint32_t) voltage);
+
+ if (CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V == voltage)
+ {
+ /* Update write assist value for the ULP mode */
+ SetWriteAssistTrimUlp();
+ }
+ else
+ {
+ /* Delay stabilizing at the new voltage is required only
+ * when changing from a lower voltage to a higher voltage
+ */
+ Cy_SysLib_DelayUs(BUCK_OUT1_0_95V_TO_1_1V_DELAY_US);
+
+ /* Update read-write margin value for the LP mode */
+ SetReadMarginTrimLp();
+
+ /* Clear bit of the flash voltage control register after
+ * the LP mode is set
+ */
+ retVal = Cy_SysPm_WriteVoltageBitForFlash(CY_SYSPM_FLASH_VOLTAGE_BIT_LP);
+ }
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BuckIsOutputEnabled
+****************************************************************************//**
+*
+* This function gets the current output status of the Buck outputs.
+*
+* \param output
+* The Buck regulator output. See \ref cy_en_syspm_buck_out_t.
+*
+* \return
+* - True if the requested output is enabled.
+* - False if the requested output is disabled.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckIsOutputEnabled
+*
+*******************************************************************************/
+bool Cy_SysPm_BuckIsOutputEnabled(cy_en_syspm_buck_out_t output)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_BUCK_OUTPUT_VALID(output));
+
+ bool retVal = false;
+
+ if (output == CY_SYSPM_BUCK_VBUCK_1)
+ {
+ retVal = (_FLD2BOOL(SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN, SRSS_PWR_BUCK_CTL));
+ }
+
+ /* Return false if device does not have the second Buck output (SIMO) */
+ if (0U != cy_device->sysPmSimoPresent)
+ {
+ if(output == CY_SYSPM_BUCK_VRF)
+ {
+ retVal = ((0U != _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, SRSS_PWR_BUCK_CTL2)) ||
+ (0U != _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, SRSS_PWR_BUCK_CTL2)));
+ }
+ }
+
+ return(retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BuckEnableVoltage2
+****************************************************************************//**
+*
+* Enable the output 2 voltage (Vbuckrf) of the SIMO Buck regulator.
+* The output 2 voltage (Vbuckrf) of the Buck regulator is typically used to
+* supply the BLE radio.
+* This function does following actions, when the Buck regulator does not
+* supply the core:
+* * Enables the Buck regulator
+* * Enables the output 2, but do not enables the output 1.
+*
+* \note The function does not affect Buck output 1 that typically supplies core.
+*
+* \warning The function does not select the Buck output 2 voltage and
+* does not set/clear the HW-controlled bit for Buck output 2. Call
+* Cy_SysPm_BuckSetVoltage2() or Cy_SysPm_BuckSetVoltage2HwControl() to
+* configure the Buck output 2.
+*
+* The function works only on devices with the SIMO Buck regulator.
+* Refer to the device datasheet for information on whether the device contains
+* the SIMO Buck.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckEnableVoltage2
+*
+*******************************************************************************/
+void Cy_SysPm_BuckEnableVoltage2(void)
+{
+ /* Do nothing if device does not have the second Buck output (SIMO) */
+ if (0U != cy_device->sysPmSimoPresent)
+ {
+ if (!Cy_SysPm_BuckIsEnabled())
+ {
+ /* Enable the SIMO Buck regulator */
+ SRSS_PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_EN, 1U);
+ }
+
+ /* Enable the SIMO Buck output 2 */
+ SRSS_PWR_BUCK_CTL2 |= _VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, 1U);
+
+ /* Wait until the output is stable */
+ Cy_SysLib_DelayUs(BUCK_OUT2_INIT_DELAY_US);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BuckSetVoltage2
+****************************************************************************//**
+*
+* This function sets output voltage 2 (Vbuckrf) of the SIMO Buck regulator.
+*
+* \param voltage
+* The voltage of the Buck regulator output 2 (Vbuckrf).
+* See \ref cy_en_syspm_buck_voltage2_t.
+*
+* \param waitToSettle
+* - True to enable the 200 us delay after setting a higher voltage.
+* - False to disable the 200 us delay after setting a higher voltage.
+*
+* \warning You must enable the delay (waitToSettle = true)
+* while changing from a lower voltage to a higher voltage.
+*
+* \note The 200 us delay is required only when changing from a
+* lower voltage to a higher voltage. When changing from a higher voltage to a
+* lower one, the delay is not required.
+*
+* The function works only on devices with the SIMO Buck regulator.
+* Refer to the device datasheet for information on whether the device contains
+* SIMO Buck.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckSetVoltage2
+*
+*******************************************************************************/
+void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSettle)
+{
+ /* Do nothing if device does not have the second Buck output (SIMO) */
+ if (0U != cy_device->sysPmSimoPresent)
+ {
+ uint32_t curVoltage;
+
+ CY_ASSERT_L3(CY_SYSPM_IS_BUCK_VOLTAGE2_VALID(voltage));
+
+ /* Get the current voltage */
+ curVoltage = (uint32_t) Cy_SysPm_BuckGetVoltage2();
+
+ if ((uint32_t) voltage != curVoltage)
+ {
+ SRSS_PWR_BUCK_CTL2 =
+ _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL2), SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL, (uint32_t) voltage);
+
+ /* Delay stabilizing at the new voltage is required only
+ * when changing from a lower voltage to a higher voltage.
+ */
+ if(waitToSettle && ((uint32_t) voltage > curVoltage))
+ {
+ Cy_SysLib_DelayUs(BUCK_OUT2_STABILIZATION_DELAY_US);
+ }
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_LdoSetVoltage
+****************************************************************************//**
+*
+* Set output voltage on the core LDO regulator.
+*
+* When changing from a higher voltage to a lower voltage as when the device
+* enters system ULP mode, ensure that:
+* * The device maximum operating frequency for all the Clk_HF paths, peripheral,
+* and slow clock are under the \ref group_syspm_ulp_limitations.
+* * The total current consumption is under the \ref group_syspm_ulp_limitations.
+* * The appropriate wait states values are set for the flash using
+* The Cy_SysLib_SetWaitStates() function as explained below.
+*
+* <b>Setting wait states values for flash</b>
+*
+* The flash access time when the core voltage is 0.9 V (nominal) is
+* longer than at 1.1 V (nominal). Therefore, the number of the wait states must
+* be adjusted. Use the Cy_SysLib_SetWaitStates() function to set the appropriate
+* wait state values for flash.
+*
+* To change from a higher voltage to a lower voltage 0.9 V (nominal),
+* call the Cy_SysLib_SetWaitStates(true, hfClkFreqMz) function before changing
+* the voltage, where hfClkFreqMz is the frequency of HfClk0 in MHz.
+*
+* To change from a lower voltage to a higher voltage 1.1 V (nominal), calling
+* the Cy_SysLib_SetWaitStates(false, hfClkFreqMz) function to set the
+* wait states is optional, but can be done to improve performance.
+* The clock frequency may now be increased up to
+* \ref group_syspm_lp_limitations.
+*
+* \note 1. The output is set to 0.9 V (nominal) - the system is in ULP mode and
+* flash works for read-only operation.
+* \note 2. The output is set to 1.1 V (nominal) - the system is in LP mode
+* and flash works for read and write operations.
+* \note 3. The actual device Vccd voltage can be different from the nominal
+* voltage because the actual voltage value depends on conditions
+* including the load current.
+*
+* For more detail, refer to the \ref group_syspm_switching_into_ulp and
+* \ref group_syspm_switching_into_lp sections.
+* Refer to the \ref group_syslib driver for more detail about setting the wait
+* states.
+*
+* \param voltage
+* The desired output regulator voltage.
+* See \ref cy_en_syspm_ldo_voltage_t voltage
+*
+* \return
+* - CY_SYSPM_SUCCESS - The voltage is set.
+* - CY_SYSPM_INVALID_STATE - The voltage was not set. The voltage cannot be set
+* because the protection context value is higher than zero (PC > 0) or the
+* device revision does not support modifying registers via syscall.
+* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until
+* the function returns CY_SYSPM_SUCCESS. See \ref cy_en_syspm_status_t.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_LDO_VOLTAGE_VALID(voltage));
+
+ cy_en_syspm_status_t retVal = CY_SYSPM_INVALID_STATE;
+
+ /* Change the voltage only if protection context is set to zero (PC = 0),
+ * or the device revision supports modifying registers via syscall
+ */
+ if (IsVoltageChangePossible())
+ {
+ uint32_t interruptState;
+ uint32_t trimVoltage;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ if (CY_SYSPM_LDO_VOLTAGE_0_9V == voltage)
+ {
+ /* Remove additional wakeup delay from Deep Sleep
+ * for 1.1 V LDO. Cypress ID #290172
+ */
+ SRSS_PWR_TRIM_WAKE_CTL = 0UL;
+
+ trimVoltage = SFLASH_LDO_0P9V_TRIM;
+
+ /* Set bit of the flash voltage control register before the ULP is set */
+ retVal = Cy_SysPm_WriteVoltageBitForFlash(CY_SYSPM_FLASH_VOLTAGE_BIT_ULP);
+
+ if (CY_SYSPM_SUCCESS == retVal)
+ {
+ /* Update read-write margin value for the ULP mode */
+ SetReadMarginTrimUlp();
+ }
+ }
+ else
+ {
+ /* Configure additional wakeup delay from Deep Sleep
+ * for 1.1 V LDO. Cypress ID #290172
+ */
+ SRSS_PWR_TRIM_WAKE_CTL = SFLASH_PWR_TRIM_WAKE_CTL;
+
+ trimVoltage = SFLASH_LDO_1P1V_TRIM;
+
+ SRSS_PWR_TRIM_PWRSYS_CTL =
+ _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_0_95V);
+
+ /* A delay for the supply to stabilize at the new higher voltage */
+ Cy_SysLib_DelayUs(LDO_0_9V_TO_0_95V_DELAY_US);
+
+ /* Update write assist value for the LP mode */
+ SetWriteAssistTrimLp();
+
+ retVal = CY_SYSPM_SUCCESS;
+ }
+
+ if (CY_SYSPM_SUCCESS == retVal)
+ {
+ /* The system may continue operating while the voltage on Vccd
+ * discharges to the new voltage. The time it takes to reach the
+ * new voltage depends on the conditions, including the load current
+ * on Vccd and the external capacitor size.
+ */
+ SRSS_PWR_TRIM_PWRSYS_CTL =
+ _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, trimVoltage);
+
+ if (CY_SYSPM_LDO_VOLTAGE_0_9V == voltage)
+ {
+ /* Update write assist value for the ULP mode */
+ SetWriteAssistTrimUlp();
+ }
+ else
+ {
+ /* A delay for the supply to stabilize at the new intermediate voltage */
+ Cy_SysLib_DelayUs(LDO_0_95V_TO_1_1V_DELAY_US);
+
+ /* Update read-write margin value for the LP mode */
+ SetReadMarginTrimLp();
+
+ /* Clear bit of the flash voltage control register after
+ * the LP mode is set
+ */
+ retVal = Cy_SysPm_WriteVoltageBitForFlash(CY_SYSPM_FLASH_VOLTAGE_BIT_LP);
+ }
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_LdoSetMode
+****************************************************************************//**
+*
+* Configures the core LDO regulator operating mode to one of three modes.
+* Disabled - turns off the LDO regulator and should be selected only after the
+* Buck regulator is operating. Normal mode configures the LDO for operation at
+* the maximum output current limit. Minimal current mode optimizes the LDO at a
+* reduced output current limit. Specific device current limits can be found in
+* the device datasheet.
+*
+* \param mode
+* The desired LDO regulator operating mode.
+* See \ref cy_en_syspm_ldo_mode_t voltage
+*
+* \return
+* - CY_SYSPM_SUCCESS - Requested regulator current mode was set
+* - CY_SYSPM_CANCELED - The power circuits were not ready to enter into
+* minimum current mode. You should try to call the function again
+* - CY_SYSPM_TIMEOUT - Timeout occurred because of active reference was not
+* ready to enter into the normal regulator current mode
+* - CY_SYSPM_FAIL - incorrect mode value was passed
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_LDO_MODE_VALID(mode));
+
+ cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED;
+
+ switch (mode)
+ {
+ case CY_SYSPM_LDO_MODE_NORMAL:
+ {
+ retVal = Cy_SysPm_SystemSetNormalRegulatorCurrent();
+ }
+ break;
+
+ case CY_SYSPM_LDO_MODE_MIN:
+ {
+ retVal = Cy_SysPm_SystemSetMinRegulatorCurrent();
+ }
+ break;
+
+ case CY_SYSPM_LDO_MODE_DISABLED:
+ {
+ /* Disable the LDO, Deep Sleep, nWell, and Retention regulators */
+ SRSS_PWR_CTL |= (_VAL2FLD(SRSS_PWR_CTL_DPSLP_REG_DIS, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_RET_REG_DIS, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_NWELL_REG_DIS, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_LINREG_DIS, 1U));
+
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ default:
+ retVal = CY_SYSPM_FAIL;
+ break;
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_LdoGetMode
+****************************************************************************//**
+*
+* Returns the current core LDO regulator operating mode.
+*
+* \return
+* The LDO regulator operating mode.
+* See \ref cy_en_syspm_ldo_mode_t mode
+*
+*******************************************************************************/
+cy_en_syspm_ldo_mode_t Cy_SysPm_LdoGetMode(void)
+{
+ cy_en_syspm_ldo_mode_t retVal;
+
+ if (!Cy_SysPm_LdoIsEnabled())
+ {
+ retVal = CY_SYSPM_LDO_MODE_DISABLED;
+ }
+ else if (Cy_SysPm_SystemIsMinRegulatorCurrentSet())
+ {
+ retVal = CY_SYSPM_LDO_MODE_MIN;
+ }
+ else
+ {
+ retVal = CY_SYSPM_LDO_MODE_NORMAL;
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_RegisterCallback
+****************************************************************************//**
+*
+* Registers a new syspm callback.
+*
+* A callback is a function called after an event in the driver or
+* middleware module has occurred. The handler callback API will be executed if
+* the specific event occurs. SysPm callbacks are called when changing power
+* modes. See \ref cy_stc_syspm_callback_t.
+*
+* \note The registered callbacks are executed in two orders, based on callback
+* mode \ref cy_en_syspm_callback_mode_t. For modes CY_SYSPM_CHECK_READY and
+* CY_SYSPM_BEFORE_TRANSITION, the order is same order as callbacks were
+* registered.
+* For modes CY_SYSPM_AFTER_TRANSITION and CY_SYSPM_CHECK_FAIL, the order is
+* reverse as the order callbacks were registered.
+*
+* \param handler
+* The address of the syspm callback structure.
+* See \ref cy_stc_syspm_callback_t.
+*
+* \return
+* - True if a callback was registered.
+* - False if a callback was not registered.
+*
+* \note Do not modify the registered structure in run-time.
+* \warning After being registered, the SysPm callback structures must be
+* allocated during power mode transition.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Func_Declaration
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Params_Declaration
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Structure_Declaration
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Func_Implementation
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_RegisterCallback
+*
+*******************************************************************************/
+bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t* handler)
+{
+ bool retVal = false;
+
+ /* Verify the input parameters. */
+ if ((handler != NULL) && (handler->callbackParams != NULL) && (handler->callback != NULL))
+ {
+ uint32_t callbackRootIdx = (uint32_t) handler->type;
+
+ /* If the callback list is not empty. */
+ if (pmCallbackRoot[callbackRootIdx] != NULL)
+ {
+ cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx];
+ cy_stc_syspm_callback_t* insertPos = curCallback;
+
+ /* Find the callback after which the new callback is to be
+ * inserted. Ensure the given callback has not been registered.
+ */
+ while ((NULL != curCallback->nextItm) && (curCallback != handler))
+ {
+ curCallback = curCallback->nextItm;
+ /* Callbacks with the same order value are stored in the order
+ * they are registered.
+ */
+ if (curCallback->order <= handler->order)
+ {
+ insertPos = curCallback;
+ }
+ }
+ /* If the callback has not been registered. */
+ if (curCallback != handler)
+ {
+ /* If the callback is to be inserted at the beginning of the list. */
+ if ((insertPos->prevItm == NULL) && (handler->order < insertPos->order))
+ {
+ handler->nextItm = insertPos;
+ handler->prevItm = NULL;
+ handler->nextItm->prevItm = handler;
+ pmCallbackRoot[callbackRootIdx] = handler;
+ }
+ else
+ {
+ handler->nextItm = insertPos->nextItm;
+ handler->prevItm = insertPos;
+
+ /* If the callback is not inserted at the end of the list. */
+ if (handler->nextItm != NULL)
+ {
+ handler->nextItm->prevItm = handler;
+ }
+ insertPos->nextItm = handler;
+ }
+ retVal = true;
+ }
+ }
+ else
+ {
+ /* The callback list is empty. */
+ pmCallbackRoot[callbackRootIdx] = handler;
+ handler->nextItm = NULL;
+ handler->prevItm = NULL;
+ retVal = true;
+ }
+ }
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_UnregisterCallback
+****************************************************************************//**
+*
+* This function unregisters a callback.
+*
+* The registered callback can be unregistered and the function returns true.
+* Otherwise, false is returned.
+*
+* \param handler The item that should be unregistered.
+* See \ref cy_stc_syspm_callback_t.
+*
+* \return
+* - True if callback was unregistered.
+* - False if it was not unregistered or no callbacks are registered.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_UnregisterCallback
+*
+*******************************************************************************/
+bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler)
+{
+ bool retVal = false;
+
+ if (handler != NULL)
+ {
+ uint32_t callbackRootIdx = (uint32_t) handler->type;
+ cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx];
+
+ /* Search requested callback item in the linked list */
+ while (curCallback != NULL)
+ {
+ /* Requested callback is found */
+ if (curCallback == handler)
+ {
+ retVal = true;
+ break;
+ }
+
+ /* Go to next callback item in the linked list */
+ curCallback = curCallback->nextItm;
+ }
+
+ if (retVal)
+ {
+ /* Requested callback is first in the list */
+ if (pmCallbackRoot[callbackRootIdx] == handler)
+ {
+ /* Check whether this the only callback registered */
+ if (pmCallbackRoot[callbackRootIdx]->nextItm != NULL)
+ {
+ pmCallbackRoot[callbackRootIdx] = pmCallbackRoot[callbackRootIdx]->nextItm;
+ pmCallbackRoot[callbackRootIdx]->prevItm = NULL;
+ }
+ else
+ {
+ /* We had only one callback */
+ pmCallbackRoot[callbackRootIdx] = NULL;
+ }
+ }
+ else
+ {
+ /* Update links of related to unregistered callback items */
+ curCallback->prevItm->nextItm = curCallback->nextItm;
+
+ if (curCallback->nextItm != NULL)
+ {
+ curCallback->nextItm->prevItm = curCallback->prevItm;
+ }
+ }
+ }
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_ExecuteCallback
+****************************************************************************//**
+*
+* The function executes all registered callbacks with provided type and mode.
+* \note This low-level function is being used by \ref Cy_SysPm_CpuEnterSleep,
+* \ref Cy_SysPm_CpuEnterDeepSleep, \ref Cy_SysPm_SystemEnterHibernate,
+* \ref Cy_SysPm_SystemEnterUlp and \ref Cy_SysPm_SystemEnterLp API functions.
+* However, it might be also useful as an independent API function in some custom
+* applications.
+*
+* \note The registered callbacks will be executed in order based on
+* \ref cy_en_syspm_callback_type_t value. There are two possible callback
+* execution orders:
+* * From first registered to last registered. This order applies to
+* callbacks with mode CY_SYSPM_CHECK_READY and CY_SYSPM_BEFORE_TRANSITION.
+* * Backward flow execution:
+* - From last registered to the first registered. This order applies
+* to callbacks with mode CY_SYSPM_AFTER_TRANSITION.
+* - From last called to the first registered callback. This order applies
+* to callbacks with mode CY_SYSPM_CHECK_FAIL. Note that, the last called
+* callback function that generated the CY_SYSPM_CHECK_FAIL is skipped when
+* mode CY_SYSPM_CHECK_FAIL. This is because the callback that returns
+* CY_SYSPM_FAIL already knows that it failed and will not take any action
+* that requires correction.
+*
+* If no callbacks are registered, returns CY_SYSPM_SUCCESS.
+*
+* \param type
+* The callback type. See \ref cy_en_syspm_callback_type_t.
+*
+* \param mode
+* The callback mode. See \ref cy_en_syspm_callback_mode_t.
+*
+* \return
+* - CY_SYSPM_SUCCESS if callback successfully completed or nor callbacks
+* registered.
+* - CY_SYSPM_FAIL one of the executed callback(s) returned fail.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_ExecuteCallback
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, cy_en_syspm_callback_mode_t mode)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_TYPE_VALID(type));
+ CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_MODE_VALID(mode));
+
+ static cy_stc_syspm_callback_t* lastExecutedCallback = NULL;
+ cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
+ cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[(uint32_t) type];
+ cy_stc_syspm_callback_params_t curParams;
+
+ if ((mode == CY_SYSPM_BEFORE_TRANSITION) || (mode == CY_SYSPM_CHECK_READY))
+ {
+ /* Execute registered callbacks with order from first registered to the
+ * last registered. Stop executing if CY_SYSPM_FAIL was returned in
+ * CY_SYSPM_CHECK_READY mode
+ */
+ while ((curCallback != NULL) && ((retVal != CY_SYSPM_FAIL) || (mode != CY_SYSPM_CHECK_READY)))
+ {
+ /* The modes defined in the .skipMode element are not executed */
+ if (0UL == ((uint32_t) mode & curCallback->skipMode))
+ {
+ /* Update elements for local callback parameter values */
+ curParams.base = curCallback->callbackParams->base;
+ curParams.context = curCallback->callbackParams->context;
+
+ retVal = curCallback->callback(&curParams, mode);
+
+ /* Update callback pointer with value of executed callback.
+ * Such update is required to execute further callbacks in
+ * backward order after exit from LP mode or to undo
+ * configuration after callback returned fail: from last called
+ * to first registered.
+ */
+ lastExecutedCallback = curCallback;
+ }
+ curCallback = curCallback->nextItm;
+ }
+
+ if (mode == CY_SYSPM_CHECK_READY)
+ {
+ /* Update the pointer to the failed callback with the result of the callback execution.
+ * If the callback fails, the value of the pointer will be updated
+ * with the address of the callback which returned CY_SYSPM_FAIL, else,
+ * it will be updated with NULL.
+ */
+ if(retVal == CY_SYSPM_FAIL)
+ {
+ failedCallback[(uint32_t) type] = lastExecutedCallback;
+ }
+ else
+ {
+ failedCallback[(uint32_t) type] = NULL;
+ }
+ }
+ }
+ else
+ {
+ /* Execute registered callbacks with order from lastCallback or last
+ * executed to the first registered callback. Such a flow is required if
+ * a previous callback function returned CY_SYSPM_FAIL or a previous
+ * callback mode was CY_SYSPM_BEFORE_TRANSITION. Such an order is
+ * required to undo configurations in correct backward order.
+ */
+ if (mode != CY_SYSPM_CHECK_FAIL)
+ {
+ while (curCallback->nextItm != NULL)
+ {
+ curCallback = curCallback->nextItm;
+ }
+ }
+ else
+ {
+ /* Skip last executed callback that returns CY_SYSPM_FAIL, as this
+ * callback already knows that it failed.
+ */
+ curCallback = lastExecutedCallback;
+
+ if (curCallback != NULL)
+ {
+ curCallback = curCallback->prevItm;
+ }
+ }
+
+ /* Execute callback functions with required type and mode */
+ while (curCallback != NULL)
+ {
+ /* The modes defined in the .skipMode element are not executed */
+ if (0UL == ((uint32_t) mode & curCallback->skipMode))
+ {
+ /* Update elements for local callback parameter values */
+ curParams.base = curCallback->callbackParams->base;
+ curParams.context = curCallback->callbackParams->context;
+
+ retVal = curCallback->callback(&curParams, mode);
+ }
+ curCallback = curCallback->prevItm;
+ }
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_GetFailedCallback
+****************************************************************************//**
+*
+* Reads the result of the callback execution after the power mode functions
+* execution.
+*
+* This function reads the value of the pointer that stores the result of callback
+* execution. It takes power mode as the parameter and returns the address of the
+* callback configuration structure in the case of failure or NULL in the case of
+* success. This address of the failed callback allows finding the callback that
+* blocks entering power mode.
+*
+* \param type
+* Power mode for which a callback execution result is required.
+*
+* \return
+* - The address of the callback configuration structure if the callback handler
+* function failed.
+* - NULL if the callback skipped or executed successfully.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_GetFailedCallback
+*
+*******************************************************************************/
+cy_stc_syspm_callback_t* Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type)
+{
+ return failedCallback[(uint32_t) type];
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_IoUnfreeze
+****************************************************************************//**
+*
+* This function unfreezes the I/O cells that are automatically frozen when
+* Hibernate is entered with the call to \ref Cy_SysPm_SystemEnterHibernate().
+*
+* I/O cells remain frozen after a wakeup from Hibernate mode until the
+* firmware unfreezes them by calling this function.
+*
+* If the firmware must retain the data value on the pin, then the
+* value must be read and re-written to the pin's port data register before
+* calling this function. Furthermore, the drive mode must be re-programmed
+* before the pins are unfrozen. If this is not done, the pin will change to
+* the default state the moment the freeze is removed.
+*
+* Note that I/O cell configuration can be changed while frozen. The new
+* configuration becomes effective only after the pins are unfrozen.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_IoUnfreeze
+*
+*******************************************************************************/
+void Cy_SysPm_IoUnfreeze(void)
+{
+ uint32_t interruptState;
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ /* Preserve the last reset reason and wakeup polarity. Then, unfreeze I/O:
+ * write PWR_HIBERNATE.FREEZE=0, .UNLOCK=0x3A, .HIBERANTE=0
+ */
+ SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_RETAIN_STATUS_MASK) | HIBERNATE_UNLOCK_VAL;
+
+ /* Lock the Hibernate mode:
+ * write PWR_HIBERNATE.HIBERNATE=0, UNLOCK=0x00, HIBERANTE=0
+ */
+ SRSS_PWR_HIBERNATE &= HIBERNATE_RETAIN_STATUS_MASK;
+
+ /* Read register to make sure it is settled */
+ (void) SRSS_PWR_HIBERNATE;
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_WriteVoltageBitForFlash
+****************************************************************************//**
+*
+* Function that changes the voltage setting for flash.
+*
+* \note
+* Call this function before system enters ULP mode. Call this function after
+* the system enters LP mode.
+*
+* \param value
+* Value to be set in the flash voltage control register.
+* See \ref cy_en_syspm_flash_voltage_bit_t.
+*
+* \return
+* - CY_SYSPM_SUCCESS - The voltage is set.
+* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until
+* the function returns CY_SYSPM_SUCCESS. See \ref cy_en_syspm_status_t.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_WriteVoltageBitForFlash
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_WriteVoltageBitForFlash(cy_en_syspm_flash_voltage_bit_t value)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_BIT_FOR_FLASH_VALID(value));
+
+ cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED;
+ uint16_t curDeviceRevision = Cy_SysLib_GetDeviceRevision();
+ uint16_t curDevice = Cy_SysLib_GetDevice();
+
+ /* Check the current protection context value. We can have a direct register
+ * update if protection context is = 0 */
+ if ((Cy_Prot_GetActivePC(ACTIVE_BUS_MASTER) == 0U) && (curDevice == CY_SYSLIB_DEVICE_PSOC6ABLE2) &&
+ (curDeviceRevision <= SYSPM_DEVICE_PSOC6ABLE2_REV_0B))
+ {
+ FLASHC_FM_CTL_ANA_CTL0 =
+ _CLR_SET_FLD32U((FLASHC_FM_CTL_ANA_CTL0), FLASHC_FM_CTL_ANA_CTL0_VCC_SEL, value);
+
+ retVal = CY_SYSPM_SUCCESS;
+ }
+
+ /* Update the flash voltage bit using a syscall. This can be done on devices
+ * that support modifying registers via syscall.
+ */
+ if (((curDevice == CY_SYSLIB_DEVICE_PSOC6ABLE2) && (curDeviceRevision > SYSPM_DEVICE_PSOC6ABLE2_REV_0B)) ||
+ (curDevice != CY_SYSLIB_DEVICE_PSOC6ABLE2))
+ {
+ uint32_t syscallCode;
+ IPC_STRUCT_Type *ipcSyscallBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL);
+
+ /* Set required syscall code */
+ if (curDevice == CY_SYSLIB_DEVICE_PSOC6ABLE2)
+ {
+ syscallCode = (CY_SYSPM_FLASH_VOLTAGE_BIT_LP != value) ?
+ FLASH_VOLTAGE_BIT_ULP_PSOC6ABLE2_OPCODE : FLASH_VOLTAGE_BIT_LP_PSOC6ABLE2_OPCODE;
+ }
+ else
+ {
+ syscallCode = (CY_SYSPM_FLASH_VOLTAGE_BIT_LP != value) ?
+ FLASH_VOLTAGE_BIT_ULP_OPCODE : FLASH_VOLTAGE_BIT_LP_OPCODE;
+ }
+
+ /* Tries to acquire the IPC structure and pass the arguments to SROM API */
+ if (Cy_IPC_Drv_SendMsgWord(ipcSyscallBase, SYSPM_IPC_NOTIFY_STRUCT0, syscallCode) == CY_IPC_DRV_SUCCESS)
+ {
+ /* Checks whether the IPC structure is not locked */
+ while (Cy_IPC_Drv_IsLockAcquired(ipcSyscallBase))
+ {
+ /* Polls whether the IPC is released */
+ }
+
+ /* Check the return status of a syscall */
+ uint32_t syscallStatus = Cy_IPC_Drv_ReadDataValue(ipcSyscallBase);
+
+ if (SYSCALL_STATUS_SUCCESS == (syscallStatus & SYSCALL_STATUS_MASK))
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ }
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_SaveRegisters
+****************************************************************************//**
+*
+* Saves non-retained UDB registers before system entering system Deep Sleep.
+* Must be called if programmable logic or function are implemented in the UDB
+* array.
+*
+* \warning
+* Only one CPU on dual CPU devices should call this function. If both CPUs call
+* this function the UDB state restored may be inconsistent with the expected
+* state when restored.
+*
+* Cypress ID #280370.
+*
+* \param regs
+* The structure where the registers are saved.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SaveRestoreRegisters
+*
+*******************************************************************************/
+void Cy_SysPm_SaveRegisters(cy_stc_syspm_backup_regs_t *regs)
+{
+ CY_ASSERT_L1(NULL != regs);
+
+ /* Save the registers before Deep Sleep */
+ regs->CY_SYSPM_UDB_UDBIF_BANK_CTL_REG = UDB_UDBIF_BANK_CTL;
+
+ regs->CY_SYSPM_UDB_BCTL_MDCLK_EN_REG = UDB_BCTL_MDCLK_EN;
+ regs->CY_SYSPM_UDB_BCTL_MBCLK_EN_REG = UDB_BCTL_MBCLK_EN;
+ regs->CY_SYSPM_UDB_BCTL_BOTSEL_L_REG = UDB_BCTL_BOTSEL_L;
+ regs->CY_SYSPM_UDB_BCTL_BOTSEL_U_REG = UDB_BCTL_BOTSEL_U;
+ regs->CY_SYSPM_UDB_BCTL_QCLK_EN0_REG = UDB_BCTL_QCLK_EN_0;
+ regs->CY_SYSPM_UDB_BCTL_QCLK_EN1_REG = UDB_BCTL_QCLK_EN_1;
+ regs->CY_SYSPM_UDB_BCTL_QCLK_EN2_REG = UDB_BCTL_QCLK_EN_2;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_RestoreRegisters
+****************************************************************************//**
+*
+* Restores non-retained UDB registers before system entering system Deep Sleep.
+* Must be called if programmable logic or function are implemented in the UDB
+* array.
+*
+* \warning
+* Only one CPU on dual CPU devices should call this function. If both CPUs call
+* this function the UDB state restored may be inconsistent with the expected
+* state when restored.
+*
+* Cypress ID #280370.
+*
+* \param regs
+* The structure with data stored (using Cy_SysPm_SaveRegisters()) into the
+* required non-retained registers after Deep Sleep.
+*
+* \funcusage
+* \snippet syspm/snippet/main.c snippet_Cy_SysPm_SaveRestoreRegisters
+*
+*******************************************************************************/
+void Cy_SysPm_RestoreRegisters(cy_stc_syspm_backup_regs_t const *regs)
+{
+ CY_ASSERT_L1(NULL != regs);
+
+ /* Restore the registers after Deep Sleep */
+ UDB_BCTL_MDCLK_EN = regs->CY_SYSPM_UDB_BCTL_MDCLK_EN_REG;
+ UDB_BCTL_MBCLK_EN = regs->CY_SYSPM_UDB_BCTL_MBCLK_EN_REG;
+ UDB_BCTL_BOTSEL_L = regs->CY_SYSPM_UDB_BCTL_BOTSEL_L_REG;
+ UDB_BCTL_BOTSEL_U = regs->CY_SYSPM_UDB_BCTL_BOTSEL_U_REG;
+ UDB_BCTL_QCLK_EN_0 = regs->CY_SYSPM_UDB_BCTL_QCLK_EN0_REG;
+ UDB_BCTL_QCLK_EN_1 = regs->CY_SYSPM_UDB_BCTL_QCLK_EN1_REG;
+ UDB_BCTL_QCLK_EN_2 = regs->CY_SYSPM_UDB_BCTL_QCLK_EN2_REG;
+
+ UDB_UDBIF_BANK_CTL = regs->CY_SYSPM_UDB_UDBIF_BANK_CTL_REG;
+}
+
+
+/*******************************************************************************
+* Function Name: EnterDeepSleepRam
+****************************************************************************//**
+*
+* The internal function that prepares the system for Deep Sleep and
+* restores the system after a wakeup from Deep Sleep.
+*
+* \param waitFor
+* Selects wait for action. See \ref cy_en_syspm_waitfor_t.
+*
+* \return
+* - true - System Deep Sleep was occurred.
+* - false - System Deep Sleep was not occurred.
+*
+*******************************************************************************/
+CY_RAMFUNC_BEGIN
+#if !defined (__ICCARM__)
+ CY_NOINLINE
+#endif
+static bool EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor)
+{
+ /* Store the address of the IPC7 acquire register into the RAM */
+ volatile uint32_t *ipcAcquire = ((uint32_t *) (&REG_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT))));
+
+ /* Store the address of the Deep Sleep indicator into the RAM */
+ volatile uint32_t *delayDoneFlag = &FLASHC_BIST_DATA_0;
+
+ /* Indicator of System Deep Sleep mode */
+ bool retVal = false;
+
+ /* Acquire the IPC to prevent changing of the shared resources at the same time */
+ while (0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT))))
+ {
+ /* Wait until the IPC structure is released by another CPU */
+ }
+
+#ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE
+ if (Cy_SysLib_GetDeviceRevision() == CY_SYSLIB_DEVICE_REV_0A)
+ {
+ /* Set the flag that the current CPU entered Deep Sleep */
+ REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) |= CUR_CORE_DP_MASK;
+
+ /* Change the slow and fast clock dividers only under the condition that
+ * the other CPU is already in Deep Sleep. Cypress ID #284516
+ */
+ if (0U != (REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) & OTHER_CORE_DP_MASK))
+ {
+ /* Get the divider values of the slow and high clocks and store them into
+ * the IPC data register
+ */
+ REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) =
+ (REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) & ((uint32_t) ~(SYSPM_CLK_DIV_MASK))) |
+ (((uint32_t)(_FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS_CM0_CLOCK_CTL) << SYSPM_SLOW_CLK_DIV_Pos)) |
+ ((uint32_t)(_FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS_CM4_CLOCK_CTL) << SYSPM_FAST_CLK_DIV_Pos)));
+
+ /* Increase the clock divider for the slow and fast clocks to SYSPM_CLK_DIVIDER */
+ CPUSS_CM0_CLOCK_CTL =
+ _CLR_SET_FLD32U(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, SYSPM_CLK_DIVIDER);
+
+ CPUSS_CM4_CLOCK_CTL =
+ _CLR_SET_FLD32U(CPUSS_CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, SYSPM_CLK_DIVIDER);
+
+ /* Read the divider value to make sure it is set */
+ (void) CPUSS_CM0_CLOCK_CTL;
+ (void) CPUSS_CM4_CLOCK_CTL;
+ }
+ }
+ else
+#endif /* #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE */
+ {
+ /* Update pointer to the latest saved UDB structure */
+ REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (uint32_t) &bkpRegs;
+ }
+
+ /* Release the IPC */
+ REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0U;
+
+#if (CY_CPU_CORTEX_M4)
+
+ /* Store the address of the CM4 power status register */
+ volatile uint32_t *cpussCm4PwrCtlAddr = &CPUSS_CM4_PWR_CTL;
+
+ /* Repeat the WFI/WFE instruction if a wake up was not intended.
+ * Cypress ID #272909
+ */
+ do
+ {
+#endif /* (CY_CPU_CORTEX_M4) */
+
+ /* The CPU enters Deep Sleep mode upon execution of WFI/WFE */
+ SCB_SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
+ {
+ __WFI();
+ }
+ else
+ {
+ __WFE();
+
+ #if (CY_CPU_CORTEX_M4)
+ /* Call the WFE instruction twice to clear the Event register
+ * of the CM4 CPU. Cypress ID #279077
+ */
+ if(wasEventSent)
+ {
+ __WFE();
+ }
+ wasEventSent = true;
+ #endif /* (CY_CPU_CORTEX_M4) */
+ }
+
+#if (CY_CPU_CORTEX_M4)
+ } while (_FLD2VAL(CPUSS_CM4_PWR_CTL_PWR_MODE, (*cpussCm4PwrCtlAddr)) == CM4_PWR_STS_RETAINED);
+#endif /* (CY_CPU_CORTEX_M4) */
+
+ /* Acquire the IPC to prevent changing of the shared resources at the same time */
+ while (0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, (*ipcAcquire)))
+ {
+ /* Wait until the IPC structure is released by another CPU */
+ }
+
+#ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE
+ if (Cy_SysLib_GetDeviceRevision() == CY_SYSLIB_DEVICE_REV_0A)
+ {
+ /* Read and change the slow and fast clock dividers only under the condition
+ * that the other CPU is already in Deep Sleep. Cypress ID #284516
+ */
+ if (0U != (REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) & OTHER_CORE_DP_MASK))
+ {
+ /* Restore the clock dividers for the slow and fast clocks */
+ CPUSS_CM0_CLOCK_CTL =
+ _CLR_SET_FLD32U(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV,
+ (_FLD2VAL(SYSPM_SLOW_CLK_DIV, REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)))));
+
+ CPUSS_CM4_CLOCK_CTL =
+ _CLR_SET_FLD32U(CPUSS_CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV,
+ (_FLD2VAL(SYSPM_FAST_CLK_DIV, REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)))));
+
+ retVal = true;
+ }
+
+ /* Indicate that the current CPU is out of Deep Sleep */
+ REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) &= ((uint32_t) ~CUR_CORE_DP_MASK);
+ }
+ else
+#endif /* #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE */
+ {
+ /* Set 10 uS delay only under condition that the FLASHC_BIST_DATA[0] is
+ * cleared. Cypress ID #288510
+ */
+ if (*delayDoneFlag == NEED_DELAY)
+ {
+ uint32_t ddftSlowCtl;
+ uint32_t clkOutputSlow;
+ uint32_t ddftFastCtl;
+
+ /* Save timer configuration */
+ ddftSlowCtl = SRSS_TST_DDFT_SLOW_CTL_REG;
+ clkOutputSlow = SRSS_CLK_OUTPUT_SLOW;
+ ddftFastCtl = SRSS_TST_DDFT_FAST_CTL_REG;
+
+ /* Configure the counter to be sourced by IMO */
+ SRSS_TST_DDFT_SLOW_CTL_REG = SRSS_TST_DDFT_SLOW_CTL_MASK;
+ SRSS_CLK_OUTPUT_SLOW = CLK_OUTPUT_SLOW_MASK;
+ SRSS_TST_DDFT_FAST_CTL_REG = TST_DDFT_FAST_CTL_MASK;
+
+ /* Load the down-counter to count the 10 us */
+ SRSS_CLK_CAL_CNT1 = IMO_10US_DELAY;
+
+ while (0U == (SRSS_CLK_CAL_CNT1 & SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk))
+ {
+ /* Wait until the counter stops counting */
+ }
+
+ /* Indicate that delay was done */
+ *delayDoneFlag = DELAY_DONE;
+
+ /* Restore timer configuration */
+ SRSS_TST_DDFT_SLOW_CTL_REG = ddftSlowCtl;
+ SRSS_CLK_OUTPUT_SLOW = clkOutputSlow;
+ SRSS_TST_DDFT_FAST_CTL_REG = ddftFastCtl;
+
+ retVal = true;
+ }
+ }
+
+ /* Release the IPC */
+ REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0U;
+
+ return retVal;
+}
+CY_RAMFUNC_END
+
+
+/*******************************************************************************
+* Function Name: SetReadMarginTrimUlp
+****************************************************************************//**
+*
+* This is the internal function that updates the read-margin trim values for the
+* RAM and ROM. The trim update is done during transition of regulator voltage
+* from higher to a lower one.
+*
+*******************************************************************************/
+static void SetReadMarginTrimUlp(void)
+{
+ /* Update read-write margin value for the ULP mode. Cypress ID#297292 */
+ if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2)
+ {
+ CPUSS_TRIM_RAM_CTL = (CPUSS_TRIM_RAM_CTL & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RM_Msk)) |
+ (CPUSS_TRIM_RAM_ULP & CPUSS_TRIM_RAM_CTL_RM_Msk);
+
+ CPUSS_TRIM_ROM_CTL = (CPUSS_TRIM_ROM_CTL & ((uint32_t) ~CPUSS_TRIM_ROM_CTL_RM_Msk)) |
+ (CPUSS_TRIM_ROM_ULP & CPUSS_TRIM_ROM_CTL_RM_Msk);
+ }
+ else
+ {
+ CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) |
+ (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_RA_MASK);
+
+ CPUSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: SetReadMarginTrimLp
+****************************************************************************//**
+*
+* The internal function that updates the read-margin trim values for the
+* RAM and ROM. The trim update is done during transition of regulator voltage
+* from a lower to a higher one.
+*
+*******************************************************************************/
+static void SetReadMarginTrimLp(void)
+{
+ /* Update read-write margin value for the LP mode. Cypress ID#297292 */
+ if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2)
+ {
+ CPUSS_TRIM_RAM_CTL = (CPUSS_TRIM_RAM_CTL & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RM_Msk)) |
+ (CPUSS_TRIM_RAM_LP & CPUSS_TRIM_RAM_CTL_RM_Msk);
+
+ CPUSS_TRIM_ROM_CTL = (CPUSS_TRIM_ROM_CTL & ((uint32_t) ~CPUSS_TRIM_ROM_CTL_RM_Msk)) |
+ (CPUSS_TRIM_ROM_LP & CPUSS_TRIM_ROM_CTL_RM_Msk);
+ }
+ else
+ {
+ CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_LP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) |
+ (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_RA_MASK);
+
+ CPUSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_LP;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: SetWriteAssistTrimUlp
+****************************************************************************//**
+*
+* The internal function that updates the write assistant trim value for the
+* RAM. The trim update is done during transition of regulator voltage
+* from higher to a lower.
+*
+*******************************************************************************/
+static void SetWriteAssistTrimUlp(void)
+{
+ /* Update write assist value for the LP mode. Cypress ID#297292 */
+ if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2)
+ {
+ CPUSS_TRIM_RAM_CTL = (CPUSS_TRIM_RAM_CTL & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_WA_Msk)) |
+ (CPUSS_TRIM_RAM_ULP & CPUSS_TRIM_RAM_CTL_WA_Msk);
+ }
+ else
+ {
+ CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_ULP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) |
+ (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_RA_MASK);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: SetWriteAssistTrimLp
+****************************************************************************//**
+*
+* The internal function that updates the write assistant trim value for the
+* RAM. The trim update is done during transition of regulator voltage
+* from lower to a higher one.
+*
+*******************************************************************************/
+static void SetWriteAssistTrimLp(void)
+{
+ /* Update write assist value for the LP mode. Cypress ID#297292 */
+ if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2)
+ {
+ CPUSS_TRIM_RAM_CTL = (CPUSS_TRIM_RAM_CTL & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_WA_Msk)) |
+ (CPUSS_TRIM_RAM_LP & CPUSS_TRIM_RAM_CTL_WA_Msk);
+ }
+ else
+ {
+ CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) |
+ (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_RA_MASK);
+
+ CPUSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: IsVoltageChangePossible
+****************************************************************************//**
+*
+* The internal function that checks wherever it is possible to change the core
+* voltage. The voltage change is possible only when the protection context is
+* set to zero (PC = 0), or the device supports modifying registers via syscall.
+*
+*******************************************************************************/
+static bool IsVoltageChangePossible(void)
+{
+ bool retVal = true;
+
+ if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2)
+ {
+ uint32_t curProtContext = Cy_Prot_GetActivePC(ACTIVE_BUS_MASTER);
+
+ retVal = ((Cy_SysLib_GetDeviceRevision() > SYSPM_DEVICE_PSOC6ABLE2_REV_0B) || (curProtContext == 0U));
+ }
+
+ return retVal;
+}
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_systick.c b/platform/ext/target/psoc64/Native_Driver/source/cy_systick.c
new file mode 100644
index 0000000000..c1af99f878
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_systick.c
@@ -0,0 +1,256 @@
+/***************************************************************************//**
+* \file cy_systick.c
+* \version 1.10
+*
+* Provides the API definitions of the SisTick driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_systick.h"
+#include <stddef.h> /* for NULL */
+
+
+static Cy_SysTick_Callback Cy_SysTick_Callbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];
+static void Cy_SysTick_ServiceCallbacks(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_Init
+****************************************************************************//**
+*
+* Initializes the SysTick driver:
+* - Initializes the callback addresses with pointers to NULL
+* - Associates the SysTick system vector with the callback functions
+* - Sets the SysTick clock by calling \ref Cy_SysTick_SetClockSource()
+* - Sets the SysTick reload interval by calling \ref Cy_SysTick_SetReload()
+* - Clears the SysTick counter value by calling \ref Cy_SysTick_Clear()
+* - Enables the SysTick by calling \ref Cy_SysTick_Enable(). Note the \ref
+* Cy_SysTick_Enable() function also enables the SysTick interrupt by calling
+* \ref Cy_SysTick_EnableInterrupt().
+*
+* \param clockSource The SysTick clock source \ref cy_en_systick_clock_source_t
+* \param interval The SysTick reload value.
+*
+* \sideeffect Clears the SysTick count flag if it was set.
+*
+*******************************************************************************/
+void Cy_SysTick_Init(cy_en_systick_clock_source_t clockSource, uint32_t interval)
+{
+ uint32_t i;
+
+ for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+ {
+ Cy_SysTick_Callbacks[i] = NULL;
+ }
+
+ __ramVectors[CY_SYSTICK_IRQ_NUM] = &Cy_SysTick_ServiceCallbacks;
+ Cy_SysTick_SetClockSource(clockSource);
+
+ Cy_SysTick_SetReload(interval);
+ Cy_SysTick_Clear();
+ Cy_SysTick_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_Enable
+****************************************************************************//**
+*
+* Enables the SysTick timer and its interrupt.
+*
+* \sideeffect Clears the SysTick count flag if it was set
+*
+*******************************************************************************/
+void Cy_SysTick_Enable(void)
+{
+ Cy_SysTick_EnableInterrupt();
+ SYSTICK_CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_Disable
+****************************************************************************//**
+*
+* Disables the SysTick timer and its interrupt.
+*
+* \sideeffect Clears the SysTick count flag if it was set
+*
+*******************************************************************************/
+void Cy_SysTick_Disable(void)
+{
+ Cy_SysTick_DisableInterrupt();
+ SYSTICK_CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_SetClockSource
+****************************************************************************//**
+*
+* Sets the clock source for the SysTick counter.
+*
+* Clears the SysTick count flag if it was set. If the clock source is not ready
+* this function call will have no effect. After changing the clock source to the
+* low frequency clock, the counter and reload register values will remain
+* unchanged so the time to the interrupt will be significantly longer and vice
+* versa.
+*
+* Changing the SysTick clock source and/or its frequency will change
+* the interrupt interval and Cy_SysTick_SetReload() should be
+* called to compensate this change.
+*
+* \param clockSource \ref cy_en_systick_clock_source_t Clock source.
+*
+*******************************************************************************/
+void Cy_SysTick_SetClockSource(cy_en_systick_clock_source_t clockSource)
+{
+ if (clockSource == CY_SYSTICK_CLOCK_SOURCE_CLK_CPU)
+ {
+ SYSTICK_CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
+ }
+ else
+ {
+ CPUSS_SYSTICK_CTL = _VAL2FLD(CPUSS_SYSTICK_CTL_CLOCK_SOURCE, (uint32_t) clockSource);
+ SYSTICK_CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_GetClockSource
+****************************************************************************//**
+*
+* Gets the clock source for the SysTick counter.
+*
+* \returns \ref cy_en_systick_clock_source_t Clock source
+*
+*******************************************************************************/
+cy_en_systick_clock_source_t Cy_SysTick_GetClockSource(void)
+{
+ cy_en_systick_clock_source_t returnValue;
+
+ if ((SYSTICK_CTRL & SysTick_CTRL_CLKSOURCE_Msk) != 0u)
+ {
+ returnValue = CY_SYSTICK_CLOCK_SOURCE_CLK_CPU;
+ }
+ else
+ {
+ returnValue = (cy_en_systick_clock_source_t) ((uint32_t) _FLD2VAL(CPUSS_SYSTICK_CTL_CLOCK_SOURCE, CPUSS_SYSTICK_CTL));
+ }
+
+ return(returnValue);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_SetCallback
+****************************************************************************//**
+*
+* Sets the callback function to the specified callback number.
+*
+* \param number The number of the callback function addresses to be set.
+* The valid range is from 0 to \ref CY_SYS_SYST_NUM_OF_CALLBACKS - 1.
+*
+* \param function The pointer to the function that will be associated with the
+* SysTick ISR for the specified number.
+*
+* \return Returns the address of the previous callback function.
+* The NULL is returned if the specified address in not set or incorrect
+* parameter is specified.
+
+* \sideeffect
+* The registered callback functions will be executed in the interrupt.
+*
+*******************************************************************************/
+Cy_SysTick_Callback Cy_SysTick_SetCallback(uint32_t number, Cy_SysTick_Callback function)
+{
+ Cy_SysTick_Callback retVal;
+
+ if (number < CY_SYS_SYST_NUM_OF_CALLBACKS)
+ {
+ retVal = Cy_SysTick_Callbacks[number];
+ Cy_SysTick_Callbacks[number] = function;
+ }
+ else
+ {
+ retVal = NULL;
+ }
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_GetCallback
+****************************************************************************//**
+*
+* Gets the specified callback function address.
+*
+* \param number The number of the callback function address to get. The valid
+* range is from 0 to \ref CY_SYS_SYST_NUM_OF_CALLBACKS - 1.
+*
+* \return Returns the address of the specified callback function.
+* The NULL is returned if the specified address in not initialized or incorrect
+* parameter is specified.
+*
+*******************************************************************************/
+Cy_SysTick_Callback Cy_SysTick_GetCallback(uint32_t number)
+{
+ Cy_SysTick_Callback retVal;
+
+ if (number < CY_SYS_SYST_NUM_OF_CALLBACKS)
+ {
+ retVal = Cy_SysTick_Callbacks[number];
+ }
+ else
+ {
+ retVal = NULL;
+ }
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_ServiceCallbacks
+****************************************************************************//**
+*
+* The system Tick timer interrupt routine.
+*
+*******************************************************************************/
+static void Cy_SysTick_ServiceCallbacks(void)
+{
+ uint32_t i;
+
+ /* Verify that tick timer flag was set */
+ if (0u != Cy_SysTick_GetCountFlag())
+ {
+ for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+ {
+ if (Cy_SysTick_Callbacks[i] != NULL)
+ {
+ (void)(Cy_SysTick_Callbacks[i])();
+ }
+ }
+ }
+}
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_trigmux.c b/platform/ext/target/psoc64/Native_Driver/source/cy_trigmux.c
new file mode 100644
index 0000000000..6956f61ef1
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_trigmux.c
@@ -0,0 +1,381 @@
+/***************************************************************************//**
+* \file cy_trigmux.c
+* \version 1.20
+*
+* \brief Trigger mux API.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_trigmux.h"
+#include "cy_device.h"
+
+
+#define CY_TRIGMUX_IS_TRIGTYPE_VALID(trigType) (((trigType) == TRIGGER_TYPE_EDGE) || \
+ ((trigType) == TRIGGER_TYPE_LEVEL))
+
+#define CY_TRIGMUX_V1_IS_CYCLES_VALID(cycles) (CY_TRIGGER_INFINITE >= (cycles))
+#define CY_TRIGMUX_V2_IS_CYCLES_VALID(cycles) ((CY_TRIGGER_DEACTIVATE == (cycles)) || \
+ (CY_TRIGGER_TWO_CYCLES == (cycles)) || \
+ (CY_TRIGGER_INFINITE == (cycles)))
+#define CY_TRIGMUX_IS_CYCLES_VALID(cycles) ((CY_PERI_V1 && CY_TRIGMUX_V1_IS_CYCLES_VALID(cycles)) || \
+ CY_TRIGMUX_V2_IS_CYCLES_VALID(cycles))
+
+#define CY_TRIGMUX_INTRIG_MASK (PERI_TR_CMD_GROUP_SEL_Msk | PERI_TR_GR_TR_OUT_CTL_TR_SEL_Msk)
+#define CY_TRIGMUX_IS_INTRIG_VALID(inTrg) (0UL == ((inTrg) & (uint32_t)~CY_TRIGMUX_INTRIG_MASK))
+
+#define CY_TRIGMUX_OUTTRIG_MASK (PERI_TR_CMD_OUT_SEL_Msk | PERI_TR_CMD_GROUP_SEL_Msk | CY_PERI_TR_CTL_SEL_Msk)
+#define CY_TRIGMUX_IS_OUTTRIG_VALID(outTrg) ((0UL == ((outTrg) & (uint32_t)~CY_TRIGMUX_OUTTRIG_MASK)) && \
+ (0UL != ((outTrg) & PERI_TR_CMD_OUT_SEL_Msk)))
+
+#define CY_TRIGMUX_ONETRIG_MASK (PERI_V2_TR_CMD_OUT_SEL_Msk | PERI_V2_TR_CMD_GROUP_SEL_Msk | CY_PERI_TR_CTL_SEL_Msk)
+#define CY_TRIGMUX_IS_ONETRIG_VALID(oneTrg) ((0UL == ((oneTrg) & (uint32_t)~CY_TRIGMUX_ONETRIG_MASK)) && \
+ (0UL != ((oneTrg) & PERI_V2_TR_CMD_OUT_SEL_Msk)) && \
+ (0UL != ((oneTrg) & (PERI_V2_TR_CMD_GROUP_SEL_Msk & (uint32_t)~PERI_TR_CMD_GROUP_SEL_Msk))))
+
+#define CY_TRIGMUX_TRIGLINE_MASK (PERI_TR_CMD_OUT_SEL_Msk | CY_PERI_TR_CMD_GROUP_SEL_Msk | CY_PERI_TR_CTL_SEL_Msk)
+#define CY_TRIGMUX_IS_TRIGLINE_VALID(trgLn) (0U == ((trgLn) & (uint32_t)~CY_TRIGMUX_TRIGLINE_MASK))
+
+#define CY_TRIGMUX_TR_CTL(outTrig) (PERI_TR_GR_TR_CTL(_FLD2VAL(CY_PERI_TR_CMD_GROUP_SEL, outTrig), \
+ _FLD2VAL(CY_PERI_TR_CTL_SEL, outTrig)))
+
+
+/*******************************************************************************
+* Function Name: Cy_TrigMux_Connect
+****************************************************************************//**
+*
+* Connects an input trigger source and output trigger.
+*
+* \param inTrig
+* An input selection for the trigger mux.
+* - Bit 30 should be cleared.
+* - Bit 12 should be cleared.
+* - Bits 11:8 represent the trigger group selection.
+* - Bits 7:0 select the input trigger signal for the specified trigger multiplexer.
+*
+* \param outTrig
+* The output of the trigger mux. This refers to the consumer of the trigger mux.
+* - Bit 30 should be set.
+* - Bit 12 should be cleared.
+* - Bits 11:8 represent the trigger group selection.<br>
+* For PERI_ver1:
+* - Bits 6:0 select the output trigger number in the trigger group.<br>
+* For PERI_ver2:
+* - Bits 7:0 select the output trigger number in the trigger group.
+*
+* \param invert
+* - true: The output trigger is inverted.
+* - false: The output trigger is not inverted.
+*
+* \param trigType The trigger signal type.
+* - TRIGGER_TYPE_EDGE: The trigger is synchronized to the consumer blocks clock
+* and a two-cycle pulse is generated on this clock.
+* - TRIGGER_TYPE_LEVEL: The trigger is a simple level output.
+*
+* \return status:
+* - CY_TRIGMUX_SUCCESS: The connection is made successfully.
+* - CY_TRIGMUX_BAD_PARAM: Some parameter is invalid.
+*
+* \funcusage
+* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_Connect
+*
+*******************************************************************************/
+cy_en_trigmux_status_t Cy_TrigMux_Connect(uint32_t inTrig, uint32_t outTrig, bool invert, en_trig_type_t trigType)
+{
+ cy_en_trigmux_status_t retVal = CY_TRIGMUX_BAD_PARAM;
+ CY_ASSERT_L3(CY_TRIGMUX_IS_TRIGTYPE_VALID(trigType));
+ CY_ASSERT_L2(CY_TRIGMUX_IS_INTRIG_VALID(inTrig));
+ CY_ASSERT_L2(CY_TRIGMUX_IS_OUTTRIG_VALID(outTrig));
+
+ /* inTrig and outTrig should be in the same group */
+ if ((inTrig & PERI_TR_CMD_GROUP_SEL_Msk) == (outTrig & PERI_TR_CMD_GROUP_SEL_Msk))
+ {
+ uint32_t interruptState = Cy_SysLib_EnterCriticalSection();
+
+ CY_TRIGMUX_TR_CTL(outTrig) = (CY_TRIGMUX_TR_CTL(outTrig) &
+ (uint32_t)~(PERI_TR_GR_TR_OUT_CTL_TR_SEL_Msk |
+ PERI_TR_GR_TR_OUT_CTL_TR_INV_Msk |
+ PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Msk)) |
+ (_VAL2FLD(PERI_TR_GR_TR_OUT_CTL_TR_SEL, inTrig) |
+ _BOOL2FLD(PERI_TR_GR_TR_OUT_CTL_TR_INV, invert) |
+ _VAL2FLD(PERI_TR_GR_TR_OUT_CTL_TR_EDGE, trigType));
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ retVal = CY_TRIGMUX_SUCCESS;
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TrigMux_Select
+****************************************************************************//**
+*
+* Enables and configures the specified 1-to-1 trigger line. For PERI_ver2 only.
+*
+* \param outTrig
+* The 1to1 trigger line.
+* - Bit 30 should be set.
+* - Bit 12 should be set.
+* - Bits 11:8 represent the 1-to-1 trigger group selection.
+* - Bits 7:0 select the trigger line number in the trigger group.
+*
+* \param invert
+* - true: The trigger signal is inverted.
+* - false: The trigger signal is not inverted.
+*
+* \param trigType The trigger signal type.
+* - TRIGGER_TYPE_EDGE: The trigger is synchronized to the consumer blocks clock
+* and a two-cycle pulse is generated on this clock.
+* - TRIGGER_TYPE_LEVEL: The trigger is a simple level output.
+*
+* \return status:
+* - CY_TRIGMUX_SUCCESS: The selection is made successfully.
+* - CY_TRIGMUX_BAD_PARAM: Some parameter is invalid.
+*
+* \funcusage
+* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_Select
+*
+*******************************************************************************/
+cy_en_trigmux_status_t Cy_TrigMux_Select(uint32_t outTrig, bool invert, en_trig_type_t trigType)
+{
+ cy_en_trigmux_status_t retVal = CY_TRIGMUX_BAD_PARAM;
+
+ CY_ASSERT_L3(CY_TRIGMUX_IS_TRIGTYPE_VALID(trigType));
+ CY_ASSERT_L2(CY_TRIGMUX_IS_ONETRIG_VALID(outTrig));
+
+ if (!CY_PERI_V1)
+ {
+ uint32_t interruptState;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ CY_TRIGMUX_TR_CTL(outTrig) = (CY_TRIGMUX_TR_CTL(outTrig) &
+ (uint32_t)~(PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Msk |
+ PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Msk)) |
+ (PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Msk |
+ _BOOL2FLD(PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV, invert) |
+ _VAL2FLD(PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE, trigType));
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ retVal = CY_TRIGMUX_SUCCESS;
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TrigMux_Deselect
+****************************************************************************//**
+*
+* Disables the specified 1-to-1 trigger line. For PERI_ver2 only.
+*
+* \param outTrig
+* The 1to1 trigger line.
+* - Bit 30 should be set.
+* - Bit 12 should be set.
+* - Bits 11:8 represent the 1-to-1 trigger group selection.
+* - Bits 7:0 select the trigger line number in the trigger group.
+*
+* \return status:
+* - CY_TRIGMUX_SUCCESS: The deselection is made successfully.
+* - CY_TRIGMUX_BAD_PARAM: Some parameter is invalid.
+*
+* \funcusage
+* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_Deselect
+*
+*******************************************************************************/
+cy_en_trigmux_status_t Cy_TrigMux_Deselect(uint32_t outTrig)
+{
+ cy_en_trigmux_status_t retVal = CY_TRIGMUX_BAD_PARAM;
+
+ CY_ASSERT_L2(CY_TRIGMUX_IS_ONETRIG_VALID(outTrig));
+
+ if (!CY_PERI_V1)
+ {
+ uint32_t interruptState;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ CY_TRIGMUX_TR_CTL(outTrig) &= (uint32_t)~(PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Msk |
+ PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Msk |
+ PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Msk);
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ retVal = CY_TRIGMUX_SUCCESS;
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TrigMux_SetDebugFreeze
+****************************************************************************//**
+*
+* Enables/disables the Debug Freeze feature for the specified trigger
+* multiplexer or 1-to-1 trigger line. For PERI_ver2 only.
+*
+* \param outTrig
+* The output of the trigger mux or dedicated 1-to-1 trigger line.
+* - Bit 30 should be set.
+* - Bits 12:8 represent the trigger group selection.
+* - Bits 7:0 select the output trigger number in the trigger group.
+*
+* \param enable
+* - true: The Debug Freeze feature is enabled.
+* - false: The Debug Freeze feature is disabled.
+*
+* \return status:
+* - CY_TRIGMUX_SUCCESS: The operation is made successfully.
+* - CY_TRIGMUX_BAD_PARAM: The outTrig parameter is invalid.
+*
+* \funcusage
+* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_SetDebugFreeze
+*
+*******************************************************************************/
+cy_en_trigmux_status_t Cy_TrigMux_SetDebugFreeze(uint32_t outTrig, bool enable)
+{
+ cy_en_trigmux_status_t retVal = CY_TRIGMUX_BAD_PARAM;
+
+ if (!CY_PERI_V1)
+ {
+ uint32_t interruptState;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ if (enable)
+ {
+ CY_TRIGMUX_TR_CTL(outTrig) |= PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk;
+ }
+ else
+ {
+ CY_TRIGMUX_TR_CTL(outTrig) &= (uint32_t)~PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk;
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ retVal = CY_TRIGMUX_SUCCESS;
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TrigMux_SwTrigger
+****************************************************************************//**
+*
+* This function generates a software trigger on an input trigger line.
+* All output triggers connected to this input trigger will be triggered.
+* The function also verifies that there is no activated trigger before
+* generating another activation.
+*
+* \param trigLine
+* The input of the trigger mux.
+* - Bit 30 represents if the signal is an input/output. When this bit is set,
+* the trigger activation is for an output trigger from the trigger multiplexer.
+* When this bit is reset, the trigger activation is for an input trigger to
+* the trigger multiplexer.
+* - Bits 12:8 represent the trigger group selection.<br>
+* In case of output trigger line (bit 30 is set):
+* For PERI_ver1:
+* - Bits 6:0 select the output trigger number in the trigger group.<br>
+* For PERI_ver2:
+* - Bits 7:0 select the output trigger number in the trigger group.
+* In case of input trigger line (bit 30 is unset):
+* - Bits 7:0 select the input trigger signal for the trigger multiplexer.
+*
+* \param cycles
+* The number of "Clk_Peri" cycles during which the trigger remains activated.<br>
+* For PERI_ver1: The valid range of cycles is 1 ... 254.<br>
+* For PERI_ver2: The only valid value of cycles is 2 (\ref CY_TRIGGER_TWO_CYCLES).<br>
+* Also there are special values (supported with both PERI_ver1 and PERI_ver2):
+* - CY_TRIGGER_INFINITE - trigger remains activated until the user deactivates it by
+* calling this function with CY_TRIGGER_DEACTIVATE parameter.
+* - CY_TRIGGER_DEACTIVATE - this is used to deactivate the trigger activated by
+* calling this function with CY_TRIGGER_INFINITE parameter.
+*
+* \return status:
+* - CY_TRIGMUX_SUCCESS: The trigger is successfully activated/deactivated.
+* - CY_TRIGMUX_INVALID_STATE: The trigger is already activated/not active.
+* - CY_TRIGMUX_BAD_PARAM: Some parameter is invalid.
+*
+* \funcusage
+* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_SwTrigger
+*
+*******************************************************************************/
+cy_en_trigmux_status_t Cy_TrigMux_SwTrigger(uint32_t trigLine, uint32_t cycles)
+{
+ cy_en_trigmux_status_t retVal = CY_TRIGMUX_INVALID_STATE;
+
+ CY_ASSERT_L2(CY_TRIGMUX_IS_TRIGLINE_VALID(trigLine));
+ CY_ASSERT_L2(CY_TRIGMUX_IS_CYCLES_VALID(cycles));
+
+ if (CY_TRIGGER_DEACTIVATE != cycles)
+ {
+ /* Activate the trigger if it is not in the active state. */
+ if (PERI_TR_CMD_ACTIVATE_Msk != (PERI_TR_CMD & PERI_TR_CMD_ACTIVATE_Msk))
+ {
+
+ uint32_t trCmd = (trigLine & (PERI_TR_CMD_TR_SEL_Msk |
+ PERI_TR_CMD_OUT_SEL_Msk |
+ CY_PERI_TR_CMD_GROUP_SEL_Msk)) |
+ PERI_TR_CMD_ACTIVATE_Msk;
+
+ retVal = CY_TRIGMUX_SUCCESS;
+
+ if (CY_PERI_V1) /* mxperi_v1 */
+ {
+ PERI_TR_CMD = trCmd | _VAL2FLD(PERI_TR_CMD_COUNT, cycles);
+ }
+ else if (CY_TRIGGER_TWO_CYCLES == cycles) /* mxperi_v2 or later, 2 cycles pulse */
+ {
+ PERI_TR_CMD = trCmd | PERI_V2_TR_CMD_TR_EDGE_Msk;
+ }
+ else if (CY_TRIGGER_INFINITE == cycles) /* mxperi_v2 or later, infinite activating */
+ {
+ PERI_TR_CMD = trCmd;
+ }
+ else /* mxperi_v2 or later, invalid cycles value */
+ {
+ retVal = CY_TRIGMUX_BAD_PARAM;
+ }
+ }
+ }
+ else
+ {
+ /* Forcibly deactivate the trigger if it is in the active state. */
+ if (PERI_TR_CMD_ACTIVATE_Msk == (PERI_TR_CMD & PERI_TR_CMD_ACTIVATE_Msk))
+ {
+ PERI_TR_CMD = 0UL;
+
+ retVal = CY_TRIGMUX_SUCCESS;
+ }
+ }
+
+ return retVal;
+}
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/Native_Driver/source/cy_wdt.c b/platform/ext/target/psoc64/Native_Driver/source/cy_wdt.c
new file mode 100644
index 0000000000..eca611f184
--- /dev/null
+++ b/platform/ext/target/psoc64/Native_Driver/source/cy_wdt.c
@@ -0,0 +1,215 @@
+/***************************************************************************//**
+* \file cy_wdt.c
+* \version 1.10.1
+*
+* This file provides the source code to the API for the WDT driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_wdt.h"
+#include "cy_syslib.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+static bool Cy_WDT_Locked(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_Init
+****************************************************************************//**
+*
+* Initializes the Watchdog timer to its default state.
+*
+* The given default setting of the WDT:
+* The WDT is unlocked and disabled.
+* The WDT match value is 4096.
+* None of ignore bits are set: the whole WDT counter bits are checked against
+* the match value.
+*
+* \sideeffect
+* This function clears the WDT interrupt.
+*
+*******************************************************************************/
+void Cy_WDT_Init(void)
+{
+ /* Unlock the WDT by two writes */
+ SRSS_WDT_CTL = ((SRSS_WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_SRSS_WDT_LOCK_BIT0);
+ SRSS_WDT_CTL |= CY_SRSS_WDT_LOCK_BIT1;
+
+ Cy_WDT_Disable();
+ Cy_WDT_SetMatch(CY_SRSS_WDT_DEFAULT_MATCH_VALUE);
+ Cy_WDT_SetIgnoreBits(CY_SRSS_WDT_DEFAULT_IGNORE_BITS);
+ Cy_WDT_ClearInterrupt();
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_Lock
+****************************************************************************//**
+*
+* Locks out configuration changes to the Watchdog Timer register.
+*
+* After this function is called, the WDT configuration cannot be changed until
+* Cy_WDT_Unlock() is called.
+*
+* \warning
+* The WDT lock state is not retained during system Deep Sleep. After the wakeup
+* from system Deep Sleep the WDT is locked.
+*
+*******************************************************************************/
+void Cy_WDT_Lock(void)
+{
+ SRSS_WDT_CTL |= _VAL2FLD(SRSS_WDT_CTL_WDT_LOCK, CY_SRSS_WDT_LOCK_BITS);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_Locked
+****************************************************************************//**
+*
+* Internal function that returns the WDT lock state.
+*
+* \return
+* True - if WDT is locked.
+* False - if WDT is unlocked.
+*
+*******************************************************************************/
+static bool Cy_WDT_Locked(void)
+{
+ /* Prohibits writing to the WDT registers and other CLK_LF */
+ return (0u != _FLD2VAL(SRSS_WDT_CTL_WDT_LOCK, SRSS_WDT_CTL));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_Unlock
+****************************************************************************//**
+*
+* Unlocks the Watchdog Timer configuration register.
+*
+* \warning
+* The WDT lock state is not retained during system Deep Sleep. After the wakeup
+* from system Deep Sleep the WDT is locked.
+*
+*******************************************************************************/
+void Cy_WDT_Unlock(void)
+{
+ /* The WDT lock is to be removed by two writes */
+ SRSS_WDT_CTL = ((SRSS_WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_SRSS_WDT_LOCK_BIT0);
+
+ SRSS_WDT_CTL |= CY_SRSS_WDT_LOCK_BIT1;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_SetMatch
+****************************************************************************//**
+*
+* Configures the WDT counter match comparison value. The Watchdog timer
+* should be unlocked before changing the match value. Call the Cy_WDT_Unlock()
+* function to unlock the WDT.
+*
+* \param match
+* The valid valid range is [0-65535]. The value to be used to match
+* against the counter.
+*
+*******************************************************************************/
+void Cy_WDT_SetMatch(uint32_t match)
+{
+ CY_ASSERT_L2(CY_WDT_IS_MATCH_VAL_VALID(match));
+
+ if (false == Cy_WDT_Locked())
+ {
+ SRSS_WDT_MATCH = _CLR_SET_FLD32U((SRSS_WDT_MATCH), SRSS_WDT_MATCH_MATCH, match);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_SetIgnoreBits
+****************************************************************************//**
+*
+* Configures the number of the most significant bits of the Watchdog timer that
+* are not checked against the match. Unlock the Watchdog timer before
+* ignoring the bits setting. Call the Cy_WDT_Unlock() API to unlock the WDT.
+*
+* \param bitsNum
+* The number of the most significant bits. The valid range is [0-15].
+* The bitsNum over 12 are considered as 12.
+*
+* \details The value of bitsNum controls the time-to-reset of the Watchdog timer
+* This happens after 3 successive matches.
+*
+* \warning This function changes the WDT interrupt period, therefore
+* the device can go into an infinite WDT reset loop. This may happen
+* if a WDT reset occurs faster that a device start-up.
+*
+*******************************************************************************/
+void Cy_WDT_SetIgnoreBits(uint32_t bitsNum)
+{
+ CY_ASSERT_L2(CY_WDT_IS_IGNORE_BITS_VALID(bitsNum));
+
+ if (false == Cy_WDT_Locked())
+ {
+ SRSS_WDT_MATCH = _CLR_SET_FLD32U((SRSS_WDT_MATCH), SRSS_WDT_MATCH_IGNORE_BITS, bitsNum);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_ClearInterrupt
+****************************************************************************//**
+*
+* Clears the WDT match flag which is set every time the WDT counter reaches a
+* WDT match value. Two unserviced interrupts lead to a system reset
+* (i.e. at the third match).
+*
+*******************************************************************************/
+void Cy_WDT_ClearInterrupt(void)
+{
+ SRSS_SRSS_INTR = _VAL2FLD(SRSS_SRSS_INTR_WDT_MATCH, 1U);
+
+ /* Read the interrupt register to ensure that the initial clearing write has
+ * been flushed out to the hardware.
+ */
+ (void) SRSS_SRSS_INTR;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_ClearWatchdog
+****************************************************************************//**
+*
+* Clears ("feeds") the watchdog, to prevent a XRES device reset.
+* This function simply call Cy_WDT_ClearInterrupt() function.
+*
+*******************************************************************************/
+void Cy_WDT_ClearWatchdog(void)
+{
+ Cy_WDT_ClearInterrupt();
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc64/attest_hal.c b/platform/ext/target/psoc64/attest_hal.c
new file mode 100644
index 0000000000..d4d2407680
--- /dev/null
+++ b/platform/ext/target/psoc64/attest_hal.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "platform/include/tfm_attest_hal.h"
+#include <stdint.h>
+
+/* Example verification service URL for initial attestation token */
+static const char verification_service_url[] = "www.trustedfirmware.org";
+
+/* Example profile definition document for initial attestation token */
+static const char attestation_profile_definition[] = "PSA_IOT_PROFILE_1";
+
+enum tfm_security_lifecycle_t tfm_attest_hal_get_security_lifecycle(void)
+{
+ return TFM_SLC_SECURED;
+}
+
+const char *
+tfm_attest_hal_get_verification_service(uint32_t *size)
+{
+ *size = sizeof(verification_service_url) - 1;
+
+ return verification_service_url;
+}
+
+const char *
+tfm_attest_hal_get_profile_definition(uint32_t *size)
+{
+ *size = sizeof(attestation_profile_definition) - 1;
+
+ return attestation_profile_definition;
+}
diff --git a/platform/ext/target/psoc64/cypress_psoc_6_spec.rst b/platform/ext/target/psoc64/cypress_psoc_6_spec.rst
new file mode 100644
index 0000000000..8b498b2e2c
--- /dev/null
+++ b/platform/ext/target/psoc64/cypress_psoc_6_spec.rst
@@ -0,0 +1,332 @@
+########################
+Cypress PSoC 6 Specifics
+########################
+
+******************************************
+Building Multi-Core TF-M on Cypress PSoC 6
+******************************************
+
+Please make sure you have all required software installed as explained in the
+:doc:`software requirements </docs/user_guides/tfm_sw_requirement>`.
+
+Please install CySecureTools with (requires Python3.7):
+
+.. code-block:: bash
+
+ pip install cysecuretools
+
+For more details please refer to
+`CySecureTools <https://pypi.org/project/cysecuretools>`_ page.
+
+Please also make sure that all the source code are fetched by following
+:doc:`general building instruction </docs/user_guides/tfm_build_instruction>`.
+
+
+Configuring the build
+=====================
+
+The build configuration for TF-M is provided to the build system using command
+line arguments:
+
+.. list-table::
+ :widths: 20 80
+
+ * - -DPROJ_CONFIG=<file>
+ - Specifies the way the application is built.
+
+ | <file> is the absolute path to configurations file
+ named as ``Config<APP_NAME>.cmake``.
+ | e.g. On Linux:
+ ``-DPROJ_CONFIG=`readlink -f ../configs/ConfigRegressionIPC.cmake```
+ | Supported configurations files
+
+ - IPC model without regression test suites in Isolation Level 1
+ ``ConfigCoreIPC.cmake``
+ - IPC model with regression test suites in Isolation Level 1
+ ``ConfigRegressionIPC.cmake``
+ - IPC model with PSA API test suite in Isolation Level 1
+ ``ConfigPsaApiTestIPC.cmake``
+ - IPC model without regression test suites in Isolation Level 2
+ ``ConfigCoreIPCTfmLevel2.cmake``
+ - IPC model with regression test suites in Isolation Level 2
+ ``ConfigRegressionIPCTfmLevel2.cmake``
+ - IPC model with PSA API test suite in Isolation Level 2
+ ``ConfigPsaApiTestIPCTfmLevel2.cmake``
+
+ * - -DTARGET_PLATFORM=psoc64
+ - Specifies target platform name ``psoc64``
+
+ * - -DCOMPILER=<compiler name>
+ - Specifies the compiler toolchain
+ The possible values are:
+
+ - ``ARMCLANG``
+ - ``GNUARM``
+
+ * - -DCMAKE_BUILD_TYPE=<build type>
+ - Configures debugging support.
+ The possible values are:
+
+ - ``Debug``
+ - ``Release``
+
+
+Build Instructions
+==================
+
+The following instructions build multi-core TF-M without regression test suites
+in Isolation Level 1 on Linux.
+Both the compiler and the debugging type can be changed to other configurations
+listed above.
+
+.. code-block:: bash
+
+ cd <TF-M base folder>
+ cd <trusted-firmware-m folder>
+
+ mkdir <build folder>
+ pushd <build folder>
+ cmake -G"Unix Makefiles" -DPROJ_CONFIG=`readlink -f ../configs/ConfigCoreIPC.cmake` -DTARGET_PLATFORM=psoc64 -DCOMPILER=ARMCLANG -DCMAKE_BUILD_TYPE=Debug ../
+ popd
+ cmake --build <build folder> -- -j VERBOSE=1
+
+The following instructions build multi-core TF-M with regression test suites
+in Isolation Level 1 on Linux.
+Both the compiler and the debugging type can be changed to other configurations
+listed above.
+
+.. code-block:: bash
+
+ cd <TF-M base folder>
+ cd <trusted-firmware-m folder>
+
+ mkdir <build folder>
+ pushd <build folder>
+ cmake -G"Unix Makefiles" -DPROJ_CONFIG=`readlink -f ../configs/ConfigRegressionIPC.cmake` -DTARGET_PLATFORM=psoc64 -DCOMPILER=ARMCLANG -DCMAKE_BUILD_TYPE=Debug ../
+ popd
+ cmake --build <build folder> -- -j VERBOSE=1
+
+The following instructions build multi-core TF-M with PSA API test suite for
+the attestation service in Isolation Level 1 on Linux.
+Both the compiler and the debugging type can be changed to other configurations
+listed above.
+
+.. list-table::
+ :widths: 20 80
+
+ * - -DPSA_API_TEST_BUILD_PATH=<path> (optional)
+ - Specifies the path to the PSA API build directory
+
+ - ``${TFM_ROOT_DIR}/../psa-arch-tests/api-tests/BUILD`` (default)
+
+ * - -D<PSA_API_TEST_xxx>=1 (choose exactly one)
+ - Specifies the service to support
+ The possible values are:
+
+ - ``PSA_API_TEST_ATTESTATION``
+ - ``PSA_API_TEST_CRYPTO``
+ - ``PSA_API_TEST_SECURE_STORAGE``
+ - ``PSA_API_TEST_INTERNAL_TRUSTED_STORAGE``
+
+.. code-block:: bash
+
+ cd <TF-M base folder>
+ cd <trusted-firmware-m folder>
+
+ mkdir <build folder>
+ pushd <build folder>
+ cmake ../ \
+ -G"Unix Makefiles" \
+ -DPROJ_CONFIG=`readlink -f ../configs/ConfigPsaApiTestIPC.cmake` \
+ -DPSA_API_TEST_BUILD_PATH=../psa-arch-tests/api-tests/BUILD_ATT.GNUARM
+ -DPSA_API_TEST_ATTESTATION=1 \
+ -DTARGET_PLATFORM=psoc64 \
+ -DCOMPILER=ARMCLANG \
+ -DCMAKE_BUILD_TYPE=Debug
+ popd
+ cmake --build <build folder> -- -j VERBOSE=1
+
+The following instructions build multi-core TF-M without regression test suites
+in Isolation Level 2 on Linux.
+Both the compiler and the debugging type can be changed to other configurations
+listed above.
+
+.. code-block:: bash
+
+ cd <TF-M base folder>
+ cd <trusted-firmware-m folder>
+
+ mkdir <build folder>
+ pushd <build folder>
+ cmake -G"Unix Makefiles" -DPROJ_CONFIG=`readlink -f ../configs/ConfigCoreIPCTfmLevel2.cmake` -DTARGET_PLATFORM=psoc64 -DCOMPILER=ARMCLANG -DCMAKE_BUILD_TYPE=Debug ../
+ popd
+ cmake --build <build folder> -- -j VERBOSE=1
+
+The following instructions build multi-core TF-M with regression test suites
+in Isolation Level 2 on Linux.
+Both the compiler and the debugging type can be changed to other configurations
+listed above.
+
+.. code-block:: bash
+
+ cd <TF-M base folder>
+ cd <trusted-firmware-m folder>
+
+ mkdir <build folder>
+ pushd <build folder>
+ cmake -G"Unix Makefiles" -DPROJ_CONFIG=`readlink -f ../configs/ConfigRegressionIPCTfmLevel2.cmake` -DTARGET_PLATFORM=psoc64 -DCOMPILER=ARMCLANG -DCMAKE_BUILD_TYPE=Debug ../
+ popd
+ cmake --build <build folder> -- -j VERBOSE=1
+
+The following instructions build multi-core TF-M with PSA API test suite for
+the protected storage service in Isolation Level 2 on Linux.
+Both the compiler and the debugging type can be changed to other configurations
+listed above.
+
+.. list-table::
+ :widths: 20 80
+
+ * - -DPSA_API_TEST_BUILD_PATH=<path> (optional)
+ - Specifies the path to the PSA API build directory
+
+ - ``${TFM_ROOT_DIR}/../psa-arch-tests/api-tests/BUILD`` (default)
+
+ * - -D<PSA_API_TEST_xxx>=1 (choose exactly one)
+ - Specifies the service to support
+ The possible values are:
+
+ - ``PSA_API_TEST_ATTESTATION``
+ - ``PSA_API_TEST_CRYPTO``
+ - ``PSA_API_TEST_SECURE_STORAGE``
+ - ``PSA_API_TEST_INTERNAL_TRUSTED_STORAGE``
+
+.. code-block:: bash
+
+ cd <TF-M base folder>
+ cd <trusted-firmware-m folder>
+
+ mkdir <build folder>
+ pushd <build folder>
+ cmake ../ \
+ -G"Unix Makefiles" \
+ -DPROJ_CONFIG=`readlink -f ../configs/ConfigPsaApiTestIPCTfmLevel2.cmake` \
+ -DPSA_API_TEST_BUILD_PATH=../psa-arch-tests/api-tests/BUILD_PS.GNUARM
+ -DPSA_API_TEST_SECURE_STORAGE=1 \
+ -DTARGET_PLATFORM=psoc64 \
+ -DCOMPILER=ARMCLANG \
+ -DCMAKE_BUILD_TYPE=Debug
+ popd
+ cmake --build <build folder> -- -j VERBOSE=1
+
+**********************
+Signing the images
+**********************
+
+First, convert tfm_s.axf and tfm_ns.axf images to hex format. This also places
+resulting files one folder level up.
+
+GNUARM build:
+
+.. code-block:: bash
+
+ arm-none-eabi-objcopy -O ihex <build folder>/secure_fw/tfm_s.axf <build folder>/tfm_s.hex
+ arm-none-eabi-objcopy -O ihex <build folder>/app/tfm_ns.axf <build folder>/tfm_ns.hex
+
+ARMCLANG build:
+
+.. code-block:: bash
+
+ fromelf --i32 --output=<build folder>/tfm_s.hex <build folder>/secure_fw/tfm_s.axf
+ fromelf --i32 --output=<build folder>/tfm_ns.hex <build folder>/app/tfm_ns.axf
+
+Copy secure keys used in the board provisioning process to
+platform/ext/target/psoc64/security/keys:
+
+MCUBOOT_CM0P_KEY.json - private OEM key for signing CM0P image
+USERAPP_CM4_KEY.json - private OEM key for signing CM4 image
+
+Note: provisioned board in SECURE claimed state is required, otherwise refer to
+Cypress documentation for details on the provisioning process.
+
+Sign the images (sign.py overwrites unsigned files with signed ones):
+
+.. code-block:: bash
+
+ ./platform/ext/target/psoc64/security/sign.py \
+ -s <build folder>/tfm_s.hex \
+ -n <build folder>/tfm_ns.hex \
+ -p platform/ext/target/psoc6/security/policy_dual_stage_CM0p_CM4.json
+
+**********************
+Programming the Device
+**********************
+
+After building and signing, the TFM images must be programmed into flash
+memory on the PSoC 6 device.
+
+There are two methods to program psoc6 device.
+
+DAPLink mode
+============
+
+Using KitProg3 mode button, switch it to DAPLink mode.
+Mode LED should start blinking rapidly and depending on the host computer
+settings DAPLINK will be mounted as a media storage device.
+Otherwise, mount it manually.
+
+Copy tfm hex files one by one to the DAPLINK device:
+
+.. code-block:: bash
+
+ cp <build folder>/tfm_ns.hex <mount point>/DAPLINK/; sync
+ cp <build folder>/tfm_s.hex <mount point>/DAPLINK/; sync
+
+OpenOCD v.2.2
+=============
+
+Using KitProg3 mode button, switch to KitProg3 CMSIS-DAP BULK mode.
+Status LED should be ON and not blinking.
+To program the signed tfm_s image to the device with openocd (assuming
+OPENOCD_PATH is pointing at the openocd installation directory) run the
+following commands:
+
+.. code-block:: bash
+
+ ${OPENOCD_PATH}/bin/openocd \
+ -s ${OPENOCD_PATH}/scripts \
+ -f interface/kitprog3.cfg \
+ -c "set ENABLE_ACQUIRE 0" \
+ -f target/psoc6_secure.cfg \
+ -c "init; reset init; flash write_image erase <build folder>/tfm_s.hex" \
+ -c "resume; reset; exit"
+
+ ${OPENOCD_PATH}/bin/openocd \
+ -s ${OPENOCD_PATH}/scripts \
+ -f interface/kitprog3.cfg \
+ -c "set ENABLE_ACQUIRE 0" \
+ -f target/psoc6_secure.cfg \
+ -c "init; reset init; flash write_image erase <build folder>/tfm_ns.hex" \
+ -c "resume; reset; exit"
+
+Optionally, erase SST partition:
+
+.. code-block:: bash
+
+ ${OPENOCD_PATH}/bin/openocd \
+ -s ${OPENOCD_PATH}/scripts \
+ -f interface/kitprog3.cfg \
+ -f target/psoc6_secure.cfg \
+ -c "init; reset init" \
+ -c "flash erase_address 0x100c0000 0x10000" \
+ -c "shutdown"
+
+Note that the ``0x100C0000`` in the command above must match the SST start
+address of the secure primary image specified in the file:
+
+ platform/ext/target/psoc64/partition/flash_layout.h
+
+so be sure to change it if you change that file.
+
+*Copyright (c) 2017-2019, Arm Limited. All rights reserved.*
+
+*Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.*
diff --git a/platform/ext/target/psoc64/driver_dap.c b/platform/ext/target/psoc64/driver_dap.c
new file mode 100644
index 0000000000..4a85356ff1
--- /dev/null
+++ b/platform/ext/target/psoc64/driver_dap.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+
+#include "driver_dap.h"
+
+#include "cycfg.h"
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_ipc_drv.h"
+#include "cy_prot.h"
+#include "cy_sysint.h"
+#include "driver_dap.h"
+#include "pc_config.h"
+
+
+int cy_access_port_control(cy_ap_name_t ap, cy_ap_control_t en)
+{
+ int rc = -1;
+ volatile uint32_t syscallCmd = 0;
+ uint32_t timeout = 0;
+
+ syscallCmd |= DAPCONTROL_SYSCALL_OPCODE;
+ syscallCmd |= (uint8_t)en << 16;
+ syscallCmd |= (uint8_t)ap << 8;
+ syscallCmd |= 1;
+
+ IPC->STRUCT[CY_IPC_CHAN_SYSCALL].DATA = syscallCmd;
+
+ while(((IPC->STRUCT[CY_IPC_CHAN_SYSCALL].ACQUIRE &
+ IPC_STRUCT_ACQUIRE_SUCCESS_Msk) == 0) &&
+ (timeout < SYSCALL_TIMEOUT))
+ {
+ ++timeout;
+ }
+
+ if(timeout < SYSCALL_TIMEOUT)
+ {
+ timeout = 0;
+
+ IPC->STRUCT[CY_IPC_CHAN_SYSCALL].NOTIFY = 1;
+
+ while(((IPC->STRUCT[CY_IPC_CHAN_SYSCALL].LOCK_STATUS &
+ IPC_STRUCT_ACQUIRE_SUCCESS_Msk) != 0) &&
+ (timeout < SYSCALL_TIMEOUT))
+ {
+ ++timeout;
+ }
+
+ if(timeout < SYSCALL_TIMEOUT)
+ {
+ syscallCmd = IPC->STRUCT[CY_IPC_CHAN_SYSCALL].DATA;
+ if(CY_FB_SYSCALL_SUCCESS != syscallCmd)
+ {
+ rc = syscallCmd;
+ }
+ else
+ {
+ rc = 0;
+ }
+ }
+ }
+ return rc;
+} \ No newline at end of file
diff --git a/platform/ext/target/psoc64/driver_dap.h b/platform/ext/target/psoc64/driver_dap.h
new file mode 100644
index 0000000000..72bec39e96
--- /dev/null
+++ b/platform/ext/target/psoc64/driver_dap.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DRIVER_DAP_H__
+#define __DRIVER_DAP_H__
+
+/* DAPControl SysCall opcode */
+#define DAPCONTROL_SYSCALL_OPCODE (0x3AUL << 24UL)
+
+/* PSA crypto SysCall return codes */
+#define CY_FB_SYSCALL_SUCCESS (0xA0000000UL)
+
+/* SysCall timeout value */
+#define SYSCALL_TIMEOUT (15000UL)
+
+/* DAPControl SysCall parameter: access port state */
+typedef enum
+{
+ CY_AP_DIS = 0,
+ CY_AP_EN = 1
+}cy_ap_control_t;
+
+/* DAPControl SysCall parameter: access port name */
+typedef enum
+{
+ CY_CM0_AP = 0,
+ CY_CM4_AP = 1,
+ CY_SYS_AP = 2
+}cy_ap_name_t;
+
+/* API functions */
+int cy_access_port_control(cy_ap_name_t ap, cy_ap_control_t en);
+
+#endif /* __DRIVER_DAP_H__ */
diff --git a/platform/ext/target/psoc64/driver_ppu.c b/platform/ext/target/psoc64/driver_ppu.c
new file mode 100644
index 0000000000..3d2e7e1882
--- /dev/null
+++ b/platform/ext/target/psoc64/driver_ppu.c
@@ -0,0 +1,611 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdio.h>
+
+#include "driver_ppu.h"
+#include "pc_config.h"
+#include "ppu_config.h"
+#include "RTE_Device.h"
+
+#include "cy_device_headers.h"
+#include "cy_prot.h"
+
+struct ms_ppu_config {
+ uint16_t pcMask;
+ cy_en_prot_perm_t user;
+ cy_en_prot_perm_t priv;
+ bool secure;
+};
+
+struct ppu_resources {
+ enum ppu_type ppu_type;
+ union ppu {
+ PERI_MS_PPU_PR_Type *ms_ppu_pr;
+ PERI_MS_PPU_FX_Type *ms_ppu_fx;
+ PERI_PPU_PR_Type *ppu_pr;
+ PERI_PPU_GR_Type *ppu_gr;
+ PERI_GR_PPU_SL_Type *gr_ppu_sl;
+ PERI_GR_PPU_RG_Type *gr_ppu_rg;
+ } ppu;
+ union master_config {
+ struct ms_ppu_config ms_ppu;
+ cy_stc_ppu_prog_cfg_t ppu_pr;
+ cy_stc_ppu_gr_cfg_t ppu_gr;
+ cy_stc_ppu_sl_cfg_t gr_ppu_sl;
+ cy_stc_ppu_rg_cfg_t gr_ppu_rg;
+ } master_cfg;
+ union slave_config {
+ struct ms_ppu_config ms_ppu;
+ /* TODO also need slave addr and size for MS_PPU_PR */
+ cy_stc_ppu_prog_cfg_t ppu_pr;
+ cy_stc_ppu_gr_cfg_t ppu_gr;
+ cy_stc_ppu_sl_cfg_t gr_ppu_sl;
+ cy_stc_ppu_rg_cfg_t gr_ppu_rg;
+ } slave_cfg;
+};
+
+/* Affect all 8 subregions */
+#define ALL_ENABLED 0
+
+/* Shared Driver wrapper functions */
+cy_en_prot_status_t PPU_Configure(const PPU_Resources *ppu_dev)
+{
+ cy_en_prot_status_t ret;
+
+ switch(ppu_dev->ppu_type) {
+/* This block is only needed if there are MS_PPU_PR PPUs on the board */
+#if defined(PERI_MS_PPU_PR0)
+ case MS_PPU_PR:
+ ret = Cy_Prot_ConfigPpuProgMasterAtt(ppu_dev->ppu.ms_ppu_pr,
+ ppu_dev->master_cfg.ms_ppu.pcMask,
+ ppu_dev->master_cfg.ms_ppu.user,
+ ppu_dev->master_cfg.ms_ppu.priv,
+ ppu_dev->master_cfg.ms_ppu.secure);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ /* TODO Sort out address and region size
+ ret = Cy_Prot_ConfigPpuProgSlaveAddr(ppu_dev->ppu.ms_ppu_pr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ */
+ ret = Cy_Prot_ConfigPpuProgSlaveAtt(ppu_dev->ppu.ms_ppu_pr,
+ ppu_dev->slave_cfg.ms_ppu.pcMask,
+ ppu_dev->slave_cfg.ms_ppu.user,
+ ppu_dev->slave_cfg.ms_ppu.priv,
+ ppu_dev->slave_cfg.ms_ppu.secure);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuProgSlaveRegion(ppu_dev->ppu.ms_ppu_pr);
+ break;
+#endif
+
+/* This block is only needed if there are MS_PPU_FX PPUs on the board */
+#if defined(PERI_MS_PPU_FX_PERI_MAIN)
+ case MS_PPU_FX:
+ ret = Cy_Prot_ConfigPpuFixedMasterAtt(ppu_dev->ppu.ms_ppu_fx,
+ ppu_dev->master_cfg.ms_ppu.pcMask,
+ ppu_dev->master_cfg.ms_ppu.user,
+ ppu_dev->master_cfg.ms_ppu.priv,
+ ppu_dev->master_cfg.ms_ppu.secure);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_ConfigPpuFixedSlaveAtt(ppu_dev->ppu.ms_ppu_fx,
+ ppu_dev->slave_cfg.ms_ppu.pcMask,
+ ppu_dev->slave_cfg.ms_ppu.user,
+ ppu_dev->slave_cfg.ms_ppu.priv,
+ ppu_dev->slave_cfg.ms_ppu.secure);
+ break;
+#endif
+
+ case PPU_PR:
+ ret = Cy_Prot_ConfigPpuProgMasterStruct(ppu_dev->ppu.ppu_pr,
+ &ppu_dev->master_cfg.ppu_pr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_ConfigPpuProgSlaveStruct(ppu_dev->ppu.ppu_pr,
+ &ppu_dev->slave_cfg.ppu_pr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuProgMasterStruct(ppu_dev->ppu.ppu_pr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuProgSlaveStruct(ppu_dev->ppu.ppu_pr);
+ break;
+
+ case PPU_GR:
+ ret = Cy_Prot_ConfigPpuFixedGrMasterStruct(ppu_dev->ppu.ppu_gr,
+ &ppu_dev->master_cfg.ppu_gr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_ConfigPpuFixedGrSlaveStruct(ppu_dev->ppu.ppu_gr,
+ &ppu_dev->slave_cfg.ppu_gr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuFixedGrMasterStruct(ppu_dev->ppu.ppu_gr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuFixedGrSlaveStruct(ppu_dev->ppu.ppu_gr);
+ break;
+
+ case GR_PPU_SL:
+ ret = Cy_Prot_ConfigPpuFixedSlMasterStruct(ppu_dev->ppu.gr_ppu_sl,
+ &ppu_dev->master_cfg.gr_ppu_sl);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_ConfigPpuFixedSlSlaveStruct(ppu_dev->ppu.gr_ppu_sl,
+ &ppu_dev->slave_cfg.gr_ppu_sl);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuFixedSlMasterStruct(ppu_dev->ppu.gr_ppu_sl);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuFixedSlSlaveStruct(ppu_dev->ppu.gr_ppu_sl);
+ break;
+
+ case GR_PPU_RG:
+ ret = Cy_Prot_ConfigPpuFixedRgMasterStruct(ppu_dev->ppu.gr_ppu_rg,
+ &ppu_dev->master_cfg.gr_ppu_rg);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_ConfigPpuFixedRgSlaveStruct(ppu_dev->ppu.gr_ppu_rg,
+ &ppu_dev->slave_cfg.gr_ppu_rg);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuFixedRgMasterStruct(ppu_dev->ppu.gr_ppu_rg);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuFixedRgSlaveStruct(ppu_dev->ppu.gr_ppu_rg);
+ break;
+
+ default:
+ printf("Unexpected peripheral type %d\n", ppu_dev->ppu_type);
+ return CY_PROT_BAD_PARAM;
+ }
+
+ return ret;
+}
+
+#define DEFINE_MS_PPU_PR(N) const PPU_Resources N##_PPU_Resources = { \
+ .ppu_type = MS_PPU_PR, \
+ .ppu = {.ms_ppu_pr = PERI_PPU_##N}, \
+ .master_cfg.ms_ppu = PPU_##N##_MASTER_CONFIG, \
+ .slave_cfg.ms_ppu = PPU_##N##_SLAVE_CONFIG, \
+};
+
+#define DEFINE_MS_PPU_FX(N) const PPU_Resources N##_PPU_Resources = { \
+ .ppu_type = MS_PPU_FX, \
+ .ppu = {.ms_ppu_fx = PERI_PPU_##N}, \
+ .master_cfg.ms_ppu = PPU_##N##_MASTER_CONFIG, \
+ .slave_cfg.ms_ppu = PPU_##N##_SLAVE_CONFIG, \
+};
+
+#define DEFINE_PPU_PR(N) const PPU_Resources N##_PPU_Resources = { \
+ .ppu_type = PPU_PR, \
+ .ppu = {.ppu_pr = PERI_PPU_##N}, \
+ .master_cfg.ppu_pr = PPU_##N##_MASTER_CONFIG, \
+ .slave_cfg.ppu_pr = PPU_##N##_SLAVE_CONFIG, \
+};
+
+#define DEFINE_PPU_GR(N) const PPU_Resources N##_PPU_Resources = { \
+ .ppu_type = PPU_GR, \
+ .ppu = {.ppu_gr = PERI_PPU_##N}, \
+ .master_cfg.ppu_gr = PPU_##N##_MASTER_CONFIG, \
+ .slave_cfg.ppu_gr = PPU_##N##_SLAVE_CONFIG, \
+};
+
+#define DEFINE_GR_PPU_SL(N) const PPU_Resources N##_PPU_Resources = { \
+ .ppu_type = GR_PPU_SL, \
+ .ppu = {.gr_ppu_sl = PERI_GR_PPU_##N}, \
+ .master_cfg.gr_ppu_sl = PPU_##N##_MASTER_CONFIG, \
+ .slave_cfg.gr_ppu_sl = PPU_##N##_SLAVE_CONFIG, \
+};
+
+#define DEFINE_GR_PPU_RG(N) const PPU_Resources N##_PPU_Resources = { \
+ .ppu_type = GR_PPU_RG, \
+ .ppu = {.gr_ppu_rg = PERI_GR_PPU_##N}, \
+ .master_cfg.gr_ppu_rg = PPU_##N##_MASTER_CONFIG, \
+ .slave_cfg.gr_ppu_rg = PPU_##N##_SLAVE_CONFIG, \
+};
+
+#if (RTE_PPU_PR0)
+DEFINE_PPU_PR(PR0)
+#endif
+
+#if (RTE_PPU_PR1)
+DEFINE_PPU_PR(PR1)
+#endif
+
+#if (RTE_PPU_PR2)
+DEFINE_PPU_PR(PR2)
+#endif
+
+#if (RTE_PPU_PR3)
+DEFINE_PPU_PR(PR3)
+#endif
+
+#if (RTE_PPU_PR4)
+DEFINE_PPU_PR(PR4)
+#endif
+
+#if (RTE_PPU_PR5)
+DEFINE_PPU_PR(PR5)
+#endif
+
+#if (RTE_PPU_PR6)
+DEFINE_PPU_PR(PR6)
+#endif
+
+#if (RTE_PPU_PR7)
+DEFINE_PPU_PR(PR7)
+#endif
+
+#if (RTE_PPU_PR8)
+DEFINE_PPU_PR(PR8)
+#endif
+
+#if (RTE_PPU_GR0)
+DEFINE_PPU_GR(GR0)
+#endif
+
+#if (RTE_PPU_GR1)
+DEFINE_PPU_GR(GR1)
+#endif
+
+#if (RTE_PPU_GR2)
+DEFINE_PPU_GR(GR2)
+#endif
+
+#if (RTE_PPU_GR3)
+DEFINE_PPU_GR(GR3)
+#endif
+
+#if (RTE_PPU_GR4)
+DEFINE_PPU_GR(GR4)
+#endif
+
+#if (RTE_PPU_GR6)
+DEFINE_PPU_GR(GR6)
+#endif
+
+#if (RTE_PPU_GR9)
+DEFINE_PPU_GR(GR9)
+#endif
+
+#if (RTE_PPU_GR10)
+DEFINE_PPU_GR(GR10)
+#endif
+
+#if (RTE_PPU_GR_MMIO0)
+DEFINE_PPU_GR(GR_MMIO0)
+#endif
+
+#if (RTE_PPU_GR_MMIO1)
+DEFINE_PPU_GR(GR_MMIO1)
+#endif
+
+#if (RTE_PPU_GR_MMIO2)
+DEFINE_PPU_GR(GR_MMIO2)
+#endif
+
+#if (RTE_PPU_GR_MMIO3)
+DEFINE_PPU_GR(GR_MMIO3)
+#endif
+
+#if (RTE_PPU_GR_MMIO4)
+DEFINE_PPU_GR(GR_MMIO4)
+#endif
+
+#if (RTE_PPU_GR_MMIO6)
+DEFINE_PPU_GR(GR_MMIO6)
+#endif
+
+#if (RTE_PPU_GR_MMIO9)
+DEFINE_PPU_GR(GR_MMIO9)
+#endif
+
+#if (RTE_PPU_GR_MMIO10)
+DEFINE_PPU_GR(GR_MMIO10)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR1)
+DEFINE_GR_PPU_SL(SL_PERI_GR1)
+#endif
+
+#if (RTE_GR_PPU_SL_CRYPTO)
+DEFINE_GR_PPU_SL(SL_CRYPTO)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR2)
+DEFINE_GR_PPU_SL(SL_PERI_GR2)
+#endif
+
+#if (RTE_GR_PPU_SL_CPUSS)
+DEFINE_GR_PPU_SL(SL_CPUSS)
+#endif
+
+#if (RTE_GR_PPU_SL_FAULT)
+DEFINE_GR_PPU_SL(SL_FAULT)
+#endif
+
+#if (RTE_GR_PPU_SL_IPC)
+DEFINE_GR_PPU_SL(SL_IPC)
+#endif
+
+#if (RTE_GR_PPU_SL_PROT)
+DEFINE_GR_PPU_SL(SL_PROT)
+#endif
+
+#if (RTE_GR_PPU_SL_FLASHC)
+DEFINE_GR_PPU_SL(SL_FLASHC)
+#endif
+
+#if (RTE_GR_PPU_SL_SRSS)
+DEFINE_GR_PPU_SL(SL_SRSS)
+#endif
+
+#if (RTE_GR_PPU_SL_BACKUP)
+DEFINE_GR_PPU_SL(SL_BACKUP)
+#endif
+
+#if (RTE_GR_PPU_SL_DW0)
+DEFINE_GR_PPU_SL(SL_DW0)
+#endif
+
+#if (RTE_GR_PPU_SL_DW1)
+DEFINE_GR_PPU_SL(SL_DW1)
+#endif
+
+#if (RTE_GR_PPU_SL_EFUSE)
+DEFINE_GR_PPU_SL(SL_EFUSE)
+#endif
+
+#if (RTE_GR_PPU_SL_PROFILE)
+DEFINE_GR_PPU_SL(SL_PROFILE)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT0)
+DEFINE_GR_PPU_RG(RG_IPC_STRUCT0)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT1)
+DEFINE_GR_PPU_RG(RG_IPC_STRUCT1)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT2)
+DEFINE_GR_PPU_RG(RG_IPC_STRUCT2)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT3)
+DEFINE_GR_PPU_RG(RG_IPC_STRUCT3)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT4)
+DEFINE_GR_PPU_RG(RG_IPC_STRUCT4)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT5)
+DEFINE_GR_PPU_RG(RG_IPC_STRUCT5)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT6)
+DEFINE_GR_PPU_RG(RG_IPC_STRUCT6)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT7)
+DEFINE_GR_PPU_RG(RG_IPC_STRUCT7)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT0)
+DEFINE_GR_PPU_RG(RG_IPC_INTR_STRUCT0)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT1)
+DEFINE_GR_PPU_RG(RG_IPC_INTR_STRUCT1)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT2)
+DEFINE_GR_PPU_RG(RG_IPC_INTR_STRUCT2)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT3)
+DEFINE_GR_PPU_RG(RG_IPC_INTR_STRUCT3)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT4)
+DEFINE_GR_PPU_RG(RG_IPC_INTR_STRUCT4)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT5)
+DEFINE_GR_PPU_RG(RG_IPC_INTR_STRUCT5)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT6)
+DEFINE_GR_PPU_RG(RG_IPC_INTR_STRUCT6)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT7)
+DEFINE_GR_PPU_RG(RG_IPC_INTR_STRUCT7)
+#endif
+
+#if (RTE_GR_PPU_RG_DW0_DW_CH_STRUCT0)
+DEFINE_GR_PPU_RG(RG_DW0_DW_CH_STRUCT0)
+#endif
+
+#if (RTE_GR_PPU_RG_DW0_DW_CH_STRUCT1)
+DEFINE_GR_PPU_RG(RG_DW0_DW_CH_STRUCT1)
+#endif
+
+#if (RTE_GR_PPU_RG_DW0_DW_CH_STRUCT2)
+DEFINE_GR_PPU_RG(RG_DW0_DW_CH_STRUCT2)
+#endif
+
+#if (RTE_GR_PPU_RG_DW0_DW_CH_STRUCT3)
+DEFINE_GR_PPU_RG(RG_DW0_DW_CH_STRUCT3)
+#endif
+
+#if (RTE_GR_PPU_RG_DW1_DW_CH_STRUCT0)
+DEFINE_GR_PPU_RG(RG_DW1_DW_CH_STRUCT0)
+#endif
+
+#if (RTE_GR_PPU_RG_DW1_DW_CH_STRUCT1)
+DEFINE_GR_PPU_RG(RG_DW1_DW_CH_STRUCT1)
+#endif
+
+#if (RTE_GR_PPU_RG_DW1_DW_CH_STRUCT2)
+DEFINE_GR_PPU_RG(RG_DW1_DW_CH_STRUCT2)
+#endif
+
+#if (RTE_GR_PPU_RG_DW1_DW_CH_STRUCT3)
+DEFINE_GR_PPU_RG(RG_DW1_DW_CH_STRUCT3)
+#endif
+
+#if (RTE_GR_PPU_RG_SMPU)
+DEFINE_GR_PPU_RG(RG_SMPU)
+#endif
+
+#if (RTE_GR_PPU_RG_MPU_CM0P)
+DEFINE_GR_PPU_RG(RG_MPU_CM0P)
+#endif
+
+#if (RTE_GR_PPU_RG_MPU_CRYPTO)
+DEFINE_GR_PPU_RG(RG_MPU_CRYPTO)
+#endif
+
+#if (RTE_GR_PPU_RG_MPU_CM4)
+DEFINE_GR_PPU_RG(RG_MPU_CM4)
+#endif
+
+#if (RTE_GR_PPU_RG_MPU_TC)
+DEFINE_GR_PPU_RG(RG_MPU_TC)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR3)
+DEFINE_GR_PPU_SL(SL_PERI_GR3)
+#endif
+
+#if (RTE_GR_PPU_SL_HSIOM)
+DEFINE_GR_PPU_SL(SL_HSIOM)
+#endif
+
+#if (RTE_GR_PPU_SL_GPIO)
+DEFINE_GR_PPU_SL(SL_GPIO)
+#endif
+
+#if (RTE_GR_PPU_SL_SMARTIO)
+DEFINE_GR_PPU_SL(SL_SMARTIO)
+#endif
+
+#if (RTE_GR_PPU_SL_UDB)
+DEFINE_GR_PPU_SL(SL_UDB)
+#endif
+
+#if (RTE_GR_PPU_SL_LPCOMP)
+DEFINE_GR_PPU_SL(SL_LPCOMP)
+#endif
+
+#if (RTE_GR_PPU_SL_CSD)
+DEFINE_GR_PPU_SL(SL_CSD)
+#endif
+
+#if (RTE_GR_PPU_SL_TCPWM0)
+DEFINE_GR_PPU_SL(SL_TCPWM0)
+#endif
+
+#if (RTE_GR_PPU_SL_TCPWM1)
+DEFINE_GR_PPU_SL(SL_TCPWM1)
+#endif
+
+#if (RTE_GR_PPU_SL_LCD)
+DEFINE_GR_PPU_SL(SL_LCD)
+#endif
+
+#if (RTE_GR_PPU_SL_BLE)
+DEFINE_GR_PPU_SL(SL_BLE)
+#endif
+
+#if (RTE_GR_PPU_SL_USBFS)
+DEFINE_GR_PPU_SL(SL_USBFS)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR4)
+DEFINE_GR_PPU_SL(SL_PERI_GR4)
+#endif
+
+#if (RTE_GR_PPU_SL_SMIF)
+DEFINE_GR_PPU_SL(SL_SMIF)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR6)
+DEFINE_GR_PPU_SL(SL_PERI_GR6)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB0)
+DEFINE_GR_PPU_SL(SL_SCB0)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB1)
+DEFINE_GR_PPU_SL(SL_SCB1)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB2)
+DEFINE_GR_PPU_SL(SL_SCB2)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB3)
+DEFINE_GR_PPU_SL(SL_SCB3)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB4)
+DEFINE_GR_PPU_SL(SL_SCB4)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB5)
+DEFINE_GR_PPU_SL(SL_SCB5)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB6)
+DEFINE_GR_PPU_SL(SL_SCB6)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB7)
+DEFINE_GR_PPU_SL(SL_SCB7)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB8)
+DEFINE_GR_PPU_SL(SL_SCB8)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR9)
+DEFINE_GR_PPU_SL(SL_PERI_GR9)
+#endif
+
+#if (RTE_GR_PPU_SL_PASS)
+DEFINE_GR_PPU_SL(SL_PASS)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR10)
+DEFINE_GR_PPU_SL(SL_PERI_GR10)
+#endif
+
+#if (RTE_GR_PPU_SL_I2S)
+DEFINE_GR_PPU_SL(SL_I2S)
+#endif
+
+#if (RTE_GR_PPU_SL_PDM)
+DEFINE_GR_PPU_SL(SL_PDM)
+#endif
+
diff --git a/platform/ext/target/psoc64/driver_ppu.h b/platform/ext/target/psoc64/driver_ppu.h
new file mode 100644
index 0000000000..4dcb2ad39c
--- /dev/null
+++ b/platform/ext/target/psoc64/driver_ppu.h
@@ -0,0 +1,435 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DRIVER_PPU_H__
+#define __DRIVER_PPU_H__
+
+#include "cy_prot.h"
+#include "RTE_Device.h"
+
+/* PSoC 6 has 6 different kinds of PPU */
+enum ppu_type {
+ MS_PPU_PR,
+ MS_PPU_FX,
+ PPU_PR,
+ PPU_GR,
+ GR_PPU_SL,
+ GR_PPU_RG,
+ NO_PPU
+};
+
+typedef struct ppu_resources PPU_Resources;
+
+/* Shared Driver wrapper functions */
+cy_en_prot_status_t PPU_Configure(const PPU_Resources *ppu_dev);
+
+/* Per-PPU macros */
+#define DECLARE_MS_PPU_PR(N) extern const PPU_Resources N##_PPU_Resources;
+#define DECLARE_MS_PPU_FX(N) extern const PPU_Resources N##_PPU_Resources;
+#define DECLARE_PPU_PR(N) extern const PPU_Resources N##_PPU_Resources;
+#define DECLARE_PPU_GR(N) extern const PPU_Resources N##_PPU_Resources;
+#define DECLARE_GR_PPU_SL(N) extern const PPU_Resources N##_PPU_Resources;
+#define DECLARE_GR_PPU_RG(N) extern const PPU_Resources N##_PPU_Resources;
+
+#if (RTE_PPU_PR0)
+DECLARE_PPU_PR(PR0)
+#endif
+
+#if (RTE_PPU_PR1)
+DECLARE_PPU_PR(PR1)
+#endif
+
+#if (RTE_PPU_PR2)
+DECLARE_PPU_PR(PR2)
+#endif
+
+#if (RTE_PPU_PR3)
+DECLARE_PPU_PR(PR3)
+#endif
+
+#if (RTE_PPU_PR4)
+DECLARE_PPU_PR(PR4)
+#endif
+
+#if (RTE_PPU_PR5)
+DECLARE_PPU_PR(PR5)
+#endif
+
+#if (RTE_PPU_PR6)
+DECLARE_PPU_PR(PR6)
+#endif
+
+#if (RTE_PPU_PR7)
+DECLARE_PPU_PR(PR7)
+#endif
+
+#if (RTE_PPU_PR8)
+DECLARE_PPU_PR(PR8)
+#endif
+
+#if (RTE_PPU_GR0)
+DECLARE_PPU_GR(GR0)
+#endif
+
+#if (RTE_PPU_GR1)
+DECLARE_PPU_GR(GR1)
+#endif
+
+#if (RTE_PPU_GR2)
+DECLARE_PPU_GR(GR2)
+#endif
+
+#if (RTE_PPU_GR3)
+DECLARE_PPU_GR(GR3)
+#endif
+
+#if (RTE_PPU_GR4)
+DECLARE_PPU_GR(GR4)
+#endif
+
+#if (RTE_PPU_GR6)
+DECLARE_PPU_GR(GR6)
+#endif
+
+#if (RTE_PPU_GR9)
+DECLARE_PPU_GR(GR9)
+#endif
+
+#if (RTE_PPU_GR10)
+DECLARE_PPU_GR(GR10)
+#endif
+
+#if (RTE_PPU_GR_MMIO0)
+DECLARE_PPU_GR(GR_MMIO0)
+#endif
+
+#if (RTE_PPU_GR_MMIO1)
+DECLARE_PPU_GR(GR_MMIO1)
+#endif
+
+#if (RTE_PPU_GR_MMIO2)
+DECLARE_PPU_GR(GR_MMIO2)
+#endif
+
+#if (RTE_PPU_GR_MMIO3)
+DECLARE_PPU_GR(GR_MMIO3)
+#endif
+
+#if (RTE_PPU_GR_MMIO4)
+DECLARE_PPU_GR(GR_MMIO4)
+#endif
+
+#if (RTE_PPU_GR_MMIO6)
+DECLARE_PPU_GR(GR_MMIO6)
+#endif
+
+#if (RTE_PPU_GR_MMIO9)
+DECLARE_PPU_GR(GR_MMIO9)
+#endif
+
+#if (RTE_PPU_GR_MMIO10)
+DECLARE_PPU_GR(GR_MMIO10)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR1)
+DECLARE_GR_PPU_SL(SL_PERI_GR1)
+#endif
+
+#if (RTE_GR_PPU_SL_CRYPTO)
+DECLARE_GR_PPU_SL(SL_CRYPTO)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR2)
+DECLARE_GR_PPU_SL(SL_PERI_GR2)
+#endif
+
+#if (RTE_GR_PPU_SL_CPUSS)
+DECLARE_GR_PPU_SL(SL_CPUSS)
+#endif
+
+#if (RTE_GR_PPU_SL_FAULT)
+DECLARE_GR_PPU_SL(SL_FAULT)
+#endif
+
+#if (RTE_GR_PPU_SL_IPC)
+DECLARE_GR_PPU_SL(SL_IPC)
+#endif
+
+#if (RTE_GR_PPU_SL_PROT)
+DECLARE_GR_PPU_SL(SL_PROT)
+#endif
+
+#if (RTE_GR_PPU_SL_FLASHC)
+DECLARE_GR_PPU_SL(SL_FLASHC)
+#endif
+
+#if (RTE_GR_PPU_SL_SRSS)
+DECLARE_GR_PPU_SL(SL_SRSS)
+#endif
+
+#if (RTE_GR_PPU_SL_BACKUP)
+DECLARE_GR_PPU_SL(SL_BACKUP)
+#endif
+
+#if (RTE_GR_PPU_SL_DW0)
+DECLARE_GR_PPU_SL(SL_DW0)
+#endif
+
+#if (RTE_GR_PPU_SL_DW1)
+DECLARE_GR_PPU_SL(SL_DW1)
+#endif
+
+#if (RTE_GR_PPU_SL_EFUSE)
+DECLARE_GR_PPU_SL(SL_EFUSE)
+#endif
+
+#if (RTE_GR_PPU_SL_PROFILE)
+DECLARE_GR_PPU_SL(SL_PROFILE)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT0)
+DECLARE_GR_PPU_RG(RG_IPC_STRUCT0)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT1)
+DECLARE_GR_PPU_RG(RG_IPC_STRUCT1)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT2)
+DECLARE_GR_PPU_RG(RG_IPC_STRUCT2)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT3)
+DECLARE_GR_PPU_RG(RG_IPC_STRUCT3)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT4)
+DECLARE_GR_PPU_RG(RG_IPC_STRUCT4)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT5)
+DECLARE_GR_PPU_RG(RG_IPC_STRUCT5)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT6)
+DECLARE_GR_PPU_RG(RG_IPC_STRUCT6)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_STRUCT7)
+DECLARE_GR_PPU_RG(RG_IPC_STRUCT7)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT0)
+DECLARE_GR_PPU_RG(RG_IPC_INTR_STRUCT0)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT1)
+DECLARE_GR_PPU_RG(RG_IPC_INTR_STRUCT1)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT2)
+DECLARE_GR_PPU_RG(RG_IPC_INTR_STRUCT2)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT3)
+DECLARE_GR_PPU_RG(RG_IPC_INTR_STRUCT3)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT4)
+DECLARE_GR_PPU_RG(RG_IPC_INTR_STRUCT4)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT5)
+DECLARE_GR_PPU_RG(RG_IPC_INTR_STRUCT5)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT6)
+DECLARE_GR_PPU_RG(RG_IPC_INTR_STRUCT6)
+#endif
+
+#if (RTE_GR_PPU_RG_IPC_INTR_STRUCT7)
+DECLARE_GR_PPU_RG(RG_IPC_INTR_STRUCT7)
+#endif
+
+#if (RTE_GR_PPU_RG_DW0_DW_CH_STRUCT0)
+DECLARE_GR_PPU_RG(RG_DW0_DW_CH_STRUCT0)
+#endif
+
+#if (RTE_GR_PPU_RG_DW0_DW_CH_STRUCT1)
+DECLARE_GR_PPU_RG(RG_DW0_DW_CH_STRUCT1)
+#endif
+
+#if (RTE_GR_PPU_RG_DW0_DW_CH_STRUCT2)
+DECLARE_GR_PPU_RG(RG_DW0_DW_CH_STRUCT2)
+#endif
+
+#if (RTE_GR_PPU_RG_DW0_DW_CH_STRUCT3)
+DECLARE_GR_PPU_RG(RG_DW0_DW_CH_STRUCT3)
+#endif
+
+#if (RTE_GR_PPU_RG_DW1_DW_CH_STRUCT0)
+DECLARE_GR_PPU_RG(RG_DW1_DW_CH_STRUCT0)
+#endif
+
+#if (RTE_GR_PPU_RG_DW1_DW_CH_STRUCT1)
+DECLARE_GR_PPU_RG(RG_DW1_DW_CH_STRUCT1)
+#endif
+
+#if (RTE_GR_PPU_RG_DW1_DW_CH_STRUCT2)
+DECLARE_GR_PPU_RG(RG_DW1_DW_CH_STRUCT2)
+#endif
+
+#if (RTE_GR_PPU_RG_DW1_DW_CH_STRUCT3)
+DECLARE_GR_PPU_RG(RG_DW1_DW_CH_STRUCT3)
+#endif
+
+#if (RTE_GR_PPU_RG_SMPU)
+DECLARE_GR_PPU_RG(RG_SMPU)
+#endif
+
+#if (RTE_GR_PPU_RG_MPU_CM0P)
+DECLARE_GR_PPU_RG(RG_MPU_CM0P)
+#endif
+
+#if (RTE_GR_PPU_RG_MPU_CRYPTO)
+DECLARE_GR_PPU_RG(RG_MPU_CRYPTO)
+#endif
+
+#if (RTE_GR_PPU_RG_MPU_CM4)
+DECLARE_GR_PPU_RG(RG_MPU_CM4)
+#endif
+
+#if (RTE_GR_PPU_RG_MPU_TC)
+DECLARE_GR_PPU_RG(RG_MPU_TC)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR3)
+DECLARE_GR_PPU_SL(SL_PERI_GR3)
+#endif
+
+#if (RTE_GR_PPU_SL_HSIOM)
+DECLARE_GR_PPU_SL(SL_HSIOM)
+#endif
+
+#if (RTE_GR_PPU_SL_GPIO)
+DECLARE_GR_PPU_SL(SL_GPIO)
+#endif
+
+#if (RTE_GR_PPU_SL_SMARTIO)
+DECLARE_GR_PPU_SL(SL_SMARTIO)
+#endif
+
+#if (RTE_GR_PPU_SL_UDB)
+DECLARE_GR_PPU_SL(SL_UDB)
+#endif
+
+#if (RTE_GR_PPU_SL_LPCOMP)
+DECLARE_GR_PPU_SL(SL_LPCOMP)
+#endif
+
+#if (RTE_GR_PPU_SL_CSD)
+DECLARE_GR_PPU_SL(SL_CSD)
+#endif
+
+#if (RTE_GR_PPU_SL_TCPWM0)
+DECLARE_GR_PPU_SL(SL_TCPWM0)
+#endif
+
+#if (RTE_GR_PPU_SL_TCPWM1)
+DECLARE_GR_PPU_SL(SL_TCPWM1)
+#endif
+
+#if (RTE_GR_PPU_SL_LCD)
+DECLARE_GR_PPU_SL(SL_LCD)
+#endif
+
+#if (RTE_GR_PPU_SL_BLE)
+DECLARE_GR_PPU_SL(SL_BLE)
+#endif
+
+#if (RTE_GR_PPU_SL_USBFS)
+DECLARE_GR_PPU_SL(SL_USBFS)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR4)
+DECLARE_GR_PPU_SL(SL_PERI_GR4)
+#endif
+
+#if (RTE_GR_PPU_SL_SMIF)
+DECLARE_GR_PPU_SL(SL_SMIF)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR6)
+DECLARE_GR_PPU_SL(SL_PERI_GR6)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB0)
+DECLARE_GR_PPU_SL(SL_SCB0)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB1)
+DECLARE_GR_PPU_SL(SL_SCB1)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB2)
+DECLARE_GR_PPU_SL(SL_SCB2)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB3)
+DECLARE_GR_PPU_SL(SL_SCB3)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB4)
+DECLARE_GR_PPU_SL(SL_SCB4)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB5)
+DECLARE_GR_PPU_SL(SL_SCB5)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB6)
+DECLARE_GR_PPU_SL(SL_SCB6)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB7)
+DECLARE_GR_PPU_SL(SL_SCB7)
+#endif
+
+#if (RTE_GR_PPU_SL_SCB8)
+DECLARE_GR_PPU_SL(SL_SCB8)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR9)
+DECLARE_GR_PPU_SL(SL_PERI_GR9)
+#endif
+
+#if (RTE_GR_PPU_SL_PASS)
+DECLARE_GR_PPU_SL(SL_PASS)
+#endif
+
+#if (RTE_GR_PPU_SL_PERI_GR10)
+DECLARE_GR_PPU_SL(SL_PERI_GR10)
+#endif
+
+#if (RTE_GR_PPU_SL_I2S)
+DECLARE_GR_PPU_SL(SL_I2S)
+#endif
+
+#if (RTE_GR_PPU_SL_PDM)
+DECLARE_GR_PPU_SL(SL_PDM)
+#endif
+
+#endif /* __DRIVER_PPU_H__ */
diff --git a/platform/ext/target/psoc64/driver_smpu.c b/platform/ext/target/psoc64/driver_smpu.c
new file mode 100644
index 0000000000..c1363628cd
--- /dev/null
+++ b/platform/ext/target/psoc64/driver_smpu.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+
+#include "driver_smpu.h"
+#include "pc_config.h"
+#include "region_defs.h"
+#include "RTE_Device.h"
+#include "smpu_config.h"
+
+#include "cy_prot.h"
+
+/* Affect all 8 subregions */
+#define ALL_ENABLED 0
+
+struct smpu_resources {
+ PROT_SMPU_SMPU_STRUCT_Type *smpu;
+ cy_stc_smpu_cfg_t slave_config;
+ cy_stc_smpu_cfg_t master_config;
+};
+
+static const char * smpu_name(const SMPU_Resources *smpu_dev)
+{
+ switch ((int)smpu_dev->smpu) {
+ case (int)PROT_SMPU_SMPU_STRUCT0:
+ return "SMPU 0";
+ case (int)PROT_SMPU_SMPU_STRUCT1:
+ return "SMPU 1";
+ case (int)PROT_SMPU_SMPU_STRUCT2:
+ return "SMPU 2";
+ case (int)PROT_SMPU_SMPU_STRUCT3:
+ return "SMPU 3";
+ case (int)PROT_SMPU_SMPU_STRUCT4:
+ return "SMPU 4";
+ case (int)PROT_SMPU_SMPU_STRUCT5:
+ return "SMPU 5";
+ case (int)PROT_SMPU_SMPU_STRUCT6:
+ return "SMPU 6";
+ case (int)PROT_SMPU_SMPU_STRUCT7:
+ return "SMPU 7";
+ case (int)PROT_SMPU_SMPU_STRUCT8:
+ return "SMPU 8";
+ case (int)PROT_SMPU_SMPU_STRUCT9:
+ return "SMPU 9";
+ case (int)PROT_SMPU_SMPU_STRUCT10:
+ return "SMPU 10";
+ case (int)PROT_SMPU_SMPU_STRUCT11:
+ return "SMPU 11";
+ case (int)PROT_SMPU_SMPU_STRUCT12:
+ return "SMPU 12";
+ case (int)PROT_SMPU_SMPU_STRUCT13:
+ return "SMPU 13";
+ case (int)PROT_SMPU_SMPU_STRUCT14:
+ return "SMPU 14";
+ case (int)PROT_SMPU_SMPU_STRUCT15:
+ return "SMPU 15";
+ default:
+ return "Unrecognised SMPU";
+ }
+}
+
+/* API functions */
+cy_en_prot_status_t SMPU_Configure(const SMPU_Resources *smpu_dev)
+{
+ cy_en_prot_status_t ret;
+
+ printf("%s(%s) - address = %p, size = %#x bytes, %s subregions enabled\n",
+ __func__,
+ smpu_name(smpu_dev),
+ smpu_dev->slave_config.address,
+ (uint32_t)REGIONSIZE_TO_BYTES(smpu_dev->slave_config.regionSize),
+ smpu_dev->slave_config.subregions == ALL_ENABLED ? "all" : "some");
+ if (smpu_dev->slave_config.subregions != ALL_ENABLED) {
+ printf("\tsubregion size = %#x bytes\n",
+ (uint32_t)REGIONSIZE_TO_BYTES(smpu_dev->slave_config.regionSize)/8);
+ for (int i=0; i<8; i++) {
+ printf("\tsubregion %d %s\n",
+ i,
+ smpu_dev->slave_config.subregions & (1<<i) ? "disabled" : "enabled");
+ }
+ }
+
+ ret = Cy_Prot_ConfigSmpuSlaveStruct(smpu_dev->smpu,
+ &smpu_dev->slave_config);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+ ret = Cy_Prot_ConfigSmpuMasterStruct(smpu_dev->smpu,
+ &smpu_dev->master_config);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+ ret = Cy_Prot_EnableSmpuSlaveStruct(smpu_dev->smpu);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+ ret = Cy_Prot_EnableSmpuMasterStruct(smpu_dev->smpu);
+ return ret;
+}
+
+/* Only allow privileged secure PC=1 bus masters to change unconfigured SMPUs */
+cy_en_prot_status_t protect_unconfigured_smpus(void)
+{
+ const cy_stc_smpu_cfg_t smpu_config = COMMON_SMPU_MASTER_CONFIG;
+ cy_en_prot_status_t ret = CY_PROT_SUCCESS;
+ int i;
+ uint32_t att0, att1;
+
+ for (i = 0; i < CPUSS_PROT_SMPU_STRUCT_NR; i++) {
+ att0 = PROT->SMPU.SMPU_STRUCT[i].ATT0;
+ att1 = PROT->SMPU.SMPU_STRUCT[i].ATT1;
+
+ if ((_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, att0) == 0)
+ && (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, att1) == 0)) {
+ printf("%s() - protecting unconfigured SMPU %d\n",
+ __func__, i);
+ ret = Cy_Prot_ConfigSmpuMasterStruct(&PROT->SMPU.SMPU_STRUCT[i],
+ &smpu_config);
+ if (ret != CY_PROT_SUCCESS) {
+ break;
+ }
+ ret = Cy_Prot_EnableSmpuMasterStruct(&PROT->SMPU.SMPU_STRUCT[i]);
+ if (ret != CY_PROT_SUCCESS) {
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/* Exported per-SMPU macros */
+#define DEFINE_SMPU(N) const SMPU_Resources SMPU##N##_Resources = { \
+ .smpu = PROT_SMPU_SMPU_STRUCT##N, \
+ .slave_config = SMPU##N##_SLAVE_CONFIG, \
+ .master_config = SMPU##N##_MASTER_CONFIG, \
+}; \
+
+#if (RTE_SMPU0)
+DEFINE_SMPU(0)
+#endif /* RTE_SMPU0 */
+
+#if (RTE_SMPU1)
+DEFINE_SMPU(1)
+#endif /* RTE_SMPU1 */
+
+#if (RTE_SMPU2)
+DEFINE_SMPU(2)
+#endif /* RTE_SMPU2 */
+
+#if (RTE_SMPU3)
+DEFINE_SMPU(3)
+#endif /* RTE_SMPU3 */
+
+#if (RTE_SMPU4)
+DEFINE_SMPU(4)
+#endif /* RTE_SMPU4 */
+
+#if (RTE_SMPU5)
+DEFINE_SMPU(5)
+#endif /* RTE_SMPU5 */
+
+#if (RTE_SMPU6)
+DEFINE_SMPU(6)
+#endif /* RTE_SMPU6 */
+
+#if (RTE_SMPU7)
+DEFINE_SMPU(7)
+#endif /* RTE_SMPU7 */
+
+#if (RTE_SMPU8)
+DEFINE_SMPU(8)
+#endif /* RTE_SMPU8 */
+
+#if (RTE_SMPU9)
+DEFINE_SMPU(9)
+#endif /* RTE_SMPU9 */
+
+#if (RTE_SMPU10)
+DEFINE_SMPU(10)
+#endif /* RTE_SMPU10 */
+
+#if (RTE_SMPU11)
+DEFINE_SMPU(11)
+#endif /* RTE_SMPU11 */
+
+#if (RTE_SMPU12)
+DEFINE_SMPU(12)
+#endif /* RTE_SMPU12 */
+
+#if (RTE_SMPU13)
+DEFINE_SMPU(13)
+#endif /* RTE_SMPU13 */
+
+/* Note that SMPUs 14 and 15 are fixed by romboot */
diff --git a/platform/ext/target/psoc64/driver_smpu.h b/platform/ext/target/psoc64/driver_smpu.h
new file mode 100644
index 0000000000..46bc0f2f38
--- /dev/null
+++ b/platform/ext/target/psoc64/driver_smpu.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DRIVER_SMPU_H__
+#define __DRIVER_SMPU_H__
+
+#include "cy_prot.h"
+#include "RTE_Device.h"
+
+typedef struct smpu_resources SMPU_Resources;
+
+/* API functions */
+cy_en_prot_status_t SMPU_Configure(const SMPU_Resources *smpu_dev);
+cy_en_prot_status_t protect_unconfigured_smpus(void);
+
+/* Exported per-SMPU macros */
+#define DECLARE_SMPU(N) extern const SMPU_Resources SMPU##N##_Resources;
+
+#if (RTE_SMPU0)
+DECLARE_SMPU(0)
+#endif /* RTE_SMPU0 */
+
+#if (RTE_SMPU1)
+DECLARE_SMPU(1)
+#endif /* RTE_SMPU1 */
+
+#if (RTE_SMPU2)
+DECLARE_SMPU(2)
+#endif /* RTE_SMPU2 */
+
+#if (RTE_SMPU3)
+DECLARE_SMPU(3)
+#endif /* RTE_SMPU3 */
+
+#if (RTE_SMPU4)
+DECLARE_SMPU(4)
+#endif /* RTE_SMPU4 */
+
+#if (RTE_SMPU5)
+DECLARE_SMPU(5)
+#endif /* RTE_SMPU5 */
+
+#if (RTE_SMPU6)
+DECLARE_SMPU(6)
+#endif /* RTE_SMPU6 */
+
+#if (RTE_SMPU7)
+DECLARE_SMPU(7)
+#endif /* RTE_SMPU7 */
+
+#if (RTE_SMPU8)
+DECLARE_SMPU(8)
+#endif /* RTE_SMPU8 */
+
+#if (RTE_SMPU9)
+DECLARE_SMPU(9)
+#endif /* RTE_SMPU9 */
+
+#if (RTE_SMPU10)
+DECLARE_SMPU(10)
+#endif /* RTE_SMPU10 */
+
+#if (RTE_SMPU11)
+DECLARE_SMPU(11)
+#endif /* RTE_SMPU11 */
+
+#if (RTE_SMPU12)
+DECLARE_SMPU(12)
+#endif /* RTE_SMPU12 */
+
+#if (RTE_SMPU13)
+DECLARE_SMPU(13)
+#endif /* RTE_SMPU13 */
+
+/* Note that SMPUs 14 and 15 are fixed by romboot */
+
+#endif /* __DRIVER_SMPU_H__ */
diff --git a/platform/ext/target/psoc64/dummy_boot_seed.c b/platform/ext/target/psoc64/dummy_boot_seed.c
new file mode 100644
index 0000000000..f4cbb5c3b4
--- /dev/null
+++ b/platform/ext/target/psoc64/dummy_boot_seed.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/include/tfm_plat_boot_seed.h"
+
+/*!
+ * \def BOOT_SEED
+ *
+ * \brief Fixed value for boot seed used for test.
+ */
+#define BOOT_SEED 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, \
+ 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, \
+ 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, \
+ 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF
+
+static const uint8_t boot_seed[BOOT_SEED_SIZE] = {BOOT_SEED};
+
+enum tfm_plat_err_t tfm_plat_get_boot_seed(uint32_t size, uint8_t *buf)
+{
+ /* FixMe: - This getter function must be ported per target platform.
+ * - Platform service shall provide an API to further interact this
+ * getter function to retrieve the boot seed.
+ */
+
+ uint32_t i;
+ uint8_t *p_dst = buf;
+ const uint8_t *p_src = boot_seed;
+
+ if (size != BOOT_SEED_SIZE) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ for (i = size; i > 0; i--) {
+ *p_dst = *p_src;
+ p_src++;
+ p_dst++;
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
diff --git a/platform/ext/target/psoc64/dummy_crypto_keys.c b/platform/ext/target/psoc64/dummy_crypto_keys.c
new file mode 100644
index 0000000000..93073c09b0
--- /dev/null
+++ b/platform/ext/target/psoc64/dummy_crypto_keys.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2017-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/include/tfm_plat_crypto_keys.h"
+#include <stddef.h>
+
+/* FIXME: Functions in this file should be implemented by platform vendor. For
+ * the security of the storage system, it is critical to use a hardware unique
+ * key. For the security of the attestation, it is critical to use a unique key
+ * pair and keep the private key is secret.
+ */
+
+#define TFM_KEY_LEN_BYTES 16
+
+static const uint8_t sample_tfm_key[TFM_KEY_LEN_BYTES] =
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F};
+
+extern const enum ecc_curve_t initial_attestation_curve_type;
+extern const uint8_t initial_attestation_private_key[];
+extern const uint32_t initial_attestation_private_key_size;
+extern const uint8_t initial_attestation_public_x_key[];
+extern const uint32_t initial_attestation_public_x_key_size;
+extern const uint8_t initial_attestation_public_y_key[];
+extern const uint32_t initial_attestation_public_y_key_size;
+
+extern const struct tfm_plat_rotpk_t device_rotpk[];
+extern const uint32_t rotpk_key_cnt;
+
+/**
+ * \brief Copy the key to the destination buffer
+ *
+ * \param[out] p_dst Pointer to buffer where to store the key
+ * \param[in] p_src Pointer to the key
+ * \param[in] size Length of the key
+ */
+static inline void copy_key(uint8_t *p_dst, const uint8_t *p_src, size_t size)
+{
+ uint32_t i;
+
+ for (i = size; i > 0; i--) {
+ *p_dst = *p_src;
+ p_src++;
+ p_dst++;
+ }
+}
+
+enum tfm_plat_err_t tfm_plat_get_crypto_huk(uint8_t *key, uint32_t size)
+{
+ if(size > TFM_KEY_LEN_BYTES) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ copy_key(key, sample_tfm_key, size);
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t
+tfm_plat_get_initial_attest_key(uint8_t *key_buf,
+ uint32_t size,
+ struct ecc_key_t *ecc_key,
+ enum ecc_curve_t *curve_type)
+{
+ uint8_t *key_dst;
+ const uint8_t *key_src;
+ uint32_t key_size;
+ uint32_t full_key_size = initial_attestation_private_key_size +
+ initial_attestation_public_x_key_size +
+ initial_attestation_public_y_key_size;
+
+ if (size < full_key_size) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Set the EC curve type which the key belongs to */
+ *curve_type = initial_attestation_curve_type;
+
+ /* Copy the private key to the buffer, it MUST be present */
+ key_dst = key_buf;
+ key_src = initial_attestation_private_key;
+ key_size = initial_attestation_private_key_size;
+ copy_key(key_dst, key_src, key_size);
+ ecc_key->priv_key = key_dst;
+ ecc_key->priv_key_size = key_size;
+
+ /* Copy the x-coordinate of public key to the buffer, it MIGHT be present */
+ if (initial_attestation_public_x_key_size != 0) {
+ key_dst = key_dst + key_size;
+ key_src = initial_attestation_public_x_key;
+ key_size = initial_attestation_public_x_key_size;
+ copy_key(key_dst, key_src, key_size);
+ ecc_key->pubx_key = key_dst;
+ ecc_key->pubx_key_size = key_size;
+ } else {
+ ecc_key->pubx_key = NULL;
+ ecc_key->pubx_key_size = 0;
+ }
+
+ /* Copy the y-coordinate of public key to the buffer, it MIGHT be present */
+ if (initial_attestation_public_y_key_size != 0) {
+ key_dst = key_dst + key_size;
+ key_src = initial_attestation_public_y_key;
+ key_size = initial_attestation_public_y_key_size;
+ copy_key(key_dst, key_src, key_size);
+ ecc_key->puby_key = key_dst;
+ ecc_key->puby_key_size = key_size;
+ } else {
+ ecc_key->puby_key = NULL;
+ ecc_key->puby_key_size = 0;
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+#ifdef BL2
+enum tfm_plat_err_t
+tfm_plat_get_rotpk_hash(uint8_t image_id,
+ uint8_t *rotpk_hash,
+ uint32_t *rotpk_hash_size)
+{
+ if(*rotpk_hash_size < ROTPK_HASH_LEN) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ if (image_id >= rotpk_key_cnt) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ *rotpk_hash_size = ROTPK_HASH_LEN;
+ copy_key(rotpk_hash, device_rotpk[image_id].key_hash, *rotpk_hash_size);
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+#endif
diff --git a/platform/ext/target/psoc64/dummy_device_id.c b/platform/ext/target/psoc64/dummy_device_id.c
new file mode 100644
index 0000000000..d282385081
--- /dev/null
+++ b/platform/ext/target/psoc64/dummy_device_id.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/include/tfm_plat_device_id.h"
+#include <stddef.h>
+/*
+ * NOTE: Functions in this file must be ported per target platform.
+ */
+
+extern const uint8_t initial_attestation_raw_public_key_hash[];
+extern const uint32_t initial_attestation_raw_public_key_hash_size;
+
+static const uint8_t implementation_id[] = {
+ 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
+ 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
+ 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+ 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+};
+
+static const uint8_t example_ean_13[] = "060456527282910010";
+/**
+ * \brief Copy the device specific ID to the destination buffer
+ *
+ * \param[out] p_dst Pointer to buffer where to store ID
+ * \param[in] p_src Pointer to the ID
+ * \param[in] size Length of the ID
+ */
+static inline void copy_id(uint8_t *p_dst, const uint8_t *p_src, size_t size)
+{
+ uint32_t i;
+
+ for (i = size; i > 0; i--) {
+ *p_dst = *p_src;
+ p_src++;
+ p_dst++;
+ }
+}
+
+/**
+ * Instance ID is mapped to EAT Universal Entity ID (UEID)
+ * This implementation creates the instance ID as follows:
+ * - byte 0: 0x01 indicates the type of UEID to be GUID
+ * - byte 1-32: Hash of attestation public key. Public key is hashed in raw
+ * format without any encoding.
+ */
+enum tfm_plat_err_t tfm_plat_get_instance_id(uint32_t *size, uint8_t *buf)
+{
+ uint8_t *p_dst;
+ const uint8_t *p_src = initial_attestation_raw_public_key_hash;
+
+ if (*size < INSTANCE_ID_MAX_SIZE) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ buf[0] = 0x01; /* First byte is type byte: 0x01 indicates GUID */
+ p_dst = &buf[1];
+
+ copy_id(p_dst, p_src, initial_attestation_raw_public_key_hash_size);
+
+ /* Instance ID size: 1 type byte + size of public key hash */
+ *size = initial_attestation_raw_public_key_hash_size + 1;
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_get_implementation_id(uint32_t *size,
+ uint8_t *buf)
+{
+ const uint8_t *p_impl_id = implementation_id;
+ uint32_t impl_id_size = sizeof(implementation_id);
+
+ if (*size < impl_id_size) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ copy_id(buf, p_impl_id, impl_id_size);
+ *size = impl_id_size;
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_get_hw_version(uint32_t *size, uint8_t *buf)
+{
+ const uint8_t *p_hw_version = example_ean_13;
+ uint32_t hw_version_size = sizeof(example_ean_13) - 1;
+
+ if (*size < hw_version_size) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ copy_id(buf, p_hw_version, hw_version_size);
+ *size = hw_version_size;
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
diff --git a/platform/ext/target/psoc64/dummy_nv_counters.c b/platform/ext/target/psoc64/dummy_nv_counters.c
new file mode 100644
index 0000000000..b867a933d8
--- /dev/null
+++ b/platform/ext/target/psoc64/dummy_nv_counters.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/* NOTE: This API should be implemented by platform vendor. For the security of
+ * the secure storage system's and the bootloader's rollback protection etc. it
+ * is CRITICAL to use a internal (in-die) persistent memory for multiple time
+ * programmable (MTP) non-volatile counters or use a One-time Programmable (OTP)
+ * non-volatile counters solution.
+ *
+ * The current software dummy implementation is not resistant to asynchronous
+ * power failures and should not be used in production code. It is exclusively
+ * for testing purposes.
+ */
+
+#include "platform/include/tfm_plat_nv_counters.h"
+
+#include <limits.h>
+#include "Driver_Flash.h"
+#include "flash_layout.h"
+
+/* Compilation time checks to be sure the defines are well defined */
+#ifndef TFM_NV_COUNTERS_AREA_ADDR
+#error "TFM_NV_COUNTERS_AREA_ADDR must be defined in flash_layout.h"
+#endif
+
+#ifndef TFM_NV_COUNTERS_AREA_SIZE
+#error "TFM_NV_COUNTERS_AREA_SIZE must be defined in flash_layout.h"
+#endif
+
+#ifndef TFM_NV_COUNTERS_SECTOR_ADDR
+#error "TFM_NV_COUNTERS_SECTOR_ADDR must be defined in flash_layout.h"
+#endif
+
+#ifndef TFM_NV_COUNTERS_SECTOR_SIZE
+#error "TFM_NV_COUNTERS_SECTOR_SIZE must be defined in flash_layout.h"
+#endif
+
+#ifndef FLASH_DEV_NAME
+#error "FLASH_DEV_NAME must be defined in flash_layout.h"
+#endif
+/* End of compilation time checks to be sure the defines are well defined */
+
+#define SECTOR_OFFSET 0
+#define NV_COUNTER_SIZE sizeof(uint32_t)
+#define INIT_VALUE_SIZE NV_COUNTER_SIZE
+#define NV_COUNTERS_AREA_OFFSET (TFM_NV_COUNTERS_AREA_ADDR - \
+ TFM_NV_COUNTERS_SECTOR_ADDR)
+
+#define NV_COUNTERS_INITIALIZED 0xC0DE0042
+
+/* Import the CMSIS flash device driver */
+extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
+
+enum tfm_plat_err_t tfm_plat_init_nv_counter(void)
+{
+ int32_t err;
+ uint32_t i;
+ uint32_t nbr_counters = ((TFM_NV_COUNTERS_AREA_SIZE - INIT_VALUE_SIZE)
+ / NV_COUNTER_SIZE);
+ uint32_t *p_nv_counter;
+ uint8_t sector_data[TFM_NV_COUNTERS_SECTOR_SIZE] = {0};
+
+ err = FLASH_DEV_NAME.Initialize(NULL);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Read the whole sector to be able to erase and write later in the flash */
+ err = FLASH_DEV_NAME.ReadData(TFM_NV_COUNTERS_SECTOR_ADDR, sector_data,
+ TFM_NV_COUNTERS_SECTOR_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Set the pointer to nv counters position */
+ p_nv_counter = (uint32_t *)(sector_data + NV_COUNTERS_AREA_OFFSET);
+
+ if (p_nv_counter[nbr_counters] == NV_COUNTERS_INITIALIZED) {
+ return TFM_PLAT_ERR_SUCCESS;
+ }
+
+ /* Add watermark, at the end of the NV counters area, to indicate that NV
+ * counters have been initialized.
+ */
+ p_nv_counter[nbr_counters] = NV_COUNTERS_INITIALIZED;
+
+ /* Initialize all counters to 0 */
+ for (i = 0; i < nbr_counters; i++) {
+ p_nv_counter[i] = 0;
+ }
+
+ /* Erase sector before write in it */
+ err = FLASH_DEV_NAME.EraseSector(TFM_NV_COUNTERS_SECTOR_ADDR);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Write in flash the in-memory block content after modification */
+ err = FLASH_DEV_NAME.ProgramData(TFM_NV_COUNTERS_SECTOR_ADDR, sector_data,
+ TFM_NV_COUNTERS_SECTOR_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_read_nv_counter(enum tfm_nv_counter_t counter_id,
+ uint32_t size, uint8_t *val)
+{
+ int32_t err;
+ uint32_t flash_addr;
+
+ if (size != NV_COUNTER_SIZE) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ flash_addr = TFM_NV_COUNTERS_AREA_ADDR + (counter_id * NV_COUNTER_SIZE);
+
+ err = FLASH_DEV_NAME.ReadData(flash_addr, val, NV_COUNTER_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_set_nv_counter(enum tfm_nv_counter_t counter_id,
+ uint32_t value)
+{
+ int32_t err;
+ uint32_t *p_nv_counter;
+ uint8_t sector_data[TFM_NV_COUNTERS_SECTOR_SIZE];
+
+ /* Read the whole sector to be able to erase and write later in the flash */
+ err = FLASH_DEV_NAME.ReadData(TFM_NV_COUNTERS_SECTOR_ADDR, sector_data,
+ TFM_NV_COUNTERS_SECTOR_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Set the pointer to nv counter position */
+ p_nv_counter = (uint32_t *)(sector_data + NV_COUNTERS_AREA_OFFSET +
+ (counter_id * NV_COUNTER_SIZE));
+
+ if (value != *p_nv_counter) {
+
+ if (value > *p_nv_counter) {
+ *p_nv_counter = value;
+ } else {
+ return TFM_PLAT_ERR_INVALID_INPUT;
+ }
+
+ /* Erase sector before write in it */
+ err = FLASH_DEV_NAME.EraseSector(TFM_NV_COUNTERS_SECTOR_ADDR);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Write in flash the in-memory block content after modification */
+ err = FLASH_DEV_NAME.ProgramData(TFM_NV_COUNTERS_SECTOR_ADDR,
+ sector_data,
+ TFM_NV_COUNTERS_SECTOR_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_increment_nv_counter(
+ enum tfm_nv_counter_t counter_id)
+{
+ uint32_t security_cnt;
+ enum tfm_plat_err_t err;
+
+ err = tfm_plat_read_nv_counter(counter_id,
+ sizeof(security_cnt),
+ (uint8_t *)&security_cnt);
+ if (err != TFM_PLAT_ERR_SUCCESS) {
+ return err;
+ }
+
+ if (security_cnt == UINT32_MAX) {
+ return TFM_PLAT_ERR_MAX_VALUE;
+ }
+
+ return tfm_plat_set_nv_counter(counter_id, security_cnt + 1u);
+}
diff --git a/platform/ext/target/psoc64/mailbox/mailbox_ipc_intr.c b/platform/ext/target/psoc64/mailbox/mailbox_ipc_intr.c
new file mode 100644
index 0000000000..38c1e3b274
--- /dev/null
+++ b/platform/ext/target/psoc64/mailbox/mailbox_ipc_intr.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdint.h>
+
+#include "cmsis.h"
+#include "cmsis_compiler.h"
+
+#include "cy_ipc_drv.h"
+#include "spe_ipc_config.h"
+#include "platform_multicore.h"
+
+__STATIC_INLINE void tfm_trigger_pendsv(void)
+{
+ SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
+}
+
+void mailbox_clear_intr(void)
+{
+ uint32_t status;
+
+ status = Cy_IPC_Drv_GetInterruptStatusMasked(
+ Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT));
+ status >>= CY_IPC_NOTIFY_SHIFT;
+ if ((status & IPC_RX_INT_MASK) == 0) {
+ return;
+ }
+
+ Cy_IPC_Drv_ClearInterrupt(Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT),
+ 0, IPC_RX_INT_MASK);
+}
+
+void NvicMux9_IRQHandler(void)
+{
+ uint32_t magic;
+
+ mailbox_clear_intr();
+
+ platform_mailbox_fetch_msg_data(&magic);
+ if (magic == PSA_CLIENT_CALL_REQ_MAGIC) {
+ tfm_trigger_pendsv();
+ }
+}
diff --git a/platform/ext/target/psoc64/mailbox/ns_ipc_config.h b/platform/ext/target/psoc64/mailbox/ns_ipc_config.h
new file mode 100644
index 0000000000..0549ba3035
--- /dev/null
+++ b/platform/ext/target/psoc64/mailbox/ns_ipc_config.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _IPC_CONFIG_H_
+#define _IPC_CONFIG_H_
+
+#include "platform_multicore.h"
+
+#define IPC_RX_CHAN IPC_PSA_CLIENT_REPLY_CHAN
+#define IPC_RX_INTR_STRUCT IPC_PSA_CLIENT_REPLY_INTR_STRUCT
+#define IPC_RX_INT_MASK IPC_PSA_CLIENT_REPLY_INTR_MASK
+
+#define IPC_TX_CHAN IPC_PSA_CLIENT_CALL_CHAN
+#define IPC_TX_NOTIFY_MASK IPC_PSA_CLIENT_CALL_NOTIFY_MASK
+
+#endif
diff --git a/platform/ext/target/psoc64/mailbox/platform_multicore.c b/platform/ext/target/psoc64/mailbox/platform_multicore.c
new file mode 100644
index 0000000000..5bb47491b3
--- /dev/null
+++ b/platform/ext/target/psoc64/mailbox/platform_multicore.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2019 Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "cmsis_compiler.h"
+
+#include "platform_multicore.h"
+#include "tfm_multi_core_api.h"
+#include "tfm_ns_mailbox.h"
+
+#include "cy_ipc_drv.h"
+#include "cy_sysint.h"
+#if CY_SYSTEM_CPU_CM0P
+#include "spe_ipc_config.h"
+#else
+#include "ns_ipc_config.h"
+#endif
+
+int platform_mailbox_fetch_msg_ptr(void **msg_ptr)
+{
+ cy_en_ipcdrv_status_t status;
+
+ if (!msg_ptr) {
+ return PLATFORM_MAILBOX_INVAL_PARAMS;
+ }
+
+ status = Cy_IPC_Drv_ReadMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(IPC_RX_CHAN),
+ msg_ptr);
+ if (status != CY_IPC_DRV_SUCCESS) {
+ return PLATFORM_MAILBOX_RX_ERROR;
+ }
+
+ Cy_IPC_Drv_ReleaseNotify(Cy_IPC_Drv_GetIpcBaseAddress(IPC_RX_CHAN),
+ IPC_RX_RELEASE_MASK);
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+int platform_mailbox_fetch_msg_data(uint32_t *data_ptr)
+{
+ cy_en_ipcdrv_status_t status;
+
+ if (!data_ptr) {
+ return PLATFORM_MAILBOX_INVAL_PARAMS;
+ }
+
+ status = Cy_IPC_Drv_ReadMsgWord(Cy_IPC_Drv_GetIpcBaseAddress(IPC_RX_CHAN),
+ data_ptr);
+ if (status != CY_IPC_DRV_SUCCESS) {
+ return PLATFORM_MAILBOX_RX_ERROR;
+ }
+
+ Cy_IPC_Drv_ReleaseNotify(Cy_IPC_Drv_GetIpcBaseAddress(IPC_RX_CHAN),
+ IPC_RX_RELEASE_MASK);
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+int platform_mailbox_send_msg_ptr(const void *msg_ptr)
+{
+ cy_en_ipcdrv_status_t status;
+
+ if (!msg_ptr)
+ return PLATFORM_MAILBOX_INVAL_PARAMS;
+
+ status = Cy_IPC_Drv_SendMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(IPC_TX_CHAN),
+ IPC_TX_NOTIFY_MASK, msg_ptr);
+ if (status != CY_IPC_DRV_SUCCESS) {
+ return PLATFORM_MAILBOX_TX_ERROR;
+ }
+
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+int platform_mailbox_send_msg_data(uint32_t data)
+{
+ cy_en_ipcdrv_status_t status;
+
+ status = Cy_IPC_Drv_SendMsgWord(Cy_IPC_Drv_GetIpcBaseAddress(IPC_TX_CHAN),
+ IPC_TX_NOTIFY_MASK, data);
+ if (status != CY_IPC_DRV_SUCCESS) {
+ return PLATFORM_MAILBOX_TX_ERROR;
+ }
+
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+void platform_mailbox_wait_for_notify(void)
+{
+ uint32_t status;
+
+ while (1) {
+ status = Cy_IPC_Drv_GetInterruptStatusMasked(
+ Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT));
+ status >>= CY_IPC_NOTIFY_SHIFT;
+ if (status & IPC_RX_INT_MASK) {
+ break;
+ }
+ }
+
+ Cy_IPC_Drv_ClearInterrupt(Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT),
+ 0, IPC_RX_INT_MASK);
+}
+
+int platform_ns_ipc_init(void)
+{
+ Cy_IPC_Drv_SetInterruptMask(Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT),
+ 0, IPC_RX_INT_MASK);
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+int tfm_platform_ns_wait_for_s_cpu_ready(void)
+{
+ uint32_t data = 0;
+
+ if (platform_ns_ipc_init() != PLATFORM_MAILBOX_SUCCESS) {
+ return PLATFORM_MAILBOX_INVAL_PARAMS;
+ }
+ while(data != IPC_SYNC_MAGIC)
+ {
+ platform_mailbox_wait_for_notify();
+ platform_mailbox_fetch_msg_data(&data);
+ }
+
+ if (platform_mailbox_send_msg_data(~IPC_SYNC_MAGIC) !=
+ PLATFORM_MAILBOX_SUCCESS) {
+ return PLATFORM_MAILBOX_RX_ERROR;
+ }
+ return PLATFORM_MAILBOX_SUCCESS;
+}
diff --git a/platform/ext/target/psoc64/mailbox/platform_multicore.h b/platform/ext/target/psoc64/mailbox/platform_multicore.h
new file mode 100644
index 0000000000..72e24b622e
--- /dev/null
+++ b/platform/ext/target/psoc64/mailbox/platform_multicore.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _TFM_PLATFORM_MULTICORE_
+#define _TFM_PLATFORM_MULTICORE_
+
+#include <stdint.h>
+#include "cy_device_headers.h"
+
+#define IPC_PSA_CLIENT_CALL_CHAN (8)
+#define IPC_PSA_CLIENT_CALL_INTR_STRUCT (6)
+#define IPC_PSA_CLIENT_CALL_INTR_MASK (1 << IPC_PSA_CLIENT_CALL_CHAN)
+#define IPC_PSA_CLIENT_CALL_NOTIFY_MASK (1 << IPC_PSA_CLIENT_CALL_INTR_STRUCT)
+#define IPC_PSA_CLIENT_CALL_IPC_INTR cpuss_interrupts_ipc_6_IRQn
+
+#define IPC_PSA_CLIENT_REPLY_CHAN (9)
+#define IPC_PSA_CLIENT_REPLY_INTR_STRUCT (5)
+#define IPC_PSA_CLIENT_REPLY_INTR_MASK (1 << IPC_PSA_CLIENT_REPLY_CHAN)
+#define IPC_PSA_CLIENT_REPLY_NOTIFY_MASK (1 << IPC_PSA_CLIENT_REPLY_INTR_STRUCT)
+
+#define IPC_RX_RELEASE_MASK (0)
+
+#define CY_IPC_NOTIFY_SHIFT (16)
+
+#define PSA_CLIENT_CALL_REQ_MAGIC (0xA5CF50C6)
+
+#define NS_MAILBOX_INIT_ENABLE (0xAE)
+#define S_MAILBOX_READY (0xC3)
+
+#define PLATFORM_MAILBOX_SUCCESS (0x0)
+#define PLATFORM_MAILBOX_INVAL_PARAMS (INT32_MIN + 1)
+#define PLATFORM_MAILBOX_TX_ERROR (INT32_MIN + 2)
+#define PLATFORM_MAILBOX_RX_ERROR (INT32_MIN + 3)
+#define PLATFORM_MAILBOX_INIT_ERROR (INT32_MIN + 4)
+
+/* Inter-Processor Communication (IPC) data channel for the Semaphores */
+#define PLATFORM_MAILBOX_IPC_CHAN_SEMA CY_IPC_CHAN_SEMA
+#define MAILBOX_SEMAPHORE_NUM (16)
+
+#define IPC_SYNC_MAGIC 0x7DADE011
+
+/**
+ * \brief Fetch a pointer from mailbox message
+ *
+ * \param[out] msg_ptr The address to write the pointer value to.
+ *
+ * \retval 0 The operation succeeds.
+ * \retval else The operation fails.
+ */
+int platform_mailbox_fetch_msg_ptr(void **msg_ptr);
+
+/**
+ * \brief Fetch a data value from mailbox message
+ *
+ * \param[out] data_ptr The address to write the pointer value to.
+ *
+ * \retval 0 The operation succeeds.
+ * \retval else The operation fails.
+ */
+int platform_mailbox_fetch_msg_data(uint32_t *data_ptr);
+
+/**
+ * \brief Send a pointer via mailbox message
+ *
+ * \param[in] msg_ptr The pointer value to be sent.
+ *
+ * \retval 0 The operation succeeds.
+ * \retval else The operation fails.
+ */
+int platform_mailbox_send_msg_ptr(const void *msg_ptr);
+
+/**
+ * \brief Send a data value via mailbox message
+ *
+ * \param[in] data The data value to be sent
+ *
+ * \retval 0 The operation succeeds.
+ * \retval else The operation fails.
+ */
+int platform_mailbox_send_msg_data(uint32_t data);
+
+/**
+ * \brief Wait for a mailbox notify event.
+ */
+void platform_mailbox_wait_for_notify(void);
+
+/**
+ * \brief IPC initialization
+ *
+ * \retval 0 The operation succeeds.
+ * \retval else The operation fails.
+ */
+int platform_ns_ipc_init(void);
+
+#endif
diff --git a/platform/ext/target/psoc64/mailbox/platform_ns_mailbox.c b/platform/ext/target/psoc64/mailbox/platform_ns_mailbox.c
new file mode 100644
index 0000000000..f1680180c9
--- /dev/null
+++ b/platform/ext/target/psoc64/mailbox/platform_ns_mailbox.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* -------------------------------------- Includes ----------------------------------- */
+#include <limits.h>
+#include <string.h>
+
+#include "cmsis_compiler.h"
+
+#include "cy_ipc_drv.h"
+#include "cy_sysint.h"
+#include "cy_ipc_sema.h"
+
+#include "ns_ipc_config.h"
+#include "tfm_ns_mailbox.h"
+#include "platform_multicore.h"
+
+/* -------------------------------------- HAL API ------------------------------------ */
+
+static void mailbox_ipc_init(void)
+{
+ Cy_IPC_Drv_SetInterruptMask(Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT),
+ 0, IPC_RX_INT_MASK);
+}
+
+int32_t mailbox_notify_peer(void)
+{
+ cy_en_ipcdrv_status_t status;
+
+ status = Cy_IPC_Drv_SendMsgWord(Cy_IPC_Drv_GetIpcBaseAddress(IPC_TX_CHAN),
+ IPC_TX_NOTIFY_MASK,
+ PSA_CLIENT_CALL_REQ_MAGIC);
+
+ if (status == CY_IPC_DRV_SUCCESS) {
+ return MAILBOX_SUCCESS;
+ } else {
+ return MAILBOX_CHAN_BUSY;
+ }
+}
+
+static int32_t mailbox_sema_init(void)
+{
+#if defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ /* semaphore data */
+ static uint32_t tfm_sema;
+
+ if (Cy_IPC_Sema_Init(PLATFORM_MAILBOX_IPC_CHAN_SEMA,
+ sizeof(tfm_sema) * CHAR_BIT,
+ &tfm_sema) != CY_IPC_SEMA_SUCCESS) {
+ return PLATFORM_MAILBOX_INIT_ERROR;
+ }
+#endif
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+int32_t mailbox_hal_init(struct ns_mailbox_queue_t *queue)
+{
+ uint32_t stage;
+
+ if (!queue) {
+ return MAILBOX_INVAL_PARAMS;
+ }
+
+ /* Init semaphores used for critical sections */
+ if (mailbox_sema_init() != PLATFORM_MAILBOX_SUCCESS)
+ return MAILBOX_INIT_ERROR;
+
+ /*
+ * FIXME
+ * Further verification of mailbox queue address may be required according
+ * to diverse NSPE implementations.
+ */
+
+ mailbox_ipc_init();
+
+ /*
+ * Wait until SPE mailbox library is ready to receive NSPE mailbox queue
+ * address.
+ */
+ while (1) {
+ platform_mailbox_wait_for_notify();
+
+ platform_mailbox_fetch_msg_data(&stage);
+ if (stage == NS_MAILBOX_INIT_ENABLE) {
+ break;
+ }
+ }
+
+ /* Send out the address */
+ platform_mailbox_send_msg_ptr(queue);
+
+ /* Wait until SPE mailbox service is ready */
+ while (1) {
+ platform_mailbox_wait_for_notify();
+
+ platform_mailbox_fetch_msg_data(&stage);
+ if (stage == S_MAILBOX_READY) {
+ break;
+ }
+ }
+
+ return MAILBOX_SUCCESS;
+}
+
+void mailbox_enter_critical(void)
+{
+ while (Cy_IPC_Sema_Set(MAILBOX_SEMAPHORE_NUM, false) !=
+ CY_IPC_SEMA_SUCCESS) {
+ }
+}
+
+void mailbox_exit_critical(void)
+{
+ while (Cy_IPC_Sema_Clear(MAILBOX_SEMAPHORE_NUM, false) !=
+ CY_IPC_SEMA_SUCCESS) {
+ }
+}
diff --git a/platform/ext/target/psoc64/mailbox/platform_spe_mailbox.c b/platform/ext/target/psoc64/mailbox/platform_spe_mailbox.c
new file mode 100644
index 0000000000..778dbf0417
--- /dev/null
+++ b/platform/ext/target/psoc64/mailbox/platform_spe_mailbox.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* -------------------------------------- Includes ----------------------------------- */
+#include "cmsis.h"
+#include "cmsis_compiler.h"
+
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_ipc_drv.h"
+#include "cy_sysint.h"
+#include "cy_ipc_sema.h"
+
+#include "spe_ipc_config.h"
+#include "tfm_spe_mailbox.h"
+#include "platform_multicore.h"
+
+/* -------------------------------------- HAL API ------------------------------------ */
+
+int32_t tfm_mailbox_notify_peer(void)
+{
+ return MAILBOX_SUCCESS;
+}
+
+static void mailbox_ipc_config(void)
+{
+ Cy_SysInt_SetIntSource(PSA_CLIENT_CALL_NVIC_IRQn, PSA_CLIENT_CALL_IPC_INTR);
+
+ NVIC_SetPriority(PSA_CLIENT_CALL_NVIC_IRQn, PSA_CLIENT_CALL_IRQ_PRIORITY);
+
+ NVIC_EnableIRQ(PSA_CLIENT_CALL_NVIC_IRQn);
+}
+
+static int32_t tfm_mailbox_sema_init(void)
+{
+#if defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ if (Cy_IPC_Sema_Init(PLATFORM_MAILBOX_IPC_CHAN_SEMA, 0,
+ NULL) != CY_IPC_SEMA_SUCCESS) {
+ return PLATFORM_MAILBOX_INIT_ERROR;
+ }
+#endif
+
+ if (MAILBOX_SEMAPHORE_NUM >= Cy_IPC_Sema_GetMaxSems()) {
+ return PLATFORM_MAILBOX_INIT_ERROR;
+ }
+
+ /* TODO Check that the semaphore data is in NS memory */
+
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+int32_t tfm_mailbox_hal_init(struct secure_mailbox_queue_t *s_queue)
+{
+ struct ns_mailbox_queue_t *ns_queue = NULL;
+
+ /* Init semaphores used for critical sections */
+ if (tfm_mailbox_sema_init() != PLATFORM_MAILBOX_SUCCESS)
+ return MAILBOX_INIT_ERROR;
+
+ /* Inform NSPE that NSPE mailbox initialization can start */
+ platform_mailbox_send_msg_data(NS_MAILBOX_INIT_ENABLE);
+
+ platform_mailbox_wait_for_notify();
+
+ /* Receive the address of NSPE mailbox queue */
+ platform_mailbox_fetch_msg_ptr((void **)&ns_queue);
+
+ /*
+ * FIXME
+ * Necessary sanity check of the address of NPSE mailbox queue should
+ * be implemented there.
+ */
+
+ s_queue->ns_queue = ns_queue;
+
+ mailbox_ipc_config();
+
+ /* Inform NSPE that SPE mailbox service is ready */
+ platform_mailbox_send_msg_data(S_MAILBOX_READY);
+
+ return MAILBOX_SUCCESS;
+}
+
+void tfm_mailbox_enter_critical(void)
+{
+ while (CY_IPC_SEMA_SUCCESS !=
+ Cy_IPC_Sema_Set(MAILBOX_SEMAPHORE_NUM, false))
+ {
+ }
+}
+
+void tfm_mailbox_exit_critical(void)
+{
+ while (CY_IPC_SEMA_SUCCESS !=
+ Cy_IPC_Sema_Clear(MAILBOX_SEMAPHORE_NUM, false))
+ {
+ }
+}
diff --git a/platform/ext/target/psoc64/mailbox/spe_ipc_config.h b/platform/ext/target/psoc64/mailbox/spe_ipc_config.h
new file mode 100644
index 0000000000..bbb2d76ada
--- /dev/null
+++ b/platform/ext/target/psoc64/mailbox/spe_ipc_config.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _IPC_CONFIG_H_
+#define _IPC_CONFIG_H_
+
+#include "platform_multicore.h"
+#include "cy_device_headers.h"
+
+#define IPC_RX_CHAN IPC_PSA_CLIENT_CALL_CHAN
+#define IPC_RX_INTR_STRUCT IPC_PSA_CLIENT_CALL_INTR_STRUCT
+#define IPC_RX_INT_MASK IPC_PSA_CLIENT_CALL_INTR_MASK
+
+#define IPC_TX_CHAN IPC_PSA_CLIENT_REPLY_CHAN
+#define IPC_TX_NOTIFY_MASK IPC_PSA_CLIENT_REPLY_NOTIFY_MASK
+
+#define PSA_CLIENT_CALL_NVIC_IRQn NvicMux9_IRQn
+#define PSA_CLIENT_CALL_IRQ_PRIORITY 3
+#define PSA_CLIENT_CALL_IPC_INTR IPC_PSA_CLIENT_CALL_IPC_INTR
+
+#endif
diff --git a/platform/ext/target/psoc64/partition/flash_layout.h b/platform/ext/target/psoc64/partition/flash_layout.h
new file mode 100644
index 0000000000..960feca776
--- /dev/null
+++ b/platform/ext/target/psoc64/partition/flash_layout.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __FLASH_LAYOUT_H__
+#define __FLASH_LAYOUT_H__
+
+/* Flash layout with BL2:
+ *
+ * TBD
+ *
+ *
+ * Flash layout if BL2 not defined:
+ *
+ * 0x1000_0000 Non-secure image primary (256 KB)
+ * 0x1004_0000 Secure/Non-secure image secondary (256 KB)
+ * Note that only one image can be upgraded per boot
+ * 0x1008_0000 Secure image primary (256 KB)
+ * 0x100c_0000 Secure Storage Area (20 KB)
+ * 0x100c_5000 NV counters area (24 Bytes)
+ * 0x100c_5018 Unused (almost 44 KB)
+ * 0x100d_0000 Reserved (192 KB)
+ *
+ */
+
+#define MAX(X, Y) (((X) > (Y)) ? (X) : (Y))
+
+/* This header file is included from linker scatter file as well, where only a
+ * limited C constructs are allowed. Therefore it is not possible to include
+ * here the platform_base_address.h to access flash related defines. To resolve
+ * this some of the values are redefined here with different names, these are
+ * marked with comment.
+ */
+
+/* The size of S partition */
+#define FLASH_S_PARTITION_SIZE 0x40000 /* 256 KB */
+/* The size of NS partition */
+#define FLASH_NS_PARTITION_SIZE 0x40000 /* 256 KB */
+
+/*
+ * Each FLASH_AREA_IMAGE contains NS and S partitions.
+ * See Flash layout above.
+ */
+#define FLASH_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \
+ FLASH_NS_PARTITION_SIZE)
+#define FLASH_MAX_PARTITION_SIZE MAX(FLASH_S_PARTITION_SIZE, \
+ FLASH_NS_PARTITION_SIZE)
+
+/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */
+#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x200) /* 512 B */
+/* Same as FLASH0_SIZE */
+#define FLASH_TOTAL_SIZE (0x00100000) /* 1 MB */
+
+/* Flash layout info for BL2 bootloader */
+#define FLASH_BASE_ADDRESS (0x10000000U) /* same as FLASH0_BASE */
+
+#ifdef BL2
+/* Offset and size definitions of the flash partitions that are handled by the
+ * bootloader. The image swapping is done between IMAGE_PRIMARY and
+ * IMAGE_SECONDARY.
+ * SCRATCH is used as a temporary storage during image swapping.
+ */
+#define FLASH_AREA_BL2_OFFSET (0x0)
+#define FLASH_AREA_BL2_SIZE (0x20000) /* 128 kB */
+
+#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)
+/* Secure + Non-secure image primary slot */
+#define FLASH_AREA_0_ID (1)
+#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + \
+ FLASH_AREA_BL2_SIZE)
+#define FLASH_AREA_0_SIZE FLASH_PARTITION_SIZE
+
+/* Secure + Non-secure secondary slot */
+#define FLASH_AREA_2_ID (FLASH_AREA_0_ID + 1)
+#define FLASH_AREA_2_OFFSET (FLASH_AREA_0_OFFSET + \
+ FLASH_AREA_0_SIZE)
+#define FLASH_AREA_2_SIZE FLASH_PARTITION_SIZE
+
+/* Scratch area */
+#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1)
+#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_2_OFFSET + \
+ FLASH_AREA_2_SIZE)
+#define FLASH_AREA_SCRATCH_SIZE (0x8000) /* 32 KB */
+
+/* Maximum number of status entries supported by the bootloader. */
+#define BOOT_STATUS_MAX_ENTRIES MAX(2, FLASH_PARTITION_SIZE / \
+ FLASH_AREA_SCRATCH_SIZE)
+
+/** Maximum number of image sectors supported by the bootloader. */
+#define BOOT_MAX_IMG_SECTORS (FLASH_PARTITION_SIZE / \
+ FLASH_AREA_IMAGE_SECTOR_SIZE)
+#elif (MCUBOOT_IMAGE_NUMBER == 2)
+
+/* Secure image primary slot */
+#define FLASH_AREA_0_ID (1)
+#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + \
+ FLASH_AREA_BL2_SIZE)
+#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE)
+
+/* Non-secure image primary slot */
+#define FLASH_AREA_1_ID (FLASH_AREA_0_ID + 1)
+#define FLASH_AREA_1_OFFSET (FLASH_AREA_0_OFFSET + \
+ FLASH_AREA_0_SIZE)
+#define FLASH_AREA_1_SIZE (FLASH_NS_PARTITION_SIZE)
+
+/* Secure image secondary slot */
+#define FLASH_AREA_2_ID (FLASH_AREA_1_ID + 1)
+#define FLASH_AREA_2_OFFSET (FLASH_AREA_1_OFFSET + \
+ FLASH_AREA_1_SIZE)
+#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE)
+
+/* Non-secure image secondary slot */
+#define FLASH_AREA_3_ID (FLASH_AREA_2_ID + 1)
+#define FLASH_AREA_3_OFFSET (FLASH_AREA_2_OFFSET + \
+ FLASH_AREA_2_SIZE)
+#define FLASH_AREA_3_SIZE (FLASH_NS_PARTITION_SIZE)
+
+/* Scratch area */
+#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_3_ID + 1)
+#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_3_OFFSET + \
+ FLASH_AREA_3_SIZE)
+#define FLASH_AREA_SCRATCH_SIZE (0x8000) /* 32 KB */
+
+/* The maximum number of status entries supported by the bootloader. */
+/* The maximum number of status entries must be at least 2. For more
+ * information see the MCUBoot issue:
+ * https://github.com/JuulLabs-OSS/mcuboot/issues/427.
+ */
+#define BOOT_STATUS_MAX_ENTRIES MAX(2, FLASH_MAX_PARTITION_SIZE / \
+ FLASH_AREA_SCRATCH_SIZE)
+/* Maximum number of image sectors supported by the bootloader. */
+#define BOOT_MAX_IMG_SECTORS (FLASH_MAX_PARTITION_SIZE / \
+ FLASH_AREA_IMAGE_SECTOR_SIZE)
+#else /* MCUBOOT_IMAGE_NUMBER > 2 */
+#error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!"
+#endif /* MCUBOOT_IMAGE_NUMBER */
+
+#else /* BL2 */
+/* SST area follows scratch area */
+#define FLASH_AREA_SCRATCH_OFFSET (SECURE_IMAGE_OFFSET + \
+ FLASH_S_PARTITION_SIZE)
+#define FLASH_AREA_SCRATCH_SIZE (0) /* None */
+#endif /* BL2 */
+
+#define FLASH_SST_AREA_OFFSET (FLASH_AREA_SCRATCH_OFFSET + \
+ FLASH_AREA_SCRATCH_SIZE)
+#define FLASH_SST_AREA_SIZE (0x5000) /* 20 KB */
+
+#define FLASH_NV_COUNTERS_AREA_OFFSET (FLASH_SST_AREA_OFFSET + \
+ FLASH_SST_AREA_SIZE)
+#define FLASH_NV_COUNTERS_AREA_SIZE (0x18) /* 24 Bytes */
+
+/* Offset and size definition in flash area, used by assemble.py */
+#ifdef BL2
+#define SECURE_IMAGE_OFFSET 0x0
+#else
+#define SECURE_IMAGE_OFFSET (NON_SECURE_IMAGE_OFFSET + \
+ FLASH_NS_PARTITION_SIZE + \
+ FLASH_MAX_PARTITION_SIZE)
+#endif
+#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE
+
+#ifdef BL2
+#define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + \
+ SECURE_IMAGE_MAX_SIZE)
+#else
+#define NON_SECURE_IMAGE_OFFSET 0x0
+#endif
+#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE
+
+/* Flash device name used by BL2 and SST
+ * Name is defined in flash driver file: Driver_Flash.c
+ */
+#define FLASH_DEV_NAME Driver_FLASH0
+
+/* Secure Storage (SST) Service definitions
+ * Note: Further documentation of these definitions can be found in the
+ * TF-M SST Integration Guide.
+ */
+#define SST_FLASH_DEV_NAME Driver_FLASH0
+
+/* In this target the CMSIS driver requires only the offset from the base
+ * address instead of the full memory address.
+ */
+#define SST_FLASH_AREA_ADDR FLASH_SST_AREA_OFFSET
+/* Dedicated flash area for SST */
+#define SST_FLASH_AREA_SIZE FLASH_SST_AREA_SIZE
+#define SST_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
+/* Number of SST_SECTOR_SIZE per block */
+#define SST_SECTORS_PER_BLOCK 0x8
+/* Specifies the smallest flash programmable unit in bytes */
+#define SST_FLASH_PROGRAM_UNIT 0x1
+/* The maximum asset size to be stored in the SST area */
+#define SST_MAX_ASSET_SIZE 2048
+/* The maximum number of assets to be stored in the SST area */
+#define SST_NUM_ASSETS 10
+
+/* NV Counters definitions */
+#define TFM_NV_COUNTERS_AREA_ADDR FLASH_NV_COUNTERS_AREA_OFFSET
+#define TFM_NV_COUNTERS_AREA_SIZE FLASH_NV_COUNTERS_AREA_SIZE
+#define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET
+#define TFM_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
+
+/* Use Flash to store Code data */
+#define S_ROM_ALIAS_BASE (0x10000000)
+#define NS_ROM_ALIAS_BASE (0x10000000)
+
+/* Use SRAM to store RW data */
+#define S_RAM_ALIAS_BASE (0x08000000)
+#define NS_RAM_ALIAS_BASE (0x08000000)
+
+#endif /* __FLASH_LAYOUT_H__ */
diff --git a/platform/ext/target/psoc64/partition/region_defs.h b/platform/ext/target/psoc64/partition/region_defs.h
new file mode 100644
index 0000000000..9138bdd0d2
--- /dev/null
+++ b/platform/ext/target/psoc64/partition/region_defs.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2017-2019 ARM Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __REGION_DEFS_H__
+#define __REGION_DEFS_H__
+
+#include "flash_layout.h"
+
+#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE
+/* 2KB of RAM (at the end of the SRAM) are reserved for system use. Using
+ * this memory region for other purposes will lead to unexpected behavior.
+ * 94KB of RAM (just before the memory reserved for system use) are
+ * allocated and protected by Cypress Bootloader */
+#define TOTAL_RAM_SIZE (0x00030000) /* CY_SRAM0_SIZE - 96KB */
+
+#define BL2_HEAP_SIZE 0x0001000
+#define BL2_MSP_STACK_SIZE 0x0001000
+
+#define S_HEAP_SIZE 0x0001000
+#define S_MSP_STACK_SIZE_INIT 0x0000400
+#define S_MSP_STACK_SIZE 0x0000800
+#define S_PSP_STACK_SIZE 0x0000800
+
+#define NS_HEAP_SIZE 0x0001000
+#define NS_MSP_STACK_SIZE 0x0000400
+#define NS_PSP_STACK_SIZE 0x0000C00
+
+/* Relocation of vectors to RAM support */
+/* #define RAM_VECTORS_SUPPORT */
+
+/*
+ * This size of buffer is big enough to store an attestation
+ * token produced by initial attestation service
+ */
+#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE 0x250
+
+/*
+ * MPC granularity is 128 KB on AN519 MPS2 FPGA image. Alignment
+ * of partitions is defined in accordance with this constraint.
+ */
+
+#ifdef BL2
+#ifndef LINK_TO_SECONDARY_PARTITION
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET)
+#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET)
+#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET + \
+ FLASH_S_PARTITION_SIZE)
+#else
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET)
+#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET)
+#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET + \
+ FLASH_S_PARTITION_SIZE)
+#endif /* !LINK_TO_SECONDARY_PARTITION */
+#else
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET SECURE_IMAGE_OFFSET
+#define NS_IMAGE_PRIMARY_PARTITION_OFFSET NON_SECURE_IMAGE_OFFSET
+#endif /* BL2 */
+
+/* TFM PSoC6 CY8CKIT_064 RAM layout:
+ *
+ * 0x0800_0000 Non-secure data (NS_DATA_SIZE, 63KB)
+ * 0x0800_FC00 Shared memory (NS_DATA_SHARED_SIZE, 1KB)
+ * 0x0801_0000 Secure unprivileged data (S_UNPRIV_DATA_SIZE, 32KB)
+ * 0x0801_8000 Secure priviliged data (S_PRIV_DATA_SIZE, 92KB)
+ * 0x0802_F000 Secure priv code executable from RAM (S_RAM_CODE_SIZE, 4KB)
+ * 0x0803_0000 System reserved memory (96KB)
+ * 0x0804_8000 End of RAM
+ */
+
+/*
+ * Boot partition structure if MCUBoot is used:
+ * 0x0_0000 Bootloader header
+ * 0x0_0400 Image area
+ * 0x1_FC00 Trailer
+ */
+/* Image code size is the space available for the software binary image.
+ * It is less than the FLASH_S_PARTITION_SIZE and FLASH_NS_PARTITION_SIZE
+ * because we reserve space for the image header and trailer introduced by the
+ * bootloader.
+ */
+#ifdef BL2
+#define BL2_HEADER_SIZE (0x400)
+#define BL2_TRAILER_SIZE (0x400)
+#else
+/* Even though TFM BL2 is excluded from the build,
+ * CY BL built externally is used and it needs offsets for header and trailer
+ * to be taken in account.
+ * */
+#define BL2_HEADER_SIZE (0x400)
+#define BL2_TRAILER_SIZE (0x400)
+
+#endif /* BL2 */
+
+#define IMAGE_S_CODE_SIZE \
+ (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
+#define IMAGE_NS_CODE_SIZE \
+ (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
+
+/* Alias definitions for secure and non-secure areas*/
+#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x))
+#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
+
+#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x))
+#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x))
+
+/* Secure regions */
+#define S_IMAGE_PRIMARY_AREA_OFFSET \
+ (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
+#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
+#define S_CODE_SIZE IMAGE_S_CODE_SIZE
+#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
+
+#define S_DATA_START (S_RAM_ALIAS(NS_DATA_SIZE))
+#define S_UNPRIV_DATA_SIZE 0x8000
+#define S_PRIV_DATA_SIZE 0x17000
+/* Reserve 4KB for RAM-based executable code */
+#define S_RAM_CODE_SIZE 0x1000
+
+/* Secure data area */
+#define S_DATA_SIZE (S_UNPRIV_DATA_SIZE + S_PRIV_DATA_SIZE + S_RAM_CODE_SIZE)
+#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
+
+/* We need the privileged data area to be aligned so that an SMPU
+ * region can cover it.
+ */
+/* TODO It would be nice to figure this out automatically.
+ * In theory, in the linker script, we could determine the amount
+ * of secure data space available after all the unprivileged data,
+ * round that down to a power of 2 to get the actual size we want
+ * to use for privileged data, and then determine this value from
+ * that. We'd also potentially have to update the configs for SMPU9
+ * and SMPU10.
+ * Leave the SMPU alignment check in SMPU configuration file.
+ */
+#define S_DATA_PRIV_OFFSET (NS_DATA_SIZE + S_UNPRIV_DATA_SIZE)
+#define S_DATA_PRIV_START S_RAM_ALIAS(S_DATA_PRIV_OFFSET)
+
+/* Reserve area for RAM-based executable code right after secure unprivilaged
+ * and privilaged data areas*/
+#define S_RAM_CODE_START (S_DATA_START + S_UNPRIV_DATA_SIZE + S_PRIV_DATA_SIZE)
+
+/* Non-secure regions */
+#define NS_IMAGE_PRIMARY_AREA_OFFSET \
+ (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
+#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET))
+#define NS_CODE_SIZE IMAGE_NS_CODE_SIZE
+#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
+
+#define NS_DATA_START (S_RAM_ALIAS(0))
+#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE)
+#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1)
+
+/* Shared memory */
+#define NS_DATA_SHARED_SIZE 0x400
+#define NS_DATA_SHARED_START (NS_DATA_START + NS_DATA_SIZE - \
+ NS_DATA_SHARED_SIZE)
+#define NS_DATA_SHARED_LIMIT (NS_DATA_SHARED_START + NS_DATA_SHARED_SIZE - 1)
+
+/* Shared variables addresses */
+/* ipcWaitMessageStc, cy_flash.c */
+#define IPC_WAIT_MESSAGE_STC_ADDR NS_DATA_SHARED_START
+#define IPC_WAIT_MESSAGE_STC_SIZE 4
+
+/* NS partition information is used for MPC and SAU configuration */
+#define NS_PARTITION_START \
+ (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
+
+#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE)
+
+/* Secondary partition for new images in case of firmware upgrade */
+#define SECONDARY_PARTITION_START \
+ (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET))
+
+#define SECONDARY_PARTITION_SIZE FLASH_PARTITION_SIZE
+
+#ifdef BL2
+/* Bootloader regions */
+#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET))
+#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE)
+#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1)
+
+#define BL2_DATA_START (S_RAM_ALIAS(S_DATA_PRIV_OFFSET))
+#define BL2_DATA_SIZE (S_PRIV_DATA_SIZE)
+#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1)
+#endif /* BL2 */
+
+/* Shared data area between bootloader and runtime firmware.
+ * Shared data area is allocated at the beginning of the privileged data area,
+ * it is overlapping with TF-M Secure code's MSP stack
+ */
+#define BOOT_TFM_SHARED_DATA_BASE (S_RAM_ALIAS(S_DATA_PRIV_OFFSET))
+#define BOOT_TFM_SHARED_DATA_SIZE 0x400
+
+#endif /* __REGION_DEFS_H__ */
+
diff --git a/platform/ext/target/psoc64/pc_config.h b/platform/ext/target/psoc64/pc_config.h
new file mode 100644
index 0000000000..311a1c4a5c
--- /dev/null
+++ b/platform/ext/target/psoc64/pc_config.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __PC_CONFIG_H__
+#define __PC_CONFIG_H__
+
+/* Which PC is used for what */
+/* PC=0 : romboot (CM0+) */
+/* PC=1 : BL2/SPM (CM0+) */
+#define CY_PROT_SPM_DEFAULT CY_PROT_PC1
+/* PC=2 : unused (secure) */
+/* PC=3 : unused (secure) */
+/* PC=4 : unused (non-secure) */
+/* PC=5 : unused (non-secure) */
+/* PC=6 : non-secure code (CM4) */
+#define CY_PROT_HOST_DEFAULT CY_PROT_PC6
+/* PC=7 : Test Controller */
+#define CY_PROT_TC CY_PROT_PC7
+
+#define ONLY_BL2_SPM_MASK CY_PROT_PCMASK1
+#define SECURE_PCS_MASK (CY_PROT_PCMASK1 | CY_PROT_PCMASK2 | CY_PROT_PCMASK3)
+#define HOST_PCS_MASK (CY_PROT_PCMASK4 | CY_PROT_PCMASK5 | CY_PROT_PCMASK6)
+#define TC_PC_MASK CY_PROT_PCMASK7
+#define ALL_PCS_EXCEPT_TC_MASK (CY_PROT_PCMASK1 | CY_PROT_PCMASK2 | CY_PROT_PCMASK3 | \
+ CY_PROT_PCMASK4 | CY_PROT_PCMASK5 | CY_PROT_PCMASK6)
+#define ALL_PCS_MASK (CY_PROT_PCMASK1 | CY_PROT_PCMASK2 | CY_PROT_PCMASK3 | \
+ CY_PROT_PCMASK4 | CY_PROT_PCMASK5 | CY_PROT_PCMASK6 | CY_PROT_PCMASK7)
+#endif /* __PC_CONFIG_H__ */
+
diff --git a/platform/ext/target/psoc64/ppu_config.h b/platform/ext/target/psoc64/ppu_config.h
new file mode 100644
index 0000000000..e29d83167d
--- /dev/null
+++ b/platform/ext/target/psoc64/ppu_config.h
@@ -0,0 +1,389 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __PPU_CONFIG_H__
+#define __PPU_CONFIG_H__
+
+/* PPU configs */
+
+/* The majority will be configured in similar ways */
+#define NON_SECURE_READ_ONLY_CONFIG { \
+ .userPermission = CY_PROT_PERM_R, \
+ .privPermission = CY_PROT_PERM_R, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = ALL_PCS_MASK, \
+}
+#define NON_SECURE_READ_WRITE_CONFIG { \
+ .userPermission = CY_PROT_PERM_RW, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = ALL_PCS_MASK, \
+}
+#define NON_SECURE_PRIV_ONLY_CONFIG { \
+ .userPermission = CY_PROT_PERM_DISABLED, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = ALL_PCS_MASK, \
+}
+#define NON_SECURE_EXCEPT_TC_READ_WRITE_CONFIG { \
+ .userPermission = CY_PROT_PERM_RW, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = ALL_PCS_EXCEPT_TC_MASK, \
+}
+#define SECURE_READ_ONLY_CONFIG { \
+ .userPermission = CY_PROT_PERM_R, \
+ .privPermission = CY_PROT_PERM_R, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SECURE_READ_WRITE_CONFIG { \
+ .userPermission = CY_PROT_PERM_R, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SECURE_PRIV_ONLY_CONFIG { \
+ .userPermission = CY_PROT_PERM_DISABLED, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+
+/* Actual configs for each PPU */
+#define PPU_PR0_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_PR0_SLAVE_CONFIG { \
+ .address = (uint32_t *)CPUSS_BASE, \
+ .regionSize = CY_PROT_SIZE_2KB, \
+ .subregions = CY_PROT_SUBREGION_DIS2 | CY_PROT_SUBREGION_DIS1 | CY_PROT_SUBREGION_DIS0, \
+ .userPermission = CY_PROT_PERM_R, \
+ .privPermission = CY_PROT_PERM_R, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+
+#define PPU_PR1_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_PR1_SLAVE_CONFIG { \
+ .address = (uint32_t *)(CPUSS_BASE + 0x8000), \
+ .regionSize = CY_PROT_SIZE_32KB, \
+ .subregions = ALL_ENABLED, \
+ .userPermission = CY_PROT_PERM_R, \
+ .privPermission = CY_PROT_PERM_R, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+
+#define PPU_PR2_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_PR2_SLAVE_CONFIG { \
+ .address = (uint32_t *)EFUSE_BASE, \
+ .regionSize = CY_PROT_SIZE_2KB, \
+ .subregions = ALL_ENABLED, \
+ .userPermission = CY_PROT_PERM_DISABLED, \
+ .privPermission = CY_PROT_PERM_DISABLED, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = ALL_PCS_MASK, \
+}
+
+#define PPU_PR3_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_PR3_SLAVE_CONFIG { \
+ .address = (uint32_t *)(EFUSE_BASE + 0x800), \
+ .regionSize = CY_PROT_SIZE_256B, \
+ .subregions = CY_PROT_SUBREGION_DIS1 | CY_PROT_SUBREGION_DIS0, \
+ .userPermission = CY_PROT_PERM_DISABLED, \
+ .privPermission = CY_PROT_PERM_DISABLED, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = ALL_PCS_MASK, \
+}
+
+#define PPU_PR4_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_PR4_SLAVE_CONFIG { \
+ .address = (uint32_t *)PERI_PPU_GR0, \
+ .regionSize = CY_PROT_SIZE_1KB, \
+ .subregions = ALL_ENABLED, \
+ .userPermission = CY_PROT_PERM_DISABLED, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+
+/* PERI.PERI */
+#define PPU_GR0_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_GR0_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_GR1_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_GR1_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_GR2_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_GR2_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_GR3_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_GR3_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_GR4_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_GR4_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_GR6_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_GR6_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_GR9_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_GR9_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_GR10_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_GR10_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_PERI_GR1_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_SL_PERI_GR1_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+/* CUPSS-M4.CRYPTO */
+#define PPU_SL_CRYPTO_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_SL_CRYPTO_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_SL_PERI_GR2_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_SL_PERI_GR2_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+/* CPUSS-M4.CPUSS */
+#define PPU_SL_CPUSS_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_SL_CPUSS_SLAVE_CONFIG NON_SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_SL_FAULT_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_FAULT_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+/* CPUSS-M4.IPC */
+#define PPU_SL_IPC_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_SL_IPC_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+/* CPUSS-M4.PROT */
+#define PPU_SL_PROT_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_SL_PROT_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+/* Flash controller */
+#define PPU_SL_FLASHC_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_SL_FLASHC_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+/* SRSS.SRSS */
+#define PPU_SL_SRSS_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_SL_SRSS_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_DW0_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_DW0_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_DW1_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_SL_DW1_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_SL_EFUSE_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_SL_EFUSE_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_PROFILE_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_PROFILE_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+/* CM0+ SysCall */
+#define PPU_RG_IPC_STRUCT0_MASTER_CONFIG SECURE_READ_ONLY_CONFIG
+#define PPU_RG_IPC_STRUCT0_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+/* CM4 SysCall */
+#define PPU_RG_IPC_STRUCT1_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_RG_IPC_STRUCT1_SLAVE_CONFIG NON_SECURE_EXCEPT_TC_READ_WRITE_CONFIG
+
+/* DAP SysCall */
+#define PPU_RG_IPC_STRUCT2_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_RG_IPC_STRUCT2_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_RG_IPC_STRUCT3_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_IPC_STRUCT3_SLAVE_CONFIG NON_SECURE_EXCEPT_TC_READ_WRITE_CONFIG
+
+#define PPU_RG_IPC_STRUCT4_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_IPC_STRUCT4_SLAVE_CONFIG NON_SECURE_EXCEPT_TC_READ_WRITE_CONFIG
+
+#define PPU_RG_IPC_STRUCT5_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_IPC_STRUCT5_SLAVE_CONFIG NON_SECURE_EXCEPT_TC_READ_WRITE_CONFIG
+
+#define PPU_RG_IPC_STRUCT7_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_RG_IPC_STRUCT7_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_RG_IPC_STRUCT6_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_IPC_STRUCT6_SLAVE_CONFIG NON_SECURE_EXCEPT_TC_READ_WRITE_CONFIG
+
+/* CM0+ NMI */
+#define PPU_RG_IPC_INTR_STRUCT0_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_RG_IPC_INTR_STRUCT0_SLAVE_CONFIG { \
+ .userPermission = CY_PROT_PERM_RW, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = 0, \
+}
+
+#define PPU_RG_IPC_INTR_STRUCT1_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_IPC_INTR_STRUCT1_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_RG_IPC_INTR_STRUCT2_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_IPC_INTR_STRUCT2_SLAVE_CONFIG NON_SECURE_EXCEPT_TC_READ_WRITE_CONFIG
+
+#define PPU_RG_IPC_INTR_STRUCT3_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_RG_IPC_INTR_STRUCT3_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_RG_IPC_INTR_STRUCT4_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_RG_IPC_INTR_STRUCT4_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_RG_IPC_INTR_STRUCT5_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_RG_IPC_INTR_STRUCT5_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_RG_IPC_INTR_STRUCT6_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_RG_IPC_INTR_STRUCT6_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_RG_IPC_INTR_STRUCT7_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_RG_IPC_INTR_STRUCT7_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_RG_DW0_DW_CH_STRUCT0_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_RG_DW0_DW_CH_STRUCT0_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_RG_DW0_DW_CH_STRUCT1_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_RG_DW0_DW_CH_STRUCT1_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_RG_DW0_DW_CH_STRUCT2_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_RG_DW0_DW_CH_STRUCT2_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_RG_DW0_DW_CH_STRUCT3_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_RG_DW0_DW_CH_STRUCT3_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_RG_DW1_DW_CH_STRUCT0_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_DW1_DW_CH_STRUCT0_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_RG_DW1_DW_CH_STRUCT1_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_DW1_DW_CH_STRUCT1_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_RG_DW1_DW_CH_STRUCT2_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_DW1_DW_CH_STRUCT2_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_RG_DW1_DW_CH_STRUCT3_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_DW1_DW_CH_STRUCT3_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_RG_SMPU_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_SMPU_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_RG_MPU_CM0P_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_MPU_CM0P_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_RG_MPU_CRYPTO_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_MPU_CRYPTO_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_RG_MPU_CM4_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_RG_MPU_CM4_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_RG_MPU_TC_MASTER_CONFIG SECURE_READ_WRITE_CONFIG
+#define PPU_RG_MPU_TC_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_SL_PERI_GR3_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_SL_PERI_GR3_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_HSIOM_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_HSIOM_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_GPIO_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_GPIO_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_SMARTIO_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_SMARTIO_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_UDB_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_UDB_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_LPCOMP_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_LPCOMP_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_CSD_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_CSD_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_TCPWM0_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_TCPWM0_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_TCPWM1_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_TCPWM1_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_LCD_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_LCD_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_BLE_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_BLE_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_USBFS_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_USBFS_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_PERI_GR4_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_SL_PERI_GR4_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_SMIF_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_SMIF_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_PERI_GR6_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_SL_PERI_GR6_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_SCB0_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_SCB0_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_SCB1_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_SCB1_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_SCB2_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_SCB2_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_SCB3_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_SCB3_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_SCB4_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_SCB4_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_SCB5_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_SCB5_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_SCB6_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_SCB6_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_SCB7_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_SCB7_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_SCB8_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_SCB8_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_PERI_GR9_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_SL_PERI_GR9_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_PASS_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_PASS_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_PERI_GR10_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_SL_PERI_GR10_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_I2S_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_I2S_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#define PPU_SL_PDM_MASTER_CONFIG NON_SECURE_READ_WRITE_CONFIG
+#define PPU_SL_PDM_SLAVE_CONFIG NON_SECURE_READ_WRITE_CONFIG
+
+#endif /* __PPU_CONFIG_H__ */
diff --git a/platform/ext/target/psoc64/security/keys/readme.rst b/platform/ext/target/psoc64/security/keys/readme.rst
new file mode 100644
index 0000000000..de80f3d16d
--- /dev/null
+++ b/platform/ext/target/psoc64/security/keys/readme.rst
@@ -0,0 +1,4 @@
+Signing keys:
+
+MCUBOOT_CM0P_KEY.json - private OEM key for signing CM0P image
+USERAPP_CM4_KEY.json - private OEM key for signing CM4 image
diff --git a/platform/ext/target/psoc64/security/policy_dual_stage_CM0p_CM4.json b/platform/ext/target/psoc64/security/policy_dual_stage_CM0p_CM4.json
new file mode 100644
index 0000000000..71c539ddc6
--- /dev/null
+++ b/platform/ext/target/psoc64/security/policy_dual_stage_CM0p_CM4.json
@@ -0,0 +1,175 @@
+{
+ "debug" :
+ {
+ "m0p" : {
+ "permission" : "enabled",
+ "control" : "firmware",
+ "key" : 5
+ },
+ "m4" : {
+ "permission" : "allowed",
+ "control" : "firmware",
+ "key" : 5
+ },
+ "system" : {
+ "permission" : "enabled",
+ "control" : "firmware",
+ "key" : 5,
+ "syscall": true,
+ "mmio": true,
+ "flash": true,
+ "workflash": true,
+ "sflash": true,
+ "sram": true
+ },
+ "rma" : {
+ "permission" : "allowed",
+ "destroy_fuses" : [
+ {
+ "start" : 888,
+ "size" : 136
+ },
+ {
+ "start" : 648,
+ "size" : 104
+ }
+ ],
+ "destroy_flash" : [
+ {
+ "start" : 268435456,
+ "size" : 851968
+ },
+ {
+ "start" : 269483520,
+ "size" : 16
+ }
+ ],
+ "key" : 5
+ }
+ },
+ "wounding" :
+ {
+ },
+ "boot_upgrade" :
+ {
+ "firmware": [
+ {
+ "boot_auth": [
+ 3
+ ],
+ "id": 0,
+ "launch": 1,
+ "monotonic": 0,
+ "smif_id": 0,
+ "upgrade": false,
+ "upgrade_auth": [
+ 3
+ ],
+ "upgrade_keys": [
+ { "kid": 3, "key": "./keys/MCUBOOT_CM0P_KEY.json" }
+ ],
+ "backup": false,
+ "resources": [
+ {
+ "type": "FLASH_PC1_SPM",
+ "address": 269287424,
+ "size": 65536
+ },
+ {
+ "type": "SRAM_SPM_PRIV",
+ "address": 134348800,
+ "size": 65536
+ }
+ ]
+ },
+ {
+ "boot_auth": [
+ 6
+ ],
+ "boot_keys": [
+ { "kid": 6, "key": "./keys/MCUBOOT_CM0P_KEY.json" }
+ ],
+ "id": 1,
+ "launch": 16,
+ "monotonic": 0,
+ "smif_id": 0,
+ "version": "0.1",
+ "rollback_counter": 0,
+ "upgrade": false,
+ "encrypt": false,
+ "encrypt_key_id": 1,
+ "upgrade_auth": [
+ 6
+ ],
+ "upgrade_keys": [
+ { "kid": 6, "key": "./keys/MCUBOOT_CM0P_KEY.json" }
+ ],
+ "backup": false,
+ "resources": [
+ {
+ "type": "BOOT",
+ "address": 268959744,
+ "size": 327680
+ },
+ {
+ "type": "UPGRADE",
+ "address": 268730368,
+ "size": 327680
+ }
+ ]
+ },
+ {
+ "boot_auth": [
+ 8
+ ],
+ "boot_keys": [
+ { "kid": 8, "key": "./keys/USERAPP_CM4_KEY.json" }
+ ],
+ "id": 16,
+ "monotonic": 0,
+ "smif_id": 0,
+ "version": "0.1",
+ "rollback_counter": 0,
+ "upgrade": false,
+ "upgrade_auth": [
+ 8
+ ],
+ "upgrade_keys": [
+ { "kid": 8, "key": "./keys/USERAPP_CM4_KEY.json" }
+ ],
+ "backup": false,
+ "resources": [
+ {
+ "type": "BOOT",
+ "address": 268435456,
+ "size": 163840
+ },
+ {
+ "type": "UPGRADE",
+ "address": 268730368,
+ "size": 262144
+ }
+ ]
+ }
+ ],
+ "reprogram": [
+ {
+ "size": 917504,
+ "start": 268435456
+ },
+ {
+ "size": 131072,
+ "start": 268828672
+ }
+ ],
+ "reprovision": {
+ "boot_loader": false,
+ "keys_and_policies": true
+ },
+ "title": "upgrade_policy"
+ },
+ "cy_bootloader":
+ {
+ "mode": "debug"
+ }
+}
diff --git a/platform/ext/target/psoc64/security/sign.py b/platform/ext/target/psoc64/security/sign.py
new file mode 100755
index 0000000000..f6c891392b
--- /dev/null
+++ b/platform/ext/target/psoc64/security/sign.py
@@ -0,0 +1,48 @@
+#!/usr/bin/python3
+"""
+Copyright (c) 2019 Cypress Semiconductor Corporation
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import cysecuretools
+import sys, getopt
+
+def main(argv):
+ s_hex_file=""
+ ns_hex_file=""
+ policy_file=""
+ try:
+ opts, args = getopt.getopt(argv,"hs:n:p:", ["s_hex=", "ns_hex=", "policy="])
+ except getopt.GetoptError:
+ print ('sign.py -s_hex <tfm_s hex> -ns_hex <tfm_ns hex> -policy <policy json>')
+ sys.exit(2)
+ for opt, arg in opts:
+ if opt == '-h':
+ print ('sign.py -s_hex <tfm_s hex> -ns_hex <tfm_ns hex> -policy <policy json>')
+ sys.exit()
+ elif opt in ("-s", "--s_hex"):
+ s_hex_file = arg
+ elif opt in ("-n", "--ns_hex"):
+ ns_hex_file = arg
+ elif opt in ("-p", "--policy"):
+ policy_file = arg
+ print ('tfm_s :', s_hex_file)
+ print ('tfm_ns:', ns_hex_file)
+ print ('policy:', policy_file)
+
+ cysecuretools.sign_image(s_hex_file, policy_file, 1);
+ cysecuretools.sign_image(ns_hex_file, policy_file, 16);
+
+if __name__ == "__main__":
+ main(sys.argv[1:])
diff --git a/platform/ext/target/psoc64/smpu_config.h b/platform/ext/target/psoc64/smpu_config.h
new file mode 100644
index 0000000000..61c79913a3
--- /dev/null
+++ b/platform/ext/target/psoc64/smpu_config.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SMPU_CONFIG_H__
+#define __SMPU_CONFIG_H__
+
+#include "flash_layout.h"
+#include "region_defs.h"
+
+#include "cy_prot.h"
+
+/* This macro depends on the actual CY_PROT_REGIONSIZE_XXX values */
+#define REGIONSIZE_TO_BYTES(X) (1UL << (1 + (X)))
+
+/* The actual SMPU configs */
+
+/* SMPU configs can only be changed by privileged secure PC=1 bus masters */
+#define COMMON_SMPU_MASTER_CONFIG {\
+ .userPermission = CY_PROT_PERM_R, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = ONLY_BL2_SPM_MASK, \
+}
+
+/* SMPU0 - secondary image in Flash */
+#define SMPU0_BASE S_ROM_ALIAS(0x00040000)
+#define SMPU0_REGIONSIZE PROT_SIZE_256KB_BIT_SHIFT
+#define SMPU0_SLAVE_CONFIG {\
+ .address = (void *)SMPU0_BASE, \
+ .regionSize = SMPU0_REGIONSIZE, \
+ .subregions = ALL_ENABLED, \
+ .userPermission = CY_PROT_PERM_RW, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SMPU0_MASTER_CONFIG COMMON_SMPU_MASTER_CONFIG
+
+/* SMPU requires base address aligned to size */
+#if SMPU0_BASE % REGIONSIZE_TO_BYTES(SMPU0_REGIONSIZE)
+#error "Flash layout has changed - SMPU0 needs updating"
+#endif
+
+/* SMPU1 - secure primary image in Flash */
+//#define SMPU1_BASE (SMPU0_BASE + REGIONSIZE_TO_BYTES(SMPU0_REGIONSIZE))
+#define SMPU1_BASE S_ROM_ALIAS(S_IMAGE_PRIMARY_PARTITION_OFFSET)
+#define SMPU1_REGIONSIZE PROT_SIZE_256KB_BIT_SHIFT
+#define SMPU1_SLAVE_CONFIG {\
+ .address = (void *)SMPU1_BASE, \
+ .regionSize = SMPU1_REGIONSIZE, \
+ .subregions = ALL_ENABLED, \
+ .userPermission = CY_PROT_PERM_RWX, \
+ .privPermission = CY_PROT_PERM_RWX, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SMPU1_MASTER_CONFIG COMMON_SMPU_MASTER_CONFIG
+
+/* SMPU requires base address aligned to size */
+#if SMPU1_BASE % REGIONSIZE_TO_BYTES(SMPU1_REGIONSIZE)
+#error "Flash layout has changed - SMPU1 needs updating"
+#endif
+
+/* SMPU2 - secure storage, NV counters, and unused space in Flash */
+//#define SMPU2_BASE (SMPU1_BASE + REGIONSIZE_TO_BYTES(SMPU1_REGIONSIZE))
+#define SMPU2_BASE S_ROM_ALIAS(FLASH_AREA_SCRATCH_OFFSET)
+#define SMPU2_REGIONSIZE PROT_SIZE_64KB_BIT_SHIFT
+#define SMPU2_SLAVE_CONFIG {\
+ .address = (void *)SMPU2_BASE, \
+ .regionSize = SMPU2_REGIONSIZE, \
+ .subregions = ALL_ENABLED, \
+ .userPermission = CY_PROT_PERM_RW, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SMPU2_MASTER_CONFIG COMMON_SMPU_MASTER_CONFIG
+
+/* SMPU requires base address aligned to size */
+#if SMPU2_BASE % REGIONSIZE_TO_BYTES(SMPU2_REGIONSIZE)
+#error "Flash layout has changed - SMPU2 needs updating"
+#endif
+
+/* SMPU6 - 32KB of unprivileged secure data in SRAM */
+#define SMPU6_BASE S_DATA_START
+#define SMPU6_REGIONSIZE PROT_SIZE_32KB_BIT_SHIFT
+#define SMPU6_SLAVE_CONFIG {\
+ .address = (void *)SMPU6_BASE, \
+ .regionSize = SMPU6_REGIONSIZE, \
+ .subregions = ALL_ENABLED, \
+ .userPermission = CY_PROT_PERM_RW, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SMPU6_MASTER_CONFIG COMMON_SMPU_MASTER_CONFIG
+
+/* SMPU requires base address aligned to size */
+#if SMPU6_BASE % REGIONSIZE_TO_BYTES(SMPU6_REGIONSIZE)
+#error "Flash layout has changed - SMPU6 needs updating"
+#endif
+
+/* S_DATA_PRIV_START must not overlap with SMPU6 region */
+#if S_DATA_PRIV_START < (SMPU6_BASE + REGIONSIZE_TO_BYTES(SMPU6_REGIONSIZE))
+#error "S_DATA_PRIV_START overlaps with unprivileged data section"
+#endif
+
+/* SMPU7 - 96KB of privileged secure data at S_DATA_PRIV_START in SRAM */
+#define SMPU7_BASE S_RAM_ALIAS(0)
+#define SMPU7_REGIONSIZE PROT_SIZE_256KB_BIT_SHIFT
+#define SMPU7_SUBREGION_DIS (CY_PROT_SUBREGION_DIS0 | \
+ CY_PROT_SUBREGION_DIS1 | \
+ CY_PROT_SUBREGION_DIS2 | \
+ CY_PROT_SUBREGION_DIS6 | \
+ CY_PROT_SUBREGION_DIS7)
+#define SMPU7_SLAVE_CONFIG {\
+ .address = (void *)SMPU7_BASE, \
+ .regionSize = SMPU7_REGIONSIZE, \
+ .subregions = SMPU7_SUBREGION_DIS, \
+ .userPermission = CY_PROT_PERM_DISABLED, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SMPU7_MASTER_CONFIG COMMON_SMPU_MASTER_CONFIG
+
+/* SMPU requires base address aligned to size */
+#if SMPU7_BASE % REGIONSIZE_TO_BYTES(SMPU7_REGIONSIZE)
+#error "Flash layout has changed - SMPU7 needs updating"
+#endif
+
+/*
+ * S_DATA_PRIV_START must equal the base address of the subregion 3 of
+ * SMPU7
+ */
+#if S_DATA_PRIV_START != (SMPU7_BASE + \
+ (3 * REGIONSIZE_TO_BYTES(SMPU7_REGIONSIZE) / 8))
+#error "Flash layout has changed - S_DATA_PRIV_START isn't subregion 3 of SMPU7"
+#endif
+
+/* SMPUs 6 and 7 should cover the whole secure data area in the RAM */
+#if S_DATA_SIZE != (REGIONSIZE_TO_BYTES(SMPU6_REGIONSIZE) + \
+ 3*REGIONSIZE_TO_BYTES(SMPU7_REGIONSIZE)/8)
+#error "Flash layout has changed - SMPU6/SMPU7 config needs updating"
+#endif
+
+/* SMPU10 - 4KB of privileged executable data in SRAM
+ * Note: Region resides in subregion 5 of SMPU 7*/
+#define SMPU10_BASE S_RAM_CODE_START
+#define SMPU10_REGIONSIZE PROT_SIZE_4KB_BIT_SHIFT
+#define SMPU10_SLAVE_CONFIG {\
+ .address = (void *)SMPU10_BASE, \
+ .regionSize = SMPU10_REGIONSIZE, \
+ .subregions = ALL_ENABLED, \
+ .userPermission = CY_PROT_PERM_DISABLED, \
+ .privPermission = CY_PROT_PERM_RX, \
+ .secure = true, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SMPU10_MASTER_CONFIG COMMON_SMPU_MASTER_CONFIG
+
+/* SMPU requires base address aligned to size */
+#if SMPU10_BASE % REGIONSIZE_TO_BYTES(SMPU10_REGIONSIZE)
+#error "Flash layout has changed - SMPU10 needs updating"
+#endif
+
+#if S_RAM_CODE_SIZE != REGIONSIZE_TO_BYTES(SMPU10_REGIONSIZE)
+#error "SMPU10_REGIONSIZE is not equal S_RAM_CODE_SIZE"
+#endif
+
+/* SMPU10 should be contained within SMPU7 */
+#if (SMPU10_BASE + SMPU10_REGIONSIZE) < (SMPU7_BASE + \
+ 3*REGIONSIZE_TO_BYTES(SMPU7_REGIONSIZE)/8)
+#error "SMPU10 is below SMPU7"
+#endif
+#if SMPU10_BASE > (SMPU7_BASE + \
+ 6*REGIONSIZE_TO_BYTES(SMPU7_REGIONSIZE)/8)
+#error "SMPU10 is above SMPU7"
+#endif
+
+#endif /* __SMPU_CONFIG_H__ */
diff --git a/platform/ext/target/psoc64/spm_hal.c b/platform/ext/target/psoc64/spm_hal.c
new file mode 100644
index 0000000000..98c4e6efbd
--- /dev/null
+++ b/platform/ext/target/psoc64/spm_hal.c
@@ -0,0 +1,435 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "platform/include/tfm_spm_hal.h"
+
+#include "region_defs.h"
+#include "secure_utilities.h"
+#include "spe_ipc_config.h"
+#include "spm_api.h"
+#include "spm_db.h"
+#include "target_cfg.h"
+#include "tfm_multi_core.h"
+#include "tfm_platform_core_api.h"
+
+#include "cycfg.h"
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_ipc_drv.h"
+#include "cy_prot.h"
+#include "cy_sysint.h"
+#include "pc_config.h"
+#include "driver_dap.h"
+
+/* Get address of memory regions to configure MPU */
+extern const struct memory_region_limits memory_regions;
+
+enum tfm_plat_err_t tfm_spm_hal_init_isolation_hw(void)
+{
+ cy_en_prot_status_t ret;
+
+ /* Ensure that CM0+ is in secure mode */
+ ret = Cy_Prot_ConfigBusMaster(CPUSS_MS_ID_CM0, true, true, SECURE_PCS_MASK);
+ if (ret != CY_PROT_SUCCESS) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+ smpu_init_cfg();
+ ppu_init_cfg();
+ bus_masters_cfg();
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+void tfm_spm_hal_configure_default_isolation(
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ printf("In %s()\n", __func__);
+ if (platform_data) {
+ /* TBD */
+ }
+}
+
+#if TFM_LVL != 1
+
+#define MPU_REGION_TFM_UNPRIV_CODE 1
+#define MPU_REGION_TFM_UNPRIV_DATA 2
+#define MPU_REGION_NS_DATA 3
+#define PARTITION_REGION_RO 4
+#define PARTITION_REGION_RW_STACK 5
+#define PARTITION_REGION_PERIPH 6
+#define PARTITION_REGION_SHARE 7
+
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
+
+static enum spm_err_t tfm_spm_mpu_init(void)
+{
+#if 0
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_armv8m_clean(&dev_mpu_s);
+
+ /* TFM Core unprivileged code region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_CODE;
+ region_cfg.region_base =
+ (uint32_t)&REGION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+ region_cfg.region_limit =
+ (uint32_t)&REGION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, &region_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged data region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_DATA;
+ region_cfg.region_base =
+ (uint32_t)&REGION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
+ region_cfg.region_limit =
+ (uint32_t)&REGION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, &region_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged non-secure data region */
+ region_cfg.region_nr = MPU_REGION_NS_DATA;
+ region_cfg.region_base = NS_DATA_START;
+ region_cfg.region_limit = NS_DATA_LIMIT;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, &region_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+#endif
+
+ return SPM_ERR_OK;
+}
+
+enum spm_err_t tfm_spm_hal_partition_sandbox_config(
+ const struct tfm_spm_partition_memory_data_t *memory_data,
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+#if 0
+ /* This function takes a partition id and enables the
+ * SPM partition for that partition
+ */
+
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_armv8m_disable(&dev_mpu_s);
+
+ /* Configure Regions */
+ if (memory_data->ro_start) {
+ /* RO region */
+ region_cfg.region_nr = PARTITION_REGION_RO;
+ region_cfg.region_base = memory_data->ro_start;
+ region_cfg.region_limit = memory_data->ro_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+
+ if (mpu_armv8m_region_enable(&dev_mpu_s, &region_cfg)
+ != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+ }
+
+ /* RW, ZI and stack as one region */
+ region_cfg.region_nr = PARTITION_REGION_RW_STACK;
+ region_cfg.region_base = memory_data->rw_start;
+ region_cfg.region_limit = memory_data->stack_top;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+
+ if (mpu_armv8m_region_enable(&dev_mpu_s, &region_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ if (platform_data) {
+ /* Peripheral */
+ region_cfg.region_nr = PARTITION_REGION_PERIPH;
+ region_cfg.region_base = platform_data->periph_start;
+ region_cfg.region_limit = platform_data->periph_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, &region_cfg)
+ != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ ppc_en_secure_unpriv(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+#endif
+
+ return SPM_ERR_OK;
+}
+
+enum tfm_plat_err_t tfm_spm_hal_setup_isolation_hw(void)
+{
+ if (tfm_spm_mpu_init() != SPM_ERR_OK) {
+ ERROR_MSG("Failed to set up initial MPU configuration! Halting.");
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+#endif /* TFM_LVL != 1 */
+
+uint32_t tfm_spm_hal_get_ns_VTOR(void)
+{
+ return memory_regions.non_secure_code_start;
+}
+
+uint32_t tfm_spm_hal_get_ns_MSP(void)
+{
+ return *((uint32_t *)memory_regions.non_secure_code_start);
+}
+
+uint32_t tfm_spm_hal_get_ns_entry_point(void)
+{
+ return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
+}
+
+void tfm_spm_hal_boot_ns_cpu(uintptr_t start_addr)
+{
+ printf("Starting Cortex-M4 at 0x%x\r\n", start_addr);
+ Cy_SysEnableCM4(start_addr);
+
+ if (cy_access_port_control(CY_CM4_AP, CY_AP_EN) == 0) {
+ /* The delay is required after Access port was enabled for
+ * debugger/programmer to connect and set TEST BIT */
+ Cy_SysLib_Delay(100);
+ }
+ else {
+ printf("Could not enable CY_CM4_AP DAP control\n");
+ }
+
+}
+
+void tfm_spm_hal_wait_for_ns_cpu_ready(void)
+{
+ uint32_t data;
+ cy_en_ipcdrv_status_t status;
+
+ Cy_IPC_Drv_SetInterruptMask(Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT),
+ 0, IPC_RX_INT_MASK);
+
+ status = Cy_IPC_Drv_SendMsgWord(Cy_IPC_Drv_GetIpcBaseAddress(IPC_TX_CHAN),
+ IPC_TX_NOTIFY_MASK, IPC_SYNC_MAGIC);
+ while (1)
+ {
+ status = Cy_IPC_Drv_GetInterruptStatusMasked(
+ Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT));
+ status >>= CY_IPC_NOTIFY_SHIFT;
+ if (status & IPC_RX_INT_MASK) {
+ Cy_IPC_Drv_ClearInterrupt(Cy_IPC_Drv_GetIntrBaseAddr(
+ IPC_RX_INTR_STRUCT),
+ 0, IPC_RX_INT_MASK);
+
+ status = Cy_IPC_Drv_ReadMsgWord(Cy_IPC_Drv_GetIpcBaseAddress(
+ IPC_RX_CHAN),
+ &data);
+ if (status == CY_IPC_DRV_SUCCESS) {
+ Cy_IPC_Drv_ReleaseNotify(Cy_IPC_Drv_GetIpcBaseAddress(IPC_RX_CHAN),
+ IPC_RX_RELEASE_MASK);
+ if (data == ~IPC_SYNC_MAGIC) {
+ printf("Cores sync success.\r\n");
+ break;
+ }
+ }
+ }
+ }
+}
+
+enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line,
+ uint32_t priority)
+{
+ uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
+ NVIC_SetPriority(irq_line, quantized_priority);
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+void tfm_spm_hal_get_mem_security_attr(const void *p, size_t s,
+ struct security_attr_info_t *p_attr)
+{
+ /*
+ * FIXME
+ * Need to check if the memory region is valid according to platform
+ * specific memory mapping.
+ */
+
+ /*
+ * TODO
+ * Currently only check static memory region layout to get security
+ * information.
+ * Check of hardware SMPU configuration can be added.
+ */
+ tfm_get_mem_region_security_attr(p, s, p_attr);
+}
+
+void tfm_spm_hal_get_secure_access_attr(const void *p, size_t s,
+ struct mem_attr_info_t *p_attr)
+{
+ uint32_t pc;
+
+ /*
+ * FIXME
+ * Need to check if the memory region is valid according to platform
+ * specific memory mapping.
+ */
+
+ /*
+ * TODO
+ * Currently only check static memory region layout to get attributes.
+ * Check of secure memory protection configuration from hardware can be
+ * added.
+ */
+ tfm_get_secure_mem_region_attr(p, s, p_attr);
+
+ pc = Cy_Prot_GetActivePC(CPUSS_MS_ID_CM0);
+ /* Check whether the current active PC is configured as the expected one .*/
+ if (pc == CY_PROT_SPM_DEFAULT) {
+ p_attr->is_mpu_enabled = true;
+ } else {
+ p_attr->is_mpu_enabled = false;
+ }
+}
+
+void tfm_spm_hal_get_ns_access_attr(const void *p, size_t s,
+ struct mem_attr_info_t *p_attr)
+{
+ /*
+ * FIXME
+ * Need to check if the memory region is valid according to platform
+ * specific memory mapping.
+ */
+
+ /*
+ * TODO
+ * Currently only check static memory region layout to get attributes.
+ * Check of non-secure memory protection configuration from hardware can be
+ * added.
+ */
+ tfm_get_ns_mem_region_attr(p, s, p_attr);
+}
+
+enum tfm_plat_err_t tfm_spm_hal_nvic_interrupt_enable(void)
+{
+ return nvic_interrupt_enable();
+}
+
+void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+{
+ (void)irq_line;
+}
+
+void tfm_spm_hal_enable_irq(int32_t irq_line)
+{
+ (void)irq_line;
+}
+
+void tfm_spm_hal_disable_irq(int32_t irq_line)
+{
+ (void)irq_line;
+}
+
+enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
+ int32_t irq_line,
+ enum irq_target_state_t target_state)
+{
+ (void)irq_line;
+ (void)target_state;
+
+ return TFM_IRQ_TARGET_STATE_SECURE;
+}
+
+enum tfm_plat_err_t tfm_spm_hal_nvic_interrupt_target_state_cfg(void)
+{
+ return nvic_interrupt_target_state_cfg();
+}
+
+enum tfm_plat_err_t tfm_spm_hal_enable_fault_handlers(void)
+{
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_spm_hal_system_reset_cfg(void)
+{
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_spm_hal_init_debug(void)
+{
+ printf("%s()\n", __func__);
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+/* FIXME:
+ * Instead of TFM-customized mcuboot, at this moment psoc64 uses
+ * Cypress version of it - CypressBootloader (CYBL). CYBL doesn't
+ * populate BOOT_TFM_SHARED_DATA.
+ * As a temp workaround, mock mcuboot shared data to pass
+ * initialization checks.
+*/
+void mock_tfm_shared_data(void)
+{
+ const uint32_t mock_data[] = {
+ 0x00D92016, 0x00071103, 0x00455053, 0x30000911,
+ 0x302E302E, 0x00081102, 0x00000000, 0x00241108,
+ 0x6C170A97, 0x5645665E, 0xDB6E2BA6, 0xA4FF4D74,
+ 0xFD34D7DB, 0x67449A82, 0x75FD0930, 0xAA15A9F9,
+ 0x000A1109, 0x32414853, 0x11013635, 0xE6BF0024,
+ 0x26886FD8, 0xFB97FFF4, 0xFBE6C496, 0x463E99C4,
+ 0x5D56FC19, 0x34DF6AA2, 0x9A4829C3, 0x114338DC,
+ 0x534E0008, 0x11404550, 0x2E300009, 0x42302E30,
+ 0x00000811, 0x48000000, 0x7E002411, 0x5FD9229A,
+ 0xE9672A5F, 0x31AAE1EA, 0x8514D772, 0x7F3B26BC,
+ 0x2C7EF27A, 0x9C6047D2, 0x4937BB9F, 0x53000A11,
+ 0x35324148, 0x24114136, 0xCA60B300, 0x6B8CC9F5,
+ 0x82482A94, 0x23489DFA, 0xA966B1EF, 0x4A6E6AEF,
+ 0x19197CA3, 0xC0CC1FED, 0x00000049, 0x00000000
+ };
+ uint32_t *boot_data = (uint32_t*)BOOT_TFM_SHARED_DATA_BASE;
+ memcpy(boot_data, mock_data, sizeof(mock_data));
+}
+
+enum tfm_plat_err_t tfm_spm_hal_post_platform_init(void)
+{
+ platform_init();
+ __enable_irq();
+ stdio_init();
+
+ /* FIXME: Use the actual data from mcuboot */
+ mock_tfm_shared_data();
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
diff --git a/platform/ext/target/psoc64/target_cfg.c b/platform/ext/target/psoc64/target_cfg.c
new file mode 100644
index 0000000000..18290ffca8
--- /dev/null
+++ b/platform/ext/target/psoc64/target_cfg.c
@@ -0,0 +1,762 @@
+/*
+ * Copyright (c) 2018 Arm Limited
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <assert.h>
+#include <stdio.h> /* for debugging printfs */
+#include "cy_prot.h"
+#include "cycfg.h"
+#include "device_definition.h"
+#include "driver_ppu.h"
+#include "driver_smpu.h"
+#include "pc_config.h"
+#include "platform_description.h"
+#include "region_defs.h"
+#include "RTE_Device.h"
+#include "target_cfg.h"
+#include "tfm_plat_defs.h"
+
+
+/* Macros to pick linker symbols */
+#define REGION(a, b, c) a##b##c
+#define REGION_NAME(a, b, c) REGION(a, b, c)
+#define REGION_DECLARE(a, b, c) extern uint32_t REGION_NAME(a, b, c)
+
+/* The section names come from the scatter file */
+REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
+#ifdef BL2
+REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
+#endif /* BL2 */
+
+const struct memory_region_limits memory_regions = {
+ .non_secure_code_start =
+ (uint32_t)&REGION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
+ BL2_HEADER_SIZE,
+
+ .non_secure_partition_base =
+ (uint32_t)&REGION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base),
+
+ .non_secure_partition_limit =
+ (uint32_t)&REGION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
+ NS_PARTITION_SIZE - 1,
+};
+
+
+#ifdef BL2
+REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
+#endif /* BL2 */
+
+/* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field,
+ * otherwise the processor ignores the write.
+ */
+#define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos))
+
+struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart = {
+ SCB5_BASE,
+ SCB5_BASE + 0xFFF,
+ -1,
+ -1
+};
+
+void enable_fault_handlers(void)
+{
+ /* Fault handles enable registers are not present in Cortex-M0+ */
+}
+
+void system_reset_cfg(void)
+{
+ uint32_t reg_value = SCB->AIRCR;
+
+ /* Clear SCB_AIRCR_VECTKEY value */
+ reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk);
+
+ /* Set Access Key (0x05FA must be written to this field) */
+ reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK);
+
+ SCB->AIRCR = reg_value;
+}
+
+extern void Cy_Platform_Init(void);
+void platform_init(void)
+{
+ Cy_PDL_Init(CY_DEVICE_CFG);
+
+ init_cycfg_all();
+ Cy_Platform_Init();
+
+ /* make sure CM4 is disabled */
+ if (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status()) {
+ Cy_SysDisableCM4();
+ }
+}
+
+enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void)
+{
+ printf("%s()\n", __func__);
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t nvic_interrupt_enable(void)
+{
+ /* PPU and SMPU don't generate interrupts.
+ * USART and Flash drivers don't export an EnableInterrupt function.
+ * So there's nothing to do here.
+ */
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+static cy_en_prot_status_t set_bus_master_attr(void)
+{
+ cy_en_prot_status_t ret;
+
+ printf("%s()\n", __func__);
+
+ /* Cortex-M4 - Unprivileged (ignored?), Non-secure, PC=6 */
+ ret = Cy_Prot_ConfigBusMaster(CPUSS_MS_ID_CM4, false, false, HOST_PCS_MASK);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+ ret = Cy_Prot_SetActivePC(CPUSS_MS_ID_CM4, CY_PROT_HOST_DEFAULT);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+
+ /* Test Controller - Unprivileged, Non-secure, PC=7 */
+ ret = Cy_Prot_ConfigBusMaster(CPUSS_MS_ID_TC, false, false, TC_PC_MASK);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+ ret = Cy_Prot_SetActivePC(CPUSS_MS_ID_TC, CY_PROT_TC);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+
+ /* Crypto - Privileged, Secure, PC=1 */
+ ret = Cy_Prot_ConfigBusMaster(CPUSS_MS_ID_CRYPTO, true, true, SECURE_PCS_MASK);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+ ret = Cy_Prot_SetActivePC(CPUSS_MS_ID_CRYPTO, CY_PROT_SPM_DEFAULT);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+
+ /* Cortex-M0+ - Privileged (ignored?), Secure, PC=1 */
+ ret = Cy_Prot_ConfigBusMaster(CPUSS_MS_ID_CM0, true, true, SECURE_PCS_MASK);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+ ret = Cy_Prot_SetActivePC(CPUSS_MS_ID_CM0, CY_PROT_SPM_DEFAULT);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+
+ return CY_PROT_SUCCESS;
+}
+
+void bus_masters_cfg(void)
+{
+ cy_en_prot_status_t ret = set_bus_master_attr();
+ if (ret) printf("set_bus_master_attr() returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+}
+
+void smpu_init_cfg(void)
+{
+ cy_en_prot_status_t ret;
+
+ printf("%s()\n", __func__);
+
+ printf("memory_regions.non_secure_code_start = %#x\n", memory_regions.non_secure_code_start);
+ printf("memory_regions.non_secure_partition_base = %#x\n", memory_regions.non_secure_partition_base);
+ printf("memory_regions.non_secure_partition_limit = %#x\n", memory_regions.non_secure_partition_limit);
+
+#if RTE_SMPU13
+ ret = SMPU_Configure(&SMPU13_Resources);
+ if (ret) printf("SMPU_Configure(SMPU13) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU12
+ ret = SMPU_Configure(&SMPU12_Resources);
+ if (ret) printf("SMPU_Configure(SMPU12) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU11
+ ret = SMPU_Configure(&SMPU11_Resources);
+ if (ret) printf("SMPU_Configure(SMPU11) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU10
+ ret = SMPU_Configure(&SMPU10_Resources);
+ if (ret) printf("SMPU_Configure(SMPU10) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU9
+ ret = SMPU_Configure(&SMPU9_Resources);
+ if (ret) printf("SMPU_Configure(SMPU9) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU8
+ ret = SMPU_Configure(&SMPU8_Resources);
+ if (ret) printf("SMPU_Configure(SMPU8) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU7
+ ret = SMPU_Configure(&SMPU7_Resources);
+ if (ret) printf("SMPU_Configure(SMPU7) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU6
+ ret = SMPU_Configure(&SMPU6_Resources);
+ if (ret) printf("SMPU_Configure(SMPU6) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU5
+ ret = SMPU_Configure(&SMPU5_Resources);
+ if (ret) printf("SMPU_Configure(SMPU5) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU4
+ ret = SMPU_Configure(&SMPU4_Resources);
+ if (ret) printf("SMPU_Configure(SMPU4) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU3
+ ret = SMPU_Configure(&SMPU3_Resources);
+ if (ret) printf("SMPU_Configure(SMPU3) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU2
+ ret = SMPU_Configure(&SMPU2_Resources);
+ if (ret) printf("SMPU_Configure(SMPU2) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU1
+ ret = SMPU_Configure(&SMPU1_Resources);
+ if (ret) printf("SMPU_Configure(SMPU1) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU0
+ ret = SMPU_Configure(&SMPU0_Resources);
+ if (ret) printf("SMPU_Configure(SMPU0) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+ /* Now protect all unconfigured SMPUs */
+ ret = protect_unconfigured_smpus();
+ if (ret) printf("protect_unconfigured_smpus() returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+
+ __DSB();
+ __ISB();
+}
+
+void ppu_init_cfg(void)
+{
+ cy_en_prot_status_t ret;
+
+ printf("%s()\n", __func__);
+
+#if RTE_PPU_PR0
+ ret = PPU_Configure(&PR0_PPU_Resources);
+ if (ret) printf("PPU_Configure(&PR0_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_PR1
+ ret = PPU_Configure(&PR1_PPU_Resources);
+ if (ret) printf("PPU_Configure(&PR1_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_PR2
+ ret = PPU_Configure(&PR2_PPU_Resources);
+ if (ret) printf("PPU_Configure(&PR2_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_PR3
+ ret = PPU_Configure(&PR3_PPU_Resources);
+ if (ret) printf("PPU_Configure(&PR3_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_PR4
+ ret = PPU_Configure(&PR4_PPU_Resources);
+ if (ret) printf("PPU_Configure(&PR4_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_PR5
+ ret = PPU_Configure(&PR5_PPU_Resources);
+ if (ret) printf("PPU_Configure(&PR5_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_PR6
+ ret = PPU_Configure(&PR6_PPU_Resources);
+ if (ret) printf("PPU_Configure(&PR6_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_PR7
+ ret = PPU_Configure(&PR7_PPU_Resources);
+ if (ret) printf("PPU_Configure(&PR7_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_PR8
+ ret = PPU_Configure(&PR8_PPU_Resources);
+ if (ret) printf("PPU_Configure(&PR8_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR0
+ ret = PPU_Configure(&GR0_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR0_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR1
+ ret = PPU_Configure(&GR1_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR1_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR2
+ ret = PPU_Configure(&GR2_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR2_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR3
+ ret = PPU_Configure(&GR3_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR3_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR4
+ ret = PPU_Configure(&GR4_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR4_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR6
+ ret = PPU_Configure(&GR6_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR6_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR9
+ ret = PPU_Configure(&GR9_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR9_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR10
+ ret = PPU_Configure(&GR10_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR10_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR_MMIO0
+ ret = PPU_Configure(&GR_MMIO0_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR_MMIO0_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR_MMIO1
+ ret = PPU_Configure(&GR_MMIO1_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR_MMIO1_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR_MMIO2
+ ret = PPU_Configure(&GR_MMIO2_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR_MMIO2_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR_MMIO3
+ ret = PPU_Configure(&GR_MMIO3_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR_MMIO3_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR_MMIO4
+ ret = PPU_Configure(&GR_MMIO4_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR_MMIO4_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR_MMIO6
+ ret = PPU_Configure(&GR_MMIO6_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR_MMIO6_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR_MMIO9
+ ret = PPU_Configure(&GR_MMIO9_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR_MMIO9_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR_MMIO10
+ ret = PPU_Configure(&GR_MMIO10_PPU_Resources);
+ if (ret) printf("PPU_Configure(&GR_MMIO10_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_PPU_GR_MMIO0
+ ret = PPU_Configure(&SL_PERI_GR1_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_PERI_GR1_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_CRYPTO
+ ret = PPU_Configure(&SL_CRYPTO_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_CRYPTO_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_PERI_GR2
+ ret = PPU_Configure(&SL_PERI_GR2_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_PERI_GR2_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_CPUSS
+ ret = PPU_Configure(&SL_CPUSS_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_CPUSS_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_FAULT
+ ret = PPU_Configure(&SL_FAULT_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_FAULT_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_IPC
+ ret = PPU_Configure(&SL_IPC_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_IPC_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_PROT
+ ret = PPU_Configure(&SL_PROT_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_PROT_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_FLASHC
+ ret = PPU_Configure(&SL_FLASHC_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_FLASHC_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_SRSS
+ ret = PPU_Configure(&SL_SRSS_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_SRSS_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_BACKUP
+ ret = PPU_Configure(&SL_BACKUP_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_BACKUP_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_DW0
+ ret = PPU_Configure(&SL_DW0_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_DW0_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_DW1
+ ret = PPU_Configure(&SL_DW1_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_DW1_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_EFUSE
+ ret = PPU_Configure(&SL_EFUSE_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_EFUSE_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_PROFILE
+ ret = PPU_Configure(&SL_PROFILE_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_PROFILE_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_STRUCT0
+ ret = PPU_Configure(&RG_IPC_STRUCT0_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_STRUCT0_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_STRUCT1
+ ret = PPU_Configure(&RG_IPC_STRUCT1_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_STRUCT1_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_STRUCT2
+ ret = PPU_Configure(&RG_IPC_STRUCT2_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_STRUCT2_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_STRUCT3
+ ret = PPU_Configure(&RG_IPC_STRUCT3_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_STRUCT3_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_STRUCT4
+ ret = PPU_Configure(&RG_IPC_STRUCT4_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_STRUCT4_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_STRUCT5
+ ret = PPU_Configure(&RG_IPC_STRUCT5_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_STRUCT5_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_STRUCT6
+ ret = PPU_Configure(&RG_IPC_STRUCT6_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_STRUCT6_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_STRUCT7
+ ret = PPU_Configure(&RG_IPC_STRUCT7_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_STRUCT7_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_INTR_STRUCT0
+ ret = PPU_Configure(&RG_IPC_INTR_STRUCT0_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_INTR_STRUCT0_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_INTR_STRUCT1
+ ret = PPU_Configure(&RG_IPC_INTR_STRUCT1_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_INTR_STRUCT1_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_INTR_STRUCT2
+ ret = PPU_Configure(&RG_IPC_INTR_STRUCT2_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_INTR_STRUCT2_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_INTR_STRUCT3
+ ret = PPU_Configure(&RG_IPC_INTR_STRUCT3_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_INTR_STRUCT3_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_INTR_STRUCT4
+ ret = PPU_Configure(&RG_IPC_INTR_STRUCT4_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_INTR_STRUCT4_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_INTR_STRUCT5
+ ret = PPU_Configure(&RG_IPC_INTR_STRUCT5_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_INTR_STRUCT5_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_INTR_STRUCT6
+ ret = PPU_Configure(&RG_IPC_INTR_STRUCT6_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_INTR_STRUCT6_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_IPC_INTR_STRUCT7
+ ret = PPU_Configure(&RG_IPC_INTR_STRUCT7_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_IPC_INTR_STRUCT7_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_DW0_DW_CH_STRUCT0
+ ret = PPU_Configure(&RG_DW0_DW_CH_STRUCT0_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_DW0_DW_CH_STRUCT0_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_DW0_DW_CH_STRUCT1
+ ret = PPU_Configure(&RG_DW0_DW_CH_STRUCT1_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_DW0_DW_CH_STRUCT1_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_DW0_DW_CH_STRUCT2
+ ret = PPU_Configure(&RG_DW0_DW_CH_STRUCT2_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_DW0_DW_CH_STRUCT2_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_DW0_DW_CH_STRUCT3
+ ret = PPU_Configure(&RG_DW0_DW_CH_STRUCT3_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_DW0_DW_CH_STRUCT3_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_DW1_DW_CH_STRUCT0
+ ret = PPU_Configure(&RG_DW1_DW_CH_STRUCT0_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_DW1_DW_CH_STRUCT0_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_DW1_DW_CH_STRUCT1
+ ret = PPU_Configure(&RG_DW1_DW_CH_STRUCT1_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_DW1_DW_CH_STRUCT1_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_DW1_DW_CH_STRUCT2
+ ret = PPU_Configure(&RG_DW1_DW_CH_STRUCT2_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_DW1_DW_CH_STRUCT2_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_DW1_DW_CH_STRUCT3
+ ret = PPU_Configure(&RG_DW1_DW_CH_STRUCT3_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_DW1_DW_CH_STRUCT3_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_SMPU
+ ret = PPU_Configure(&RG_SMPU_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_SMPU_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_MPU_CM0P
+ ret = PPU_Configure(&RG_MPU_CM0P_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_MPU_CM0P_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_MPU_CRYPTO
+ ret = PPU_Configure(&RG_MPU_CRYPTO_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_MPU_CRYPTO_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_MPU_CM4
+ ret = PPU_Configure(&RG_MPU_CM4_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_MPU_CM4_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_RG_MPU_TC
+ ret = PPU_Configure(&RG_MPU_TC_PPU_Resources);
+ if (ret) printf("PPU_Configure(&RG_MPU_TC_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_PERI_GR3
+ ret = PPU_Configure(&SL_PERI_GR3_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_PERI_GR3_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_HSIOM
+ ret = PPU_Configure(&SL_HSIOM_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_HSIOM_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_GPIO
+ ret = PPU_Configure(&SL_GPIO_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_GPIO_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_SMARTIO
+ ret = PPU_Configure(&SL_SMARTIO_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_SMARTIO_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_UDB
+ ret = PPU_Configure(&SL_UDB_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_UDB_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_LPCOMP
+ ret = PPU_Configure(&SL_LPCOMP_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_LPCOMP_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_CSD
+ ret = PPU_Configure(&SL_CSD_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_CSD_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_TCPWM0
+ ret = PPU_Configure(&SL_TCPWM0_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_TCPWM0_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_TCPWM1
+ ret = PPU_Configure(&SL_TCPWM1_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_TCPWM1_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_LCD
+ ret = PPU_Configure(&SL_LCD_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_LCD_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_BLE
+ ret = PPU_Configure(&SL_BLE_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_BLE_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_USBFS
+ ret = PPU_Configure(&SL_USBFS_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_USBFS_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_PERI_GR4
+ ret = PPU_Configure(&SL_PERI_GR4_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_PERI_GR4_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_SMIF
+ ret = PPU_Configure(&SL_SMIF_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_SMIF_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_PERI_GR6
+ ret = PPU_Configure(&SL_PERI_GR6_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_PERI_GR6_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_SCB0
+ ret = PPU_Configure(&SL_SCB0_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_SCB0_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_SCB1
+ ret = PPU_Configure(&SL_SCB1_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_SCB1_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_SCB2
+ ret = PPU_Configure(&SL_SCB2_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_SCB2_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_SCB3
+ ret = PPU_Configure(&SL_SCB3_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_SCB3_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_SCB4
+ ret = PPU_Configure(&SL_SCB4_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_SCB4_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_SCB5
+ ret = PPU_Configure(&SL_SCB5_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_SCB5_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_SCB6
+ ret = PPU_Configure(&SL_SCB6_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_SCB6_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_SCB7
+ ret = PPU_Configure(&SL_SCB7_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_SCB7_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_SCB8
+ ret = PPU_Configure(&SL_SCB8_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_SCB8_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_PERI_GR9
+ ret = PPU_Configure(&SL_PERI_GR9_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_PERI_GR9_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_PASS
+ ret = PPU_Configure(&SL_PASS_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_PASS_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_PERI_GB10
+ ret = PPU_Configure(&SL_PERI_GR10_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_PERI_GR10_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_I2S
+ ret = PPU_Configure(&SL_I2S_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_I2S_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_GR_PPU_SL_PDM
+ ret = PPU_Configure(&SL_PDM_PPU_Resources);
+ if (ret) printf("PPU_Configure(&SL_PDM_PPU_Resources) returned %#x\n", ret);
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+ __DSB();
+ __ISB();
+}
diff --git a/platform/ext/target/psoc64/target_cfg.h b/platform/ext/target/psoc64/target_cfg.h
new file mode 100644
index 0000000000..d325a54afa
--- /dev/null
+++ b/platform/ext/target/psoc64/target_cfg.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __TARGET_CFG_H__
+#define __TARGET_CFG_H__
+
+#include "platform/ext/common/uart_stdout.h"
+#include "tfm_peripherals_def.h"
+
+#define TFM_DRIVER_STDIO Driver_USART5
+#define NS_DRIVER_STDIO Driver_USART5
+
+/**
+ * \brief Store the addresses of memory regions
+ */
+struct memory_region_limits {
+ uint32_t non_secure_code_start;
+ uint32_t non_secure_partition_base;
+ uint32_t non_secure_partition_limit;
+};
+
+/**
+ * \brief Holds the data necessary to do isolation for a specific peripheral.
+ */
+struct tfm_spm_partition_platform_data_t
+{
+ uint32_t periph_start;
+ uint32_t periph_limit;
+ int16_t periph_ppc_bank;
+ int16_t periph_ppc_loc;
+};
+
+/**
+ * \brief Configures the Shared Memory Protection Units.
+ */
+void smpu_init_cfg(void);
+
+/**
+ * \brief Configures the Peripheral Protection Units.
+ */
+void ppu_init_cfg(void);
+
+/**
+ * \brief Configure bus masters/Protectoin Contexts.
+ */
+void bus_masters_cfg(void);
+
+/**
+ * \brief Performs platform specific hw initialization.
+ */
+void platform_init(void);
+
+/**
+ * \brief Configures all external interrupts to target the
+ * NS state, apart for the ones associated to secure
+ * peripherals.
+ *
+ * \return Returns values as specified by the \ref tfm_plat_err_t
+ */
+enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void);
+
+/**
+ * \brief This function enable the interrupts associated
+ * to the secure peripherals (plus the isolation boundary violation
+ * interrupts)
+ *
+ * \return Returns values as specified by the \ref tfm_plat_err_t
+ */
+enum tfm_plat_err_t nvic_interrupt_enable(void);
+
+#endif /* __TARGET_CFG_H__ */
diff --git a/platform/ext/target/psoc64/tfm_peripherals_def.h b/platform/ext/target/psoc64/tfm_peripherals_def.h
new file mode 100644
index 0000000000..724db32fe9
--- /dev/null
+++ b/platform/ext/target/psoc64/tfm_peripherals_def.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __TFM_PERIPHERALS_DEF_H__
+#define __TFM_PERIPHERALS_DEF_H__
+
+struct tfm_spm_partition_platform_data_t;
+
+extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
+extern struct tfm_spm_partition_platform_data_t tfm_peripheral_uart1;
+
+#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart)
+#define TFM_PERIPHERAL_UART1 (&tfm_peripheral_uart1)
+#define TFM_PERIPHERAL_FPGA_IO (0)
+
+#endif /* __TFM_PERIPHERALS_DEF_H__ */
diff --git a/platform/ext/target/psoc64/tfm_platform_system.c b/platform/ext/target/psoc64/tfm_platform_system.c
new file mode 100644
index 0000000000..cc21804eb1
--- /dev/null
+++ b/platform/ext/target/psoc64/tfm_platform_system.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "platform/include/tfm_platform_system.h"
+#include "platform_description.h"
+
+void tfm_platform_hal_system_reset(void)
+{
+ /* Reset the system */
+ NVIC_SystemReset();
+}
+
+enum tfm_plat_err_t
+tfm_platform_hal_pin_service(const psa_invec *in_vec, uint32_t num_invec,
+ const psa_outvec *out_vec, uint32_t num_outvec)
+{
+ (void)in_vec;
+ (void)num_invec;
+ (void)out_vec;
+ (void)num_outvec;
+ /* SCC is configured as non-secure through PPC,
+ * so this function is not needed on this platform
+ */
+ return TFM_PLAT_ERR_SUCCESS;
+}
+