diff options
author | Andrei Narkevitch <ainh@cypress.com> | 2019-10-10 11:31:02 -0700 |
---|---|---|
committer | David Hu <david.hu@arm.com> | 2019-10-12 03:18:24 +0000 |
commit | 2de48e80778f83d07c8dc5aef68a3cdf5afbe13b (patch) | |
tree | f22feadf03d27a4a083336a57d980b2217b23202 | |
parent | d7ec66c9889845f17ee3f6db8a23f61b74874adf (diff) | |
download | trusted-firmware-m-2de48e80778f83d07c8dc5aef68a3cdf5afbe13b.tar.gz |
plat: Enable Flash driver RWW support (PSoC62)
"Read while write" (RWW) improves flash driver performance
and enables flash driver notifications between two cores.
The latter is required to trigger an interrupt on CM4 side,
which handler is located in RAM, thus preventing the core
accessing flash memory during flash erase/program operations.
- add Cy_SysIpcPipeIsrCm0 interrupt handler to
CM0P interrupt vectors table
- add Cy_SysIpcPipeIsrCm4 and Cy_Flash_ResumeIrqHandler to
CM4 interrupt vectors table
- consider supporting vectors table relocation to RAM in order
to support run-time interrupt handlers registration - TBD
Signed-off-by: Andrei Narkevitch <ainh@cypress.com>
Change-Id: I797be7334aef2b95c27b7aaa466380d7fb28f114
7 files changed, 15 insertions, 20 deletions
diff --git a/platform/ext/psoc62.cmake b/platform/ext/psoc62.cmake index f058365413..f5589bc9ad 100644 --- a/platform/ext/psoc62.cmake +++ b/platform/ext/psoc62.cmake @@ -16,7 +16,7 @@ enable_multi_core_topology_config() set(TFM_NS_CLIENT_IDENTIFICATION OFF) add_definitions(-DCY8C6247BZI_D54=1) -add_definitions(-DCY_FLASH_RWW_DRV_SUPPORT_DISABLED=1 -DNDEBUG=1) +add_definitions(-DNDEBUG=1) add_definitions(-DTFM_CORE_DEBUG) # Skip Core Test temporarily diff --git a/platform/ext/target/psoc62/Device/Source/armclang/startup_psoc6_bl2.s b/platform/ext/target/psoc62/Device/Source/armclang/startup_psoc6_bl2.s index 4635c1b743..e7e8bffbb5 100644 --- a/platform/ext/target/psoc62/Device/Source/armclang/startup_psoc6_bl2.s +++ b/platform/ext/target/psoc62/Device/Source/armclang/startup_psoc6_bl2.s @@ -40,6 +40,8 @@ CY_NMI_HANLDER_ADDR EQU 0x0000000D EXPORT __Vectors_Size EXPORT __ramVectors + IMPORT Cy_SysIpcPipeIsrCm0 + __Vectors ;Core Interrupts DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler @@ -60,7 +62,7 @@ __Vectors ;Core Interrupts ; External interrupts Description DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 - DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 + DCD Cy_SysIpcPipeIsrCm0 DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 @@ -131,7 +133,6 @@ $handler_name PROC Default_Handler PendSV_Handler Default_Handler SysTick_Handler Default_Handler NvicMux0_IRQHandler - Default_Handler NvicMux1_IRQHandler Default_Handler NvicMux2_IRQHandler Default_Handler NvicMux3_IRQHandler Default_Handler NvicMux4_IRQHandler diff --git a/platform/ext/target/psoc62/Device/Source/armclang/startup_psoc6_ns.s b/platform/ext/target/psoc62/Device/Source/armclang/startup_psoc6_ns.s index f09b7000f4..623655c6a0 100644 --- a/platform/ext/target/psoc62/Device/Source/armclang/startup_psoc6_ns.s +++ b/platform/ext/target/psoc62/Device/Source/armclang/startup_psoc6_ns.s @@ -60,6 +60,8 @@ __heap_limit EXPORT __Vectors_End EXPORT __Vectors_Size EXPORT __ramVectors + IMPORT Cy_SysIpcPipeIsrCm4 + IMPORT Cy_Flash_ResumeIrqHandler __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler @@ -108,7 +110,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 - DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD Cy_SysIpcPipeIsrCm4 DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 @@ -164,7 +166,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt - DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD Cy_Flash_ResumeIrqHandler DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 @@ -341,7 +343,6 @@ Default_Handler PROC EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] @@ -397,7 +398,6 @@ Default_Handler PROC EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] - EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] @@ -489,7 +489,6 @@ cpuss_interrupts_ipc_0_IRQHandler cpuss_interrupts_ipc_1_IRQHandler cpuss_interrupts_ipc_2_IRQHandler cpuss_interrupts_ipc_3_IRQHandler -cpuss_interrupts_ipc_4_IRQHandler cpuss_interrupts_ipc_5_IRQHandler cpuss_interrupts_ipc_6_IRQHandler cpuss_interrupts_ipc_7_IRQHandler @@ -545,7 +544,6 @@ cpuss_interrupts_dw1_15_IRQHandler cpuss_interrupts_fault_0_IRQHandler cpuss_interrupts_fault_1_IRQHandler cpuss_interrupt_crypto_IRQHandler -cpuss_interrupt_fm_IRQHandler cpuss_interrupts_cm0_cti_0_IRQHandler cpuss_interrupts_cm0_cti_1_IRQHandler cpuss_interrupts_cm4_cti_0_IRQHandler diff --git a/platform/ext/target/psoc62/Device/Source/armclang/startup_psoc6_s.s b/platform/ext/target/psoc62/Device/Source/armclang/startup_psoc6_s.s index 4e62333f4e..22ac8d3748 100644 --- a/platform/ext/target/psoc62/Device/Source/armclang/startup_psoc6_s.s +++ b/platform/ext/target/psoc62/Device/Source/armclang/startup_psoc6_s.s @@ -46,6 +46,7 @@ CY_NMI_HANLDER_ADDR EQU 0x0000000D IMPORT SVC_Handler IMPORT PendSV_Handler IMPORT NvicMux9_IRQHandler + IMPORT Cy_SysIpcPipeIsrCm0 __Vectors ;Core Interrupts DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack @@ -67,7 +68,7 @@ __Vectors ;Core Interrupts ; External interrupts Description DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 - DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 + DCD Cy_SysIpcPipeIsrCm0 DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 @@ -141,7 +142,6 @@ $handler_name PROC Default_Handler SysTick_Handler Default_Handler NvicMux0_IRQHandler - Default_Handler NvicMux1_IRQHandler Default_Handler NvicMux2_IRQHandler Default_Handler NvicMux3_IRQHandler Default_Handler NvicMux4_IRQHandler diff --git a/platform/ext/target/psoc62/Device/Source/gcc/startup_psoc6_bl2.S b/platform/ext/target/psoc62/Device/Source/gcc/startup_psoc6_bl2.S index bd060e7975..40b4aa9754 100644 --- a/platform/ext/target/psoc62/Device/Source/gcc/startup_psoc6_bl2.S +++ b/platform/ext/target/psoc62/Device/Source/gcc/startup_psoc6_bl2.S @@ -53,7 +53,7 @@ __Vectors: /* External interrupts Description */ .long NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */ - .long NvicMux1_IRQHandler /* CM0 + NVIC Mux input 1 */ + .long Cy_SysIpcPipeIsrCm0 .long NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */ .long NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */ .long NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */ @@ -109,7 +109,7 @@ __ramVectors: /* Device startup customization */ .weak Cy_OnResetUser - .func Cy_OnResetUser, Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser .type Cy_OnResetUser, %function Cy_OnResetUser: @@ -348,7 +348,6 @@ Fault_Handler: def_irq_handler SysTick_Handler def_irq_handler NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */ - def_irq_handler NvicMux1_IRQHandler /* CM0 + NVIC Mux input 1 */ def_irq_handler NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */ def_irq_handler NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */ def_irq_handler NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */ diff --git a/platform/ext/target/psoc62/Device/Source/gcc/startup_psoc6_ns.S b/platform/ext/target/psoc62/Device/Source/gcc/startup_psoc6_ns.S index 7de6b22287..68011103d0 100644 --- a/platform/ext/target/psoc62/Device/Source/gcc/startup_psoc6_ns.S +++ b/platform/ext/target/psoc62/Device/Source/gcc/startup_psoc6_ns.S @@ -78,7 +78,7 @@ __Vectors: .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ - .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long Cy_SysIpcPipeIsrCm4 .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ @@ -134,7 +134,7 @@ __Vectors: .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ - .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long Cy_Flash_ResumeIrqHandler .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ @@ -493,7 +493,6 @@ Fault_Handler: def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ - def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ @@ -549,7 +548,6 @@ Fault_Handler: def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ - def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ diff --git a/platform/ext/target/psoc62/Device/Source/gcc/startup_psoc6_s.S b/platform/ext/target/psoc62/Device/Source/gcc/startup_psoc6_s.S index 7e970cf1e5..887f692cad 100644 --- a/platform/ext/target/psoc62/Device/Source/gcc/startup_psoc6_s.S +++ b/platform/ext/target/psoc62/Device/Source/gcc/startup_psoc6_s.S @@ -53,7 +53,7 @@ __Vectors: /* External interrupts Description */ .long NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */ - .long NvicMux1_IRQHandler /* CM0 + NVIC Mux input 1 */ + .long Cy_SysIpcPipeIsrCm0 .long NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */ .long NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */ .long NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */ @@ -350,7 +350,6 @@ Fault_Handler: def_irq_handler SysTick_Handler def_irq_handler NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */ - def_irq_handler NvicMux1_IRQHandler /* CM0 + NVIC Mux input 1 */ def_irq_handler NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */ def_irq_handler NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */ def_irq_handler NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */ |