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authorAndrei Narkevitch <ainh@cypress.com>2019-06-28 09:46:41 -0700
committerDavid Hu <david.hu@arm.com>2019-07-12 13:56:57 +0800
commit08bfcfec87a7844d9b704486b7541d723ecedefb (patch)
tree6f1c8510a446012a361a6c8f26db987a549ec104
parent70d83d6636ba29acdfd0c732e01a908e90d8dc18 (diff)
downloadtrusted-firmware-m-08bfcfec87a7844d9b704486b7541d723ecedefb.tar.gz
plat: add GCC toolchain support for Cypress PSoC6
Add GCC startup code and linker script for Cypress PSoC6. Add Cortex-M0+ and Cortex-M4 entires in GNUARM 6.3 and 7.3 cmake file. Clean up veneer generation and installation in multi-core topology. Signed-off-by: Andrei Narkevitch <ainh@cypress.com> Co-authored-by: David Hu <david.hu@arm.com> Change-Id: I9d88d95967398eb5336f4e1dac4536822343b750
-rw-r--r--app/CMakeLists.txt10
-rw-r--r--cmake/Common/CompilerGNUARM63.cmake21
-rw-r--r--cmake/Common/CompilerGNUARM73.cmake21
-rw-r--r--platform/ext/psoc6_host.cmake7
-rw-r--r--platform/ext/psoc6_sc.cmake4
-rw-r--r--platform/ext/target/psoc6/Device/Source/gcc/psoc6_bl2.ld397
-rw-r--r--platform/ext/target/psoc6/Device/Source/gcc/psoc6_ns.ld414
-rw-r--r--platform/ext/target/psoc6/Device/Source/gcc/psoc6_s.ld1082
-rw-r--r--platform/ext/target/psoc6/Device/Source/gcc/startup_psoc6_bl2.S386
-rw-r--r--platform/ext/target/psoc6/Device/Source/gcc/startup_psoc6_ns.S618
-rw-r--r--platform/ext/target/psoc6/Device/Source/gcc/startup_psoc6_s.S388
-rw-r--r--platform/ext/target/psoc6/partition/region_defs.h3
-rw-r--r--secure_fw/CMakeLists.txt28
13 files changed, 3359 insertions, 20 deletions
diff --git a/app/CMakeLists.txt b/app/CMakeLists.txt
index e3b1311fd1..4c2fc16ca5 100644
--- a/app/CMakeLists.txt
+++ b/app/CMakeLists.txt
@@ -284,9 +284,13 @@ function(set_up_app_build)
#Ensure secure_fw is built before our executable.
add_dependencies(${EXE_NAME} ${S_BIN})
- #Add the veneers to the executable.
- set(S_VENEER_FILE "${CMAKE_CURRENT_BINARY_DIR}/${VENEER_NAME}")
- set_property(TARGET ${EXE_NAME} APPEND PROPERTY LINK_LIBRARIES ${S_VENEER_FILE})
+ if (DEFINED TFM_MULTI_CORE_TOPOLOGY AND TFM_MULTI_CORE_TOPOLOGY)
+ message (STATUS "TFM_MULTI_CORE_TOPOLOGY is defined, not adding s_veneer.o")
+ else()
+ #Add the veneers to the executable.
+ set(S_VENEER_FILE "${CMAKE_CURRENT_BINARY_DIR}/${VENEER_NAME}")
+ set_property(TARGET ${EXE_NAME} APPEND PROPERTY LINK_LIBRARIES ${S_VENEER_FILE})
+ endif()
#Collect executables to common location: build/install/outputs/
install(FILES ${CMAKE_CURRENT_BINARY_DIR}/${EXE_NAME}.axf
diff --git a/cmake/Common/CompilerGNUARM63.cmake b/cmake/Common/CompilerGNUARM63.cmake
index a9bdd89f52..4df3d43cfb 100644
--- a/cmake/Common/CompilerGNUARM63.cmake
+++ b/cmake/Common/CompilerGNUARM63.cmake
@@ -30,6 +30,15 @@ elseif(${ARM_CPU_ARCHITECTURE} STREQUAL "ARMv7-M")
string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
+elseif(${ARM_CPU_ARCHITECTURE} STREQUAL "ARMv6-M")
+ string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "-march=" VAL "-march=armv6-m")
+ string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=cortex-m0")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "-march=" VAL "-march=armv6-m")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=cortex-m0")
+ string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "-march=" VAL "-march=armv6-m")
+ string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=cortex-m0")
+ string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "-march=" VAL "-march=armv6-m")
+ string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "-mcpu" VAL "-mcpu=cortex-m0plus")
else()
message(FATAL_ERROR "Unknown or unsupported ARM cpu architecture setting.")
endif()
@@ -53,6 +62,18 @@ if(NOT DEFINED ARM_CPU_ARCHITECTURE)
string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=cortex-m23")
string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "--cpu=" VAL "--cpu=Cortex-M23")
string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu=" VAL "--cpu=Cortex-M23")
+ elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M4")
+ string_append_unique_item (STRING CMAKE_C_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
+ string_append_unique_item (STRING CMAKE_CXX_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
+ string_append_unique_item (STRING CMAKE_ASM_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
+ string_append_unique_item (STRING CMAKE_LINK_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
+ set(ARM_CPU_ARCHITECTURE "ARMv7-M")
+ elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M0p")
+ string_append_unique_item (STRING CMAKE_C_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=cortex-m0plus")
+ string_append_unique_item (STRING CMAKE_CXX_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=cortex-m0plus")
+ string_append_unique_item (STRING CMAKE_ASM_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=Cortex-M0plus")
+ string_append_unique_item (STRING CMAKE_LINK_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=Cortex-M0plus")
+ set(ARM_CPU_ARCHITECTURE "ARMv6-M")
else()
message(FATAL_ERROR "Unknown ARM cpu setting.")
endif()
diff --git a/cmake/Common/CompilerGNUARM73.cmake b/cmake/Common/CompilerGNUARM73.cmake
index 5b173e05ef..23369de084 100644
--- a/cmake/Common/CompilerGNUARM73.cmake
+++ b/cmake/Common/CompilerGNUARM73.cmake
@@ -30,6 +30,15 @@ elseif(${ARM_CPU_ARCHITECTURE} STREQUAL "ARMv7-M")
string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
+elseif(${ARM_CPU_ARCHITECTURE} STREQUAL "ARMv6-M")
+ string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "-march=" VAL "-march=armv6-m")
+ string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=cortex-m0")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "-march=" VAL "-march=armv6-m")
+ string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=cortex-m0")
+ string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "-march=" VAL "-march=armv6-m")
+ string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=cortex-m0")
+ string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "-march=" VAL "-march=armv6-m")
+ string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "-mcpu" VAL "-mcpu=cortex-m0plus")
else()
message(FATAL_ERROR "Unknown or unsupported ARM cpu architecture setting.")
endif()
@@ -53,6 +62,18 @@ if(NOT DEFINED ARM_CPU_ARCHITECTURE)
string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=cortex-m23")
string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "--cpu=" VAL "--cpu=Cortex-M23")
string_append_unique_item(STRING CMAKE_LINK_FLAGS_CPU KEY "--cpu=" VAL "--cpu=Cortex-M23")
+ elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M4")
+ string_append_unique_item (STRING CMAKE_C_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
+ string_append_unique_item (STRING CMAKE_CXX_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
+ string_append_unique_item (STRING CMAKE_ASM_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
+ string_append_unique_item (STRING CMAKE_LINK_FLAGS_CPU KEY "-march=" VAL "-march=armv7-m")
+ set(ARM_CPU_ARCHITECTURE "ARMv7-M")
+ elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M0p")
+ string_append_unique_item (STRING CMAKE_C_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=cortex-m0plus")
+ string_append_unique_item (STRING CMAKE_CXX_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=cortex-m0plus")
+ string_append_unique_item (STRING CMAKE_ASM_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=Cortex-M0plus")
+ string_append_unique_item (STRING CMAKE_LINK_FLAGS_CPU KEY "-mcpu=" VAL "-mcpu=Cortex-M0plus")
+ set(ARM_CPU_ARCHITECTURE "ARMv6-M")
else()
message(FATAL_ERROR "Unknown ARM cpu setting.")
endif()
diff --git a/platform/ext/psoc6_host.cmake b/platform/ext/psoc6_host.cmake
index dd3617acec..1e45e50729 100644
--- a/platform/ext/psoc6_host.cmake
+++ b/platform/ext/psoc6_host.cmake
@@ -36,7 +36,8 @@ elseif(COMPILER STREQUAL "GNUARM")
set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/psoc6/Device/Source/gcc/psoc6_ns.ld")
if (DEFINED CMSIS_5_DIR)
# not all project defines CMSIS_5_DIR, only the ones that use it.
- set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a")
+ # [libRTX_CM3.a should be used for CM4 without FPU]
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a")
endif()
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
@@ -143,8 +144,8 @@ elseif(BUILD_STARTUP)
list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/psoc6/Device/Source/armclang/startup_ARMCM4.s")
list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/psoc6/Device/Source/armclang/startup_psoc6_bl2.s")
elseif(CMAKE_C_COMPILER_ID STREQUAL "GNUARM")
- list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/psoc6/Device/Source/gcc/startup_ARMCM0P.S")
- list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/psoc6/Device/Source/gcc/startup_ARMCM4.S")
+ list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/psoc6/Device/Source/gcc/startup_psoc6_s.S")
+ list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/psoc6/Device/Source/gcc/startup_psoc6_ns.S")
list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/psoc6/Device/Source/gcc/startup_psoc6_bl2.S")
set_property(SOURCE "${ALL_SRC_ASM_S}" "${ALL_SRC_ASM_NS}" "${ALL_SRC_ASM_BL2}" APPEND
PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
diff --git a/platform/ext/psoc6_sc.cmake b/platform/ext/psoc6_sc.cmake
index 40765dabfc..3f5c999def 100644
--- a/platform/ext/psoc6_sc.cmake
+++ b/platform/ext/psoc6_sc.cmake
@@ -146,8 +146,8 @@ elseif(BUILD_STARTUP)
list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/psoc6/Device/Source/armclang/startup_ARMCM4.s")
list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/psoc6/Device/Source/armclang/startup_psoc6_bl2.s")
elseif(CMAKE_C_COMPILER_ID STREQUAL "GNUARM")
- list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/psoc6/Device/Source/gcc/startup_ARMCM0P.S")
- list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/psoc6/Device/Source/gcc/startup_ARMCM4.S")
+ list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/psoc6/Device/Source/gcc/startup_psoc6_s.S")
+ list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/psoc6/Device/Source/gcc/startup_psoc6_ns.S")
list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/psoc6/Device/Source/gcc/startup_psoc6_bl2.S")
set_property(SOURCE "${ALL_SRC_ASM_S}" "${ALL_SRC_ASM_NS}" "${ALL_SRC_ASM_BL2}" APPEND
PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
diff --git a/platform/ext/target/psoc6/Device/Source/gcc/psoc6_bl2.ld b/platform/ext/target/psoc6/Device/Source/gcc/psoc6_bl2.ld
new file mode 100644
index 0000000000..905d05f59a
--- /dev/null
+++ b/platform/ext/target/psoc6/Device/Source/gcc/psoc6_bl2.ld
@@ -0,0 +1,397 @@
+/*
+ * Copyright (c) 2018-2019 ARM Limited
+ * Copyright 2016-2018 Cypress Semiconductor Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of Cypress PDL 3.0 cy8c6xx7_cm0plus.ld
+ */
+
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+#include "region_defs.h"
+
+__heap_size__ = BL2_HEAP_SIZE;
+__msp_stack_size__ = BL2_MSP_STACK_SIZE;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
+ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+ */
+ ram (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE
+ flash (rx) : ORIGIN = BL2_CODE_START, LENGTH = BL2_CODE_SIZE
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
+ sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
+ sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ .cy_app_header :
+ {
+ KEEP(*(.cy_app_header))
+ } > flash
+
+ .text :
+ {
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+#endif
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+ } > flash
+
+ __etext = . ;
+
+ .tfm_bl2_shared_data BOOT_TFM_SHARED_DATA_BASE : ALIGN(32)
+ {
+ . += BOOT_TFM_SHARED_DATA_SIZE;
+ } > ram
+
+ Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data);
+ Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data);
+
+#ifdef RAM_VECTORS_SUPPORT
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+ .data __ram_vectors_end__ : AT (__etext)
+#else
+ .data : AT (__etext)
+#endif
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+ bss_size = __bss_end__ - __bss_start__;
+
+ .msp_stack (NOLOAD): ALIGN(32)
+ {
+ . += __msp_stack_size__;
+ } > ram
+
+ Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+ .heap (NOLOAD): ALIGN(8)
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += __heap_size__;
+ __HeapLimit = .;
+ } > ram
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+
+ /* Supervisory Flash: Table of Content # 2 Copy */
+ .cy_rtoc_part2 :
+ {
+ KEEP(*(.cy_rtoc_part2))
+ } > sflash_rtoc_2
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ .cy_xip :
+ {
+ KEEP(*(.cy_xip))
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+
+ /* These sections are used for additional metadata (silicon revision,
+ * Silicon/JTAG ID, etc.) storage.
+ */
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start = 0x10000000;
+__cy_memory_0_length = 0x00100000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start = 0x14000000;
+__cy_memory_1_length = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start = 0x16000000;
+__cy_memory_2_length = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start = 0x18000000;
+__cy_memory_3_length = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start = 0x90700000;
+__cy_memory_4_length = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/platform/ext/target/psoc6/Device/Source/gcc/psoc6_ns.ld b/platform/ext/target/psoc6/Device/Source/gcc/psoc6_ns.ld
new file mode 100644
index 0000000000..ecd1c75fc9
--- /dev/null
+++ b/platform/ext/target/psoc6/Device/Source/gcc/psoc6_ns.ld
@@ -0,0 +1,414 @@
+/*
+ * Copyright (c) 2018-2019 ARM Limited
+ * Copyright 2016-2018 Cypress Semiconductor Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of Cypress PDL 3.0 cy8c6xx7_cm4_dual.ld
+ */
+
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+#include "region_defs.h"
+
+__heap_size__ = NS_HEAP_SIZE;
+__psp_stack_size__ = NS_PSP_STACK_SIZE;
+__msp_stack_size__ = NS_MSP_STACK_SIZE;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+ */
+ ram (rwx) : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE
+ flash (rx) : ORIGIN = NS_CODE_START, LENGTH = NS_CODE_SIZE
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
+ sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
+ sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+#endif
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+ } > flash
+
+ __etext = . ;
+
+
+#ifdef RAM_VECTORS_SUPPORT
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+ .data __ram_vectors_end__ : AT (__etext)
+#else
+ .data : AT (__etext)
+#endif
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ PROVIDE(end = .);
+ end = __end__;
+ . += __heap_size__;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > ram
+
+ .msp_stack : ALIGN(32)
+ {
+ . += __msp_stack_size__;
+ } > ram
+ Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+ .psp_stack : ALIGN(32)
+ {
+ . += __psp_stack_size__;
+ } > ram
+
+ Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack);
+ Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);
+
+ PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);
+
+ Image$$ER_TFM_DATA$$RW$$Base = ADDR(.data);
+ Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.data) + SIZEOF(.data);
+
+ Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.bss);
+ Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.bss) + SIZEOF(.bss);
+
+ Image$$ER_TFM_DATA$$Base = ADDR(.data);
+ Image$$ER_TFM_DATA$$Limit = ADDR(.data) + SIZEOF(.data) + SIZEOF(.bss);
+
+
+ /* Used for the digital signature of the secure application and the Bootloader SDK appication.
+ * The size of the section depends on the required data size. */
+ .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
+ {
+ KEEP(*(.cy_app_signature))
+ } > flash
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+
+ /* Supervisory Flash: Table of Content # 2 Copy */
+ .cy_rtoc_part2 :
+ {
+ KEEP(*(.cy_rtoc_part2))
+ } > sflash_rtoc_2
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ .cy_xip :
+ {
+ KEEP(*(.cy_xip))
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+
+ /* These sections are used for additional metadata (silicon revision,
+ * Silicon/JTAG ID, etc.) storage.
+ */
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start = 0x10000000;
+__cy_memory_0_length = 0x00100000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start = 0x14000000;
+__cy_memory_1_length = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start = 0x16000000;
+__cy_memory_2_length = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start = 0x18000000;
+__cy_memory_3_length = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start = 0x90700000;
+__cy_memory_4_length = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/platform/ext/target/psoc6/Device/Source/gcc/psoc6_s.ld b/platform/ext/target/psoc6/Device/Source/gcc/psoc6_s.ld
new file mode 100644
index 0000000000..ea32d68c19
--- /dev/null
+++ b/platform/ext/target/psoc6/Device/Source/gcc/psoc6_s.ld
@@ -0,0 +1,1082 @@
+/*
+ * Copyright (c) 2018-2019 ARM Limited
+ * Copyright 2016-2018 Cypress Semiconductor Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of Cypress PDL 3.0 cy8c6xx7_cm0plus.ld
+ */
+
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+#include "region_defs.h"
+
+__heap_size__ = S_HEAP_SIZE;
+__psp_stack_size__ = S_PSP_STACK_SIZE;
+__msp_init_stack_size__ = S_MSP_STACK_SIZE_INIT;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
+ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+ */
+ ram (rwx) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE
+ flash (rx) : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
+ sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
+ sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ .cy_app_header :
+ {
+ KEEP(*(.cy_app_header))
+ } > flash
+
+ .text :
+ {
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+#if TFM_LVL == 1
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+#endif
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (ADDR(.TFM_SECURE_STACK))
+ LONG (SIZEOF(.TFM_SECURE_STACK))
+ LONG (ADDR(.TFM_UNPRIV_SCRATCH))
+ LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
+ __zero_table_end__ = .;
+ } > flash
+
+ __etext = . ;
+
+#else /* TFM_LVL == 1 */
+ .copy.table : ALIGN(4)
+ {
+ __copy_table_start__ = .;
+ LONG (LOADADDR(.TFM_DATA))
+ LONG (ADDR(.TFM_DATA))
+ LONG (SIZEOF(.TFM_DATA))
+ LONG (LOADADDR(.TFM_UNPRIV_RO_DATA))
+ LONG (ADDR(.TFM_UNPRIV_RO_DATA))
+ LONG (SIZEOF(.TFM_UNPRIV_RO_DATA))
+ LONG (LOADADDR(.TFM_SP_STORAGE_DATA))
+ LONG (ADDR(.TFM_SP_STORAGE_DATA))
+ LONG (SIZEOF(.TFM_SP_STORAGE_DATA))
+ LONG (LOADADDR(.TFM_SP_AUDIT_LOG_DATA))
+ LONG (ADDR(.TFM_SP_AUDIT_LOG_DATA))
+ LONG (SIZEOF(.TFM_SP_AUDIT_LOG_DATA))
+ LONG (LOADADDR(.TFM_SP_CRYPTO_DATA))
+ LONG (ADDR(.TFM_SP_CRYPTO_DATA))
+ LONG (SIZEOF(.TFM_SP_CRYPTO_DATA))
+ LONG (LOADADDR(.TFM_SP_PLATFORM_DATA))
+ LONG (ADDR(.TFM_SP_PLATFORM_DATA))
+ LONG (SIZEOF(.TFM_SP_PLATFORM_DATA))
+ LONG (LOADADDR(.TFM_SP_INITIAL_ATTESTATION_DATA))
+ LONG (ADDR(.TFM_SP_INITIAL_ATTESTATION_DATA))
+ LONG (SIZEOF(.TFM_SP_INITIAL_ATTESTATION_DATA))
+#ifdef TFM_PARTITION_TEST_CORE
+ LONG (LOADADDR(.TFM_SP_CORE_TEST_DATA))
+ LONG (ADDR(.TFM_SP_CORE_TEST_DATA))
+ LONG (SIZEOF(.TFM_SP_CORE_TEST_DATA))
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_CORE
+ LONG (LOADADDR(.TFM_SP_CORE_TEST_2_DATA))
+ LONG (ADDR(.TFM_SP_CORE_TEST_2_DATA))
+ LONG (SIZEOF(.TFM_SP_CORE_TEST_2_DATA))
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+ LONG (LOADADDR(.TFM_SP_SECURE_TEST_PARTITION_DATA))
+ LONG (ADDR(.TFM_SP_SECURE_TEST_PARTITION_DATA))
+ LONG (SIZEOF(.TFM_SP_SECURE_TEST_PARTITION_DATA))
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+#ifdef TFM_PSA_API
+ LONG (LOADADDR(.TFM_SP_IPC_SERVICE_TEST_DATA))
+ LONG (ADDR(.TFM_SP_IPC_SERVICE_TEST_DATA))
+ LONG (SIZEOF(.TFM_SP_IPC_SERVICE_TEST_DATA))
+#endif /* TFM_PSA_API */
+#ifdef TFM_PSA_API
+ LONG (LOADADDR(.TFM_SP_IPC_CLIENT_TEST_DATA))
+ LONG (ADDR(.TFM_SP_IPC_CLIENT_TEST_DATA))
+ LONG (SIZEOF(.TFM_SP_IPC_CLIENT_TEST_DATA))
+#endif /* TFM_PSA_API */
+ __copy_table_end__ = .;
+ } > flash
+
+ .zero.table : ALIGN(4)
+ {
+ __zero_table_start__ = .;
+ LONG (ADDR(.TFM_BSS))
+ LONG (SIZEOF(.TFM_BSS))
+ LONG (ADDR(.TFM_UNPRIV_RO_BSS))
+ LONG (SIZEOF(.TFM_UNPRIV_RO_BSS))
+ LONG (ADDR(.TFM_SP_STORAGE_BSS))
+ LONG (SIZEOF(.TFM_SP_STORAGE_BSS))
+ LONG (ADDR(.TFM_SP_STORAGE_STACK))
+ LONG (SIZEOF(.TFM_SP_STORAGE_STACK))
+ LONG (ADDR(.TFM_SP_AUDIT_LOG_BSS))
+ LONG (SIZEOF(.TFM_SP_AUDIT_LOG_BSS))
+ LONG (ADDR(.TFM_SP_AUDIT_LOG_STACK))
+ LONG (SIZEOF(.TFM_SP_AUDIT_LOG_STACK))
+ LONG (ADDR(.TFM_SP_CRYPTO_BSS))
+ LONG (SIZEOF(.TFM_SP_CRYPTO_BSS))
+ LONG (ADDR(.TFM_SP_CRYPTO_STACK))
+ LONG (SIZEOF(.TFM_SP_CRYPTO_STACK))
+ LONG (ADDR(.TFM_SP_PLATFORM_BSS))
+ LONG (SIZEOF(.TFM_SP_PLATFORM_BSS))
+ LONG (ADDR(.TFM_SP_PLATFORM_STACK))
+ LONG (SIZEOF(.TFM_SP_PLATFORM_STACK))
+ LONG (ADDR(.TFM_SP_INITIAL_ATTESTATION_BSS))
+ LONG (SIZEOF(.TFM_SP_INITIAL_ATTESTATION_BSS))
+ LONG (ADDR(.TFM_SP_INITIAL_ATTESTATION_STACK))
+ LONG (SIZEOF(.TFM_SP_INITIAL_ATTESTATION_STACK))
+#ifdef TFM_PARTITION_TEST_CORE
+ LONG (ADDR(.TFM_SP_CORE_TEST_BSS))
+ LONG (SIZEOF(.TFM_SP_CORE_TEST_BSS))
+ LONG (ADDR(.TFM_SP_CORE_TEST_STACK))
+ LONG (SIZEOF(.TFM_SP_CORE_TEST_STACK))
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_CORE
+ LONG (ADDR(.TFM_SP_CORE_TEST_2_BSS))
+ LONG (SIZEOF(.TFM_SP_CORE_TEST_2_BSS))
+ LONG (ADDR(.TFM_SP_CORE_TEST_2_STACK))
+ LONG (SIZEOF(.TFM_SP_CORE_TEST_2_STACK))
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+ LONG (ADDR(.TFM_SP_SECURE_TEST_PARTITION_BSS))
+ LONG (SIZEOF(.TFM_SP_SECURE_TEST_PARTITION_BSS))
+ LONG (ADDR(.TFM_SP_SECURE_TEST_PARTITION_STACK))
+ LONG (SIZEOF(.TFM_SP_SECURE_TEST_PARTITION_STACK))
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+#ifdef TFM_PSA_API
+ LONG (ADDR(.TFM_SP_IPC_SERVICE_TEST_BSS))
+ LONG (SIZEOF(.TFM_SP_IPC_SERVICE_TEST_BSS))
+ LONG (ADDR(.TFM_SP_IPC_SERVICE_TEST_STACK))
+ LONG (SIZEOF(.TFM_SP_IPC_SERVICE_TEST_STACK))
+#endif /* TFM_PSA_API */
+#ifdef TFM_PSA_API
+ LONG (ADDR(.TFM_SP_IPC_CLIENT_TEST_BSS))
+ LONG (SIZEOF(.TFM_SP_IPC_CLIENT_TEST_BSS))
+ LONG (ADDR(.TFM_SP_IPC_CLIENT_TEST_STACK))
+ LONG (SIZEOF(.TFM_SP_IPC_CLIENT_TEST_STACK))
+#endif /* TFM_PSA_API */
+ LONG (ADDR(.TFM_UNPRIV_SCRATCH))
+ LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
+ __zero_table_end__ = .;
+ } > flash
+
+ .TFM_UNPRIV_CODE : ALIGN(32)
+ {
+ *libc_nano*:*(.text*)
+ *libc_nano*:*(.rodata*)
+ *tfm_spm_services.o(.text*)
+ *tfm_spm_services.o(.rodata*)
+ *dummy_crypto_keys.o(.text*)
+ *dummy_crypto_keys.o(.rodata*)
+ *dummy_nv_counters.o(.text*)
+ *dummy_nv_counters.o(.rodata*)
+ *dummy_boot_seed.o(.text*)
+ *dummy_boot_seed.o(.rodata*)
+ *dummy_device_id.o(.text*)
+ *dummy_device_id.o(.rodata*)
+ *platform_retarget_dev.o(.text*)
+ *platform_retarget_dev.o(.rodata*)
+ *(SFN)
+ *libgcc*:*(.text*)
+ *libgcc*:*(.rodata*)
+ . = ALIGN(32);
+ } > flash
+ Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);
+ Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);
+
+ .TFM_SP_STORAGE : ALIGN(32)
+ {
+ *tfm_storage*:*(.text*)
+ *tfm_storage*:*(.rodata*)
+ *(TFM_SP_STORAGE_ATTR_FN)
+ . = ALIGN(32);
+ } > flash
+ Image$$TFM_SP_STORAGE$$RO$$Base = ADDR(.TFM_SP_STORAGE);
+ Image$$TFM_SP_STORAGE$$RO$$Limit = ADDR(.TFM_SP_STORAGE) + SIZEOF(.TFM_SP_STORAGE);
+ Image$$TFM_SP_STORAGE$$Base = ADDR(.TFM_SP_STORAGE);
+ Image$$TFM_SP_STORAGE$$Limit = ADDR(.TFM_SP_STORAGE) + SIZEOF(.TFM_SP_STORAGE);
+
+ .TFM_SP_AUDIT_LOG : ALIGN(32)
+ {
+ *tfm_audit*:*(.text*)
+ *tfm_audit*:*(.rodata*)
+ *(TFM_SP_AUDIT_LOG_ATTR_FN)
+ . = ALIGN(32);
+ } > flash
+ Image$$TFM_SP_AUDIT_LOG$$RO$$Base = ADDR(.TFM_SP_AUDIT_LOG);
+ Image$$TFM_SP_AUDIT_LOG$$RO$$Limit = ADDR(.TFM_SP_AUDIT_LOG) + SIZEOF(.TFM_SP_AUDIT_LOG);
+ Image$$TFM_SP_AUDIT_LOG$$Base = ADDR(.TFM_SP_AUDIT_LOG);
+ Image$$TFM_SP_AUDIT_LOG$$Limit = ADDR(.TFM_SP_AUDIT_LOG) + SIZEOF(.TFM_SP_AUDIT_LOG);
+
+ .TFM_SP_CRYPTO : ALIGN(32)
+ {
+ *tfm_crypto*:*(.text*)
+ *tfm_crypto*:*(.rodata*)
+ *(TFM_SP_CRYPTO_ATTR_FN)
+ . = ALIGN(32);
+ } > flash
+ Image$$TFM_SP_CRYPTO$$RO$$Base = ADDR(.TFM_SP_CRYPTO);
+ Image$$TFM_SP_CRYPTO$$RO$$Limit = ADDR(.TFM_SP_CRYPTO) + SIZEOF(.TFM_SP_CRYPTO);
+ Image$$TFM_SP_CRYPTO$$Base = ADDR(.TFM_SP_CRYPTO);
+ Image$$TFM_SP_CRYPTO$$Limit = ADDR(.TFM_SP_CRYPTO) + SIZEOF(.TFM_SP_CRYPTO);
+
+ .TFM_SP_PLATFORM : ALIGN(32)
+ {
+ *tfm_platform*:*(.text*)
+ *tfm_platform*:*(.rodata*)
+ *(TFM_SP_PLATFORM_ATTR_FN)
+ . = ALIGN(32);
+ } > flash
+ Image$$TFM_SP_PLATFORM$$RO$$Base = ADDR(.TFM_SP_PLATFORM);
+ Image$$TFM_SP_PLATFORM$$RO$$Limit = ADDR(.TFM_SP_PLATFORM) + SIZEOF(.TFM_SP_PLATFORM);
+ Image$$TFM_SP_PLATFORM$$Base = ADDR(.TFM_SP_PLATFORM);
+ Image$$TFM_SP_PLATFORM$$Limit = ADDR(.TFM_SP_PLATFORM) + SIZEOF(.TFM_SP_PLATFORM);
+
+ .TFM_SP_INITIAL_ATTESTATION : ALIGN(32)
+ {
+ *tfm_attest*:*(.text*)
+ *tfm_attest*:*(.rodata*)
+ *(TFM_SP_INITIAL_ATTESTATION_ATTR_FN)
+ . = ALIGN(32);
+ } > flash
+ Image$$TFM_SP_INITIAL_ATTESTATION$$RO$$Base = ADDR(.TFM_SP_INITIAL_ATTESTATION);
+ Image$$TFM_SP_INITIAL_ATTESTATION$$RO$$Limit = ADDR(.TFM_SP_INITIAL_ATTESTATION) + SIZEOF(.TFM_SP_INITIAL_ATTESTATION);
+ Image$$TFM_SP_INITIAL_ATTESTATION$$Base = ADDR(.TFM_SP_INITIAL_ATTESTATION);
+ Image$$TFM_SP_INITIAL_ATTESTATION$$Limit = ADDR(.TFM_SP_INITIAL_ATTESTATION) + SIZEOF(.TFM_SP_INITIAL_ATTESTATION);
+
+#ifdef TFM_PARTITION_TEST_CORE
+ .TFM_SP_CORE_TEST : ALIGN(32)
+ {
+ *tfm_ss_core_test.*(.text*)
+ *tfm_ss_core_test.*(.rodata*)
+ *(TFM_SP_CORE_TEST_ATTR_FN)
+ . = ALIGN(32);
+ } > flash
+ Image$$TFM_SP_CORE_TEST$$RO$$Base = ADDR(.TFM_SP_CORE_TEST);
+ Image$$TFM_SP_CORE_TEST$$RO$$Limit = ADDR(.TFM_SP_CORE_TEST) + SIZEOF(.TFM_SP_CORE_TEST);
+ Image$$TFM_SP_CORE_TEST$$Base = ADDR(.TFM_SP_CORE_TEST);
+ Image$$TFM_SP_CORE_TEST$$Limit = ADDR(.TFM_SP_CORE_TEST) + SIZEOF(.TFM_SP_CORE_TEST);
+
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_CORE
+ .TFM_SP_CORE_TEST_2 : ALIGN(32)
+ {
+ *tfm_ss_core_test_2.*(.text*)
+ *tfm_ss_core_test_2.*(.rodata*)
+ *(TFM_SP_CORE_TEST_2_ATTR_FN)
+ . = ALIGN(32);
+ } > flash
+ Image$$TFM_SP_CORE_TEST_2$$RO$$Base = ADDR(.TFM_SP_CORE_TEST_2);
+ Image$$TFM_SP_CORE_TEST_2$$RO$$Limit = ADDR(.TFM_SP_CORE_TEST_2) + SIZEOF(.TFM_SP_CORE_TEST_2);
+ Image$$TFM_SP_CORE_TEST_2$$Base = ADDR(.TFM_SP_CORE_TEST_2);
+ Image$$TFM_SP_CORE_TEST_2$$Limit = ADDR(.TFM_SP_CORE_TEST_2) + SIZEOF(.TFM_SP_CORE_TEST_2);
+
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+ .TFM_SP_SECURE_TEST_PARTITION : ALIGN(32)
+ {
+ *tfm_secure_client_service.*(.text*)
+ *tfm_secure_client_service.*(.rodata*)
+ *test_framework*(.text*)
+ *test_framework*(.rodata*)
+ *uart_stdout.*(.text*)
+ *uart_stdout.*(.rodata*)
+ *Driver_USART.*(.text*)
+ *Driver_USART.*(.rodata*)
+ *arm_uart_drv.*(.text*)
+ *arm_uart_drv.*(.rodata*)
+ *uart_pl011_drv.*(.text*)
+ *uart_pl011_drv.*(.rodata*)
+ *secure_suites.*(.text*)
+ *secure_suites.*(.rodata*)
+ *attestation_s_interface_testsuite.*(.text*)
+ *attestation_s_interface_testsuite.*(.rodata*)
+ *(TFM_SP_SECURE_TEST_PARTITION_ATTR_FN)
+ . = ALIGN(32);
+ } > flash
+ Image$$TFM_SP_SECURE_TEST_PARTITION$$RO$$Base = ADDR(.TFM_SP_SECURE_TEST_PARTITION);
+ Image$$TFM_SP_SECURE_TEST_PARTITION$$RO$$Limit = ADDR(.TFM_SP_SECURE_TEST_PARTITION) + SIZEOF(.TFM_SP_SECURE_TEST_PARTITION);
+ Image$$TFM_SP_SECURE_TEST_PARTITION$$Base = ADDR(.TFM_SP_SECURE_TEST_PARTITION);
+ Image$$TFM_SP_SECURE_TEST_PARTITION$$Limit = ADDR(.TFM_SP_SECURE_TEST_PARTITION) + SIZEOF(.TFM_SP_SECURE_TEST_PARTITION);
+
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+#ifdef TFM_PSA_API
+ .TFM_SP_IPC_SERVICE_TEST : ALIGN(32)
+ {
+ *ipc_service_test*:*(.text*)
+ *ipc_service_test*:*(.rodata*)
+ *(TFM_SP_IPC_SERVICE_TEST_ATTR_FN)
+ . = ALIGN(32);
+ } > flash
+ Image$$TFM_SP_IPC_SERVICE_TEST$$RO$$Base = ADDR(.TFM_SP_IPC_SERVICE_TEST);
+ Image$$TFM_SP_IPC_SERVICE_TEST$$RO$$Limit = ADDR(.TFM_SP_IPC_SERVICE_TEST) + SIZEOF(.TFM_SP_IPC_SERVICE_TEST);
+ Image$$TFM_SP_IPC_SERVICE_TEST$$Base = ADDR(.TFM_SP_IPC_SERVICE_TEST);
+ Image$$TFM_SP_IPC_SERVICE_TEST$$Limit = ADDR(.TFM_SP_IPC_SERVICE_TEST) + SIZEOF(.TFM_SP_IPC_SERVICE_TEST);
+
+#endif /* TFM_PSA_API */
+#ifdef TFM_PSA_API
+ .TFM_SP_IPC_CLIENT_TEST : ALIGN(32)
+ {
+ *ipc_client_test*:*(.text*)
+ *ipc_client_test*:*(.rodata*)
+ *(TFM_SP_IPC_CLIENT_TEST_ATTR_FN)
+ . = ALIGN(32);
+ } > flash
+ Image$$TFM_SP_IPC_CLIENT_TEST$$RO$$Base = ADDR(.TFM_SP_IPC_CLIENT_TEST);
+ Image$$TFM_SP_IPC_CLIENT_TEST$$RO$$Limit = ADDR(.TFM_SP_IPC_CLIENT_TEST) + SIZEOF(.TFM_SP_IPC_CLIENT_TEST);
+ Image$$TFM_SP_IPC_CLIENT_TEST$$Base = ADDR(.TFM_SP_IPC_CLIENT_TEST);
+ Image$$TFM_SP_IPC_CLIENT_TEST$$Limit = ADDR(.TFM_SP_IPC_CLIENT_TEST) + SIZEOF(.TFM_SP_IPC_CLIENT_TEST);
+
+#endif /* TFM_PSA_API */
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+#endif /* TFM_LVL == 1 */
+
+ /* shared_data and msp_stack are overlapping on purpose when
+ * msp_stack is extended until the beginning of RAM, when shared_date
+ * was read out by partitions
+ */
+ .tfm_bl2_shared_data BOOT_TFM_SHARED_DATA_BASE : ALIGN(32)
+ {
+ . += BOOT_TFM_SHARED_DATA_SIZE;
+ } > ram
+
+ .msp_stack : ALIGN(32)
+ {
+ . += __msp_init_stack_size__;
+ } > ram
+ Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+ .psp_stack : ALIGN(32)
+ {
+ . += __psp_stack_size__;
+ } > ram
+ Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack);
+ Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);
+
+#ifdef RAM_VECTORS_SUPPORT
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+ .data __ram_vectors_end__ : AT (__etext)
+#else
+ .data : AT (__etext)
+#endif
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+ Image$$ER_TFM_DATA$$RW$$Base = ADDR(.data);
+ Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.data) + SIZEOF(.data);
+
+ Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.bss);
+ Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.bss) + SIZEOF(.bss);
+
+ Image$$ER_TFM_DATA$$Base = ADDR(.data);
+ Image$$ER_TFM_DATA$$Limit = ADDR(.data) + SIZEOF(.data) + SIZEOF(.bss);
+
+#if TFM_LVL == 1
+
+ .TFM_SECURE_STACK : ALIGN(128)
+ {
+ . += 0x2000;
+ } > ram
+ Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
+ Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
+
+ .TFM_UNPRIV_SCRATCH : ALIGN(32)
+ {
+ . += 0x400;
+ } > ram
+ Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
+ Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
+
+ .heap : ALIGN(8)
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += __heap_size__;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > ram
+
+
+#else /* TFM_LVL == 1 */
+ .TFM_UNPRIV_RO_DATA : ALIGN(32)
+ {
+ */tfm_spm_services.o(.data*)
+ */dummy_crypto_keys.o(.data*)
+ */dummy_nv_counters.o(.data*)
+ */dummy_boot_seed.o(.data*)
+ */dummy_device_id.o(.data*)
+ */platform_retarget_dev.o(.data*)
+ . = ALIGN(32);
+ } > ram AT> flash
+ Image$$TFM_UNPRIV_RO_DATA$$RW$$Base = ADDR(.TFM_UNPRIV_RO_DATA);
+ Image$$TFM_UNPRIV_RO_DATA$$RW$$Limit = ADDR(.TFM_UNPRIV_RO_DATA) + SIZEOF(.TFM_UNPRIV_RO_DATA);
+
+ .TFM_UNPRIV_RO_BSS : ALIGN(32)
+ {
+ */tfm_spm_services.o(.bss*)
+ */platform_retarget_dev.o(.bss*)
+ */dummy_crypto_keys.o(.bss*)
+ */dummy_nv_counters.o(.bss*)
+ */dummy_boot_seed.o(.bss*)
+ */dummy_device_id.o(.bss*)
+ */tfm_spm_services.o(COMMON)
+ */platform_retarget_dev.o(COMMON)
+ */dummy_crypto_keys.o(COMMON)
+ */dummy_nv_counters.o(COMMON)
+ */dummy_boot_seed.o(COMMON)
+ */dummy_device_id.o(COMMON)
+ . = ALIGN(32);
+ } > ram
+ Image$$TFM_UNPRIV_RO_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_RO_BSS);
+ Image$$TFM_UNPRIV_RO_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_RO_BSS) + SIZEOF(.TFM_UNPRIV_RO_BSS);
+
+ .TFM_UNPRIV_SCRATCH : ALIGN(32)
+ {
+ . += 0x400;
+ } > ram
+ Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
+ Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
+
+ .TFM_SP_STORAGE_DATA : ALIGN(32)
+ {
+ *tfm_storage*:*(.data*)
+ . = ALIGN(32);
+ } > ram AT> flash
+ Image$$TFM_SP_STORAGE_DATA$$RW$$Base = ADDR(.TFM_SP_STORAGE_DATA);
+ Image$$TFM_SP_STORAGE_DATA$$RW$$Limit = ADDR(.TFM_SP_STORAGE_DATA) + SIZEOF(.TFM_SP_STORAGE_DATA);
+
+ .TFM_SP_STORAGE_BSS : ALIGN(32)
+ {
+ *tfm_storage*:*(.bss*)
+ *tfm_storage*:*(COMMON)
+ . = ALIGN(32);
+ } > ram
+ Image$$TFM_SP_STORAGE_DATA$$ZI$$Base = ADDR(.TFM_SP_STORAGE_BSS);
+ Image$$TFM_SP_STORAGE_DATA$$ZI$$Limit = ADDR(.TFM_SP_STORAGE_BSS) + SIZEOF(.TFM_SP_STORAGE_BSS);
+
+ .TFM_SP_STORAGE_STACK : ALIGN(128)
+ {
+ . += 0x2000;
+ } > ram
+ Image$$TFM_SP_STORAGE_STACK$$ZI$$Base = ADDR(.TFM_SP_STORAGE_STACK);
+ Image$$TFM_SP_STORAGE_STACK$$ZI$$Limit = ADDR(.TFM_SP_STORAGE_STACK) + SIZEOF(.TFM_SP_STORAGE_STACK);
+
+ .TFM_SP_AUDIT_LOG_DATA : ALIGN(32)
+ {
+ *tfm_audit*:*(.data*)
+ . = ALIGN(32);
+ } > ram AT> flash
+ Image$$TFM_SP_AUDIT_LOG_DATA$$RW$$Base = ADDR(.TFM_SP_AUDIT_LOG_DATA);
+ Image$$TFM_SP_AUDIT_LOG_DATA$$RW$$Limit = ADDR(.TFM_SP_AUDIT_LOG_DATA) + SIZEOF(.TFM_SP_AUDIT_LOG_DATA);
+
+ .TFM_SP_AUDIT_LOG_BSS : ALIGN(32)
+ {
+ *tfm_audit*:*(.bss*)
+ *tfm_audit*:*(COMMON)
+ . = ALIGN(32);
+ } > ram
+ Image$$TFM_SP_AUDIT_LOG_DATA$$ZI$$Base = ADDR(.TFM_SP_AUDIT_LOG_BSS);
+ Image$$TFM_SP_AUDIT_LOG_DATA$$ZI$$Limit = ADDR(.TFM_SP_AUDIT_LOG_BSS) + SIZEOF(.TFM_SP_AUDIT_LOG_BSS);
+
+ .TFM_SP_AUDIT_LOG_STACK : ALIGN(128)
+ {
+ . += 0x1000;
+ } > ram
+ Image$$TFM_SP_AUDIT_LOG_STACK$$ZI$$Base = ADDR(.TFM_SP_AUDIT_LOG_STACK);
+ Image$$TFM_SP_AUDIT_LOG_STACK$$ZI$$Limit = ADDR(.TFM_SP_AUDIT_LOG_STACK) + SIZEOF(.TFM_SP_AUDIT_LOG_STACK);
+
+ .TFM_SP_CRYPTO_DATA : ALIGN(32)
+ {
+ *tfm_crypto*:*(.data*)
+ . = ALIGN(32);
+ } > ram AT> flash
+ Image$$TFM_SP_CRYPTO_DATA$$RW$$Base = ADDR(.TFM_SP_CRYPTO_DATA);
+ Image$$TFM_SP_CRYPTO_DATA$$RW$$Limit = ADDR(.TFM_SP_CRYPTO_DATA) + SIZEOF(.TFM_SP_CRYPTO_DATA);
+
+ .TFM_SP_CRYPTO_BSS : ALIGN(32)
+ {
+ *tfm_crypto*:*(.bss*)
+ *tfm_crypto*:*(COMMON)
+ . = ALIGN(32);
+ } > ram
+ Image$$TFM_SP_CRYPTO_DATA$$ZI$$Base = ADDR(.TFM_SP_CRYPTO_BSS);
+ Image$$TFM_SP_CRYPTO_DATA$$ZI$$Limit = ADDR(.TFM_SP_CRYPTO_BSS) + SIZEOF(.TFM_SP_CRYPTO_BSS);
+
+ .TFM_SP_CRYPTO_STACK : ALIGN(128)
+ {
+ . += 0x2000;
+ } > ram
+ Image$$TFM_SP_CRYPTO_STACK$$ZI$$Base = ADDR(.TFM_SP_CRYPTO_STACK);
+ Image$$TFM_SP_CRYPTO_STACK$$ZI$$Limit = ADDR(.TFM_SP_CRYPTO_STACK) + SIZEOF(.TFM_SP_CRYPTO_STACK);
+
+ .TFM_SP_PLATFORM_DATA : ALIGN(32)
+ {
+ *tfm_platform*:*(.data*)
+ . = ALIGN(32);
+ } > ram AT> flash
+ Image$$TFM_SP_PLATFORM_DATA$$RW$$Base = ADDR(.TFM_SP_PLATFORM_DATA);
+ Image$$TFM_SP_PLATFORM_DATA$$RW$$Limit = ADDR(.TFM_SP_PLATFORM_DATA) + SIZEOF(.TFM_SP_PLATFORM_DATA);
+
+ .TFM_SP_PLATFORM_BSS : ALIGN(32)
+ {
+ *tfm_platform*:*(.bss*)
+ *tfm_platform*:*(COMMON)
+ . = ALIGN(32);
+ } > ram
+ Image$$TFM_SP_PLATFORM_DATA$$ZI$$Base = ADDR(.TFM_SP_PLATFORM_BSS);
+ Image$$TFM_SP_PLATFORM_DATA$$ZI$$Limit = ADDR(.TFM_SP_PLATFORM_BSS) + SIZEOF(.TFM_SP_PLATFORM_BSS);
+
+ .TFM_SP_PLATFORM_STACK : ALIGN(128)
+ {
+ . += 0x0400;
+ } > ram
+ Image$$TFM_SP_PLATFORM_STACK$$ZI$$Base = ADDR(.TFM_SP_PLATFORM_STACK);
+ Image$$TFM_SP_PLATFORM_STACK$$ZI$$Limit = ADDR(.TFM_SP_PLATFORM_STACK) + SIZEOF(.TFM_SP_PLATFORM_STACK);
+
+ .TFM_SP_INITIAL_ATTESTATION_DATA : ALIGN(32)
+ {
+ *tfm_attest*:*(.data*)
+ . = ALIGN(32);
+ } > ram AT> flash
+ Image$$TFM_SP_INITIAL_ATTESTATION_DATA$$RW$$Base = ADDR(.TFM_SP_INITIAL_ATTESTATION_DATA);
+ Image$$TFM_SP_INITIAL_ATTESTATION_DATA$$RW$$Limit = ADDR(.TFM_SP_INITIAL_ATTESTATION_DATA) + SIZEOF(.TFM_SP_INITIAL_ATTESTATION_DATA);
+
+ .TFM_SP_INITIAL_ATTESTATION_BSS : ALIGN(32)
+ {
+ *tfm_attest*:*(.bss*)
+ *tfm_attest*:*(COMMON)
+ . = ALIGN(32);
+ } > ram
+ Image$$TFM_SP_INITIAL_ATTESTATION_DATA$$ZI$$Base = ADDR(.TFM_SP_INITIAL_ATTESTATION_BSS);
+ Image$$TFM_SP_INITIAL_ATTESTATION_DATA$$ZI$$Limit = ADDR(.TFM_SP_INITIAL_ATTESTATION_BSS) + SIZEOF(.TFM_SP_INITIAL_ATTESTATION_BSS);
+
+ .TFM_SP_INITIAL_ATTESTATION_STACK : ALIGN(128)
+ {
+ . += 0x0400;
+ } > ram
+ Image$$TFM_SP_INITIAL_ATTESTATION_STACK$$ZI$$Base = ADDR(.TFM_SP_INITIAL_ATTESTATION_STACK);
+ Image$$TFM_SP_INITIAL_ATTESTATION_STACK$$ZI$$Limit = ADDR(.TFM_SP_INITIAL_ATTESTATION_STACK) + SIZEOF(.TFM_SP_INITIAL_ATTESTATION_STACK);
+
+#ifdef TFM_PARTITION_TEST_CORE
+ .TFM_SP_CORE_TEST_DATA : ALIGN(32)
+ {
+ *tfm_ss_core_test.*(.data*)
+ . = ALIGN(32);
+ } > ram AT> flash
+ Image$$TFM_SP_CORE_TEST_DATA$$RW$$Base = ADDR(.TFM_SP_CORE_TEST_DATA);
+ Image$$TFM_SP_CORE_TEST_DATA$$RW$$Limit = ADDR(.TFM_SP_CORE_TEST_DATA) + SIZEOF(.TFM_SP_CORE_TEST_DATA);
+
+ .TFM_SP_CORE_TEST_BSS : ALIGN(32)
+ {
+ *tfm_ss_core_test.*(.bss*)
+ *tfm_ss_core_test.*(COMMON)
+ . = ALIGN(32);
+ } > ram
+ Image$$TFM_SP_CORE_TEST_DATA$$ZI$$Base = ADDR(.TFM_SP_CORE_TEST_BSS);
+ Image$$TFM_SP_CORE_TEST_DATA$$ZI$$Limit = ADDR(.TFM_SP_CORE_TEST_BSS) + SIZEOF(.TFM_SP_CORE_TEST_BSS);
+
+ .TFM_SP_CORE_TEST_STACK : ALIGN(128)
+ {
+ . += 0x0400;
+ } > ram
+ Image$$TFM_SP_CORE_TEST_STACK$$ZI$$Base = ADDR(.TFM_SP_CORE_TEST_STACK);
+ Image$$TFM_SP_CORE_TEST_STACK$$ZI$$Limit = ADDR(.TFM_SP_CORE_TEST_STACK) + SIZEOF(.TFM_SP_CORE_TEST_STACK);
+
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_CORE
+ .TFM_SP_CORE_TEST_2_DATA : ALIGN(32)
+ {
+ *tfm_ss_core_test_2.*(.data*)
+ . = ALIGN(32);
+ } > ram AT> flash
+ Image$$TFM_SP_CORE_TEST_2_DATA$$RW$$Base = ADDR(.TFM_SP_CORE_TEST_2_DATA);
+ Image$$TFM_SP_CORE_TEST_2_DATA$$RW$$Limit = ADDR(.TFM_SP_CORE_TEST_2_DATA) + SIZEOF(.TFM_SP_CORE_TEST_2_DATA);
+
+ .TFM_SP_CORE_TEST_2_BSS : ALIGN(32)
+ {
+ *tfm_ss_core_test_2.*(.bss*)
+ *tfm_ss_core_test_2.*(COMMON)
+ . = ALIGN(32);
+ } > ram
+ Image$$TFM_SP_CORE_TEST_2_DATA$$ZI$$Base = ADDR(.TFM_SP_CORE_TEST_2_BSS);
+ Image$$TFM_SP_CORE_TEST_2_DATA$$ZI$$Limit = ADDR(.TFM_SP_CORE_TEST_2_BSS) + SIZEOF(.TFM_SP_CORE_TEST_2_BSS);
+
+ .TFM_SP_CORE_TEST_2_STACK : ALIGN(128)
+ {
+ . += 0x0400;
+ } > ram
+ Image$$TFM_SP_CORE_TEST_2_STACK$$ZI$$Base = ADDR(.TFM_SP_CORE_TEST_2_STACK);
+ Image$$TFM_SP_CORE_TEST_2_STACK$$ZI$$Limit = ADDR(.TFM_SP_CORE_TEST_2_STACK) + SIZEOF(.TFM_SP_CORE_TEST_2_STACK);
+
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+ .TFM_SP_SECURE_TEST_PARTITION_DATA : ALIGN(32)
+ {
+ *tfm_secure_client_service.*(.data*)
+ *test_framework*(.data*)
+ *uart_stdout.*(.data*)
+ *Driver_USART.*(.data*)
+ *arm_uart_drv.*(.data*)
+ *uart_pl011_drv.*(.data*)
+ *secure_suites.*(.data*)
+ *attestation_s_interface_testsuite.*(.data*)
+ . = ALIGN(32);
+ } > ram AT> flash
+ Image$$TFM_SP_SECURE_TEST_PARTITION_DATA$$RW$$Base = ADDR(.TFM_SP_SECURE_TEST_PARTITION_DATA);
+ Image$$TFM_SP_SECURE_TEST_PARTITION_DATA$$RW$$Limit = ADDR(.TFM_SP_SECURE_TEST_PARTITION_DATA) + SIZEOF(.TFM_SP_SECURE_TEST_PARTITION_DATA);
+
+ .TFM_SP_SECURE_TEST_PARTITION_BSS : ALIGN(32)
+ {
+ *tfm_secure_client_service.*(.bss*)
+ *tfm_secure_client_service.*(COMMON)
+ *test_framework*(.bss*)
+ *test_framework*(COMMON)
+ *uart_stdout.*(.bss*)
+ *uart_stdout.*(COMMON)
+ *Driver_USART.*(.bss*)
+ *Driver_USART.*(COMMON)
+ *arm_uart_drv.*(.bss*)
+ *arm_uart_drv.*(COMMON)
+ *uart_pl011_drv.*(.bss*)
+ *uart_pl011_drv.*(COMMON)
+ *secure_suites.*(.bss*)
+ *secure_suites.*(COMMON)
+ *attestation_s_interface_testsuite.*(.bss*)
+ *attestation_s_interface_testsuite.*(COMMON)
+ . = ALIGN(32);
+ } > ram
+ Image$$TFM_SP_SECURE_TEST_PARTITION_DATA$$ZI$$Base = ADDR(.TFM_SP_SECURE_TEST_PARTITION_BSS);
+ Image$$TFM_SP_SECURE_TEST_PARTITION_DATA$$ZI$$Limit = ADDR(.TFM_SP_SECURE_TEST_PARTITION_BSS) + SIZEOF(.TFM_SP_SECURE_TEST_PARTITION_BSS);
+
+ .TFM_SP_SECURE_TEST_PARTITION_STACK : ALIGN(128)
+ {
+ . += 0x1000;
+ } > ram
+ Image$$TFM_SP_SECURE_TEST_PARTITION_STACK$$ZI$$Base = ADDR(.TFM_SP_SECURE_TEST_PARTITION_STACK);
+ Image$$TFM_SP_SECURE_TEST_PARTITION_STACK$$ZI$$Limit = ADDR(.TFM_SP_SECURE_TEST_PARTITION_STACK) + SIZEOF(.TFM_SP_SECURE_TEST_PARTITION_STACK);
+
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+#ifdef TFM_PSA_API
+ .TFM_SP_IPC_SERVICE_TEST_DATA : ALIGN(32)
+ {
+ *ipc_service_test*:*(.data*)
+ . = ALIGN(32);
+ } > ram AT> flash
+ Image$$TFM_SP_IPC_SERVICE_TEST_DATA$$RW$$Base = ADDR(.TFM_SP_IPC_SERVICE_TEST_DATA);
+ Image$$TFM_SP_IPC_SERVICE_TEST_DATA$$RW$$Limit = ADDR(.TFM_SP_IPC_SERVICE_TEST_DATA) + SIZEOF(.TFM_SP_IPC_SERVICE_TEST_DATA);
+
+ .TFM_SP_IPC_SERVICE_TEST_BSS : ALIGN(32)
+ {
+ *ipc_service_test*:*(.bss*)
+ *ipc_service_test*:*(COMMON)
+ . = ALIGN(32);
+ } > ram
+ Image$$TFM_SP_IPC_SERVICE_TEST_DATA$$ZI$$Base = ADDR(.TFM_SP_IPC_SERVICE_TEST_BSS);
+ Image$$TFM_SP_IPC_SERVICE_TEST_DATA$$ZI$$Limit = ADDR(.TFM_SP_IPC_SERVICE_TEST_BSS) + SIZEOF(.TFM_SP_IPC_SERVICE_TEST_BSS);
+
+ .TFM_SP_IPC_SERVICE_TEST_STACK : ALIGN(128)
+ {
+ . += 0x1000;
+ } > ram
+ Image$$TFM_SP_IPC_SERVICE_TEST_STACK$$ZI$$Base = ADDR(.TFM_SP_IPC_SERVICE_TEST_STACK);
+ Image$$TFM_SP_IPC_SERVICE_TEST_STACK$$ZI$$Limit = ADDR(.TFM_SP_IPC_SERVICE_TEST_STACK) + SIZEOF(.TFM_SP_IPC_SERVICE_TEST_STACK);
+
+#endif /* TFM_PSA_API */
+#ifdef TFM_PSA_API
+ .TFM_SP_IPC_CLIENT_TEST_DATA : ALIGN(32)
+ {
+ *ipc_client_test*:*(.data*)
+ . = ALIGN(32);
+ } > ram AT> flash
+ Image$$TFM_SP_IPC_CLIENT_TEST_DATA$$RW$$Base = ADDR(.TFM_SP_IPC_CLIENT_TEST_DATA);
+ Image$$TFM_SP_IPC_CLIENT_TEST_DATA$$RW$$Limit = ADDR(.TFM_SP_IPC_CLIENT_TEST_DATA) + SIZEOF(.TFM_SP_IPC_CLIENT_TEST_DATA);
+
+ .TFM_SP_IPC_CLIENT_TEST_BSS : ALIGN(32)
+ {
+ *ipc_client_test*:*(.bss*)
+ *ipc_client_test*:*(COMMON)
+ . = ALIGN(32);
+ } > ram
+ Image$$TFM_SP_IPC_CLIENT_TEST_DATA$$ZI$$Base = ADDR(.TFM_SP_IPC_CLIENT_TEST_BSS);
+ Image$$TFM_SP_IPC_CLIENT_TEST_DATA$$ZI$$Limit = ADDR(.TFM_SP_IPC_CLIENT_TEST_BSS) + SIZEOF(.TFM_SP_IPC_CLIENT_TEST_BSS);
+
+ .TFM_SP_IPC_CLIENT_TEST_STACK : ALIGN(128)
+ {
+ . += 0x1000;
+ } > ram
+ Image$$TFM_SP_IPC_CLIENT_TEST_STACK$$ZI$$Base = ADDR(.TFM_SP_IPC_CLIENT_TEST_STACK);
+ Image$$TFM_SP_IPC_CLIENT_TEST_STACK$$ZI$$Limit = ADDR(.TFM_SP_IPC_CLIENT_TEST_STACK) + SIZEOF(.TFM_SP_IPC_CLIENT_TEST_STACK);
+
+#endif /* TFM_PSA_API */
+
+ .TFM_SP_SECURE_TEST_PARTITION_DATA : ALIGN(32)
+ {
+ *libc_nano*:*(.data*)
+ . = ALIGN(32);
+ } > ram AT> flash
+
+ .TFM_SP_SECURE_TEST_PARTITION_BSS : ALIGN(32)
+ {
+ /* FixMe:
+ * Test framework use printf to print out test result. Implementation of
+ * printf in GCC libc use static data and heap as well. To be able to
+ * execute test suites with TFM_LVL=3 this workaround is needed to
+ * allocate libc static data and heap within the data section of secure
+ * test partition. This can be removed if test service will be executed
+ * in privileged mode.
+ */
+ *libc_nano*:*(.bss*)
+ *libc_nano*:*(COMMON)
+
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += __heap_size__;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+
+ . = ALIGN(32);
+ } > ram
+#endif /* TFM_LVL == 1 */
+
+
+ Load$$LR$$LR_NS_PARTITION$$Base = NS_PARTITION_START;
+
+#ifdef BL2
+ Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START;
+#endif /* BL2 */
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+
+ /* Supervisory Flash: Table of Content # 2 Copy */
+ .cy_rtoc_part2 :
+ {
+ KEEP(*(.cy_rtoc_part2))
+ } > sflash_rtoc_2
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ .cy_xip :
+ {
+ KEEP(*(.cy_xip))
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+
+ /* These sections are used for additional metadata (silicon revision,
+ * Silicon/JTAG ID, etc.) storage.
+ */
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start = 0x10000000;
+__cy_memory_0_length = 0x00100000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start = 0x14000000;
+__cy_memory_1_length = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start = 0x16000000;
+__cy_memory_2_length = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start = 0x18000000;
+__cy_memory_3_length = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start = 0x90700000;
+__cy_memory_4_length = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/platform/ext/target/psoc6/Device/Source/gcc/startup_psoc6_bl2.S b/platform/ext/target/psoc6/Device/Source/gcc/startup_psoc6_bl2.S
new file mode 100644
index 0000000000..bd060e7975
--- /dev/null
+++ b/platform/ext/target/psoc6/Device/Source/gcc/startup_psoc6_bl2.S
@@ -0,0 +1,386 @@
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* adapted from Cypress-Peripheral-Driver-Library-v3.0.1 startup_psoc63_cm0plus.S*/
+
+#include "region_defs.h"
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */
+ .long NvicMux1_IRQHandler /* CM0 + NVIC Mux input 1 */
+ .long NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */
+ .long NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */
+ .long NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */
+ .long NvicMux5_IRQHandler /* CM0 + NVIC Mux input 5 */
+ .long NvicMux6_IRQHandler /* CM0 + NVIC Mux input 6 */
+ .long NvicMux7_IRQHandler /* CM0 + NVIC Mux input 7 */
+ .long NvicMux8_IRQHandler /* CM0 + NVIC Mux input 8 */
+ .long NvicMux9_IRQHandler /* CM0 + NVIC Mux input 9 */
+ .long NvicMux10_IRQHandler /* CM0 + NVIC Mux input 10 */
+ .long NvicMux11_IRQHandler /* CM0 + NVIC Mux input 11 */
+ .long NvicMux12_IRQHandler /* CM0 + NVIC Mux input 12 */
+ .long NvicMux13_IRQHandler /* CM0 + NVIC Mux input 13 */
+ .long NvicMux14_IRQHandler /* CM0 + NVIC Mux input 14 */
+ .long NvicMux15_IRQHandler /* CM0 + NVIC Mux input 15 */
+ .long NvicMux16_IRQHandler /* CM0 + NVIC Mux input 16 */
+ .long NvicMux17_IRQHandler /* CM0 + NVIC Mux input 17 */
+ .long NvicMux18_IRQHandler /* CM0 + NVIC Mux input 18 */
+ .long NvicMux19_IRQHandler /* CM0 + NVIC Mux input 19 */
+ .long NvicMux20_IRQHandler /* CM0 + NVIC Mux input 20 */
+ .long NvicMux21_IRQHandler /* CM0 + NVIC Mux input 21 */
+ .long NvicMux22_IRQHandler /* CM0 + NVIC Mux input 22 */
+ .long NvicMux23_IRQHandler /* CM0 + NVIC Mux input 23 */
+ .long NvicMux24_IRQHandler /* CM0 + NVIC Mux input 24 */
+ .long NvicMux25_IRQHandler /* CM0 + NVIC Mux input 25 */
+ .long NvicMux26_IRQHandler /* CM0 + NVIC Mux input 26 */
+ .long NvicMux27_IRQHandler /* CM0 + NVIC Mux input 27 */
+ .long NvicMux28_IRQHandler /* CM0 + NVIC Mux input 28 */
+ .long NvicMux29_IRQHandler /* CM0 + NVIC Mux input 29 */
+ .long NvicMux30_IRQHandler /* CM0 + NVIC Mux input 30 */
+ .long NvicMux31_IRQHandler /* CM0 + NVIC Mux input 31 */
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+#ifdef RAM_VECTORS_SUPPORT
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+#else
+ /* vectors relocation is not supported,
+ but allocate __ramVectors for PDL code */
+ .globl __ramVectors
+ .equ __ramVectors, 0
+#endif
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /* Device startup customization */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+Cy_OnResetUser:
+
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Saves and disables the interrupts */
+ .global Cy_SaveIRQ
+ .func Cy_SaveIRQ, Cy_SaveIRQ
+ .type Cy_SaveIRQ, %function
+Cy_SaveIRQ:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+ .size Cy_SaveIRQ, . - Cy_SaveIRQ
+ .endfunc
+
+ /* Restores the interrupts */
+ .global Cy_RestoreIRQ
+ .func Cy_RestoreIRQ, Cy_RestoreIRQ
+ .type Cy_RestoreIRQ, %function
+Cy_RestoreIRQ:
+ msr PRIMASK, r0
+ bx lr
+ .size Cy_RestoreIRQ, . - Cy_RestoreIRQ
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ bl main
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+
+
+ .type Fault_Handler, %function
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+.L_API_call:
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_fault_Handler HardFault_Handler
+
+ def_irq_handler SVC_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */
+ def_irq_handler NvicMux1_IRQHandler /* CM0 + NVIC Mux input 1 */
+ def_irq_handler NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */
+ def_irq_handler NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */
+ def_irq_handler NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */
+ def_irq_handler NvicMux5_IRQHandler /* CM0 + NVIC Mux input 5 */
+ def_irq_handler NvicMux6_IRQHandler /* CM0 + NVIC Mux input 6 */
+ def_irq_handler NvicMux7_IRQHandler /* CM0 + NVIC Mux input 7 */
+ def_irq_handler NvicMux8_IRQHandler /* CM0 + NVIC Mux input 8 */
+ def_irq_handler NvicMux9_IRQHandler /* CM0 + NVIC Mux input 9 */
+ def_irq_handler NvicMux10_IRQHandler /* CM0 + NVIC Mux input 10 */
+ def_irq_handler NvicMux11_IRQHandler /* CM0 + NVIC Mux input 11 */
+ def_irq_handler NvicMux12_IRQHandler /* CM0 + NVIC Mux input 12 */
+ def_irq_handler NvicMux13_IRQHandler /* CM0 + NVIC Mux input 13 */
+ def_irq_handler NvicMux14_IRQHandler /* CM0 + NVIC Mux input 14 */
+ def_irq_handler NvicMux15_IRQHandler /* CM0 + NVIC Mux input 15 */
+ def_irq_handler NvicMux16_IRQHandler /* CM0 + NVIC Mux input 16 */
+ def_irq_handler NvicMux17_IRQHandler /* CM0 + NVIC Mux input 17 */
+ def_irq_handler NvicMux18_IRQHandler /* CM0 + NVIC Mux input 18 */
+ def_irq_handler NvicMux19_IRQHandler /* CM0 + NVIC Mux input 19 */
+ def_irq_handler NvicMux20_IRQHandler /* CM0 + NVIC Mux input 20 */
+ def_irq_handler NvicMux21_IRQHandler /* CM0 + NVIC Mux input 21 */
+ def_irq_handler NvicMux22_IRQHandler /* CM0 + NVIC Mux input 22 */
+ def_irq_handler NvicMux23_IRQHandler /* CM0 + NVIC Mux input 23 */
+ def_irq_handler NvicMux24_IRQHandler /* CM0 + NVIC Mux input 24 */
+ def_irq_handler NvicMux25_IRQHandler /* CM0 + NVIC Mux input 25 */
+ def_irq_handler NvicMux26_IRQHandler /* CM0 + NVIC Mux input 26 */
+ def_irq_handler NvicMux27_IRQHandler /* CM0 + NVIC Mux input 27 */
+ def_irq_handler NvicMux28_IRQHandler /* CM0 + NVIC Mux input 28 */
+ def_irq_handler NvicMux29_IRQHandler /* CM0 + NVIC Mux input 29 */
+ def_irq_handler NvicMux30_IRQHandler /* CM0 + NVIC Mux input 30 */
+ def_irq_handler NvicMux31_IRQHandler /* CM0 + NVIC Mux input 31 */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc6/Device/Source/gcc/startup_psoc6_ns.S b/platform/ext/target/psoc6/Device/Source/gcc/startup_psoc6_ns.S
new file mode 100644
index 0000000000..7de6b22287
--- /dev/null
+++ b/platform/ext/target/psoc6/Device/Source/gcc/startup_psoc6_ns.S
@@ -0,0 +1,618 @@
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* adapted from Cypress-Peripheral-Driver-Library-v3.0.1 startup_psoc63_cm4.S*/
+
+#include "region_defs.h"
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
+ .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
+ .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
+ .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
+ .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
+ .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
+ .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
+ .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
+ .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
+ .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
+ .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
+ .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
+ .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
+ .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
+ .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
+ .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
+ .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
+ .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
+ .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
+ .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
+ .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
+ .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
+ .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ .long usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_med_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
+
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+#ifdef RAM_VECTORS_SUPPORT
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+#else
+ /* vectors relocation is not supported,
+ but allocate __ramVectors for PDL code */
+ .globl __ramVectors
+ .equ __ramVectors, 0
+#endif
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /* Device startup customization */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+Cy_OnResetUser:
+
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Saves and disables the interrupts */
+ .global Cy_SaveIRQ
+ .func Cy_SaveIRQ, Cy_SaveIRQ
+ .type Cy_SaveIRQ, %function
+Cy_SaveIRQ:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+ .size Cy_SaveIRQ, . - Cy_SaveIRQ
+ .endfunc
+
+ /* Restores the interrupts */
+ .global Cy_RestoreIRQ
+ .func Cy_RestoreIRQ, Cy_RestoreIRQ
+ .type Cy_RestoreIRQ, %function
+Cy_RestoreIRQ:
+ msr PRIMASK, r0
+ bx lr
+ .size Cy_RestoreIRQ, . - Cy_RestoreIRQ
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+#endif
+
+#if defined (__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ /* temp workaround: this file is built as a part of sc built too */
+ /* Enable the FPU if used */
+ bl Cy_SystemInitFpuEnable
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ cpsie i
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+
+ .type Fault_Handler, %function
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+.L_API_call:
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+
+ def_fault_Handler HardFault_Handler
+ def_fault_Handler MemManage_Handler
+ def_fault_Handler BusFault_Handler
+ def_fault_Handler UsageFault_Handler
+
+ def_irq_handler DebugMon_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
+ def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
+ def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
+ def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
+ def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
+ def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
+ def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
+ def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
+ def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
+ def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
+ def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
+ def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
+ def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
+ def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
+ def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
+ def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
+ def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
+ def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
+ def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
+ def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
+ def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
+ def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
+ def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc6/Device/Source/gcc/startup_psoc6_s.S b/platform/ext/target/psoc6/Device/Source/gcc/startup_psoc6_s.S
new file mode 100644
index 0000000000..7e970cf1e5
--- /dev/null
+++ b/platform/ext/target/psoc6/Device/Source/gcc/startup_psoc6_s.S
@@ -0,0 +1,388 @@
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* adapted from Cypress-Peripheral-Driver-Library-v3.0.1 startup_psoc63_cm0plus.S*/
+
+#include "region_defs.h"
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */
+ .long NvicMux1_IRQHandler /* CM0 + NVIC Mux input 1 */
+ .long NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */
+ .long NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */
+ .long NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */
+ .long NvicMux5_IRQHandler /* CM0 + NVIC Mux input 5 */
+ .long NvicMux6_IRQHandler /* CM0 + NVIC Mux input 6 */
+ .long NvicMux7_IRQHandler /* CM0 + NVIC Mux input 7 */
+ .long NvicMux8_IRQHandler /* CM0 + NVIC Mux input 8 */
+ .long NvicMux9_IRQHandler /* CM0 + NVIC Mux input 9 */
+ .long NvicMux10_IRQHandler /* CM0 + NVIC Mux input 10 */
+ .long NvicMux11_IRQHandler /* CM0 + NVIC Mux input 11 */
+ .long NvicMux12_IRQHandler /* CM0 + NVIC Mux input 12 */
+ .long NvicMux13_IRQHandler /* CM0 + NVIC Mux input 13 */
+ .long NvicMux14_IRQHandler /* CM0 + NVIC Mux input 14 */
+ .long NvicMux15_IRQHandler /* CM0 + NVIC Mux input 15 */
+ .long NvicMux16_IRQHandler /* CM0 + NVIC Mux input 16 */
+ .long NvicMux17_IRQHandler /* CM0 + NVIC Mux input 17 */
+ .long NvicMux18_IRQHandler /* CM0 + NVIC Mux input 18 */
+ .long NvicMux19_IRQHandler /* CM0 + NVIC Mux input 19 */
+ .long NvicMux20_IRQHandler /* CM0 + NVIC Mux input 20 */
+ .long NvicMux21_IRQHandler /* CM0 + NVIC Mux input 21 */
+ .long NvicMux22_IRQHandler /* CM0 + NVIC Mux input 22 */
+ .long NvicMux23_IRQHandler /* CM0 + NVIC Mux input 23 */
+ .long NvicMux24_IRQHandler /* CM0 + NVIC Mux input 24 */
+ .long NvicMux25_IRQHandler /* CM0 + NVIC Mux input 25 */
+ .long NvicMux26_IRQHandler /* CM0 + NVIC Mux input 26 */
+ .long NvicMux27_IRQHandler /* CM0 + NVIC Mux input 27 */
+ .long NvicMux28_IRQHandler /* CM0 + NVIC Mux input 28 */
+ .long NvicMux29_IRQHandler /* CM0 + NVIC Mux input 29 */
+ .long NvicMux30_IRQHandler /* CM0 + NVIC Mux input 30 */
+ .long NvicMux31_IRQHandler /* CM0 + NVIC Mux input 31 */
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+#ifdef RAM_VECTORS_SUPPORT
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+#else
+ /* vectors relocation is not supported,
+ but allocate __ramVectors for PDL code */
+ .globl __ramVectors
+ .equ __ramVectors, 0
+#endif
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /* Device startup customization */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+Cy_OnResetUser:
+
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Saves and disables the interrupts */
+ .global Cy_SaveIRQ
+ .func Cy_SaveIRQ, Cy_SaveIRQ
+ .type Cy_SaveIRQ, %function
+Cy_SaveIRQ:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+ .size Cy_SaveIRQ, . - Cy_SaveIRQ
+ .endfunc
+
+ /* Restores the interrupts */
+ .global Cy_RestoreIRQ
+ .func Cy_RestoreIRQ, Cy_RestoreIRQ
+ .type Cy_RestoreIRQ, %function
+Cy_RestoreIRQ:
+ msr PRIMASK, r0
+ bx lr
+ .size Cy_RestoreIRQ, . - Cy_RestoreIRQ
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ mrs r0, control /* Get control value */
+ movs r1, #2
+ orrs r0, r0, r1 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+ msr psp, r0
+
+ bl main
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+
+ .type Fault_Handler, %function
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+.L_API_call:
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */
+ def_irq_handler NvicMux1_IRQHandler /* CM0 + NVIC Mux input 1 */
+ def_irq_handler NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */
+ def_irq_handler NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */
+ def_irq_handler NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */
+ def_irq_handler NvicMux5_IRQHandler /* CM0 + NVIC Mux input 5 */
+ def_irq_handler NvicMux6_IRQHandler /* CM0 + NVIC Mux input 6 */
+ def_irq_handler NvicMux7_IRQHandler /* CM0 + NVIC Mux input 7 */
+ def_irq_handler NvicMux8_IRQHandler /* CM0 + NVIC Mux input 8 */
+ def_irq_handler NvicMux9_IRQHandler /* CM0 + NVIC Mux input 9 */
+ def_irq_handler NvicMux10_IRQHandler /* CM0 + NVIC Mux input 10 */
+ def_irq_handler NvicMux11_IRQHandler /* CM0 + NVIC Mux input 11 */
+ def_irq_handler NvicMux12_IRQHandler /* CM0 + NVIC Mux input 12 */
+ def_irq_handler NvicMux13_IRQHandler /* CM0 + NVIC Mux input 13 */
+ def_irq_handler NvicMux14_IRQHandler /* CM0 + NVIC Mux input 14 */
+ def_irq_handler NvicMux15_IRQHandler /* CM0 + NVIC Mux input 15 */
+ def_irq_handler NvicMux16_IRQHandler /* CM0 + NVIC Mux input 16 */
+ def_irq_handler NvicMux17_IRQHandler /* CM0 + NVIC Mux input 17 */
+ def_irq_handler NvicMux18_IRQHandler /* CM0 + NVIC Mux input 18 */
+ def_irq_handler NvicMux19_IRQHandler /* CM0 + NVIC Mux input 19 */
+ def_irq_handler NvicMux20_IRQHandler /* CM0 + NVIC Mux input 20 */
+ def_irq_handler NvicMux21_IRQHandler /* CM0 + NVIC Mux input 21 */
+ def_irq_handler NvicMux22_IRQHandler /* CM0 + NVIC Mux input 22 */
+ def_irq_handler NvicMux23_IRQHandler /* CM0 + NVIC Mux input 23 */
+ def_irq_handler NvicMux24_IRQHandler /* CM0 + NVIC Mux input 24 */
+ def_irq_handler NvicMux25_IRQHandler /* CM0 + NVIC Mux input 25 */
+ def_irq_handler NvicMux26_IRQHandler /* CM0 + NVIC Mux input 26 */
+ def_irq_handler NvicMux27_IRQHandler /* CM0 + NVIC Mux input 27 */
+ def_irq_handler NvicMux28_IRQHandler /* CM0 + NVIC Mux input 28 */
+ def_irq_handler NvicMux29_IRQHandler /* CM0 + NVIC Mux input 29 */
+ def_irq_handler NvicMux30_IRQHandler /* CM0 + NVIC Mux input 30 */
+ def_irq_handler NvicMux31_IRQHandler /* CM0 + NVIC Mux input 31 */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/psoc6/partition/region_defs.h b/platform/ext/target/psoc6/partition/region_defs.h
index 538df100bf..acf3afec8f 100644
--- a/platform/ext/target/psoc6/partition/region_defs.h
+++ b/platform/ext/target/psoc6/partition/region_defs.h
@@ -34,6 +34,9 @@
#define NS_MSP_STACK_SIZE 0x0000400
#define NS_PSP_STACK_SIZE 0x0000C00
+/* Relocation of vectors to RAM support */
+/* #define RAM_VECTORS_SUPPORT */
+
/*
* This size of buffer is big enough to store an attestation
* token produced by initial attestation service
diff --git a/secure_fw/CMakeLists.txt b/secure_fw/CMakeLists.txt
index 3b55df4255..3ac3035822 100644
--- a/secure_fw/CMakeLists.txt
+++ b/secure_fw/CMakeLists.txt
@@ -269,18 +269,20 @@ function(set_up_secure_fw_build)
#Generate binary file from executable
compiler_generate_binary_output(${EXE_NAME})
- #Configure where we put the CMSE veneers generated by the compiler.
- if (DEFINED S_VENEER_FILE_LOCATION)
- set(S_VENEER_FILE "${S_VENEER_FILE_LOCATION}/${VENEER_NAME}")
- else()
- set(S_VENEER_FILE "${CMAKE_CURRENT_BINARY_DIR}/${VENEER_NAME}")
- endif()
- compiler_set_cmse_output(${EXE_NAME} "${S_VENEER_FILE}")
+ if (NOT DEFINED TFM_MULTI_CORE_TOPOLOGY OR NOT TFM_MULTI_CORE_TOPOLOGY)
+ #Configure where we put the CMSE veneers generated by the compiler.
+ if (DEFINED S_VENEER_FILE_LOCATION)
+ set(S_VENEER_FILE "${S_VENEER_FILE_LOCATION}/${VENEER_NAME}")
+ else()
+ set(S_VENEER_FILE "${CMAKE_CURRENT_BINARY_DIR}/${VENEER_NAME}")
+ endif()
+ compiler_set_cmse_output(${EXE_NAME} "${S_VENEER_FILE}")
- #Configure what file shall be installed.
- #Set install location. Keep original value to avoid overriding command line settings.
- if(CMAKE_INSTALL_PREFIX_INITIALIZED_TO_DEFAULT)
- set(CMAKE_INSTALL_PREFIX "${CMAKE_BINARY_DIR}/install" CACHE PATH "Default install location for secure_fw." FORCE)
+ #Configure what file shall be installed.
+ #Set install location. Keep original value to avoid overriding command line settings.
+ if(CMAKE_INSTALL_PREFIX_INITIALIZED_TO_DEFAULT)
+ set(CMAKE_INSTALL_PREFIX "${CMAKE_BINARY_DIR}/install" CACHE PATH "Default install location for secure_fw." FORCE)
+ endif()
endif()
#Export files needed to interface external applications at: <build_dir>/install/export/tfm/
@@ -290,7 +292,9 @@ function(set_up_secure_fw_build)
install(DIRECTORY ${TFM_ROOT_DIR}/interface/src/
DESTINATION export/tfm/src)
- install(FILES ${S_VENEER_FILE} DESTINATION export/tfm/veneers)
+ if (NOT DEFINED TFM_MULTI_CORE_TOPOLOGY OR NOT TFM_MULTI_CORE_TOPOLOGY)
+ install(FILES ${S_VENEER_FILE} DESTINATION export/tfm/veneers)
+ endif()
#Collect executables to common location: <build_dir>/install/outputs/
if (DEFINED SECURE_AXF_DIR_PREFIX)