Structure containing information for manual configuration of a PLL.
Data Fields | |
| uint8_t | feedbackDiv |
| CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits. | |
| uint8_t | referenceDiv |
| CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits. | |
| uint8_t | outputDiv |
| CLK_PLL_CONFIG register, OUTPUT_DIV bits. | |
| bool | lfMode |
| CLK_PLL_CONFIG register, PLL_LF_MODE bit. | |
| cy_en_fll_pll_output_mode_t | outputMode |
| CLK_PLL_CONFIG register, BYPASS_SEL bits. | |