Structure containing information for manual configuration of FLL.
Data Fields | |
| uint32_t | fllMult |
| CLK_FLL_CONFIG register, FLL_MULT bits. | |
| uint16_t | refDiv |
| CLK_FLL_CONFIG2 register, FLL_REF_DIV bits. | |
| cy_en_fll_cco_ranges_t | ccoRange |
| CLK_FLL_CONFIG4 register, CCO_RANGE bits. | |
| bool | enableOutputDiv |
| CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit. | |
| uint16_t | lockTolerance |
| CLK_FLL_CONFIG2 register, LOCK_TOL bits. | |
| uint8_t | igain |
| CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits. | |
| uint8_t | pgain |
| CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits. | |
| uint16_t | settlingCount |
| CLK_FLL_CONFIG3 register, SETTLING_COUNT bits. | |
| cy_en_fll_pll_output_mode_t | outputMode |
| CLK_FLL_CONFIG3 register, BYPASS_SEL bits. | |
| uint16_t | cco_Freq |
| CLK_FLL_CONFIG4 register, CCO_FREQ bits. | |