Dualcpu: Platform specific communication option

By setting the TFM_PLAT_SPECIFIC_MULTI_CORE_COMM cmake flag platform
specific implementation can be used to communicate between the Secure
and Non-secure cpu.

Change-Id: Ia966fa7150a709b75b6dfd1bce0d41135f287398
Signed-off-by: Mark Horvath <mark.horvath@arm.com>
diff --git a/config/check_config.cmake b/config/check_config.cmake
index ff11f44..0bf4986 100644
--- a/config/check_config.cmake
+++ b/config/check_config.cmake
@@ -28,6 +28,7 @@
 tfm_invalid_config(TFM_ISOLATION_LEVEL GREATER 1 AND NOT TFM_PSA_API)
 
 tfm_invalid_config(TFM_MULTI_CORE_TOPOLOGY AND NOT TFM_PSA_API)
+tfm_invalid_config(TFM_PLAT_SPECIFIC_MULTI_CORE_COMM AND NOT TFM_MULTI_CORE_TOPOLOGY)
 
 tfm_invalid_config(TEST_S  AND TEST_PSA_API)
 tfm_invalid_config(TEST_NS AND TEST_PSA_API)
diff --git a/config/config_default.cmake b/config/config_default.cmake
index bace812..5ad8034 100644
--- a/config/config_default.cmake
+++ b/config/config_default.cmake
@@ -84,6 +84,7 @@
 
 set(TFM_MULTI_CORE_TOPOLOGY             OFF         CACHE BOOL      "Whether to build for a dual-cpu architecture")
 set(NUM_MAILBOX_QUEUE_SLOT              1           CACHE BOOL      "Number of mailbox queue slots")
+set(TFM_PLAT_SPECIFIC_MULTI_CORE_COMM   OFF         CACHE BOOL      "Whether to use a platform specific inter-core communication instead of mailbox in dual-cpu topology")
 
 set(DEBUG_AUTHENTICATION                CHIP_DEFAULT CACHE STRING   "Debug authentication setting. [CHIP_DEFAULT, NONE, NS_ONLY, FULL")
 set(SECURE_UART1                        OFF         CACHE BOOL      "Enable secure UART1")
diff --git a/secure_fw/spm/CMakeLists.txt b/secure_fw/spm/CMakeLists.txt
index 098c518..5348ce9 100755
--- a/secure_fw/spm/CMakeLists.txt
+++ b/secure_fw/spm/CMakeLists.txt
@@ -40,7 +40,7 @@
         $<$<BOOL:${TFM_MULTI_CORE_TOPOLOGY}>:cmsis_psa/tfm_multi_core.c>
         $<$<BOOL:${TFM_MULTI_CORE_TOPOLOGY}>:cmsis_psa/tfm_multi_core_mem_check.c>
         $<$<BOOL:${TFM_MULTI_CORE_TOPOLOGY}>:cmsis_psa/tfm_rpc.c>
-        $<$<BOOL:${TFM_MULTI_CORE_TOPOLOGY}>:cmsis_psa/tfm_spe_mailbox.c>
+        $<$<AND:$<BOOL:${TFM_MULTI_CORE_TOPOLOGY}>,$<NOT:$<BOOL:${TFM_PLAT_SPECIFIC_MULTI_CORE_COMM}>>>:cmsis_psa/tfm_spe_mailbox.c>
         $<$<NOT:$<BOOL:${TFM_PSA_API}>>:ffm/tfm_core_mem_check.c>
         $<$<BOOL:${TFM_PSA_API}>:cmsis_psa/arch/tfm_arch.c>
         $<$<BOOL:${TFM_PSA_API}>:cmsis_psa/main.c>
diff --git a/secure_fw/spm/cmsis_psa/tfm_multi_core.c b/secure_fw/spm/cmsis_psa/tfm_multi_core.c
index 03a1afe..54b5da2 100644
--- a/secure_fw/spm/cmsis_psa/tfm_multi_core.c
+++ b/secure_fw/spm/cmsis_psa/tfm_multi_core.c
@@ -1,14 +1,14 @@
 /*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "tfm_arch.h"
 #include "tfm_assert.h"
-#include "tfm_spe_mailbox.h"
 #include "tfm_spm_hal.h"
 #include "tfm_spm_log.h"
+#include "tfm_multi_core.h"
 
 #define DEFAULT_NS_CLIENT_ID            (-1)
 
@@ -27,7 +27,7 @@
     tfm_spm_hal_boot_ns_cpu(tfm_spm_hal_get_ns_VTOR());
     tfm_spm_hal_wait_for_ns_cpu_ready();
 
-    tfm_mailbox_init();
+    tfm_inter_core_comm_init();
 
     /*
      * TODO
diff --git a/secure_fw/spm/cmsis_psa/tfm_multi_core.h b/secure_fw/spm/cmsis_psa/tfm_multi_core.h
index 0cf4ba2..87c8bc7 100644
--- a/secure_fw/spm/cmsis_psa/tfm_multi_core.h
+++ b/secure_fw/spm/cmsis_psa/tfm_multi_core.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -89,4 +89,12 @@
  */
 int32_t tfm_has_access_to_region(const void *p, size_t s, uint32_t attr);
 
+/**
+ * \brief Initialization of the multi core communication.
+ *
+ * \retval 0                    Operation succeeded.
+ * \retval Other return code    Operation failed with an error code.
+ */
+int32_t tfm_inter_core_comm_init(void);
+
 #endif /* __TFM_MULTI_CORE_H__ */
diff --git a/secure_fw/spm/cmsis_psa/tfm_spe_mailbox.c b/secure_fw/spm/cmsis_psa/tfm_spe_mailbox.c
index fe30726..5580169 100644
--- a/secure_fw/spm/cmsis_psa/tfm_spe_mailbox.c
+++ b/secure_fw/spm/cmsis_psa/tfm_spe_mailbox.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -12,6 +12,7 @@
 #include "utilities.h"
 #include "tfm_spe_mailbox.h"
 #include "tfm_rpc.h"
+#include "tfm_multi_core.h"
 
 #define NS_CALLER_FLAG          (true)
 
@@ -404,3 +405,8 @@
 
     return MAILBOX_SUCCESS;
 }
+
+int32_t tfm_inter_core_comm_init(void)
+{
+    return tfm_mailbox_init();
+}