Add possibility for platforms to define linker sections alignment
Some platforms may use different protection hardware (e.g. MPC) which
may require different alignment of linker sections. Also alignment size
may be dependent on the type of memory section is located in.
This patch adds a possibility for platforms to define needed linker
sections alignment. Platforms can define custom alignment in
region_defs.h file.
Alignment value can be changed for one or multiple sections using
appropriate macros.
Note that alignment macros are provided only for sections that use
alignment for protection hardware related reasons. Sections that use
alignment for other reasons (e.g. word alignment for better memory
access) has no need to be custom alienable thus align macros are not
provided for them.
Signed-off-by: Bohdan Hunko <Bohdan.Hunko@infineon.com>
Signed-off-by: Chris Brand <chris.brand@cypress.com>
Change-Id: Ic36e06b4a8a3bed922bbfb3e5651cf5a2abe95bc
diff --git a/platform/CMakeLists.txt b/platform/CMakeLists.txt
index 0992553..0f0fc1c 100755
--- a/platform/CMakeLists.txt
+++ b/platform/CMakeLists.txt
@@ -296,3 +296,8 @@
$<$<OR:$<CONFIG:Debug>,$<CONFIG:relwithdebinfo>>:ENABLE_HEAP>
PLATFORM_NS_NV_COUNTERS=${TFM_NS_NV_COUNTER_AMOUNT}
)
+
+target_include_directories(platform_region_defs
+ INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/ext/common
+)
diff --git a/platform/ext/common/armclang/tfm_common_s.sct b/platform/ext/common/armclang/tfm_common_s.sct
index ac7d2be..e159d91 100644
--- a/platform/ext/common/armclang/tfm_common_s.sct
+++ b/platform/ext/common/armclang/tfm_common_s.sct
@@ -18,6 +18,11 @@
#include "region_defs.h"
+/* Include file with definitions for section alignments.
+ * Note: it should be included after region_defs.h to let platform define
+ * default values if needed. */
+#include "tfm_s_linker_alignments.h"
+
LR_CODE S_CODE_START S_CODE_SIZE {
/**** This initial section contains common code for secure binary */
@@ -32,14 +37,14 @@
* 32 bytes aligned region so that the SAU can be programmed to
* just set this region as Non-Secure Callable.
*/
- ER_VENEER +0 FIXED ALIGN 32 {
+ ER_VENEER +0 FIXED ALIGN TFM_LINKER_VENEERS_ALIGNMENT {
*(Veneer$$CMSE)
}
/*
- * The Limit of the VENEER_ALIGN region should be 32 bytes aligned so that
- * the SAU can set this region as Non-Secure Callable.
+ * The Limit of the VENEER_ALIGN region should be at least 32 bytes aligned
+ * so that the SAU can set this region as Non-Secure Callable.
*/
- VENEER_ALIGN +0 ALIGN 32 EMPTY 0x0 {
+ VENEER_ALIGN +0 ALIGN TFM_LINKER_VENEERS_ALIGNMENT EMPTY 0x0 {
}
#endif
@@ -50,7 +55,7 @@
}
/**** Unprivileged Secure code start here */
- TFM_UNPRIV_CODE +0 ALIGN 32 {
+ TFM_UNPRIV_CODE +0 ALIGN TFM_LINKER_UNPRIV_CODE_ALIGNMENT {
*(SFN)
* (+RO)
}
@@ -72,10 +77,10 @@
* This empty, zero long execution region is here to mark the start address
* of PSA RoT code.
*/
- TFM_PSA_CODE_START +0 ALIGN 32 EMPTY 0x0 {
+ TFM_PSA_CODE_START +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT EMPTY 0x0 {
}
- TFM_PSA_ROT_LINKER +0 ALIGN 32 {
+ TFM_PSA_ROT_LINKER +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT {
*tfm_psa_rot_partition* (+RO-CODE, +RO-DATA)
*libplatform_s* (TFM_*_PSA-ROT_ATTR_FN)
*.o (TFM_*_PSA-ROT_ATTR_FN)
@@ -85,7 +90,7 @@
* This empty, zero long execution region is here to mark the end address
* of PSA RoT code.
*/
- TFM_PSA_CODE_END +0 ALIGN 32 EMPTY 0x0 {
+ TFM_PSA_CODE_END +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT EMPTY 0x0 {
}
/**** APPLICATION RoT RO part (CODE + RODATA) start here */
@@ -93,10 +98,10 @@
* This empty, zero long execution region is here to mark the start address
* of APP RoT code.
*/
- TFM_APP_CODE_START +0 ALIGN 32 EMPTY 0x0 {
+ TFM_APP_CODE_START +0 ALIGN TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT EMPTY 0x0 {
}
- TFM_APP_ROT_LINKER +0 ALIGN 32 {
+ TFM_APP_ROT_LINKER +0 ALIGN TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT {
*tfm_app_rot_partition* (+RO-CODE, +RO-DATA)
*libplatform_s* (TFM_*_APP-ROT_ATTR_FN)
*.o (TFM_*_APP-ROT_ATTR_FN)
@@ -106,7 +111,7 @@
* This empty, zero long execution region is here to mark the end address
* of APP RoT code.
*/
- TFM_APP_CODE_END +0 ALIGN 32 EMPTY 0x0 {
+ TFM_APP_CODE_END +0 ALIGN TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT EMPTY 0x0 {
}
#if defined(S_CODE_SRAM_ALIAS_BASE)
@@ -139,16 +144,16 @@
/* The code sharing between bootloader and runtime requires to share the
* global variables.
*/
- TFM_SHARED_SYMBOLS +0 ALIGN 32 EMPTY SHARED_SYMBOL_AREA_SIZE {
+ TFM_SHARED_SYMBOLS +0 ALIGN TFM_LINKER_SHARED_SYMBOLS_ALIGNMENT EMPTY SHARED_SYMBOL_AREA_SIZE {
}
#endif
/* Shared area between BL2 and runtime to exchange data */
- TFM_SHARED_DATA +0 ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
+ TFM_SHARED_DATA +0 ALIGN TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
}
/* MSP */
- ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE - 0x8 {
+ ARM_LIB_STACK +0 ALIGN TFM_LINKER_MSP_STACK_ALIGNMENT OVERLAY EMPTY S_MSP_STACK_SIZE - 0x8 {
}
STACKSEAL +0 EMPTY 0x8 {
@@ -158,7 +163,7 @@
* defined(__ARM_ARCH_8_1M_MAIN__) */
#if defined(CONFIG_TFM_PARTITION_META)
- TFM_SP_META_PTR +0 ALIGN 32 {
+ TFM_SP_META_PTR +0 ALIGN TFM_LINKER_SP_META_PTR_ALIGNMENT {
*(.bss.SP_META_PTR_SPRTL_INST)
}
#endif
@@ -168,10 +173,10 @@
* This empty, zero long execution region is here to mark the start address
* of APP RoT RW and Stack.
*/
- TFM_APP_RW_STACK_START +0 ALIGN 32 EMPTY 0x0 {
+ TFM_APP_RW_STACK_START +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
}
- TFM_APP_ROT_LINKER_DATA +0 ALIGN 32 {
+ TFM_APP_ROT_LINKER_DATA +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT {
*tfm_app_rot_partition* (+RW +ZI)
*.o(TFM_*_APP-ROT_ATTR_RW)
*.o(TFM_*_APP-ROT_ATTR_ZI)
@@ -181,7 +186,7 @@
* This empty, zero long execution region is here to mark the end address
* of APP RoT RW and Stack.
*/
- TFM_APP_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
+ TFM_APP_RW_STACK_END +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
}
#if defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_7M__) || \
@@ -197,11 +202,11 @@
* area on Armv6-M/v7-M platforms.
*/
/* Shared area between BL2 and runtime to exchange data */
- TFM_SHARED_DATA +0 ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
+ TFM_SHARED_DATA +0 ALIGN TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
}
/* MSP */
- ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE {
+ ARM_LIB_STACK +0 ALIGN TFM_LINKER_MSP_STACK_ALIGNMENT OVERLAY EMPTY S_MSP_STACK_SIZE {
}
#endif /* defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_7M__) || \
* defined(__ARM_ARCH_7EM__) */
@@ -231,10 +236,10 @@
* This empty, zero long execution region is here to mark the start address
* of PSA RoT RW and Stack.
*/
- TFM_PSA_RW_STACK_START +0 ALIGN 32 EMPTY 0x0 {
+ TFM_PSA_RW_STACK_START +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
}
- TFM_PSA_ROT_LINKER_DATA +0 ALIGN 32 {
+ TFM_PSA_ROT_LINKER_DATA +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT {
*tfm_psa_rot_partition* (+RW +ZI)
*.o(TFM_*_PSA-ROT_ATTR_RW)
*.o(TFM_*_PSA-ROT_ATTR_ZI)
@@ -244,11 +249,11 @@
* This empty, zero long execution region is here to mark the end address
* of PSA RoT RW and Stack.
*/
- TFM_PSA_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
+ TFM_PSA_RW_STACK_END +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
}
#ifdef RAM_VECTORS_SUPPORT
- ER_RAM_VECTORS +0 ALIGN 256 UNINIT {
+ ER_RAM_VECTORS +0 ALIGN TFM_LINKER_RAM_VECTORS_ALIGNMENT UNINIT {
* (RESET_RAM)
}
#endif
diff --git a/platform/ext/common/armclang/tfm_isolation_l3.sct.template b/platform/ext/common/armclang/tfm_isolation_l3.sct.template
index 73337b9..be9753f 100644
--- a/platform/ext/common/armclang/tfm_isolation_l3.sct.template
+++ b/platform/ext/common/armclang/tfm_isolation_l3.sct.template
@@ -30,8 +30,13 @@
#include "region_defs.h"
+/* Include file with definitions for section alignments.
+ * Note: it should be included after region_defs.h to let platform define
+ * default values if needed. */
+#include "tfm_s_linker_alignments.h"
+
LR_CODE S_CODE_START S_CODE_SIZE {
- PT_RO_START +0 ALIGN 32 EMPTY 0x0 {
+ PT_RO_START +0 ALIGN TFM_LINKER_PT_RO_ALIGNMENT EMPTY 0x0 {
/* Position tag: code + RO-data */
}
@@ -48,14 +53,14 @@
* 32 bytes aligned region so that the SAU can be programmed to
* just set this region as Non-Secure Callable.
*/
- ER_VENEER +0 FIXED ALIGN 32 {
+ ER_VENEER +0 FIXED ALIGN TFM_LINKER_VENEERS_ALIGNMENT {
*(Veneer$$CMSE)
}
/*
- * The Limit of the VENEER_ALIGN region should be 32 bytes aligned so that
- * the SAU can set this region as Non-Secure Callable.
+ * The Limit of the VENEER_ALIGN region should be at least 32 bytes aligned
+ * so that the SAU can set this region as Non-Secure Callable.
*/
- VENEER_ALIGN +0 ALIGN 32 EMPTY 0x0 {
+ VENEER_ALIGN +0 ALIGN TFM_LINKER_VENEERS_ALIGNMENT EMPTY 0x0 {
}
#endif
@@ -80,7 +85,7 @@
/**** PSA RoT CODE + RO-data starts here */
{% for partition in partitions %}
{% if partition.manifest.type == 'PSA-ROT' %}
- ER_{{partition.manifest.name}}_RO +0 ALIGN 32 {
+ ER_{{partition.manifest.name}}_RO +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT {
{% if partition.attr.linker_pattern.library_list %}
{% for pattern in partition.attr.linker_pattern.library_list %}
{{pattern}} (+RO-CODE, +RO-DATA)
@@ -101,7 +106,7 @@
/**** APPLICATION RoT CODE + RO-data starts here */
{% for partition in partitions %}
{% if partition.manifest.type == 'APPLICATION-ROT' %}
- ER_{{partition.manifest.name}}_RO +0 ALIGN 32 {
+ ER_{{partition.manifest.name}}_RO +0 ALIGN TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT {
{% if partition.attr.linker_pattern.library_list %}
{% for pattern in partition.attr.linker_pattern.library_list %}
{{pattern}} (+RO-CODE, +RO-DATA)
@@ -120,12 +125,12 @@
/**** APPLICATION RoT CODE + RO-data ends here */
/**** Unprivileged Secure code + RO-data starts here */
- TFM_UNPRIV_CODE +0 ALIGN 32 {
+ TFM_UNPRIV_CODE +0 ALIGN TFM_LINKER_UNPRIV_CODE_ALIGNMENT {
*(SFN)
* (+RO)
}
- PT_RO_END +0 ALIGN 32 EMPTY 0x0 {
+ PT_RO_END +0 ALIGN TFM_LINKER_PT_RO_ALIGNMENT EMPTY 0x0 {
/* Position tag */
}
@@ -134,16 +139,16 @@
/* Position tag */
}
- PT_PRIV_RWZI_START +0 ALIGN 32 EMPTY 0x0 {
+ PT_PRIV_RWZI_START +0 ALIGN TFM_LINKER_PT_PRIV_RWZI_ALIGNMENT EMPTY 0x0 {
/* Position tag */
}
/* Shared area between BL2 and runtime to exchange data */
- TFM_SHARED_DATA +0 ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
+ TFM_SHARED_DATA +0 ALIGN TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
}
/* MSP */
- ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE - 0x8 {
+ ARM_LIB_STACK +0 ALIGN TFM_LINKER_MSP_STACK_ALIGNMENT OVERLAY EMPTY S_MSP_STACK_SIZE - 0x8 {
}
STACKSEAL +0 EMPTY 0x8 {
@@ -173,11 +178,11 @@
{% for partition in partitions %}
{% if partition.manifest.type == 'PSA-ROT' %}
- PT_{{partition.manifest.name}}_PRIVATE_DATA_START +0 ALIGN 32 {
+ PT_{{partition.manifest.name}}_PRIVATE_DATA_START +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT {
/* Position tag */
}
- ER_{{partition.manifest.name}}_RWZI +0 ALIGN 32 {
+ ER_{{partition.manifest.name}}_RWZI +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT {
{% if partition.attr.linker_pattern.library_list %}
{% for pattern in partition.attr.linker_pattern.library_list %}
{{pattern}} (+RW +ZI)
@@ -192,7 +197,7 @@
*({{partition.manifest.name}}_PSA-ROT_ATTR_ZI)
}
- PT_{{partition.manifest.name}}_PRIVATE_DATA_END +0 ALIGN 32 {
+ PT_{{partition.manifest.name}}_PRIVATE_DATA_END +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT {
/* Position tag */
}
@@ -200,18 +205,18 @@
{% endfor %}
/**** PSA RoT RWZI ends here */
- PT_PRIV_RWZI_END +0 ALIGN 32 EMPTY 0x0 {
+ PT_PRIV_RWZI_END +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
/* Position tag */
}
{% for partition in partitions %}
{% if partition.manifest.type == 'APPLICATION-ROT' %}
- PT_{{partition.manifest.name}}_PRIVATE_DATA_START +0 ALIGN 32 {
+ PT_{{partition.manifest.name}}_PRIVATE_DATA_START +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT {
/* Position tag */
}
- ER_{{partition.manifest.name}}_RWZI +0 ALIGN 32 {
+ ER_{{partition.manifest.name}}_RWZI +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT {
{% if partition.attr.linker_pattern.library_list %}
{% for pattern in partition.attr.linker_pattern.library_list %}
{{pattern}} (+RW +ZI)
@@ -226,7 +231,7 @@
*({{partition.manifest.name}}_APP-ROT_ATTR_ZI)
}
- PT_{{partition.manifest.name}}_PRIVATE_DATA_END +0 ALIGN 32 {
+ PT_{{partition.manifest.name}}_PRIVATE_DATA_END +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT {
/* Position tag */
}
@@ -234,13 +239,13 @@
{% endfor %}
#if defined(CONFIG_TFM_PARTITION_META)
- TFM_SP_META_PTR +0 ALIGN 32 {
+ TFM_SP_META_PTR +0 ALIGN TFM_LINKER_SP_META_PTR_ALIGNMENT {
*(.bss.SP_META_PTR_SPRTL_INST)
}
#endif
#ifdef RAM_VECTORS_SUPPORT
- ER_RAM_VECTORS +0 ALIGN 256 UNINIT {
+ ER_RAM_VECTORS +0 ALIGN TFM_LINKER_RAM_VECTORS_ALIGNMENT UNINIT {
* (RESET_RAM)
}
#endif
diff --git a/platform/ext/common/gcc/tfm_common_s.ld b/platform/ext/common/gcc/tfm_common_s.ld
index a16135e..29561d7 100644
--- a/platform/ext/common/gcc/tfm_common_s.ld
+++ b/platform/ext/common/gcc/tfm_common_s.ld
@@ -24,6 +24,11 @@
#include "region_defs.h"
+/* Include file with definitions for section alignments.
+ * Note: it should be included after region_defs.h to let platform define
+ * default values if needed. */
+#include "tfm_s_linker_alignments.h"
+
MEMORY
{
FLASH (rx) : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE
@@ -55,13 +60,13 @@
. = ADDR(.TFM_VECTORS) + S_CODE_VECTOR_TABLE_SIZE;
/*
* Place the CMSE Veneers (containing the SG instruction) after the code, in
- * a separate 32 bytes aligned region so that the SAU can programmed to just
- * set this region as Non-Secure Callable.
+ * a separate at least 32 bytes aligned region so that the SAU can
+ * programmed to just set this region as Non-Secure Callable.
*/
- .gnu.sgstubs ALIGN(32) :
+ .gnu.sgstubs ALIGN(TFM_LINKER_VENEERS_ALIGNMENT) :
{
*(.gnu.sgstubs*)
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_VENEERS_ALIGNMENT);
} > FLASH
Image$$ER_VENEER$$Base = ADDR(.gnu.sgstubs);
Image$$VENEER_ALIGN$$Limit = ADDR(.gnu.sgstubs) + SIZEOF(.gnu.sgstubs);
@@ -134,15 +139,15 @@
Image$$TFM_SP_LOAD_LIST$$RO$$Limit = ADDR(.TFM_SP_LOAD_LIST) + SIZEOF(.TFM_SP_LOAD_LIST);
/**** PSA RoT RO part (CODE + RODATA) start here */
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT);
Image$$TFM_PSA_CODE_START$$Base = .;
- .TFM_PSA_ROT_LINKER : ALIGN(32)
+ .TFM_PSA_ROT_LINKER : ALIGN(TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT)
{
*tfm_psa_rot_partition*:*(.text*)
*tfm_psa_rot_partition*:*(.rodata*)
*(TFM_*_PSA-ROT_ATTR_FN)
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT);
} > FLASH
Image$$TFM_PSA_ROT_LINKER$$RO$$Base = ADDR(.TFM_PSA_ROT_LINKER);
@@ -156,12 +161,12 @@
/**** APPLICATION RoT RO part (CODE + RODATA) start here */
Image$$TFM_APP_CODE_START$$Base = .;
- .TFM_APP_ROT_LINKER : ALIGN(32)
+ .TFM_APP_ROT_LINKER : ALIGN(TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT)
{
*tfm_app_rot_partition*:*(.text*)
*tfm_app_rot_partition*:*(.rodata*)
*(TFM_*_APP-ROT_ATTR_FN)
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT);
} > FLASH
Image$$TFM_APP_ROT_LINKER$$RO$$Base = ADDR(.TFM_APP_ROT_LINKER);
@@ -237,7 +242,7 @@
/* The code sharing between bootloader and runtime requires to share the
* global variables.
*/
- .TFM_SHARED_SYMBOLS : ALIGN(32)
+ .TFM_SHARED_SYMBOLS : ALIGN(TFM_LINKER_SHARED_SYMBOLS_ALIGNMENT)
{
. += SHARED_SYMBOL_AREA_SIZE;
} > RAM
@@ -247,12 +252,12 @@
* msp_stack is extended until the beginning of RAM, when shared_date
* was read out by partitions
*/
- .tfm_bl2_shared_data : ALIGN(32)
+ .tfm_bl2_shared_data : ALIGN(TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT)
{
. += BOOT_TFM_SHARED_DATA_SIZE;
} > RAM
- .msp_stack : ALIGN(32)
+ .msp_stack : ALIGN(TFM_LINKER_MSP_STACK_ALIGNMENT)
{
. += __msp_stack_size__ - 0x8;
} > RAM
@@ -282,20 +287,20 @@
#endif
#if defined(CONFIG_TFM_PARTITION_META)
- .TFM_SP_META_PTR : ALIGN(32)
+ .TFM_SP_META_PTR : ALIGN(TFM_LINKER_SP_META_PTR_ALIGNMENT)
{
*(.bss.SP_META_PTR_SPRTL_INST)
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_SP_META_PTR_ALIGNMENT);
} > RAM
Image$$TFM_SP_META_PTR$$ZI$$Base = ADDR(.TFM_SP_META_PTR);
Image$$TFM_SP_META_PTR$$ZI$$Limit = ADDR(.TFM_SP_META_PTR) + SIZEOF(.TFM_SP_META_PTR);
#endif
/**** APPLICATION RoT DATA start here */
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT);
Image$$TFM_APP_RW_STACK_START$$Base = .;
- .TFM_APP_ROT_LINKER_DATA : ALIGN(32)
+ .TFM_APP_ROT_LINKER_DATA : ALIGN(TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT)
{
*tfm_app_rot_partition*:*(.data*)
*(TFM_*_APP-ROT_ATTR_RW)
@@ -311,7 +316,7 @@
*tfm_app_rot_partition*:*(COMMON)
*(TFM_*_APP-ROT_ATTR_ZI)
. += (. - start_of_TFM_APP_ROT_LINKER) ? 0 : 4;
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT);
} > RAM AT> RAM
Image$$TFM_APP_ROT_LINKER_DATA$$ZI$$Base = ADDR(.TFM_APP_ROT_LINKER_BSS);
Image$$TFM_APP_ROT_LINKER_DATA$$ZI$$Limit = ADDR(.TFM_APP_ROT_LINKER_BSS) + SIZEOF(.TFM_APP_ROT_LINKER_BSS);
@@ -338,12 +343,12 @@
* msp_stack is extended until the beginning of RAM, when shared_date
* was read out by partitions
*/
- .tfm_bl2_shared_data : ALIGN(32)
+ .tfm_bl2_shared_data : ALIGN(TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT)
{
. += BOOT_TFM_SHARED_DATA_SIZE;
} > RAM AT> RAM
- .msp_stack : ALIGN(32)
+ .msp_stack : ALIGN(TFM_LINKER_MSP_STACK_ALIGNMENT)
{
. += __msp_stack_size__;
} > RAM
@@ -356,7 +361,7 @@
Image$$TFM_PSA_RW_STACK_START$$Base = .;
- .TFM_PSA_ROT_LINKER_DATA : ALIGN(32)
+ .TFM_PSA_ROT_LINKER_DATA : ALIGN(TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT)
{
*tfm_psa_rot_partition*:*(.data*)
*(TFM_*_PSA-ROT_ATTR_RW)
@@ -372,7 +377,7 @@
*tfm_psa_rot_partition*:*(COMMON)
*(TFM_*_PSA-ROT_ATTR_ZI)
. += (. - start_of_TFM_PSA_ROT_LINKER) ? 0 : 4;
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT);
} > RAM AT> RAM
Image$$TFM_PSA_ROT_LINKER_DATA$$ZI$$Base = ADDR(.TFM_PSA_ROT_LINKER_BSS);
Image$$TFM_PSA_ROT_LINKER_DATA$$ZI$$Limit = ADDR(.TFM_PSA_ROT_LINKER_BSS) + SIZEOF(.TFM_PSA_ROT_LINKER_BSS);
@@ -380,7 +385,7 @@
/**** PSA RoT DATA end here */
Image$$TFM_PSA_RW_STACK_END$$Base = .;
- .TFM_UNPRIV_CODE : ALIGN(32)
+ .TFM_UNPRIV_CODE : ALIGN(TFM_LINKER_UNPRIV_CODE_ALIGNMENT)
{
*(SFN)
*(.text*)
@@ -405,13 +410,13 @@
*(.rodata*)
KEEP(*(.eh_frame*))
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_UNPRIV_CODE_ALIGNMENT);
} > FLASH
Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);
Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);
#ifdef RAM_VECTORS_SUPPORT
- .ramVectors (NOLOAD) : ALIGN(256)
+ .ramVectors (NOLOAD) : ALIGN(TFM_LINKER_RAM_VECTORS_ALIGNMENT)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
diff --git a/platform/ext/common/gcc/tfm_isolation_l3.ld.template b/platform/ext/common/gcc/tfm_isolation_l3.ld.template
index b1f5811..9960537 100644
--- a/platform/ext/common/gcc/tfm_isolation_l3.ld.template
+++ b/platform/ext/common/gcc/tfm_isolation_l3.ld.template
@@ -26,6 +26,11 @@
#include "region_defs.h"
+/* Include file with definitions for section alignments.
+ * Note: it should be included after region_defs.h to let platform define
+ * default values if needed. */
+#include "tfm_s_linker_alignments.h"
+
MEMORY
{
FLASH (rx) : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE
@@ -60,13 +65,13 @@
. = ADDR(.TFM_VECTORS) + S_CODE_VECTOR_TABLE_SIZE;
/*
* Place the CMSE Veneers (containing the SG instruction) after the code, in
- * a separate 32 bytes aligned region so that the SAU can programmed to just
- * set this region as Non-Secure Callable.
+ * a separate at least 32 bytes aligned region so that the SAU can
+ * programmed to just set this region as Non-Secure Callable.
*/
- .gnu.sgstubs ALIGN(32) :
+ .gnu.sgstubs ALIGN(TFM_LINKER_VENEERS_ALIGNMENT) :
{
*(.gnu.sgstubs*)
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_VENEERS_ALIGNMENT);
} > FLASH
Image$$ER_VENEER$$Base = ADDR(.gnu.sgstubs);
Image$$VENEER_ALIGN$$Limit = ADDR(.gnu.sgstubs) + SIZEOF(.gnu.sgstubs);
@@ -129,10 +134,10 @@
Image$$TFM_SP_LOAD_LIST$$RO$$Limit = ADDR(.TFM_SP_LOAD_LIST) + SIZEOF(.TFM_SP_LOAD_LIST);
/**** PSA RoT RO CODE + RO-data starts here */
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT);
{% for partition in partitions %}
{% if partition.manifest.type == 'PSA-ROT' %}
- .{{partition.manifest.name}}_RO : ALIGN(32)
+ .{{partition.manifest.name}}_RO : ALIGN(TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT)
{
{% if partition.attr.linker_pattern.library_list %}
{% for pattern in partition.attr.linker_pattern.library_list %}
@@ -147,7 +152,7 @@
{% endfor %}
{% endif %}
*({{partition.manifest.name}}_PSA-ROT_ATTR_FN)
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT);
} > FLASH
Image$${{partition.manifest.name}}_RO$$Base = ADDR(.{{partition.manifest.name}}_RO);
Image$${{partition.manifest.name}}_RO$$Limit = ADDR(.{{partition.manifest.name}}_RO) + SIZEOF(.{{partition.manifest.name}}_RO);
@@ -159,7 +164,7 @@
/**** APPLICATION RoT RO CODE + data starts here */
{% for partition in partitions %}
{% if partition.manifest.type == 'APPLICATION-ROT' %}
- .{{partition.manifest.name}}_RO : ALIGN(32)
+ .{{partition.manifest.name}}_RO : ALIGN(TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT)
{
{% if partition.attr.linker_pattern.library_list %}
{% for pattern in partition.attr.linker_pattern.library_list %}
@@ -174,7 +179,7 @@
{% endfor %}
{% endif %}
*({{partition.manifest.name}}_APP-ROT_ATTR_FN)
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT);
} > FLASH
Image$${{partition.manifest.name}}_CODE$$Base = ADDR(.{{partition.manifest.name}}_RO);
Image$${{partition.manifest.name}}_CODE$$Limit = ADDR(.{{partition.manifest.name}}_RO) + SIZEOF(.{{partition.manifest.name}}_RO);
@@ -209,7 +214,7 @@
} > FLASH
/**** Unprivileged Secure code starts here */
- .ER_UNPRIV_CODE : ALIGN(32)
+ .ER_UNPRIV_CODE : ALIGN(TFM_LINKER_UNPRIV_CODE_ALIGNMENT)
{
*(SFN)
*(.text*)
@@ -235,13 +240,13 @@
KEEP(*(.eh_frame*))
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_UNPRIV_CODE_ALIGNMENT);
} > FLASH
Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.ER_UNPRIV_CODE);
Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.ER_UNPRIV_CODE) + SIZEOF(.ER_UNPRIV_CODE);
/* Position tag */
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_PT_RO_ALIGNMENT);
Image$$PT_RO_END$$Base = .;
.ARM.extab :
@@ -263,19 +268,19 @@
} > RAM
/* Position tag */
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_PT_PRIV_RWZI_ALIGNMENT);
Image$$PT_PRIV_RWZI_START$$Base = .;
/* shared_data and msp_stack are overlapping on purpose when
* msp_stack is extended until the beginning of RAM, when shared_date
* was read out by partitions
*/
- .tfm_bl2_shared_data : ALIGN(32)
+ .tfm_bl2_shared_data : ALIGN(TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT)
{
. += BOOT_TFM_SHARED_DATA_SIZE;
} > RAM
- .msp_stack : ALIGN(32)
+ .msp_stack : ALIGN(TFM_LINKER_MSP_STACK_ALIGNMENT)
{
. += __msp_stack_size__ - 0x8;
} > RAM
@@ -306,10 +311,10 @@
{% if partition.manifest.type == 'PSA-ROT' %}
/* Position tag */
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT);
Image$$PT_{{partition.manifest.name}}_PRIVATE_DATA_START$$Base = .;
- .ER_{{partition.manifest.name}}_RWZI : ALIGN(32)
+ .ER_{{partition.manifest.name}}_RWZI : ALIGN(TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT)
{
{% if partition.attr.linker_pattern.library_list %}
{% for pattern in partition.attr.linker_pattern.library_list %}
@@ -344,19 +349,19 @@
{% endif %}
*({{partition.manifest.name}}_PSA-ROT_ATTR_ZI)
. += (. - start_of_{{partition.manifest.name}}_RWZI) ? 0 : 4;
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT);
} > RAM AT> RAM
Image$$ER_{{partition.manifest.name}}_RWZI$$ZI$$Base = ADDR(.{{partition.manifest.name}}_RWZI_BSS);
Image$$ER_{{partition.manifest.name}}_RWZI$$ZI$$Limit = ADDR(.{{partition.manifest.name}}_RWZI_BSS) + SIZEOF(.{{partition.manifest.name}}_RWZI_BSS);
/* Position tag */
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT);
Image$$PT_{{partition.manifest.name}}_PRIVATE_DATA_END$$Base = .;
{% endif %}
{% endfor %}
/**** PSA RoT DATA end here */
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_PT_PRIV_RWZI_ALIGNMENT);
/* Position tag */
Image$$PT_PRIV_RWZI_END$$Base = .;
@@ -365,10 +370,10 @@
{% for partition in partitions %}
{% if partition.manifest.type == 'APPLICATION-ROT' %}
/* Position tag */
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT);
Image$$PT_{{partition.manifest.name}}_PRIVATE_DATA_START$$Base = .;
- .ER_{{partition.manifest.name}}_RWZI : ALIGN(32)
+ .ER_{{partition.manifest.name}}_RWZI : ALIGN(TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT)
{
{% if partition.attr.linker_pattern.library_list %}
{% for pattern in partition.attr.linker_pattern.library_list %}
@@ -403,13 +408,13 @@
{% endif %}
*({{partition.manifest.name}}_APP-ROT_ATTR_ZI)
. += (. - start_of_{{partition.manifest.name}}_RWZI) ? 0 : 4;
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT);
} > RAM AT> RAM
Image$$ER_{{partition.manifest.name}}_RWZI$$ZI$$Base = ADDR(.{{partition.manifest.name}}_RWZI_BSS);
Image$$ER_{{partition.manifest.name}}_RWZI$$ZI$$Limit = ADDR(.{{partition.manifest.name}}_RWZI_BSS) + SIZEOF(.{{partition.manifest.name}}_RWZI_BSS);
/* Position tag */
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT);
Image$$PT_{{partition.manifest.name}}_PRIVATE_DATA_END$$Base = .;
{% endif %}
@@ -417,11 +422,11 @@
/**** APPLICATION RoT DATA end here */
/* Position tag */
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT);
Image$$PT_APP_RWZI_END$$Base = .;
#ifdef RAM_VECTORS_SUPPORT
- .ramVectors (NOLOAD) : ALIGN(256)
+ .ramVectors (NOLOAD) : ALIGN(TFM_LINKER_RAM_VECTORS_ALIGNMENT)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
@@ -463,10 +468,10 @@
Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);
#if defined(CONFIG_TFM_PARTITION_META)
- .TFM_SP_META_PTR : ALIGN(32)
+ .TFM_SP_META_PTR : ALIGN(TFM_LINKER_SP_META_PTR_ALIGNMENT)
{
*(.bss.SP_META_PTR_SPRTL_INST)
- . = ALIGN(32);
+ . = ALIGN(TFM_LINKER_SP_META_PTR_ALIGNMENT);
} > RAM AT> RAM
Image$$TFM_SP_META_PTR$$ZI$$Base = ADDR(.TFM_SP_META_PTR);
Image$$TFM_SP_META_PTR$$ZI$$Limit = ADDR(.TFM_SP_META_PTR) + SIZEOF(.TFM_SP_META_PTR);
diff --git a/platform/ext/common/iar/tfm_common_s.icf b/platform/ext/common/iar/tfm_common_s.icf
index 2a41888..259b574 100644
--- a/platform/ext/common/iar/tfm_common_s.icf
+++ b/platform/ext/common/iar/tfm_common_s.icf
@@ -21,6 +21,11 @@
#include "region_defs.h"
+/* Include file with definitions for section alignments.
+ * Note: it should be included after region_defs.h to let platform define
+ * default values if needed. */
+#include "tfm_s_linker_alignments.h"
+
define block ER_VECTORS with size = S_CODE_VECTOR_TABLE_SIZE {
readonly section .intvec
};
@@ -28,12 +33,12 @@
#ifdef CONFIG_TFM_USE_TRUSTZONE
/*
* Place the CMSE Veneers (containing the SG instruction) in a separate
- * 32 bytes aligned region so that the SAU can be programmed to
+ * at least 32 bytes aligned region so that the SAU can be programmed to
* just set this region as Non-Secure Callable.
*/
-define block ER_VENEER with alignment = 0x20 {section Veneer$$CMSE};
+define block ER_VENEER with alignment = TFM_LINKER_VENEERS_ALIGNMENT {section Veneer$$CMSE};
-define block VENEER_ALIGN with alignment = 0x20, size = 0 { };
+define block VENEER_ALIGN with alignment = TFM_LINKER_VENEERS_ALIGNMENT, size = 0 { };
#endif
define block ER_TFM_CODE with fixed order, alignment = 8, maximum size = S_CODE_SIZE {
@@ -43,7 +48,7 @@
ro object *libtfm_spm*,
};
-define block TFM_UNPRIV_CODE with alignment = 32 {
+define block TFM_UNPRIV_CODE with alignment = TFM_LINKER_UNPRIV_CODE_ALIGNMENT {
section SFN,
readonly
};
@@ -65,9 +70,9 @@
* This empty, zero long execution region is here to mark the start address
* of PSA RoT code.
*/
-define block TFM_PSA_CODE_START with alignment = 32, size = 0 { };
+define block TFM_PSA_CODE_START with alignment = TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT, size = 0 { };
-define block TFM_PSA_ROT_LINKER with alignment = 32 {
+define block TFM_PSA_ROT_LINKER with alignment = TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT {
ro object *tfm_psa_rot_partition*,
section TFM_*_PSA-ROT_ATTR_FN object *libplatform_s*,
section TFM_*_PSA-ROT_ATTR_FN object *.o,
@@ -77,16 +82,16 @@
* This empty, zero long execution region is here to mark the end address
* of PSA RoT code.
*/
-define block TFM_PSA_CODE_END with alignment = 32, size = 0 { };
+define block TFM_PSA_CODE_END with alignment = TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT, size = 0 { };
/**** APPLICATION RoT RO part (CODE + RODATA) start here */
/*
* This empty, zero long execution region is here to mark the start address
* of APP RoT code.
*/
-define block TFM_APP_CODE_START with alignment = 32, size = 0 { };
+define block TFM_APP_CODE_START with alignment = TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT, size = 0 { };
- define block TFM_APP_ROT_LINKER with alignment = 32 {
+ define block TFM_APP_ROT_LINKER with alignment = TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT {
ro object *tfm_app_rot_partition*,
};
@@ -94,7 +99,7 @@
* This empty, zero long execution region is here to mark the end address
* of APP RoT code.
*/
-define block TFM_APP_CODE_END with alignment = 32, size = 0 { };
+define block TFM_APP_CODE_END with alignment = TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT, size = 0 { };
#if defined(S_CODE_SRAM_ALIAS_BASE)
/* eFlash driver code that gets copied from Flash to SRAM */
@@ -119,8 +124,8 @@
(defined(__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) || \
(defined(__ARM8EM_MAINLINE__) && (__CORE__ == __ARM8EM_MAINLINE__)))
/* Shared area between BL2 and runtime to exchange data */
-define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
-define block ARM_LIB_STACK with alignment = 32, size = S_MSP_STACK_SIZE - 0x8 { };
+define block TFM_SHARED_DATA with alignment = TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT, size = BOOT_TFM_SHARED_DATA_SIZE { };
+define block ARM_LIB_STACK with alignment = TFM_LINKER_MSP_STACK_ALIGNMENT, size = S_MSP_STACK_SIZE - 0x8 { };
define overlay STACK_DATA {block TFM_SHARED_DATA};
define overlay STACK_DATA {block ARM_LIB_STACK};
@@ -132,14 +137,14 @@
* (defined(__ARM8EM_MAINLINE__) && (__CORE__ == __ARM8EM_MAINLINE__)) */
#if defined(CONFIG_TFM_PARTITION_META)
-define block TFM_SP_META_PTR with alignment = 32 {
+define block TFM_SP_META_PTR with alignment = TFM_LINKER_SP_META_PTR_ALIGNMENT {
zi section .bss.SP_META_PTR_SPRTL_INST
};
#endif
-define block TFM_APP_RW_STACK_START with alignment = 32, size = 0 { };
+define block TFM_APP_RW_STACK_START with alignment = TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT, size = 0 { };
-define block TFM_APP_ROT_LINKER_DATA with alignment = 32 {
+define block TFM_APP_ROT_LINKER_DATA with alignment = TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT {
rw object *tfm_app_rot_partition*,
section TFM_*_APP-ROT_ATTR_RW object *.o,
section TFM_*_APP-ROT_ATTR_ZI object *.o,
@@ -150,7 +155,7 @@
* This empty, zero long execution region is here to mark the end address
* of APP RoT RW and Stack.
*/
-define block TFM_APP_RW_STACK_END with alignment = 32, size = 0 { };
+define block TFM_APP_RW_STACK_END with alignment = TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT, size = 0 { };
#if ((defined(__ARM6M__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARM7M__) && (__CORE__ == __ARM7M__)) || \
@@ -165,10 +170,10 @@
* area on Armv6-M/v7-M platforms.
*/
/* Shared area between BL2 and runtime to exchange data */
-define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
+define block TFM_SHARED_DATA with alignment = TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT, size = BOOT_TFM_SHARED_DATA_SIZE { };
/* MSP */
-define block ARM_LIB_STACK with alignment = 32, size = S_MSP_STACK_SIZE { };
+define block ARM_LIB_STACK with alignment = TFM_LINKER_MSP_STACK_ALIGNMENT, size = S_MSP_STACK_SIZE { };
define overlay STACK_DATA {block TFM_SHARED_DATA};
define overlay STACK_DATA {block ARM_LIB_STACK};
@@ -209,9 +214,9 @@
* This empty, zero long execution region is here to mark the start address
* of PSA RoT RW and Stack.
*/
-define block TFM_PSA_RW_STACK_START with alignment = 32, size = 0 { };
+define block TFM_PSA_RW_STACK_START with alignment = TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT, size = 0 { };
-define block TFM_PSA_ROT_LINKER_DATA with alignment = 32 {
+define block TFM_PSA_ROT_LINKER_DATA with alignment = TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT {
rw object *tfm_psa_rot_partition*,
section TFM_*_PSA-ROT_ATTR_RW object *.o,
section TFM_*_PSA-ROT_ATTR_ZI object *.o,
@@ -222,10 +227,10 @@
* This empty, zero long execution region is here to mark the end address
* of PSA RoT RW and Stack.
*/
-define block TFM_PSA_RW_STACK_END with alignment = 32, size = 0x0 { };
+define block TFM_PSA_RW_STACK_END with alignment = TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT, size = 0x0 { };
#ifdef RAM_VECTORS_SUPPORT
-define block ER_RAM_VECTORS with alignment = 256 { section .ramvec };
+define block ER_RAM_VECTORS with alignment = TFM_LINKER_RAM_VECTORS_ALIGNMENT { section .ramvec };
#endif
#if defined (S_RAM_CODE_START)
diff --git a/platform/ext/common/iar/tfm_isolation_l3.icf.template b/platform/ext/common/iar/tfm_isolation_l3.icf.template
index d1a757a..0a7b48c 100644
--- a/platform/ext/common/iar/tfm_isolation_l3.icf.template
+++ b/platform/ext/common/iar/tfm_isolation_l3.icf.template
@@ -29,9 +29,15 @@
*/
#include "region_defs.h"
+
+/* Include file with definitions for section alignments.
+ * Note: it should be included after region_defs.h to let platform define
+ * default values if needed. */
+#include "tfm_s_linker_alignments.h"
+
/* position tag block : code + RO-data */
-define block PT_RO_START with alignment = 32, size = 0 { };
-define block PT_RO_END with alignment = 32, size = 0 { };
+define block PT_RO_START with alignment = TFM_LINKER_PT_RO_ALIGNMENT, size = 0 { };
+define block PT_RO_END with alignment = TFM_LINKER_PT_RO_ALIGNMENT, size = 0 { };
define block ER_VECTORS with size = S_CODE_VECTOR_TABLE_SIZE {
readonly section .intvec
@@ -40,12 +46,12 @@
#ifdef CONFIG_TFM_USE_TRUSTZONE
/*
* Place the CMSE Veneers (containing the SG instruction) in a separate
- * 32 bytes aligned region so that the SAU can be programmed to
+ * at least 32 bytes aligned region so that the SAU can be programmed to
* just set this region as Non-Secure Callable.
*/
-define block ER_VENEER with alignment = 0x20 {section Veneer$$CMSE};
+define block ER_VENEER with alignment = TFM_LINKER_VENEERS_ALIGNMENT {section Veneer$$CMSE};
-define block VENEER_ALIGN with alignment = 0x20, size = 0 { };
+define block VENEER_ALIGN with alignment = TFM_LINKER_VENEERS_ALIGNMENT, size = 0 { };
#endif
define block ER_TFM_CODE with fixed order, alignment = 8 {
@@ -84,7 +90,7 @@
/**** blocks CODE + RO-data definition starts here */
{% for partition in partitions %}
-define block ER_{{partition.manifest.name}}_RO with alignment = 32
+define block ER_{{partition.manifest.name}}_RO with alignment = {{ 'TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT' if partition.manifest.type == 'PSA-ROT' else 'TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT' }}
{
{% if partition.attr.linker_pattern.library_list %}
{% for pattern in partition.attr.linker_pattern.library_list %}
@@ -108,19 +114,18 @@
/**** blocks CODE + RO-data definition ends here*/
/**** Block Unprivileged Secure code + RO-data definition starts here */
-define block TFM_UNPRIV_CODE with alignment = 32 {
+define block TFM_UNPRIV_CODE with alignment = TFM_LINKER_UNPRIV_CODE_ALIGNMENT {
section SFN,
readonly
};
/* position tag block : base address of secure data area ( S_DATA_START)*/
-define block PT_SECURE_DATA_START with alignment = 32, size = 0 { };
-define block PT_PRIV_RWZI_START with alignment = 32, size = 0 { };
+define block PT_SECURE_DATA_START with alignment = TFM_LINKER_SECURE_DATA_ALIGNMENT, size = 0 { };
+define block PT_PRIV_RWZI_START with alignment = TFM_LINKER_PT_PRIV_RWZI_ALIGNMENT, size = 0 { };
-define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
-define block ARM_LIB_STACK with alignment = 32, size = S_MSP_STACK_SIZE - 0x8 { };
-
+define block TFM_SHARED_DATA with alignment = TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT, size = BOOT_TFM_SHARED_DATA_SIZE { };
+define block ARM_LIB_STACK with alignment = TFM_LINKER_MSP_STACK_ALIGNMENT, size = S_MSP_STACK_SIZE - 0x8 { };
define block STACKSEAL with size = 0x8 { };
#if defined(ENABLE_HEAP)
@@ -153,9 +158,9 @@
{% for partition in partitions %}
{% if partition.manifest.type == 'PSA-ROT' %}
/* Position tag : start Block :*/
- define block PT_{{partition.manifest.name}}_PRIVATE_DATA_START with alignment = 32, size = 0 { };
+ define block PT_{{partition.manifest.name}}_PRIVATE_DATA_START with alignment = TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT, size = 0 { };
- define block ER_{{partition.manifest.name}}_RWZI with alignment = 32 {
+ define block ER_{{partition.manifest.name}}_RWZI with alignment = TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT {
{% if partition.attr.linker_pattern.library_list %}
{% for pattern in partition.attr.linker_pattern.library_list %}
rw section .data object {{pattern}},
@@ -171,19 +176,19 @@
section {{partition.manifest.name}}_PSA-ROT_ATTR_ZI,
};
/* Position tag : start Block :*/
- define block PT_{{partition.manifest.name}}_PRIVATE_DATA_END with alignment = 32, size = 0 { };
+ define block PT_{{partition.manifest.name}}_PRIVATE_DATA_END with alignment = TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT, size = 0 { };
{% endif %}
{% endfor %}
/**** block Position tag PSA RoT RWZI ends definition */
-define block PT_PRIV_RWZI_END with alignment = 32, size = 0 { };
+define block PT_PRIV_RWZI_END with alignment = TFM_LINKER_PT_PRIV_RWZI_ALIGNMENT, size = 0 { };
{% for partition in partitions %}
{% if partition.manifest.type == 'APPLICATION-ROT' %}
/* Position tag : start Block :*/
- define block PT_{{partition.manifest.name}}_PRIVATE_DATA_START with alignment = 32, size = 0 { };
+ define block PT_{{partition.manifest.name}}_PRIVATE_DATA_START with alignment = TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT, size = 0 { };
- define block ER_{{partition.manifest.name}}_RWZI with alignment = 32 {
+ define block ER_{{partition.manifest.name}}_RWZI with alignment = TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT {
{% if partition.attr.linker_pattern.library_list %}
{% for pattern in partition.attr.linker_pattern.library_list %}
rw section .data object {{pattern}},
@@ -199,21 +204,21 @@
section {{partition.manifest.name}}_APP-ROT_ATTR_ZI,
};
/* Position tag : start Block :*/
- define block PT_{{partition.manifest.name}}_PRIVATE_DATA_END with alignment = 32, size = 0 { };
+ define block PT_{{partition.manifest.name}}_PRIVATE_DATA_END with alignment = TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT, size = 0 { };
{% endif %}
{% endfor %}
#if defined(CONFIG_TFM_PARTITION_META)
-define block TFM_SP_META_PTR with alignment = 32 {
+define block TFM_SP_META_PTR with alignment = TFM_LINKER_SP_META_PTR_ALIGNMENT {
zi section .bss.SP_META_PTR_SPRTL_INST
};
#endif
#ifdef RAM_VECTORS_SUPPORT
-define block ER_RAM_VECTORS with alignment = 256 { section .ramvec };
+define block ER_RAM_VECTORS with alignment = TFM_LINKER_RAM_VECTORS_ALIGNMENT { section .ramvec };
#endif
-define block PT_SRAM_WATERMARK with alignment = 32, size = 0 { };
+define block PT_SRAM_WATERMARK with alignment = TFM_LINKER_SECURE_DATA_ALIGNMENT, size = 0 { };
/* Define Flash content */
define block LR_CODE with fixed order {
diff --git a/platform/ext/common/tfm_s_linker_alignments.h b/platform/ext/common/tfm_s_linker_alignments.h
new file mode 100644
index 0000000..6a92396
--- /dev/null
+++ b/platform/ext/common/tfm_s_linker_alignments.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company)
+ * or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/* This file defines default alignments for TFM secure linker script sections.
+ * If needed, platform may define some/all of them in its' region_defs.h
+ * file.*/
+
+#ifndef __TFM_S_LINKER_ALIGNMENTS__
+#define __TFM_S_LINKER_ALIGNMENTS__
+
+/* Default alignment for linker file sections is set to 32 because ARM TrustZone
+ * protection units (SAU and MPU) require regions to be 32 bytes aligned. */
+#ifndef TFM_LINKER_DEFAULT_ALIGNMENT
+#define TFM_LINKER_DEFAULT_ALIGNMENT 32
+#endif
+
+#ifndef TFM_LINKER_VENEERS_ALIGNMENT
+#define TFM_LINKER_VENEERS_ALIGNMENT TFM_LINKER_DEFAULT_ALIGNMENT
+#endif
+
+#ifndef TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT
+#define TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT TFM_LINKER_DEFAULT_ALIGNMENT
+#endif
+
+#ifndef TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT
+#define TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT TFM_LINKER_DEFAULT_ALIGNMENT
+#endif
+
+#ifndef TFM_LINKER_SHARED_SYMBOLS_ALIGNMENT
+#define TFM_LINKER_SHARED_SYMBOLS_ALIGNMENT TFM_LINKER_DEFAULT_ALIGNMENT
+#endif
+
+#ifndef TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT
+#define TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT TFM_LINKER_DEFAULT_ALIGNMENT
+#endif
+
+#ifndef TFM_LINKER_MSP_STACK_ALIGNMENT
+#define TFM_LINKER_MSP_STACK_ALIGNMENT TFM_LINKER_DEFAULT_ALIGNMENT
+#endif
+
+#ifndef TFM_LINKER_SP_META_PTR_ALIGNMENT
+#define TFM_LINKER_SP_META_PTR_ALIGNMENT TFM_LINKER_DEFAULT_ALIGNMENT
+#endif
+
+#ifndef TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT
+#define TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT TFM_LINKER_DEFAULT_ALIGNMENT
+#endif
+
+#ifndef TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT
+#define TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT TFM_LINKER_DEFAULT_ALIGNMENT
+#endif
+
+#ifndef TFM_LINKER_UNPRIV_CODE_ALIGNMENT
+#define TFM_LINKER_UNPRIV_CODE_ALIGNMENT TFM_LINKER_DEFAULT_ALIGNMENT
+#endif
+
+#ifndef TFM_LINKER_PT_RO_ALIGNMENT
+#define TFM_LINKER_PT_RO_ALIGNMENT TFM_LINKER_DEFAULT_ALIGNMENT
+#endif
+
+#ifndef TFM_LINKER_PT_PRIV_RWZI_ALIGNMENT
+#define TFM_LINKER_PT_PRIV_RWZI_ALIGNMENT TFM_LINKER_DEFAULT_ALIGNMENT
+#endif
+
+#ifndef TFM_LINKER_SECURE_DATA_ALIGNMENT
+#define TFM_LINKER_SECURE_DATA_ALIGNMENT TFM_LINKER_DEFAULT_ALIGNMENT
+#endif
+
+/* Alignment of RAM vector table */
+#ifndef TFM_LINKER_RAM_VECTORS_ALIGNMENT
+#define TFM_LINKER_RAM_VECTORS_ALIGNMENT 256
+#endif
+
+#endif /* __TFM_S_LINKER_ALIGNMENTS__ */