Platform: Add full support for PSoC64 platform
Add support for the Cypress CYS0644ABZI-S2D44 board.
This support was developed over the course of 2019 in
the feature-twincpu branch. Full commit history is
available there.
Signed-off-by: Chris Brand <chris.brand@cypress.com>
Change-Id: I709633d04227b71aea87aee84fd63a48c7d26fb1
diff --git a/configs/ConfigCoreIPC.cmake b/configs/ConfigCoreIPC.cmake
index bcee297..7d3e007 100644
--- a/configs/ConfigCoreIPC.cmake
+++ b/configs/ConfigCoreIPC.cmake
@@ -29,6 +29,8 @@
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_b1.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_S1")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_s1.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "psoc64")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64.cmake")
else()
message(FATAL_ERROR "ERROR: Target \"${TARGET_PLATFORM}\" is not supported.")
endif()
diff --git a/configs/ConfigCoreIPCTfmLevel2.cmake b/configs/ConfigCoreIPCTfmLevel2.cmake
index 873fb85..605c145 100644
--- a/configs/ConfigCoreIPCTfmLevel2.cmake
+++ b/configs/ConfigCoreIPCTfmLevel2.cmake
@@ -29,6 +29,8 @@
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_b1.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_S1")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_s1.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "psoc64")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64.cmake")
else()
message(FATAL_ERROR "ERROR: Target \"${TARGET_PLATFORM}\" is not supported.")
endif()
diff --git a/configs/ConfigPsaApiTestIPC.cmake b/configs/ConfigPsaApiTestIPC.cmake
index 1bede26..bfcc834 100644
--- a/configs/ConfigPsaApiTestIPC.cmake
+++ b/configs/ConfigPsaApiTestIPC.cmake
@@ -25,6 +25,8 @@
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_b1.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "AN524")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps3AN524.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "psoc64")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64.cmake")
else()
message(FATAL_ERROR "ERROR: Target \"${TARGET_PLATFORM}\" is not supported.")
endif()
diff --git a/configs/ConfigPsaApiTestIPCTfmLevel2.cmake b/configs/ConfigPsaApiTestIPCTfmLevel2.cmake
index 55acf45..ee9abbe 100644
--- a/configs/ConfigPsaApiTestIPCTfmLevel2.cmake
+++ b/configs/ConfigPsaApiTestIPCTfmLevel2.cmake
@@ -23,6 +23,8 @@
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_b1.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "AN524")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps3AN524.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "psoc64")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64.cmake")
else()
message(FATAL_ERROR "ERROR: Target \"${TARGET_PLATFORM}\" is not supported.")
endif()
diff --git a/configs/ConfigRegressionIPC.cmake b/configs/ConfigRegressionIPC.cmake
index 5172f37..c1999b6 100644
--- a/configs/ConfigRegressionIPC.cmake
+++ b/configs/ConfigRegressionIPC.cmake
@@ -29,6 +29,8 @@
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_b1.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_S1")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_s1.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "psoc64")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64.cmake")
else()
message(FATAL_ERROR "ERROR: Target \"${TARGET_PLATFORM}\" is not supported.")
endif()
diff --git a/configs/ConfigRegressionIPCTfmLevel2.cmake b/configs/ConfigRegressionIPCTfmLevel2.cmake
index 58fc0da..15f86eb 100644
--- a/configs/ConfigRegressionIPCTfmLevel2.cmake
+++ b/configs/ConfigRegressionIPCTfmLevel2.cmake
@@ -29,6 +29,8 @@
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_b1.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_S1")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_s1.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "psoc64")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/psoc64.cmake")
else()
message(FATAL_ERROR "ERROR: Target \"${TARGET_PLATFORM}\" is not supported.")
endif()
diff --git a/docs/user_guides/tfm_build_instruction.rst b/docs/user_guides/tfm_build_instruction.rst
index db6e0fe..16d8945 100644
--- a/docs/user_guides/tfm_build_instruction.rst
+++ b/docs/user_guides/tfm_build_instruction.rst
@@ -212,6 +212,9 @@
``-DTARGET_PLATFORM=MUSCA_S1``
- Cortex-M33 SSE-200 subsystem for MPS3 (AN524)
``-DTARGET_PLATFORM=AN524``
+ - Cypress CYS0644ABZI-S2D44 board (PSoC64 platform)
+ ``-DTARGET_PLATFORM=psoc64``
+ See :doc:`Cypress PSoC 64 platform specifics </platform/ext/target/cypress/psoc64/cypress_psoc_64_spec>`
* - -DCOMPILER=<compiler name>
- Specifies the compiler toolchain
diff --git a/docs/user_guides/tfm_secure_boot.rst b/docs/user_guides/tfm_secure_boot.rst
index 3c63258..d36c428 100644
--- a/docs/user_guides/tfm_secure_boot.rst
+++ b/docs/user_guides/tfm_secure_boot.rst
@@ -239,6 +239,8 @@
+----------+-----------------+---------------+----------+-------------+-----------------+
| AN524 | Yes | No | No | Yes | No |
+----------+-----------------+---------------+----------+-------------+-----------------+
+| PSoC64 | Yes | No | No | No | No |
++----------+-----------------+---------------+----------+-------------+-----------------+
.. [1] To disable BL2, please turn off the ``BL2`` compiler switch in the
build configuration file (``bl2/ext/mcuboot/MCUBootConfig.cmake``) or
diff --git a/platform/ext/psoc64.cmake b/platform/ext/psoc64.cmake
new file mode 100644
index 0000000..318deca
--- /dev/null
+++ b/platform/ext/psoc64.cmake
@@ -0,0 +1,232 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+# Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+#This file gathers all Cypress PSoC 6 specific files in the application.
+
+include("Common/MultiCore")
+
+# Select configuration of multi-core topology
+enable_multi_core_topology_config()
+
+set(TFM_NS_CLIENT_IDENTIFICATION OFF)
+
+add_definitions(-DCYB0644ABZI_S2D44=1)
+
+add_definitions(-DTFM_CORE_DEBUG)
+
+# psoc64 platform doesn't yet use TF-M BL2
+set(BL2 False)
+remove_definitions(-DBL2)
+
+# Skip Core Test temporarily
+set(CORE_TEST OFF)
+# Skip peripheral access test
+set(TFM_ENABLE_PERIPH_ACCESS_TEST OFF)
+
+# Set Cortex-M0plus as secure core
+set_secure_cpu_type("CpuM0p")
+# Set Cortex-M4 as non-secure core
+set_ns_cpu_type("CpuM4")
+
+# Set PSoC62 specific secure definitions
+add_platform_secure_definitions(CY_PSOC6_CM0P=1)
+
+set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR})
+
+#Specify the location of platform specific build dependencies.
+if(COMPILER STREQUAL "ARMCLANG")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/armclang/tfm_common_s.sct")
+ set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/cypress/psoc64/Device/Source/armclang/psoc6_ns.sct")
+ if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib")
+ endif()
+elseif(COMPILER STREQUAL "GNUARM")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/gcc/tfm_common_s.ld")
+ set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/cypress/psoc64/Device/Source/gcc/psoc6_ns.ld")
+ if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ # [libRTX_CM3.a should be used for CM4 without FPU]
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a")
+ endif()
+else()
+ message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
+endif()
+set (FLASH_LAYOUT "${PLATFORM_DIR}/target/cypress/psoc64/partition/flash_layout.h")
+set (PLATFORM_LINK_INCLUDES "${PLATFORM_DIR}/target/cypress/psoc64/partition")
+
+embedded_include_directories(PATH "${PLATFORM_DIR}/cmsis" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/cypress/psoc64" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/cypress/psoc64/CMSIS_Driver/Config" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/cypress/psoc64/Device/Config" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/cypress/psoc64/Device/Include" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/include" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/generated_source" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/cypress/psoc64/mailbox" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/cypress/psoc64/partition" ABSOLUTE)
+embedded_include_directories(PATH "${TFM_ROOT_DIR}/interface/include" ABSOLUTE)
+embedded_include_directories(PATH "${TFM_ROOT_DIR}/platform/include" ABSOLUTE)
+embedded_include_directories(PATH "${TFM_ROOT_DIR}/secure_fw/core/arch/include" ABSOLUTE)
+embedded_include_directories(PATH "${TFM_ROOT_DIR}/secure_fw/core/ipc/include" ABSOLUTE)
+
+#Gather all source files we need.
+list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/mailbox/platform_multicore.c")
+list(APPEND ALL_SRC_C_NS "${PLATFORM_DIR}/target/cypress/psoc64/mailbox/platform_ns_mailbox.c")
+list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/cypress/psoc64/mailbox/mailbox_ipc_intr.c")
+list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/cypress/psoc64/mailbox/platform_spe_mailbox.c")
+
+install(FILES ${PLATFORM_DIR}/target/cypress/psoc64/mailbox/ns_ipc_config.h
+ ${PLATFORM_DIR}/target/cypress/psoc64/mailbox/platform_multicore.h
+ DESTINATION export/tfm/inc)
+
+install(FILES ${PLATFORM_DIR}/target/cypress/psoc64/mailbox/platform_multicore.c
+ ${PLATFORM_DIR}/target/cypress/psoc64/mailbox/platform_ns_mailbox.c
+ DESTINATION export/tfm/src)
+
+if (NOT DEFINED BUILD_CMSIS_CORE)
+ message(FATAL_ERROR "Configuration variable BUILD_CMSIS_CORE (true|false) is undefined!")
+elseif(BUILD_CMSIS_CORE)
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/cypress/psoc64/Device/Source/system_psoc6_cm0plus.c")
+ list(APPEND ALL_SRC_C_NS "${PLATFORM_DIR}/target/cypress/psoc64/Device/Source/system_psoc6_cm4.c")
+endif()
+
+if (NOT DEFINED BUILD_RETARGET)
+ message(FATAL_ERROR "Configuration variable BUILD_RETARGET (true|false) is undefined!")
+elseif(BUILD_RETARGET)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Device/Source/device_definition.c")
+endif()
+
+if (NOT DEFINED BUILD_UART_STDOUT)
+ message(FATAL_ERROR "Configuration variable BUILD_UART_STDOUT (true|false) is undefined!")
+elseif(BUILD_UART_STDOUT)
+ if (NOT DEFINED SECURE_UART1)
+ message(FATAL_ERROR "Configuration variable SECURE_UART1 (true|false) is undefined!")
+ elseif(SECURE_UART1)
+ message(FATAL_ERROR "Configuration SECURE_UART1 TRUE is invalid for this target!")
+ endif()
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/common/uart_stdout.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/common" ABSOLUTE)
+ set(BUILD_NATIVE_DRIVERS true)
+ set(BUILD_CMSIS_DRIVERS true)
+endif()
+
+if (NOT DEFINED BUILD_NATIVE_DRIVERS)
+ message(FATAL_ERROR "Configuration variable BUILD_NATIVE_DRIVERS (true|false) is undefined!")
+elseif(BUILD_NATIVE_DRIVERS)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_device.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_flash.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_gpio.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_prot.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_ipc_drv.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_ipc_pipe.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_ipc_sema.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_scb_common.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_scb_uart.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_sysclk.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_sysint.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_syslib.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_syspm.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_systick.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_trigmux.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/source/cy_wdt.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/generated_source/cycfg.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/generated_source/cycfg_clocks.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/generated_source/cycfg_clocks.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/generated_source/cycfg_pins.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/generated_source/cycfg_routing.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/Native_Driver/generated_source/cycfg_system.c")
+ if(CMAKE_C_COMPILER_ID STREQUAL "ARMCLANG")
+ list(APPEND ALL_SRC_ASM "${PLATFORM_DIR}/target/cypress/psoc64/Device/Source/armclang/cy_syslib_mdk.s")
+ elseif(CMAKE_C_COMPILER_ID STREQUAL "GNUARM")
+ list(APPEND ALL_SRC_ASM "${PLATFORM_DIR}/target/cypress/psoc64/Device/Source/gcc/cy_syslib_gcc.S")
+ else()
+ message(FATAL_ERROR "No cy_syslib is available for compiler '${CMAKE_C_COMPILER_ID}'.")
+ endif()
+endif()
+
+if (NOT DEFINED BUILD_TIME)
+ message(FATAL_ERROR "Configuration variable BUILD_TIME (true|false) is undefined!")
+elseif(BUILD_TIME)
+endif()
+
+if (NOT DEFINED BUILD_STARTUP)
+ message(FATAL_ERROR "Configuration variable BUILD_STARTUP (true|false) is undefined!")
+elseif(BUILD_STARTUP)
+ if(CMAKE_C_COMPILER_ID STREQUAL "ARMCLANG")
+ list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_s.s")
+ list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_ns.s")
+ elseif(CMAKE_C_COMPILER_ID STREQUAL "GNUARM")
+ list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S")
+ list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_ns.S")
+ set_property(SOURCE "${ALL_SRC_ASM_S}" "${ALL_SRC_ASM_NS}" APPEND
+ PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
+ else()
+ message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
+ endif()
+endif()
+
+if (NOT DEFINED BUILD_TARGET_CFG)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_CFG (true|false) is undefined!")
+elseif(BUILD_TARGET_CFG)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/target_cfg.c")
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/cypress/psoc64/spm_hal.c")
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/cypress/psoc64/attest_hal.c")
+ if (TFM_PARTITION_PLATFORM)
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/cypress/psoc64/services/src/tfm_platform_system.c")
+ endif()
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/common/tfm_platform.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/common" ABSOLUTE)
+endif()
+
+if (NOT DEFINED BUILD_TARGET_HARDWARE_KEYS)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_HARDWARE_KEYS (true|false) is undefined!")
+elseif(BUILD_TARGET_HARDWARE_KEYS)
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/common/tfm_initial_attestation_key_material.c")
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/common/tfm_rotpk.c")
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/cypress/psoc64/dummy_crypto_keys.c")
+endif()
+
+if (NOT DEFINED BUILD_TARGET_NV_COUNTERS)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_NV_COUNTERS (true|false) is undefined!")
+elseif(BUILD_TARGET_NV_COUNTERS)
+ # NOTE: This non-volatile counters implementation is a dummy
+ # implementation. Platform vendors have to implement the
+ # API ONLY if the target has non-volatile counters.
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/cypress/psoc64/dummy_nv_counters.c")
+ set(TARGET_NV_COUNTERS_ENABLE ON)
+ # Sets SST_ROLLBACK_PROTECTION flag to compile in the SST services
+ # rollback protection code as the target supports nv counters.
+ set (SST_ROLLBACK_PROTECTION ON)
+endif()
+
+if (NOT DEFINED BUILD_CMSIS_DRIVERS)
+ message(FATAL_ERROR "Configuration variable BUILD_CMSIS_DRIVERS (true|false) is undefined!")
+elseif(BUILD_CMSIS_DRIVERS)
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/cypress/psoc64/driver_smpu.c")
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/cypress/psoc64/driver_ppu.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/CMSIS_Driver/Driver_USART.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/target/cypress/psoc64/CMSIS_Driver" ABSOLUTE)
+ embedded_include_directories(PATH "${PLATFORM_DIR}/driver" ABSOLUTE)
+endif()
+
+if (NOT DEFINED BUILD_FLASH)
+ message(FATAL_ERROR "Configuration variable BUILD_FLASH (true|false) is undefined!")
+elseif(BUILD_FLASH)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/cypress/psoc64/CMSIS_Driver/Driver_Flash.c")
+ # As the SST area is going to be in RAM, it is required to set SST_CREATE_FLASH_LAYOUT
+ # to be sure the SST service knows that when it starts the SST area does not contain any
+ # valid SST flash layout and it needs to create one.
+ set(SST_CREATE_FLASH_LAYOUT ON)
+ set(ITS_CREATE_FLASH_LAYOUT ON)
+ embedded_include_directories(PATH "${PLATFORM_DIR}/target/cypress/psoc64/CMSIS_Driver" ABSOLUTE)
+ embedded_include_directories(PATH "${PLATFORM_DIR}/driver" ABSOLUTE)
+endif()
+
+list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/cypress/psoc64/dummy_boot_seed.c")
+list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/cypress/psoc64/dummy_device_id.c")
diff --git a/platform/ext/target/cypress/psoc64/CMSIS_Driver/Config/RTE_Device.h b/platform/ext/target/cypress/psoc64/CMSIS_Driver/Config/RTE_Device.h
new file mode 100644
index 0000000..2f9773e
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/CMSIS_Driver/Config/RTE_Device.h
@@ -0,0 +1,1290 @@
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H__
+#define __RTE_DEVICE_H__
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU0]
+// <i> Configuration settings for Driver_SMPU0 in component ::Drivers:MPC
+#define RTE_SMPU0 1
+// </e> MPC (Memory Protection Controller) [Driver_SMPU0]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU1]
+// <i> Configuration settings for Driver_SMPU1 in component ::Drivers:MPC
+#define RTE_SMPU1 1
+// </e> MPC (Memory Protection Controller) [Driver_SMPU1]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU2]
+// <i> Configuration settings for Driver_SMPU2 in component ::Drivers:MPC
+#define RTE_SMPU2 1
+// </e> MPC (Memory Protection Controller) [Driver_SMPU2]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU3]
+// <i> Configuration settings for Driver_SMPU3 in component ::Drivers:MPC
+#define RTE_SMPU3 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU3]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU4]
+// <i> Configuration settings for Driver_SMPU4 in component ::Drivers:MPC
+#define RTE_SMPU4 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU4]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU5]
+// <i> Configuration settings for Driver_SMPU5 in component ::Drivers:MPC
+#define RTE_SMPU5 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU5]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU6]
+// <i> Configuration settings for Driver_SMPU6 in component ::Drivers:MPC
+#define RTE_SMPU6 1
+// </e> MPC (Memory Protection Controller) [Driver_SMPU6]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU7]
+// <i> Configuration settings for Driver_SMPU7 in component ::Drivers:MPC
+#define RTE_SMPU7 1
+// </e> MPC (Memory Protection Controller) [Driver_SMPU7]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU8]
+// <i> Configuration settings for Driver_SMPU8 in component ::Drivers:MPC
+#define RTE_SMPU8 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU8]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU9]
+// <i> Configuration settings for Driver_SMPU9 in component ::Drivers:MPC
+#define RTE_SMPU9 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU9]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU10]
+// <i> Configuration settings for Driver_SMPU10 in component ::Drivers:MPC
+#define RTE_SMPU10 1
+// </e> MPC (Memory Protection Controller) [Driver_SMPU10]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU11]
+// <i> Configuration settings for Driver_SMPU11 in component ::Drivers:MPC
+#define RTE_SMPU11 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU11]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU12]
+// <i> Configuration settings for Driver_SMPU12 in component ::Drivers:MPC
+#define RTE_SMPU12 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU12]
+
+// <e> MPC (Memory Protection Controller) [Driver_SMPU13]
+// <i> Configuration settings for Driver_SMPU13 in component ::Drivers:MPC
+#define RTE_SMPU13 0
+// </e> MPC (Memory Protection Controller) [Driver_SMPU13]
+
+/* SMPUs 14 and 15 are used by flashboot */
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
+#define RTE_USART0 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
+#define RTE_USART1 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART2]
+// <i> Configuration settings for Driver_USART2 in component ::Drivers:USART
+#define RTE_USART2 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART2]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART3]
+// <i> Configuration settings for Driver_USART3 in component ::Drivers:USART
+#define RTE_USART3 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART3]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART4]
+// <i> Configuration settings for Driver_USART4 in component ::Drivers:USART
+#define RTE_USART4 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART4]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART5]
+// <i> Configuration settings for Driver_USART5 in component ::Drivers:USART
+#define RTE_USART5 1
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART5]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART6]
+// <i> Configuration settings for Driver_USART6 in component ::Drivers:USART
+#define RTE_USART6 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART6]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART7]
+// <i> Configuration settings for Driver_USART7 in component ::Drivers:USART
+#define RTE_USART7 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART7]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_MS_PPU_PR7]
+// <i> Configuration settings for Driver_MS_PPU_PR7 in component ::Drivers:PPC
+#define RTE_MS_PPU_PR7 0
+// </e> PPC (Peripheral Protection Controller) [Driver_MS_PPU_PR7]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_MAIN]
+// <i> Configuration settings for Driver_PPU_PERI_MAIN in component ::Drivers:PPC
+#define RTE_MS_PPU_PERI_MAIN 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_MAIN]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR0_GROUP]
+// <i> Configuration settings for Driver_PPU_PERI_GR0_GROUP in component ::Drivers:PPC
+#define RTE_MS_PPU_PERI_GR0_GROUP 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR0_GROUP]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR1_GROUP]
+// <i> Configuration settings for Driver_PPU_PERI_GR1_GROUP in component ::Drivers:PPC
+#define RTE_MS_PPU_PERI_GR1_GROUP 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR1_GROUP]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR2_GROUP]
+// <i> Configuration settings for Driver_PPU_PERI_GR2_GROUP in component ::Drivers:PPC
+#define RTE_MS_PPU_PERI_GR2_GROUP 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR2_GROUP]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR3_GROUP]
+// <i> Configuration settings for Driver_PPU_PERI_GR3_GROUP in component ::Drivers:PPC
+#define RTE_MS_PPU_PERI_GR3_GROUP 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR3_GROUP]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR4_GROUP]
+// <i> Configuration settings for Driver_PPU_PERI_GR4_GROUP in component ::Drivers:PPC
+#define RTE_MS_PPU_PERI_GR4_GROUP 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR4_GROUP]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR6_GROUP]
+// <i> Configuration settings for Driver_PPU_PERI_GR6_GROUP in component ::Drivers:PPC
+#define RTE_MS_PPU_PERI_GR6_GROUP 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR6_GROUP]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR9_GROUP]
+// <i> Configuration settings for Driver_PPU_PERI_GR9_GROUP in component ::Drivers:PPC
+#define RTE_MS_PPU_PERI_GR9_GROUP 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR9_GROUP]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR10_GROUP]
+// <i> Configuration settings for Driver_PPU_PERI_GR10_GROUP in component ::Drivers:PPC
+#define RTE_MS_PPU_PERI_GR10_GROUP 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_GR10_GROUP]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_TR]
+// <i> Configuration settings for Driver_PPU_PERI_TR in component ::Drivers:PPC
+#define RTE_MS_PPU_PERI_TR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PERI_TR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_CRYPTO_MAIN]
+// <i> Configuration settings for Driver_PPU_CRYPTO_MAIN in component ::Drivers:PPC
+#define RTE_MS_PPU_CRYPTO_MAIN 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_CRYPTO_MAIN]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_CRYPTO_CRYPTO]
+// <i> Configuration settings for Driver_PPU_CRYPTO_CRYPTO in component ::Drivers:PPC
+#define RTE_MS_PPU_CRYPTO_CRYPTO 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_CRYPTO_CRYPTO]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_CRYPTO_BOOT]
+// <i> Configuration settings for Driver_PPU_CRYPTO_BOOT in component ::Drivers:PPC
+#define RTE_MS_PPU_CRYPTO_BOOT 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_CRYPTO_BOOT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_CRYPTO_KEY0]
+// <i> Configuration settings for Driver_PPU_CRYPTO_KEY0 in component ::Drivers:PPC
+#define RTE_MS_PPU_CRYPTO_KEY0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_CRYPTO_KEY0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_CRYPTO_KEY1]
+// <i> Configuration settings for Driver_PPU_CRYPTO_KEY1 in component ::Drivers:PPC
+#define RTE_MS_PPU_CRYPTO_KEY1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_CRYPTO_KEY1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_CRYPTO_BUF]
+// <i> Configuration settings for Driver_PPU_CRYPTO_BUF in component ::Drivers:PPC
+#define RTE_MS_PPU_CRYPTO_BUF 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_CRYPTO_BUF]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_CPUSS_CM4]
+// <i> Configuration settings for Driver_PPU_CPUSS_CM4 in component ::Drivers:PPC
+#define RTE_MS_PPU_CPUSS_CM4 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_CPUSS_CM4]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_CPUSS_CM0]
+// <i> Configuration settings for Driver_PPU_CPUSS_CM0 in component ::Drivers:PPC
+#define RTE_MS_PPU_CPUSS_CM0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_CPUSS_CM0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_CPUSS_BOOT]
+// <i> Configuration settings for Driver_PPU_CPUSS_BOOT in component ::Drivers:PPC
+#define RTE_MS_PPU_CPUSS_BOOT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_CPUSS_BOOT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_CPUSS_CM0_INT]
+// <i> Configuration settings for Driver_PPU_CPUSS_CM0_INT in component ::Drivers:PPC
+#define RTE_MS_PPU_CPUSS_CM0_INT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_CPUSS_CM0_INT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_CPUSS_CM4_INT]
+// <i> Configuration settings for Driver_PPU_CPUSS_CM4_INT in component ::Drivers:PPC
+#define RTE_MS_PPU_CPUSS_CM4_INT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_CPUSS_CM4_INT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FAULT_STRUCT0_MAIN]
+// <i> Configuration settings for Driver_PPU_FAULT_STRUCT0_MAIN in component ::Drivers:PPC
+#define RTE_MS_PPU_FAULT_STRUCT0_MAIN 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FAULT_STRUCT0_MAIN]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FAULT_STRUCT1_MAIN]
+// <i> Configuration settings for Driver_PPU_FAULT_STRUCT1_MAIN in component ::Drivers:PPC
+#define RTE_MS_PPU_FAULT_STRUCT1_MAIN 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FAULT_STRUCT1_MAIN]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT0_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT0_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT0_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT0_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT1_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT1_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT1_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT1_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT2_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT2_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT2_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT2_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT3_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT3_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT3_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT3_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT4_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT4_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT4_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT4_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT5_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT5_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT5_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT5_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT6_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT6_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT6_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT6_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT7_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT7_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT7_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT7_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT8_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT8_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT8_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT8_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT9_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT9_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT9_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT9_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT10_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT10_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT10_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT10_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT11_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT11_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT11_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT11_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT12_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT12_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT12_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT12_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT13_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT13_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT13_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT13_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT14_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT14_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT14_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT14_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT15_IPC]
+// <i> Configuration settings for Driver_PPU_IPC_STRUCT15_IPC in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_STRUCT15_IPC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_STRUCT15_IPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT0_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT0_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT0_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT0_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT1_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT1_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT1_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT1_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT2_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT2_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT2_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT2_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT3_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT3_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT3_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT3_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT4_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT4_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT4_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT4_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT5_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT5_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT5_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT5_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT6_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT6_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT6_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT6_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT7_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT7_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT7_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT7_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT8_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT8_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT8_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT8_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT9_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT9_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT9_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT9_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT10_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT10_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT10_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT10_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT11_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT11_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT11_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT11_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT12_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT12_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT12_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT12_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT13_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT13_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT13_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT13_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT14_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT14_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT14_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT14_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT15_INTR]
+// <i> Configuration settings for Driver_PPU_IPC_INTR_STRUCT15_INTR in component ::Drivers:PPC
+#define RTE_MS_PPU_IPC_INTR_STRUCT15_INTR 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_IPC_INTR_STRUCT15_INTR]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PROT_SMPU_MAIN]
+// <i> Configuration settings for Driver_PPU_PROT_SMPU_MAIN in component ::Drivers:PPC
+#define RTE_MS_PPU_PROT_SMPU_MAIN 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PROT_SMPU_MAIN]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PROT_MPU0_MAIN]
+// <i> Configuration settings for Driver_PPU_PROT_MPU0_MAIN in component ::Drivers:PPC
+#define RTE_MS_PPU_PROT_MPU0_MAIN 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PROT_MPU0_MAIN]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PROT_MPU5_MAIN]
+// <i> Configuration settings for Driver_PPU_PROT_MPU5_MAIN in component ::Drivers:PPC
+#define RTE_MS_PPU_PROT_MPU5_MAIN 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PROT_MPU5_MAIN]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PROT_MPU6_MAIN]
+// <i> Configuration settings for Driver_PPU_PROT_MPU6_MAIN in component ::Drivers:PPC
+#define RTE_MS_PPU_PROT_MPU6_MAIN 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PROT_MPU6_MAIN]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PROT_MPU14_MAIN]
+// <i> Configuration settings for Driver_PPU_PROT_MPU14_MAIN in component ::Drivers:PPC
+#define RTE_MS_PPU_PROT_MPU14_MAIN 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PROT_MPU14_MAIN]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PROT_MPU15_MAIN]
+// <i> Configuration settings for Driver_PPU_PROT_MPU15_MAIN in component ::Drivers:PPC
+#define RTE_MS_PPU_PROT_MPU15_MAIN 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PROT_MPU15_MAIN]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_MAIN]
+// <i> Configuration settings for Driver_PPU_FLASHC_MAIN in component ::Drivers:PPC
+#define RTE_MS_PPU_FLASHC_MAIN 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_MAIN]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_CMD]
+// <i> Configuration settings for Driver_PPU_FLASHC_CMD in component ::Drivers:PPC
+#define RTE_MS_PPU_FLASHC_CMD 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_CMD]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_DFT]
+// <i> Configuration settings for Driver_PPU_FLASHC_DFT in component ::Drivers:PPC
+#define RTE_MS_PPU_FLASHC_DFT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_DFT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_CM0]
+// <i> Configuration settings for Driver_PPU_FLASHC_CM0 in component ::Drivers:PPC
+#define RTE_MS_PPU_FLASHC_CM0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_CM0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_CM4]
+// <i> Configuration settings for Driver_PPU_FLASHC_CM4 in component ::Drivers:PPC
+#define RTE_MS_PPU_FLASHC_CM4 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_CM4]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_CRYPTO]
+// <i> Configuration settings for Driver_PPU_FLASHC_CRYPTO in component ::Drivers:PPC
+#define RTE_MS_PPU_FLASHC_CRYPTO 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_CRYPTO]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_DW0]
+// <i> Configuration settings for Driver_PPU_FLASHC_DW0 in component ::Drivers:PPC
+#define RTE_MS_PPU_FLASHC_DW0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_DW0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_DW1]
+// <i> Configuration settings for Driver_PPU_FLASHC_DW1 in component ::Drivers:PPC
+#define RTE_MS_PPU_FLASHC_DW1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_DW1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_DMAC]
+// <i> Configuration settings for Driver_PPU_FLASHC_DMAC in component ::Drivers:PPC
+#define RTE_MS_PPU_FLASHC_DMAC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_DMAC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_EXT_MS0]
+// <i> Configuration settings for Driver_PPU_FLASHC_EXT_MS0 in component ::Drivers:PPC
+#define RTE_MS_PPU_FLASHC_EXT_MS0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_EXT_MS0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_EXT_MS1]
+// <i> Configuration settings for Driver_PPU_FLASHC_EXT_MS1 in component ::Drivers:PPC
+#define RTE_MS_PPU_FLASHC_EXT_MS1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_EXT_MS1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_FM]
+// <i> Configuration settings for Driver_PPU_FLASHC_FM in component ::Drivers:PPC
+#define RTE_MS_PPU_FLASHC_FM 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_FLASHC_FM]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN1]
+// <i> Configuration settings for Driver_PPU_SRSS_MAIN1 in component ::Drivers:PPC
+#define RTE_MS_PPU_SRSS_MAIN1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN2]
+// <i> Configuration settings for Driver_PPU_SRSS_MAIN2 in component ::Drivers:PPC
+#define RTE_MS_PPU_SRSS_MAIN2 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_WDT]
+// <i> Configuration settings for Driver_PPU_WDT in component ::Drivers:PPC
+#define RTE_MS_PPU_WDT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_WDT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_MAIN]
+// <i> Configuration settings for Driver_PPU_MAIN in component ::Drivers:PPC
+#define RTE_MS_PPU_MAIN 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_MAIN]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN3]
+// <i> Configuration settings for Driver_PPU_SRSS_MAIN3 in component ::Drivers:PPC
+#define RTE_MS_PPU_SRSS_MAIN3 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN4]
+// <i> Configuration settings for Driver_PPU_SRSS_MAIN4 in component ::Drivers:PPC
+#define RTE_MS_PPU_SRSS_MAIN4 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN4]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN5]
+// <i> Configuration settings for Driver_PPU_SRSS_MAIN5 in component ::Drivers:PPC
+#define RTE_MS_PPU_SRSS_MAIN5 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN5]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN6]
+// <i> Configuration settings for Driver_PPU_SRSS_MAIN6 in component ::Drivers:PPC
+#define RTE_MS_PPU_SRSS_MAIN6 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN6]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN7]
+// <i> Configuration settings for Driver_PPU_SRSS_MAIN7 in component ::Drivers:PPC
+#define RTE_MS_PPU_SRSS_MAIN7 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SRSS_MAIN7]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_BACKUP_BACKUP]
+// <i> Configuration settings for Driver_PPU_BACKUP_BACKUP in component ::Drivers:PPC
+#define RTE_MS_PPU_BACKUP_BACKUP 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_BACKUP_BACKUP]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_DW]
+// <i> Configuration settings for Driver_PPU_DW0_DW in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_DW 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_DW]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_DW]
+// <i> Configuration settings for Driver_PPU_DW1_DW in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_DW 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_DW]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_DW_CRC]
+// <i> Configuration settings for Driver_PPU_DW0_DW_CRC in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_DW_CRC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_DW_CRC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_DW_CRC]
+// <i> Configuration settings for Driver_PPU_DW1_DW_CRC in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_DW_CRC 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_DW_CRC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT0_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT0_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT0_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT0_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT1_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT1_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT1_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT1_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT2_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT2_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT2_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT2_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT3_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT3_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT3_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT3_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT4_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT4_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT4_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT4_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT5_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT5_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT5_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT5_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT6_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT6_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT6_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT6_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT7_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT7_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT7_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT7_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT8_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT8_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT8_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT8_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT9_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT9_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT9_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT9_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT10_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT10_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT10_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT10_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT11_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT11_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT11_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT11_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT12_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT12_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT12_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT12_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT13_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT13_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT13_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT13_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT14_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT14_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT14_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT14_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT15_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT15_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT15_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT15_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT16_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT16_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT16_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT16_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT17_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT17_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT17_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT17_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT18_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT18_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT18_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT18_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT19_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT19_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT19_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT19_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT20_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT20_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT20_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT20_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT21_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT21_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT21_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT21_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT22_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT22_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT22_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT22_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT23_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT23_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT23_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT23_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT24_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT24_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT24_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT24_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT25_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT25_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT25_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT25_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT26_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT26_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT26_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT26_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT27_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT27_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT27_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT27_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT28_CH]
+// <i> Configuration settings for Driver_PPU_DW0_CH_STRUCT28_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW0_CH_STRUCT28_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW0_CH_STRUCT28_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT0_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT0_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT0_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT0_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT1_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT1_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT1_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT1_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT2_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT2_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT2_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT2_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT3_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT3_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT3_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT3_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT4_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT4_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT4_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT4_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT5_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT5_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT5_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT5_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT6_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT6_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT6_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT6_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT7_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT7_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT7_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT7_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT8_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT8_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT8_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT8_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT9_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT9_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT9_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT9_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT10_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT10_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT10_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT10_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT11_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT11_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT11_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT11_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT12_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT12_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT12_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT12_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT13_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT13_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT13_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT13_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT14_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT14_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT14_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT14_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT15_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT15_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT15_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT15_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT16_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT16_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT16_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT16_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT17_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT17_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT17_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT17_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT18_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT18_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT18_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT18_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT19_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT19_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT19_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT19_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT20_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT20_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT20_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT20_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT21_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT21_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT21_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT21_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT22_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT22_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT22_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT22_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT23_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT23_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT23_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT23_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT24_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT24_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT24_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT24_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT25_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT25_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT25_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT25_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT26_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT26_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT26_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT26_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT27_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT27_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT27_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT27_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT28_CH]
+// <i> Configuration settings for Driver_PPU_DW1_CH_STRUCT28_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DW1_CH_STRUCT28_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DW1_CH_STRUCT28_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DMAC_TOP]
+// <i> Configuration settings for Driver_PPU_DMAC_TOP in component ::Drivers:PPC
+#define RTE_MS_PPU_DMAC_TOP 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DMAC_TOP]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DMAC_CH0_CH]
+// <i> Configuration settings for Driver_PPU_DMAC_CH0_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DMAC_CH0_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DMAC_CH0_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DMAC_CH1_CH]
+// <i> Configuration settings for Driver_PPU_DMAC_CH1_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DMAC_CH1_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DMAC_CH1_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DMAC_CH2_CH]
+// <i> Configuration settings for Driver_PPU_DMAC_CH2_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DMAC_CH2_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DMAC_CH2_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_DMAC_CH3_CH]
+// <i> Configuration settings for Driver_PPU_DMAC_CH3_CH in component ::Drivers:PPC
+#define RTE_MS_PPU_DMAC_CH3_CH 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_DMAC_CH3_CH]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_EFUSE_CTL]
+// <i> Configuration settings for Driver_PPU_EFUSE_CTL in component ::Drivers:PPC
+#define RTE_MS_PPU_EFUSE_CTL 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_EFUSE_CTL]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_EFUSE_DATA]
+// <i> Configuration settings for Driver_PPU_EFUSE_DATA in component ::Drivers:PPC
+#define RTE_MS_PPU_EFUSE_DATA 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_EFUSE_DATA]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PROFILE]
+// <i> Configuration settings for Driver_PPU_PROFILE in component ::Drivers:PPC
+#define RTE_MS_PPU_PROFILE 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PROFILE]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT0_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT0_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT0_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT0_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT1_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT1_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT1_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT1_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT2_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT2_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT2_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT2_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT3_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT3_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT3_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT3_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT4_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT4_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT4_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT4_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT5_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT5_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT5_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT5_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT6_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT6_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT6_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT6_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT7_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT7_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT7_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT7_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT8_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT8_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT8_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT8_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT9_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT9_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT9_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT9_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT10_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT10_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT10_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT10_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT11_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT11_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT11_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT11_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT12_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT12_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT12_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT12_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT13_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT13_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT13_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT13_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT14_PRT]
+// <i> Configuration settings for Driver_PPU_HSIOM_PRT14_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_PRT14_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_PRT14_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_AMUX]
+// <i> Configuration settings for Driver_PPU_HSIOM_AMUX in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_AMUX 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_AMUX]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_MON]
+// <i> Configuration settings for Driver_PPU_HSIOM_MON in component ::Drivers:PPC
+#define RTE_MS_PPU_HSIOM_MON 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_HSIOM_MON]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT0_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT0_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT0_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT0_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT1_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT1_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT1_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT1_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT2_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT2_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT2_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT2_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT3_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT3_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT3_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT3_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT4_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT4_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT4_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT4_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT5_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT5_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT5_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT5_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT6_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT6_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT6_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT6_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT7_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT7_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT7_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT7_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT8_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT8_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT8_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT8_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT9_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT9_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT9_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT9_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT10_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT10_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT10_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT10_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT11_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT11_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT11_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT11_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT12_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT12_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT12_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT12_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT13_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT13_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT13_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT13_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT14_PRT]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT14_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT14_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT14_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT0_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT0_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT0_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT0_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT1_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT1_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT1_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT1_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT2_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT2_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT2_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT2_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT3_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT3_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT3_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT3_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT4_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT4_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT4_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT4_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT5_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT5_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT5_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT5_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT6_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT6_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT6_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT6_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT7_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT7_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT7_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT7_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT8_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT8_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT8_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT8_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT9_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT9_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT9_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT9_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT10_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT10_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT10_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT10_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT11_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT11_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT11_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT11_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT12_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT12_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT12_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT12_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT13_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT13_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT13_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT13_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT14_CFG]
+// <i> Configuration settings for Driver_PPU_GPIO_PRT14_CFG in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_PRT14_CFG 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_PRT14_CFG]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_GPIO]
+// <i> Configuration settings for Driver_PPU_GPIO_GPIO in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_GPIO 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_GPIO]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_TEST]
+// <i> Configuration settings for Driver_PPU_GPIO_TEST in component ::Drivers:PPC
+#define RTE_MS_PPU_GPIO_TEST 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_GPIO_TEST]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SMARTIO_PRT8_PRT]
+// <i> Configuration settings for Driver_PPU_SMARTIO_PRT8_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_SMARTIO_PRT8_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SMARTIO_PRT8_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SMARTIO_PRT9_PRT]
+// <i> Configuration settings for Driver_PPU_SMARTIO_PRT9_PRT in component ::Drivers:PPC
+#define RTE_MS_PPU_SMARTIO_PRT9_PRT 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SMARTIO_PRT9_PRT]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_LPCOMP]
+// <i> Configuration settings for Driver_PPU_LPCOMP in component ::Drivers:PPC
+#define RTE_MS_PPU_LPCOMP 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_LPCOMP]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_CSD0]
+// <i> Configuration settings for Driver_PPU_CSD0 in component ::Drivers:PPC
+#define RTE_MS_PPU_CSD0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_CSD0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_TCPWM0]
+// <i> Configuration settings for Driver_PPU_TCPWM0 in component ::Drivers:PPC
+#define RTE_MS_PPU_TCPWM0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_TCPWM0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_TCPWM1]
+// <i> Configuration settings for Driver_PPU_TCPWM1 in component ::Drivers:PPC
+#define RTE_MS_PPU_TCPWM1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_TCPWM1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_LCD0]
+// <i> Configuration settings for Driver_PPU_LCD0 in component ::Drivers:PPC
+#define RTE_MS_PPU_LCD0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_LCD0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_USBFS0]
+// <i> Configuration settings for Driver_PPU_USBFS0 in component ::Drivers:PPC
+#define RTE_MS_PPU_USBFS0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_USBFS0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SMIF0]
+// <i> Configuration settings for Driver_PPU_SMIF0 in component ::Drivers:PPC
+#define RTE_MS_PPU_SMIF0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SMIF0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SDHC0]
+// <i> Configuration settings for Driver_PPU_SDHC0 in component ::Drivers:PPC
+#define RTE_MS_PPU_SDHC0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SDHC0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SDHC1]
+// <i> Configuration settings for Driver_PPU_SDHC1 in component ::Drivers:PPC
+#define RTE_MS_PPU_SDHC1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SDHC1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB0]
+// <i> Configuration settings for Driver_PPU_SCB0 in component ::Drivers:PPC
+#define RTE_MS_PPU_SCB0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB1]
+// <i> Configuration settings for Driver_PPU_SCB1 in component ::Drivers:PPC
+#define RTE_MS_PPU_SCB1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB2]
+// <i> Configuration settings for Driver_PPU_SCB2 in component ::Drivers:PPC
+#define RTE_MS_PPU_SCB2 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB3]
+// <i> Configuration settings for Driver_PPU_SCB3 in component ::Drivers:PPC
+#define RTE_MS_PPU_SCB3 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB4]
+// <i> Configuration settings for Driver_PPU_SCB4 in component ::Drivers:PPC
+#define RTE_MS_PPU_SCB4 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB4]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB5]
+// <i> Configuration settings for Driver_PPU_SCB5 in component ::Drivers:PPC
+#define RTE_MS_PPU_SCB5 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB5]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB6]
+// <i> Configuration settings for Driver_PPU_SCB6 in component ::Drivers:PPC
+#define RTE_MS_PPU_SCB6 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB6]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB7]
+// <i> Configuration settings for Driver_PPU_SCB7 in component ::Drivers:PPC
+#define RTE_MS_PPU_SCB7 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB7]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB8]
+// <i> Configuration settings for Driver_PPU_SCB8 in component ::Drivers:PPC
+#define RTE_MS_PPU_SCB8 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB8]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB9]
+// <i> Configuration settings for Driver_PPU_SCB9 in component ::Drivers:PPC
+#define RTE_MS_PPU_SCB9 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB9]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB10]
+// <i> Configuration settings for Driver_PPU_SCB10 in component ::Drivers:PPC
+#define RTE_MS_PPU_SCB10 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB10]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB11]
+// <i> Configuration settings for Driver_PPU_SCB11 in component ::Drivers:PPC
+#define RTE_MS_PPU_SCB11 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB11]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB12]
+// <i> Configuration settings for Driver_PPU_SCB12 in component ::Drivers:PPC
+#define RTE_MS_PPU_SCB12 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_SCB12]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_PDM0]
+// <i> Configuration settings for Driver_PPU_PDM0 in component ::Drivers:PPC
+#define RTE_MS_PPU_PDM0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_PDM0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_I2S0]
+// <i> Configuration settings for Driver_PPU_I2S0 in component ::Drivers:PPC
+#define RTE_MS_PPU_I2S0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_I2S0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_PPU_I2S1]
+// <i> Configuration settings for Driver_PPU_I2S1 in component ::Drivers:PPC
+#define RTE_MS_PPU_I2S1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_PPU_I2S1]
+
+// <e> FLASH (Flash Memory) [Driver_FLASH0]
+// <i> Configuration settings for Driver_FLASH0 in component ::Drivers:FLASH
+#define RTE_FLASH0 1
+// </e> FLASH (Flash Memory) [Driver_FLASH0]
+
+#endif /* __RTE_DEVICE_H__ */
diff --git a/platform/ext/target/cypress/psoc64/CMSIS_Driver/Config/cmsis_driver_config.h b/platform/ext/target/cypress/psoc64/CMSIS_Driver/Config/cmsis_driver_config.h
new file mode 100644
index 0000000..7cb5bae
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/CMSIS_Driver/Config/cmsis_driver_config.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_DRIVER_CONFIG_H__
+#define __CMSIS_DRIVER_CONFIG_H__
+
+#include "device_cfg.h"
+#include "device_definition.h"
+#include "platform_description.h"
+#include "RTE_Device.h"
+#include "target_cfg.h"
+
+#endif /* __CMSIS_DRIVER_CONFIG_H__ */
diff --git a/platform/ext/target/cypress/psoc64/CMSIS_Driver/Driver_Flash.c b/platform/ext/target/cypress/psoc64/CMSIS_Driver/Driver_Flash.c
new file mode 100644
index 0000000..2487598
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/CMSIS_Driver/Driver_Flash.c
@@ -0,0 +1,318 @@
+/*
+ * Copyright (c) 2013-2019 ARM Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* This is a modified copy of the ref_twincpu version at
+ * platform/ext/target/ref_twincpu/CMSIS_Driver/Driver_Flash.c
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <stdio.h>
+#include "Driver_Flash.h"
+#include "RTE_Device.h"
+#include "flash_layout.h"
+#include "region_defs.h"
+
+#include "cycfg.h"
+#include "cy_device.h"
+#include "cy_flash.h"
+
+#ifndef ARG_UNUSED
+#define ARG_UNUSED(arg) ((void)arg)
+#endif
+
+/* Driver version */
+#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 1)
+#define ARM_FLASH_DRV_ERASE_VALUE 0xFF
+
+#define FLASH0_BASE CY_FLASH_BASE // User Flash start address for both CM0+ & CM4
+#define FLASH0_SIZE CY_FLASH_SIZE // 1 MB
+#define FLASH0_SECTOR_SIZE CY_FLASH_SIZEOF_ROW // 512 B
+#define FLASH0_PAGE_SIZE CY_FLASH_SIZEOF_ROW // 512 B
+
+struct arm_flash_dev_t {
+ const uint32_t memory_base; /*!< FLASH memory base address */
+ ARM_FLASH_INFO *data; /*!< FLASH data */
+};
+
+/* Flash Status */
+static ARM_FLASH_STATUS FlashStatus = {0, 0, 0};
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_FLASH_API_VERSION,
+ ARM_FLASH_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_FLASH_CAPABILITIES DriverCapabilities = {
+ 0, /* event_ready */
+ 0, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */
+ 1 /* erase_chip */
+};
+
+
+#if (RTE_FLASH0)
+
+static ARM_FLASH_INFO ARM_FLASH0_DEV_DATA = {
+ .sector_info = NULL, /* Uniform sector layout */
+ .sector_count = FLASH0_SIZE / FLASH0_SECTOR_SIZE,
+ .sector_size = FLASH0_SECTOR_SIZE,
+ .page_size = FLASH0_PAGE_SIZE,
+ .program_unit = SST_FLASH_PROGRAM_UNIT,
+ .erased_value = ARM_FLASH_DRV_ERASE_VALUE
+};
+
+static struct arm_flash_dev_t ARM_FLASH0_DEV = {
+ .memory_base = FLASH0_BASE,
+ .data = &(ARM_FLASH0_DEV_DATA)
+};
+
+struct arm_flash_dev_t *FLASH0_DEV = &ARM_FLASH0_DEV;
+
+/*
+ * Functions
+ */
+
+static ARM_DRIVER_VERSION ARM_Flash_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void)
+{
+ return DriverCapabilities;
+}
+
+static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event)
+{
+ ARG_UNUSED(cb_event);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state)
+{
+ switch (state) {
+ case ARM_POWER_FULL:
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+ break;
+
+ case ARM_POWER_OFF:
+ case ARM_POWER_LOW:
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+}
+
+static int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt)
+{
+ if ( (data == NULL) || (cnt == 0) ) {
+ return ARM_DRIVER_OK;
+ }
+
+ // Wraparound check (before adding FLASH0_DEV->memory_base + addr)
+ if (FLASH0_DEV->memory_base >= UINT32_MAX - addr) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ uint32_t start_addr = FLASH0_DEV->memory_base + addr;
+
+ if (start_addr >= FLASH0_DEV->memory_base + FLASH0_SIZE) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ // Wraparound check (before adding start_addr + cnt)
+ if (start_addr >= UINT32_MAX - cnt) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ if ( (start_addr + cnt < FLASH0_DEV->memory_base) ||
+ (start_addr + cnt > FLASH0_DEV->memory_base + FLASH0_SIZE)
+ ) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ // Using memcpy for reading
+ memcpy(data, (void *)start_addr, cnt);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data,
+ uint32_t cnt)
+{
+ static uint8_t prog_buf[CY_FLASH_SIZEOF_ROW];
+ uint8_t *data_ptr = (uint8_t *) data;
+ uint32_t address = FLASH0_DEV->memory_base + addr;
+ cy_en_flashdrv_status_t cy_status = CY_FLASH_DRV_ERR_UNC;
+
+ // Address checks can be omitted here as they are done by Cypress API
+
+ if ( (data == NULL) || (cnt == 0) ) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ // Make sure cnt argument is aligned to program_unit size
+ if (cnt % FLASH0_DEV->data->program_unit) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ // Wraparound check (before adding FLASH0_DEV->memory_base + addr)
+ if (FLASH0_DEV->memory_base >= UINT32_MAX - addr) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ while (cnt)
+ {
+ uint32_t offset = address % CY_FLASH_SIZEOF_ROW;
+ uint32_t chunk_size;
+ if (offset + cnt > CY_FLASH_SIZEOF_ROW) {
+ chunk_size = CY_FLASH_SIZEOF_ROW - offset;
+ } else {
+ chunk_size = cnt;
+ }
+ uint32_t row_address = address / CY_FLASH_SIZEOF_ROW * CY_FLASH_SIZEOF_ROW;
+ memcpy(prog_buf, (const void *)row_address, CY_FLASH_SIZEOF_ROW);
+ memcpy(prog_buf + offset, data_ptr, chunk_size);
+
+ cy_status = Cy_Flash_ProgramRow(row_address, (const uint32_t *)prog_buf);
+ if (cy_status != CY_FLASH_DRV_SUCCESS) {
+ break;
+ }
+ data_ptr += chunk_size;
+ address += chunk_size;
+ cnt -= chunk_size;
+ }
+
+ switch (cy_status)
+ {
+ case CY_FLASH_DRV_SUCCESS:
+ return ARM_DRIVER_OK;
+
+ case CY_FLASH_DRV_IPC_BUSY:
+ return ARM_DRIVER_ERROR_BUSY;
+
+ case CY_FLASH_DRV_INVALID_INPUT_PARAMETERS:
+ return ARM_DRIVER_ERROR_PARAMETER;
+
+ default:
+ return ARM_DRIVER_ERROR;
+ }
+}
+
+static int32_t ARM_Flash_EraseSector(uint32_t addr)
+{
+ // Wraparound check (before adding FLASH0_DEV->memory_base + addr)
+ if (FLASH0_DEV->memory_base >= UINT32_MAX - addr) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ uint32_t start_addr = FLASH0_DEV->memory_base + addr;
+
+ // Address checks can be omitted here as they are done by Cypress API
+
+ cy_en_flashdrv_status_t cy_status = Cy_Flash_EraseRow(start_addr);
+
+ switch (cy_status)
+ {
+ case CY_FLASH_DRV_SUCCESS:
+ return ARM_DRIVER_OK;
+
+ case CY_FLASH_DRV_IPC_BUSY:
+ return ARM_DRIVER_ERROR_BUSY;
+
+ case CY_FLASH_DRV_INVALID_INPUT_PARAMETERS:
+ return ARM_DRIVER_ERROR_PARAMETER;
+
+ default:
+ return ARM_DRIVER_ERROR;
+ }
+}
+
+static int32_t ARM_Flash_EraseChip(void)
+{
+ uint32_t addr = FLASH0_DEV->memory_base;
+
+ cy_en_flashdrv_status_t cy_status = CY_FLASH_DRV_ERR_UNC;
+
+
+ if (DriverCapabilities.erase_chip != 1) {
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ for (uint32_t i = 0; i < FLASH0_DEV->data->sector_count; i++) {
+
+ cy_status = Cy_Flash_EraseRow(addr);
+
+ if (cy_status != CY_FLASH_DRV_SUCCESS) {
+ break;
+ }
+
+ addr += FLASH0_DEV->data->sector_size;
+ }
+
+ switch (cy_status)
+ {
+ case CY_FLASH_DRV_SUCCESS:
+ return ARM_DRIVER_OK;
+
+ case CY_FLASH_DRV_IPC_BUSY:
+ return ARM_DRIVER_ERROR_BUSY;
+
+ case CY_FLASH_DRV_INVALID_INPUT_PARAMETERS:
+ return ARM_DRIVER_ERROR_PARAMETER;
+
+ default:
+ return ARM_DRIVER_ERROR;
+ }
+}
+
+static ARM_FLASH_STATUS ARM_Flash_GetStatus(void)
+{
+ return FlashStatus;
+}
+
+static ARM_FLASH_INFO * ARM_Flash_GetInfo(void)
+{
+ return FLASH0_DEV->data;
+}
+
+ARM_DRIVER_FLASH Driver_FLASH0 = {
+ ARM_Flash_GetVersion,
+ ARM_Flash_GetCapabilities,
+ ARM_Flash_Initialize,
+ ARM_Flash_Uninitialize,
+ ARM_Flash_PowerControl,
+ ARM_Flash_ReadData,
+ ARM_Flash_ProgramData,
+ ARM_Flash_EraseSector,
+ ARM_Flash_EraseChip,
+ ARM_Flash_GetStatus,
+ ARM_Flash_GetInfo
+};
+
+#endif /* RTE_FLASH0 */
diff --git a/platform/ext/target/cypress/psoc64/CMSIS_Driver/Driver_USART.c b/platform/ext/target/cypress/psoc64/CMSIS_Driver/Driver_USART.c
new file mode 100644
index 0000000..9443f88
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/CMSIS_Driver/Driver_USART.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* This is a modified copy of the ref_twincpu version at
+ * platform/ext/target/ref_twincpu/CMSIS_Driver/Driver_USART.c
+ */
+
+#include "Driver_USART.h"
+
+#include "cmsis.h"
+#include "cmsis_driver_config.h"
+#include "RTE_Device.h"
+
+#include "cycfg.h"
+#include "cy_device.h"
+#include "cy_scb_uart.h"
+
+#ifndef ARG_UNUSED
+#define ARG_UNUSED(arg) (void)arg
+#endif
+
+/* Driver version */
+#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_USART_API_VERSION,
+ ARM_USART_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_USART_CAPABILITIES DriverCapabilities = {
+ 1, /* supports UART (Asynchronous) mode */
+ 0, /* supports Synchronous Master mode */
+ 0, /* supports Synchronous Slave mode */
+ 0, /* supports UART Single-wire mode */
+ 0, /* supports UART IrDA mode */
+ 0, /* supports UART Smart Card mode */
+ 0, /* Smart Card Clock generator available */
+ 0, /* RTS Flow Control available */
+ 0, /* CTS Flow Control available */
+ 0, /* Transmit completed event: \ref ARM_USARTx_EVENT_TX_COMPLETE */
+ 0, /* Signal receive character timeout event: \ref ARM_USARTx_EVENT_RX_TIMEOUT */
+ 0, /* RTS Line: 0=not available, 1=available */
+ 0, /* CTS Line: 0=not available, 1=available */
+ 0, /* DTR Line: 0=not available, 1=available */
+ 0, /* DSR Line: 0=not available, 1=available */
+ 0, /* DCD Line: 0=not available, 1=available */
+ 0, /* RI Line: 0=not available, 1=available */
+ 0, /* Signal CTS change event: \ref ARM_USARTx_EVENT_CTS */
+ 0, /* Signal DSR change event: \ref ARM_USARTx_EVENT_DSR */
+ 0, /* Signal DCD change event: \ref ARM_USARTx_EVENT_DCD */
+ 0, /* Signal RI change event: \ref ARM_USARTx_EVENT_RI */
+ 0 /* Reserved */
+};
+
+static ARM_DRIVER_VERSION ARM_USART_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void)
+{
+ return DriverCapabilities;
+}
+
+typedef struct {
+ CySCB_Type* base; /* UART device structure */
+ uint32_t tx_nbr_bytes; /* Number of bytes transfered */
+ uint32_t rx_nbr_bytes; /* Number of bytes recevied */
+ ARM_USART_SignalEvent_t cb_event; /* Callback function for events */
+} UARTx_Resources;
+
+static int32_t USARTx_convert_retval(cy_en_scb_uart_status_t val)
+{
+ switch (val) {
+ case CY_SCB_UART_SUCCESS:
+ return ARM_DRIVER_OK;
+ case CY_SCB_UART_BAD_PARAM:
+ return ARM_DRIVER_ERROR_PARAMETER;
+ case CY_SCB_UART_RECEIVE_BUSY:
+ case CY_SCB_UART_TRANSMIT_BUSY:
+ return ARM_DRIVER_ERROR_BUSY;
+ }
+}
+
+static int32_t ARM_USARTx_Initialize(UARTx_Resources* uart_dev)
+{
+ cy_en_scb_uart_status_t retval;
+
+#ifdef CY_SYSTEM_CPU_CM0P
+ cy_stc_scb_uart_config_t config = KITPROG_UART_config;
+
+ /* Assign and configure pins, assign clock divider */
+ retval = Cy_SCB_UART_Init(uart_dev->base, &config, NULL);
+
+ if (retval == CY_SCB_UART_SUCCESS)
+ Cy_SCB_UART_Enable(uart_dev->base);
+#else
+ // all hw initializations is done on the cm0p side
+ retval = CY_SCB_UART_SUCCESS;
+
+#endif
+ return USARTx_convert_retval(retval);
+}
+
+static uint32_t ARM_USARTx_Uninitialize(UARTx_Resources* uart_dev)
+{
+ Cy_SCB_UART_Disable(uart_dev->base, NULL);
+
+ Cy_SCB_UART_DeInit(uart_dev->base);
+
+ return ARM_DRIVER_OK;
+}
+
+
+static int32_t ARM_USARTx_PowerControl(UARTx_Resources* uart_dev,
+ ARM_POWER_STATE state)
+{
+ ARG_UNUSED(uart_dev);
+
+ switch (state) {
+ case ARM_POWER_OFF:
+ case ARM_POWER_LOW:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ case ARM_POWER_FULL:
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all the enumeration values are
+ * covered in the switch.*/
+ }
+}
+
+static int32_t ARM_USARTx_Send(UARTx_Resources* uart_dev, const void *data,
+ uint32_t num)
+{
+ void *p_data = (void *)data;
+
+ if ((data == NULL) || (num == 0U)) {
+ /* Invalid parameters */
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ Cy_SCB_UART_PutArrayBlocking(uart_dev->base, p_data, num);
+
+ while (!Cy_SCB_UART_IsTxComplete(uart_dev->base))
+ ;
+
+ uart_dev->tx_nbr_bytes = num;
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USARTx_Receive(UARTx_Resources* uart_dev,
+ void *data, uint32_t num)
+{
+ if ((data == NULL) || (num == 0U)) {
+ // Invalid parameters
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ Cy_SCB_UART_GetArrayBlocking(uart_dev->base, data, num);
+
+ uart_dev->rx_nbr_bytes = num;
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USARTx_Transfer(UARTx_Resources* uart_dev,
+ const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(uart_dev);
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USARTx_GetTxCount(UARTx_Resources* uart_dev)
+{
+ return uart_dev->tx_nbr_bytes;
+}
+
+static uint32_t ARM_USARTx_GetRxCount(UARTx_Resources* uart_dev)
+{
+ return uart_dev->rx_nbr_bytes;
+}
+
+static uint32_t USARTx_SetDataBits(uint32_t control,
+ cy_stc_scb_uart_config_t *config)
+{
+ switch (control & ARM_USART_DATA_BITS_Msk) {
+ case ARM_USART_DATA_BITS_5:
+ config->dataWidth = 5;
+ break;
+
+ case ARM_USART_DATA_BITS_6:
+ config->dataWidth = 6;
+ break;
+
+ case ARM_USART_DATA_BITS_7:
+ config->dataWidth = 7;
+ break;
+
+ case ARM_USART_DATA_BITS_8:
+ config->dataWidth = 8;
+ break;
+
+ case ARM_USART_DATA_BITS_9:
+ config->dataWidth = 9;
+ break;
+
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t USARTx_SetParity(uint32_t control,
+ cy_stc_scb_uart_config_t *config)
+{
+ switch (control & ARM_USART_PARITY_Msk) {
+ case ARM_USART_PARITY_NONE:
+ config->parity = CY_SCB_UART_PARITY_NONE;
+ break;
+
+ case ARM_USART_PARITY_EVEN:
+ config->parity = CY_SCB_UART_PARITY_EVEN;
+ break;
+
+ case ARM_USART_PARITY_ODD:
+ config->parity = CY_SCB_UART_PARITY_ODD;
+ break;
+
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t USARTx_SetStopBits(uint32_t control,
+ cy_stc_scb_uart_config_t *config)
+{
+ switch (control & ARM_USART_STOP_BITS_Msk) {
+ case ARM_USART_STOP_BITS_1:
+ config->stopBits = CY_SCB_UART_STOP_BITS_1;
+ break;
+
+ case ARM_USART_STOP_BITS_2:
+ config->stopBits = CY_SCB_UART_STOP_BITS_2;
+ break;
+
+ case ARM_USART_STOP_BITS_1_5:
+ config->stopBits = CY_SCB_UART_STOP_BITS_1_5;
+ break;
+
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void USARTx_SetFlowControl(uint32_t control,
+ cy_stc_scb_uart_config_t *config)
+{
+ /* First, deal with CTS */
+ switch (control & ARM_USART_FLOW_CONTROL_Msk) {
+ case ARM_USART_FLOW_CONTROL_NONE:
+ case ARM_USART_FLOW_CONTROL_RTS:
+ config->enableCts = false;
+ config->ctsPolarity = CY_SCB_UART_ACTIVE_LOW;
+ break;
+
+ case ARM_USART_FLOW_CONTROL_CTS:
+ case ARM_USART_FLOW_CONTROL_RTS_CTS:
+ config->enableCts = true;
+ config->ctsPolarity = CY_SCB_UART_ACTIVE_LOW;
+ break;
+ }
+
+ /* Then RTS */
+ switch (control & ARM_USART_FLOW_CONTROL_Msk) {
+ case ARM_USART_FLOW_CONTROL_NONE:
+ case ARM_USART_FLOW_CONTROL_CTS:
+ config->rtsRxFifoLevel = 0;
+ config->rtsPolarity = CY_SCB_UART_ACTIVE_LOW;
+ break;
+
+ case ARM_USART_FLOW_CONTROL_RTS:
+ case ARM_USART_FLOW_CONTROL_RTS_CTS:
+ config->rtsRxFifoLevel = 8; /* TODO What's a sensible value ? */
+ config->rtsPolarity = CY_SCB_UART_ACTIVE_LOW;
+ break;
+ }
+}
+
+static int32_t ARM_USARTx_Control(UARTx_Resources* uart_dev, uint32_t control,
+ uint32_t arg)
+{
+ cy_stc_scb_uart_config_t config = KITPROG_UART_config;
+ cy_en_scb_uart_status_t cy_retval;
+ uint32_t retval;
+
+ Cy_SCB_UART_Disable(uart_dev->base, NULL);
+
+ Cy_SCB_UART_DeInit(uart_dev->base);
+
+ switch (control & ARM_USART_CONTROL_Msk) {
+ case ARM_USART_MODE_ASYNCHRONOUS:
+ /* TODO Default values work for 115200 baud,
+ * but we should set config.oversample to
+ * a value derived from the divider
+ */
+ break;
+ /* Unsupported command */
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ /* UART Data bits */
+ retval = USARTx_SetDataBits(control, &config);
+ if (retval != ARM_DRIVER_OK)
+ return retval;
+
+ /* UART Parity */
+ retval = USARTx_SetParity(control, &config);
+ if (retval != ARM_DRIVER_OK)
+ return retval;
+
+ /* USART Stop bits */
+ retval = USARTx_SetStopBits(control, &config);
+ if (retval != ARM_DRIVER_OK)
+ return retval;
+
+ /* USART Flow Control */
+ USARTx_SetFlowControl(control, &config);
+
+ cy_retval = Cy_SCB_UART_Init(uart_dev->base, &config, NULL);
+
+ if (retval == CY_SCB_UART_SUCCESS)
+ Cy_SCB_UART_Enable(uart_dev->base);
+
+ return USARTx_convert_retval(cy_retval);
+}
+
+static ARM_USART_STATUS ARM_USARTx_GetStatus(UARTx_Resources* uart_dev)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USARTx_SetModemControl(UARTx_Resources* uart_dev,
+ ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USARTx_GetModemStatus(UARTx_Resources* uart_dev)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+/* Per-UART macros */
+#define DEFINE_UARTX(N) static UARTx_Resources USART##N##_DEV = { \
+ .base = SCB##N, \
+ .tx_nbr_bytes = 0, \
+ .rx_nbr_bytes = 0, \
+ .cb_event = NULL, \
+}; \
+\
+static int32_t ARM_USART##N##_Initialize(ARM_USART_SignalEvent_t cb_event) \
+{ \
+ USART##N##_DEV.cb_event = cb_event; \
+ return ARM_USARTx_Initialize(&USART##N##_DEV); \
+} \
+\
+static int32_t ARM_USART##N##_Uninitialize(void) \
+{ \
+ return ARM_USARTx_Uninitialize(&USART##N##_DEV); \
+} \
+\
+static int32_t ARM_USART##N##_PowerControl(ARM_POWER_STATE state) \
+{ \
+ return ARM_USARTx_PowerControl(&USART##N##_DEV, state); \
+} \
+ \
+static int32_t ARM_USART##N##_Send(const void *data, uint32_t num) \
+{ \
+ return ARM_USARTx_Send(&USART##N##_DEV, data, num); \
+} \
+ \
+static int32_t ARM_USART##N##_Receive(void *data, uint32_t num) \
+{ \
+ return ARM_USARTx_Receive(&USART##N##_DEV, data, num); \
+} \
+ \
+static int32_t ARM_USART##N##_Transfer(const void *data_out, void *data_in, \
+ uint32_t num) \
+{ \
+ return ARM_USARTx_Transfer(&USART##N##_DEV, data_out, data_in, num); \
+} \
+ \
+static uint32_t ARM_USART##N##_GetTxCount(void) \
+{ \
+ return ARM_USARTx_GetTxCount(&USART##N##_DEV); \
+} \
+ \
+static uint32_t ARM_USART##N##_GetRxCount(void) \
+{ \
+ return ARM_USARTx_GetRxCount(&USART##N##_DEV); \
+} \
+static int32_t ARM_USART##N##_Control(uint32_t control, uint32_t arg) \
+{ \
+ return ARM_USARTx_Control(&USART##N##_DEV, control, arg); \
+} \
+ \
+static ARM_USART_STATUS ARM_USART##N##_GetStatus(void) \
+{ \
+ return ARM_USARTx_GetStatus(&USART##N##_DEV); \
+} \
+ \
+static int32_t ARM_USART##N##_SetModemControl(ARM_USART_MODEM_CONTROL control) \
+{ \
+ return ARM_USARTx_SetModemControl(&USART##N##_DEV, control); \
+} \
+ \
+static ARM_USART_MODEM_STATUS ARM_USART##N##_GetModemStatus(void) \
+{ \
+ return ARM_USARTx_GetModemStatus(&USART##N##_DEV); \
+} \
+ \
+extern ARM_DRIVER_USART Driver_USART##N; \
+ARM_DRIVER_USART Driver_USART##N = { \
+ ARM_USART_GetVersion, \
+ ARM_USART_GetCapabilities, \
+ ARM_USART##N##_Initialize, \
+ ARM_USART##N##_Uninitialize, \
+ ARM_USART##N##_PowerControl, \
+ ARM_USART##N##_Send, \
+ ARM_USART##N##_Receive, \
+ ARM_USART##N##_Transfer, \
+ ARM_USART##N##_GetTxCount, \
+ ARM_USART##N##_GetRxCount, \
+ ARM_USART##N##_Control, \
+ ARM_USART##N##_GetStatus, \
+ ARM_USART##N##_SetModemControl, \
+ ARM_USART##N##_GetModemStatus \
+};
+
+#if (RTE_USART0)
+DEFINE_UARTX(0)
+#endif
+
+#if (RTE_USART1)
+DEFINE_UARTX(1)
+#endif
+
+#if (RTE_USART2)
+DEFINE_UARTX(2)
+#endif
+
+#if (RTE_USART3)
+DEFINE_UARTX(3)
+#endif
+
+#if (RTE_USART4)
+DEFINE_UARTX(4)
+#endif
+
+#if (RTE_USART5)
+DEFINE_UARTX(5)
+#endif
+
+#if (RTE_USART6)
+DEFINE_UARTX(6)
+#endif
+
+#if (RTE_USART7)
+DEFINE_UARTX(7)
+#endif
diff --git a/platform/ext/target/cypress/psoc64/Device/Config/device_cfg.h b/platform/ext/target/cypress/psoc64/Device/Config/device_cfg.h
new file mode 100644
index 0000000..531f926
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Config/device_cfg.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017-2018 Arm Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_DEVICE_CFG_H__
+#define __ARM_LTD_DEVICE_CFG_H__
+
+/**
+ * \file device_cfg.h
+ * \brief Configuration file native driver re-targeting
+ *
+ * \details This file can be used to add native driver specific macro
+ * definitions to select which peripherals are available in the build.
+ *
+ * This is a default device configuration file with all peripherals enabled.
+ */
+
+#define DEFAULT_UART_BAUDRATE 115200
+
+#endif /* __ARM_LTD_DEVICE_CFG_H__ */
diff --git a/platform/ext/target/cypress/psoc64/Device/Include/cmsis.h b/platform/ext/target/cypress/psoc64/Device/Include/cmsis.h
new file mode 100644
index 0000000..5c28355
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Include/cmsis.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_H__
+#define __CMSIS_H__
+
+/* CMSIS wrapper for PSoC 6 board */
+
+#include "cmsis_compiler.h"
+#include "system_psoc6.h"
+#include "cy_device_headers.h"
+#include "platform_regs.h" /* Platform registers */
+#include "platform_base_address.h" /* Peripherals base addresses */
+
+#endif /*__CMSIS_H__ */
diff --git a/platform/ext/target/cypress/psoc64/Device/Include/device_definition.h b/platform/ext/target/cypress/psoc64/Device/Include/device_definition.h
new file mode 100644
index 0000000..981a0e0
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Include/device_definition.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2017-2018 Arm Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file device_definition.h
+ * \brief The structure definitions in this file are exported based on the peripheral
+ * definitions from device_cfg.h.
+ * This retarget file is meant to be used as a helper for baremetal
+ * applications and/or as an example of how to configure the generic
+ * driver structures.
+ */
+
+#ifndef __DEVICE_DEFINITION_H__
+#define __DEVICE_DEFINITION_H__
+
+#include "device_cfg.h"
+
+
+/* ======= Defines peripheral configuration structures ======= */
+/* ======= and includes generic driver headers if necessary ======= */
+/* CMSDK Timer driver structures */
+#ifdef CMSDK_TIMER0_S
+#include "timer_cmsdk_drv.h"
+extern struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S;
+#endif
+#ifdef CMSDK_TIMER0_NS
+#include "timer_cmsdk_drv.h"
+extern struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS;
+#endif
+
+#ifdef CMSDK_TIMER1_S
+#include "timer_cmsdk_drv.h"
+extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S;
+#endif
+#ifdef CMSDK_TIMER1_NS
+#include "timer_cmsdk_drv.h"
+extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS;
+#endif
+
+#endif /* __DEVICE_DEFINITION_H__ */
diff --git a/platform/ext/target/cypress/psoc64/Device/Include/platform_base_address.h b/platform/ext/target/cypress/psoc64/Device/Include/platform_base_address.h
new file mode 100644
index 0000000..f90be77
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Include/platform_base_address.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.01 Device\_Template_Vendor\Vendor\Device\Include\Device.h
+ */
+
+#ifndef __PLATFORM_BASE_ADDRESS_H__
+#define __PLATFORM_BASE_ADDRESS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+/* Non-Secure Peripheral and SRAM base address */
+/* Secure Peripheral and SRAM base address */
+
+/* SRAM MPC ranges and limits */
+/* Internal memory */
+
+/* Code SRAM memory */
+
+/* QSPI Flash memory */
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLATFORM_BASE_ADDRESS_H__ */
diff --git a/platform/ext/target/cypress/psoc64/Device/Include/platform_description.h b/platform/ext/target/cypress/psoc64/Device/Include/platform_description.h
new file mode 100644
index 0000000..e5760c7
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Include/platform_description.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __PLATFORM_DESCRIPTION_H__
+#define __PLATFORM_DESCRIPTION_H__
+
+#include "platform_base_address.h"
+#include "platform_pins.h"
+#include "platform_regs.h"
+#include "cmsis.h"
+
+#endif /* __PLATFORM_DESCRIPTION_H__ */
diff --git a/platform/ext/target/cypress/psoc64/Device/Include/platform_pins.h b/platform/ext/target/cypress/psoc64/Device/Include/platform_pins.h
new file mode 100644
index 0000000..d883093
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Include/platform_pins.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_pins.h
+ * \brief This file defines all the pins for this platform.
+ */
+
+#ifndef __PLATFORM_PINS__
+#define __PLATFORM_PINS__
+
+#endif /* __PLATFORM_PINS__ */
diff --git a/platform/ext/target/cypress/psoc64/Device/Include/platform_regs.h b/platform/ext/target/cypress/psoc64/Device/Include/platform_regs.h
new file mode 100644
index 0000000..1fddeae
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Include/platform_regs.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2016-2018 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __PLATFORM_REGS_H__
+#define __PLATFORM_REGS_H__
+
+/* ARM APB PPCEXP1 peripherals definition */
+/* End of ARM AHB PPC0 peripherals definition */
+
+#endif /* __PLATFORM_REGS_H__ */
diff --git a/platform/ext/target/cypress/psoc64/Device/Source/armclang/psoc6_ns.sct b/platform/ext/target/cypress/psoc64/Device/Source/armclang/psoc6_ns.sct
new file mode 100644
index 0000000..c9c71d6
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Source/armclang/psoc6_ns.sct
@@ -0,0 +1,53 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "region_defs.h"
+
+LR_CODE NS_CODE_START {
+ ER_CODE NS_CODE_START NS_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+ ER_DATA NS_DATA_START NS_DATA_SIZE {
+ .ANY (+ZI +RW)
+ }
+
+ /* MSP */
+ ARM_LIB_STACK_MSP +0 ALIGN 32 EMPTY NS_MSP_STACK_SIZE {
+ }
+
+ /* PSP */
+ ARM_LIB_STACK +0 ALIGN 32 EMPTY NS_PSP_STACK_SIZE {
+ }
+
+ ARM_LIB_HEAP +0 ALIGN 8 EMPTY NS_HEAP_SIZE {
+ }
+
+ /* Executable code allocated in RAM */
+ TFM_RAM_CODE +0 ALIGN 32 {
+ * (.ramfunc)
+ }
+
+#if defined (NS_DATA_SHARED_START)
+ /* Shared memory data */
+ TFM_SHARED_MEM NS_DATA_SHARED_START EMPTY NS_DATA_SHARED_SIZE {
+ }
+#endif
+}
+
diff --git a/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_ns.s b/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_ns.s
new file mode 100644
index 0000000..0ce210d
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_ns.s
@@ -0,0 +1,708 @@
+;/*
+; * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+; * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; adapted from Cypress PSoC64 Peripheral-Driver-Library v1.3.1
+; startup_psoc6_02_cm4.s*/
+;
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+ EXPORT __ramVectors
+ IMPORT Cy_SysIpcPipeIsrCm4
+ IMPORT Cy_Flash_ResumeIrqHandler
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External interrupts Description
+ DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0
+ DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1
+ DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2
+ DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3
+ DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4
+ DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5
+ DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6
+ DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7
+ DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8
+ DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9
+ DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10
+ DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11
+ DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12
+ DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13
+ DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14
+ DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports
+ DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt
+ DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt
+ DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable)
+ DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
+ DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
+ DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
+ DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)
+ DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0
+ DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1
+ DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2
+ DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3
+ DCD Cy_SysIpcPipeIsrCm4
+ DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5
+ DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6
+ DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7
+ DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8
+ DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9
+ DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10
+ DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11
+ DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12
+ DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13
+ DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14
+ DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15
+ DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0
+ DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1
+ DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2
+ DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3
+ DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4
+ DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5
+ DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6
+ DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7
+ DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9
+ DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10
+ DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11
+ DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #1
+ DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
+ DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0
+ DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1
+ DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2
+ DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3
+ DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0
+ DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1
+ DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2
+ DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3
+ DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4
+ DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5
+ DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6
+ DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7
+ DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8
+ DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9
+ DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10
+ DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11
+ DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12
+ DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13
+ DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14
+ DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15
+ DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16
+ DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17
+ DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18
+ DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19
+ DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20
+ DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21
+ DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22
+ DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23
+ DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24
+ DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25
+ DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26
+ DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27
+ DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28
+ DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0
+ DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1
+ DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2
+ DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3
+ DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4
+ DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5
+ DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6
+ DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7
+ DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8
+ DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9
+ DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10
+ DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11
+ DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12
+ DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13
+ DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14
+ DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15
+ DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16
+ DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17
+ DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18
+ DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19
+ DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20
+ DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21
+ DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22
+ DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23
+ DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24
+ DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25
+ DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26
+ DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27
+ DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28
+ DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0
+ DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1
+ DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt
+ DCD Cy_Flash_ResumeIrqHandler
+ DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault
+ DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0
+ DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1
+ DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0
+ DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1
+ DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
+ DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
+ DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
+ DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
+ DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
+ DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
+ DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
+ DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
+ DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
+ DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
+ DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2
+ DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3
+ DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4
+ DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5
+ DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6
+ DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7
+ DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8
+ DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9
+ DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10
+ DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11
+ DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12
+ DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13
+ DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14
+ DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15
+ DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16
+ DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17
+ DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18
+ DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19
+ DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20
+ DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21
+ DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22
+ DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23
+ DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
+ DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt
+ DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt
+ DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt
+ DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
+ DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
+ DCD usb_interrupt_hi_IRQHandler ; USB Interrupt
+ DCD usb_interrupt_med_IRQHandler ; USB Interrupt
+ DCD usb_interrupt_lo_IRQHandler ; USB Interrupt
+ DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc
+ DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else
+ DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used
+ DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA RESET_RAM, READWRITE, NOINIT
+__ramVectors
+ SPACE __Vectors_Size
+
+ AREA |.text|, CODE, READONLY
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT Cy_SystemInitFpuEnable
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =Cy_SystemInitFpuEnable
+ BLX R0
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+ EXPORT Cy_SysLib_FaultHandler [WEAK]
+ AREA |.text|, CODE, READONLY
+Cy_SysLib_FaultHandler
+ B .
+
+ EXPORT HardFault_Handler [WEAK]
+ AREA |.text|, CODE, READONLY
+HardFault_Handler
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq L_MSP
+ mrs r0, PSP
+ b L_API_call
+L_MSP
+ mrs r0, MSP
+L_API_call
+ ; Storing LR content for Creator call stack trace
+ push {LR}
+ bl Cy_SysLib_FaultHandler
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+
+Default_Handler PROC
+ EXPORT Default_Handler [WEAK]
+ EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK]
+ EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK]
+ EXPORT ioss_interrupt_gpio_IRQHandler [WEAK]
+ EXPORT ioss_interrupt_vdd_IRQHandler [WEAK]
+ EXPORT lpcomp_interrupt_IRQHandler [WEAK]
+ EXPORT scb_8_interrupt_IRQHandler [WEAK]
+ EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK]
+ EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK]
+ EXPORT srss_interrupt_backup_IRQHandler [WEAK]
+ EXPORT srss_interrupt_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK]
+ EXPORT scb_0_interrupt_IRQHandler [WEAK]
+ EXPORT scb_1_interrupt_IRQHandler [WEAK]
+ EXPORT scb_2_interrupt_IRQHandler [WEAK]
+ EXPORT scb_3_interrupt_IRQHandler [WEAK]
+ EXPORT scb_4_interrupt_IRQHandler [WEAK]
+ EXPORT scb_5_interrupt_IRQHandler [WEAK]
+ EXPORT scb_6_interrupt_IRQHandler [WEAK]
+ EXPORT scb_7_interrupt_IRQHandler [WEAK]
+ EXPORT scb_9_interrupt_IRQHandler [WEAK]
+ EXPORT scb_10_interrupt_IRQHandler [WEAK]
+ EXPORT scb_11_interrupt_IRQHandler [WEAK]
+ EXPORT scb_12_interrupt_IRQHandler [WEAK]
+ EXPORT csd_interrupt_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dmac_2_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dmac_3_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK]
+ EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK]
+ EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK]
+ EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK]
+ EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK]
+ EXPORT pass_interrupt_sar_IRQHandler [WEAK]
+ EXPORT audioss_0_interrupt_i2s_IRQHandler [WEAK]
+ EXPORT audioss_0_interrupt_pdm_IRQHandler [WEAK]
+ EXPORT audioss_1_interrupt_i2s_IRQHandler [WEAK]
+ EXPORT profile_interrupt_IRQHandler [WEAK]
+ EXPORT smif_interrupt_IRQHandler [WEAK]
+ EXPORT usb_interrupt_hi_IRQHandler [WEAK]
+ EXPORT usb_interrupt_med_IRQHandler [WEAK]
+ EXPORT usb_interrupt_lo_IRQHandler [WEAK]
+ EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK]
+ EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK]
+ EXPORT sdhc_1_interrupt_wakeup_IRQHandler [WEAK]
+ EXPORT sdhc_1_interrupt_general_IRQHandler [WEAK]
+
+ioss_interrupts_gpio_0_IRQHandler
+ioss_interrupts_gpio_1_IRQHandler
+ioss_interrupts_gpio_2_IRQHandler
+ioss_interrupts_gpio_3_IRQHandler
+ioss_interrupts_gpio_4_IRQHandler
+ioss_interrupts_gpio_5_IRQHandler
+ioss_interrupts_gpio_6_IRQHandler
+ioss_interrupts_gpio_7_IRQHandler
+ioss_interrupts_gpio_8_IRQHandler
+ioss_interrupts_gpio_9_IRQHandler
+ioss_interrupts_gpio_10_IRQHandler
+ioss_interrupts_gpio_11_IRQHandler
+ioss_interrupts_gpio_12_IRQHandler
+ioss_interrupts_gpio_13_IRQHandler
+ioss_interrupts_gpio_14_IRQHandler
+ioss_interrupt_gpio_IRQHandler
+ioss_interrupt_vdd_IRQHandler
+lpcomp_interrupt_IRQHandler
+scb_8_interrupt_IRQHandler
+srss_interrupt_mcwdt_0_IRQHandler
+srss_interrupt_mcwdt_1_IRQHandler
+srss_interrupt_backup_IRQHandler
+srss_interrupt_IRQHandler
+cpuss_interrupts_ipc_0_IRQHandler
+cpuss_interrupts_ipc_1_IRQHandler
+cpuss_interrupts_ipc_2_IRQHandler
+cpuss_interrupts_ipc_3_IRQHandler
+cpuss_interrupts_ipc_5_IRQHandler
+cpuss_interrupts_ipc_6_IRQHandler
+cpuss_interrupts_ipc_7_IRQHandler
+cpuss_interrupts_ipc_8_IRQHandler
+cpuss_interrupts_ipc_9_IRQHandler
+cpuss_interrupts_ipc_10_IRQHandler
+cpuss_interrupts_ipc_11_IRQHandler
+cpuss_interrupts_ipc_12_IRQHandler
+cpuss_interrupts_ipc_13_IRQHandler
+cpuss_interrupts_ipc_14_IRQHandler
+cpuss_interrupts_ipc_15_IRQHandler
+scb_0_interrupt_IRQHandler
+scb_1_interrupt_IRQHandler
+scb_2_interrupt_IRQHandler
+scb_3_interrupt_IRQHandler
+scb_4_interrupt_IRQHandler
+scb_5_interrupt_IRQHandler
+scb_6_interrupt_IRQHandler
+scb_7_interrupt_IRQHandler
+scb_9_interrupt_IRQHandler
+scb_10_interrupt_IRQHandler
+scb_11_interrupt_IRQHandler
+scb_12_interrupt_IRQHandler
+csd_interrupt_IRQHandler
+cpuss_interrupts_dmac_0_IRQHandler
+cpuss_interrupts_dmac_1_IRQHandler
+cpuss_interrupts_dmac_2_IRQHandler
+cpuss_interrupts_dmac_3_IRQHandler
+cpuss_interrupts_dw0_0_IRQHandler
+cpuss_interrupts_dw0_1_IRQHandler
+cpuss_interrupts_dw0_2_IRQHandler
+cpuss_interrupts_dw0_3_IRQHandler
+cpuss_interrupts_dw0_4_IRQHandler
+cpuss_interrupts_dw0_5_IRQHandler
+cpuss_interrupts_dw0_6_IRQHandler
+cpuss_interrupts_dw0_7_IRQHandler
+cpuss_interrupts_dw0_8_IRQHandler
+cpuss_interrupts_dw0_9_IRQHandler
+cpuss_interrupts_dw0_10_IRQHandler
+cpuss_interrupts_dw0_11_IRQHandler
+cpuss_interrupts_dw0_12_IRQHandler
+cpuss_interrupts_dw0_13_IRQHandler
+cpuss_interrupts_dw0_14_IRQHandler
+cpuss_interrupts_dw0_15_IRQHandler
+cpuss_interrupts_dw0_16_IRQHandler
+cpuss_interrupts_dw0_17_IRQHandler
+cpuss_interrupts_dw0_18_IRQHandler
+cpuss_interrupts_dw0_19_IRQHandler
+cpuss_interrupts_dw0_20_IRQHandler
+cpuss_interrupts_dw0_21_IRQHandler
+cpuss_interrupts_dw0_22_IRQHandler
+cpuss_interrupts_dw0_23_IRQHandler
+cpuss_interrupts_dw0_24_IRQHandler
+cpuss_interrupts_dw0_25_IRQHandler
+cpuss_interrupts_dw0_26_IRQHandler
+cpuss_interrupts_dw0_27_IRQHandler
+cpuss_interrupts_dw0_28_IRQHandler
+cpuss_interrupts_dw1_0_IRQHandler
+cpuss_interrupts_dw1_1_IRQHandler
+cpuss_interrupts_dw1_2_IRQHandler
+cpuss_interrupts_dw1_3_IRQHandler
+cpuss_interrupts_dw1_4_IRQHandler
+cpuss_interrupts_dw1_5_IRQHandler
+cpuss_interrupts_dw1_6_IRQHandler
+cpuss_interrupts_dw1_7_IRQHandler
+cpuss_interrupts_dw1_8_IRQHandler
+cpuss_interrupts_dw1_9_IRQHandler
+cpuss_interrupts_dw1_10_IRQHandler
+cpuss_interrupts_dw1_11_IRQHandler
+cpuss_interrupts_dw1_12_IRQHandler
+cpuss_interrupts_dw1_13_IRQHandler
+cpuss_interrupts_dw1_14_IRQHandler
+cpuss_interrupts_dw1_15_IRQHandler
+cpuss_interrupts_dw1_16_IRQHandler
+cpuss_interrupts_dw1_17_IRQHandler
+cpuss_interrupts_dw1_18_IRQHandler
+cpuss_interrupts_dw1_19_IRQHandler
+cpuss_interrupts_dw1_20_IRQHandler
+cpuss_interrupts_dw1_21_IRQHandler
+cpuss_interrupts_dw1_22_IRQHandler
+cpuss_interrupts_dw1_23_IRQHandler
+cpuss_interrupts_dw1_24_IRQHandler
+cpuss_interrupts_dw1_25_IRQHandler
+cpuss_interrupts_dw1_26_IRQHandler
+cpuss_interrupts_dw1_27_IRQHandler
+cpuss_interrupts_dw1_28_IRQHandler
+cpuss_interrupts_fault_0_IRQHandler
+cpuss_interrupts_fault_1_IRQHandler
+cpuss_interrupt_crypto_IRQHandler
+cpuss_interrupts_cm4_fp_IRQHandler
+cpuss_interrupts_cm0_cti_0_IRQHandler
+cpuss_interrupts_cm0_cti_1_IRQHandler
+cpuss_interrupts_cm4_cti_0_IRQHandler
+cpuss_interrupts_cm4_cti_1_IRQHandler
+tcpwm_0_interrupts_0_IRQHandler
+tcpwm_0_interrupts_1_IRQHandler
+tcpwm_0_interrupts_2_IRQHandler
+tcpwm_0_interrupts_3_IRQHandler
+tcpwm_0_interrupts_4_IRQHandler
+tcpwm_0_interrupts_5_IRQHandler
+tcpwm_0_interrupts_6_IRQHandler
+tcpwm_0_interrupts_7_IRQHandler
+tcpwm_1_interrupts_0_IRQHandler
+tcpwm_1_interrupts_1_IRQHandler
+tcpwm_1_interrupts_2_IRQHandler
+tcpwm_1_interrupts_3_IRQHandler
+tcpwm_1_interrupts_4_IRQHandler
+tcpwm_1_interrupts_5_IRQHandler
+tcpwm_1_interrupts_6_IRQHandler
+tcpwm_1_interrupts_7_IRQHandler
+tcpwm_1_interrupts_8_IRQHandler
+tcpwm_1_interrupts_9_IRQHandler
+tcpwm_1_interrupts_10_IRQHandler
+tcpwm_1_interrupts_11_IRQHandler
+tcpwm_1_interrupts_12_IRQHandler
+tcpwm_1_interrupts_13_IRQHandler
+tcpwm_1_interrupts_14_IRQHandler
+tcpwm_1_interrupts_15_IRQHandler
+tcpwm_1_interrupts_16_IRQHandler
+tcpwm_1_interrupts_17_IRQHandler
+tcpwm_1_interrupts_18_IRQHandler
+tcpwm_1_interrupts_19_IRQHandler
+tcpwm_1_interrupts_20_IRQHandler
+tcpwm_1_interrupts_21_IRQHandler
+tcpwm_1_interrupts_22_IRQHandler
+tcpwm_1_interrupts_23_IRQHandler
+pass_interrupt_sar_IRQHandler
+audioss_0_interrupt_i2s_IRQHandler
+audioss_0_interrupt_pdm_IRQHandler
+audioss_1_interrupt_i2s_IRQHandler
+profile_interrupt_IRQHandler
+smif_interrupt_IRQHandler
+usb_interrupt_hi_IRQHandler
+usb_interrupt_med_IRQHandler
+usb_interrupt_lo_IRQHandler
+sdhc_0_interrupt_wakeup_IRQHandler
+sdhc_0_interrupt_general_IRQHandler
+sdhc_1_interrupt_wakeup_IRQHandler
+sdhc_1_interrupt_general_IRQHandler
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_s.s b/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_s.s
new file mode 100644
index 0000000..cbc8164
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_s.s
@@ -0,0 +1,145 @@
+;/*
+; * Copyright (c) 2017-2018 ARM Limited
+; * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; adapted from Cypress PSoC64 Peripheral-Driver-Library v1.3.1
+; startup_psoc6_02_cm0plus.s
+;
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+; Address of the NMI handler in ROM
+CY_NMI_HANLDER_ADDR EQU 0x0000000D
+
+ PRESERVE8
+
+ IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+ EXPORT __ramVectors
+
+ IMPORT HardFault_Handler
+ IMPORT SVC_Handler
+ IMPORT PendSV_Handler
+ IMPORT NvicMux7_IRQHandler
+ IMPORT Cy_SysIpcPipeIsrCm0
+
+__Vectors ;Core Interrupts
+ DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD CY_NMI_HANLDER_ADDR ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External interrupts Description
+ DCD NvicMux0_IRQHandler ; CPU User Interrupt #0
+ DCD Cy_SysIpcPipeIsrCm0
+ DCD NvicMux2_IRQHandler ; CPU User Interrupt #2
+ DCD NvicMux3_IRQHandler ; CPU User Interrupt #3
+ DCD NvicMux4_IRQHandler ; CPU User Interrupt #4
+ DCD NvicMux5_IRQHandler ; CPU User Interrupt #5
+ DCD NvicMux6_IRQHandler ; CPU User Interrupt #6
+ DCD NvicMux7_IRQHandler ; CPU User Interrupt #7
+ DCD Internal0_IRQHandler ; Internal SW Interrupt #0
+ DCD Internal1_IRQHandler ; Internal SW Interrupt #1
+ DCD Internal2_IRQHandler ; Internal SW Interrupt #2
+ DCD Internal3_IRQHandler ; Internal SW Interrupt #3
+ DCD Internal4_IRQHandler ; Internal SW Interrupt #4
+ DCD Internal5_IRQHandler ; Internal SW Interrupt #5
+ DCD Internal6_IRQHandler ; Internal SW Interrupt #6
+ DCD Internal7_IRQHandler ; Internal SW Interrupt #7
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA RESET_RAM, READWRITE, NOINIT
+__ramVectors
+ SPACE __Vectors_Size
+
+; Reset Handler
+ AREA |.text|, CODE, READONLY
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ CPSID i ; Disable IRQs
+ LDR R0, =SystemInit
+ BLX R0
+ MOV R3, SP
+ MRS R0, control ; Get control value
+ MOVS R1, #2
+ ORRS R0, R0, R1 ; Select switch to PSP
+
+ MSR control, R0
+ MOV SP, R3
+ LDR R0, =__main
+ BX R0
+ ENDP
+End_Of_Main
+ B .
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+ MACRO
+ Default_Handler $handler_name
+$handler_name PROC
+ EXPORT $handler_name [WEAK]
+ B .
+ ENDP
+ MEND
+
+ Default_Handler SysTick_Handler
+ Default_Handler NvicMux0_IRQHandler
+ Default_Handler NvicMux2_IRQHandler
+ Default_Handler NvicMux3_IRQHandler
+ Default_Handler NvicMux4_IRQHandler
+ Default_Handler NvicMux5_IRQHandler
+ Default_Handler NvicMux6_IRQHandler
+ Default_Handler Internal0_IRQHandler
+ Default_Handler Internal1_IRQHandler
+ Default_Handler Internal2_IRQHandler
+ Default_Handler Internal3_IRQHandler
+ Default_Handler Internal4_IRQHandler
+ Default_Handler Internal5_IRQHandler
+ Default_Handler Internal6_IRQHandler
+ Default_Handler Internal7_IRQHandler
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/cypress/psoc64/Device/Source/device_definition.c b/platform/ext/target/cypress/psoc64/Device/Source/device_definition.c
new file mode 100644
index 0000000..b11f5b2
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Source/device_definition.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file device_definition.c
+ * \brief This file defines exports the structures based on the peripheral
+ * definitions from device_cfg.h.
+ * This retarget file is meant to be used as a helper for baremetal
+ * applications and/or as an example of how to configure the generic
+ * driver structures.
+ */
+
+#include "device_definition.h"
+#include "platform_base_address.h"
+
+/* CMSDK Timer driver structures */
+#ifdef CMSDK_TIMER0_S
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S = {
+ .base = CMSDK_TIMER0_BASE_S};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_S = {
+ .is_initialized = 0};
+struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S = {&(CMSDK_TIMER0_DEV_CFG_S),
+ &(CMSDK_TIMER0_DEV_DATA_S)};
+#endif
+#ifdef CMSDK_TIMER0_NS
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_NS = {
+ .base = CMSDK_TIMER0_BASE_NS};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_NS = {
+ .is_initialized = 0};
+struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS = {&(CMSDK_TIMER0_DEV_CFG_NS),
+ &(CMSDK_TIMER0_DEV_DATA_NS)};
+#endif
+
+#ifdef CMSDK_TIMER1_S
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_S = {
+ .base = CMSDK_TIMER1_BASE_S};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_S = {
+ .is_initialized = 0};
+struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S = {&(CMSDK_TIMER1_DEV_CFG_S),
+ &(CMSDK_TIMER1_DEV_DATA_S)};
+#endif
+#ifdef CMSDK_TIMER1_NS
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_NS = {
+ .base = CMSDK_TIMER1_BASE_NS};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_NS = {
+ .is_initialized = 0};
+struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS = {&(CMSDK_TIMER1_DEV_CFG_NS),
+ &(CMSDK_TIMER1_DEV_DATA_NS)};
+#endif
+
diff --git a/platform/ext/target/cypress/psoc64/Device/Source/gcc/psoc6_ns.ld b/platform/ext/target/cypress/psoc64/Device/Source/gcc/psoc6_ns.ld
new file mode 100644
index 0000000..77a436a
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Source/gcc/psoc6_ns.ld
@@ -0,0 +1,421 @@
+/*
+ * Copyright (c) 2018-2019 ARM Limited
+ * Copyright 2016-2018 Cypress Semiconductor Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of Cypress PDL 3.0 cy8c6xx7_cm4_dual.ld
+ */
+
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+#include "region_defs.h"
+
+__heap_size__ = NS_HEAP_SIZE;
+__psp_stack_size__ = NS_PSP_STACK_SIZE;
+__msp_stack_size__ = NS_MSP_STACK_SIZE;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+ */
+ ram (rwx) : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE
+ flash (rx) : ORIGIN = NS_CODE_START, LENGTH = NS_CODE_SIZE
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
+ sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
+ sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+#endif
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+ } > flash
+
+ __etext = . ;
+
+
+#ifdef RAM_VECTORS_SUPPORT
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+ .data __ram_vectors_end__ : AT (__etext)
+#else
+ .data : AT (__etext)
+#endif
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.ramfunc))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ PROVIDE(end = .);
+ end = __end__;
+ . += __heap_size__;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > ram
+
+ .msp_stack : ALIGN(32)
+ {
+ . += __msp_stack_size__;
+ } > ram
+ Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+ .psp_stack : ALIGN(32)
+ {
+ . += __psp_stack_size__;
+ } > ram
+
+ Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack);
+ Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);
+
+ PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);
+
+ Image$$ER_TFM_DATA$$RW$$Base = ADDR(.data);
+ Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.data) + SIZEOF(.data);
+
+ Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.bss);
+ Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.bss) + SIZEOF(.bss);
+
+ Image$$ER_TFM_DATA$$Base = ADDR(.data);
+ Image$$ER_TFM_DATA$$Limit = ADDR(.data) + SIZEOF(.data) + SIZEOF(.bss);
+
+#if defined (NS_DATA_SHARED_START)
+ .TFM_SHARED NS_DATA_SHARED_START (NOLOAD) :
+ {
+ . = ALIGN(4);
+ . += NS_DATA_SHARED_SIZE;
+ } > ram
+#endif
+
+ /* Used for the digital signature of the secure application and the Bootloader SDK appication.
+ * The size of the section depends on the required data size. */
+ .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
+ {
+ KEEP(*(.cy_app_signature))
+ } > flash
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+
+ /* Supervisory Flash: Table of Content # 2 Copy */
+ .cy_rtoc_part2 :
+ {
+ KEEP(*(.cy_rtoc_part2))
+ } > sflash_rtoc_2
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ .cy_xip :
+ {
+ KEEP(*(.cy_xip))
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+
+ /* These sections are used for additional metadata (silicon revision,
+ * Silicon/JTAG ID, etc.) storage.
+ */
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start = 0x10000000;
+__cy_memory_0_length = 0x00100000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start = 0x14000000;
+__cy_memory_1_length = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start = 0x16000000;
+__cy_memory_2_length = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start = 0x18000000;
+__cy_memory_3_length = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start = 0x90700000;
+__cy_memory_4_length = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_ns.S b/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_ns.S
new file mode 100644
index 0000000..abdc5bb
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_ns.S
@@ -0,0 +1,662 @@
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* adapted from Cypress PSoC64 Peripheral-Driver-Library v1.3.1
+ startup_psoc6_02_cm4.S*/
+
+#include "region_defs.h"
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ .long Cy_SysIpcPipeIsrCm4
+ .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
+ .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
+ .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
+ .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
+ .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
+ .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
+ .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
+ .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
+ .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
+ .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
+ .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
+ .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
+ .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
+ .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
+ .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
+ .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
+ .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
+ .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
+ .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
+ .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
+ .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
+ .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
+ .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
+ .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
+ .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
+ .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
+ .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
+ .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
+ .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
+ .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
+ .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
+ .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
+ .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
+ .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
+ .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ .long Cy_Flash_ResumeIrqHandler /* FLASH Macro Interrupt */
+ .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
+ .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
+ .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
+ .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
+ .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ .long usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_med_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
+ .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+ .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
+ .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+#ifdef RAM_VECTORS_SUPPORT
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+#else
+ /* vectors relocation is not supported,
+ but allocate __ramVectors for PDL code */
+ .globl __ramVectors
+ .equ __ramVectors, 0
+#endif
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /* Device startup customization */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+
+Cy_OnResetUser:
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Saves and disables the interrupts */
+ .global Cy_SaveIRQ
+ .func Cy_SaveIRQ, Cy_SaveIRQ
+ .type Cy_SaveIRQ, %function
+
+Cy_SaveIRQ:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+ .size Cy_SaveIRQ, . - Cy_SaveIRQ
+ .endfunc
+
+ /* Restores the interrupts */
+ .global Cy_RestoreIRQ
+ .func Cy_RestoreIRQ, Cy_RestoreIRQ
+ .type Cy_RestoreIRQ, %function
+
+Cy_RestoreIRQ:
+ msr PRIMASK, r0
+ bx lr
+ .size Cy_RestoreIRQ, . - Cy_RestoreIRQ
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+
+Reset_Handler:
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+#endif
+
+ /* Enable the FPU if used */
+ bl Cy_SystemInitFpuEnable
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ cpsie i
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+ .type Fault_Handler, %function
+
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+.L_API_call:
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+
+ def_fault_Handler HardFault_Handler
+ def_fault_Handler MemManage_Handler
+ def_fault_Handler BusFault_Handler
+ def_fault_Handler UsageFault_Handler
+
+ def_irq_handler DebugMon_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
+ def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
+ def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
+ def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
+ def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
+ def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
+ def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
+ def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
+ def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
+ def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
+ def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
+ def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
+ def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
+ def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
+ def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
+ def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
+ def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
+ def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
+ def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
+ def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
+ def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
+ def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
+ def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
+ def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
+ def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
+ def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
+ def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
+ def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
+ def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
+ def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
+ def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
+ def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
+ def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
+ def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
+ def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
+ def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
+ def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
+ def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
+ def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
+ def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
+ def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+ def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
+ def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S b/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S
new file mode 100644
index 0000000..cb95acf
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S
@@ -0,0 +1,355 @@
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* adapted from Cypress PSoC64 Peripheral-Driver-Library v1.3.1
+ startup_psoc6_02_cm0plus.S*/
+
+#include "region_defs.h"
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */
+ .long Cy_SysIpcPipeIsrCm0
+ .long NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */
+ .long NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */
+ .long NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */
+ .long NvicMux5_IRQHandler /* CM0 + NVIC Mux input 5 */
+ .long NvicMux6_IRQHandler /* CM0 + NVIC Mux input 6 */
+ .long NvicMux7_IRQHandler /* CM0 + NVIC Mux input 7 */
+ .long Internal0_IRQHandler /* Internal SW Interrupt #0 */
+ .long Internal1_IRQHandler /* Internal SW Interrupt #1 */
+ .long Internal2_IRQHandler /* Internal SW Interrupt #2 */
+ .long Internal3_IRQHandler /* Internal SW Interrupt #3 */
+ .long Internal4_IRQHandler /* Internal SW Interrupt #4 */
+ .long Internal5_IRQHandler /* Internal SW Interrupt #5 */
+ .long Internal6_IRQHandler /* Internal SW Interrupt #6 */
+ .long Internal7_IRQHandler /* Internal SW Interrupt #7 */
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+#ifdef RAM_VECTORS_SUPPORT
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+#else
+ /* vectors relocation is not supported,
+ but allocate __ramVectors for PDL code */
+ .globl __ramVectors
+ .equ __ramVectors, 0
+#endif
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /* Device startup customization */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+
+Cy_OnResetUser:
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Saves and disables the interrupts */
+ .global Cy_SaveIRQ
+ .func Cy_SaveIRQ, Cy_SaveIRQ
+ .type Cy_SaveIRQ, %function
+Cy_SaveIRQ:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+ .size Cy_SaveIRQ, . - Cy_SaveIRQ
+ .endfunc
+
+ /* Restores the interrupts */
+ .global Cy_RestoreIRQ
+ .func Cy_RestoreIRQ, Cy_RestoreIRQ
+ .type Cy_RestoreIRQ, %function
+Cy_RestoreIRQ:
+ msr PRIMASK, r0
+ bx lr
+ .size Cy_RestoreIRQ, . - Cy_RestoreIRQ
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+
+Reset_Handler:
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifdef RAM_VECTORS_SUPPORT
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ mrs r0, control /* Get control value */
+ movs r1, #2
+ orrs r0, r0, r1 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+ msr psp, r0
+
+ bl main
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+ .type Fault_Handler, %function
+
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+.L_API_call:
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */
+ def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */
+ def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */
+ def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */
+ def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */
+ def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */
+ def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */
+ def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */
+ def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */
+ def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */
+ def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */
+ def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */
+ def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */
+ def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */
+ def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/platform/ext/target/cypress/psoc64/Device/Source/system_psoc6_cm0plus.c b/platform/ext/target/cypress/psoc64/Device/Source/system_psoc6_cm0plus.c
index 9164b15..45dc6be 100644
--- a/platform/ext/target/cypress/psoc64/Device/Source/system_psoc6_cm0plus.c
+++ b/platform/ext/target/cypress/psoc64/Device/Source/system_psoc6_cm0plus.c
@@ -24,10 +24,13 @@
#include <stdbool.h>
#include "system_psoc6.h"
+#include "cycfg.h"
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
+#include "Driver_Flash.h"
+#include "flash_layout.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
@@ -156,6 +159,7 @@
#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL)
+void Cy_Platform_Init(void);
/*******************************************************************************
* Function Name: SystemInit
@@ -164,7 +168,6 @@
* Initializes the system:
* - Restores FLL registers to the default state.
* - Unlocks and disables WDT.
-* - Calls Cy_PDL_Init() function to define the driver library.
* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
* - Calls \ref SystemCoreClockUpdate().
*
@@ -173,6 +176,11 @@
{
Cy_PDL_Init(CY_DEVICE_CFG);
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern const cy_israddress __Vectors[]; /* Vector Table in flash */;
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
/* Restore FLL registers to the default state as they are not restored by the ROM code */
uint32_t copy = SRSS->CLK_FLL_CONFIG;
copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
@@ -203,69 +211,6 @@
IPC_STRUCT7->RELEASE = 0UL;
}
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
- /* Allocate and initialize semaphores for the system operations. */
- CY_SECTION(".cy_sharedmem")
- static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
-
- (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
-
-
- /********************************************************************************
- *
- * Initializes the system pipes. The system pipes are used by BLE and Flash.
- *
- * If the default startup file is not used, or SystemInit() is not called in your
- * project, call the following three functions prior to executing any flash or
- * EmEEPROM write or erase operation:
- * -# Cy_IPC_Sema_Init()
- * -# Cy_IPC_Pipe_Config()
- * -# Cy_IPC_Pipe_Init()
- * -# Cy_Flash_Init()
- *
- *******************************************************************************/
-
- /* Create an array of endpoint structures */
- static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
-
- Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
-
- static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
-
- static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
- {
- /* .ep0ConfigData */
- {
- /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
- /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
- /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
- /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
- /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
- },
- /* .ep1ConfigData */
- {
- /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
- /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
- /* .ipcNotifierMuxNumber */ 0u,
- /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
- /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
- },
- /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
- /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
- /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
- };
-
- if (cy_device->flashPipeRequired != 0u)
- {
- Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
- }
-
-#if defined(CY_DEVICE_PSOC6ABLE2)
- Cy_Flash_Init();
-#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
-
-#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
}
@@ -627,7 +572,8 @@
}
#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) && !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
/*******************************************************************************
* Function Name: Cy_SysIpcPipeIsrCm0
****************************************************************************//**
@@ -707,4 +653,99 @@
#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
+/*******************************************************************************
+* Function Name: Cy_Platform_Init
+****************************************************************************//**
+*
+* CM0 custom HW initialization
+*
+*******************************************************************************/
+void Cy_Platform_Init(void)
+{
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ /* Initialize semaphores for the system operations.*/
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ /********************************************************************************
+ *
+ * Initializes the system pipes. The system pipes are used by BLE and Flash.
+ *
+ * If the default startup file is not used, or SystemInit() is not called in your
+ * project, call the following three functions prior to executing any flash or
+ * EmEEPROM write or erase operation:
+ * -# Cy_IPC_Sema_Init()
+ * -# Cy_IPC_Pipe_Config()
+ * -# Cy_IPC_Pipe_Init()
+ * -# Cy_Flash_Init()
+ *
+ *******************************************************************************/
+
+ /* Create an array of endpoint structures */
+ static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
+
+ Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
+
+ static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
+
+ static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
+ {
+ /* .ep0ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
+ /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
+ },
+ /* .ep1ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
+ /* .ipcNotifierMuxNumber */ 0u,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
+ },
+ /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
+ /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
+ /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
+ };
+
+ if (cy_device->flashPipeRequired != 0u)
+ {
+ Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
+ }
+
+#if defined(CY_DEVICE_PSOC6ABLE2)
+ Cy_Flash_Init();
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+
+ return;
+}
+
+#ifdef BL2
+/* Flash device name must be specified by target */
+extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
+
+uint32_t bl2_platform_init(void)
+{
+ Cy_PDL_Init(CY_DEVICE_CFG);
+
+ init_cycfg_all();
+ Cy_Platform_Init();
+
+ /* make sure CM4 is disabled */
+ if (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status()) {
+ Cy_SysDisableCM4();
+ }
+
+ return FLASH_DEV_NAME.Initialize(NULL);
+}
+#endif
+
/* [] END OF FILE */
diff --git a/platform/ext/target/cypress/psoc64/Device/Source/system_psoc6_cm4.c b/platform/ext/target/cypress/psoc64/Device/Source/system_psoc6_cm4.c
index 0a18f50..b56bd56 100644
--- a/platform/ext/target/cypress/psoc64/Device/Source/system_psoc6_cm4.c
+++ b/platform/ext/target/cypress/psoc64/Device/Source/system_psoc6_cm4.c
@@ -28,7 +28,7 @@
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
-
+#include "cycfg.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
#include "cy_ipc_pipe.h"
@@ -39,6 +39,8 @@
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+#include "target_cfg.h"
+#include "Driver_USART.h"
/*******************************************************************************
* SystemCoreClockUpdate()
@@ -158,14 +160,24 @@
* Initializes the system:
* - Restores FLL registers to the default state for single core devices.
* - Unlocks and disables WDT.
-* - Calls Cy_PDL_Init() function to define the driver library.
* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
* - Calls \ref SystemCoreClockUpdate().
* \endcond
*******************************************************************************/
void SystemInit(void)
{
- Cy_PDL_Init(CY_DEVICE_CFG);
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern const cy_israddress __Vectors[]; /* Vector Table in flash */
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+ /*
+ * FIXME:
+ * Even if __FPU_USED is undefined or cleared, FP registers are still
+ * accessed inside armclang library. Not sure about why armclang doesn't
+ * care about the __FPU_USED.
+ */
+ SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
@@ -191,75 +203,6 @@
Cy_SystemInit();
SystemCoreClockUpdate();
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-
-#ifdef __CM0P_PRESENT
- #if (__CM0P_PRESENT == 0)
- /* Allocate and initialize semaphores for the system operations. */
- static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
- (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
- #else
- (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
- #endif /* (__CM0P_PRESENT) */
-#else
- (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
-#endif /* __CM0P_PRESENT */
-
-
- /********************************************************************************
- *
- * Initializes the system pipes. The system pipes are used by BLE and Flash.
- *
- * If the default startup file is not used, or SystemInit() is not called in your
- * project, call the following three functions prior to executing any flash or
- * EmEEPROM write or erase operation:
- * -# Cy_IPC_Sema_Init()
- * -# Cy_IPC_Pipe_Config()
- * -# Cy_IPC_Pipe_Init()
- * -# Cy_Flash_Init()
- *
- *******************************************************************************/
- /* Create an array of endpoint structures */
- static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
-
- Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
-
- static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
-
- static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 =
- {
- /* .ep0ConfigData */
- {
- /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
- /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
- /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
- /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
- /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
- },
- /* .ep1ConfigData */
- {
- /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
- /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
- /* .ipcNotifierMuxNumber */ 0u,
- /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
- /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
- },
- /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
- /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
- /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
- };
-
- if (cy_device->flashPipeRequired != 0u)
- {
- Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
- }
-
-#if defined(CY_DEVICE_PSOC6ABLE2)
- Cy_Flash_Init();
-#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
-
-#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
}
@@ -469,21 +412,6 @@
}
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-/*******************************************************************************
-* Function Name: Cy_SysIpcPipeIsrCm4
-****************************************************************************//**
-*
-* This is the interrupt service routine for the system pipe.
-*
-*******************************************************************************/
-void Cy_SysIpcPipeIsrCm4(void)
-{
- Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR);
-}
-#endif
-
-
/*******************************************************************************
* Function Name: Cy_MemorySymbols
****************************************************************************//**
@@ -549,4 +477,111 @@
#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) && !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+/*******************************************************************************
+* Function Name: Cy_SysIpcPipeIsrCm4
+****************************************************************************//**
+*
+* This is the interrupt service routine for the system pipe.
+*
+*******************************************************************************/
+void Cy_SysIpcPipeIsrCm4(void)
+{
+ Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR);
+}
+#endif
+
+
+/* For UART the CMSIS driver is used */
+extern ARM_DRIVER_USART NS_DRIVER_STDIO;
+
+/*******************************************************************************
+* Function Name: Cy_Platform_Init
+****************************************************************************//**
+*
+* CM4 custom HW initialization
+*
+*******************************************************************************/
+void Cy_Platform_Init(void)
+{
+ Cy_PDL_Init(CY_DEVICE_CFG);
+
+ (void)NS_DRIVER_STDIO.Initialize(NULL);
+ NS_DRIVER_STDIO.Control(ARM_USART_MODE_ASYNCHRONOUS, 115200);
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+#ifdef __CM0P_PRESENT
+ /* Allocate and initialize semaphores for the system operations. */
+ static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
+#else
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
+#endif /* __CM0P_PRESENT */
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ /********************************************************************************
+ *
+ * Initializes the system pipes. The system pipes are used by BLE and Flash.
+ *
+ * If the default startup file is not used, or SystemInit() is not called in your
+ * project, call the following three functions prior to executing any flash or
+ * EmEEPROM write or erase operation:
+ * -# Cy_IPC_Sema_Init()
+ * -# Cy_IPC_Pipe_Config()
+ * -# Cy_IPC_Pipe_Init()
+ * -# Cy_Flash_Init()
+ *
+ *******************************************************************************/
+ /* Create an array of endpoint structures */
+ static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
+
+ Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
+
+ static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
+
+ static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 =
+ {
+ /* .ep0ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
+ /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
+
+ },
+ /* .ep1ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
+ /* .ipcNotifierMuxNumber */ 0u,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
+ },
+ /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
+ /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
+ /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
+ };
+
+ if (cy_device->flashPipeRequired != 0u)
+ {
+ Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
+ }
+
+#if defined(CY_DEVICE_PSOC6ABLE2)
+ Cy_Flash_Init();
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+ return;
+}
+
+
+int32_t tfm_ns_platform_init (void)
+{
+ Cy_Platform_Init();
+ return ARM_DRIVER_OK;
+}
+
/* [] END OF FILE */
diff --git a/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_clocks.c b/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_clocks.c
index 7f720f7..a15b23e 100644
--- a/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_clocks.c
+++ b/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_clocks.c
@@ -41,6 +41,11 @@
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+
+ Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 54U);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
diff --git a/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.c b/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.c
index 71f1528..811b944 100644
--- a/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.c
+++ b/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.c
@@ -26,6 +26,35 @@
#include "cycfg_peripherals.h"
+const cy_stc_scb_uart_config_t KITPROG_UART_config =
+{
+ .uartMode = CY_SCB_UART_STANDARD,
+ .enableMutliProcessorMode = false,
+ .smartCardRetryOnNack = false,
+ .irdaInvertRx = false,
+ .irdaEnableLowPowerReceiver = false,
+ .oversample = 8,
+ .enableMsbFirst = false,
+ .dataWidth = 8UL,
+ .parity = CY_SCB_UART_PARITY_NONE,
+ .stopBits = CY_SCB_UART_STOP_BITS_1,
+ .enableInputFilter = false,
+ .breakWidth = 11UL,
+ .dropOnFrameError = false,
+ .dropOnParityError = false,
+ .receiverAddress = 0x0UL,
+ .receiverAddressMask = 0x0UL,
+ .acceptAddrInFifo = false,
+ .enableCts = false,
+ .ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rtsRxFifoLevel = 0UL,
+ .rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rxFifoTriggerLevel = 63UL,
+ .rxFifoIntEnableMask = 0UL,
+ .txFifoTriggerLevel = 63UL,
+ .txFifoIntEnableMask = 0UL,
+};
+
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
@@ -34,5 +63,6 @@
void init_cycfg_peripherals(void)
{
- Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+ Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+ Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
}
diff --git a/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.h b/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.h
index 5cdf515..b7b4c98 100644
--- a/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.h
+++ b/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.h
@@ -28,6 +28,7 @@
#define CYCFG_PERIPHERALS_H
#include "cycfg_notices.h"
+#include "cy_scb_uart.h"
#include "cy_sysclk.h"
#include "cy_csd.h"
@@ -72,6 +73,7 @@
#define CYBSP_CSD_HW CSD0
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
+extern const cy_stc_scb_uart_config_t KITPROG_UART_config;
extern cy_stc_csd_context_t cy_csd_0_context;
void init_cycfg_peripherals(void);
diff --git a/platform/ext/target/cypress/psoc64/Native_Driver/include/cy_prot.h b/platform/ext/target/cypress/psoc64/Native_Driver/include/cy_prot.h
index c51985c..14bf407 100644
--- a/platform/ext/target/cypress/psoc64/Native_Driver/include/cy_prot.h
+++ b/platform/ext/target/cypress/psoc64/Native_Driver/include/cy_prot.h
@@ -519,42 +519,80 @@
}cy_en_prot_perm_t;
/**
+* Bit shift of memory region size setting
+*/
+#define PROT_SIZE_4B_BIT_SHIFT 1U /**< 4 bytes */
+#define PROT_SIZE_8B_BIT_SHIFT 2U /**< 8 bytes */
+#define PROT_SIZE_16B_BIT_SHIFT 3U /**< 16 bytes */
+#define PROT_SIZE_32B_BIT_SHIFT 4U /**< 32 bytes */
+#define PROT_SIZE_64B_BIT_SHIFT 5U /**< 64 bytes */
+#define PROT_SIZE_128B_BIT_SHIFT 6U /**< 128 bytes */
+#define PROT_SIZE_256B_BIT_SHIFT 7U /**< 256 bytes */
+#define PROT_SIZE_512B_BIT_SHIFT 8U /**< 512 bytes */
+
+#define PROT_SIZE_1KB_BIT_SHIFT 9U /**< 1 Kilobyte */
+#define PROT_SIZE_2KB_BIT_SHIFT 10U /**< 2 Kilobytes */
+#define PROT_SIZE_4KB_BIT_SHIFT 11U /**< 4 Kilobytes */
+#define PROT_SIZE_8KB_BIT_SHIFT 12U /**< 8 Kilobytes */
+#define PROT_SIZE_16KB_BIT_SHIFT 13U /**< 16 Kilobytes */
+#define PROT_SIZE_32KB_BIT_SHIFT 14U /**< 32 Kilobytes */
+#define PROT_SIZE_64KB_BIT_SHIFT 15U /**< 64 Kilobytes */
+#define PROT_SIZE_128KB_BIT_SHIFT 16U /**< 128 Kilobytes */
+#define PROT_SIZE_256KB_BIT_SHIFT 17U /**< 256 Kilobytes */
+#define PROT_SIZE_512KB_BIT_SHIFT 18U /**< 512 Kilobytes */
+
+#define PROT_SIZE_1MB_BIT_SHIFT 19U /**< 1 Megabyte */
+#define PROT_SIZE_2MB_BIT_SHIFT 20U /**< 2 Megabytes */
+#define PROT_SIZE_4MB_BIT_SHIFT 21U /**< 4 Megabytes */
+#define PROT_SIZE_8MB_BIT_SHIFT 22U /**< 8 Megabytes */
+#define PROT_SIZE_16MB_BIT_SHIFT 23U /**< 16 Megabytes */
+#define PROT_SIZE_32MB_BIT_SHIFT 24U /**< 32 Megabytes */
+#define PROT_SIZE_64MB_BIT_SHIFT 25U /**< 64 Megabytes */
+#define PROT_SIZE_128MB_BIT_SHIFT 26U /**< 128 Megabytes */
+#define PROT_SIZE_256MB_BIT_SHIFT 27U /**< 256 Megabytes */
+#define PROT_SIZE_512MB_BIT_SHIFT 28U /**< 512 Megabytes */
+
+#define PROT_SIZE_1GB_BIT_SHIFT 29U /**< 1 Gigabyte */
+#define PROT_SIZE_2GB_BIT_SHIFT 30U /**< 2 Gigabytes */
+#define PROT_SIZE_4GB_BIT_SHIFT 31U /**< 4 Gigabytes */
+
+/**
* Memory region size
*/
typedef enum
{
- CY_PROT_SIZE_4B = 1U, /**< 4 bytes */
- CY_PROT_SIZE_8B = 2U, /**< 8 bytes */
- CY_PROT_SIZE_16B = 3U, /**< 16 bytes */
- CY_PROT_SIZE_32B = 4U, /**< 32 bytes */
- CY_PROT_SIZE_64B = 5U, /**< 64 bytes */
- CY_PROT_SIZE_128B = 6U, /**< 128 bytes */
+ CY_PROT_SIZE_4B = PROT_SIZE_4B_BIT_SHIFT, /**< 4 bytes */
+ CY_PROT_SIZE_8B = PROT_SIZE_8B_BIT_SHIFT, /**< 8 bytes */
+ CY_PROT_SIZE_16B = PROT_SIZE_16B_BIT_SHIFT, /**< 16 bytes */
+ CY_PROT_SIZE_32B = PROT_SIZE_32B_BIT_SHIFT, /**< 32 bytes */
+ CY_PROT_SIZE_64B = PROT_SIZE_64B_BIT_SHIFT, /**< 64 bytes */
+ CY_PROT_SIZE_128B = PROT_SIZE_128B_BIT_SHIFT, /**< 128 bytes */
- CY_PROT_SIZE_256B = 7U, /**< 256 bytes */
- CY_PROT_SIZE_512B = 8U, /**< 512 bytes */
- CY_PROT_SIZE_1KB = 9U, /**< 1 Kilobyte */
- CY_PROT_SIZE_2KB = 10U, /**< 2 Kilobytes */
- CY_PROT_SIZE_4KB = 11U, /**< 4 Kilobytes */
- CY_PROT_SIZE_8KB = 12U, /**< 8 Kilobytes */
- CY_PROT_SIZE_16KB = 13U, /**< 16 Kilobytes */
- CY_PROT_SIZE_32KB = 14U, /**< 32 Kilobytes */
- CY_PROT_SIZE_64KB = 15U, /**< 64 Kilobytes */
- CY_PROT_SIZE_128KB = 16U, /**< 128 Kilobytes */
- CY_PROT_SIZE_256KB = 17U, /**< 256 Kilobytes */
- CY_PROT_SIZE_512KB = 18U, /**< 512 Kilobytes */
- CY_PROT_SIZE_1MB = 19U, /**< 1 Megabyte */
- CY_PROT_SIZE_2MB = 20U, /**< 2 Megabytes */
- CY_PROT_SIZE_4MB = 21U, /**< 4 Megabytes */
- CY_PROT_SIZE_8MB = 22U, /**< 8 Megabytes */
- CY_PROT_SIZE_16MB = 23U, /**< 16 Megabytes */
- CY_PROT_SIZE_32MB = 24U, /**< 32 Megabytes */
- CY_PROT_SIZE_64MB = 25U, /**< 64 Megabytes */
- CY_PROT_SIZE_128MB = 26U, /**< 128 Megabytes */
- CY_PROT_SIZE_256MB = 27U, /**< 256 Megabytes */
- CY_PROT_SIZE_512MB = 28U, /**< 512 Megabytes */
- CY_PROT_SIZE_1GB = 29U, /**< 1 Gigabyte */
- CY_PROT_SIZE_2GB = 30U, /**< 2 Gigabytes */
- CY_PROT_SIZE_4GB = 31U /**< 4 Gigabytes */
+ CY_PROT_SIZE_256B = PROT_SIZE_256B_BIT_SHIFT, /**< 256 bytes */
+ CY_PROT_SIZE_512B = PROT_SIZE_512B_BIT_SHIFT, /**< 512 bytes */
+ CY_PROT_SIZE_1KB = PROT_SIZE_1KB_BIT_SHIFT, /**< 1 Kilobyte */
+ CY_PROT_SIZE_2KB = PROT_SIZE_2KB_BIT_SHIFT, /**< 2 Kilobytes */
+ CY_PROT_SIZE_4KB = PROT_SIZE_4KB_BIT_SHIFT, /**< 4 Kilobytes */
+ CY_PROT_SIZE_8KB = PROT_SIZE_8KB_BIT_SHIFT, /**< 8 Kilobytes */
+ CY_PROT_SIZE_16KB = PROT_SIZE_16KB_BIT_SHIFT, /**< 16 Kilobytes */
+ CY_PROT_SIZE_32KB = PROT_SIZE_32KB_BIT_SHIFT, /**< 32 Kilobytes */
+ CY_PROT_SIZE_64KB = PROT_SIZE_64KB_BIT_SHIFT, /**< 64 Kilobytes */
+ CY_PROT_SIZE_128KB = PROT_SIZE_128KB_BIT_SHIFT, /**< 128 Kilobytes */
+ CY_PROT_SIZE_256KB = PROT_SIZE_256KB_BIT_SHIFT, /**< 256 Kilobytes */
+ CY_PROT_SIZE_512KB = PROT_SIZE_512KB_BIT_SHIFT, /**< 512 Kilobytes */
+ CY_PROT_SIZE_1MB = PROT_SIZE_1MB_BIT_SHIFT, /**< 1 Megabyte */
+ CY_PROT_SIZE_2MB = PROT_SIZE_2MB_BIT_SHIFT, /**< 2 Megabytes */
+ CY_PROT_SIZE_4MB = PROT_SIZE_4MB_BIT_SHIFT, /**< 4 Megabytes */
+ CY_PROT_SIZE_8MB = PROT_SIZE_8MB_BIT_SHIFT, /**< 8 Megabytes */
+ CY_PROT_SIZE_16MB = PROT_SIZE_16MB_BIT_SHIFT, /**< 16 Megabytes */
+ CY_PROT_SIZE_32MB = PROT_SIZE_32MB_BIT_SHIFT, /**< 32 Megabytes */
+ CY_PROT_SIZE_64MB = PROT_SIZE_64MB_BIT_SHIFT, /**< 64 Megabytes */
+ CY_PROT_SIZE_128MB = PROT_SIZE_128MB_BIT_SHIFT, /**< 128 Megabytes */
+ CY_PROT_SIZE_256MB = PROT_SIZE_256MB_BIT_SHIFT, /**< 256 Megabytes */
+ CY_PROT_SIZE_512MB = PROT_SIZE_512MB_BIT_SHIFT, /**< 512 Megabytes */
+ CY_PROT_SIZE_1GB = PROT_SIZE_1GB_BIT_SHIFT, /**< 1 Gigabyte */
+ CY_PROT_SIZE_2GB = PROT_SIZE_2GB_BIT_SHIFT, /**< 2 Gigabytes */
+ CY_PROT_SIZE_4GB = PROT_SIZE_4GB_BIT_SHIFT /**< 4 Gigabytes */
}cy_en_prot_size_t;
/**
diff --git a/platform/ext/target/cypress/psoc64/Native_Driver/include/cy_syslib.h b/platform/ext/target/cypress/psoc64/Native_Driver/include/cy_syslib.h
index b568337..36f93dd 100644
--- a/platform/ext/target/cypress/psoc64/Native_Driver/include/cy_syslib.h
+++ b/platform/ext/target/cypress/psoc64/Native_Driver/include/cy_syslib.h
@@ -510,18 +510,18 @@
#define CY_NOINLINE __attribute__ ((noinline))
/* Specifies the minimum alignment (in bytes) for variables of the specified type. */
#define CY_ALIGN(align) __ALIGNED(align)
- #define CY_RAMFUNC_BEGIN __attribute__ ((section(".cy_ramfunc")))
+ #define CY_RAMFUNC_BEGIN __attribute__ ((section(".ramfunc")))
#define CY_RAMFUNC_END
#elif defined (__GNUC__)
#if defined (__clang__)
#define CY_NOINIT __attribute__ ((section("__DATA, __noinit")))
#define CY_SECTION(name) __attribute__ ((section("__DATA, "name)))
- #define CY_RAMFUNC_BEGIN __attribute__ ((section("__DATA, .cy_ramfunc")))
+ #define CY_RAMFUNC_BEGIN __attribute__ ((section("__DATA, .ramfunc")))
#define CY_RAMFUNC_END
#else
#define CY_NOINIT __attribute__ ((section(".noinit")))
#define CY_SECTION(name) __attribute__ ((section(name)))
- #define CY_RAMFUNC_BEGIN __attribute__ ((section(".cy_ramfunc")))
+ #define CY_RAMFUNC_BEGIN __attribute__ ((section(".ramfunc")))
#define CY_RAMFUNC_END
#endif
diff --git a/platform/ext/target/cypress/psoc64/Native_Driver/include/cy_wdt.h b/platform/ext/target/cypress/psoc64/Native_Driver/include/cy_wdt.h
index 8bba1d0..07e29b1 100644
--- a/platform/ext/target/cypress/psoc64/Native_Driver/include/cy_wdt.h
+++ b/platform/ext/target/cypress/psoc64/Native_Driver/include/cy_wdt.h
@@ -320,6 +320,7 @@
void Cy_WDT_Init(void);
__STATIC_INLINE void Cy_WDT_Enable(void);
__STATIC_INLINE void Cy_WDT_Disable(void);
+__STATIC_INLINE bool Cy_WDT_IsEnabled(void);
void Cy_WDT_Lock(void);
void Cy_WDT_Unlock(void);
__STATIC_INLINE uint32_t Cy_WDT_GetCount(void);
@@ -365,6 +366,22 @@
/*******************************************************************************
+* Function Name: Cy_WDT_IsEnabled
+****************************************************************************//**
+*
+* Detect if the Watchdog timer is enabled.
+*
+* \return
+* Enabled state: true - enabled, false - disabled
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_WDT_IsEnabled(void)
+{
+ return ((SRSS_WDT_CTL & _VAL2FLD(SRSS_WDT_CTL_WDT_EN, 1U)) ? 1 : 0);
+}
+
+
+/*******************************************************************************
* Function Name: Cy_WDT_GetMatch
****************************************************************************//**
*
diff --git a/platform/ext/target/cypress/psoc64/Native_Driver/source/cy_flash.c b/platform/ext/target/cypress/psoc64/Native_Driver/source/cy_flash.c
index 4c7b385..e1a44a3 100644
--- a/platform/ext/target/cypress/psoc64/Native_Driver/source/cy_flash.c
+++ b/platform/ext/target/cypress/psoc64/Native_Driver/source/cy_flash.c
@@ -30,7 +30,9 @@
#include "cy_ipc_pipe.h"
#include "cy_device.h"
#include "cy_syslib.h"
-
+#ifdef TFM_MULTI_CORE_TOPOLOGY
+ #include "region_defs.h"
+#endif
/***************************************
* Data Structure definitions
@@ -326,10 +328,16 @@
void Cy_Flash_Init(void)
{
#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
- CY_SECTION(".cy_sharedmem")
- CY_ALIGN(4) static cy_stc_flash_notify_t ipcWaitMessageStc;
-
- Cy_Flash_InitExt(&ipcWaitMessageStc);
+ #if defined TFM_MULTI_CORE_TOPOLOGY && CY_CPU_CORTEX_M0P
+ cy_stc_flash_notify_t *ipcWaitMessageStc =
+ (cy_stc_flash_notify_t *)IPC_WAIT_MESSAGE_STC_ADDR;
+
+ Cy_Flash_InitExt(ipcWaitMessageStc);
+ #else
+ CY_ALIGN(4) static cy_stc_flash_notify_t ipcWaitMessageStc;
+
+ Cy_Flash_InitExt(&ipcWaitMessageStc);
+ #endif
#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
}
diff --git a/platform/ext/target/cypress/psoc64/Native_Driver/source/cy_prot.c b/platform/ext/target/cypress/psoc64/Native_Driver/source/cy_prot.c
index 4731fa7..f3c127f 100644
--- a/platform/ext/target/cypress/psoc64/Native_Driver/source/cy_prot.c
+++ b/platform/ext/target/cypress/psoc64/Native_Driver/source/cy_prot.c
@@ -802,7 +802,7 @@
* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version.
*
*******************************************************************************/
-static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t pcMask,
+static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t pcMask,
cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure)
{
cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
@@ -810,50 +810,50 @@
if (!CY_PERI_V1)
{
uint32_t tmpMask = (uint32_t)pcMask << CY_PROT_PCMASK_CHECK;
+ uint32_t tmpMask2;
uint32_t attReg;
- uint32_t regIdx;
+ int32_t regIdx;
uint32_t fldIdx;
-
+
status = CY_PROT_SUCCESS;
-
+
/* Populate the ATT values */
- for(regIdx = 0U; regIdx < CY_PROT_ATT_REGS_MAX; regIdx++)
+ for(regIdx = CY_PROT_ATT_REGS_MAX - 1; regIdx >= 0; regIdx--)
{
- if (0UL == tmpMask)
- {
- break;
- }
-
+ tmpMask2 = (tmpMask >> (CY_PROT_ATT_PC_MAX * regIdx)) & 0xf;
+
/* Get the attributes register value */
attReg = reg[regIdx];
for(fldIdx = 0UL; fldIdx < CY_PROT_ATT_PC_MAX; fldIdx++)
{
- if((tmpMask & CY_PROT_PCMASK_CHECK) == CY_PROT_STRUCT_ENABLE)
+ /* Reset the bitfield for the PCx attributes */
+ attReg &= ~((_VAL2FLD(CY_PROT_ATT_PERI_USER_PERM, CY_PROT_PERM_RW) |
+ _VAL2FLD(CY_PROT_ATT_PERI_PRIV_PERM, CY_PROT_PERM_RW) |
+ _BOOL2FLD(PERI_MS_PPU_PR_V2_MS_ATT0_PC0_NS, true)) <<
+ (PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UR_Pos * fldIdx));
+
+ if((tmpMask2 & CY_PROT_PCMASK_CHECK) == CY_PROT_STRUCT_ENABLE)
{
- /* Reset the bitfield for the PCx attributes */
- attReg &= ~((_VAL2FLD(CY_PROT_ATT_PERI_USER_PERM, CY_PROT_PERM_RW) |
- _VAL2FLD(CY_PROT_ATT_PERI_PRIV_PERM, CY_PROT_PERM_RW) |
- _BOOL2FLD(PERI_MS_PPU_PR_V2_MS_ATT0_PC0_NS, true)) <<
- (PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UR_Pos * fldIdx));
-
/* Set the bitfield for the PCx attributes */
attReg |= (_VAL2FLD(CY_PROT_ATT_PERI_USER_PERM, userPermission) |
_VAL2FLD(CY_PROT_ATT_PERI_PRIV_PERM, privPermission) |
_BOOL2FLD(PERI_MS_PPU_PR_V2_MS_ATT0_PC0_NS, !secure)) <<
(PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UR_Pos * fldIdx);
}
- tmpMask = tmpMask >> CY_PROT_PCMASK_CHECK;
+ tmpMask2 = tmpMask2 >> CY_PROT_PCMASK_CHECK;
}
-
+
/* Update the attributes register */
reg[regIdx] = attReg;
/* Check the result */
- if ((0UL == regIdx) &&
- ((reg[regIdx] & PROT_PERI_PPU_PROG_PC1_PC3_MASK) != (attReg & PROT_PERI_PPU_PROG_PC1_PC3_MASK)))
+ if (0UL == regIdx)
{
- status = CY_PROT_FAILURE;
+ if ((reg[regIdx] & PROT_PERI_PPU_PROG_PC1_PC3_MASK) != (attReg & PROT_PERI_PPU_PROG_PC1_PC3_MASK))
+ {
+ status = CY_PROT_FAILURE;
+ }
}
else if (reg[regIdx] != attReg)
{
diff --git a/platform/ext/target/cypress/psoc64/Native_Driver/source/cy_syspm.c b/platform/ext/target/cypress/psoc64/Native_Driver/source/cy_syspm.c
index 7b1244e..8368020 100644
--- a/platform/ext/target/cypress/psoc64/Native_Driver/source/cy_syspm.c
+++ b/platform/ext/target/cypress/psoc64/Native_Driver/source/cy_syspm.c
@@ -2903,11 +2903,9 @@
* - false - System Deep Sleep was not occurred.
*
*******************************************************************************/
-#if defined (__ICCARM__)
- #pragma diag_suppress=Ta023
- __ramfunc
-#else
- CY_SECTION(".cy_ramfunc") CY_NOINLINE
+CY_RAMFUNC_BEGIN
+#if !defined (__ICCARM__)
+ CY_NOINLINE
#endif
static bool EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor)
{
@@ -3082,9 +3080,7 @@
return retVal;
}
-#if defined (__ICCARM__)
- #pragma diag_default=Ta023
-#endif
+CY_RAMFUNC_END
/*******************************************************************************
diff --git a/platform/ext/target/cypress/psoc64/attest_hal.c b/platform/ext/target/cypress/psoc64/attest_hal.c
new file mode 100644
index 0000000..d4d2407
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/attest_hal.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "platform/include/tfm_attest_hal.h"
+#include <stdint.h>
+
+/* Example verification service URL for initial attestation token */
+static const char verification_service_url[] = "www.trustedfirmware.org";
+
+/* Example profile definition document for initial attestation token */
+static const char attestation_profile_definition[] = "PSA_IOT_PROFILE_1";
+
+enum tfm_security_lifecycle_t tfm_attest_hal_get_security_lifecycle(void)
+{
+ return TFM_SLC_SECURED;
+}
+
+const char *
+tfm_attest_hal_get_verification_service(uint32_t *size)
+{
+ *size = sizeof(verification_service_url) - 1;
+
+ return verification_service_url;
+}
+
+const char *
+tfm_attest_hal_get_profile_definition(uint32_t *size)
+{
+ *size = sizeof(attestation_profile_definition) - 1;
+
+ return attestation_profile_definition;
+}
diff --git a/platform/ext/target/cypress/psoc64/cypress_psoc64_spec.rst b/platform/ext/target/cypress/psoc64/cypress_psoc64_spec.rst
new file mode 100644
index 0000000..dda8dc1
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/cypress_psoc64_spec.rst
@@ -0,0 +1,387 @@
+########################
+Cypress PSoC64 Specifics
+########################
+
+*************
+Prerequisites
+*************
+
+PSoC64 must first be provisioned with SecureBoot firmware and a provisioning packet
+containing policy and secure keys. Please refer to the guide at
+https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide
+
+Please make sure you have all required software installed as explained in the
+:doc:`software requirements </docs/user_guides/tfm_sw_requirement>`.
+
+Please also make sure that all the source code are fetched by following
+:doc:`general building instruction </docs/user_guides/tfm_build_instruction>`.
+
+Install CySecureTools. The exact command to use depends on what version of
+python you are running (which can be determined with "python3 --version").
+
+If you have python 3.7, use
+
+.. code-block:: bash
+
+ pip install cysecuretools==1.0.0
+
+If you have python 3.6.8, use
+
+.. code-block:: bash
+
+ pip3 install --ignore-requires-python git+https://github.com/cypresssemiconductorco/cysecuretools@v1.0.0
+
+For more details please refer to
+`CySecureTools <https://pypi.org/project/cysecuretools/1.0.0/>`_ page.
+
+Install OpenOCD with PSoC6 support. It can be obtained from the Cypress
+Programmer, download it from:
+https://www.cypress.com/products/psoc-programming-solutions
+
+******************************************
+Building Multi-Core TF-M on Cypress PSoC64
+******************************************
+
+Configuring the build
+=====================
+
+The build configuration for TF-M is provided to the build system using command
+line arguments:
+
+.. list-table::
+ :widths: 20 80
+
+ * - -DPROJ_CONFIG=<file>
+ - Specifies the way the application is built.
+
+ | <file> is the absolute path to configurations file
+ named as ``Config<APP_NAME>.cmake``.
+ | e.g. On Linux:
+ ``-DPROJ_CONFIG=`readlink -f ../configs/ConfigRegressionIPC.cmake```
+ | Supported configurations files
+
+ - IPC model without regression test suites in Isolation Level 1
+ ``ConfigCoreIPC.cmake``
+ - IPC model with regression test suites in Isolation Level 1
+ ``ConfigRegressionIPC.cmake``
+ - IPC model with PSA API test suite in Isolation Level 1
+ ``ConfigPsaApiTestIPC.cmake``
+ - IPC model without regression test suites in Isolation Level 2
+ ``ConfigCoreIPCTfmLevel2.cmake``
+ - IPC model with regression test suites in Isolation Level 2
+ ``ConfigRegressionIPCTfmLevel2.cmake``
+ - IPC model with PSA API test suite in Isolation Level 2
+ ``ConfigPsaApiTestIPCTfmLevel2.cmake``
+
+ * - -DTARGET_PLATFORM=psoc64
+ - Specifies target platform name ``psoc64``
+
+ * - -DCOMPILER=<compiler name>
+ - Specifies the compiler toolchain
+ The possible values are:
+
+ - ``ARMCLANG``
+ - ``GNUARM``
+
+ * - -DCMAKE_BUILD_TYPE=<build type>
+ - Configures debugging support.
+ The possible values are:
+
+ - ``Debug``
+ - ``Release``
+
+
+Build Instructions
+==================
+
+The following instructions build multi-core TF-M without regression test suites
+in Isolation Level 1 on Linux.
+Both the compiler and the debugging type can be changed to other configurations
+listed above.
+
+.. code-block:: bash
+
+ cd <TF-M base folder>
+ cd <trusted-firmware-m folder>
+
+ mkdir <build folder>
+ pushd <build folder>
+ cmake -G"Unix Makefiles" -DPROJ_CONFIG=`readlink \
+ -f ../configs/ConfigCoreIPC.cmake` \
+ -DTARGET_PLATFORM=psoc64 \
+ -DCOMPILER=ARMCLANG \
+ -DCMAKE_BUILD_TYPE=Release \
+ ../
+ popd
+ cmake --build <build folder> -- -j VERBOSE=1
+
+The following instructions build multi-core TF-M with regression test suites
+in Isolation Level 1 on Linux.
+Both the compiler and the debugging type can be changed to other configurations
+listed above.
+
+.. code-block:: bash
+
+ cd <TF-M base folder>
+ cd <trusted-firmware-m folder>
+
+ mkdir <build folder>
+ pushd <build folder>
+ cmake -G"Unix Makefiles" -DPROJ_CONFIG=`readlink \
+ -f ../configs/ConfigRegressionIPC.cmake` \
+ -DTARGET_PLATFORM=psoc64 \
+ -DCOMPILER=ARMCLANG \
+ -DCMAKE_BUILD_TYPE=Release ../
+ popd
+ cmake --build <build folder> -- -j VERBOSE=1
+
+The following instructions build multi-core TF-M with PSA API test suite for
+the attestation service in Isolation Level 1 on Linux.
+Both the compiler and the debugging type can be changed to other configurations
+listed above.
+
+.. list-table::
+ :widths: 20 80
+
+ * - -DPSA_API_TEST_BUILD_PATH=<path> (optional)
+ - Specifies the path to the PSA API build directory
+
+ - ``${TFM_ROOT_DIR}/../psa-arch-tests/api-tests/BUILD`` (default)
+
+ * - -D<PSA_API_TEST_xxx>=1 (choose exactly one)
+ - Specifies the service to support
+ The possible values are:
+
+ - ``PSA_API_TEST_ATTESTATION``
+ - ``PSA_API_TEST_CRYPTO``
+ - ``PSA_API_TEST_SECURE_STORAGE``
+ - ``PSA_API_TEST_INTERNAL_TRUSTED_STORAGE``
+
+.. code-block:: bash
+
+ cd <TF-M base folder>
+ cd <trusted-firmware-m folder>
+
+ mkdir <build folder>
+ pushd <build folder>
+ cmake ../ \
+ -G"Unix Makefiles" \
+ -DPROJ_CONFIG=`readlink -f ../configs/ConfigPsaApiTestIPC.cmake` \
+ -DPSA_API_TEST_BUILD_PATH=../psa-arch-tests/api-tests/BUILD_ATT.GNUARM
+ -DPSA_API_TEST_ATTESTATION=1 \
+ -DTARGET_PLATFORM=psoc64 \
+ -DCOMPILER=ARMCLANG \
+ -DCMAKE_BUILD_TYPE=Release
+ popd
+ cmake --build <build folder> -- -j VERBOSE=1
+
+The following instructions build multi-core TF-M without regression test suites
+in Isolation Level 2 on Linux.
+Both the compiler and the debugging type can be changed to other configurations
+listed above.
+
+.. code-block:: bash
+
+ cd <TF-M base folder>
+ cd <trusted-firmware-m folder>
+
+ mkdir <build folder>
+ pushd <build folder>
+ cmake -G"Unix Makefiles" \
+ -DPROJ_CONFIG=`readlink -f ../configs/ConfigCoreIPCTfmLevel2.cmake` \
+ -DTARGET_PLATFORM=psoc64 \
+ -DCOMPILER=ARMCLANG \
+ -DCMAKE_BUILD_TYPE=Release \
+ ../
+ popd
+ cmake --build <build folder> -- -j VERBOSE=1
+
+The following instructions build multi-core TF-M with regression test suites
+in Isolation Level 2 on Linux.
+Both the compiler and the debugging type can be changed to other configurations
+listed above.
+
+.. code-block:: bash
+
+ cd <TF-M base folder>
+ cd <trusted-firmware-m folder>
+
+ mkdir <build folder>
+ pushd <build folder>
+ cmake -G"Unix Makefiles" \
+ -DPROJ_CONFIG=`readlink \
+ -f ../configs/ConfigRegressionIPCTfmLevel2.cmake` \
+ -DTARGET_PLATFORM=psoc64 \
+ -DCOMPILER=ARMCLANG \
+ -DCMAKE_BUILD_TYPE=Release \
+ ../
+ popd
+ cmake --build <build folder> -- -j VERBOSE=1
+
+The following instructions build multi-core TF-M with PSA API test suite for
+the protected storage service in Isolation Level 2 on Linux.
+Both the compiler and the debugging type can be changed to other configurations
+listed above.
+
+.. list-table::
+ :widths: 20 80
+
+ * - -DPSA_API_TEST_BUILD_PATH=<path> (optional)
+ - Specifies the path to the PSA API build directory
+
+ - ``${TFM_ROOT_DIR}/../psa-arch-tests/api-tests/BUILD`` (default)
+
+ * - -D<PSA_API_TEST_xxx>=1 (choose exactly one)
+ - Specifies the service to support
+ The possible values are:
+
+ - ``PSA_API_TEST_ATTESTATION``
+ - ``PSA_API_TEST_CRYPTO``
+ - ``PSA_API_TEST_SECURE_STORAGE``
+ - ``PSA_API_TEST_INTERNAL_TRUSTED_STORAGE``
+
+.. code-block:: bash
+
+ cd <TF-M base folder>
+ cd <trusted-firmware-m folder>
+
+ mkdir <build folder>
+ pushd <build folder>
+ cmake ../ \
+ -G"Unix Makefiles" \
+ -DPROJ_CONFIG=`readlink -f ../configs/ConfigPsaApiTestIPCTfmLevel2.cmake` \
+ -DPSA_API_TEST_BUILD_PATH=../psa-arch-tests/api-tests/BUILD_PS.GNUARM
+ -DPSA_API_TEST_SECURE_STORAGE=1 \
+ -DTARGET_PLATFORM=psoc64 \
+ -DCOMPILER=ARMCLANG \
+ -DCMAKE_BUILD_TYPE=Release
+ popd
+ cmake --build <build folder> -- -j VERBOSE=1
+
+**********************
+Signing the images
+**********************
+
+First, convert tfm_s.axf and tfm_ns.axf images to hex format. This also places
+resulting files one folder level up.
+
+GNUARM build:
+
+.. code-block:: bash
+
+ arm-none-eabi-objcopy -O ihex <build folder>/secure_fw/tfm_s.axf <build folder>/tfm_s.hex
+ arm-none-eabi-objcopy -O ihex <build folder>/app/tfm_ns.axf <build folder>/tfm_ns.hex
+
+ARMCLANG build:
+
+.. code-block:: bash
+
+ fromelf --i32 --output=<build folder>/tfm_s.hex <build folder>/secure_fw/tfm_s.axf
+ fromelf --i32 --output=<build folder>/tfm_ns.hex <build folder>/app/tfm_ns.axf
+
+Copy secure keys used in the board provisioning process to
+platform/ext/target/cypress/psoc64/security/keys:
+
+-MCUBOOT_CM0P_KEY_PRIV.pem - private OEM key for signing CM0P image
+-USERAPP_CM4_KEY_PRIV.pem - private OEM key for signing CM4 image
+
+Note: provisioned board in SECURE claimed state is required, otherwise refer to
+Cypress documentation for details on the provisioning process.
+
+Sign the images (sign.py overwrites unsigned files with signed ones):
+
+.. code-block:: bash
+
+ ./platform/ext/target/cypress/psoc64/security/sign.py \
+ -s <build folder>/tfm_s.hex \
+ -n <build folder>/tfm_ns.hex \
+ -p platform/ext/target/cypress/psoc64/security/policy_dual_stage_CM0p_CM4_debug_2M.json
+
+Note: each image can be signed individually, for example:
+
+.. code-block:: bash
+
+ ./platform/ext/target/cypress/psoc64/security/sign.py \
+ -n <build folder>/tfm_ns.hex \
+ -p platform/ext/target/cypress/psoc64/security/policy_dual_stage_CM0p_CM4_debug_2M.json
+
+.. code-block:: bash
+
+ ./platform/ext/target/cypress/psoc64/security/sign.py \
+ -s <build folder>/tfm_s.hex \
+ -p platform/ext/target/cypress/psoc64/security/policy_dual_stage_CM0p_CM4_debug_2M.json
+
+**********************
+Programming the Device
+**********************
+
+After building and signing, the TFM images must be programmed into flash
+memory on the PSoC64 device. There are two methods to program it.
+
+DAPLink mode
+============
+
+Using KitProg3 mode button, switch it to DAPLink mode.
+Mode LED should start blinking rapidly and depending on the host computer
+settings DAPLINK will be mounted as a media storage device.
+Otherwise, mount it manually.
+
+Copy tfm hex files one by one to the DAPLINK device:
+
+.. code-block:: bash
+
+ cp <build folder>/tfm_ns.hex <mount point>/DAPLINK/; sync
+ cp <build folder>/tfm_s.hex <mount point>/DAPLINK/; sync
+
+OpenOCD v.2.2
+=============
+
+Using KitProg3 mode button, switch to KitProg3 CMSIS-DAP BULK mode.
+Status LED should be ON and not blinking.
+To program the signed tfm_s image to the device with openocd (assuming
+OPENOCD_PATH is pointing at the openocd installation directory) run the
+following commands:
+
+.. code-block:: bash
+
+ OPENOCD_PATH=<cyprogrammer dir>/openocd
+ BUILD_DIR=<build folder>
+
+ ${OPENOCD_PATH}/bin/openocd \
+ -s ${OPENOCD_PATH}/scripts \
+ -f interface/kitprog3.cfg \
+ -c "set ENABLE_ACQUIRE 0" \
+ -f target/psoc6_2m_secure.cfg \
+ -c "init; reset init; flash write_image erase ${BUILD_DIR}/tfm_s.hex" \
+ -c "resume; reset; exit"
+
+ ${OPENOCD_PATH}/bin/openocd \
+ -s ${OPENOCD_PATH}/scripts \
+ -f interface/kitprog3.cfg \
+ -c "set ENABLE_ACQUIRE 0" \
+ -f target/psoc6_2m_secure.cfg \
+ -c "init; reset init; flash write_image erase ${BUILD_DIR}/tfm_ns.hex" \
+ -c "resume; reset; exit"
+
+Optionally, erase SST partition:
+
+.. code-block:: bash
+
+ ${OPENOCD_PATH}/bin/openocd \
+ -s ${OPENOCD_PATH}/scripts \
+ -f interface/kitprog3.cfg \
+ -f target/psoc6_2m_secure.cfg \
+ -c "init; reset init" \
+ -c "flash erase_address 0x101c0000 0x10000" \
+ -c "shutdown"
+
+Note that the ``0x101C0000`` in the command above must match the SST start
+address of the secure primary image specified in the file:
+
+ platform/ext/target/cypress/psoc64/partition/flash_layout.h
+
+so be sure to change it if you change that file.
+
+*Copyright (c) 2017-2019, Arm Limited. All rights reserved.*
+
+*Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.*
diff --git a/platform/ext/target/cypress/psoc64/driver_ppu.c b/platform/ext/target/cypress/psoc64/driver_ppu.c
new file mode 100644
index 0000000..96ff47f
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/driver_ppu.c
@@ -0,0 +1,1098 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdio.h>
+
+#include "driver_ppu.h"
+#include "pc_config.h"
+#include "ppu_config.h"
+#include "RTE_Device.h"
+
+#include "cy_device_headers.h"
+#include "cy_prot.h"
+
+struct ms_ppu_config {
+ uint16_t pcMask;
+ cy_en_prot_perm_t user;
+ cy_en_prot_perm_t priv;
+ bool secure;
+};
+
+struct ppu_resources {
+ enum ppu_type ppu_type;
+ union ppu {
+ PERI_MS_PPU_PR_Type *ms_ppu_pr;
+ PERI_MS_PPU_FX_Type *ms_ppu_fx;
+ PERI_PPU_PR_Type *ppu_pr;
+ PERI_PPU_GR_Type *ppu_gr;
+ PERI_GR_PPU_SL_Type *gr_ppu_sl;
+ PERI_GR_PPU_RG_Type *gr_ppu_rg;
+ } ppu;
+ union master_config {
+ struct ms_ppu_config ms_ppu;
+ cy_stc_ppu_prog_cfg_t ppu_pr;
+ cy_stc_ppu_gr_cfg_t ppu_gr;
+ cy_stc_ppu_sl_cfg_t gr_ppu_sl;
+ cy_stc_ppu_rg_cfg_t gr_ppu_rg;
+ } master_cfg;
+ union slave_config {
+ struct ms_ppu_config ms_ppu;
+ cy_stc_ppu_prog_cfg_t ppu_pr;
+ cy_stc_ppu_gr_cfg_t ppu_gr;
+ cy_stc_ppu_sl_cfg_t gr_ppu_sl;
+ cy_stc_ppu_rg_cfg_t gr_ppu_rg;
+ } slave_cfg;
+ /* These are only applicable when ppu_type is MS_PPU_PR */
+ uint32_t slave_address;
+ cy_en_prot_size_t slave_region_size;
+};
+
+/* Affect all 8 subregions */
+#define ALL_ENABLED 0
+
+/* Shared Driver wrapper functions */
+cy_en_prot_status_t PPU_Configure(const PPU_Resources *ppu_dev)
+{
+ cy_en_prot_status_t ret;
+
+ switch(ppu_dev->ppu_type) {
+/* This block is only needed if there are MS_PPU_PR PPUs on the board */
+#if defined(PERI_MS_PPU_PR0)
+ case MS_PPU_PR:
+ ret = Cy_Prot_ConfigPpuProgSlaveAddr(ppu_dev->ppu.ms_ppu_pr,
+ ppu_dev->slave_address,
+ ppu_dev->slave_region_size);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_ConfigPpuProgSlaveAtt(ppu_dev->ppu.ms_ppu_pr,
+ ppu_dev->slave_cfg.ms_ppu.pcMask,
+ ppu_dev->slave_cfg.ms_ppu.user,
+ ppu_dev->slave_cfg.ms_ppu.priv,
+ ppu_dev->slave_cfg.ms_ppu.secure);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuProgSlaveRegion(ppu_dev->ppu.ms_ppu_pr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_ConfigPpuProgMasterAtt(ppu_dev->ppu.ms_ppu_pr,
+ ppu_dev->master_cfg.ms_ppu.pcMask,
+ ppu_dev->master_cfg.ms_ppu.user,
+ ppu_dev->master_cfg.ms_ppu.priv,
+ ppu_dev->master_cfg.ms_ppu.secure);
+ break;
+#endif
+
+/* This block is only needed if there are MS_PPU_FX PPUs on the board */
+#if defined(PERI_MS_PPU_FX_PERI_MAIN)
+ case MS_PPU_FX:
+ ret = Cy_Prot_ConfigPpuFixedSlaveAtt(ppu_dev->ppu.ms_ppu_fx,
+ ppu_dev->slave_cfg.ms_ppu.pcMask,
+ ppu_dev->slave_cfg.ms_ppu.user,
+ ppu_dev->slave_cfg.ms_ppu.priv,
+ ppu_dev->slave_cfg.ms_ppu.secure);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_ConfigPpuFixedMasterAtt(ppu_dev->ppu.ms_ppu_fx,
+ ppu_dev->master_cfg.ms_ppu.pcMask,
+ ppu_dev->master_cfg.ms_ppu.user,
+ ppu_dev->master_cfg.ms_ppu.priv,
+ ppu_dev->master_cfg.ms_ppu.secure);
+ break;
+#endif
+
+/* This block is only needed if there are PPU_PR PPUs on the board */
+#if defined(PERI_PPU_PR0)
+ case PPU_PR:
+ ret = Cy_Prot_ConfigPpuProgSlaveStruct(ppu_dev->ppu.ppu_pr,
+ &ppu_dev->slave_cfg.ppu_pr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuProgSlaveStruct(ppu_dev->ppu.ppu_pr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_ConfigPpuProgMasterStruct(ppu_dev->ppu.ppu_pr,
+ &ppu_dev->master_cfg.ppu_pr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuProgMasterStruct(ppu_dev->ppu.ppu_pr);
+ break;
+#endif
+
+/* This block is only needed if there are PPU_GR PPUs on the board */
+#if defined(PERI_PPU_GR0)
+ case PPU_GR:
+ ret = Cy_Prot_ConfigPpuFixedGrSlaveStruct(ppu_dev->ppu.ppu_gr,
+ &ppu_dev->slave_cfg.ppu_gr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuFixedGrSlaveStruct(ppu_dev->ppu.ppu_gr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_ConfigPpuFixedGrMasterStruct(ppu_dev->ppu.ppu_gr,
+ &ppu_dev->master_cfg.ppu_gr);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuFixedGrMasterStruct(ppu_dev->ppu.ppu_gr);
+ break;
+#endif
+
+/* This block is only needed if there are GR_PPU_SL PPUs on the board */
+#if defined(PERI_GR_PPU_SL_CRYPTO)
+ case GR_PPU_SL:
+ ret = Cy_Prot_ConfigPpuFixedSlSlaveStruct(ppu_dev->ppu.gr_ppu_sl,
+ &ppu_dev->slave_cfg.gr_ppu_sl);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuFixedSlSlaveStruct(ppu_dev->ppu.gr_ppu_sl);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_ConfigPpuFixedSlMasterStruct(ppu_dev->ppu.gr_ppu_sl,
+ &ppu_dev->master_cfg.gr_ppu_sl);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuFixedSlMasterStruct(ppu_dev->ppu.gr_ppu_sl);
+ break;
+#endif
+
+/* This block is only needed if there are GR_PPU_RG PPUs on the board */
+#if defined(PERI_GR_PPU_RG_IPC_STRUCT0)
+ case GR_PPU_RG:
+ ret = Cy_Prot_ConfigPpuFixedRgSlaveStruct(ppu_dev->ppu.gr_ppu_rg,
+ &ppu_dev->slave_cfg.gr_ppu_rg);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuFixedRgSlaveStruct(ppu_dev->ppu.gr_ppu_rg);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_ConfigPpuFixedRgMasterStruct(ppu_dev->ppu.gr_ppu_rg,
+ &ppu_dev->master_cfg.gr_ppu_rg);
+ if (ret != CY_PROT_SUCCESS)
+ return ret;
+ ret = Cy_Prot_EnablePpuFixedRgMasterStruct(ppu_dev->ppu.gr_ppu_rg);
+ break;
+#endif
+
+ default:
+ printf("Unexpected peripheral type %d\n", ppu_dev->ppu_type);
+ return CY_PROT_BAD_PARAM;
+ }
+
+ return ret;
+}
+
+#define DEFINE_MS_PPU_PR(N) const PPU_Resources N##_PPU_Resources = { \
+ .ppu_type = MS_PPU_PR, \
+ .ppu = {.ms_ppu_pr = PERI_MS_PPU_##N}, \
+ .master_cfg.ms_ppu = PPU_##N##_MASTER_CONFIG, \
+ .slave_cfg.ms_ppu = PPU_##N##_SLAVE_CONFIG, \
+ .slave_address = PPU_##N##_SLAVE_ADDRESS, \
+ .slave_region_size = PPU_##N##_SLAVE_REGION_SIZE, \
+};
+
+#define DEFINE_MS_PPU_FX(N) const PPU_Resources N##_PPU_Resources = { \
+ .ppu_type = MS_PPU_FX, \
+ .ppu = {.ms_ppu_fx = PERI_MS_PPU_FX_##N}, \
+ .master_cfg.ms_ppu = PPU_##N##_MASTER_CONFIG, \
+ .slave_cfg.ms_ppu = PPU_##N##_SLAVE_CONFIG, \
+};
+
+#define DEFINE_PPU_PR(N) const PPU_Resources N##_PPU_Resources = { \
+ .ppu_type = PPU_PR, \
+ .ppu = {.ppu_pr = PERI_PPU_##N}, \
+ .master_cfg.ppu_pr = PPU_##N##_MASTER_CONFIG, \
+ .slave_cfg.ppu_pr = PPU_##N##_SLAVE_CONFIG, \
+};
+
+#define DEFINE_PPU_GR(N) const PPU_Resources N##_PPU_Resources = { \
+ .ppu_type = PPU_GR, \
+ .ppu = {.ppu_gr = PERI_PPU_##N}, \
+ .master_cfg.ppu_gr = PPU_##N##_MASTER_CONFIG, \
+ .slave_cfg.ppu_gr = PPU_##N##_SLAVE_CONFIG, \
+};
+
+#define DEFINE_GR_PPU_SL(N) const PPU_Resources N##_PPU_Resources = { \
+ .ppu_type = GR_PPU_SL, \
+ .ppu = {.gr_ppu_sl = PERI_GR_PPU_##N}, \
+ .master_cfg.gr_ppu_sl = PPU_##N##_MASTER_CONFIG, \
+ .slave_cfg.gr_ppu_sl = PPU_##N##_SLAVE_CONFIG, \
+};
+
+#define DEFINE_GR_PPU_RG(N) const PPU_Resources N##_PPU_Resources = { \
+ .ppu_type = GR_PPU_RG, \
+ .ppu = {.gr_ppu_rg = PERI_GR_PPU_##N}, \
+ .master_cfg.gr_ppu_rg = PPU_##N##_MASTER_CONFIG, \
+ .slave_cfg.gr_ppu_rg = PPU_##N##_SLAVE_CONFIG, \
+};
+
+#if (RTE_MS_PPU_PR7)
+DEFINE_MS_PPU_PR(PR7)
+#endif
+
+#if (RTE_MS_PPU_PERI_MAIN)
+DEFINE_MS_PPU_FX(PERI_MAIN)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR0_GROUP)
+DEFINE_MS_PPU_FX(PERI_GR0_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR1_GROUP)
+DEFINE_MS_PPU_FX(PERI_GR1_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR2_GROUP)
+DEFINE_MS_PPU_FX(PERI_GR2_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR3_GROUP)
+DEFINE_MS_PPU_FX(PERI_GR3_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR4_GROUP)
+DEFINE_MS_PPU_FX(PERI_GR4_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR6_GROUP)
+DEFINE_MS_PPU_FX(PERI_GR6_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR9_GROUP)
+DEFINE_MS_PPU_FX(PERI_GR9_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR10_GROUP)
+DEFINE_MS_PPU_FX(PERI_GR10_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_TR)
+DEFINE_MS_PPU_FX(PERI_TR)
+#endif
+
+#if (RTE_MS_PPU_CRYPTO_MAIN)
+DEFINE_MS_PPU_FX(CRYPTO_MAIN)
+#endif
+
+#if (RTE_MS_PPU_CRYPTO_CRYPTO)
+DEFINE_MS_PPU_FX(CRYPTO_CRYPTO)
+#endif
+
+#if (RTE_MS_PPU_CRYPTO_BOOT)
+DEFINE_MS_PPU_FX(CRYPTO_BOOT)
+#endif
+
+#if (RTE_MS_PPU_CRYPTO_KEY0)
+DEFINE_MS_PPU_FX(CRYPTO_KEY0)
+#endif
+
+#if (RTE_MS_PPU_CRYPTO_KEY1)
+DEFINE_MS_PPU_FX(CRYPTO_KEY1)
+#endif
+
+#if (RTE_MS_PPU_CRYPTO_BUF)
+DEFINE_MS_PPU_FX(CRYPTO_BUF)
+#endif
+
+#if (RTE_MS_PPU_CPUSS_CM4)
+DEFINE_MS_PPU_FX(CPUSS_CM4)
+#endif
+
+#if (RTE_MS_PPU_CPUSS_CM0)
+DEFINE_MS_PPU_FX(CPUSS_CM0)
+#endif
+
+#if (RTE_MS_PPU_CPUSS_CM0_INT)
+DEFINE_MS_PPU_FX(CPUSS_CM0_INT)
+#endif
+
+#if (RTE_MS_PPU_CPUSS_CM4_INT)
+DEFINE_MS_PPU_FX(CPUSS_CM4_INT)
+#endif
+
+#if (RTE_MS_PPU_FAULT_STRUCT0_MAIN)
+DEFINE_MS_PPU_FX(FAULT_STRUCT0_MAIN)
+#endif
+
+#if (RTE_MS_PPU_FAULT_STRUCT1_MAIN)
+DEFINE_MS_PPU_FX(FAULT_STRUCT1_MAIN)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT0_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT0_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT1_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT1_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT2_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT2_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT3_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT3_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT4_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT4_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT5_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT5_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT6_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT6_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT7_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT7_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT8_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT8_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT9_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT9_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT10_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT10_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT11_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT11_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT12_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT12_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT13_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT13_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT14_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT14_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT15_IPC)
+DEFINE_MS_PPU_FX(IPC_STRUCT15_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT1_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT1_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT2_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT2_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT3_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT3_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT4_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT4_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT5_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT5_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT6_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT6_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT7_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT7_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT8_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT8_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT9_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT9_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT10_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT10_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT11_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT11_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT12_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT12_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT13_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT13_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT14_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT14_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT15_INTR)
+DEFINE_MS_PPU_FX(IPC_INTR_STRUCT15_INTR)
+#endif
+
+#if (RTE_MS_PPU_PROT_SMPU_MAIN)
+DEFINE_MS_PPU_FX(PROT_SMPU_MAIN)
+#endif
+
+#if (RTE_MS_PPU_PROT_MPU0_MAIN)
+DEFINE_MS_PPU_FX(PROT_MPU0_MAIN)
+#endif
+
+#if (RTE_MS_PPU_PROT_MPU5_MAIN)
+DEFINE_MS_PPU_FX(PROT_MPU5_MAIN)
+#endif
+
+#if (RTE_MS_PPU_PROT_MPU6_MAIN)
+DEFINE_MS_PPU_FX(PROT_MPU6_MAIN)
+#endif
+
+#if (RTE_MS_PPU_PROT_MPU14_MAIN)
+DEFINE_MS_PPU_FX(PROT_MPU14_MAIN)
+#endif
+
+#if (RTE_MS_PPU_FLASHC_MAIN)
+DEFINE_MS_PPU_FX(FLASHC_MAIN)
+#endif
+
+#if (RTE_MS_PPU_FLASHC_CMD)
+DEFINE_MS_PPU_FX(FLASHC_CMD)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN1)
+DEFINE_MS_PPU_FX(SRSS_MAIN1)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN2)
+DEFINE_MS_PPU_FX(SRSS_MAIN2)
+#endif
+
+#if (RTE_MS_PPU_WDT)
+DEFINE_MS_PPU_FX(WDT)
+#endif
+
+#if (RTE_MS_PPU_MAIN)
+DEFINE_MS_PPU_FX(MAIN)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN3)
+DEFINE_MS_PPU_FX(SRSS_MAIN3)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN4)
+DEFINE_MS_PPU_FX(SRSS_MAIN4)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN5)
+DEFINE_MS_PPU_FX(SRSS_MAIN5)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN6)
+DEFINE_MS_PPU_FX(SRSS_MAIN6)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN7)
+DEFINE_MS_PPU_FX(SRSS_MAIN7)
+#endif
+
+#if (RTE_MS_PPU_BACKUP_BACKUP)
+DEFINE_MS_PPU_FX(BACKUP_BACKUP)
+#endif
+
+#if (RTE_MS_PPU_DW0_DW)
+DEFINE_MS_PPU_FX(DW0_DW)
+#endif
+
+#if (RTE_MS_PPU_DW1_DW)
+DEFINE_MS_PPU_FX(DW1_DW)
+#endif
+
+#if (RTE_MS_PPU_DW0_DW_CRC)
+DEFINE_MS_PPU_FX(DW0_DW_CRC)
+#endif
+
+#if (RTE_MS_PPU_DW1_DW_CRC)
+DEFINE_MS_PPU_FX(DW1_DW_CRC)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT0_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT0_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT1_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT1_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT2_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT2_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT3_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT3_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT4_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT4_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT5_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT5_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT6_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT6_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT7_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT7_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT8_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT8_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT9_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT9_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT10_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT10_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT11_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT11_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT12_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT12_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT13_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT13_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT14_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT14_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT15_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT15_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT16_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT16_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT17_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT17_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT18_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT18_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT19_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT19_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT20_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT20_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT21_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT21_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT22_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT22_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT23_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT23_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT24_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT24_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT25_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT25_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT26_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT26_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT27_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT27_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT28_CH)
+DEFINE_MS_PPU_FX(DW0_CH_STRUCT28_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT0_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT0_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT1_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT1_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT2_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT2_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT3_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT3_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT4_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT4_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT5_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT5_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT6_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT6_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT7_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT7_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT8_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT8_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT9_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT9_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT10_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT10_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT11_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT11_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT12_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT12_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT13_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT13_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT14_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT14_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT15_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT15_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT16_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT16_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT17_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT17_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT18_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT18_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT19_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT19_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT20_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT20_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT21_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT21_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT22_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT22_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT23_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT23_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT24_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT24_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT25_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT25_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT26_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT26_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT27_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT27_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT28_CH)
+DEFINE_MS_PPU_FX(DW1_CH_STRUCT28_CH)
+#endif
+
+#if (RTE_MS_PPU_DMAC_TOP)
+DEFINE_MS_PPU_FX(DMAC_TOP)
+#endif
+
+#if (RTE_MS_PPU_DMAC_CH0_CH)
+DEFINE_MS_PPU_FX(DMAC_CH0_CH)
+#endif
+
+#if (RTE_MS_PPU_DMAC_CH1_CH)
+DEFINE_MS_PPU_FX(DMAC_CH1_CH)
+#endif
+
+#if (RTE_MS_PPU_DMAC_CH2_CH)
+DEFINE_MS_PPU_FX(DMAC_CH2_CH)
+#endif
+
+#if (RTE_MS_PPU_DMAC_CH3_CH)
+DEFINE_MS_PPU_FX(DMAC_CH3_CH)
+#endif
+
+#if (RTE_MS_PPU_EFUSE_DATA)
+DEFINE_MS_PPU_FX(EFUSE_DATA)
+#endif
+
+#if (RTE_MS_PPU_PROFILE)
+DEFINE_MS_PPU_FX(PROFILE)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT0_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT0_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT1_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT1_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT2_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT2_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT3_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT3_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT4_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT4_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT5_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT5_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT6_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT6_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT7_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT7_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT8_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT8_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT9_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT9_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT10_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT10_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT11_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT11_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT12_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT12_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT13_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT13_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT14_PRT)
+DEFINE_MS_PPU_FX(HSIOM_PRT14_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_AMUX)
+DEFINE_MS_PPU_FX(HSIOM_AMUX)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_MON)
+DEFINE_MS_PPU_FX(HSIOM_MON)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT0_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT0_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT1_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT1_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT2_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT2_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT3_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT3_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT4_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT4_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT5_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT5_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT6_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT6_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT7_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT7_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT8_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT8_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT9_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT9_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT10_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT10_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT11_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT11_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT12_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT12_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT13_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT13_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT14_PRT)
+DEFINE_MS_PPU_FX(GPIO_PRT14_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT0_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT0_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT1_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT1_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT2_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT2_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT3_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT3_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT4_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT4_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT5_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT5_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT6_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT6_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT7_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT7_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT8_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT8_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT9_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT9_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT10_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT10_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT11_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT11_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT12_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT12_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT13_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT13_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT14_CFG)
+DEFINE_MS_PPU_FX(GPIO_PRT14_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_GPIO)
+DEFINE_MS_PPU_FX(GPIO_GPIO)
+#endif
+
+#if (RTE_MS_PPU_SMARTIO_PRT8_PRT)
+DEFINE_MS_PPU_FX(SMARTIO_PRT8_PRT)
+#endif
+
+#if (RTE_MS_PPU_SMARTIO_PRT9_PRT)
+DEFINE_MS_PPU_FX(SMARTIO_PRT9_PRT)
+#endif
+
+#if (RTE_MS_PPU_LPCOMP)
+DEFINE_MS_PPU_FX(LPCOMP)
+#endif
+
+#if (RTE_MS_PPU_CSD0)
+DEFINE_MS_PPU_FX(CSD0)
+#endif
+
+#if (RTE_MS_PPU_TCPWM0)
+DEFINE_MS_PPU_FX(TCPWM0)
+#endif
+
+#if (RTE_MS_PPU_TCPWM1)
+DEFINE_MS_PPU_FX(TCPWM1)
+#endif
+
+#if (RTE_MS_PPU_LCD0)
+DEFINE_MS_PPU_FX(LCD0)
+#endif
+
+#if (RTE_MS_PPU_USBFS0)
+DEFINE_MS_PPU_FX(USBFS0)
+#endif
+
+#if (RTE_MS_PPU_SMIF0)
+DEFINE_MS_PPU_FX(SMIF0)
+#endif
+
+#if (RTE_MS_PPU_SDHC0)
+DEFINE_MS_PPU_FX(SDHC0)
+#endif
+
+#if (RTE_MS_PPU_SDHC1)
+DEFINE_MS_PPU_FX(SDHC1)
+#endif
+
+#if (RTE_MS_PPU_SCB0)
+DEFINE_MS_PPU_FX(SCB0)
+#endif
+
+#if (RTE_MS_PPU_SCB1)
+DEFINE_MS_PPU_FX(SCB1)
+#endif
+
+#if (RTE_MS_PPU_SCB2)
+DEFINE_MS_PPU_FX(SCB2)
+#endif
+
+#if (RTE_MS_PPU_SCB3)
+DEFINE_MS_PPU_FX(SCB3)
+#endif
+
+#if (RTE_MS_PPU_SCB4)
+DEFINE_MS_PPU_FX(SCB4)
+#endif
+
+#if (RTE_MS_PPU_SCB5)
+DEFINE_MS_PPU_FX(SCB5)
+#endif
+
+#if (RTE_MS_PPU_SCB6)
+DEFINE_MS_PPU_FX(SCB6)
+#endif
+
+#if (RTE_MS_PPU_SCB7)
+DEFINE_MS_PPU_FX(SCB7)
+#endif
+
+#if (RTE_MS_PPU_SCB8)
+DEFINE_MS_PPU_FX(SCB8)
+#endif
+
+#if (RTE_MS_PPU_SCB9)
+DEFINE_MS_PPU_FX(SCB9)
+#endif
+
+#if (RTE_MS_PPU_SCB10)
+DEFINE_MS_PPU_FX(SCB10)
+#endif
+
+#if (RTE_MS_PPU_SCB11)
+DEFINE_MS_PPU_FX(SCB11)
+#endif
+
+#if (RTE_MS_PPU_SCB12)
+DEFINE_MS_PPU_FX(SCB12)
+#endif
+
+#if (RTE_MS_PPU_PDM0)
+DEFINE_MS_PPU_FX(PDM0)
+#endif
+
+#if (RTE_MS_PPU_I2S0)
+DEFINE_MS_PPU_FX(I2S0)
+#endif
+
+#if (RTE_MS_PPU_I2S1)
+DEFINE_MS_PPU_FX(I2S1)
+#endif
diff --git a/platform/ext/target/cypress/psoc64/driver_ppu.h b/platform/ext/target/cypress/psoc64/driver_ppu.h
new file mode 100644
index 0000000..518e045
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/driver_ppu.h
@@ -0,0 +1,907 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DRIVER_PPU_H__
+#define __DRIVER_PPU_H__
+
+#include "cy_prot.h"
+#include "RTE_Device.h"
+
+/* PSoC 6 has 6 different kinds of PPU */
+enum ppu_type {
+ MS_PPU_PR,
+ MS_PPU_FX,
+ PPU_PR,
+ PPU_GR,
+ GR_PPU_SL,
+ GR_PPU_RG,
+ NO_PPU
+};
+
+typedef struct ppu_resources PPU_Resources;
+
+/* Shared Driver wrapper functions */
+cy_en_prot_status_t PPU_Configure(const PPU_Resources *ppu_dev);
+
+/* Per-PPU macros */
+#define DECLARE_MS_PPU_PR(N) extern const PPU_Resources N##_PPU_Resources;
+#define DECLARE_MS_PPU_FX(N) extern const PPU_Resources N##_PPU_Resources;
+#define DECLARE_PPU_PR(N) extern const PPU_Resources N##_PPU_Resources;
+#define DECLARE_PPU_GR(N) extern const PPU_Resources N##_PPU_Resources;
+#define DECLARE_GR_PPU_SL(N) extern const PPU_Resources N##_PPU_Resources;
+#define DECLARE_GR_PPU_RG(N) extern const PPU_Resources N##_PPU_Resources;
+
+#if (RTE_MS_PPU_PR7)
+DECLARE_MS_PPU_PR(PR7)
+#endif
+
+#if (RTE_MS_PPU_PERI_MAIN)
+DECLARE_MS_PPU_FX(PERI_MAIN)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR0_GROUP)
+DECLARE_MS_PPU_FX(PERI_GR0_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR1_GROUP)
+DECLARE_MS_PPU_FX(PERI_GR1_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR2_GROUP)
+DECLARE_MS_PPU_FX(PERI_GR2_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR3_GROUP)
+DECLARE_MS_PPU_FX(PERI_GR3_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR4_GROUP)
+DECLARE_MS_PPU_FX(PERI_GR4_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR6_GROUP)
+DECLARE_MS_PPU_FX(PERI_GR6_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR9_GROUP)
+DECLARE_MS_PPU_FX(PERI_GR9_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_GR10_GROUP)
+DECLARE_MS_PPU_FX(PERI_GR10_GROUP)
+#endif
+
+#if (RTE_MS_PPU_PERI_TR)
+DECLARE_MS_PPU_FX(PERI_TR)
+#endif
+
+#if (RTE_MS_PPU_CRYPTO_MAIN)
+DECLARE_MS_PPU_FX(CRYPTO_MAIN)
+#endif
+
+#if (RTE_MS_PPU_CRYPTO_CRYPTO)
+DECLARE_MS_PPU_FX(CRYPTO_CRYPTO)
+#endif
+
+#if (RTE_MS_PPU_CRYPTO_BOOT)
+DECLARE_MS_PPU_FX(CRYPTO_BOOT)
+#endif
+
+#if (RTE_MS_PPU_CRYPTO_KEY0)
+DECLARE_MS_PPU_FX(CRYPTO_KEY0)
+#endif
+
+#if (RTE_MS_PPU_CRYPTO_KEY1)
+DECLARE_MS_PPU_FX(CRYPTO_KEY1)
+#endif
+
+#if (RTE_MS_PPU_CRYPTO_BUF)
+DECLARE_MS_PPU_FX(CRYPTO_BUF)
+#endif
+
+#if (RTE_MS_PPU_CPUSS_CM4)
+DECLARE_MS_PPU_FX(CPUSS_CM4)
+#endif
+
+#if (RTE_MS_PPU_CPUSS_CM0)
+DECLARE_MS_PPU_FX(CPUSS_CM0)
+#endif
+
+#if (RTE_MS_PPU_CPUSS_CM0_INT)
+DECLARE_MS_PPU_FX(CPUSS_CM0_INT)
+#endif
+
+#if (RTE_MS_PPU_CPUSS_CM4_INT)
+DECLARE_MS_PPU_FX(CPUSS_CM4_INT)
+#endif
+
+#if (RTE_MS_PPU_FAULT_STRUCT0_MAIN)
+DECLARE_MS_PPU_FX(FAULT_STRUCT0_MAIN)
+#endif
+
+#if (RTE_MS_PPU_FAULT_STRUCT1_MAIN)
+DECLARE_MS_PPU_FX(FAULT_STRUCT1_MAIN)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT0_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT0_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT1_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT1_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT2_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT2_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT3_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT3_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT4_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT4_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT5_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT5_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT6_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT6_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT7_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT7_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT8_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT8_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT9_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT9_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT10_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT10_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT11_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT11_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT12_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT12_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT13_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT13_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT14_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT14_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_STRUCT15_IPC)
+DECLARE_MS_PPU_FX(IPC_STRUCT15_IPC)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT1_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT1_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT2_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT2_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT3_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT3_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT4_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT4_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT5_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT5_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT6_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT6_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT7_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT7_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT8_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT8_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT9_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT9_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT10_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT10_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT11_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT11_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT12_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT12_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT13_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT13_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT14_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT14_INTR)
+#endif
+
+#if (RTE_MS_PPU_IPC_INTR_STRUCT15_INTR)
+DECLARE_MS_PPU_FX(IPC_INTR_STRUCT15_INTR)
+#endif
+
+#if (RTE_MS_PPU_PROT_SMPU_MAIN)
+DECLARE_MS_PPU_FX(PROT_SMPU_MAIN)
+#endif
+
+#if (RTE_MS_PPU_PROT_MPU0_MAIN)
+DECLARE_MS_PPU_FX(PROT_MPU0_MAIN)
+#endif
+
+#if (RTE_MS_PPU_PROT_MPU5_MAIN)
+DECLARE_MS_PPU_FX(PROT_MPU5_MAIN)
+#endif
+
+#if (RTE_MS_PPU_PROT_MPU6_MAIN)
+DECLARE_MS_PPU_FX(PROT_MPU6_MAIN)
+#endif
+
+#if (RTE_MS_PPU_PROT_MPU14_MAIN)
+DECLARE_MS_PPU_FX(PROT_MPU14_MAIN)
+#endif
+
+#if (RTE_MS_PPU_FLASHC_MAIN)
+DECLARE_MS_PPU_FX(FLASHC_MAIN)
+#endif
+
+#if (RTE_MS_PPU_FLASHC_CMD)
+DECLARE_MS_PPU_FX(FLASHC_CMD)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN1)
+DECLARE_MS_PPU_FX(SRSS_MAIN1)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN2)
+DECLARE_MS_PPU_FX(SRSS_MAIN2)
+#endif
+
+#if (RTE_MS_PPU_WDT)
+DECLARE_MS_PPU_FX(WDT)
+#endif
+
+#if (RTE_MS_PPU_MAIN)
+DECLARE_MS_PPU_FX(MAIN)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN3)
+DECLARE_MS_PPU_FX(SRSS_MAIN3)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN4)
+DECLARE_MS_PPU_FX(SRSS_MAIN4)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN5)
+DECLARE_MS_PPU_FX(SRSS_MAIN5)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN6)
+DECLARE_MS_PPU_FX(SRSS_MAIN6)
+#endif
+
+#if (RTE_MS_PPU_SRSS_MAIN7)
+DECLARE_MS_PPU_FX(SRSS_MAIN7)
+#endif
+
+#if (RTE_MS_PPU_BACKUP_BACKUP)
+DECLARE_MS_PPU_FX(BACKUP_BACKUP)
+#endif
+
+#if (RTE_MS_PPU_DW0_DW)
+DECLARE_MS_PPU_FX(DW0_DW)
+#endif
+
+#if (RTE_MS_PPU_DW1_DW)
+DECLARE_MS_PPU_FX(DW1_DW)
+#endif
+
+#if (RTE_MS_PPU_DW0_DW_CRC)
+DECLARE_MS_PPU_FX(DW0_DW_CRC)
+#endif
+
+#if (RTE_MS_PPU_DW1_DW_CRC)
+DECLARE_MS_PPU_FX(DW1_DW_CRC)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT0_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT0_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT1_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT1_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT2_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT2_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT3_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT3_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT4_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT4_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT5_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT5_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT6_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT6_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT7_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT7_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT8_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT8_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT9_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT9_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT10_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT10_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT11_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT11_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT12_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT12_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT13_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT13_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT14_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT14_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT15_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT15_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT16_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT16_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT17_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT17_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT18_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT18_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT19_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT19_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT20_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT20_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT21_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT21_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT22_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT22_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT23_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT23_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT24_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT24_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT25_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT25_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT26_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT26_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT27_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT27_CH)
+#endif
+
+#if (RTE_MS_PPU_DW0_CH_STRUCT28_CH)
+DECLARE_MS_PPU_FX(DW0_CH_STRUCT28_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT0_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT0_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT1_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT1_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT2_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT2_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT3_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT3_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT4_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT4_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT5_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT5_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT6_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT6_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT7_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT7_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT8_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT8_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT9_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT9_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT10_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT10_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT11_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT11_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT12_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT12_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT13_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT13_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT14_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT14_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT15_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT15_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT16_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT16_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT17_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT17_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT18_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT18_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT19_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT19_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT20_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT20_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT21_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT21_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT22_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT22_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT23_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT23_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT24_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT24_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT25_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT25_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT26_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT26_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT27_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT27_CH)
+#endif
+
+#if (RTE_MS_PPU_DW1_CH_STRUCT28_CH)
+DECLARE_MS_PPU_FX(DW1_CH_STRUCT28_CH)
+#endif
+
+#if (RTE_MS_PPU_DMAC_TOP)
+DECLARE_MS_PPU_FX(DMAC_TOP)
+#endif
+
+#if (RTE_MS_PPU_DMAC_CH0_CH)
+DECLARE_MS_PPU_FX(DMAC_CH0_CH)
+#endif
+
+#if (RTE_MS_PPU_DMAC_CH1_CH)
+DECLARE_MS_PPU_FX(DMAC_CH1_CH)
+#endif
+
+#if (RTE_MS_PPU_DMAC_CH2_CH)
+DECLARE_MS_PPU_FX(DMAC_CH2_CH)
+#endif
+
+#if (RTE_MS_PPU_DMAC_CH3_CH)
+DECLARE_MS_PPU_FX(DMAC_CH3_CH)
+#endif
+
+#if (RTE_MS_PPU_EFUSE_DATA)
+DECLARE_MS_PPU_FX(EFUSE_DATA)
+#endif
+
+#if (RTE_MS_PPU_PROFILE)
+DECLARE_MS_PPU_FX(PROFILE)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT0_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT0_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT1_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT1_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT2_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT2_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT3_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT3_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT4_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT4_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT5_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT5_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT6_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT6_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT7_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT7_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT8_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT8_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT9_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT9_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT10_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT10_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT11_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT11_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT12_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT12_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT13_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT13_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_PRT14_PRT)
+DECLARE_MS_PPU_FX(HSIOM_PRT14_PRT)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_AMUX)
+DECLARE_MS_PPU_FX(HSIOM_AMUX)
+#endif
+
+#if (RTE_MS_PPU_HSIOM_MON)
+DECLARE_MS_PPU_FX(HSIOM_MON)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT0_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT0_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT1_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT1_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT2_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT2_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT3_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT3_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT4_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT4_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT5_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT5_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT6_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT6_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT7_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT7_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT8_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT8_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT9_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT9_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT10_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT10_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT11_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT11_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT12_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT12_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT13_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT13_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT14_PRT)
+DECLARE_MS_PPU_FX(GPIO_PRT14_PRT)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT0_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT0_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT1_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT1_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT2_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT2_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT3_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT3_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT4_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT4_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT5_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT5_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT6_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT6_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT7_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT7_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT8_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT8_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT9_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT9_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT10_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT10_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT11_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT11_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT12_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT12_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT13_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT13_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_PRT14_CFG)
+DECLARE_MS_PPU_FX(GPIO_PRT14_CFG)
+#endif
+
+#if (RTE_MS_PPU_GPIO_GPIO)
+DECLARE_MS_PPU_FX(GPIO_GPIO)
+#endif
+
+#if (RTE_MS_PPU_SMARTIO_PRT8_PRT)
+DECLARE_MS_PPU_FX(SMARTIO_PRT8_PRT)
+#endif
+
+#if (RTE_MS_PPU_SMARTIO_PRT9_PRT)
+DECLARE_MS_PPU_FX(SMARTIO_PRT9_PRT)
+#endif
+
+#if (RTE_MS_PPU_LPCOMP)
+DECLARE_MS_PPU_FX(LPCOMP)
+#endif
+
+#if (RTE_MS_PPU_CSD0)
+DECLARE_MS_PPU_FX(CSD0)
+#endif
+
+#if (RTE_MS_PPU_TCPWM0)
+DECLARE_MS_PPU_FX(TCPWM0)
+#endif
+
+#if (RTE_MS_PPU_TCPWM1)
+DECLARE_MS_PPU_FX(TCPWM1)
+#endif
+
+#if (RTE_MS_PPU_LCD0)
+DECLARE_MS_PPU_FX(LCD0)
+#endif
+
+#if (RTE_MS_PPU_USBFS0)
+DECLARE_MS_PPU_FX(USBFS0)
+#endif
+
+#if (RTE_MS_PPU_SMIF0)
+DECLARE_MS_PPU_FX(SMIF0)
+#endif
+
+#if (RTE_MS_PPU_SDHC0)
+DECLARE_MS_PPU_FX(SDHC0)
+#endif
+
+#if (RTE_MS_PPU_SDHC1)
+DECLARE_MS_PPU_FX(SDHC1)
+#endif
+
+#if (RTE_MS_PPU_SCB0)
+DECLARE_MS_PPU_FX(SCB0)
+#endif
+
+#if (RTE_MS_PPU_SCB1)
+DECLARE_MS_PPU_FX(SCB1)
+#endif
+
+#if (RTE_MS_PPU_SCB2)
+DECLARE_MS_PPU_FX(SCB2)
+#endif
+
+#if (RTE_MS_PPU_SCB3)
+DECLARE_MS_PPU_FX(SCB3)
+#endif
+
+#if (RTE_MS_PPU_SCB4)
+DECLARE_MS_PPU_FX(SCB4)
+#endif
+
+#if (RTE_MS_PPU_SCB5)
+DECLARE_MS_PPU_FX(SCB5)
+#endif
+
+#if (RTE_MS_PPU_SCB6)
+DECLARE_MS_PPU_FX(SCB6)
+#endif
+
+#if (RTE_MS_PPU_SCB7)
+DECLARE_MS_PPU_FX(SCB7)
+#endif
+
+#if (RTE_MS_PPU_SCB8)
+DECLARE_MS_PPU_FX(SCB8)
+#endif
+
+#if (RTE_MS_PPU_SCB9)
+DECLARE_MS_PPU_FX(SCB9)
+#endif
+
+#if (RTE_MS_PPU_SCB10)
+DECLARE_MS_PPU_FX(SCB10)
+#endif
+
+#if (RTE_MS_PPU_SCB11)
+DECLARE_MS_PPU_FX(SCB11)
+#endif
+
+#if (RTE_MS_PPU_SCB12)
+DECLARE_MS_PPU_FX(SCB12)
+#endif
+
+#if (RTE_MS_PPU_PDM0)
+DECLARE_MS_PPU_FX(PDM0)
+#endif
+
+#if (RTE_MS_PPU_I2S0)
+DECLARE_MS_PPU_FX(I2S0)
+#endif
+
+#if (RTE_MS_PPU_I2S1)
+DECLARE_MS_PPU_FX(I2S1)
+#endif
+
+#endif /* __DRIVER_PPU_H__ */
diff --git a/platform/ext/target/cypress/psoc64/driver_smpu.c b/platform/ext/target/cypress/psoc64/driver_smpu.c
new file mode 100644
index 0000000..c136362
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/driver_smpu.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+
+#include "driver_smpu.h"
+#include "pc_config.h"
+#include "region_defs.h"
+#include "RTE_Device.h"
+#include "smpu_config.h"
+
+#include "cy_prot.h"
+
+/* Affect all 8 subregions */
+#define ALL_ENABLED 0
+
+struct smpu_resources {
+ PROT_SMPU_SMPU_STRUCT_Type *smpu;
+ cy_stc_smpu_cfg_t slave_config;
+ cy_stc_smpu_cfg_t master_config;
+};
+
+static const char * smpu_name(const SMPU_Resources *smpu_dev)
+{
+ switch ((int)smpu_dev->smpu) {
+ case (int)PROT_SMPU_SMPU_STRUCT0:
+ return "SMPU 0";
+ case (int)PROT_SMPU_SMPU_STRUCT1:
+ return "SMPU 1";
+ case (int)PROT_SMPU_SMPU_STRUCT2:
+ return "SMPU 2";
+ case (int)PROT_SMPU_SMPU_STRUCT3:
+ return "SMPU 3";
+ case (int)PROT_SMPU_SMPU_STRUCT4:
+ return "SMPU 4";
+ case (int)PROT_SMPU_SMPU_STRUCT5:
+ return "SMPU 5";
+ case (int)PROT_SMPU_SMPU_STRUCT6:
+ return "SMPU 6";
+ case (int)PROT_SMPU_SMPU_STRUCT7:
+ return "SMPU 7";
+ case (int)PROT_SMPU_SMPU_STRUCT8:
+ return "SMPU 8";
+ case (int)PROT_SMPU_SMPU_STRUCT9:
+ return "SMPU 9";
+ case (int)PROT_SMPU_SMPU_STRUCT10:
+ return "SMPU 10";
+ case (int)PROT_SMPU_SMPU_STRUCT11:
+ return "SMPU 11";
+ case (int)PROT_SMPU_SMPU_STRUCT12:
+ return "SMPU 12";
+ case (int)PROT_SMPU_SMPU_STRUCT13:
+ return "SMPU 13";
+ case (int)PROT_SMPU_SMPU_STRUCT14:
+ return "SMPU 14";
+ case (int)PROT_SMPU_SMPU_STRUCT15:
+ return "SMPU 15";
+ default:
+ return "Unrecognised SMPU";
+ }
+}
+
+/* API functions */
+cy_en_prot_status_t SMPU_Configure(const SMPU_Resources *smpu_dev)
+{
+ cy_en_prot_status_t ret;
+
+ printf("%s(%s) - address = %p, size = %#x bytes, %s subregions enabled\n",
+ __func__,
+ smpu_name(smpu_dev),
+ smpu_dev->slave_config.address,
+ (uint32_t)REGIONSIZE_TO_BYTES(smpu_dev->slave_config.regionSize),
+ smpu_dev->slave_config.subregions == ALL_ENABLED ? "all" : "some");
+ if (smpu_dev->slave_config.subregions != ALL_ENABLED) {
+ printf("\tsubregion size = %#x bytes\n",
+ (uint32_t)REGIONSIZE_TO_BYTES(smpu_dev->slave_config.regionSize)/8);
+ for (int i=0; i<8; i++) {
+ printf("\tsubregion %d %s\n",
+ i,
+ smpu_dev->slave_config.subregions & (1<<i) ? "disabled" : "enabled");
+ }
+ }
+
+ ret = Cy_Prot_ConfigSmpuSlaveStruct(smpu_dev->smpu,
+ &smpu_dev->slave_config);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+ ret = Cy_Prot_ConfigSmpuMasterStruct(smpu_dev->smpu,
+ &smpu_dev->master_config);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+ ret = Cy_Prot_EnableSmpuSlaveStruct(smpu_dev->smpu);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+ ret = Cy_Prot_EnableSmpuMasterStruct(smpu_dev->smpu);
+ return ret;
+}
+
+/* Only allow privileged secure PC=1 bus masters to change unconfigured SMPUs */
+cy_en_prot_status_t protect_unconfigured_smpus(void)
+{
+ const cy_stc_smpu_cfg_t smpu_config = COMMON_SMPU_MASTER_CONFIG;
+ cy_en_prot_status_t ret = CY_PROT_SUCCESS;
+ int i;
+ uint32_t att0, att1;
+
+ for (i = 0; i < CPUSS_PROT_SMPU_STRUCT_NR; i++) {
+ att0 = PROT->SMPU.SMPU_STRUCT[i].ATT0;
+ att1 = PROT->SMPU.SMPU_STRUCT[i].ATT1;
+
+ if ((_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, att0) == 0)
+ && (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, att1) == 0)) {
+ printf("%s() - protecting unconfigured SMPU %d\n",
+ __func__, i);
+ ret = Cy_Prot_ConfigSmpuMasterStruct(&PROT->SMPU.SMPU_STRUCT[i],
+ &smpu_config);
+ if (ret != CY_PROT_SUCCESS) {
+ break;
+ }
+ ret = Cy_Prot_EnableSmpuMasterStruct(&PROT->SMPU.SMPU_STRUCT[i]);
+ if (ret != CY_PROT_SUCCESS) {
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/* Exported per-SMPU macros */
+#define DEFINE_SMPU(N) const SMPU_Resources SMPU##N##_Resources = { \
+ .smpu = PROT_SMPU_SMPU_STRUCT##N, \
+ .slave_config = SMPU##N##_SLAVE_CONFIG, \
+ .master_config = SMPU##N##_MASTER_CONFIG, \
+}; \
+
+#if (RTE_SMPU0)
+DEFINE_SMPU(0)
+#endif /* RTE_SMPU0 */
+
+#if (RTE_SMPU1)
+DEFINE_SMPU(1)
+#endif /* RTE_SMPU1 */
+
+#if (RTE_SMPU2)
+DEFINE_SMPU(2)
+#endif /* RTE_SMPU2 */
+
+#if (RTE_SMPU3)
+DEFINE_SMPU(3)
+#endif /* RTE_SMPU3 */
+
+#if (RTE_SMPU4)
+DEFINE_SMPU(4)
+#endif /* RTE_SMPU4 */
+
+#if (RTE_SMPU5)
+DEFINE_SMPU(5)
+#endif /* RTE_SMPU5 */
+
+#if (RTE_SMPU6)
+DEFINE_SMPU(6)
+#endif /* RTE_SMPU6 */
+
+#if (RTE_SMPU7)
+DEFINE_SMPU(7)
+#endif /* RTE_SMPU7 */
+
+#if (RTE_SMPU8)
+DEFINE_SMPU(8)
+#endif /* RTE_SMPU8 */
+
+#if (RTE_SMPU9)
+DEFINE_SMPU(9)
+#endif /* RTE_SMPU9 */
+
+#if (RTE_SMPU10)
+DEFINE_SMPU(10)
+#endif /* RTE_SMPU10 */
+
+#if (RTE_SMPU11)
+DEFINE_SMPU(11)
+#endif /* RTE_SMPU11 */
+
+#if (RTE_SMPU12)
+DEFINE_SMPU(12)
+#endif /* RTE_SMPU12 */
+
+#if (RTE_SMPU13)
+DEFINE_SMPU(13)
+#endif /* RTE_SMPU13 */
+
+/* Note that SMPUs 14 and 15 are fixed by romboot */
diff --git a/platform/ext/target/cypress/psoc64/driver_smpu.h b/platform/ext/target/cypress/psoc64/driver_smpu.h
new file mode 100644
index 0000000..46bc0f2
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/driver_smpu.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DRIVER_SMPU_H__
+#define __DRIVER_SMPU_H__
+
+#include "cy_prot.h"
+#include "RTE_Device.h"
+
+typedef struct smpu_resources SMPU_Resources;
+
+/* API functions */
+cy_en_prot_status_t SMPU_Configure(const SMPU_Resources *smpu_dev);
+cy_en_prot_status_t protect_unconfigured_smpus(void);
+
+/* Exported per-SMPU macros */
+#define DECLARE_SMPU(N) extern const SMPU_Resources SMPU##N##_Resources;
+
+#if (RTE_SMPU0)
+DECLARE_SMPU(0)
+#endif /* RTE_SMPU0 */
+
+#if (RTE_SMPU1)
+DECLARE_SMPU(1)
+#endif /* RTE_SMPU1 */
+
+#if (RTE_SMPU2)
+DECLARE_SMPU(2)
+#endif /* RTE_SMPU2 */
+
+#if (RTE_SMPU3)
+DECLARE_SMPU(3)
+#endif /* RTE_SMPU3 */
+
+#if (RTE_SMPU4)
+DECLARE_SMPU(4)
+#endif /* RTE_SMPU4 */
+
+#if (RTE_SMPU5)
+DECLARE_SMPU(5)
+#endif /* RTE_SMPU5 */
+
+#if (RTE_SMPU6)
+DECLARE_SMPU(6)
+#endif /* RTE_SMPU6 */
+
+#if (RTE_SMPU7)
+DECLARE_SMPU(7)
+#endif /* RTE_SMPU7 */
+
+#if (RTE_SMPU8)
+DECLARE_SMPU(8)
+#endif /* RTE_SMPU8 */
+
+#if (RTE_SMPU9)
+DECLARE_SMPU(9)
+#endif /* RTE_SMPU9 */
+
+#if (RTE_SMPU10)
+DECLARE_SMPU(10)
+#endif /* RTE_SMPU10 */
+
+#if (RTE_SMPU11)
+DECLARE_SMPU(11)
+#endif /* RTE_SMPU11 */
+
+#if (RTE_SMPU12)
+DECLARE_SMPU(12)
+#endif /* RTE_SMPU12 */
+
+#if (RTE_SMPU13)
+DECLARE_SMPU(13)
+#endif /* RTE_SMPU13 */
+
+/* Note that SMPUs 14 and 15 are fixed by romboot */
+
+#endif /* __DRIVER_SMPU_H__ */
diff --git a/platform/ext/target/cypress/psoc64/dummy_boot_seed.c b/platform/ext/target/cypress/psoc64/dummy_boot_seed.c
new file mode 100644
index 0000000..f4cbb5c
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/dummy_boot_seed.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/include/tfm_plat_boot_seed.h"
+
+/*!
+ * \def BOOT_SEED
+ *
+ * \brief Fixed value for boot seed used for test.
+ */
+#define BOOT_SEED 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, \
+ 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, \
+ 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, \
+ 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF
+
+static const uint8_t boot_seed[BOOT_SEED_SIZE] = {BOOT_SEED};
+
+enum tfm_plat_err_t tfm_plat_get_boot_seed(uint32_t size, uint8_t *buf)
+{
+ /* FixMe: - This getter function must be ported per target platform.
+ * - Platform service shall provide an API to further interact this
+ * getter function to retrieve the boot seed.
+ */
+
+ uint32_t i;
+ uint8_t *p_dst = buf;
+ const uint8_t *p_src = boot_seed;
+
+ if (size != BOOT_SEED_SIZE) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ for (i = size; i > 0; i--) {
+ *p_dst = *p_src;
+ p_src++;
+ p_dst++;
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
diff --git a/platform/ext/target/cypress/psoc64/dummy_crypto_keys.c b/platform/ext/target/cypress/psoc64/dummy_crypto_keys.c
new file mode 100644
index 0000000..4281b38
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/dummy_crypto_keys.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2017-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/include/tfm_plat_crypto_keys.h"
+#include <stddef.h>
+#include "psa/crypto_types.h"
+
+/* FIXME: Functions in this file should be implemented by platform vendor. For
+ * the security of the storage system, it is critical to use a hardware unique
+ * key. For the security of the attestation, it is critical to use a unique key
+ * pair and keep the private key is secret.
+ */
+
+#define TFM_KEY_LEN_BYTES 16
+
+static const uint8_t sample_tfm_key[TFM_KEY_LEN_BYTES] =
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F};
+
+extern const psa_ecc_curve_t initial_attestation_curve_type;
+extern const uint8_t initial_attestation_private_key[];
+extern const uint32_t initial_attestation_private_key_size;
+
+extern const struct tfm_plat_rotpk_t device_rotpk[];
+extern const uint32_t rotpk_key_cnt;
+
+/**
+ * \brief Copy the key to the destination buffer
+ *
+ * \param[out] p_dst Pointer to buffer where to store the key
+ * \param[in] p_src Pointer to the key
+ * \param[in] size Length of the key
+ */
+static inline void copy_key(uint8_t *p_dst, const uint8_t *p_src, size_t size)
+{
+ uint32_t i;
+
+ for (i = size; i > 0; i--) {
+ *p_dst = *p_src;
+ p_src++;
+ p_dst++;
+ }
+}
+
+enum tfm_plat_err_t tfm_plat_get_huk_derived_key(const uint8_t *label,
+ size_t label_size,
+ const uint8_t *context,
+ size_t context_size,
+ uint8_t *key,
+ size_t key_size)
+{
+ (void)label;
+ (void)label_size;
+ (void)context;
+ (void)context_size;
+
+ if (key_size > TFM_KEY_LEN_BYTES) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* FIXME: Do key derivation */
+ copy_key(key, sample_tfm_key, key_size);
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t
+tfm_plat_get_initial_attest_key(uint8_t *key_buf,
+ uint32_t size,
+ struct ecc_key_t *ecc_key,
+ psa_ecc_curve_t *curve_type)
+{
+ uint8_t *key_dst;
+ const uint8_t *key_src;
+ uint32_t key_size;
+ uint32_t full_key_size = initial_attestation_private_key_size;
+
+ if (size < full_key_size) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Set the EC curve type which the key belongs to */
+ *curve_type = initial_attestation_curve_type;
+
+ /* Copy the private key to the buffer, it MUST be present */
+ key_dst = key_buf;
+ key_src = initial_attestation_private_key;
+ key_size = initial_attestation_private_key_size;
+ copy_key(key_dst, key_src, key_size);
+ ecc_key->priv_key = key_dst;
+ ecc_key->priv_key_size = key_size;
+
+ ecc_key->pubx_key = NULL;
+ ecc_key->pubx_key_size = 0;
+ ecc_key->puby_key = NULL;
+ ecc_key->puby_key_size = 0;
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+#ifdef BL2
+enum tfm_plat_err_t
+tfm_plat_get_rotpk_hash(uint8_t image_id,
+ uint8_t *rotpk_hash,
+ uint32_t *rotpk_hash_size)
+{
+ if(*rotpk_hash_size < ROTPK_HASH_LEN) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ if (image_id >= rotpk_key_cnt) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ *rotpk_hash_size = ROTPK_HASH_LEN;
+ copy_key(rotpk_hash, device_rotpk[image_id].key_hash, *rotpk_hash_size);
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+#endif
diff --git a/platform/ext/target/cypress/psoc64/dummy_device_id.c b/platform/ext/target/cypress/psoc64/dummy_device_id.c
new file mode 100644
index 0000000..1ff99b1
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/dummy_device_id.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2018-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/include/tfm_plat_device_id.h"
+#include <stddef.h>
+/*
+ * NOTE: Functions in this file must be ported per target platform.
+ */
+
+static const uint8_t implementation_id[] = {
+ 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
+ 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
+ 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+ 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+};
+
+static const uint8_t example_ean_13[] = "060456527282910010";
+/**
+ * \brief Copy the device specific ID to the destination buffer
+ *
+ * \param[out] p_dst Pointer to buffer where to store ID
+ * \param[in] p_src Pointer to the ID
+ * \param[in] size Length of the ID
+ */
+static inline void copy_id(uint8_t *p_dst, const uint8_t *p_src, size_t size)
+{
+ uint32_t i;
+
+ for (i = size; i > 0; i--) {
+ *p_dst = *p_src;
+ p_src++;
+ p_dst++;
+ }
+}
+
+enum tfm_plat_err_t tfm_plat_get_implementation_id(uint32_t *size,
+ uint8_t *buf)
+{
+ const uint8_t *p_impl_id = implementation_id;
+ uint32_t impl_id_size = sizeof(implementation_id);
+
+ if (*size < impl_id_size) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ copy_id(buf, p_impl_id, impl_id_size);
+ *size = impl_id_size;
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_get_hw_version(uint32_t *size, uint8_t *buf)
+{
+ const uint8_t *p_hw_version = example_ean_13;
+ uint32_t hw_version_size = sizeof(example_ean_13) - 1;
+
+ if (*size < hw_version_size) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ copy_id(buf, p_hw_version, hw_version_size);
+ *size = hw_version_size;
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
diff --git a/platform/ext/target/cypress/psoc64/dummy_nv_counters.c b/platform/ext/target/cypress/psoc64/dummy_nv_counters.c
new file mode 100644
index 0000000..b867a93
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/dummy_nv_counters.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/* NOTE: This API should be implemented by platform vendor. For the security of
+ * the secure storage system's and the bootloader's rollback protection etc. it
+ * is CRITICAL to use a internal (in-die) persistent memory for multiple time
+ * programmable (MTP) non-volatile counters or use a One-time Programmable (OTP)
+ * non-volatile counters solution.
+ *
+ * The current software dummy implementation is not resistant to asynchronous
+ * power failures and should not be used in production code. It is exclusively
+ * for testing purposes.
+ */
+
+#include "platform/include/tfm_plat_nv_counters.h"
+
+#include <limits.h>
+#include "Driver_Flash.h"
+#include "flash_layout.h"
+
+/* Compilation time checks to be sure the defines are well defined */
+#ifndef TFM_NV_COUNTERS_AREA_ADDR
+#error "TFM_NV_COUNTERS_AREA_ADDR must be defined in flash_layout.h"
+#endif
+
+#ifndef TFM_NV_COUNTERS_AREA_SIZE
+#error "TFM_NV_COUNTERS_AREA_SIZE must be defined in flash_layout.h"
+#endif
+
+#ifndef TFM_NV_COUNTERS_SECTOR_ADDR
+#error "TFM_NV_COUNTERS_SECTOR_ADDR must be defined in flash_layout.h"
+#endif
+
+#ifndef TFM_NV_COUNTERS_SECTOR_SIZE
+#error "TFM_NV_COUNTERS_SECTOR_SIZE must be defined in flash_layout.h"
+#endif
+
+#ifndef FLASH_DEV_NAME
+#error "FLASH_DEV_NAME must be defined in flash_layout.h"
+#endif
+/* End of compilation time checks to be sure the defines are well defined */
+
+#define SECTOR_OFFSET 0
+#define NV_COUNTER_SIZE sizeof(uint32_t)
+#define INIT_VALUE_SIZE NV_COUNTER_SIZE
+#define NV_COUNTERS_AREA_OFFSET (TFM_NV_COUNTERS_AREA_ADDR - \
+ TFM_NV_COUNTERS_SECTOR_ADDR)
+
+#define NV_COUNTERS_INITIALIZED 0xC0DE0042
+
+/* Import the CMSIS flash device driver */
+extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
+
+enum tfm_plat_err_t tfm_plat_init_nv_counter(void)
+{
+ int32_t err;
+ uint32_t i;
+ uint32_t nbr_counters = ((TFM_NV_COUNTERS_AREA_SIZE - INIT_VALUE_SIZE)
+ / NV_COUNTER_SIZE);
+ uint32_t *p_nv_counter;
+ uint8_t sector_data[TFM_NV_COUNTERS_SECTOR_SIZE] = {0};
+
+ err = FLASH_DEV_NAME.Initialize(NULL);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Read the whole sector to be able to erase and write later in the flash */
+ err = FLASH_DEV_NAME.ReadData(TFM_NV_COUNTERS_SECTOR_ADDR, sector_data,
+ TFM_NV_COUNTERS_SECTOR_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Set the pointer to nv counters position */
+ p_nv_counter = (uint32_t *)(sector_data + NV_COUNTERS_AREA_OFFSET);
+
+ if (p_nv_counter[nbr_counters] == NV_COUNTERS_INITIALIZED) {
+ return TFM_PLAT_ERR_SUCCESS;
+ }
+
+ /* Add watermark, at the end of the NV counters area, to indicate that NV
+ * counters have been initialized.
+ */
+ p_nv_counter[nbr_counters] = NV_COUNTERS_INITIALIZED;
+
+ /* Initialize all counters to 0 */
+ for (i = 0; i < nbr_counters; i++) {
+ p_nv_counter[i] = 0;
+ }
+
+ /* Erase sector before write in it */
+ err = FLASH_DEV_NAME.EraseSector(TFM_NV_COUNTERS_SECTOR_ADDR);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Write in flash the in-memory block content after modification */
+ err = FLASH_DEV_NAME.ProgramData(TFM_NV_COUNTERS_SECTOR_ADDR, sector_data,
+ TFM_NV_COUNTERS_SECTOR_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_read_nv_counter(enum tfm_nv_counter_t counter_id,
+ uint32_t size, uint8_t *val)
+{
+ int32_t err;
+ uint32_t flash_addr;
+
+ if (size != NV_COUNTER_SIZE) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ flash_addr = TFM_NV_COUNTERS_AREA_ADDR + (counter_id * NV_COUNTER_SIZE);
+
+ err = FLASH_DEV_NAME.ReadData(flash_addr, val, NV_COUNTER_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_set_nv_counter(enum tfm_nv_counter_t counter_id,
+ uint32_t value)
+{
+ int32_t err;
+ uint32_t *p_nv_counter;
+ uint8_t sector_data[TFM_NV_COUNTERS_SECTOR_SIZE];
+
+ /* Read the whole sector to be able to erase and write later in the flash */
+ err = FLASH_DEV_NAME.ReadData(TFM_NV_COUNTERS_SECTOR_ADDR, sector_data,
+ TFM_NV_COUNTERS_SECTOR_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Set the pointer to nv counter position */
+ p_nv_counter = (uint32_t *)(sector_data + NV_COUNTERS_AREA_OFFSET +
+ (counter_id * NV_COUNTER_SIZE));
+
+ if (value != *p_nv_counter) {
+
+ if (value > *p_nv_counter) {
+ *p_nv_counter = value;
+ } else {
+ return TFM_PLAT_ERR_INVALID_INPUT;
+ }
+
+ /* Erase sector before write in it */
+ err = FLASH_DEV_NAME.EraseSector(TFM_NV_COUNTERS_SECTOR_ADDR);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Write in flash the in-memory block content after modification */
+ err = FLASH_DEV_NAME.ProgramData(TFM_NV_COUNTERS_SECTOR_ADDR,
+ sector_data,
+ TFM_NV_COUNTERS_SECTOR_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_increment_nv_counter(
+ enum tfm_nv_counter_t counter_id)
+{
+ uint32_t security_cnt;
+ enum tfm_plat_err_t err;
+
+ err = tfm_plat_read_nv_counter(counter_id,
+ sizeof(security_cnt),
+ (uint8_t *)&security_cnt);
+ if (err != TFM_PLAT_ERR_SUCCESS) {
+ return err;
+ }
+
+ if (security_cnt == UINT32_MAX) {
+ return TFM_PLAT_ERR_MAX_VALUE;
+ }
+
+ return tfm_plat_set_nv_counter(counter_id, security_cnt + 1u);
+}
diff --git a/platform/ext/target/cypress/psoc64/mailbox/mailbox_ipc_intr.c b/platform/ext/target/cypress/psoc64/mailbox/mailbox_ipc_intr.c
new file mode 100644
index 0000000..89bdc37
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/mailbox/mailbox_ipc_intr.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdint.h>
+
+#include "cmsis.h"
+#include "cmsis_compiler.h"
+
+#include "cy_ipc_drv.h"
+#include "spe_ipc_config.h"
+#include "platform_multicore.h"
+
+__STATIC_INLINE void tfm_trigger_pendsv(void)
+{
+ SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
+}
+
+void mailbox_clear_intr(void)
+{
+ uint32_t status;
+
+ status = Cy_IPC_Drv_GetInterruptStatusMasked(
+ Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT));
+ status >>= CY_IPC_NOTIFY_SHIFT;
+ if ((status & IPC_RX_INT_MASK) == 0) {
+ return;
+ }
+
+ Cy_IPC_Drv_ClearInterrupt(Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT),
+ 0, IPC_RX_INT_MASK);
+}
+
+void NvicMux7_IRQHandler(void)
+{
+ uint32_t magic;
+
+ mailbox_clear_intr();
+
+ platform_mailbox_fetch_msg_data(&magic);
+ if (magic == PSA_CLIENT_CALL_REQ_MAGIC) {
+ tfm_trigger_pendsv();
+ }
+}
diff --git a/platform/ext/target/cypress/psoc64/mailbox/ns_ipc_config.h b/platform/ext/target/cypress/psoc64/mailbox/ns_ipc_config.h
new file mode 100644
index 0000000..0549ba3
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/mailbox/ns_ipc_config.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _IPC_CONFIG_H_
+#define _IPC_CONFIG_H_
+
+#include "platform_multicore.h"
+
+#define IPC_RX_CHAN IPC_PSA_CLIENT_REPLY_CHAN
+#define IPC_RX_INTR_STRUCT IPC_PSA_CLIENT_REPLY_INTR_STRUCT
+#define IPC_RX_INT_MASK IPC_PSA_CLIENT_REPLY_INTR_MASK
+
+#define IPC_TX_CHAN IPC_PSA_CLIENT_CALL_CHAN
+#define IPC_TX_NOTIFY_MASK IPC_PSA_CLIENT_CALL_NOTIFY_MASK
+
+#endif
diff --git a/platform/ext/target/cypress/psoc64/mailbox/platform_multicore.c b/platform/ext/target/cypress/psoc64/mailbox/platform_multicore.c
new file mode 100644
index 0000000..e860ae0
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/mailbox/platform_multicore.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2019 Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "cmsis_compiler.h"
+
+#include "platform_multicore.h"
+#include "tfm_multi_core_api.h"
+#include "tfm_ns_mailbox.h"
+
+#include "cy_ipc_drv.h"
+#include "cy_sysint.h"
+#if CY_SYSTEM_CPU_CM0P
+#include "spe_ipc_config.h"
+#else
+#include "ns_ipc_config.h"
+#endif
+
+int platform_mailbox_fetch_msg_ptr(void **msg_ptr)
+{
+ cy_en_ipcdrv_status_t status;
+
+ if (!msg_ptr) {
+ return PLATFORM_MAILBOX_INVAL_PARAMS;
+ }
+
+ status = Cy_IPC_Drv_ReadMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(IPC_RX_CHAN),
+ msg_ptr);
+ if (status != CY_IPC_DRV_SUCCESS) {
+ return PLATFORM_MAILBOX_RX_ERROR;
+ }
+
+ Cy_IPC_Drv_ReleaseNotify(Cy_IPC_Drv_GetIpcBaseAddress(IPC_RX_CHAN),
+ IPC_RX_RELEASE_MASK);
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+int platform_mailbox_fetch_msg_data(uint32_t *data_ptr)
+{
+ cy_en_ipcdrv_status_t status;
+
+ if (!data_ptr) {
+ return PLATFORM_MAILBOX_INVAL_PARAMS;
+ }
+
+ status = Cy_IPC_Drv_ReadMsgWord(Cy_IPC_Drv_GetIpcBaseAddress(IPC_RX_CHAN),
+ data_ptr);
+ if (status != CY_IPC_DRV_SUCCESS) {
+ return PLATFORM_MAILBOX_RX_ERROR;
+ }
+
+ Cy_IPC_Drv_ReleaseNotify(Cy_IPC_Drv_GetIpcBaseAddress(IPC_RX_CHAN),
+ IPC_RX_RELEASE_MASK);
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+int platform_mailbox_send_msg_ptr(const void *msg_ptr)
+{
+ cy_en_ipcdrv_status_t status;
+
+ if (!msg_ptr)
+ return PLATFORM_MAILBOX_INVAL_PARAMS;
+
+ status = Cy_IPC_Drv_SendMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(IPC_TX_CHAN),
+ IPC_TX_NOTIFY_MASK, msg_ptr);
+ if (status != CY_IPC_DRV_SUCCESS) {
+ return PLATFORM_MAILBOX_TX_ERROR;
+ }
+
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+int platform_mailbox_send_msg_data(uint32_t data)
+{
+ cy_en_ipcdrv_status_t status;
+
+ status = Cy_IPC_Drv_SendMsgWord(Cy_IPC_Drv_GetIpcBaseAddress(IPC_TX_CHAN),
+ IPC_TX_NOTIFY_MASK, data);
+ if (status != CY_IPC_DRV_SUCCESS) {
+ return PLATFORM_MAILBOX_TX_ERROR;
+ }
+
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+void platform_mailbox_wait_for_notify(void)
+{
+ uint32_t status;
+
+ while (1) {
+ status = Cy_IPC_Drv_GetInterruptStatusMasked(
+ Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT));
+ status >>= CY_IPC_NOTIFY_SHIFT;
+ if (status & IPC_RX_INT_MASK) {
+ break;
+ }
+ }
+
+ Cy_IPC_Drv_ClearInterrupt(Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT),
+ 0, IPC_RX_INT_MASK);
+}
+
+int platform_ns_ipc_init(void)
+{
+ Cy_IPC_Drv_SetInterruptMask(Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT),
+ 0, IPC_RX_INT_MASK);
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+int32_t tfm_platform_ns_wait_for_s_cpu_ready(void)
+{
+ uint32_t data = 0;
+
+ if (platform_ns_ipc_init() != PLATFORM_MAILBOX_SUCCESS) {
+ return PLATFORM_MAILBOX_INVAL_PARAMS;
+ }
+ while(data != IPC_SYNC_MAGIC)
+ {
+ platform_mailbox_wait_for_notify();
+ platform_mailbox_fetch_msg_data(&data);
+ }
+
+ if (platform_mailbox_send_msg_data(~IPC_SYNC_MAGIC) !=
+ PLATFORM_MAILBOX_SUCCESS) {
+ return PLATFORM_MAILBOX_RX_ERROR;
+ }
+ return PLATFORM_MAILBOX_SUCCESS;
+}
diff --git a/platform/ext/target/cypress/psoc64/mailbox/platform_multicore.h b/platform/ext/target/cypress/psoc64/mailbox/platform_multicore.h
new file mode 100644
index 0000000..72e24b6
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/mailbox/platform_multicore.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _TFM_PLATFORM_MULTICORE_
+#define _TFM_PLATFORM_MULTICORE_
+
+#include <stdint.h>
+#include "cy_device_headers.h"
+
+#define IPC_PSA_CLIENT_CALL_CHAN (8)
+#define IPC_PSA_CLIENT_CALL_INTR_STRUCT (6)
+#define IPC_PSA_CLIENT_CALL_INTR_MASK (1 << IPC_PSA_CLIENT_CALL_CHAN)
+#define IPC_PSA_CLIENT_CALL_NOTIFY_MASK (1 << IPC_PSA_CLIENT_CALL_INTR_STRUCT)
+#define IPC_PSA_CLIENT_CALL_IPC_INTR cpuss_interrupts_ipc_6_IRQn
+
+#define IPC_PSA_CLIENT_REPLY_CHAN (9)
+#define IPC_PSA_CLIENT_REPLY_INTR_STRUCT (5)
+#define IPC_PSA_CLIENT_REPLY_INTR_MASK (1 << IPC_PSA_CLIENT_REPLY_CHAN)
+#define IPC_PSA_CLIENT_REPLY_NOTIFY_MASK (1 << IPC_PSA_CLIENT_REPLY_INTR_STRUCT)
+
+#define IPC_RX_RELEASE_MASK (0)
+
+#define CY_IPC_NOTIFY_SHIFT (16)
+
+#define PSA_CLIENT_CALL_REQ_MAGIC (0xA5CF50C6)
+
+#define NS_MAILBOX_INIT_ENABLE (0xAE)
+#define S_MAILBOX_READY (0xC3)
+
+#define PLATFORM_MAILBOX_SUCCESS (0x0)
+#define PLATFORM_MAILBOX_INVAL_PARAMS (INT32_MIN + 1)
+#define PLATFORM_MAILBOX_TX_ERROR (INT32_MIN + 2)
+#define PLATFORM_MAILBOX_RX_ERROR (INT32_MIN + 3)
+#define PLATFORM_MAILBOX_INIT_ERROR (INT32_MIN + 4)
+
+/* Inter-Processor Communication (IPC) data channel for the Semaphores */
+#define PLATFORM_MAILBOX_IPC_CHAN_SEMA CY_IPC_CHAN_SEMA
+#define MAILBOX_SEMAPHORE_NUM (16)
+
+#define IPC_SYNC_MAGIC 0x7DADE011
+
+/**
+ * \brief Fetch a pointer from mailbox message
+ *
+ * \param[out] msg_ptr The address to write the pointer value to.
+ *
+ * \retval 0 The operation succeeds.
+ * \retval else The operation fails.
+ */
+int platform_mailbox_fetch_msg_ptr(void **msg_ptr);
+
+/**
+ * \brief Fetch a data value from mailbox message
+ *
+ * \param[out] data_ptr The address to write the pointer value to.
+ *
+ * \retval 0 The operation succeeds.
+ * \retval else The operation fails.
+ */
+int platform_mailbox_fetch_msg_data(uint32_t *data_ptr);
+
+/**
+ * \brief Send a pointer via mailbox message
+ *
+ * \param[in] msg_ptr The pointer value to be sent.
+ *
+ * \retval 0 The operation succeeds.
+ * \retval else The operation fails.
+ */
+int platform_mailbox_send_msg_ptr(const void *msg_ptr);
+
+/**
+ * \brief Send a data value via mailbox message
+ *
+ * \param[in] data The data value to be sent
+ *
+ * \retval 0 The operation succeeds.
+ * \retval else The operation fails.
+ */
+int platform_mailbox_send_msg_data(uint32_t data);
+
+/**
+ * \brief Wait for a mailbox notify event.
+ */
+void platform_mailbox_wait_for_notify(void);
+
+/**
+ * \brief IPC initialization
+ *
+ * \retval 0 The operation succeeds.
+ * \retval else The operation fails.
+ */
+int platform_ns_ipc_init(void);
+
+#endif
diff --git a/platform/ext/target/cypress/psoc64/mailbox/platform_ns_mailbox.c b/platform/ext/target/cypress/psoc64/mailbox/platform_ns_mailbox.c
new file mode 100644
index 0000000..f608da6
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/mailbox/platform_ns_mailbox.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* -------------------------------------- Includes ----------------------------------- */
+#include <limits.h>
+#include <string.h>
+
+#include "cmsis_compiler.h"
+
+#include "cy_ipc_drv.h"
+#include "cy_sysint.h"
+#include "cy_ipc_sema.h"
+
+#include "ns_ipc_config.h"
+#include "tfm_ns_mailbox.h"
+#include "platform_multicore.h"
+
+/* -------------------------------------- HAL API ------------------------------------ */
+
+static void mailbox_ipc_init(void)
+{
+ Cy_IPC_Drv_SetInterruptMask(Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT),
+ 0, IPC_RX_INT_MASK);
+}
+
+int32_t tfm_ns_mailbox_hal_notify_peer(void)
+{
+ cy_en_ipcdrv_status_t status;
+
+ status = Cy_IPC_Drv_SendMsgWord(Cy_IPC_Drv_GetIpcBaseAddress(IPC_TX_CHAN),
+ IPC_TX_NOTIFY_MASK,
+ PSA_CLIENT_CALL_REQ_MAGIC);
+
+ if (status == CY_IPC_DRV_SUCCESS) {
+ return MAILBOX_SUCCESS;
+ } else {
+ return MAILBOX_CHAN_BUSY;
+ }
+}
+
+static int32_t mailbox_sema_init(void)
+{
+#if defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ /* semaphore data */
+ static uint32_t tfm_sema __attribute__((section("TFM_SHARED_DATA")));
+
+ if (Cy_IPC_Sema_Init(PLATFORM_MAILBOX_IPC_CHAN_SEMA,
+ sizeof(tfm_sema) * CHAR_BIT,
+ &tfm_sema) != CY_IPC_SEMA_SUCCESS) {
+ return PLATFORM_MAILBOX_INIT_ERROR;
+ }
+#endif
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+int32_t tfm_ns_mailbox_hal_init(struct ns_mailbox_queue_t *queue)
+{
+ uint32_t stage;
+
+ if (!queue) {
+ return MAILBOX_INVAL_PARAMS;
+ }
+
+ /* Init semaphores used for critical sections */
+ if (mailbox_sema_init() != PLATFORM_MAILBOX_SUCCESS)
+ return MAILBOX_INIT_ERROR;
+
+ /*
+ * FIXME
+ * Further verification of mailbox queue address may be required according
+ * to diverse NSPE implementations.
+ */
+
+ mailbox_ipc_init();
+
+ /*
+ * Wait until SPE mailbox library is ready to receive NSPE mailbox queue
+ * address.
+ */
+ while (1) {
+ platform_mailbox_wait_for_notify();
+
+ platform_mailbox_fetch_msg_data(&stage);
+ if (stage == NS_MAILBOX_INIT_ENABLE) {
+ break;
+ }
+ }
+
+ /* Send out the address */
+ platform_mailbox_send_msg_ptr(queue);
+
+ /* Wait until SPE mailbox service is ready */
+ while (1) {
+ platform_mailbox_wait_for_notify();
+
+ platform_mailbox_fetch_msg_data(&stage);
+ if (stage == S_MAILBOX_READY) {
+ break;
+ }
+ }
+
+ return MAILBOX_SUCCESS;
+}
+
+void tfm_ns_mailbox_hal_enter_critical(void)
+{
+ while (Cy_IPC_Sema_Set(MAILBOX_SEMAPHORE_NUM, false) !=
+ CY_IPC_SEMA_SUCCESS) {
+ }
+}
+
+void tfm_ns_mailbox_hal_exit_critical(void)
+{
+ while (Cy_IPC_Sema_Clear(MAILBOX_SEMAPHORE_NUM, false) !=
+ CY_IPC_SEMA_SUCCESS) {
+ }
+}
diff --git a/platform/ext/target/cypress/psoc64/mailbox/platform_spe_mailbox.c b/platform/ext/target/cypress/psoc64/mailbox/platform_spe_mailbox.c
new file mode 100644
index 0000000..272bf42
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/mailbox/platform_spe_mailbox.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* -------------------------------------- Includes ----------------------------------- */
+#include "cmsis.h"
+#include "cmsis_compiler.h"
+
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_ipc_drv.h"
+#include "cy_sysint.h"
+#include "cy_ipc_sema.h"
+
+#include "spe_ipc_config.h"
+#include "tfm_spe_mailbox.h"
+#include "platform_multicore.h"
+
+/* -------------------------------------- HAL API ------------------------------------ */
+
+int32_t tfm_mailbox_hal_notify_peer(void)
+{
+ return MAILBOX_SUCCESS;
+}
+
+static void mailbox_ipc_config(void)
+{
+ Cy_SysInt_SetIntSource(PSA_CLIENT_CALL_NVIC_IRQn, PSA_CLIENT_CALL_IPC_INTR);
+
+ NVIC_SetPriority(PSA_CLIENT_CALL_NVIC_IRQn, PSA_CLIENT_CALL_IRQ_PRIORITY);
+
+ NVIC_EnableIRQ(PSA_CLIENT_CALL_NVIC_IRQn);
+}
+
+static int32_t tfm_mailbox_sema_init(void)
+{
+#if defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ if (Cy_IPC_Sema_Init(PLATFORM_MAILBOX_IPC_CHAN_SEMA, 0,
+ NULL) != CY_IPC_SEMA_SUCCESS) {
+ return PLATFORM_MAILBOX_INIT_ERROR;
+ }
+#endif
+
+ if (MAILBOX_SEMAPHORE_NUM >= Cy_IPC_Sema_GetMaxSems()) {
+ return PLATFORM_MAILBOX_INIT_ERROR;
+ }
+
+ /* TODO Check that the semaphore data is in NS memory */
+
+ return PLATFORM_MAILBOX_SUCCESS;
+}
+
+int32_t tfm_mailbox_hal_init(struct secure_mailbox_queue_t *s_queue)
+{
+ struct ns_mailbox_queue_t *ns_queue = NULL;
+
+ /* Init semaphores used for critical sections */
+ if (tfm_mailbox_sema_init() != PLATFORM_MAILBOX_SUCCESS)
+ return MAILBOX_INIT_ERROR;
+
+ /* Inform NSPE that NSPE mailbox initialization can start */
+ platform_mailbox_send_msg_data(NS_MAILBOX_INIT_ENABLE);
+
+ platform_mailbox_wait_for_notify();
+
+ /* Receive the address of NSPE mailbox queue */
+ platform_mailbox_fetch_msg_ptr((void **)&ns_queue);
+
+ /*
+ * FIXME
+ * Necessary sanity check of the address of NPSE mailbox queue should
+ * be implemented there.
+ */
+
+ s_queue->ns_queue = ns_queue;
+
+ mailbox_ipc_config();
+
+ /* Inform NSPE that SPE mailbox service is ready */
+ platform_mailbox_send_msg_data(S_MAILBOX_READY);
+
+ return MAILBOX_SUCCESS;
+}
+
+void tfm_mailbox_hal_enter_critical(void)
+{
+ while (CY_IPC_SEMA_SUCCESS !=
+ Cy_IPC_Sema_Set(MAILBOX_SEMAPHORE_NUM, false))
+ {
+ }
+}
+
+void tfm_mailbox_hal_exit_critical(void)
+{
+ while (CY_IPC_SEMA_SUCCESS !=
+ Cy_IPC_Sema_Clear(MAILBOX_SEMAPHORE_NUM, false))
+ {
+ }
+}
diff --git a/platform/ext/target/cypress/psoc64/mailbox/spe_ipc_config.h b/platform/ext/target/cypress/psoc64/mailbox/spe_ipc_config.h
new file mode 100644
index 0000000..1bdefcc
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/mailbox/spe_ipc_config.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _IPC_CONFIG_H_
+#define _IPC_CONFIG_H_
+
+#include "platform_multicore.h"
+#include "cy_device_headers.h"
+
+#define IPC_RX_CHAN IPC_PSA_CLIENT_CALL_CHAN
+#define IPC_RX_INTR_STRUCT IPC_PSA_CLIENT_CALL_INTR_STRUCT
+#define IPC_RX_INT_MASK IPC_PSA_CLIENT_CALL_INTR_MASK
+
+#define IPC_TX_CHAN IPC_PSA_CLIENT_REPLY_CHAN
+#define IPC_TX_NOTIFY_MASK IPC_PSA_CLIENT_REPLY_NOTIFY_MASK
+
+#define PSA_CLIENT_CALL_NVIC_IRQn NvicMux7_IRQn
+#define PSA_CLIENT_CALL_IRQ_PRIORITY 3
+#define PSA_CLIENT_CALL_IPC_INTR IPC_PSA_CLIENT_CALL_IPC_INTR
+
+#endif
diff --git a/platform/ext/target/cypress/psoc64/partition/flash_layout.h b/platform/ext/target/cypress/psoc64/partition/flash_layout.h
new file mode 100644
index 0000000..c33adf0
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/partition/flash_layout.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __FLASH_LAYOUT_H__
+#define __FLASH_LAYOUT_H__
+
+/* Flash layout with BL2:
+ *
+ * Not supported
+ *
+ * Flash layout if BL2 not defined:
+ *
+ * 0x1000_0000 Secure image primary (320 KB)
+ * 0x1005_0000 Non-secure image primary (1152 KB)
+ * 0x1017_0000 Secure image secondary (320 KB)
+ * 0x101c_0000 - 0x101f_ffff Reserved
+ * 0x101c_0000 Secure Storage Area (20 KB)
+ * 0x101c_5000 Internal Trusted Storage Area (16 KB)
+ * 0x101c_9000 NV counters area (512 Bytes)
+ * 0x101c_9200 Scratch area (27.5 KB)
+ * 0x101d_0000 Reserved (192 KB)
+ * 0x101f_ffff End of Flash
+ *
+ */
+
+#define MAX(X, Y) (((X) > (Y)) ? (X) : (Y))
+
+/* This header file is included from linker scatter file as well, where only a
+ * limited C constructs are allowed. Therefore it is not possible to include
+ * here the platform_base_address.h to access flash related defines. To resolve
+ * this some of the values are redefined here with different names, these are
+ * marked with comment.
+ */
+
+/* The size of S partition */
+#define FLASH_S_PARTITION_SIZE 0x50000 /* 320 KB */
+/* The size of NS partition */
+#define FLASH_NS_PARTITION_SIZE 0x120000 /* 1152 KB */
+
+/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */
+#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x200) /* 512 B */
+/* Same as FLASH0_SIZE */
+#define FLASH_TOTAL_SIZE (0x00200000) /* 2 MB */
+
+/* Flash layout info for BL2 bootloader */
+#define FLASH_BASE_ADDRESS (0x10000000U) /* same as FLASH0_BASE */
+
+/* Reserved areas */
+#define FLASH_RESERVED_AREA_OFFSET (SECURE_IMAGE_OFFSET + \
+ 2*SECURE_IMAGE_MAX_SIZE + \
+ NON_SECURE_IMAGE_MAX_SIZE)
+
+/* FixMe: implement proper mcuboot partitioning for CYBL */
+
+/* Reserved for Secure Storage Area */
+#define FLASH_SST_AREA_OFFSET (FLASH_RESERVED_AREA_OFFSET)
+#define FLASH_SST_AREA_SIZE (0x5000) /* 20 KB */
+
+/* Internal Trusted Storage Area */
+#define FLASH_ITS_AREA_OFFSET (FLASH_SST_AREA_OFFSET + \
+ FLASH_SST_AREA_SIZE)
+#define FLASH_ITS_AREA_SIZE (0x4000) /* 16 KB */
+
+#define FLASH_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + \
+ FLASH_ITS_AREA_SIZE)
+#define FLASH_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE)
+
+#ifdef BL2
+#error "BL2 configuration is not supported"
+#else /* BL2 */
+
+#define FLASH_AREA_SCRATCH_OFFSET (FLASH_NV_COUNTERS_AREA_OFFSET + \
+ FLASH_NV_COUNTERS_AREA_SIZE)
+#define FLASH_AREA_SCRATCH_SIZE (0x6e00) /* 27.5 KB */
+#endif /* BL2 */
+
+#define FLASH_AREA_SYSTEM_RESERVED_SIZE (0x30000) /* 192 KB */
+
+
+/* Secure and non-secure images definition in flash area */
+
+#define SECURE_IMAGE_OFFSET 0x0
+
+#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE
+
+#define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + \
+ SECURE_IMAGE_MAX_SIZE)
+
+#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE
+
+/* Check if it fits into available Flash*/
+
+#define FLASH_RESERVED_AREA_SIZE (FLASH_SST_AREA_SIZE + \
+ FLASH_ITS_AREA_SIZE + \
+ FLASH_NV_COUNTERS_AREA_SIZE + \
+ FLASH_AREA_SCRATCH_SIZE + \
+ FLASH_AREA_SYSTEM_RESERVED_SIZE)
+
+#if (FLASH_RESERVED_AREA_OFFSET + FLASH_RESERVED_AREA_SIZE) > (FLASH_TOTAL_SIZE)
+#error "Out of Flash memory"
+#endif
+
+/* Flash device name used by BL2 and SST
+ * Name is defined in flash driver file: Driver_Flash.c
+ */
+#define FLASH_DEV_NAME Driver_FLASH0
+
+/* Secure Storage (SST) Service definitions
+ * Note: Further documentation of these definitions can be found in the
+ * TF-M SST Integration Guide.
+ */
+#define SST_FLASH_DEV_NAME Driver_FLASH0
+
+/* In this target the CMSIS driver requires only the offset from the base
+ * address instead of the full memory address.
+ */
+#define SST_FLASH_AREA_ADDR FLASH_SST_AREA_OFFSET
+/* Dedicated flash area for SST */
+#define SST_FLASH_AREA_SIZE FLASH_SST_AREA_SIZE
+#define SST_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
+/* Number of SST_SECTOR_SIZE per block */
+#define SST_SECTORS_PER_BLOCK 0x8
+/* Specifies the smallest flash programmable unit in bytes */
+#define SST_FLASH_PROGRAM_UNIT 0x1
+/* The maximum asset size to be stored in the SST area */
+#define SST_MAX_ASSET_SIZE 2048
+/* The maximum number of assets to be stored in the SST area */
+#define SST_NUM_ASSETS 10
+
+/* Internal Trusted Storage (ITS) Service definitions
+ * Note: Further documentation of these definitions can be found in the
+ * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is
+ * allocated in the external flash just for development platforms that don't
+ * have internal flash available.
+ */
+#define ITS_FLASH_DEV_NAME Driver_FLASH0
+
+/* In this target the CMSIS driver requires only the offset from the base
+ * address instead of the full memory address.
+ */
+#define ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET
+/* Dedicated flash area for ITS */
+#define ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE
+#define ITS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
+/* Number of ITS_SECTOR_SIZE per block */
+#define ITS_SECTORS_PER_BLOCK (0x8)
+/* Specifies the smallest flash programmable unit in bytes */
+#define ITS_FLASH_PROGRAM_UNIT (0x1)
+/* The maximum asset size to be stored in the ITS area */
+#define ITS_MAX_ASSET_SIZE (512)
+/* The maximum number of assets to be stored in the ITS area */
+#define ITS_NUM_ASSETS (10)
+
+/* NV Counters definitions */
+#define TFM_NV_COUNTERS_AREA_ADDR FLASH_NV_COUNTERS_AREA_OFFSET
+#define TFM_NV_COUNTERS_AREA_SIZE FLASH_NV_COUNTERS_AREA_SIZE
+#define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET
+#define TFM_NV_COUNTERS_SECTOR_SIZE MAX(FLASH_NV_COUNTERS_AREA_SIZE, \
+ FLASH_AREA_IMAGE_SECTOR_SIZE)
+
+/* Use Flash to store Code data */
+#define S_ROM_ALIAS_BASE (0x10000000)
+#define NS_ROM_ALIAS_BASE (0x10000000)
+
+/* Use SRAM to store RW data */
+#define S_RAM_ALIAS_BASE (0x08000000)
+#define NS_RAM_ALIAS_BASE (0x08000000)
+
+#endif /* __FLASH_LAYOUT_H__ */
diff --git a/platform/ext/target/cypress/psoc64/partition/region_defs.h b/platform/ext/target/cypress/psoc64/partition/region_defs.h
new file mode 100644
index 0000000..e5058fd
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/partition/region_defs.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2017-2019 ARM Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __REGION_DEFS_H__
+#define __REGION_DEFS_H__
+
+#include "flash_layout.h"
+
+#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE
+/* 2KB of RAM (at the end of the SRAM) are reserved for system use. Using
+ * this memory region for other purposes will lead to unexpected behavior.
+ * 94KB of RAM (just before the memory reserved for system use) are
+ * allocated and protected by Cypress Bootloader */
+/* FixMe: confirm exact available amount of RAM based on the actual
+ system allocation */
+#define TOTAL_RAM_SIZE (0x000E8000) /* CY_SRAM_SIZE - 96KB */
+
+#define BL2_HEAP_SIZE 0x0001000
+#define BL2_MSP_STACK_SIZE 0x0001000
+
+#define S_HEAP_SIZE 0x0001000
+#define S_MSP_STACK_SIZE_INIT 0x0000400
+#define S_MSP_STACK_SIZE 0x0000800
+#define S_PSP_STACK_SIZE 0x0000800
+
+#define NS_HEAP_SIZE 0x0001000
+#define NS_MSP_STACK_SIZE 0x0000400
+#define NS_PSP_STACK_SIZE 0x0000C00
+
+/* Relocation of vectors to RAM support */
+/* #define RAM_VECTORS_SUPPORT */
+
+/*
+ * This size of buffer is big enough to store an attestation
+ * token produced by initial attestation service
+ */
+#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE 0x250
+
+/*
+ * MPC granularity is 128 KB on AN519 MPS2 FPGA image. Alignment
+ * of partitions is defined in accordance with this constraint.
+ */
+
+#ifdef BL2
+#error "BL2 configuration is not supported"
+#else
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET SECURE_IMAGE_OFFSET
+#define NS_IMAGE_PRIMARY_PARTITION_OFFSET NON_SECURE_IMAGE_OFFSET
+#endif /* BL2 */
+
+/* TFM PSoC6 CY8CKIT_064 RAM layout:
+ *
+ * 0x0800_0000 - 0x0802_FFFF Secure (192KB)
+ * 0x0800_0000 - 0x0800_FFFF Secure unprivileged data (S_UNPRIV_DATA_SIZE, 64KB)
+ * 0x0801_0000 - 0x0802_EFFF Secure priviliged data (S_PRIV_DATA_SIZE, 124KB)
+ * 0x0802_F000 - 0x0802_FFFF Secure priv code executable from RAM (S_RAM_CODE_SIZE, 4KB)
+ *
+ * 0x0803_0000 - 0x080E_7FFF Non-secure (736KB)
+ * 0x0803_0000 - 0x080E_6FFF Non-secure OS/App (732KB)
+ * 0x080E_7000 - 0x080E_7FFF Shared memory (NS_DATA_SHARED_SIZE, 4KB)
+ * 0x080E_8000 - 0x080F_FFFF System reserved memory (96KB)
+ * 0x0810_0000 End of RAM
+ */
+
+/*
+ * Boot partition structure if MCUBoot is used:
+ * 0x0_0000 Bootloader header
+ * 0x0_0400 Image area
+ * 0x1_FC00 Trailer
+ */
+/* Image code size is the space available for the software binary image.
+ * It is less than the FLASH_S_PARTITION_SIZE and FLASH_NS_PARTITION_SIZE
+ * because we reserve space for the image header and trailer introduced by the
+ * bootloader.
+ */
+#ifdef BL2
+#error "BL2 configuration is not supported"
+#else
+/* Even though TFM BL2 is excluded from the build,
+ * CY BL built externally is used and it needs offsets for header and trailer
+ * to be taken in account.
+ * */
+#define BL2_HEADER_SIZE (0x400)
+#define BL2_TRAILER_SIZE (0x400)
+
+#endif /* BL2 */
+
+#define IMAGE_S_CODE_SIZE \
+ (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
+#define IMAGE_NS_CODE_SIZE \
+ (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
+
+/* Alias definitions for secure and non-secure areas*/
+#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x))
+#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
+
+#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x))
+#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x))
+
+/* Secure regions */
+#define S_IMAGE_PRIMARY_AREA_OFFSET \
+ (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
+#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
+#define S_CODE_SIZE IMAGE_S_CODE_SIZE
+#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
+
+#define S_DATA_START (S_RAM_ALIAS(0))
+#define S_UNPRIV_DATA_SIZE 0x10000
+#define S_PRIV_DATA_SIZE 0x1F000
+/* Reserve 4KB for RAM-based executable code */
+#define S_RAM_CODE_SIZE 0x1000
+
+/* Secure data area */
+#define S_DATA_SIZE (S_UNPRIV_DATA_SIZE + S_PRIV_DATA_SIZE + S_RAM_CODE_SIZE)
+#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
+
+/* We need the privileged data area to be aligned so that an SMPU
+ * region can cover it.
+ */
+/* TODO It would be nice to figure this out automatically.
+ * In theory, in the linker script, we could determine the amount
+ * of secure data space available after all the unprivileged data,
+ * round that down to a power of 2 to get the actual size we want
+ * to use for privileged data, and then determine this value from
+ * that. We'd also potentially have to update the configs for SMPU9
+ * and SMPU10.
+ * Leave the SMPU alignment check in SMPU configuration file.
+ */
+#define S_DATA_UNPRIV_OFFSET (0)
+#define S_DATA_UNPRIV_START S_RAM_ALIAS(S_DATA_UNPRIV_OFFSET)
+
+#define S_DATA_PRIV_OFFSET (S_DATA_UNPRIV_OFFSET + S_UNPRIV_DATA_SIZE)
+#define S_DATA_PRIV_START S_RAM_ALIAS(S_DATA_PRIV_OFFSET)
+
+/* Reserve area for RAM-based executable code right after secure unprivilaged
+ * and privilaged data areas*/
+#define S_RAM_CODE_OFFSET (S_DATA_PRIV_OFFSET + S_PRIV_DATA_SIZE)
+#define S_RAM_CODE_START S_RAM_ALIAS(S_RAM_CODE_OFFSET)
+
+/* Non-secure regions */
+#define NS_IMAGE_PRIMARY_AREA_OFFSET \
+ (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
+#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET))
+#define NS_CODE_SIZE IMAGE_NS_CODE_SIZE
+#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
+
+#define NS_DATA_START (S_RAM_ALIAS(S_DATA_SIZE))
+#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE)
+#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1)
+
+/* Shared memory */
+#define NS_DATA_SHARED_SIZE 0x1000
+#define NS_DATA_SHARED_START (NS_DATA_START + NS_DATA_SIZE - \
+ NS_DATA_SHARED_SIZE)
+#define NS_DATA_SHARED_LIMIT (NS_DATA_SHARED_START + NS_DATA_SHARED_SIZE - 1)
+
+/* Shared variables addresses */
+/* ipcWaitMessageStc, cy_flash.c */
+#define IPC_WAIT_MESSAGE_STC_SIZE 4
+#define IPC_WAIT_MESSAGE_STC_ADDR (NS_DATA_SHARED_START + \
+ NS_DATA_SHARED_SIZE - \
+ IPC_WAIT_MESSAGE_STC_SIZE)
+
+/* NS partition information is used for MPC and SAU configuration */
+#define NS_PARTITION_START \
+ (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
+
+#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE)
+
+#ifdef BL2
+#error "BL2 configuration is not supported"
+#endif /* BL2 */
+
+/* Shared data area between bootloader and runtime firmware.
+ * Shared data area is allocated at the beginning of the privileged data area,
+ * it is overlapping with TF-M Secure code's MSP stack
+ */
+#define BOOT_TFM_SHARED_DATA_BASE (S_RAM_ALIAS(S_DATA_PRIV_OFFSET))
+#define BOOT_TFM_SHARED_DATA_SIZE 0x400
+
+#endif /* __REGION_DEFS_H__ */
+
diff --git a/platform/ext/target/cypress/psoc64/pc_config.h b/platform/ext/target/cypress/psoc64/pc_config.h
new file mode 100644
index 0000000..311a1c4
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/pc_config.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __PC_CONFIG_H__
+#define __PC_CONFIG_H__
+
+/* Which PC is used for what */
+/* PC=0 : romboot (CM0+) */
+/* PC=1 : BL2/SPM (CM0+) */
+#define CY_PROT_SPM_DEFAULT CY_PROT_PC1
+/* PC=2 : unused (secure) */
+/* PC=3 : unused (secure) */
+/* PC=4 : unused (non-secure) */
+/* PC=5 : unused (non-secure) */
+/* PC=6 : non-secure code (CM4) */
+#define CY_PROT_HOST_DEFAULT CY_PROT_PC6
+/* PC=7 : Test Controller */
+#define CY_PROT_TC CY_PROT_PC7
+
+#define ONLY_BL2_SPM_MASK CY_PROT_PCMASK1
+#define SECURE_PCS_MASK (CY_PROT_PCMASK1 | CY_PROT_PCMASK2 | CY_PROT_PCMASK3)
+#define HOST_PCS_MASK (CY_PROT_PCMASK4 | CY_PROT_PCMASK5 | CY_PROT_PCMASK6)
+#define TC_PC_MASK CY_PROT_PCMASK7
+#define ALL_PCS_EXCEPT_TC_MASK (CY_PROT_PCMASK1 | CY_PROT_PCMASK2 | CY_PROT_PCMASK3 | \
+ CY_PROT_PCMASK4 | CY_PROT_PCMASK5 | CY_PROT_PCMASK6)
+#define ALL_PCS_MASK (CY_PROT_PCMASK1 | CY_PROT_PCMASK2 | CY_PROT_PCMASK3 | \
+ CY_PROT_PCMASK4 | CY_PROT_PCMASK5 | CY_PROT_PCMASK6 | CY_PROT_PCMASK7)
+#endif /* __PC_CONFIG_H__ */
+
diff --git a/platform/ext/target/cypress/psoc64/ppu_config.h b/platform/ext/target/cypress/psoc64/ppu_config.h
new file mode 100644
index 0000000..4f3bb1c
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/ppu_config.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __PPU_CONFIG_H__
+#define __PPU_CONFIG_H__
+
+/* PPU configs */
+
+/* The majority will be configured in similar ways */
+#define NON_SECURE_READ_ONLY_CONFIG { \
+ .user = CY_PROT_PERM_R, \
+ .priv = CY_PROT_PERM_R, \
+ .secure = false, \
+ .pcMask = ALL_PCS_MASK, \
+}
+#define NON_SECURE_READ_WRITE_CONFIG { \
+ .user = CY_PROT_PERM_RW, \
+ .priv = CY_PROT_PERM_RW, \
+ .secure = false, \
+ .pcMask = ALL_PCS_MASK, \
+}
+#define NON_SECURE_PRIV_ONLY_CONFIG { \
+ .user = CY_PROT_PERM_DISABLED, \
+ .priv = CY_PROT_PERM_RW, \
+ .secure = false, \
+ .pcMask = ALL_PCS_MASK, \
+}
+#define NON_SECURE_EXCEPT_TC_READ_WRITE_CONFIG { \
+ .user = CY_PROT_PERM_RW, \
+ .priv = CY_PROT_PERM_RW, \
+ .secure = false, \
+ .pcMask = ALL_PCS_EXCEPT_TC_MASK, \
+}
+#define SECURE_READ_ONLY_CONFIG { \
+ .user = CY_PROT_PERM_R, \
+ .priv = CY_PROT_PERM_R, \
+ .secure = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SECURE_READ_WRITE_CONFIG { \
+ .user = CY_PROT_PERM_R, \
+ .priv = CY_PROT_PERM_RW, \
+ .secure = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SECURE_PRIV_ONLY_CONFIG { \
+ .user = CY_PROT_PERM_DISABLED, \
+ .priv = CY_PROT_PERM_RW, \
+ .secure = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+
+/* Actual configs for each PPU */
+
+/* To provide a config for a programmable PPU,
+ * use something like this:
+#define PPU_PR7_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_PR7_SLAVE_CONFIG { \
+ .user = CY_PROT_PERM_R, \
+ .priv = CY_PROT_PERM_R, \
+ .secure = true, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define PPU_PR7_SLAVE_ADDRESS CPUSS_BASE
+#define PPU_PR7_SLAVE_REGION_SIZE CY_PROT_SIZE_2KB
+*/
+
+#define PPU_CRYPTO_MAIN_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_CRYPTO_MAIN_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_CRYPTO_CRYPTO_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_CRYPTO_CRYPTO_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_CRYPTO_BOOT_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_CRYPTO_BOOT_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_CRYPTO_KEY0_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_CRYPTO_KEY0_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_CRYPTO_KEY1_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_CRYPTO_KEY1_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#define PPU_CRYPTO_BUF_MASTER_CONFIG NON_SECURE_READ_ONLY_CONFIG
+#define PPU_CRYPTO_BUF_SLAVE_CONFIG SECURE_PRIV_ONLY_CONFIG
+
+#endif /* __PPU_CONFIG_H__ */
diff --git a/platform/ext/target/cypress/psoc64/security/keys/readme.rst b/platform/ext/target/cypress/psoc64/security/keys/readme.rst
new file mode 100644
index 0000000..de80f3d
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/security/keys/readme.rst
@@ -0,0 +1,4 @@
+Signing keys:
+
+MCUBOOT_CM0P_KEY.json - private OEM key for signing CM0P image
+USERAPP_CM4_KEY.json - private OEM key for signing CM4 image
diff --git a/platform/ext/target/cypress/psoc64/security/policy_dual_stage_CM0p_CM4.json b/platform/ext/target/cypress/psoc64/security/policy_dual_stage_CM0p_CM4.json
new file mode 100644
index 0000000..71c539d
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/security/policy_dual_stage_CM0p_CM4.json
@@ -0,0 +1,175 @@
+{
+ "debug" :
+ {
+ "m0p" : {
+ "permission" : "enabled",
+ "control" : "firmware",
+ "key" : 5
+ },
+ "m4" : {
+ "permission" : "allowed",
+ "control" : "firmware",
+ "key" : 5
+ },
+ "system" : {
+ "permission" : "enabled",
+ "control" : "firmware",
+ "key" : 5,
+ "syscall": true,
+ "mmio": true,
+ "flash": true,
+ "workflash": true,
+ "sflash": true,
+ "sram": true
+ },
+ "rma" : {
+ "permission" : "allowed",
+ "destroy_fuses" : [
+ {
+ "start" : 888,
+ "size" : 136
+ },
+ {
+ "start" : 648,
+ "size" : 104
+ }
+ ],
+ "destroy_flash" : [
+ {
+ "start" : 268435456,
+ "size" : 851968
+ },
+ {
+ "start" : 269483520,
+ "size" : 16
+ }
+ ],
+ "key" : 5
+ }
+ },
+ "wounding" :
+ {
+ },
+ "boot_upgrade" :
+ {
+ "firmware": [
+ {
+ "boot_auth": [
+ 3
+ ],
+ "id": 0,
+ "launch": 1,
+ "monotonic": 0,
+ "smif_id": 0,
+ "upgrade": false,
+ "upgrade_auth": [
+ 3
+ ],
+ "upgrade_keys": [
+ { "kid": 3, "key": "./keys/MCUBOOT_CM0P_KEY.json" }
+ ],
+ "backup": false,
+ "resources": [
+ {
+ "type": "FLASH_PC1_SPM",
+ "address": 269287424,
+ "size": 65536
+ },
+ {
+ "type": "SRAM_SPM_PRIV",
+ "address": 134348800,
+ "size": 65536
+ }
+ ]
+ },
+ {
+ "boot_auth": [
+ 6
+ ],
+ "boot_keys": [
+ { "kid": 6, "key": "./keys/MCUBOOT_CM0P_KEY.json" }
+ ],
+ "id": 1,
+ "launch": 16,
+ "monotonic": 0,
+ "smif_id": 0,
+ "version": "0.1",
+ "rollback_counter": 0,
+ "upgrade": false,
+ "encrypt": false,
+ "encrypt_key_id": 1,
+ "upgrade_auth": [
+ 6
+ ],
+ "upgrade_keys": [
+ { "kid": 6, "key": "./keys/MCUBOOT_CM0P_KEY.json" }
+ ],
+ "backup": false,
+ "resources": [
+ {
+ "type": "BOOT",
+ "address": 268959744,
+ "size": 327680
+ },
+ {
+ "type": "UPGRADE",
+ "address": 268730368,
+ "size": 327680
+ }
+ ]
+ },
+ {
+ "boot_auth": [
+ 8
+ ],
+ "boot_keys": [
+ { "kid": 8, "key": "./keys/USERAPP_CM4_KEY.json" }
+ ],
+ "id": 16,
+ "monotonic": 0,
+ "smif_id": 0,
+ "version": "0.1",
+ "rollback_counter": 0,
+ "upgrade": false,
+ "upgrade_auth": [
+ 8
+ ],
+ "upgrade_keys": [
+ { "kid": 8, "key": "./keys/USERAPP_CM4_KEY.json" }
+ ],
+ "backup": false,
+ "resources": [
+ {
+ "type": "BOOT",
+ "address": 268435456,
+ "size": 163840
+ },
+ {
+ "type": "UPGRADE",
+ "address": 268730368,
+ "size": 262144
+ }
+ ]
+ }
+ ],
+ "reprogram": [
+ {
+ "size": 917504,
+ "start": 268435456
+ },
+ {
+ "size": 131072,
+ "start": 268828672
+ }
+ ],
+ "reprovision": {
+ "boot_loader": false,
+ "keys_and_policies": true
+ },
+ "title": "upgrade_policy"
+ },
+ "cy_bootloader":
+ {
+ "mode": "debug"
+ }
+}
diff --git a/platform/ext/target/cypress/psoc64/security/policy_dual_stage_CM0p_CM4_debug_2M.json b/platform/ext/target/cypress/psoc64/security/policy_dual_stage_CM0p_CM4_debug_2M.json
new file mode 100644
index 0000000..4a95235
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/security/policy_dual_stage_CM0p_CM4_debug_2M.json
@@ -0,0 +1,166 @@
+{
+ "debug" :
+ {
+ "m0p" : {
+ "permission" : "enabled",
+ "control" : "firmware",
+ "key" : 5
+ },
+ "m4" : {
+ "permission" : "allowed",
+ "control" : "firmware",
+ "key" : 5
+ },
+ "system" : {
+ "permission" : "enabled",
+ "control" : "firmware",
+ "key" : 5,
+ "syscall": true,
+ "mmio": true,
+ "flash": true,
+ "workflash": true,
+ "sflash": true,
+ "sram": true
+ },
+ "rma" : {
+ "permission" : "allowed",
+ "destroy_fuses" : [
+ {
+ "start" : 888,
+ "size" : 136
+ },
+ {
+ "start" : 648,
+ "size" : 104
+ }
+ ],
+ "destroy_flash" : [
+ {
+ "start" : 268435456,
+ "size" : 851968
+ },
+ {
+ "start" : 269483520,
+ "size" : 16
+ }
+ ],
+ "key" : 5
+ }
+ },
+ "wounding" :
+ {
+ },
+ "boot_upgrade" :
+ {
+ "title": "upgrade_policy",
+ "firmware": [
+ {
+ "boot_auth": [
+ 3
+ ],
+ "id": 0,
+ "launch": 1,
+ "monotonic": 0,
+ "smif_id": 0,
+ "upgrade": false,
+ "upgrade_auth": [
+ 3
+ ],
+ "upgrade_keys": [
+ { "kid": 3, "key": "./keys/MCUBOOT_CM0P_KEY.json" }
+ ],
+ "backup": false,
+ "resources": [
+ {
+ "type": "FLASH_PC1_SPM",
+ "address": 270336000,
+ "size": 65536
+ },
+ {
+ "type": "SRAM_SPM_PRIV",
+ "address": 135004160,
+ "size": 262144
+ },
+ {
+ "type": "SRAM_DAP",
+ "address": 135184384,
+ "size": 16384
+ }
+ ]
+ },
+ {
+ "boot_auth": [
+ 6
+ ],
+ "boot_keys": [
+ { "kid": 6, "key": "./keys/MCUBOOT_CM0P_KEY.json" }
+ ],
+ "id": 1,
+ "launch": 16,
+ "monotonic": 0,
+ "smif_id": 0,
+ "version": "0.1",
+ "rollback_counter": 0,
+ "upgrade": false,
+ "encrypt": false,
+ "encrypt_key_id": 1,
+ "upgrade_auth": [
+ 6
+ ],
+ "upgrade_keys": [
+ { "kid": 6, "key": "./keys/MCUBOOT_CM0P_KEY.json" }
+ ],
+ "backup": false,
+ "resources": [
+ {
+ "type": "BOOT",
+ "address": 268435456,
+ "size": 327680
+ },
+ {
+ "type": "UPGRADE",
+ "address": 269942784,
+ "size": 327680
+ }
+ ]
+ },
+ {
+ "boot_auth": [
+ 8
+ ],
+ "boot_keys": [
+ { "kid": 8, "key": "./keys/USERAPP_CM4_KEY.json" }
+ ],
+ "id": 16,
+ "monotonic": 0,
+ "smif_id": 0,
+ "version": "0.1",
+ "rollback_counter": 0,
+ "upgrade": false,
+ "upgrade_auth": [
+ 8
+ ],
+ "upgrade_keys": [
+ { "kid": 8, "key": "./keys/USERAPP_CM4_KEY.json" }
+ ],
+ "backup": false,
+ "resources": [
+ {
+ "type": "BOOT",
+ "address": 268763136,
+ "size": 1179648
+ },
+ {
+ "type": "UPGRADE",
+ "address": 268763136,
+ "size": 1179648
+ }
+ ]
+ }
+ ]
+ },
+ "cy_bootloader":
+ {
+ "mode": "debug"
+ }
+}
diff --git a/platform/ext/target/cypress/psoc64/security/sign.py b/platform/ext/target/cypress/psoc64/security/sign.py
new file mode 100755
index 0000000..187d67c
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/security/sign.py
@@ -0,0 +1,48 @@
+#!/usr/bin/python3
+"""
+Copyright (c) 2019 Cypress Semiconductor Corporation
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import cysecuretools
+import sys, getopt
+
+def main(argv):
+ s_hex_file=""
+ ns_hex_file=""
+ policy_file=""
+ try:
+ opts, args = getopt.getopt(argv,"hs:n:p:", ["s_hex=", "ns_hex=", "policy="])
+ except getopt.GetoptError:
+ print ('sign.py -s <tfm_s hex> -n <tfm_ns hex> -p <policy json>')
+ sys.exit(2)
+ for opt, arg in opts:
+ if opt == '-h':
+ print ('sign.py -s <tfm_s hex> -n <tfm_ns hex> -p <policy json>')
+ sys.exit()
+ elif opt in ("-s", "--s_hex"):
+ s_hex_file = arg
+ elif opt in ("-n", "--ns_hex"):
+ ns_hex_file = arg
+ elif opt in ("-p", "--policy"):
+ policy_file = arg
+ print ('tfm_s :', s_hex_file)
+ print ('tfm_ns:', ns_hex_file)
+ print ('policy:', policy_file)
+
+ cysecuretools.sign_image(s_hex_file, policy_file, 1);
+ cysecuretools.sign_image(ns_hex_file, policy_file, 16);
+
+if __name__ == "__main__":
+ main(sys.argv[1:])
diff --git a/platform/ext/target/cypress/psoc64/services/src/tfm_platform_system.c b/platform/ext/target/cypress/psoc64/services/src/tfm_platform_system.c
new file mode 100644
index 0000000..1d8c97a
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/services/src/tfm_platform_system.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "platform/include/tfm_platform_system.h"
+#include "platform_description.h"
+
+void tfm_platform_hal_system_reset(void)
+{
+ /* Reset the system */
+ NVIC_SystemReset();
+}
+
+enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request,
+ psa_invec *in_vec,
+ psa_outvec *out_vec)
+{
+ (void)in_vec;
+ (void)out_vec;
+ /* SCC is configured as non-secure through PPC,
+ * so this function is not needed on this platform
+ */
+ return TFM_PLATFORM_ERR_NOT_SUPPORTED;
+}
+
diff --git a/platform/ext/target/cypress/psoc64/smpu_config.h b/platform/ext/target/cypress/psoc64/smpu_config.h
new file mode 100644
index 0000000..db77e16
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/smpu_config.h
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SMPU_CONFIG_H__
+#define __SMPU_CONFIG_H__
+
+#include "flash_layout.h"
+#include "region_defs.h"
+
+#include "cy_prot.h"
+
+/* This macro depends on the actual CY_PROT_REGIONSIZE_XXX values */
+#define REGIONSIZE_TO_BYTES(X) (1UL << (1 + (X)))
+
+/* The actual SMPU configs */
+
+/* SMPU configs can only be changed by privileged secure PC=1 bus masters */
+#define COMMON_SMPU_MASTER_CONFIG {\
+ .userPermission = CY_PROT_PERM_R, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = ONLY_BL2_SPM_MASK, \
+}
+
+/* SMPU0 - secure primary image in Flash */
+#define SMPU0_BASE S_ROM_ALIAS(SECURE_IMAGE_OFFSET)
+#define SMPU0_REGIONSIZE PROT_SIZE_512KB_BIT_SHIFT
+#define SMPU0_SUBREGION_DIS (CY_PROT_SUBREGION_DIS5 | \
+ CY_PROT_SUBREGION_DIS6 | \
+ CY_PROT_SUBREGION_DIS7)
+#define SMPU0_SLAVE_CONFIG {\
+ .address = (void *)SMPU0_BASE, \
+ .regionSize = SMPU0_REGIONSIZE, \
+ .subregions = SMPU0_SUBREGION_DIS, \
+ .userPermission = CY_PROT_PERM_RWX, \
+ .privPermission = CY_PROT_PERM_RWX, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SMPU0_MASTER_CONFIG COMMON_SMPU_MASTER_CONFIG
+
+/* SMPU requires base address aligned to size */
+#if SMPU0_BASE % REGIONSIZE_TO_BYTES(SMPU0_REGIONSIZE)
+#error "Flash layout has changed - SMPU0 needs updating"
+#endif
+
+/*
+ * SMPU0 protected area should be exactly the size of the secure primary image
+ */
+#if FLASH_S_PARTITION_SIZE != (5 * REGIONSIZE_TO_BYTES(SMPU0_REGIONSIZE)/8)
+#error "Flash layout has changed - FLASH_S_PARTITION_SIZE isn't 5/8 of SMPU0_REGIONSIZE"
+#endif
+
+/* SMPU1 - start of secondary images in Flash */
+#define SMPU1_BASE S_ROM_ALIAS(NON_SECURE_IMAGE_OFFSET + \
+ NON_SECURE_IMAGE_MAX_SIZE)
+#define SMPU1_REGIONSIZE PROT_SIZE_64KB_BIT_SHIFT
+#define SMPU1_SLAVE_CONFIG {\
+ .address = (void *)SMPU1_BASE, \
+ .regionSize = SMPU1_REGIONSIZE, \
+ .subregions = ALL_ENABLED, \
+ .userPermission = CY_PROT_PERM_RW, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SMPU1_MASTER_CONFIG COMMON_SMPU_MASTER_CONFIG
+
+/* SMPU requires base address aligned to size */
+#if SMPU1_BASE % REGIONSIZE_TO_BYTES(SMPU1_REGIONSIZE)
+#error "Flash layout has changed - SMPU1 needs updating"
+#endif
+
+/* SMPU2 - remainder of secondary images, plus secure storage, NV counters,
+ * and unused space in Flash
+ */
+/* SMPU2 should start immediately after SMPU1 */
+#define SMPU2_BASE (SMPU1_BASE + REGIONSIZE_TO_BYTES(SMPU1_REGIONSIZE))
+#define SMPU2_REGIONSIZE PROT_SIZE_512KB_BIT_SHIFT
+#define SMPU2_SLAVE_CONFIG {\
+ .address = (void *)SMPU2_BASE, \
+ .regionSize = SMPU2_REGIONSIZE, \
+ .subregions = ALL_ENABLED, \
+ .userPermission = CY_PROT_PERM_RW, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SMPU2_MASTER_CONFIG COMMON_SMPU_MASTER_CONFIG
+
+/* SMPU requires base address aligned to size */
+#if SMPU2_BASE % REGIONSIZE_TO_BYTES(SMPU2_REGIONSIZE)
+#error "Flash layout has changed - SMPU2 needs updating"
+#endif
+
+/* SMPU6 - 64KB of unprivileged secure data in SRAM */
+#define SMPU6_BASE S_DATA_START
+#define SMPU6_REGIONSIZE PROT_SIZE_64KB_BIT_SHIFT
+#define SMPU6_SLAVE_CONFIG {\
+ .address = (void *)SMPU6_BASE, \
+ .regionSize = SMPU6_REGIONSIZE, \
+ .subregions = ALL_ENABLED, \
+ .userPermission = CY_PROT_PERM_RW, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SMPU6_MASTER_CONFIG COMMON_SMPU_MASTER_CONFIG
+
+/* SMPU requires base address aligned to size */
+#if SMPU6_BASE % REGIONSIZE_TO_BYTES(SMPU6_REGIONSIZE)
+#error "Flash layout has changed - SMPU6 needs updating"
+#endif
+
+/* S_DATA_PRIV_START must not overlap with SMPU6 region */
+#if S_DATA_PRIV_START < (SMPU6_BASE + REGIONSIZE_TO_BYTES(SMPU6_REGIONSIZE))
+#error "S_DATA_PRIV_START overlaps with unprivileged data section"
+#endif
+
+/* SMPU7 - 96KB of privileged secure data at S_DATA_PRIV_START in SRAM */
+#define SMPU7_BASE S_RAM_ALIAS(0)
+#define SMPU7_REGIONSIZE PROT_SIZE_256KB_BIT_SHIFT
+#define SMPU7_SUBREGION_DIS (CY_PROT_SUBREGION_DIS0 | \
+ CY_PROT_SUBREGION_DIS1 | \
+ CY_PROT_SUBREGION_DIS6 | \
+ CY_PROT_SUBREGION_DIS7)
+#define SMPU7_SLAVE_CONFIG {\
+ .address = (void *)SMPU7_BASE, \
+ .regionSize = SMPU7_REGIONSIZE, \
+ .subregions = SMPU7_SUBREGION_DIS, \
+ .userPermission = CY_PROT_PERM_DISABLED, \
+ .privPermission = CY_PROT_PERM_RW, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SMPU7_MASTER_CONFIG COMMON_SMPU_MASTER_CONFIG
+
+/* SMPU requires base address aligned to size */
+#if SMPU7_BASE % REGIONSIZE_TO_BYTES(SMPU7_REGIONSIZE)
+#error "Flash layout has changed - SMPU7 needs updating"
+#endif
+
+/*
+ * S_DATA_PRIV_START must equal the base address of subregion 2 of
+ * SMPU7
+ */
+#if S_DATA_PRIV_START != (SMPU7_BASE + \
+ (2 * REGIONSIZE_TO_BYTES(SMPU7_REGIONSIZE) / 8))
+#error "Flash layout has changed - S_DATA_PRIV_START isn't subregion 2 of SMPU7"
+#endif
+
+/* SMPUs 6 and 7 should cover the whole secure data area in the RAM */
+#if S_DATA_SIZE != (REGIONSIZE_TO_BYTES(SMPU6_REGIONSIZE) + \
+ 4*REGIONSIZE_TO_BYTES(SMPU7_REGIONSIZE)/8)
+#error "Flash layout has changed - SMPU6/SMPU7 config needs updating"
+#endif
+
+/* SMPU10 - 4KB of privileged executable data in SRAM
+ * Note: Region resides in subregion 4 of SMPU 7*/
+#define SMPU10_BASE S_RAM_CODE_START
+#define SMPU10_REGIONSIZE PROT_SIZE_4KB_BIT_SHIFT
+#define SMPU10_SLAVE_CONFIG {\
+ .address = (void *)SMPU10_BASE, \
+ .regionSize = SMPU10_REGIONSIZE, \
+ .subregions = ALL_ENABLED, \
+ .userPermission = CY_PROT_PERM_DISABLED, \
+ .privPermission = CY_PROT_PERM_RX, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SMPU10_MASTER_CONFIG COMMON_SMPU_MASTER_CONFIG
+
+/* SMPU requires base address aligned to size */
+#if SMPU10_BASE % REGIONSIZE_TO_BYTES(SMPU10_REGIONSIZE)
+#error "Flash layout has changed - SMPU10 needs updating"
+#endif
+
+#if S_RAM_CODE_SIZE != REGIONSIZE_TO_BYTES(SMPU10_REGIONSIZE)
+#error "SMPU10_REGIONSIZE is not equal S_RAM_CODE_SIZE"
+#endif
+
+/* SMPU10 should be contained within SMPU7 */
+#if (SMPU10_BASE + SMPU10_REGIONSIZE) < (SMPU7_BASE + \
+ 2*REGIONSIZE_TO_BYTES(SMPU7_REGIONSIZE)/8)
+#error "SMPU10 is below SMPU7"
+#endif
+#if SMPU10_BASE > (SMPU7_BASE + \
+ 6*REGIONSIZE_TO_BYTES(SMPU7_REGIONSIZE)/8)
+#error "SMPU10 is above SMPU7"
+#endif
+
+#endif /* __SMPU_CONFIG_H__ */
diff --git a/platform/ext/target/cypress/psoc64/spm_hal.c b/platform/ext/target/cypress/psoc64/spm_hal.c
new file mode 100644
index 0000000..a487576
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/spm_hal.c
@@ -0,0 +1,415 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "platform/include/tfm_spm_hal.h"
+
+#include "region_defs.h"
+#include "secure_utilities.h"
+#include "spe_ipc_config.h"
+#include "spm_api.h"
+#include "spm_db.h"
+#include "target_cfg.h"
+#include "tfm_multi_core.h"
+#include "tfm_platform_core_api.h"
+
+#include "cycfg.h"
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_ipc_drv.h"
+#include "cy_prot.h"
+#include "cy_sysint.h"
+#include "pc_config.h"
+
+/* Get address of memory regions to configure MPU */
+extern const struct memory_region_limits memory_regions;
+
+enum tfm_plat_err_t tfm_spm_hal_init_isolation_hw(void)
+{
+ smpu_init_cfg();
+ ppu_init_cfg();
+ bus_masters_cfg();
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+void tfm_spm_hal_configure_default_isolation(
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ printf("In %s()\n", __func__);
+ if (platform_data) {
+ /* TBD */
+ }
+}
+
+#if TFM_LVL != 1
+
+#define MPU_REGION_TFM_UNPRIV_CODE 1
+#define MPU_REGION_TFM_UNPRIV_DATA 2
+#define MPU_REGION_NS_DATA 3
+#define PARTITION_REGION_RO 4
+#define PARTITION_REGION_RW_STACK 5
+#define PARTITION_REGION_PERIPH 6
+#define PARTITION_REGION_SHARE 7
+
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
+
+static enum spm_err_t tfm_spm_mpu_init(void)
+{
+#if 0
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_armv8m_clean(&dev_mpu_s);
+
+ /* TFM Core unprivileged code region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_CODE;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged data region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_DATA;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged non-secure data region */
+ region_cfg.region_nr = MPU_REGION_NS_DATA;
+ region_cfg.region_base = NS_DATA_START;
+ region_cfg.region_limit = NS_DATA_LIMIT;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+#endif
+
+ return SPM_ERR_OK;
+}
+
+enum spm_err_t tfm_spm_hal_partition_sandbox_config(
+ const struct tfm_spm_partition_memory_data_t *memory_data,
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+#if 0
+ /* This function takes a partition id and enables the
+ * SPM partition for that partition
+ */
+
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_armv8m_disable(&dev_mpu_s);
+
+ /* Configure Regions */
+ if (memory_data->ro_start) {
+ /* RO region */
+ region_cfg.region_nr = PARTITION_REGION_RO;
+ region_cfg.region_base = memory_data->ro_start;
+ region_cfg.region_limit = memory_data->ro_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
+ != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+ }
+
+ /* RW, ZI and stack as one region */
+ region_cfg.region_nr = PARTITION_REGION_RW_STACK;
+ region_cfg.region_base = memory_data->rw_start;
+ region_cfg.region_limit = memory_data->stack_top;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ if (platform_data) {
+ /* Peripheral */
+ region_cfg.region_nr = PARTITION_REGION_PERIPH;
+ region_cfg.region_base = platform_data->periph_start;
+ region_cfg.region_limit = platform_data->periph_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
+ != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ ppc_en_secure_unpriv(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+#endif
+
+ return SPM_ERR_OK;
+}
+
+enum tfm_plat_err_t tfm_spm_hal_setup_isolation_hw(void)
+{
+ if (tfm_spm_mpu_init() != SPM_ERR_OK) {
+ ERROR_MSG("Failed to set up initial MPU configuration! Halting.");
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+#endif /* TFM_LVL != 1 */
+
+uint32_t tfm_spm_hal_get_ns_VTOR(void)
+{
+ return memory_regions.non_secure_code_start;
+}
+
+uint32_t tfm_spm_hal_get_ns_MSP(void)
+{
+ return *((uint32_t *)memory_regions.non_secure_code_start);
+}
+
+uint32_t tfm_spm_hal_get_ns_entry_point(void)
+{
+ return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
+}
+
+void tfm_spm_hal_boot_ns_cpu(uintptr_t start_addr)
+{
+ printf("Starting Cortex-M4 at 0x%x\r\n", start_addr);
+ Cy_SysEnableCM4(start_addr);
+}
+
+void tfm_spm_hal_wait_for_ns_cpu_ready(void)
+{
+ uint32_t data;
+ cy_en_ipcdrv_status_t status;
+
+ Cy_IPC_Drv_SetInterruptMask(Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT),
+ 0, IPC_RX_INT_MASK);
+
+ status = Cy_IPC_Drv_SendMsgWord(Cy_IPC_Drv_GetIpcBaseAddress(IPC_TX_CHAN),
+ IPC_TX_NOTIFY_MASK, IPC_SYNC_MAGIC);
+ while (1)
+ {
+ status = Cy_IPC_Drv_GetInterruptStatusMasked(
+ Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT));
+ status >>= CY_IPC_NOTIFY_SHIFT;
+ if (status & IPC_RX_INT_MASK) {
+ Cy_IPC_Drv_ClearInterrupt(Cy_IPC_Drv_GetIntrBaseAddr(
+ IPC_RX_INTR_STRUCT),
+ 0, IPC_RX_INT_MASK);
+
+ status = Cy_IPC_Drv_ReadMsgWord(Cy_IPC_Drv_GetIpcBaseAddress(
+ IPC_RX_CHAN),
+ &data);
+ if (status == CY_IPC_DRV_SUCCESS) {
+ Cy_IPC_Drv_ReleaseNotify(Cy_IPC_Drv_GetIpcBaseAddress(IPC_RX_CHAN),
+ IPC_RX_RELEASE_MASK);
+ if (data == ~IPC_SYNC_MAGIC) {
+ printf("Cores sync success.\r\n");
+ break;
+ }
+ }
+ }
+ }
+}
+
+enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line,
+ uint32_t priority)
+{
+ uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
+ NVIC_SetPriority(irq_line, quantized_priority);
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+void tfm_spm_hal_get_mem_security_attr(const void *p, size_t s,
+ struct security_attr_info_t *p_attr)
+{
+ /*
+ * FIXME
+ * Need to check if the memory region is valid according to platform
+ * specific memory mapping.
+ */
+
+ /*
+ * TODO
+ * Currently only check static memory region layout to get security
+ * information.
+ * Check of hardware SMPU configuration can be added.
+ */
+ tfm_get_mem_region_security_attr(p, s, p_attr);
+}
+
+void tfm_spm_hal_get_secure_access_attr(const void *p, size_t s,
+ struct mem_attr_info_t *p_attr)
+{
+ uint32_t pc;
+
+ /*
+ * FIXME
+ * Need to check if the memory region is valid according to platform
+ * specific memory mapping.
+ */
+
+ /*
+ * TODO
+ * Currently only check static memory region layout to get attributes.
+ * Check of secure memory protection configuration from hardware can be
+ * added.
+ */
+ tfm_get_secure_mem_region_attr(p, s, p_attr);
+
+ pc = Cy_Prot_GetActivePC(CPUSS_MS_ID_CM0);
+ /* Check whether the current active PC is configured as the expected one .*/
+ if (pc == CY_PROT_SPM_DEFAULT) {
+ p_attr->is_mpu_enabled = true;
+ } else {
+ p_attr->is_mpu_enabled = false;
+ }
+}
+
+void tfm_spm_hal_get_ns_access_attr(const void *p, size_t s,
+ struct mem_attr_info_t *p_attr)
+{
+ /*
+ * FIXME
+ * Need to check if the memory region is valid according to platform
+ * specific memory mapping.
+ */
+
+ /*
+ * TODO
+ * Currently only check static memory region layout to get attributes.
+ * Check of non-secure memory protection configuration from hardware can be
+ * added.
+ */
+ tfm_get_ns_mem_region_attr(p, s, p_attr);
+}
+
+enum tfm_plat_err_t tfm_spm_hal_nvic_interrupt_enable(void)
+{
+ return nvic_interrupt_enable();
+}
+
+void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+{
+ (void)irq_line;
+}
+
+void tfm_spm_hal_enable_irq(int32_t irq_line)
+{
+ (void)irq_line;
+}
+
+void tfm_spm_hal_disable_irq(int32_t irq_line)
+{
+ (void)irq_line;
+}
+
+enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
+ int32_t irq_line,
+ enum irq_target_state_t target_state)
+{
+ (void)irq_line;
+ (void)target_state;
+
+ return TFM_IRQ_TARGET_STATE_SECURE;
+}
+
+enum tfm_plat_err_t tfm_spm_hal_nvic_interrupt_target_state_cfg(void)
+{
+ return nvic_interrupt_target_state_cfg();
+}
+
+enum tfm_plat_err_t tfm_spm_hal_enable_fault_handlers(void)
+{
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_spm_hal_system_reset_cfg(void)
+{
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_spm_hal_init_debug(void)
+{
+ printf("%s()\n", __func__);
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+/* FIXME:
+ * Instead of TFM-customized mcuboot, at this moment psoc64 uses
+ * Cypress version of it - CypressBootloader (CYBL). CYBL doesn't
+ * populate BOOT_TFM_SHARED_DATA.
+ * As a temp workaround, mock mcuboot shared data to pass
+ * initialization checks.
+*/
+void mock_tfm_shared_data(void)
+{
+ const uint32_t mock_data[] = {
+ 0x00D92016, 0x00071103, 0x00455053, 0x30000911,
+ 0x302E302E, 0x00081102, 0x00000000, 0x00241108,
+ 0x6C170A97, 0x5645665E, 0xDB6E2BA6, 0xA4FF4D74,
+ 0xFD34D7DB, 0x67449A82, 0x75FD0930, 0xAA15A9F9,
+ 0x000A1109, 0x32414853, 0x11013635, 0xE6BF0024,
+ 0x26886FD8, 0xFB97FFF4, 0xFBE6C496, 0x463E99C4,
+ 0x5D56FC19, 0x34DF6AA2, 0x9A4829C3, 0x114338DC,
+ 0x534E0008, 0x11404550, 0x2E300009, 0x42302E30,
+ 0x00000811, 0x48000000, 0x7E002411, 0x5FD9229A,
+ 0xE9672A5F, 0x31AAE1EA, 0x8514D772, 0x7F3B26BC,
+ 0x2C7EF27A, 0x9C6047D2, 0x4937BB9F, 0x53000A11,
+ 0x35324148, 0x24114136, 0xCA60B300, 0x6B8CC9F5,
+ 0x82482A94, 0x23489DFA, 0xA966B1EF, 0x4A6E6AEF,
+ 0x19197CA3, 0xC0CC1FED, 0x00000049, 0x00000000
+ };
+ uint32_t *boot_data = (uint32_t*)BOOT_TFM_SHARED_DATA_BASE;
+ memcpy(boot_data, mock_data, sizeof(mock_data));
+}
+
+enum tfm_plat_err_t tfm_spm_hal_post_init_platform(void)
+{
+ platform_init();
+
+ /* FIXME: Use the actual data from mcuboot */
+ mock_tfm_shared_data();
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
diff --git a/platform/ext/target/cypress/psoc64/target_cfg.c b/platform/ext/target/cypress/psoc64/target_cfg.c
new file mode 100644
index 0000000..6292560
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/target_cfg.c
@@ -0,0 +1,2127 @@
+/*
+ * Copyright (c) 2018 Arm Limited
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <assert.h>
+#include <stdio.h> /* for debugging printfs */
+#include "cy_prot.h"
+#include "cycfg.h"
+#include "device_definition.h"
+#include "driver_ppu.h"
+#include "driver_smpu.h"
+#include "pc_config.h"
+#include "platform_description.h"
+#include "region_defs.h"
+#include "RTE_Device.h"
+#include "target_cfg.h"
+#include "tfm_plat_defs.h"
+
+
+/* Macros to pick linker symbols */
+#define REGION(a, b, c) a##b##c
+#define REGION_NAME(a, b, c) REGION(a, b, c)
+#define REGION_DECLARE(a, b, c) extern uint32_t REGION_NAME(a, b, c)
+
+/* The section names come from the scatter file */
+REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
+#ifdef BL2
+REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
+#endif /* BL2 */
+
+const struct memory_region_limits memory_regions = {
+ .non_secure_code_start =
+ (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
+ BL2_HEADER_SIZE,
+
+ .non_secure_partition_base =
+ (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base),
+
+ .non_secure_partition_limit =
+ (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
+ NS_PARTITION_SIZE - 1,
+};
+
+
+#ifdef BL2
+REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
+#endif /* BL2 */
+
+/* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field,
+ * otherwise the processor ignores the write.
+ */
+#define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos))
+
+struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart = {
+ SCB5_BASE,
+ SCB5_BASE + 0xFFF,
+ -1,
+ -1
+};
+
+void enable_fault_handlers(void)
+{
+ /* Fault handles enable registers are not present in Cortex-M0+ */
+}
+
+void system_reset_cfg(void)
+{
+ uint32_t reg_value = SCB->AIRCR;
+
+ /* Clear SCB_AIRCR_VECTKEY value */
+ reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk);
+
+ /* Set Access Key (0x05FA must be written to this field) */
+ reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK);
+
+ SCB->AIRCR = reg_value;
+}
+
+extern void Cy_Platform_Init(void);
+void platform_init(void)
+{
+ Cy_PDL_Init(CY_DEVICE_CFG);
+
+ init_cycfg_all();
+ Cy_Platform_Init();
+
+ /* make sure CM4 is disabled */
+ if (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status()) {
+ Cy_SysDisableCM4();
+ }
+}
+
+enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void)
+{
+ printf("%s()\n", __func__);
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t nvic_interrupt_enable(void)
+{
+ /* PPU and SMPU don't generate interrupts.
+ * USART and Flash drivers don't export an EnableInterrupt function.
+ * So there's nothing to do here.
+ */
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+static cy_en_prot_status_t set_bus_master_attr(void)
+{
+ cy_en_prot_status_t ret;
+
+ printf("%s()\n", __func__);
+
+ /* Cortex-M4 - PC=6 */
+ ret = Cy_Prot_SetActivePC(CPUSS_MS_ID_CM4, CY_PROT_HOST_DEFAULT);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+
+ /* Test Controller - PC=7 */
+ ret = Cy_Prot_SetActivePC(CPUSS_MS_ID_TC, CY_PROT_TC);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+
+ /* Cortex-M0+ - PC=1 */
+ ret = Cy_Prot_SetActivePC(CPUSS_MS_ID_CM0, CY_PROT_SPM_DEFAULT);
+ if (ret != CY_PROT_SUCCESS) {
+ return ret;
+ }
+
+ return CY_PROT_SUCCESS;
+}
+
+void bus_masters_cfg(void)
+{
+ cy_en_prot_status_t ret = set_bus_master_attr();
+ if (ret) {
+ printf("set_bus_master_attr() returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+}
+
+void smpu_init_cfg(void)
+{
+ cy_en_prot_status_t ret;
+
+ printf("%s()\n", __func__);
+
+ printf("memory_regions.non_secure_code_start = %#x\n", memory_regions.non_secure_code_start);
+ printf("memory_regions.non_secure_partition_base = %#x\n", memory_regions.non_secure_partition_base);
+ printf("memory_regions.non_secure_partition_limit = %#x\n", memory_regions.non_secure_partition_limit);
+
+#if RTE_SMPU13
+ ret = SMPU_Configure(&SMPU13_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU13) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU12
+ ret = SMPU_Configure(&SMPU12_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU12) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU11
+ ret = SMPU_Configure(&SMPU11_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU11) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU10
+ ret = SMPU_Configure(&SMPU10_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU10) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU9
+ ret = SMPU_Configure(&SMPU9_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU9) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU8
+ ret = SMPU_Configure(&SMPU8_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU8) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU7
+ ret = SMPU_Configure(&SMPU7_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU7) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU6
+ ret = SMPU_Configure(&SMPU6_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU6) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU5
+ ret = SMPU_Configure(&SMPU5_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU5) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU4
+ ret = SMPU_Configure(&SMPU4_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU4) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU3
+ ret = SMPU_Configure(&SMPU3_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU3) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU2
+ ret = SMPU_Configure(&SMPU2_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU2) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU1
+ ret = SMPU_Configure(&SMPU1_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU1) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+#if RTE_SMPU0
+ ret = SMPU_Configure(&SMPU0_Resources);
+ if (ret) {
+ printf("SMPU_Configure(SMPU0) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+ /* Now protect all unconfigured SMPUs */
+ ret = protect_unconfigured_smpus();
+ if (ret) {
+ printf("protect_unconfigured_smpus() returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+
+ __DSB();
+ __ISB();
+}
+
+void ppu_init_cfg(void)
+{
+ cy_en_prot_status_t ret;
+ (void)ret;
+
+ printf("%s()\n", __func__);
+
+#if RTE_MS_PPU_PR7
+ ret = PPU_Configure(&PR7_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PR7_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PERI_MAIN
+ ret = PPU_Configure(&PERI_MAIN_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PERI_MAIN_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PERI_GR0_GROUP
+ ret = PPU_Configure(&PERI_GR0_GROUP_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PERI_GR0_GROUP_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PERI_GR1_GROUP
+ ret = PPU_Configure(&PERI_GR1_GROUP_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PERI_GR1_GROUP_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PERI_GR2_GROUP
+ ret = PPU_Configure(&PERI_GR2_GROUP_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PERI_GR2_GROUP_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PERI_GR3_GROUP
+ ret = PPU_Configure(&PERI_GR3_GROUP_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PERI_GR3_GROUP_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PERI_GR4_GROUP
+ ret = PPU_Configure(&PERI_GR4_GROUP_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PERI_GR4_GROUP_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PERI_GR6_GROUP
+ ret = PPU_Configure(&PERI_GR6_GROUP_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PERI_GR6_GROUP_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PERI_GR9_GROUP
+ ret = PPU_Configure(&PERI_GR9_GROUP_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PERI_GR9_GROUP_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PERI_GR10_GROUP
+ ret = PPU_Configure(&PERI_GR10_GROUP_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PERI_GR10_GROUP_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PERI_TR
+ ret = PPU_Configure(&PERI_TR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PERI_TR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_CRYPTO_MAIN
+ ret = PPU_Configure(&CRYPTO_MAIN_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&CRYPTO_MAIN_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_CRYPTO_CRYPTO
+ ret = PPU_Configure(&CRYPTO_CRYPTO_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&CRYPTO_CRYPTO_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_CRYPTO_BOOT
+ ret = PPU_Configure(&CRYPTO_BOOT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&CRYPTO_BOOT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_CRYPTO_KEY0
+ ret = PPU_Configure(&CRYPTO_KEY0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&CRYPTO_KEY0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_CRYPTO_KEY1
+ ret = PPU_Configure(&CRYPTO_KEY1_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&CRYPTO_KEY1_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_CRYPTO_BUF
+ ret = PPU_Configure(&CRYPTO_BUF_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&CRYPTO_BUF_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_CPUSS_CM4
+ ret = PPU_Configure(&CPUSS_CM4_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&CPUSS_CM4_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_CPUSS_CM0
+ ret = PPU_Configure(&CPUSS_CM0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&CPUSS_CM0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_CPUSS_BOOT
+ ret = PPU_Configure(&CPUSS_BOOT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&CPUSS_BOOT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_CPUSS_CM0_INT
+ ret = PPU_Configure(&CPUSS_CM0_INT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&CPUSS_CM0_INT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_CPUSS_CM4_INT
+ ret = PPU_Configure(&CPUSS_CM4_INT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&CPUSS_CM4_INT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FAULT_STRUCT0_MAIN
+ ret = PPU_Configure(&FAULT_STRUCT0_MAIN_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FAULT_STRUCT0_MAIN_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FAULT_STRUCT1_MAIN
+ ret = PPU_Configure(&FAULT_STRUCT1_MAIN_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FAULT_STRUCT1_MAIN_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT0_IPC
+ ret = PPU_Configure(&IPC_STRUCT0_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT0_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT1_IPC
+ ret = PPU_Configure(&IPC_STRUCT1_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT1_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT2_IPC
+ ret = PPU_Configure(&IPC_STRUCT2_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT2_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT3_IPC
+ ret = PPU_Configure(&IPC_STRUCT3_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT3_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT4_IPC
+ ret = PPU_Configure(&IPC_STRUCT4_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT4_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT5_IPC
+ ret = PPU_Configure(&IPC_STRUCT5_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT5_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT6_IPC
+ ret = PPU_Configure(&IPC_STRUCT6_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT6_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT7_IPC
+ ret = PPU_Configure(&IPC_STRUCT7_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT7_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT8_IPC
+ ret = PPU_Configure(&IPC_STRUCT8_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT8_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT9_IPC
+ ret = PPU_Configure(&IPC_STRUCT9_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT9_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT10_IPC
+ ret = PPU_Configure(&IPC_STRUCT10_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT10_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT11_IPC
+ ret = PPU_Configure(&IPC_STRUCT11_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT11_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT12_IPC
+ ret = PPU_Configure(&IPC_STRUCT12_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT12_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT13_IPC
+ ret = PPU_Configure(&IPC_STRUCT13_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT13_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT14_IPC
+ ret = PPU_Configure(&IPC_STRUCT14_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT14_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_STRUCT15_IPC
+ ret = PPU_Configure(&IPC_STRUCT15_IPC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_STRUCT15_IPC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT0_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT0_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT0_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT1_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT1_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT1_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT2_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT2_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT2_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT3_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT3_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT3_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT4_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT4_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT4_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT5_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT5_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT5_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT6_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT6_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT6_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT7_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT7_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT7_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT8_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT8_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT8_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT9_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT9_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT9_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT10_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT10_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT10_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT11_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT11_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT11_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT12_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT12_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT12_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT13_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT13_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT13_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT14_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT14_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT14_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_IPC_INTR_STRUCT15_INTR
+ ret = PPU_Configure(&IPC_INTR_STRUCT15_INTR_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&IPC_INTR_STRUCT15_INTR_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PROT_SMPU_MAIN
+ ret = PPU_Configure(&PROT_SMPU_MAIN_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PROT_SMPU_MAIN_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PROT_MPU0_MAIN
+ ret = PPU_Configure(&PROT_MPU0_MAIN_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PROT_MPU0_MAIN_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PROT_MPU5_MAIN
+ ret = PPU_Configure(&PROT_MPU5_MAIN_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PROT_MPU5_MAIN_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PROT_MPU6_MAIN
+ ret = PPU_Configure(&PROT_MPU6_MAIN_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PROT_MPU6_MAIN_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PROT_MPU14_MAIN
+ ret = PPU_Configure(&PROT_MPU14_MAIN_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PROT_MPU14_MAIN_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PROT_MPU15_MAIN
+ ret = PPU_Configure(&PROT_MPU15_MAIN_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PROT_MPU15_MAIN_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FLASHC_MAIN
+ ret = PPU_Configure(&FLASHC_MAIN_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FLASHC_MAIN_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FLASHC_CMD
+ ret = PPU_Configure(&FLASHC_CMD_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FLASHC_CMD_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FLASHC_DFT
+ ret = PPU_Configure(&FLASHC_DFT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FLASHC_DFT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FLASHC_CM0
+ ret = PPU_Configure(&FLASHC_CM0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FLASHC_CM0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FLASHC_CM4
+ ret = PPU_Configure(&FLASHC_CM4_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FLASHC_CM4_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FLASHC_CRYPTO
+ ret = PPU_Configure(&FLASHC_CRYPTO_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FLASHC_CRYPTO_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FLASHC_DW0
+ ret = PPU_Configure(&FLASHC_DW0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FLASHC_DW0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FLASHC_DW1
+ ret = PPU_Configure(&FLASHC_DW1_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FLASHC_DW1_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FLASHC_DMAC
+ ret = PPU_Configure(&FLASHC_DMAC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FLASHC_DMAC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FLASHC_EXT_MS0
+ ret = PPU_Configure(&FLASHC_EXT_MS0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FLASHC_EXT_MS0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FLASHC_EXT_MS1
+ ret = PPU_Configure(&FLASHC_EXT_MS1_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FLASHC_EXT_MS1_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_FLASHC_FM
+ ret = PPU_Configure(&FLASHC_FM_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&FLASHC_FM_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SRSS_MAIN1
+ ret = PPU_Configure(&SRSS_MAIN1_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SRSS_MAIN1_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SRSS_MAIN2
+ ret = PPU_Configure(&SRSS_MAIN2_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SRSS_MAIN2_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_WDT
+ ret = PPU_Configure(&WDT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&WDT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_MAIN
+ ret = PPU_Configure(&MAIN_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&MAIN_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SRSS_MAIN3
+ ret = PPU_Configure(&SRSS_MAIN3_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SRSS_MAIN3_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SRSS_MAIN4
+ ret = PPU_Configure(&SRSS_MAIN4_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SRSS_MAIN4_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SRSS_MAIN5
+ ret = PPU_Configure(&SRSS_MAIN5_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SRSS_MAIN5_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SRSS_MAIN6
+ ret = PPU_Configure(&SRSS_MAIN6_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SRSS_MAIN6_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SRSS_MAIN7
+ ret = PPU_Configure(&SRSS_MAIN7_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SRSS_MAIN7_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_BACKUP_BACKUP
+ ret = PPU_Configure(&BACKUP_BACKUP_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&BACKUP_BACKUP_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_DW
+ ret = PPU_Configure(&DW0_DW_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_DW_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_DW
+ ret = PPU_Configure(&DW1_DW_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_DW_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_DW_CRC
+ ret = PPU_Configure(&DW0_DW_CRC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_DW_CRC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_DW_CRC
+ ret = PPU_Configure(&DW1_DW_CRC_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_DW_CRC_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT0_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT0_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT0_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT1_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT1_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT1_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT2_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT2_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT2_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT3_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT3_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT3_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT4_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT4_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT4_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT5_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT5_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT5_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT6_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT6_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT6_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT7_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT7_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT7_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT8_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT8_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT8_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT9_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT9_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT9_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT10_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT10_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT10_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT11_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT11_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT11_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT12_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT12_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT12_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT13_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT13_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT13_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT14_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT14_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT14_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT15_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT15_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT15_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT16_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT16_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT16_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT17_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT17_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT17_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT18_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT18_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT18_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT19_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT19_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT19_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT20_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT20_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT20_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT21_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT21_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT21_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT22_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT22_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT22_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT23_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT23_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT23_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT24_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT24_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT24_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT25_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT25_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT25_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT26_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT26_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT26_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT27_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT27_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT27_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW0_CH_STRUCT28_CH
+ ret = PPU_Configure(&DW0_CH_STRUCT28_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW0_CH_STRUCT28_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT0_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT0_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT0_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT1_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT1_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT1_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT2_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT2_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT2_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT3_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT3_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT3_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT4_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT4_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT4_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT5_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT5_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT5_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT6_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT6_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT6_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT7_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT7_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT7_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT8_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT8_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT8_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT9_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT9_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT9_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT10_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT10_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT10_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT11_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT11_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT11_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT12_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT12_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT12_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT13_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT13_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT13_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT14_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT14_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT14_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT15_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT15_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT15_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT16_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT16_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT16_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT17_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT17_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT17_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT18_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT18_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT18_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT19_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT19_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT19_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT20_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT20_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT20_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT21_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT21_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT21_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT22_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT22_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT22_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT23_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT23_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT23_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT24_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT24_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT24_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT25_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT25_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT25_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT26_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT26_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT26_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT27_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT27_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT27_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DW1_CH_STRUCT28_CH
+ ret = PPU_Configure(&DW1_CH_STRUCT28_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DW1_CH_STRUCT28_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DMAC_TOP
+ ret = PPU_Configure(&DMAC_TOP_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DMAC_TOP_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DMAC_CH0_CH
+ ret = PPU_Configure(&DMAC_CH0_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DMAC_CH0_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DMAC_CH1_CH
+ ret = PPU_Configure(&DMAC_CH1_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DMAC_CH1_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DMAC_CH2_CH
+ ret = PPU_Configure(&DMAC_CH2_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DMAC_CH2_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_DMAC_CH3_CH
+ ret = PPU_Configure(&DMAC_CH3_CH_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&DMAC_CH3_CH_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_EFUSE_CTL
+ ret = PPU_Configure(&EFUSE_CTL_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&EFUSE_CTL_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_EFUSE_DATA
+ ret = PPU_Configure(&EFUSE_DATA_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&EFUSE_DATA_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PROFILE
+ ret = PPU_Configure(&PROFILE_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PROFILE_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT0_PRT
+ ret = PPU_Configure(&HSIOM_PRT0_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT0_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT1_PRT
+ ret = PPU_Configure(&HSIOM_PRT1_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT1_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT2_PRT
+ ret = PPU_Configure(&HSIOM_PRT2_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT2_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT3_PRT
+ ret = PPU_Configure(&HSIOM_PRT3_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT3_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT4_PRT
+ ret = PPU_Configure(&HSIOM_PRT4_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT4_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT5_PRT
+ ret = PPU_Configure(&HSIOM_PRT5_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT5_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT6_PRT
+ ret = PPU_Configure(&HSIOM_PRT6_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT6_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT7_PRT
+ ret = PPU_Configure(&HSIOM_PRT7_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT7_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT8_PRT
+ ret = PPU_Configure(&HSIOM_PRT8_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT8_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT9_PRT
+ ret = PPU_Configure(&HSIOM_PRT9_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT9_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT10_PRT
+ ret = PPU_Configure(&HSIOM_PRT10_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT10_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT11_PRT
+ ret = PPU_Configure(&HSIOM_PRT11_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT11_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT12_PRT
+ ret = PPU_Configure(&HSIOM_PRT12_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT12_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT13_PRT
+ ret = PPU_Configure(&HSIOM_PRT13_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT13_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_PRT14_PRT
+ ret = PPU_Configure(&HSIOM_PRT14_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_PRT14_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_AMUX
+ ret = PPU_Configure(&HSIOM_AMUX_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_AMUX_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_HSIOM_MON
+ ret = PPU_Configure(&HSIOM_MON_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&HSIOM_MON_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT0_PRT
+ ret = PPU_Configure(&GPIO_PRT0_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT0_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT1_PRT
+ ret = PPU_Configure(&GPIO_PRT1_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT1_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT2_PRT
+ ret = PPU_Configure(&GPIO_PRT2_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT2_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT3_PRT
+ ret = PPU_Configure(&GPIO_PRT3_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT3_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT4_PRT
+ ret = PPU_Configure(&GPIO_PRT4_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT4_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT5_PRT
+ ret = PPU_Configure(&GPIO_PRT5_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT5_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT6_PRT
+ ret = PPU_Configure(&GPIO_PRT6_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT6_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT7_PRT
+ ret = PPU_Configure(&GPIO_PRT7_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT7_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT8_PRT
+ ret = PPU_Configure(&GPIO_PRT8_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT8_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT9_PRT
+ ret = PPU_Configure(&GPIO_PRT9_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT9_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT10_PRT
+ ret = PPU_Configure(&GPIO_PRT10_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT10_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT11_PRT
+ ret = PPU_Configure(&GPIO_PRT11_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT11_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT12_PRT
+ ret = PPU_Configure(&GPIO_PRT12_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT12_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT13_PRT
+ ret = PPU_Configure(&GPIO_PRT13_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT13_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT14_PRT
+ ret = PPU_Configure(&GPIO_PRT14_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT14_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT0_CFG
+ ret = PPU_Configure(&GPIO_PRT0_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT0_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT1_CFG
+ ret = PPU_Configure(&GPIO_PRT1_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT1_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT2_CFG
+ ret = PPU_Configure(&GPIO_PRT2_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT2_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT3_CFG
+ ret = PPU_Configure(&GPIO_PRT3_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT3_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT4_CFG
+ ret = PPU_Configure(&GPIO_PRT4_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT4_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT5_CFG
+ ret = PPU_Configure(&GPIO_PRT5_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT5_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT6_CFG
+ ret = PPU_Configure(&GPIO_PRT6_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT6_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT7_CFG
+ ret = PPU_Configure(&GPIO_PRT7_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT7_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT8_CFG
+ ret = PPU_Configure(&GPIO_PRT8_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT8_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT9_CFG
+ ret = PPU_Configure(&GPIO_PRT9_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT9_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT10_CFG
+ ret = PPU_Configure(&GPIO_PRT10_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT10_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT11_CFG
+ ret = PPU_Configure(&GPIO_PRT11_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT11_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT12_CFG
+ ret = PPU_Configure(&GPIO_PRT12_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT12_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT13_CFG
+ ret = PPU_Configure(&GPIO_PRT13_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT13_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_PRT14_CFG
+ ret = PPU_Configure(&GPIO_PRT14_CFG_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_PRT14_CFG_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_GPIO
+ ret = PPU_Configure(&GPIO_GPIO_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_GPIO_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_GPIO_TEST
+ ret = PPU_Configure(&GPIO_TEST_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&GPIO_TEST_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SMARTIO_PRT8_PRT
+ ret = PPU_Configure(&SMARTIO_PRT8_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SMARTIO_PRT8_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SMARTIO_PRT9_PRT
+ ret = PPU_Configure(&SMARTIO_PRT9_PRT_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SMARTIO_PRT9_PRT_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_LPCOMP
+ ret = PPU_Configure(&LPCOMP_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&LPCOMP_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_CSD0
+ ret = PPU_Configure(&CSD0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&CSD0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_TCPWM0
+ ret = PPU_Configure(&TCPWM0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&TCPWM0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_TCPWM1
+ ret = PPU_Configure(&TCPWM1_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&TCPWM1_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_LCD0
+ ret = PPU_Configure(&LCD0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&LCD0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_USBFS0
+ ret = PPU_Configure(&USBFS0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&USBFS0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SMIF0
+ ret = PPU_Configure(&SMIF0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SMIF0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SDHC0
+ ret = PPU_Configure(&SDHC0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SDHC0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SDHC1
+ ret = PPU_Configure(&SDHC1_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SDHC1_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SCB0
+ ret = PPU_Configure(&SCB0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SCB0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SCB1
+ ret = PPU_Configure(&SCB1_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SCB1_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SCB2
+ ret = PPU_Configure(&SCB2_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SCB2_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SCB3
+ ret = PPU_Configure(&SCB3_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SCB3_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SCB4
+ ret = PPU_Configure(&SCB4_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SCB4_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SCB5
+ ret = PPU_Configure(&SCB5_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SCB5_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SCB6
+ ret = PPU_Configure(&SCB6_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SCB6_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SCB7
+ ret = PPU_Configure(&SCB7_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SCB7_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SCB8
+ ret = PPU_Configure(&SCB8_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SCB8_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SCB9
+ ret = PPU_Configure(&SCB9_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SCB9_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SCB10
+ ret = PPU_Configure(&SCB10_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SCB10_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SCB11
+ ret = PPU_Configure(&SCB11_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SCB11_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_SCB12
+ ret = PPU_Configure(&SCB12_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&SCB12_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_PDM0
+ ret = PPU_Configure(&PDM0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&PDM0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_I2S0
+ ret = PPU_Configure(&I2S0_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&I2S0_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+#if RTE_MS_PPU_I2S1
+ ret = PPU_Configure(&I2S1_PPU_Resources);
+ if (ret) {
+ printf("PPU_Configure(&I2S1_PPU_Resources) returned %#x\n", ret);
+ }
+ assert(ret == CY_PROT_SUCCESS);
+#endif
+
+ __DSB();
+ __ISB();
+}
diff --git a/platform/ext/target/cypress/psoc64/target_cfg.h b/platform/ext/target/cypress/psoc64/target_cfg.h
new file mode 100644
index 0000000..d325a54
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/target_cfg.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __TARGET_CFG_H__
+#define __TARGET_CFG_H__
+
+#include "platform/ext/common/uart_stdout.h"
+#include "tfm_peripherals_def.h"
+
+#define TFM_DRIVER_STDIO Driver_USART5
+#define NS_DRIVER_STDIO Driver_USART5
+
+/**
+ * \brief Store the addresses of memory regions
+ */
+struct memory_region_limits {
+ uint32_t non_secure_code_start;
+ uint32_t non_secure_partition_base;
+ uint32_t non_secure_partition_limit;
+};
+
+/**
+ * \brief Holds the data necessary to do isolation for a specific peripheral.
+ */
+struct tfm_spm_partition_platform_data_t
+{
+ uint32_t periph_start;
+ uint32_t periph_limit;
+ int16_t periph_ppc_bank;
+ int16_t periph_ppc_loc;
+};
+
+/**
+ * \brief Configures the Shared Memory Protection Units.
+ */
+void smpu_init_cfg(void);
+
+/**
+ * \brief Configures the Peripheral Protection Units.
+ */
+void ppu_init_cfg(void);
+
+/**
+ * \brief Configure bus masters/Protectoin Contexts.
+ */
+void bus_masters_cfg(void);
+
+/**
+ * \brief Performs platform specific hw initialization.
+ */
+void platform_init(void);
+
+/**
+ * \brief Configures all external interrupts to target the
+ * NS state, apart for the ones associated to secure
+ * peripherals.
+ *
+ * \return Returns values as specified by the \ref tfm_plat_err_t
+ */
+enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void);
+
+/**
+ * \brief This function enable the interrupts associated
+ * to the secure peripherals (plus the isolation boundary violation
+ * interrupts)
+ *
+ * \return Returns values as specified by the \ref tfm_plat_err_t
+ */
+enum tfm_plat_err_t nvic_interrupt_enable(void);
+
+#endif /* __TARGET_CFG_H__ */
diff --git a/platform/ext/target/cypress/psoc64/tfm_peripherals_def.h b/platform/ext/target/cypress/psoc64/tfm_peripherals_def.h
new file mode 100644
index 0000000..724db32
--- /dev/null
+++ b/platform/ext/target/cypress/psoc64/tfm_peripherals_def.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __TFM_PERIPHERALS_DEF_H__
+#define __TFM_PERIPHERALS_DEF_H__
+
+struct tfm_spm_partition_platform_data_t;
+
+extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
+extern struct tfm_spm_partition_platform_data_t tfm_peripheral_uart1;
+
+#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart)
+#define TFM_PERIPHERAL_UART1 (&tfm_peripheral_uart1)
+#define TFM_PERIPHERAL_FPGA_IO (0)
+
+#endif /* __TFM_PERIPHERALS_DEF_H__ */