SPM: Use CMSIS defined EXC_RETURN macros
Every EXC_RETURN macro references have been renamed
according to CMSIS.
Signed-off-by: Xinyu Zhang <xinyu.zhang@arm.com>
Signed-off-by: Dávid Házi <david.hazi@arm.com>
Change-Id: I326d654a63ca5bb95e059c563a6d56cdaa165cc3
diff --git a/secure_fw/spm/cmsis_psa/arch/tfm_arch.c b/secure_fw/spm/cmsis_psa/arch/tfm_arch.c
index 9bd9d98..1b622e0 100644
--- a/secure_fw/spm/cmsis_psa/arch/tfm_arch.c
+++ b/secure_fw/spm/cmsis_psa/arch/tfm_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -86,7 +86,7 @@
ARCH_CTXCTRL_EXCRET_PATTERN(&p_tctx->stat_ctx, param, pfn, pfnlr);
- ((struct context_ctrl_t *)p_ctx_ctrl)->exc_ret = EXC_RETURN_THREAD_S_PSP;
+ ((struct context_ctrl_t *)p_ctx_ctrl)->exc_ret = EXC_RETURN_THREAD_PSP;
((struct context_ctrl_t *)p_ctx_ctrl)->sp = (uintptr_t)p_tctx;
}
diff --git a/secure_fw/spm/cmsis_psa/arch/tfm_arch_v6m_v7m.h b/secure_fw/spm/cmsis_psa/arch/tfm_arch_v6m_v7m.h
index c792a20..ccaa60c 100644
--- a/secure_fw/spm/cmsis_psa/arch/tfm_arch_v6m_v7m.h
+++ b/secure_fw/spm/cmsis_psa/arch/tfm_arch_v6m_v7m.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -17,26 +17,23 @@
#endif
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
-#define EXC_RETURN_FPU_FRAME_BASIC (1 << 4)
+#define EXC_RETURN_FTYPE (1 << 4)
#endif
-#define EXC_RETURN_THREAD_S_PSP 0xFFFFFFFD
-#define EXC_RETURN_HANDLER_S_MSP 0xFFFFFFF1
-
/* Exception return behavior */
/* stack pointer used to restore context: 0=MSP 1=PSP. */
-#define EXC_RETURN_SPSEL (1UL << 2)
+#define EXC_RETURN_SPSEL (1UL << 2)
/* processor mode for return: 0=Handler mode 1=Thread mod. */
-#define EXC_RETURN_MODE (1UL << 3)
+#define EXC_RETURN_MODE (1UL << 3)
/* Exception numbers */
#define EXC_NUM_THREAD_MODE (0)
#define EXC_NUM_SVCALL (11)
#define EXC_NUM_PENDSV (14)
-#define SCB_ICSR_ADDR (0xE000ED04)
-#define SCB_ICSR_PENDSVSET_BIT (0x10000000)
+#define SCB_ICSR_ADDR (0xE000ED04)
+#define SCB_ICSR_PENDSVSET_BIT (0x10000000)
/**
* \brief Check whether Secure or Non-secure stack is used to restore stack
@@ -66,7 +63,7 @@
*/
__STATIC_INLINE bool is_stack_alloc_fp_space(uint32_t lr)
{
- return (lr & EXC_RETURN_FPU_FRAME_BASIC) ? false : true;
+ return (lr & EXC_RETURN_FTYPE) ? false : true;
}
#elif defined(__ARM_ARCH_6M__)
/**
diff --git a/secure_fw/spm/cmsis_psa/arch/tfm_arch_v8m_base.c b/secure_fw/spm/cmsis_psa/arch/tfm_arch_v8m_base.c
index 1a91d81..c51f8f8 100644
--- a/secure_fw/spm/cmsis_psa/arch/tfm_arch_v8m_base.c
+++ b/secure_fw/spm/cmsis_psa/arch/tfm_arch_v8m_base.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited. All rights reserved.
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon
* company) or an affiliate of Cypress Semiconductor Corporation. All rights
* reserved.
@@ -98,7 +98,7 @@
#if !defined(__ICCARM__)
".syntax unified \n"
#endif
- " movs r0, #"M2S(EXC_RETURN_SECURE_STACK)" \n"
+ " movs r0, #"M2S(EXC_RETURN_S)" \n"
" mov r1, lr \n"
" tst r0, r1 \n" /* NS interrupted */
" beq v8b_pendsv_exit \n" /* No schedule */
diff --git a/secure_fw/spm/cmsis_psa/arch/tfm_arch_v8m_main.c b/secure_fw/spm/cmsis_psa/arch/tfm_arch_v8m_main.c
index 2edea55..e0f665c 100644
--- a/secure_fw/spm/cmsis_psa/arch/tfm_arch_v8m_main.c
+++ b/secure_fw/spm/cmsis_psa/arch/tfm_arch_v8m_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited. All rights reserved.
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon
* * company) or an affiliate of Cypress Semiconductor Corporation. All rights
* * reserved.
@@ -99,7 +99,7 @@
#if !defined(__ICCARM__)
".syntax unified \n"
#endif
- " movs r0, #"M2S(EXC_RETURN_SECURE_STACK)" \n"
+ " movs r0, #"M2S(EXC_RETURN_S)" \n"
" ands r0, lr \n" /* NS interrupted */
" beq v8m_pendsv_exit \n" /* No schedule */
" push {r0, lr} \n" /* Save R0, LR */
diff --git a/secure_fw/spm/ffm/backend_sfn.c b/secure_fw/spm/ffm/backend_sfn.c
index b2650c2..336fec1 100644
--- a/secure_fw/spm/ffm/backend_sfn.c
+++ b/secure_fw/spm/ffm/backend_sfn.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon
* company) or an affiliate of Cypress Semiconductor Corporation. All rights
* reserved.
@@ -146,7 +146,7 @@
uint32_t backend_system_run(void)
{
- return EXC_RETURN_THREAD_S_PSP;
+ return EXC_RETURN_THREAD_PSP;
}
psa_signal_t backend_wait(struct partition_t *p_pt, psa_signal_t signal_mask)
diff --git a/secure_fw/spm/ffm/interrupt.c b/secure_fw/spm/ffm/interrupt.c
index 72e7383..1f28123 100644
--- a/secure_fw/spm/ffm/interrupt.c
+++ b/secure_fw/spm/ffm/interrupt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon
* company) or an affiliate of Cypress Semiconductor Corporation. All rights
* reserved.
@@ -112,7 +112,7 @@
/* Set FLIH result to the ISR */
p_ctx_flih_ret->state_ctx.r0 = (uint32_t)result;
- return EXC_RETURN_HANDLER_S_MSP;
+ return EXC_RETURN_HANDLER;
}
#endif
diff --git a/secure_fw/spm/include/tfm_arch_v8m.h b/secure_fw/spm/include/tfm_arch_v8m.h
index d6f74bf..68f12ad 100644
--- a/secure_fw/spm/include/tfm_arch_v8m.h
+++ b/secure_fw/spm/include/tfm_arch_v8m.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -14,38 +14,25 @@
#include "tfm_core_trustzone.h"
#include "utilities.h"
-#define EXC_RETURN_INDICATOR (0xFFUL << 24)
#define EXC_RETURN_RES1 (0x1FFFFUL << 7)
-#define EXC_RETURN_SECURE_STACK (1UL << 6)
-#define EXC_RETURN_STACK_RULE (1UL << 5)
-#define EXC_RETURN_FPU_FRAME_BASIC (1UL << 4)
-#define EXC_RETURN_MODE_THREAD (1UL << 3)
-#define EXC_RETURN_STACK_PROCESS (1UL << 2)
-#define EXC_RETURN_STACK_MAIN (0UL << 2)
-#define EXC_RETURN_RES0 (0UL << 1)
-#define EXC_RETURN_EXC_SECURE (1UL)
/* Initial EXC_RETURN value in LR when a thread is loaded at the first time */
-#define EXC_RETURN_THREAD_S_PSP \
- EXC_RETURN_INDICATOR | EXC_RETURN_RES1 | \
- EXC_RETURN_SECURE_STACK | EXC_RETURN_STACK_RULE | \
- EXC_RETURN_FPU_FRAME_BASIC | EXC_RETURN_MODE_THREAD | \
- EXC_RETURN_STACK_PROCESS | EXC_RETURN_RES0 | \
- EXC_RETURN_EXC_SECURE
+#define EXC_RETURN_THREAD_PSP \
+ EXC_RETURN_PREFIX | EXC_RETURN_RES1 | \
+ EXC_RETURN_S | EXC_RETURN_DCRS | \
+ EXC_RETURN_FTYPE | EXC_RETURN_MODE | \
+ EXC_RETURN_SPSEL | EXC_RETURN_ES
-#define EXC_RETURN_THREAD_S_MSP \
- EXC_RETURN_INDICATOR | EXC_RETURN_RES1 | \
- EXC_RETURN_SECURE_STACK | EXC_RETURN_STACK_RULE | \
- EXC_RETURN_FPU_FRAME_BASIC | EXC_RETURN_MODE_THREAD | \
- EXC_RETURN_STACK_MAIN | EXC_RETURN_RES0 | \
- EXC_RETURN_EXC_SECURE
+#define EXC_RETURN_THREAD_MSP \
+ EXC_RETURN_PREFIX | EXC_RETURN_RES1 | \
+ EXC_RETURN_S | EXC_RETURN_DCRS | \
+ EXC_RETURN_FTYPE | EXC_RETURN_MODE | \
+ EXC_RETURN_ES
-#define EXC_RETURN_HANDLER_S_MSP \
- EXC_RETURN_INDICATOR | EXC_RETURN_RES1 | \
- EXC_RETURN_SECURE_STACK | EXC_RETURN_STACK_RULE | \
- EXC_RETURN_FPU_FRAME_BASIC | \
- EXC_RETURN_STACK_MAIN | EXC_RETURN_RES0 | \
- EXC_RETURN_EXC_SECURE
+#define EXC_RETURN_HANDLER \
+ EXC_RETURN_PREFIX | EXC_RETURN_RES1 | \
+ EXC_RETURN_S | EXC_RETURN_DCRS | \
+ EXC_RETURN_FTYPE | EXC_RETURN_ES
/* Exception numbers */
#define EXC_NUM_THREAD_MODE (0)
@@ -75,7 +62,7 @@
*/
__STATIC_INLINE bool is_return_secure_stack(uint32_t lr)
{
- return (lr & EXC_RETURN_SECURE_STACK);
+ return (lr & EXC_RETURN_S);
}
/**
@@ -89,7 +76,7 @@
*/
__STATIC_INLINE bool is_stack_alloc_fp_space(uint32_t lr)
{
- return (lr & EXC_RETURN_FPU_FRAME_BASIC) ? false : true;
+ return (lr & EXC_RETURN_FTYPE) ? false : true;
}
/**