Boot: integrate MCUBoot with TF-M to act as a BL2 bootloader
Modifications in MCUBoot to be aligned with BL2 requirements in TF-M:
-- OS dependency was removed, no need to copy any OS repo to build it
-- CMSIS serial driver is used
-- flash driver interface is aligned with original version
-- S and NS images are handeled as a single binary blob
-- automatic image concatenation and signing at build time
-- authentication based on SHA256 and RSA-2048 digital signature
-- mbedTLS library is used for cryptographic operation
-- static analyser warnings fixed in some files
Change-Id: I54891762eac8d0df634e954ff19a9505b16f3028
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
diff --git a/platform/ext/target/common/flash.h b/platform/ext/target/common/flash.h
index 525f866..12cd9eb 100644
--- a/platform/ext/target/common/flash.h
+++ b/platform/ext/target/common/flash.h
@@ -20,87 +20,28 @@
* @{
*/
-#include <zephyr/types.h>
-#include <stddef.h>
-#include <sys/types.h>
-#include <device.h>
-
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(CONFIG_FLASH_PAGE_LAYOUT)
-struct flash_pages_layout {
- size_t pages_count; /* count of pages sequence of the same size */
- size_t pages_size;
-};
-#endif /* CONFIG_FLASH_PAGE_LAYOUT */
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "bl2_util.h" /* struct device */
-typedef int (*flash_api_read)(struct device *dev, off_t offset, void *data,
- size_t len);
-typedef int (*flash_api_write)(struct device *dev, off_t offset,
- const void *data, size_t len);
-typedef int (*flash_api_erase)(struct device *dev, off_t offset, size_t size);
-typedef int (*flash_api_write_protection)(struct device *dev, bool enable);
-
-#if defined(CONFIG_FLASH_PAGE_LAYOUT)
-/**
- * @brief Retrieve a flash device's layout.
- *
- * A flash device layout is a run-length encoded description of the
- * pages on the device. (Here, "pages" means the smallest erasable
- * areas on the flash device.)
- *
- * For flash memories which have uniform page sizes, this routine
- * returns an array of length 1, which specifies the page size and
- * number of pages in the memory.
- *
- * Layouts for flash memories with nonuniform page sizes will be
- * returned as an array with multiple elements, each of which
- * describes a group of pages that all have the same size. In this
- * case, the sequence of array elements specifies the order in which
- * these groups occur on the device.
- *
- * @param dev Flash device whose layout to retrieve.
- * @param layout The flash layout will be returned in this argument.
- * @param layout_size The number of elements in the returned layout.
- */
-typedef void (*flash_api_pages_layout)(struct device *dev,
- const struct flash_pages_layout **layout,
- size_t *layout_size);
-#endif /* CONFIG_FLASH_PAGE_LAYOUT */
-
-struct flash_driver_api {
- flash_api_read read;
- flash_api_write write;
- flash_api_erase erase;
- flash_api_write_protection write_protection;
-#if defined(CONFIG_FLASH_PAGE_LAYOUT)
- flash_api_pages_layout page_layout;
-#endif /* CONFIG_FLASH_PAGE_LAYOUT */
- const size_t write_block_size;
-};
+#define off_t int32_t
/**
* @brief Read data from flash
- *
- * @param dev : flash dev
+ * @param dev : flash device
* @param offset : Offset (byte aligned) to read
* @param data : Buffer to store read data
* @param len : Number of bytes to read.
*
* @return 0 on success, negative errno code on fail.
*/
-__syscall int flash_read(struct device *dev, off_t offset, void *data,
- size_t len);
-
-static inline int _impl_flash_read(struct device *dev, off_t offset, void *data,
- size_t len)
-{
- const struct flash_driver_api *api = dev->driver_api;
-
- return api->read(dev, offset, data, len);
-}
+int
+flash_read(struct device *dev, off_t offset, void *data, size_t len);
/**
* @brief Write buffer into flash memory.
@@ -115,25 +56,15 @@
*
* @return 0 on success, negative errno code on fail.
*/
-__syscall int flash_write(struct device *dev, off_t offset, const void *data,
- size_t len);
-
-static inline int _impl_flash_write(struct device *dev, off_t offset,
- const void *data, size_t len)
-{
- const struct flash_driver_api *api = dev->driver_api;
-
- return api->write(dev, offset, data, len);
-}
+int
+flash_write(struct device *dev, off_t offset, const void *data, size_t len);
/**
* @brief Erase part or all of a flash memory
*
* Acceptable values of erase size and offset are subject to
- * hardware-specific multiples of page size and offset. Please check
- * the API implemented by the underlying sub driver, for example by
- * using flash_get_page_info_by_offs() if that is supported by your
- * flash driver.
+ * hardware-specific multiples of sector size and offset. Please check the
+ * API implemented by the underlying sub driver.
*
* Prior to the invocation of this API, the flash_write_protection_set needs
* to be called first to disable the write protection.
@@ -143,19 +74,9 @@
* @param size : size of area to be erased
*
* @return 0 on success, negative errno code on fail.
- *
- * @see flash_get_page_info_by_offs()
- * @see flash_get_page_info_by_idx()
*/
-__syscall int flash_erase(struct device *dev, off_t offset, size_t size);
-
-static inline int _impl_flash_erase(struct device *dev, off_t offset,
- size_t size)
-{
- const struct flash_driver_api *api = dev->driver_api;
-
- return api->erase(dev, offset, size);
-}
+int
+flash_erase(struct device *dev, off_t offset, size_t size);
/**
* @brief Enable or disable write protection for a flash memory
@@ -163,112 +84,18 @@
* This API is required to be called before the invocation of write or erase
* API. Please note that on some flash components, the write protection is
* automatically turned on again by the device after the completion of each
- * write or erase calls. Therefore, on those flash parts, write protection needs
- * to be disabled before each invocation of the write or erase API. Please refer
- * to the sub-driver API or the data sheet of the flash component to get details
- * on the write protection behavior.
+ * write or erase calls. Therefore, on those flash parts, write protection
+ * needs to be disabled before each invocation of the write or erase API.
+ * Please refer to the sub-driver API or the data sheet of the flash component
+ * to get details on the write protection behavior.
*
* @param dev : flash device
* @param enable : enable or disable flash write protection
*
* @return 0 on success, negative errno code on fail.
*/
-__syscall int flash_write_protection_set(struct device *dev, bool enable);
-
-static inline int _impl_flash_write_protection_set(struct device *dev,
- bool enable)
-{
- const struct flash_driver_api *api = dev->driver_api;
-
- return api->write_protection(dev, enable);
-}
-
-struct flash_pages_info {
- off_t start_offset; /* offset from the base of flash address */
- size_t size;
- u32_t index;
-};
-
-#if defined(CONFIG_FLASH_PAGE_LAYOUT)
-/**
- * @brief Get size and start offset of flash page at certain flash offset.
- *
- * @param dev flash device
- * @param offset Offset within the page
- * @param info Page Info structure to be filled
- *
- * @return 0 on success, -EINVAL if page of the offset doesn't exist.
- */
-__syscall int flash_get_page_info_by_offs(struct device *dev, off_t offset,
- struct flash_pages_info *info);
-
-/**
- * @brief Get size and start offset of flash page of certain index.
- *
- * @param dev flash device
- * @param page_index Index of the page. Index are counted from 0.
- * @param info Page Info structure to be filled
- *
- * @return 0 on success, -EINVAL if page of the index doesn't exist.
- */
-__syscall int flash_get_page_info_by_idx(struct device *dev, u32_t page_index,
- struct flash_pages_info *info);
-
-/**
- * @brief Get number of flash pages.
- *
- * @param dev flash device
- *
- * @return Number of flash pages.
- */
-__syscall size_t flash_get_page_count(struct device *dev);
-
-/**
- * @brief Callback type for iterating over flash pages present on a device.
- *
- * The callback should return true to continue iterating, and false to halt.
- *
- * @param info Information for current page
- * @param data Private data for callback
- * @return True to continue iteration, false to halt iteration.
- * @see flash_page_foreach()
- */
-typedef bool (*flash_page_cb)(const struct flash_pages_info *info, void *data);
-
-/**
- * @brief Iterate over flash pages on a device
- *
- * This routine iterates over all flash pages on the given device,
- * ordered by increasing start offset. For each page, it invokes the
- * given callback, passing it the page's information and a private
- * data object.
- *
- * @param dev Device whose pages to iterate over
- * @param cb Callback to invoke for each flash page
- * @param data Private data for callback function
- */
-void flash_page_foreach(struct device *dev, flash_page_cb cb, void *data);
-#endif /* CONFIG_FLASH_PAGE_LAYOUT */
-
-/**
- * @brief Get the minimum write block size supported by the driver
- *
- * The Write block size supported by the driver might defer from the write
- * block size of memory used because the driver might implements write-modify
- * algorithm.
- *
- * @param dev flash device
- *
- * @return write block size in Bytes.
- */
-__syscall size_t flash_get_write_block_size(struct device *dev);
-
-static inline size_t _impl_flash_get_write_block_size(struct device *dev)
-{
- const struct flash_driver_api *api = dev->driver_api;
-
- return api->write_block_size;
-}
+int
+flash_write_protection_set(struct device *dev, bool enable);
#ifdef __cplusplus
}
@@ -278,6 +105,4 @@
* @}
*/
-#include <syscalls/flash.h>
-
-#endif /* _FLASH_H_ */
+#endif /* __FLASH_H__ */
diff --git a/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_flash.c b/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_flash.c
new file mode 100644
index 0000000..6d38f05
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/mps2/mps2_board/mps2_flash.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2017, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <flash.h>
+#include <string.h>
+#include "target.h"
+
+
+int flash_erase(struct device *dev, off_t offset, size_t size)
+{
+ uint32_t address = FLASH_BASE_ADDRESS + offset;
+
+ memset((void *)address, 0xff, size);
+ return 0;
+}
+
+int flash_read(struct device *dev, off_t offset, void *data, size_t len)
+{
+ uint32_t address = FLASH_BASE_ADDRESS + offset;
+
+ memcpy(data, (void *)address, len);
+ return 0;
+}
+
+int flash_write(struct device *dev, off_t offset, const void *data, size_t len)
+{
+ uint32_t address = FLASH_BASE_ADDRESS + offset;
+
+ memcpy((void *)address, data, len);
+ return 0;
+}
+
+int flash_write_protection_set(struct device *dev, bool enable)
+{
+ /* Do nothing */
+ return 0;
+}
diff --git a/platform/ext/target/sse_200_mps2/sse_200/armclang/sse_200_bl2.sct b/platform/ext/target/sse_200_mps2/sse_200/armclang/sse_200_bl2.sct
new file mode 100644
index 0000000..a8ce7d9
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/armclang/sse_200_bl2.sct
@@ -0,0 +1,30 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2017 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "../partition/region_defs.h"
+
+LR_CODE BL2_CODE_START {
+ ER_CODE BL2_CODE_START BL2_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+ ER_DATA BL2_DATA_START BL2_DATA_SIZE {
+ .ANY (+ZI +RW)
+ }
+}
diff --git a/platform/ext/target/sse_200_mps2/sse_200/armclang/startup_cmsdk_sse_200_bl2.s b/platform/ext/target/sse_200_mps2/sse_200/armclang/startup_cmsdk_sse_200_bl2.s
new file mode 100644
index 0000000..250a02d
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/armclang/startup_cmsdk_sse_200_bl2.s
@@ -0,0 +1,363 @@
+;/*
+; * Copyright (c) 2016 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00001000
+MSP_STACK_SIZE EQU 0x00000800
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT Stack_Mem
+Stack_Mem SPACE Stack_Size
+__initial_msp
+__initial_sp EQU __initial_msp - MSP_STACK_SIZE
+
+Heap_Size EQU 0x00010000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_msp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+
+SecureFault_Handler\
+ PROC
+ EXPORT SecureFault_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+MPC_Handler PROC
+ EXPORT MPC_Handler [WEAK]
+ B .
+ ENDP
+PPC_Handler PROC
+ EXPORT PPC_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; Core IoT Interrupts
+ EXPORT NONSEC_WATCHDOG_RESET_Handler [WEAK] ; - 0 Non-Secure Watchdog Reset Handler
+ EXPORT NONSEC_WATCHDOG_Handler [WEAK] ; - 1 Non-Secure Watchdog Handler
+ EXPORT S32K_TIMER_Handler [WEAK] ; - 2 S32K Timer Handler
+ EXPORT TIMER0_Handler [WEAK] ; - 3 TIMER 0 Handler
+ EXPORT TIMER1_Handler [WEAK] ; - 4 TIMER 1 Handler
+ EXPORT DUALTIMER_Handler [WEAK] ; - 5 Dual Timer Handler
+; External Interrupts
+ EXPORT UARTRX0_Handler [WEAK] ; 32 UART 0 RX Handler
+ EXPORT UARTTX0_Handler [WEAK] ; 33 UART 0 TX Handler
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TIMER0_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, = __initial_sp
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/platform/ext/target/sse_200_mps2/sse_200/partition/flash_layout.h b/platform/ext/target/sse_200_mps2/sse_200/partition/flash_layout.h
new file mode 100644
index 0000000..a0cc0d0
--- /dev/null
+++ b/platform/ext/target/sse_200_mps2/sse_200/partition/flash_layout.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2017 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __FLASH_LAYOUT_H__
+#define __FLASH_LAYOUT_H__
+
+/* Flash layout on MPS2 AN521 with BL2:
+ *
+ * 0x0000_0000 BL2 - MCUBoot
+ * 0x0008_0000 Flash_area_image_0:
+ * 0x0008_0000 Secure image primary
+ * 0x0010_0000 Non-secure image primary
+ * 0x0018_0000 Flash_area_image_1:
+ * 0x0018_0000 Secure image secondary
+ * 0x0020_0000 Non-secure image secondary
+ * 0x0028_0000 Scratch area
+ */
+#define FLASH_BASE_ADDRESS (0x0)
+
+#define FLASH_ALIGN (1)
+#define FLASH_PARTITION_SIZE (0x80000)
+#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x4000)
+
+
+#define FLASH_AREA_BL2_OFFSET (0x0)
+#define FLASH_AREA_BL2_SIZE (FLASH_PARTITION_SIZE)
+
+#define FLASH_AREA_IMAGE_0_OFFSET (0x080000)
+#define FLASH_AREA_IMAGE_0_SIZE (2 * FLASH_PARTITION_SIZE)
+
+#define FLASH_AREA_IMAGE_1_OFFSET (0x180000)
+#define FLASH_AREA_IMAGE_1_SIZE (2 * FLASH_PARTITION_SIZE)
+
+#define FLASH_AREA_IMAGE_SCRATCH_OFFSET (0x280000)
+#define FLASH_AREA_IMAGE_SCRATCH_SIZE (2 * FLASH_PARTITION_SIZE)
+
+/* Offset and size definition in flash area, used by assemble.py */
+#define SECURE_IMAGE_OFFSET 0x0
+#define SECURE_IMAGE_MAX_SIZE 0x80000
+
+#define NON_SECURE_IMAGE_OFFSET 0x80000
+#define NON_SECURE_IMAGE_MAX_SIZE 0x80000
+
+#endif /* __FLASH_LAYOUT_H__ */
diff --git a/platform/ext/target/sse_200_mps2/sse_200/partition/region_defs.h b/platform/ext/target/sse_200_mps2/sse_200/partition/region_defs.h
index afbf957..d569c61 100644
--- a/platform/ext/target/sse_200_mps2/sse_200/partition/region_defs.h
+++ b/platform/ext/target/sse_200_mps2/sse_200/partition/region_defs.h
@@ -17,58 +17,60 @@
#ifndef __REGION_DEFS_H__
#define __REGION_DEFS_H__
+#include "flash_layout.h"
+
#define TOTAL_ROM_SIZE (0x00400000) /* 4MB */
#define TOTAL_RAM_SIZE (0x00200000) /* 2MB */
/*
- * MPC granularity is 128 KB on AN505 IoT Kit MPS2 FPGA image. Alignment
+ * MPC granularity is 128 KB on AN521 Castor MPS2 FPGA image. Alignment
* of partitions is defined in accordance with this constraint.
*/
-#define BL_PARTITION_SIZE (0x80000)
-
-/*Flash partitions on MPS2 AN505 with MCUboot:
+/*Flash partitions on MPS2 AN521 with BL2:
*
- * 0x0000_0000 MCUBoot
- * 0x0008_0000 Secure image primary
- * 0x0010_0000 Non-secure image primary
- * 0x0018_0000 Secure image secondary
- * 0x0020_0000 Non-secure image secondary
+ * 0x0000_0000 BL2 - MCUBoot
+ * 0x0008_0000 Flash_area_image_0:
+ * 0x0008_0000 Secure image primary
+ * 0x0010_0000 Non-secure image primary
+ * 0x0018_0000 Flash_area_image_1:
+ * 0x0018_0000 Secure image secondary
+ * 0x0020_0000 Non-secure image secondary
* 0x0028_0000 Scratch area
*
- * Flash partitions on bare metal
- * 0x0000_0000 Secure image
+ * Flash partitions on bare metal, if BL2 not defined:
+ * 0x0000_0000 Secure image
* 0x0010_0000 Non-secure image
*/
-#ifdef MCUBOOT
-#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x80000)
+#ifdef BL2
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_IMAGE_0_OFFSET)
#else
#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0)
-#endif
+#endif /* BL2 */
#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (0x100000)
/*
- * Boot partition structure if MCUboot is used:
+ * Boot partition structure if MCUBoot is used:
* 0x0_0000 Bootloader header
* 0x0_0200 Image area
* 0x7_0000 Trailer
*/
-/* IMAGE_AREA_SIZE is the space available for the software binary image.
- * It is less than the PARTITION_SIZE because we reserve space
+/* IMAGE_CODE_SIZE is the space available for the software binary image.
+ * It is less than the FLASH_PARTITION_SIZE because we reserve space
* for the image header and trailer introduced by the bootloader. */
-#ifdef MCUBOOT
-#define BL_HEADER_SIZE (0x200)
-#define BL_TRAILER_SIZE (0x10000)
+#ifdef BL2
+#define BL2_HEADER_SIZE (0x200)
+#define BL2_TRAILER_SIZE (0x10000)
#else
-/* No header if no bootloader, but keep IMAGE_AREA_SIZE the same */
-#define BL_HEADER_SIZE (0x0)
-#define BL_TRAILER_SIZE (0x10200)
-#endif
+/* No header if no bootloader, but keep IMAGE_CODE_SIZE the same */
+#define BL2_HEADER_SIZE (0x0)
+#define BL2_TRAILER_SIZE (0x10200)
+#endif /* BL2 */
-#define IMAGE_AREA_SIZE \
- (BL_PARTITION_SIZE - BL_HEADER_SIZE - BL_TRAILER_SIZE)
+#define IMAGE_CODE_SIZE \
+ (FLASH_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
#define CMSE_VENEER_REGION_SIZE (0x00000080)
@@ -89,9 +91,9 @@
/* Secure regions */
#define S_IMAGE_PRIMARY_AREA_OFFSET \
- (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL_HEADER_SIZE)
+ (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
-#define S_CODE_SIZE (IMAGE_AREA_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
#define S_DATA_START (S_RAM_ALIAS(0x0))
@@ -105,27 +107,38 @@
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
- (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL_HEADER_SIZE)
+ (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET))
-#define NS_CODE_SIZE (IMAGE_AREA_SIZE)
+#define NS_CODE_SIZE (IMAGE_CODE_SIZE)
#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
/* NS partition information is used for MPC configuration */
#define NS_PARTITION_START \
(NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
-#ifdef MCUBOOT
+#ifdef BL2
/* Cover: non-secure primary + secure secondary + non-secure secondary area */
#define NS_PARTITION_LIMIT \
- (NS_PARTITION_START + 3 * BL_PARTITION_SIZE - 1)
+ (NS_PARTITION_START + 3 * FLASH_PARTITION_SIZE - 1)
#else
#define NS_PARTITION_LIMIT \
- (NS_PARTITION_START + BL_PARTITION_SIZE - 1)
-#endif /* MCUBOOT */
+ (NS_PARTITION_START + FLASH_PARTITION_SIZE - 1)
+#endif /* BL2 */
#define NS_DATA_START (NS_RAM_ALIAS(TOTAL_RAM_SIZE/2))
#define NS_DATA_SIZE (TOTAL_RAM_SIZE/2)
#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE -1)
+#ifdef BL2
+/* Bootloader regions */
+#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET))
+#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE)
+#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1)
+
+#define BL2_DATA_START (S_RAM_ALIAS(0x0))
+#define BL2_DATA_SIZE (TOTAL_RAM_SIZE)
+#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1)
+#endif /* BL2 */
+
#endif /* __REGION_DEFS_H__ */