platform:nrf: Add support for psa-arch-tests Firmware Framework tests
Add memory functionality and peripheral configurations needed to
execute the psa-arch-tests Firmware Framework tests.
Signed-off-by: Andreas Vibeto <andreas.vibeto@nordicsemi.no>
Change-Id: I5842556832ee189991a6144582be185ea98cd345
diff --git a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt
index f899387..0465d8e 100644
--- a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt
+++ b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt
@@ -66,6 +66,7 @@
native_drivers/spu.c
spm_hal.c
tfm_hal_isolation.c
+ PUBLIC
plat_test.c
)
diff --git a/platform/ext/target/nordic_nrf/common/core/pal_plat_test.h b/platform/ext/target/nordic_nrf/common/core/pal_plat_test.h
new file mode 100644
index 0000000..ff4bf18
--- /dev/null
+++ b/platform/ext/target/nordic_nrf/common/core/pal_plat_test.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2021 Nordic Semiconductor ASA. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \note These interfaces are needed to execute PSA tests
+ * on Nordic platforms
+ */
+
+/**
+ * \brief Initialize the timer with the given number of ticks.
+ *
+ * \param[in] ticks Number of ticks per microsecond
+ */
+void pal_timer_init_ns(uint32_t ticks);
+
+/**
+ * \brief Start the timer.
+ */
+void pal_timer_start_ns(void);
+
+/**
+ * \brief Stop and reset the timer.
+ */
+void pal_timer_stop_ns(void);
+
+/**
+ * \brief Get the address of a free, word-aligned, 1K memory area.
+ */
+uint32_t pal_nvmem_get_addr(void);
diff --git a/platform/ext/target/nordic_nrf/common/core/plat_test.c b/platform/ext/target/nordic_nrf/common/core/plat_test.c
index 1b9eeb5..e9bc442 100644
--- a/platform/ext/target/nordic_nrf/common/core/plat_test.c
+++ b/platform/ext/target/nordic_nrf/common/core/plat_test.c
@@ -16,6 +16,7 @@
#include <string.h>
#include "tfm_plat_test.h"
+#include "pal_plat_test.h"
#include <stdint.h>
#include <stdbool.h>
#include <hal/nrf_gpio.h>
@@ -23,8 +24,11 @@
#include <helpers/nrfx_reset_reason.h>
#include <nrf_board.h>
#include <region_defs.h>
+
+#if defined(PSA_API_TEST_NS) && !defined(PSA_API_TEST_IPC)
#include <tfm_platform_api.h>
#include <log/tfm_log.h>
+#endif
#define TIMER_RELOAD_VALUE (1*1000*1000)
#define USERLED_MASK (1UL)
@@ -139,7 +143,7 @@
timer_stop(NRF_TIMER1);
}
-#if !defined(TEST_NS_SLIH_IRQ)
+#if defined(PSA_API_TEST_NS) && !defined(PSA_API_TEST_IPC)
/* Watchdog timeout handler. */
void TIMER1_Handler(void)
{
diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/config.cmake b/platform/ext/target/nordic_nrf/common/nrf5340/config.cmake
index ceb1ecf..b421d9c 100644
--- a/platform/ext/target/nordic_nrf/common/nrf5340/config.cmake
+++ b/platform/ext/target/nordic_nrf/common/nrf5340/config.cmake
@@ -7,5 +7,5 @@
#-------------------------------------------------------------------------------
set(SECURE_UART1 ON CACHE BOOL "Enable secure UART1")
-set(PSA_API_TEST_TARGET "nrf" CACHE STRING "PSA API test target")
+set(PSA_API_TEST_TARGET "nrf5340" CACHE STRING "PSA API test target")
set(ITS_NUM_ASSETS "5" CACHE STRING "The maximum number of assets to be stored in the Internal Trusted Storage area")
diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf5340/partition/flash_layout.h
index 4fec9f5..128a07d 100644
--- a/platform/ext/target/nordic_nrf/common/nrf5340/partition/flash_layout.h
+++ b/platform/ext/target/nordic_nrf/common/nrf5340/partition/flash_layout.h
@@ -51,8 +51,15 @@
*/
/* Size of a Secure and of a Non-secure image */
+#ifdef PSA_API_TEST_IPC
+/* Firmware Framework test suites */
+#define FLASH_S_PARTITION_SIZE (0x48000) /* S partition: 288 kB*/
+#define FLASH_NS_PARTITION_SIZE (0x28000) /* NS partition: 160 kB*/
+#else
#define FLASH_S_PARTITION_SIZE (0x40000) /* S partition: 256 kB*/
#define FLASH_NS_PARTITION_SIZE (0x30000) /* NS partition: 192 kB*/
+#endif
+
#define FLASH_MAX_PARTITION_SIZE ((FLASH_S_PARTITION_SIZE > \
FLASH_NS_PARTITION_SIZE) ? \
FLASH_S_PARTITION_SIZE : \
@@ -148,6 +155,11 @@
FLASH_ITS_AREA_SIZE)
#define FLASH_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE)
+/* PSA MMIO Area definitions */
+#define FLASH_MMIO_AREA_OFFSET (FLASH_NV_COUNTERS_AREA_OFFSET + \
+ FLASH_NV_COUNTERS_AREA_SIZE)
+#define FLASH_MMIO_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE)
+
/* Offset and size definition in flash area used by assemble.py */
#define SECURE_IMAGE_OFFSET (0x0)
#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE
diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf5340/partition/region_defs.h
index 3651b4b..99dcf7e 100644
--- a/platform/ext/target/nordic_nrf/common/nrf5340/partition/region_defs.h
+++ b/platform/ext/target/nordic_nrf/common/nrf5340/partition/region_defs.h
@@ -129,7 +129,12 @@
#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE))
+#ifdef PSA_API_TEST_IPC
+/* Last SRAM region must be kept secure for PSA FF tests */
+#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - SPU_SRAM_REGION_SIZE)
+#else
#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE)
+#endif
#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1)
/* NS partition information is used for SPU configuration */
@@ -163,9 +168,37 @@
#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \
BOOT_TFM_SHARED_DATA_SIZE - 1)
-/* Region used by psa-arch-tests to keep state */
+/* Regions used by psa-arch-tests to keep state */
#define PSA_TEST_SCRATCH_AREA_SIZE (0x400)
+
+#ifdef PSA_API_TEST_IPC
+/* Firmware Framework test suites */
+#define FF_TEST_PARTITION_SIZE 0x100
+#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \
+ PSA_TEST_SCRATCH_AREA_SIZE - \
+ FF_TEST_PARTITION_SIZE)
+
+/* The psa-arch-tests implementation requires that the test partitions are
+ * placed in this specific order:
+ * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER
+ *
+ * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER
+ * must be in SPE.
+ *
+ * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation,
+ * and it should be placed at the end of the NSPE area, after
+ * PSA_TEST_SCRATCH_AREA.
+ */
+#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1)
+#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \
+ FF_TEST_PARTITION_SIZE - 1)
+#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1)
+#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \
+ FF_TEST_PARTITION_SIZE - 1)
+#else
+/* Development APIs test suites */
#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \
PSA_TEST_SCRATCH_AREA_SIZE)
+#endif /* PSA_API_TEST_IPC */
#endif /* __REGION_DEFS_H__ */
diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c b/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c
index 69bbcae..b6553c2 100644
--- a/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c
+++ b/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c
@@ -37,6 +37,31 @@
NRF_UARTE1_S_BASE + (sizeof(NRF_UARTE_Type) - 1),
};
+#ifdef PSA_API_TEST_IPC
+struct platform_data_t
+ tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO = {
+ FF_TEST_SERVER_PARTITION_MMIO_START,
+ FF_TEST_SERVER_PARTITION_MMIO_END
+};
+
+struct platform_data_t
+ tfm_peripheral_FF_TEST_DRIVER_PARTITION_MMIO = {
+ FF_TEST_DRIVER_PARTITION_MMIO_START,
+ FF_TEST_DRIVER_PARTITION_MMIO_END
+};
+
+/* This platform implementation uses PSA_TEST_SCRATCH_AREA for
+ * storing the state between resets, but the FF_TEST_NVMEM_REGIONS
+ * definitons are still needed for tests to compile.
+ */
+#define FF_TEST_NVMEM_REGION_START 0xFFFFFFFF
+#define FF_TEST_NVMEM_REGION_END 0xFFFFFFFF
+struct platform_data_t
+ tfm_peripheral_FF_TEST_NVMEM_REGION = {
+ FF_TEST_NVMEM_REGION_START,
+ FF_TEST_NVMEM_REGION_END
+};
+#endif /* PSA_API_TEST_IPC */
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
@@ -238,7 +263,10 @@
spu_peripheral_config_non_secure((uint32_t)NRF_EGU2, false);
spu_peripheral_config_non_secure((uint32_t)NRF_EGU3, false);
spu_peripheral_config_non_secure((uint32_t)NRF_EGU4, false);
+#ifndef PSA_API_TEST_IPC
+ /* EGU5 is used as a secure peripheral in PSA FF tests */
spu_peripheral_config_non_secure((uint32_t)NRF_EGU5, false);
+#endif
spu_peripheral_config_non_secure((uint32_t)NRF_PWM0, false);
spu_peripheral_config_non_secure((uint32_t)NRF_PWM1, false);
spu_peripheral_config_non_secure((uint32_t)NRF_PWM2, false);
diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/tfm_peripherals_def.h b/platform/ext/target/nordic_nrf/common/nrf5340/tfm_peripherals_def.h
index bba6a81..5b349a7 100644
--- a/platform/ext/target/nordic_nrf/common/nrf5340/tfm_peripherals_def.h
+++ b/platform/ext/target/nordic_nrf/common/nrf5340/tfm_peripherals_def.h
@@ -28,6 +28,21 @@
#define TFM_PERIPHERAL_TIMER0 (&tfm_peripheral_timer0)
#define TFM_PERIPHERAL_FPGA_IO (0)
+#ifdef PSA_API_TEST_IPC
+#define FF_TEST_UART_IRQ (EGU5_IRQn)
+#define FF_TEST_UART_IRQ_Handler (pal_interrupt_handler)
+
+extern struct platform_data_t tfm_peripheral_FF_TEST_NVMEM_REGION;
+extern struct platform_data_t tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO;
+extern struct platform_data_t tfm_peripheral_FF_TEST_DRIVER_PARTITION_MMIO;
+
+#define FF_TEST_UART_REGION (&tfm_peripheral_std_uart)
+#define FF_TEST_WATCHDOG_REGION (&tfm_peripheral_timer0)
+#define FF_TEST_NVMEM_REGION (&tfm_peripheral_FF_TEST_NVMEM_REGION)
+#define FF_TEST_SERVER_PARTITION_MMIO (&tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO)
+#define FF_TEST_DRIVER_PARTITION_MMIO (&tfm_peripheral_FF_TEST_DRIVER_PARTITION_MMIO)
+#endif /* PSA_API_TEST_IPC */
+
#ifdef __cplusplus
}
#endif
diff --git a/platform/ext/target/nordic_nrf/common/nrf9160/config.cmake b/platform/ext/target/nordic_nrf/common/nrf9160/config.cmake
index ceb1ecf..d0131a3 100644
--- a/platform/ext/target/nordic_nrf/common/nrf9160/config.cmake
+++ b/platform/ext/target/nordic_nrf/common/nrf9160/config.cmake
@@ -7,5 +7,5 @@
#-------------------------------------------------------------------------------
set(SECURE_UART1 ON CACHE BOOL "Enable secure UART1")
-set(PSA_API_TEST_TARGET "nrf" CACHE STRING "PSA API test target")
+set(PSA_API_TEST_TARGET "nrf9160" CACHE STRING "PSA API test target")
set(ITS_NUM_ASSETS "5" CACHE STRING "The maximum number of assets to be stored in the Internal Trusted Storage area")
diff --git a/platform/ext/target/nordic_nrf/common/nrf9160/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf9160/partition/flash_layout.h
index ad53de9..e4679d0 100644
--- a/platform/ext/target/nordic_nrf/common/nrf9160/partition/flash_layout.h
+++ b/platform/ext/target/nordic_nrf/common/nrf9160/partition/flash_layout.h
@@ -51,8 +51,15 @@
*/
/* Size of a Secure and of a Non-secure image */
+#ifdef PSA_API_TEST_IPC
+/* Firmware Framework test suites */
+#define FLASH_S_PARTITION_SIZE (0x48000) /* S partition: 288 kB*/
+#define FLASH_NS_PARTITION_SIZE (0x28000) /* NS partition: 160 kB*/
+#else
#define FLASH_S_PARTITION_SIZE (0x40000) /* S partition: 256 kB*/
#define FLASH_NS_PARTITION_SIZE (0x30000) /* NS partition: 192 kB*/
+#endif
+
#define FLASH_MAX_PARTITION_SIZE ((FLASH_S_PARTITION_SIZE > \
FLASH_NS_PARTITION_SIZE) ? \
FLASH_S_PARTITION_SIZE : \
@@ -149,6 +156,11 @@
FLASH_ITS_AREA_SIZE)
#define FLASH_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE)
+/* PSA MMIO Area definitions */
+#define FLASH_MMIO_AREA_OFFSET (FLASH_NV_COUNTERS_AREA_OFFSET + \
+ FLASH_NV_COUNTERS_AREA_SIZE)
+#define FLASH_MMIO_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE)
+
/* Offset and size definition in flash area used by assemble.py */
#define SECURE_IMAGE_OFFSET (0x0)
#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE
diff --git a/platform/ext/target/nordic_nrf/common/nrf9160/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf9160/partition/region_defs.h
index 98f2080..f670370 100644
--- a/platform/ext/target/nordic_nrf/common/nrf9160/partition/region_defs.h
+++ b/platform/ext/target/nordic_nrf/common/nrf9160/partition/region_defs.h
@@ -132,7 +132,12 @@
#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE))
+#ifdef PSA_API_TEST_IPC
+/* Last SRAM region must be kept secure for PSA FF tests */
+#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - SPU_SRAM_REGION_SIZE)
+#else
#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE)
+#endif
#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1)
/* NS partition information is used for SPU configuration */
@@ -166,9 +171,37 @@
#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \
BOOT_TFM_SHARED_DATA_SIZE - 1)
-/* Region used by psa-arch-tests to keep state */
+/* Regions used by psa-arch-tests to keep state */
#define PSA_TEST_SCRATCH_AREA_SIZE (0x400)
+
+#ifdef PSA_API_TEST_IPC
+/* Firmware Framework test suites */
+#define FF_TEST_PARTITION_SIZE 0x100
+#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \
+ PSA_TEST_SCRATCH_AREA_SIZE - \
+ FF_TEST_PARTITION_SIZE)
+
+/* The psa-arch-tests implementation requires that the test partitions are
+ * placed in this specific order:
+ * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER
+ *
+ * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER
+ * must be in SPE.
+ *
+ * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation,
+ * and it should be placed at the end of the NSPE area, after
+ * PSA_TEST_SCRATCH_AREA.
+ */
+#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1)
+#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \
+ FF_TEST_PARTITION_SIZE - 1)
+#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1)
+#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \
+ FF_TEST_PARTITION_SIZE - 1)
+#else
+/* Development APIs test suites */
#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \
PSA_TEST_SCRATCH_AREA_SIZE)
+#endif /* PSA_API_TEST_IPC */
#endif /* __REGION_DEFS_H__ */
diff --git a/platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c b/platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c
index 17d7861..7365bb8 100644
--- a/platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c
+++ b/platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c
@@ -34,6 +34,33 @@
NRF_UARTE1_S_BASE + (sizeof(NRF_UARTE_Type) - 1),
};
+#ifdef PSA_API_TEST_IPC
+struct platform_data_t
+ tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO = {
+ FF_TEST_SERVER_PARTITION_MMIO_START,
+ FF_TEST_SERVER_PARTITION_MMIO_END
+};
+
+struct platform_data_t
+ tfm_peripheral_FF_TEST_DRIVER_PARTITION_MMIO = {
+ FF_TEST_DRIVER_PARTITION_MMIO_START,
+ FF_TEST_DRIVER_PARTITION_MMIO_END
+};
+
+/* This platform implementation uses PSA_TEST_SCRATCH_AREA for
+ * storing the state between resets, but the FF_TEST_NVMEM_REGIONS
+ * definitons are still needed for tests to compile.
+ */
+#define FF_TEST_NVMEM_REGION_START 0xFFFFFFFF
+#define FF_TEST_NVMEM_REGION_END 0xFFFFFFFF
+struct platform_data_t
+ tfm_peripheral_FF_TEST_NVMEM_REGION = {
+ FF_TEST_NVMEM_REGION_START,
+ FF_TEST_NVMEM_REGION_END
+};
+#endif /* PSA_API_TEST_IPC */
+
+
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
@@ -212,7 +239,10 @@
spu_peripheral_config_non_secure((uint32_t)NRF_EGU2, false);
spu_peripheral_config_non_secure((uint32_t)NRF_EGU3, false);
spu_peripheral_config_non_secure((uint32_t)NRF_EGU4, false);
+#ifndef PSA_API_TEST_IPC
+ /* EGU5 is used as a secure peripheral in PSA FF tests */
spu_peripheral_config_non_secure((uint32_t)NRF_EGU5, false);
+#endif
spu_peripheral_config_non_secure((uint32_t)NRF_PWM0, false);
spu_peripheral_config_non_secure((uint32_t)NRF_PWM1, false);
spu_peripheral_config_non_secure((uint32_t)NRF_PWM2, false);
diff --git a/platform/ext/target/nordic_nrf/common/nrf9160/tfm_peripherals_def.h b/platform/ext/target/nordic_nrf/common/nrf9160/tfm_peripherals_def.h
index bba6a81..3ac1ee9 100644
--- a/platform/ext/target/nordic_nrf/common/nrf9160/tfm_peripherals_def.h
+++ b/platform/ext/target/nordic_nrf/common/nrf9160/tfm_peripherals_def.h
@@ -28,6 +28,22 @@
#define TFM_PERIPHERAL_TIMER0 (&tfm_peripheral_timer0)
#define TFM_PERIPHERAL_FPGA_IO (0)
+#ifdef PSA_API_TEST_IPC
+#define FF_TEST_UART_IRQ (EGU5_IRQn)
+#define FF_TEST_UART_IRQ_Handler (pal_interrupt_handler)
+
+extern struct platform_data_t tfm_peripheral_FF_TEST_NVMEM_REGION;
+extern struct platform_data_t tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO;
+extern struct platform_data_t tfm_peripheral_FF_TEST_DRIVER_PARTITION_MMIO;
+
+#define FF_TEST_UART_REGION (&tfm_peripheral_std_uart)
+#define FF_TEST_WATCHDOG_REGION (&tfm_peripheral_timer0)
+#define FF_TEST_NVMEM_REGION (&tfm_peripheral_FF_TEST_NVMEM_REGION)
+#define FF_TEST_SERVER_PARTITION_MMIO (&tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO)
+#define FF_TEST_DRIVER_PARTITION_MMIO (&tfm_peripheral_FF_TEST_DRIVER_PARTITION_MMIO)
+#endif /* PSA_API_TEST_IPC */
+
+
#ifdef __cplusplus
}
#endif