Platform: Refine image flash layout
Eliminate the unnecessary space between the LR_VENEER section
and the rest of the secure code. Place the CMSE veneers right
after the vectors section. The size of vectors section is fixed
for each platform. So the start address of the CMSE veneers
section is also fixed.
Add "a" attribute for the vectors section in startup.S file for
gcc so that the vectors section can be kept in the .bin file.
This patch covers all the platforms that use the tfm_common_s.
sct/ld link script.
Move the .ER_EFLASH_DRIVER_RO section in front of .ER_TFM_CODE
section in gnulinker so that the flash driver code can be picked
into the .ER_EFLASH_DRIVER_RO sectio instead of .ER_TFM_CODE
section.
Signed-off-by: Sherry Zhang <sherry.zhang2@arm.com>
Change-Id: I0084aef576d90af45513c7eaae58ba6c6dbbddab
diff --git a/platform/ext/common/armclang/tfm_common_s.sct b/platform/ext/common/armclang/tfm_common_s.sct
index cce1573..2af02b1 100644
--- a/platform/ext/common/armclang/tfm_common_s.sct
+++ b/platform/ext/common/armclang/tfm_common_s.sct
@@ -19,8 +19,30 @@
LR_CODE S_CODE_START S_CODE_SIZE {
/**** This initial section contains common code for secure binary */
- ER_TFM_CODE S_CODE_START {
+ ER_VECTORS S_CODE_START S_CODE_VECTOR_TABLE_SIZE {
*.o (RESET +First)
+ }
+#ifndef TFM_MULTI_CORE_TOPOLOGY
+ ER_VECTORS_FILL +0 EMPTY (S_CODE_VECTOR_TABLE_SIZE - ImageLength(ER_VECTORS)) {
+ }
+ /*
+ * Place the CMSE Veneers (containing the SG instruction) in a separate
+ * 32 bytes aligned region so that the SAU can be programmed to
+ * just set this region as Non-Secure Callable.
+ */
+ ER_VENEER +0 FIXED ALIGN 32 {
+ *(Veneer$$CMSE)
+ }
+ /*
+ * The Limit of the VENEER_ALIGN region should be 32 bytes aligned so that
+ * the SAU can set this region as Non-Secure Callable.
+ */
+ VENEER_ALIGN +0 ALIGN 32 EMPTY 0x0 {
+ }
+#endif
+
+ ER_TFM_CODE +0 {
+ *startup*(.text*)
*libplatform_s* (.text*, .rodata*)
*libtfm_spm* (+RO)
}
@@ -256,19 +278,6 @@
ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
}
-#ifndef TFM_MULTI_CORE_TOPOLOGY
-LR_VENEER CMSE_VENEER_REGION_START {
- /*
- * Place the CMSE Veneers (containing the SG instruction) in a separate
- * 32 bytes aligned region so that the SAU can be programmed to
- * just set this region as Non-Secure Callable.
- */
- CMSE_VENEER CMSE_VENEER_REGION_START CMSE_VENEER_REGION_SIZE {
- *(Veneer$$CMSE)
- }
-}
-#endif
-
LR_NS_PARTITION NS_PARTITION_START {
/* Reserved place for NS application.
* No code will be placed here, just address of this region is used in the
diff --git a/platform/ext/common/armclang/tfm_isolation_l3.sct.template b/platform/ext/common/armclang/tfm_isolation_l3.sct.template
index 1cbc6eb..b357249 100644
--- a/platform/ext/common/armclang/tfm_isolation_l3.sct.template
+++ b/platform/ext/common/armclang/tfm_isolation_l3.sct.template
@@ -28,17 +28,39 @@
#include "region_defs.h"
-LR_CODE S_CODE_START {
-
- PT_RO_START S_CODE_START ALIGN 32 EMPTY 0x0 {
+LR_CODE S_CODE_START S_CODE_SIZE {
+ PT_RO_START +0 ALIGN 32 EMPTY 0x0 {
/* Position tag: code + RO-data */
}
/**** This initial section contains mainly the SPM code and RO-data */
- ER_TFM_CODE +0 ALIGN 32 {
+ ER_VECTORS +0 ALIGN 32 S_CODE_VECTOR_TABLE_SIZE {
*.o (RESET +First)
- *libtfm_spm* (+RO)
+ }
+#ifndef TFM_MULTI_CORE_TOPOLOGY
+ ER_VECTORS_FILL +0 EMPTY (S_CODE_VECTOR_TABLE_SIZE - ImageLength(ER_VECTORS)) {
+ }
+
+ /*
+ * Place the CMSE Veneers (containing the SG instruction) in a separate
+ * 32 bytes aligned region so that the SAU can be programmed to
+ * just set this region as Non-Secure Callable.
+ */
+ ER_VENEER +0 FIXED ALIGN 32 {
+ *(Veneer$$CMSE)
+ }
+ /*
+ * The Limit of the VENEER_ALIGN region should be 32 bytes aligned so that
+ * the SAU can set this region as Non-Secure Callable.
+ */
+ VENEER_ALIGN +0 ALIGN 32 EMPTY 0x0 {
+ }
+#endif
+
+ ER_TFM_CODE +0 {
+ *startup*(.text*)
*libplatform_s* (+RO)
+ *libtfm_spm* (+RO)
}
/**** Section for holding partition RO load data */
@@ -217,17 +239,6 @@
#endif
}
-LR_VENEER CMSE_VENEER_REGION_START {
- /*
- * Place the CMSE Veneers (containing the SG instruction) in a separate
- * 32 bytes aligned region so that the SAU can be programmed to
- * just set this region as Non-Secure Callable.
- */
- CMSE_VENEER CMSE_VENEER_REGION_START CMSE_VENEER_REGION_SIZE {
- *(Veneer$$CMSE)
- }
-}
-
LR_NS_PARTITION NS_PARTITION_START {
/* Reserved place for NS application.
* No code will be placed here, just address of this region is used in the
diff --git a/platform/ext/common/gcc/tfm_common_s.ld b/platform/ext/common/gcc/tfm_common_s.ld
index d3aada3..a7eb8db 100644
--- a/platform/ext/common/gcc/tfm_common_s.ld
+++ b/platform/ext/common/gcc/tfm_common_s.ld
@@ -29,9 +29,6 @@
#if defined(S_CODE_SRAM_ALIAS_BASE)
CODE_RAM (rwx) : ORIGIN = S_CODE_SRAM_ALIAS_BASE, LENGTH = TOTAL_CODE_SRAM_SIZE
#endif
-#ifndef TFM_MULTI_CORE_TOPOLOGY
- VENEERS (rx) : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE
-#endif
#if defined(PSA_PROXY_SHARED_MEMORY_BASE)
PSA_PROXY_SHARED_MEMORY_RAM (rw) : ORIGIN = PSA_PROXY_SHARED_MEMORY_BASE, LENGTH = PSA_PROXY_SHARED_MEMORY_SIZE
@@ -55,10 +52,25 @@
__vectors_start__ = .;
KEEP(*(.vectors))
__vectors_end__ = .;
- *startup*(.text*)
- . = ALIGN(4);
} > FLASH
+#ifndef TFM_MULTI_CORE_TOPOLOGY
+ ASSERT(. <= ADDR(.TFM_VECTORS) + S_CODE_VECTOR_TABLE_SIZE, ".TFM_VECTORS section size overflow.")
+ . = ADDR(.TFM_VECTORS) + S_CODE_VECTOR_TABLE_SIZE;
+ /*
+ * Place the CMSE Veneers (containing the SG instruction) after the code, in
+ * a separate 32 bytes aligned region so that the SAU can programmed to just
+ * set this region as Non-Secure Callable.
+ */
+ .gnu.sgstubs ALIGN(32) : ALIGN(32)
+ {
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ } > FLASH
+ Image$$ER_VENEER$$Base = ADDR(.gnu.sgstubs);
+ Image$$VENEER_ALIGN$$Limit = ADDR(.gnu.sgstubs) + SIZEOF(.gnu.sgstubs);
+#endif
+
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
@@ -200,6 +212,7 @@
.ER_TFM_CODE : ALIGN(4)
{
+ *startup*(.text*)
*libplatform_s*:*(.text*)
*libtfm_spm*:*(.text*)
@@ -556,21 +569,6 @@
} > RAM AT> FLASH
#endif
-#ifndef TFM_MULTI_CORE_TOPOLOGY
- /*
- * Place the CMSE Veneers (containing the SG instruction) after the code, in a
- * separate 32 bytes aligned region so that the SAU can programmed to just set
- * this region as Non-Secure Callable.
- */
- .gnu.sgstubs : ALIGN(32)
- {
- *(.gnu.sgstubs*)
- . = ALIGN(32);
- } > VENEERS AT> VENEERS
- Load$$LR$$LR_VENEER$$Base = ADDR(.gnu.sgstubs);
- Load$$LR$$LR_VENEER$$Limit = ADDR(.gnu.sgstubs) + SIZEOF(.gnu.sgstubs);
-#endif
-
Load$$LR$$LR_NS_PARTITION$$Base = NS_PARTITION_START;
#ifdef BL2
diff --git a/platform/ext/common/gcc/tfm_isolation_l3.ld.template b/platform/ext/common/gcc/tfm_isolation_l3.ld.template
index 0ab9b07..88bfd2e 100644
--- a/platform/ext/common/gcc/tfm_isolation_l3.ld.template
+++ b/platform/ext/common/gcc/tfm_isolation_l3.ld.template
@@ -31,7 +31,6 @@
#if defined(S_CODE_SRAM_ALIAS_BASE)
CODE_RAM (rwx) : ORIGIN = S_CODE_SRAM_ALIAS_BASE, LENGTH = TOTAL_CODE_SRAM_SIZE
#endif
- VENEERS (rx) : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE
}
__heap_size__ = S_HEAP_SIZE;
@@ -45,15 +44,34 @@
SECTIONS
{
+ /* Start address of the code. */
+ Image$$PT_RO_START$$Base = ADDR(.TFM_VECTORS);
+
.TFM_VECTORS : ALIGN(4)
{
__vectors_start__ = .;
KEEP(*(.vectors))
__vectors_end__ = .;
- *startup*(.text*)
. = ALIGN(4);
} > FLASH
+#ifndef TFM_MULTI_CORE_TOPOLOGY
+ ASSERT(. <= ADDR(.TFM_VECTORS) + S_CODE_VECTOR_TABLE_SIZE, ".TFM_VECTORS section size overflow.")
+ . = ADDR(.TFM_VECTORS) + S_CODE_VECTOR_TABLE_SIZE;
+ /*
+ * Place the CMSE Veneers (containing the SG instruction) after the code, in
+ * a separate 32 bytes aligned region so that the SAU can programmed to just
+ * set this region as Non-Secure Callable.
+ */
+ .gnu.sgstubs ALIGN(32) : ALIGN(32)
+ {
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ } > FLASH
+ Image$$ER_VENEER$$Base = ADDR(.gnu.sgstubs);
+ Image$$VENEER_ALIGN$$Limit = ADDR(.gnu.sgstubs) + SIZEOF(.gnu.sgstubs);
+#endif
+
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
@@ -85,10 +103,6 @@
__zero_table_end__ = .;
} > FLASH
- /* Position tag */
- . = ALIGN(32);
- Image$$PT_RO_START$$Base = .;
-
/**** Section for holding partition RO load data */
.TFM_SP_LOAD_LIST : ALIGN(4)
{
@@ -152,8 +166,24 @@
{% endfor %}
/**** APPLICATION RoT RO CODE + data ends here */
+#if defined(S_CODE_SRAM_ALIAS_BASE)
+ .ER_EFLASH_DRIVER_RO : ALIGN(4)
+ {
+ *Driver_GFC100_EFlash.o(.text*)
+ *Driver_GFC100_EFlash.o(.rodata*)
+ *gfc100_eflash_drv.o(.text*)
+ *gfc100_eflash_drv.o(.rodata*)
+ *musca_b1_eflash_drv.o(.text*)
+ *musca_b1_eflash_drv.o(.rodata*)
+ . = ALIGN(4); /* This alignment is needed to make the section size 4 bytes aligned */
+ } > CODE_RAM AT > FLASH
+ Image$$ER_EFLASH_DRIVER_RO$$Base = ADDR(.ER_EFLASH_DRIVER_RO);
+ Image$$ER_EFLASH_DRIVER_RO$$Limit = ADDR(.ER_EFLASH_DRIVER_RO) + SIZEOF(.ER_EFLASH_DRIVER_RO);
+#endif
+
.ER_TFM_CODE : ALIGN(4)
{
+ *startup*(.text*)
*libplatform_s*:*(.text*)
*libtfm_spm*:*(.text*)
@@ -197,21 +227,6 @@
. = ALIGN(32);
Image$$PT_RO_END$$Base = .;
-#if defined(S_CODE_SRAM_ALIAS_BASE)
- .ER_EFLASH_DRIVER_RO : ALIGN(4)
- {
- *Driver_GFC100_EFlash.o(.text*)
- *Driver_GFC100_EFlash.o(.rodata*)
- *gfc100_eflash_drv.o(.text*)
- *gfc100_eflash_drv.o(.rodata*)
- *musca_b1_eflash_drv.o(.text*)
- *musca_b1_eflash_drv.o(.rodata*)
- . = ALIGN(4); /* This alignment is needed to make the section size 4 bytes aligned */
- } > CODE_RAM AT > FLASH
- Image$$ER_EFLASH_DRIVER_RO$$Base = ADDR(.ER_EFLASH_DRIVER_RO);
- Image$$ER_EFLASH_DRIVER_RO$$Limit = ADDR(.ER_EFLASH_DRIVER_RO) + SIZEOF(.ER_EFLASH_DRIVER_RO);
-#endif
-
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -474,19 +489,6 @@
Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA);
Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS);
- /*
- * Place the CMSE Veneers (containing the SG instruction) after the code, in a
- * separate 32 bytes aligned region so that the SAU can programmed to just set
- * this region as Non-Secure Callable.
- */
- .gnu.sgstubs : ALIGN(32)
- {
- *(.gnu.sgstubs*)
- . = ALIGN(32);
- } > VENEERS AT> VENEERS
- Load$$LR$$LR_VENEER$$Base = ADDR(.gnu.sgstubs);
- Load$$LR$$LR_VENEER$$Limit = ADDR(.gnu.sgstubs) + SIZEOF(.gnu.sgstubs);
-
Load$$LR$$LR_NS_PARTITION$$Base = NS_PARTITION_START;
#ifdef BL2
diff --git a/platform/ext/target/arm/corstone1000/Device/Source/gcc/startup_corstone1000_s.S b/platform/ext/target/arm/corstone1000/Device/Source/gcc/startup_corstone1000_s.S
index dd7a8de..fd1bac8 100644
--- a/platform/ext/target/arm/corstone1000/Device/Source/gcc/startup_corstone1000_s.S
+++ b/platform/ext/target/arm/corstone1000/Device/Source/gcc/startup_corstone1000_s.S
@@ -21,7 +21,7 @@
.syntax unified
.arch armv6-m
- .section .vectors
+ .section .vectors, "a"
.align 2
.globl __Vectors
__Vectors:
diff --git a/platform/ext/target/arm/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S b/platform/ext/target/arm/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S
index e151ab6..2346d7d 100644
--- a/platform/ext/target/arm/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S
+++ b/platform/ext/target/arm/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S
@@ -22,7 +22,7 @@
.syntax unified
.arch armv8-m.base
- .section .vectors
+ .section .vectors, "a"
.align 2
.globl __Vectors
__Vectors:
diff --git a/platform/ext/target/arm/mps2/an519/partition/region_defs.h b/platform/ext/target/arm/mps2/an519/partition/region_defs.h
index 4762e82..b084ab7 100755
--- a/platform/ext/target/arm/mps2/an519/partition/region_defs.h
+++ b/platform/ext/target/arm/mps2/an519/partition/region_defs.h
@@ -87,8 +87,6 @@
#define IMAGE_NS_CODE_SIZE \
(FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-#define CMSE_VENEER_REGION_SIZE (0x340)
-
/* Alias definitions for secure and non-secure areas*/
#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x))
#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
@@ -100,15 +98,15 @@
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
-#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
#define S_DATA_START (S_RAM_ALIAS(0x0))
#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
-/* CMSE Veneers region */
-#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+/* Size of vector table: 139 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x230)
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
diff --git a/platform/ext/target/arm/mps2/an519/target_cfg.c b/platform/ext/target/arm/mps2/an519/target_cfg.c
index 3548cc9..e8940e2 100644
--- a/platform/ext/target/arm/mps2/an519/target_cfg.c
+++ b/platform/ext/target/arm/mps2/an519/target_cfg.c
@@ -26,8 +26,8 @@
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
#ifdef BL2
REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
#endif /* BL2 */
@@ -45,10 +45,10 @@
NS_PARTITION_SIZE - 1,
.veneer_base =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
.veneer_limit =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
#ifdef BL2
.secondary_partition_base =
@@ -261,8 +261,8 @@
false,
},
{
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
true,
},
{
diff --git a/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c b/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c
index 4594457..ccd4de1 100644
--- a/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c
@@ -26,8 +26,8 @@
static uint32_t n_configured_regions = 0;
struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base);
@@ -45,8 +45,8 @@
/* Veneer region */
{
0, /* will be updated before using */
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
MPU_ARMV8M_XN_EXEC_OK,
MPU_ARMV8M_AP_RO_PRIV_UNPRIV,
diff --git a/platform/ext/target/arm/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S b/platform/ext/target/arm/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S
index 5f2e23a..85e35dd 100644
--- a/platform/ext/target/arm/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S
+++ b/platform/ext/target/arm/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S
@@ -22,7 +22,7 @@
.syntax unified
.arch armv8-m.main
- .section .vectors
+ .section .vectors, "a"
.align 2
.globl __Vectors
__Vectors:
diff --git a/platform/ext/target/arm/mps2/an521/partition/region_defs.h b/platform/ext/target/arm/mps2/an521/partition/region_defs.h
index 4a01eda..cfeac49 100755
--- a/platform/ext/target/arm/mps2/an521/partition/region_defs.h
+++ b/platform/ext/target/arm/mps2/an521/partition/region_defs.h
@@ -87,8 +87,6 @@
#define IMAGE_NS_CODE_SIZE \
(FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-#define CMSE_VENEER_REGION_SIZE (0x340)
-
/* Alias definitions for secure and non-secure areas*/
#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x))
#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
@@ -100,16 +98,16 @@
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
-#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
+/* Size of vector table: 139 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x230)
+
#define S_DATA_START (S_RAM_ALIAS(0x0))
#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
-/* CMSE Veneers region */
-#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
-
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
(NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
diff --git a/platform/ext/target/arm/mps2/an521/target_cfg.c b/platform/ext/target/arm/mps2/an521/target_cfg.c
index 0f94da2..6070e53 100644
--- a/platform/ext/target/arm/mps2/an521/target_cfg.c
+++ b/platform/ext/target/arm/mps2/an521/target_cfg.c
@@ -30,8 +30,9 @@
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
+
#ifdef BL2
REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
#endif /* BL2 */
@@ -48,8 +49,8 @@
(uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
NS_PARTITION_SIZE - 1,
- .veneer_base = (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- .veneer_limit = (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ .veneer_base = (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ .veneer_limit = (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
#ifdef BL2
.secondary_partition_base =
@@ -327,8 +328,8 @@
false,
},
{
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
true,
},
{
diff --git a/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c b/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c
index ea7687a..c326f4f 100644
--- a/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c
@@ -27,8 +27,6 @@
struct mpu_armv8m_dev_t dev_mpu_s = {MPU_BASE};
#if TFM_LVL == 3
static uint32_t idx_boundary_handle = 0;
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
REGION_DECLARE(Image$$, PT_RO_START, $$Base);
REGION_DECLARE(Image$$, PT_RO_END, $$Base);
REGION_DECLARE(Image$$, PT_PRIV_RWZI_START, $$Base);
@@ -37,15 +35,6 @@
const static struct mpu_armv8m_region_cfg_t isolation_regions[] = {
{
0, /* will be updated before using */
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
- MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
- MPU_ARMV8M_XN_EXEC_OK,
- MPU_ARMV8M_AP_RO_PRIV_UNPRIV,
- MPU_ARMV8M_SH_NONE,
- },
- {
- 0, /* will be updated before using */
(uint32_t)®ION_NAME(Image$$, PT_RO_START, $$Base),
(uint32_t)®ION_NAME(Image$$, PT_RO_END, $$Base),
MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
@@ -68,8 +57,8 @@
};
#else /* TFM_LVL == 3 */
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base);
@@ -87,8 +76,8 @@
/* Veneer region */
{
0, /* will be updated before using */
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
MPU_ARMV8M_XN_EXEC_OK,
MPU_ARMV8M_AP_RO_PRIV_UNPRIV,
diff --git a/platform/ext/target/arm/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S b/platform/ext/target/arm/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S
index 18a4fd4..77e4c6d 100644
--- a/platform/ext/target/arm/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S
+++ b/platform/ext/target/arm/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S
@@ -24,7 +24,7 @@
.syntax unified
.arch armv8-m.main
- .section .vectors
+ .section .vectors, "a"
.align 2
.globl __Vectors
__Vectors:
diff --git a/platform/ext/target/arm/mps3/an524/partition/region_defs.h b/platform/ext/target/arm/mps3/an524/partition/region_defs.h
index 4637fa5..a43c3ba 100755
--- a/platform/ext/target/arm/mps3/an524/partition/region_defs.h
+++ b/platform/ext/target/arm/mps3/an524/partition/region_defs.h
@@ -76,8 +76,6 @@
#define IMAGE_NS_CODE_SIZE \
(FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-#define CMSE_VENEER_REGION_SIZE (0x340)
-
/* Alias definitions for secure and non-secure areas*/
#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x))
#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
@@ -89,7 +87,7 @@
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
-#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
/* ISRAM0 and ISRAM1 are assigned to Secure data */
@@ -97,8 +95,8 @@
#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2 + (TOTAL_RAM_SIZE / 4))
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
-/* CMSE Veneers region */
-#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+/* Size of vector table: 143 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x240)
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
diff --git a/platform/ext/target/arm/mps3/an524/target_cfg.c b/platform/ext/target/arm/mps3/an524/target_cfg.c
index ae42559..f193019 100644
--- a/platform/ext/target/arm/mps3/an524/target_cfg.c
+++ b/platform/ext/target/arm/mps3/an524/target_cfg.c
@@ -39,8 +39,8 @@
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
#ifdef BL2
REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
#endif /* BL2 */
@@ -58,10 +58,10 @@
NS_PARTITION_SIZE - 1,
.veneer_base =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
.veneer_limit =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
#ifdef BL2
.secondary_partition_base =
diff --git a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_bl2.c b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_bl2.c
index cdab22b..020547e 100644
--- a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_bl2.c
+++ b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_bl2.c
@@ -174,8 +174,8 @@
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
-extern const pFunc __VECTOR_TABLE[496];
- const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+extern const pFunc __VECTOR_TABLE[];
+ const pFunc __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14: NMI Handler */
diff --git a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_ns.c b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_ns.c
index db4061a..b839bfc 100644
--- a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_ns.c
+++ b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_ns.c
@@ -182,8 +182,8 @@
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
-extern const pFunc __VECTOR_TABLE[496];
- const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+extern const pFunc __VECTOR_TABLE[];
+ const pFunc __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__MSP_INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14: NMI Handler */
diff --git a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c
index 567e12f..371b72c 100644
--- a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c
+++ b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c
@@ -179,8 +179,8 @@
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
-extern const pFunc __VECTOR_TABLE[496];
- const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+extern const pFunc __VECTOR_TABLE[];
+ const pFunc __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__MSP_INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14: NMI Handler */
diff --git a/platform/ext/target/arm/mps3/an547/partition/region_defs.h b/platform/ext/target/arm/mps3/an547/partition/region_defs.h
index 6638612..0732bf3 100755
--- a/platform/ext/target/arm/mps3/an547/partition/region_defs.h
+++ b/platform/ext/target/arm/mps3/an547/partition/region_defs.h
@@ -83,14 +83,12 @@
#define IMAGE_NS_CODE_SIZE \
(FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-#define CMSE_VENEER_REGION_SIZE (0x340)
-
/* Secure regions */
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
/* Secure Code stored in Code SRAM */
#define S_CODE_START ((SRAM_BASE_S) + (S_IMAGE_PRIMARY_AREA_OFFSET))
-#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
/* Secure Data stored in DTCM */
@@ -98,8 +96,8 @@
#define S_DATA_SIZE (DTCM_BLK_SIZE * DTCM_BLK_NUM)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
-/* CMSE Veneers region */
-#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+/* Size of vector table: 146 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x24C)
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
diff --git a/platform/ext/target/arm/mps3/an547/target_cfg.c b/platform/ext/target/arm/mps3/an547/target_cfg.c
index b30d5c8..23650c3 100644
--- a/platform/ext/target/arm/mps3/an547/target_cfg.c
+++ b/platform/ext/target/arm/mps3/an547/target_cfg.c
@@ -31,8 +31,8 @@
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
const struct memory_region_limits memory_regions = {
.non_secure_code_start =
@@ -46,8 +46,8 @@
(uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
NS_PARTITION_SIZE - 1,
- .veneer_base = (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- .veneer_limit = (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ .veneer_base = (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ .veneer_limit = (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
};
/* Configures the RAM region to NS callable in sacfg block's nsccfg register */
diff --git a/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c b/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c
index adc4131..6ab92cb 100644
--- a/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c
@@ -27,8 +27,8 @@
static uint32_t n_configured_regions = 0;
struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base);
@@ -46,8 +46,8 @@
/* Veneer region */
{
0, /* will be updated before using */
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
MPU_ARMV8M_XN_EXEC_OK,
MPU_ARMV8M_AP_RO_PRIV_UNPRIV,
diff --git a/platform/ext/target/arm/mps3/an552/device/source/startup_an552_bl2.c b/platform/ext/target/arm/mps3/an552/device/source/startup_an552_bl2.c
index cdab22b..020547e 100644
--- a/platform/ext/target/arm/mps3/an552/device/source/startup_an552_bl2.c
+++ b/platform/ext/target/arm/mps3/an552/device/source/startup_an552_bl2.c
@@ -174,8 +174,8 @@
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
-extern const pFunc __VECTOR_TABLE[496];
- const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+extern const pFunc __VECTOR_TABLE[];
+ const pFunc __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14: NMI Handler */
diff --git a/platform/ext/target/arm/mps3/an552/device/source/startup_an552_ns.c b/platform/ext/target/arm/mps3/an552/device/source/startup_an552_ns.c
index db4061a..b839bfc 100644
--- a/platform/ext/target/arm/mps3/an552/device/source/startup_an552_ns.c
+++ b/platform/ext/target/arm/mps3/an552/device/source/startup_an552_ns.c
@@ -182,8 +182,8 @@
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
-extern const pFunc __VECTOR_TABLE[496];
- const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+extern const pFunc __VECTOR_TABLE[];
+ const pFunc __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__MSP_INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14: NMI Handler */
diff --git a/platform/ext/target/arm/mps3/an552/device/source/startup_an552_s.c b/platform/ext/target/arm/mps3/an552/device/source/startup_an552_s.c
index 567e12f..371b72c 100644
--- a/platform/ext/target/arm/mps3/an552/device/source/startup_an552_s.c
+++ b/platform/ext/target/arm/mps3/an552/device/source/startup_an552_s.c
@@ -179,8 +179,8 @@
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
-extern const pFunc __VECTOR_TABLE[496];
- const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+extern const pFunc __VECTOR_TABLE[];
+ const pFunc __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__MSP_INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14: NMI Handler */
diff --git a/platform/ext/target/arm/mps3/an552/partition/region_defs.h b/platform/ext/target/arm/mps3/an552/partition/region_defs.h
index 6638612..0732bf3 100755
--- a/platform/ext/target/arm/mps3/an552/partition/region_defs.h
+++ b/platform/ext/target/arm/mps3/an552/partition/region_defs.h
@@ -83,14 +83,12 @@
#define IMAGE_NS_CODE_SIZE \
(FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-#define CMSE_VENEER_REGION_SIZE (0x340)
-
/* Secure regions */
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
/* Secure Code stored in Code SRAM */
#define S_CODE_START ((SRAM_BASE_S) + (S_IMAGE_PRIMARY_AREA_OFFSET))
-#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
/* Secure Data stored in DTCM */
@@ -98,8 +96,8 @@
#define S_DATA_SIZE (DTCM_BLK_SIZE * DTCM_BLK_NUM)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
-/* CMSE Veneers region */
-#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+/* Size of vector table: 146 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x24C)
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
diff --git a/platform/ext/target/arm/mps3/an552/target_cfg.c b/platform/ext/target/arm/mps3/an552/target_cfg.c
index 0afc3d6..a01bcdc 100644
--- a/platform/ext/target/arm/mps3/an552/target_cfg.c
+++ b/platform/ext/target/arm/mps3/an552/target_cfg.c
@@ -31,8 +31,8 @@
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
const struct memory_region_limits memory_regions = {
.non_secure_code_start =
@@ -46,8 +46,8 @@
(uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
NS_PARTITION_SIZE - 1,
- .veneer_base = (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- .veneer_limit = (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ .veneer_base = (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ .veneer_limit = (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
};
/* Configures the RAM region to NS callable in sacfg block's nsccfg register */
diff --git a/platform/ext/target/arm/mps3/an552/tfm_hal_isolation.c b/platform/ext/target/arm/mps3/an552/tfm_hal_isolation.c
index c020e68..5cdf62a 100644
--- a/platform/ext/target/arm/mps3/an552/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/mps3/an552/tfm_hal_isolation.c
@@ -27,8 +27,8 @@
static uint32_t n_configured_regions = 0;
struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base);
@@ -46,8 +46,8 @@
/* Veneer region */
{
0, /* will be updated before using */
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
MPU_ARMV8M_XN_EXEC_OK,
MPU_ARMV8M_AP_RO_PRIV_UNPRIV,
diff --git a/platform/ext/target/arm/mps3/corstone_polaris/device/source/startup_corstone_polaris_bl2.c b/platform/ext/target/arm/mps3/corstone_polaris/device/source/startup_corstone_polaris_bl2.c
index e65837e..62f495b 100644
--- a/platform/ext/target/arm/mps3/corstone_polaris/device/source/startup_corstone_polaris_bl2.c
+++ b/platform/ext/target/arm/mps3/corstone_polaris/device/source/startup_corstone_polaris_bl2.c
@@ -172,8 +172,8 @@
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
-extern const pFunc __VECTOR_TABLE[496];
- const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+extern const pFunc __VECTOR_TABLE[];
+ const pFunc __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14: NMI Handler */
diff --git a/platform/ext/target/arm/mps3/corstone_polaris/device/source/startup_corstone_polaris_ns.c b/platform/ext/target/arm/mps3/corstone_polaris/device/source/startup_corstone_polaris_ns.c
index 1efe8a7..0957c82 100644
--- a/platform/ext/target/arm/mps3/corstone_polaris/device/source/startup_corstone_polaris_ns.c
+++ b/platform/ext/target/arm/mps3/corstone_polaris/device/source/startup_corstone_polaris_ns.c
@@ -180,8 +180,8 @@
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
-extern const pFunc __VECTOR_TABLE[496];
- const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+extern const pFunc __VECTOR_TABLE[];
+ const pFunc __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__MSP_INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14: NMI Handler */
diff --git a/platform/ext/target/arm/mps3/corstone_polaris/device/source/startup_corstone_polaris_s.c b/platform/ext/target/arm/mps3/corstone_polaris/device/source/startup_corstone_polaris_s.c
index b76536b..16973db 100644
--- a/platform/ext/target/arm/mps3/corstone_polaris/device/source/startup_corstone_polaris_s.c
+++ b/platform/ext/target/arm/mps3/corstone_polaris/device/source/startup_corstone_polaris_s.c
@@ -177,8 +177,8 @@
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
-extern const pFunc __VECTOR_TABLE[496];
- const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+extern const pFunc __VECTOR_TABLE[];
+ const pFunc __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__MSP_INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14: NMI Handler */
diff --git a/platform/ext/target/arm/mps3/corstone_polaris/partition/region_defs.h b/platform/ext/target/arm/mps3/corstone_polaris/partition/region_defs.h
index 6638612..0732bf3 100644
--- a/platform/ext/target/arm/mps3/corstone_polaris/partition/region_defs.h
+++ b/platform/ext/target/arm/mps3/corstone_polaris/partition/region_defs.h
@@ -83,14 +83,12 @@
#define IMAGE_NS_CODE_SIZE \
(FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-#define CMSE_VENEER_REGION_SIZE (0x340)
-
/* Secure regions */
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
/* Secure Code stored in Code SRAM */
#define S_CODE_START ((SRAM_BASE_S) + (S_IMAGE_PRIMARY_AREA_OFFSET))
-#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
/* Secure Data stored in DTCM */
@@ -98,8 +96,8 @@
#define S_DATA_SIZE (DTCM_BLK_SIZE * DTCM_BLK_NUM)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
-/* CMSE Veneers region */
-#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+/* Size of vector table: 146 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x24C)
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
diff --git a/platform/ext/target/arm/mps3/corstone_polaris/target_cfg.c b/platform/ext/target/arm/mps3/corstone_polaris/target_cfg.c
index 7221543..dd1d14b 100644
--- a/platform/ext/target/arm/mps3/corstone_polaris/target_cfg.c
+++ b/platform/ext/target/arm/mps3/corstone_polaris/target_cfg.c
@@ -31,8 +31,8 @@
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
const struct memory_region_limits memory_regions = {
.non_secure_code_start =
@@ -46,8 +46,8 @@
(uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
NS_PARTITION_SIZE - 1,
- .veneer_base = (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- .veneer_limit = (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ .veneer_base = (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ .veneer_limit = (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
};
/* Configures the RAM region to NS callable in sacfg block's nsccfg register */
diff --git a/platform/ext/target/arm/mps3/corstone_polaris/tfm_hal_isolation.c b/platform/ext/target/arm/mps3/corstone_polaris/tfm_hal_isolation.c
index 576f4e8..34bfca0 100644
--- a/platform/ext/target/arm/mps3/corstone_polaris/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/mps3/corstone_polaris/tfm_hal_isolation.c
@@ -27,8 +27,8 @@
static uint32_t n_configured_regions = 0;
struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base);
@@ -46,8 +46,8 @@
/* Veneer region */
{
0, /* will be updated before using */
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
MPU_ARMV8M_XN_EXEC_OK,
MPU_ARMV8M_AP_RO_PRIV_UNPRIV,
diff --git a/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/gcc/startup_musca_b1_secure_enclave_s.S b/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/gcc/startup_musca_b1_secure_enclave_s.S
index a62adbf..50f8f28 100644
--- a/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/gcc/startup_musca_b1_secure_enclave_s.S
+++ b/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/gcc/startup_musca_b1_secure_enclave_s.S
@@ -22,7 +22,7 @@
.syntax unified
.arch armv6-m
- .section .vectors
+ .section .vectors, "a"
.align 2
.globl __Vectors
__Vectors:
diff --git a/platform/ext/target/arm/musca_b1/sse_200/Device/Source/gcc/startup_cmsdk_musca_s.S b/platform/ext/target/arm/musca_b1/sse_200/Device/Source/gcc/startup_cmsdk_musca_s.S
index 226f7ed..6435c45 100644
--- a/platform/ext/target/arm/musca_b1/sse_200/Device/Source/gcc/startup_cmsdk_musca_s.S
+++ b/platform/ext/target/arm/musca_b1/sse_200/Device/Source/gcc/startup_cmsdk_musca_s.S
@@ -22,7 +22,7 @@
.syntax unified
.arch armv8-m.main
- .section .vectors
+ .section .vectors, "a"
.align 2
.globl __Vectors
__Vectors:
diff --git a/platform/ext/target/arm/musca_b1/sse_200/partition/region_defs.h b/platform/ext/target/arm/musca_b1/sse_200/partition/region_defs.h
index fad6db3..fc9eb20 100755
--- a/platform/ext/target/arm/musca_b1/sse_200/partition/region_defs.h
+++ b/platform/ext/target/arm/musca_b1/sse_200/partition/region_defs.h
@@ -86,8 +86,6 @@
#define IMAGE_NS_CODE_SIZE \
(FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-#define CMSE_VENEER_REGION_SIZE (0x380)
-
/* Alias definitions for secure and non-secure areas*/
#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x))
#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
@@ -99,15 +97,15 @@
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
-#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
#define S_DATA_START (S_RAM_ALIAS(0x0))
#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
-/* CMSE Veneers region */
-#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+/* Size of vector table: 143 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x240)
/* Shared memory used by PSA Proxy partition */
#ifdef TFM_PARTITION_PSA_PROXY
diff --git a/platform/ext/target/arm/musca_b1/sse_200/target_cfg.c b/platform/ext/target/arm/musca_b1/sse_200/target_cfg.c
index 033d283..e903cdd 100755
--- a/platform/ext/target/arm/musca_b1/sse_200/target_cfg.c
+++ b/platform/ext/target/arm/musca_b1/sse_200/target_cfg.c
@@ -25,8 +25,8 @@
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
#ifdef BL2
REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
#endif /* BL2 */
@@ -44,10 +44,10 @@
NS_PARTITION_SIZE - 1,
.veneer_base =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
.veneer_limit =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
};
/* Allows software, via SAU, to define the code region as a NSC */
diff --git a/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c b/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c
index c2dcc81..c5d2c49 100644
--- a/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c
@@ -27,8 +27,6 @@
struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
#if TFM_LVL == 3
static uint32_t idx_boundary_handle = 0;
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
REGION_DECLARE(Image$$, PT_RO_START, $$Base);
REGION_DECLARE(Image$$, PT_RO_END, $$Base);
REGION_DECLARE(Image$$, PT_PRIV_RWZI_START, $$Base);
@@ -37,15 +35,6 @@
static struct mpu_armv8m_region_cfg_t isolation_regions[] = {
{
0, /* will be updated before using */
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
- MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
- MPU_ARMV8M_XN_EXEC_OK,
- MPU_ARMV8M_AP_RO_PRIV_UNPRIV,
- MPU_ARMV8M_SH_NONE,
- },
- {
- 0, /* will be updated before using */
(uint32_t)®ION_NAME(Image$$, PT_RO_START, $$Base),
(uint32_t)®ION_NAME(Image$$, PT_RO_END, $$Base),
MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
diff --git a/platform/ext/target/arm/musca_s1/Device/Source/gcc/startup_cmsdk_musca_s.S b/platform/ext/target/arm/musca_s1/Device/Source/gcc/startup_cmsdk_musca_s.S
index 6cd30d9..aad6e6e 100644
--- a/platform/ext/target/arm/musca_s1/Device/Source/gcc/startup_cmsdk_musca_s.S
+++ b/platform/ext/target/arm/musca_s1/Device/Source/gcc/startup_cmsdk_musca_s.S
@@ -22,7 +22,7 @@
.syntax unified
.arch armv8-m.main
- .section .vectors
+ .section .vectors, "a"
.align 2
.globl __Vectors
__Vectors:
diff --git a/platform/ext/target/arm/musca_s1/partition/region_defs.h b/platform/ext/target/arm/musca_s1/partition/region_defs.h
index f9b0887..4425187 100755
--- a/platform/ext/target/arm/musca_s1/partition/region_defs.h
+++ b/platform/ext/target/arm/musca_s1/partition/region_defs.h
@@ -87,8 +87,6 @@
#define IMAGE_NS_CODE_SIZE \
(FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-#define CMSE_VENEER_REGION_SIZE (0x340)
-
/* Alias definitions for secure and non-secure areas*/
#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x))
#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
@@ -100,7 +98,7 @@
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
-#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
#define S_DATA_START (S_RAM_ALIAS(0x0))
@@ -108,7 +106,9 @@
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
/* CMSE Veneers region */
-#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+#define CMSE_VENEER_REGION_START (S_CODE_START + S_CODE_VECTOR_TABLE_SIZE)
+/* Size of vector table: 111 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x1C0)
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
diff --git a/platform/ext/target/arm/musca_s1/target_cfg.c b/platform/ext/target/arm/musca_s1/target_cfg.c
index 81431dc..ae4bc04 100644
--- a/platform/ext/target/arm/musca_s1/target_cfg.c
+++ b/platform/ext/target/arm/musca_s1/target_cfg.c
@@ -29,8 +29,8 @@
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
const struct memory_region_limits memory_regions = {
@@ -46,10 +46,10 @@
NS_PARTITION_SIZE - 1,
.veneer_base =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
.veneer_limit =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
};
/* Allows software, via SAU, to define the code region as a NSC */
diff --git a/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S b/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S
index ebf5294..f7f2830 100644
--- a/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S
+++ b/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S
@@ -31,7 +31,7 @@
.syntax unified
.arch armv6-m
- .section .vectors
+ .section .vectors, "a"
.align 2
.globl __Vectors
__Vectors:
diff --git a/platform/ext/target/cypress/psoc64/partition/region_defs.h b/platform/ext/target/cypress/psoc64/partition/region_defs.h
index 5307ee0..e41ecac 100644
--- a/platform/ext/target/cypress/psoc64/partition/region_defs.h
+++ b/platform/ext/target/cypress/psoc64/partition/region_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 ARM Limited. All rights reserved.
+ * Copyright (c) 2017-2021 ARM Limited. All rights reserved.
* Copyright (c) 2019-2021 Cypress Semiconductor Corp. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -140,6 +140,9 @@
#define S_RAM_CODE_OFFSET (S_DATA_PRIV_OFFSET + S_PRIV_DATA_SIZE)
#define S_RAM_CODE_START S_RAM_ALIAS(S_RAM_CODE_OFFSET)
+/* Size of vector table: 31 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x80)
+
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
(NS_IMAGE_PRIMARY_PARTITION_OFFSET + CYBL_HEADER_SIZE)
diff --git a/platform/ext/target/nuvoton/common/tfm_hal_isolation.c b/platform/ext/target/nuvoton/common/tfm_hal_isolation.c
index f5485da..79bfa2e 100644
--- a/platform/ext/target/nuvoton/common/tfm_hal_isolation.c
+++ b/platform/ext/target/nuvoton/common/tfm_hal_isolation.c
@@ -25,8 +25,8 @@
#define MPU_REGION_SP_META_PTR 7
#endif /* TFM_SP_META_PTR_ENABLE */
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base);
@@ -44,8 +44,8 @@
/* Veneer region */
{
MPU_REGION_VENEERS,
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
MPU_ARMV8M_XN_EXEC_OK,
MPU_ARMV8M_AP_RO_PRIV_UNPRIV,
diff --git a/platform/ext/target/nuvoton/m2351/device/source/gcc/startup_cmsdk_m2351_s.S b/platform/ext/target/nuvoton/m2351/device/source/gcc/startup_cmsdk_m2351_s.S
index 848d3af..66030ae 100644
--- a/platform/ext/target/nuvoton/m2351/device/source/gcc/startup_cmsdk_m2351_s.S
+++ b/platform/ext/target/nuvoton/m2351/device/source/gcc/startup_cmsdk_m2351_s.S
@@ -1,5 +1,5 @@
;/*
-; * Copyright (c) 2009-2018 ARM Limited
+; * Copyright (c) 2009-2021 ARM Limited
; * Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved.
; * Licensed under the Apache License, Version 2.0 (the "License");
@@ -23,7 +23,7 @@
.syntax unified
.arch armv8-m.base
- .section .vectors
+ .section .vectors, "a"
.align 2
.globl __Vectors
__Vectors:
diff --git a/platform/ext/target/nuvoton/m2351/partition/region_defs.h b/platform/ext/target/nuvoton/m2351/partition/region_defs.h
index e61a796..ee3705f 100644
--- a/platform/ext/target/nuvoton/m2351/partition/region_defs.h
+++ b/platform/ext/target/nuvoton/m2351/partition/region_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
* Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -72,8 +72,6 @@
#define IMAGE_S_CODE_SIZE (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
#define IMAGE_NS_CODE_SIZE (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-#define CMSE_VENEER_REGION_SIZE (0x340)
-
/* Alias definitions for secure and non-secure areas*/
#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x))
#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
@@ -85,15 +83,16 @@
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) /* 0x8400 */
#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) /* 0x8400 */
-#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
#define S_DATA_START (S_RAM_ALIAS(0x0))
#define S_DATA_SIZE (64 * 1024)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
-/* CMSE Veneers region */
-#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+
+/* Size of vector table: 117 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x1D8)
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
diff --git a/platform/ext/target/nuvoton/m2351/target_cfg.c b/platform/ext/target/nuvoton/m2351/target_cfg.c
index efd1b23..1b9cb91 100644
--- a/platform/ext/target/nuvoton/m2351/target_cfg.c
+++ b/platform/ext/target/nuvoton/m2351/target_cfg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited
+ * Copyright (c) 2018-2021 Arm Limited
* Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,8 +29,8 @@
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
#ifdef BL2
REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
#endif /* BL2 */
@@ -48,10 +48,10 @@
NS_PARTITION_SIZE - 1,
.veneer_base =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
.veneer_limit =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
#ifdef BL2
.secondary_partition_base =
@@ -193,8 +193,8 @@
false,
},
{
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
true,
},
{
diff --git a/platform/ext/target/nuvoton/m2354/device/source/gcc/startup_cmsdk_m2354_s.S b/platform/ext/target/nuvoton/m2354/device/source/gcc/startup_cmsdk_m2354_s.S
index 9242946..fe79b2d 100644
--- a/platform/ext/target/nuvoton/m2354/device/source/gcc/startup_cmsdk_m2354_s.S
+++ b/platform/ext/target/nuvoton/m2354/device/source/gcc/startup_cmsdk_m2354_s.S
@@ -23,7 +23,7 @@
.syntax unified
.arch armv8-m.base
- .section .vectors
+ .section .vectors, "a"
.align 2
.globl __Vectors
__Vectors:
diff --git a/platform/ext/target/nuvoton/m2354/partition/region_defs.h b/platform/ext/target/nuvoton/m2354/partition/region_defs.h
index 1aa3b25..b69c066 100644
--- a/platform/ext/target/nuvoton/m2354/partition/region_defs.h
+++ b/platform/ext/target/nuvoton/m2354/partition/region_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
* Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -72,8 +72,6 @@
#define IMAGE_S_CODE_SIZE (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
#define IMAGE_NS_CODE_SIZE (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-#define CMSE_VENEER_REGION_SIZE (0x340)
-
/* Alias definitions for secure and non-secure areas*/
#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x))
#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
@@ -85,15 +83,15 @@
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) /* 0x8400 */
#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) /* 0x8400 */
-#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
#define S_DATA_START (S_RAM_ALIAS(0x0))
#define S_DATA_SIZE (80 * 1024)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
-/* CMSE Veneers region */
-#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+/* Size of vector table: 117 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x1D8)
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
diff --git a/platform/ext/target/nuvoton/m2354/target_cfg.c b/platform/ext/target/nuvoton/m2354/target_cfg.c
index 46e1360..e0504a7 100644
--- a/platform/ext/target/nuvoton/m2354/target_cfg.c
+++ b/platform/ext/target/nuvoton/m2354/target_cfg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited
+ * Copyright (c) 2018-2021 Arm Limited
* Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,8 +30,8 @@
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
#ifdef BL2
REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
#endif /* BL2 */
@@ -49,10 +49,10 @@
NS_PARTITION_SIZE - 1,
.veneer_base =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
.veneer_limit =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
#ifdef BL2
.secondary_partition_base =
@@ -194,8 +194,8 @@
false,
},
{
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
true,
},
{
diff --git a/platform/ext/target/nxp/common/tfm_hal_isolation.c b/platform/ext/target/nxp/common/tfm_hal_isolation.c
index ad9affb..4bb08ed 100644
--- a/platform/ext/target/nxp/common/tfm_hal_isolation.c
+++ b/platform/ext/target/nxp/common/tfm_hal_isolation.c
@@ -29,8 +29,6 @@
struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
#if TFM_LVL == 3
static uint32_t idx_boundary_handle = 0;
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
REGION_DECLARE(Image$$, PT_RO_START, $$Base);
REGION_DECLARE(Image$$, PT_RO_END, $$Base);
REGION_DECLARE(Image$$, PT_PRIV_RWZI_START, $$Base);
@@ -39,15 +37,6 @@
static struct mpu_armv8m_region_cfg_t isolation_regions[] = {
{
0, /* will be updated before using */
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
- MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
- MPU_ARMV8M_XN_EXEC_OK,
- MPU_ARMV8M_AP_RO_PRIV_UNPRIV,
- MPU_ARMV8M_SH_NONE,
- },
- {
- 0, /* will be updated before using */
(uint32_t)®ION_NAME(Image$$, PT_RO_START, $$Base),
(uint32_t)®ION_NAME(Image$$, PT_RO_END, $$Base),
MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_s.S b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_s.S
index 23e3dfa..f876f90 100755
--- a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_s.S
+++ b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_s.S
@@ -22,7 +22,7 @@
.syntax unified
.arch armv8-m.main
- .section .vectors
+ .section .vectors, "a"
.align 2
.globl __Vectors
__Vectors:
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/partition/region_defs.h b/platform/ext/target/nxp/lpcxpresso55s69/partition/region_defs.h
index 86b5a57..4e45998 100755
--- a/platform/ext/target/nxp/lpcxpresso55s69/partition/region_defs.h
+++ b/platform/ext/target/nxp/lpcxpresso55s69/partition/region_defs.h
@@ -100,15 +100,15 @@
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
-#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
#define S_DATA_START (S_RAM_ALIAS(0x0))
#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
-/* CMSE Veneers region */
-#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+/* Size of vector table: 75 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x130)
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c b/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c
index 27198f4..9c2f687 100755
--- a/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c
+++ b/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c
@@ -28,8 +28,8 @@
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
#ifdef BL2
REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
#endif /* BL2 */
@@ -47,10 +47,10 @@
NS_PARTITION_SIZE - 1,
.veneer_base =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
.veneer_limit =
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
#ifdef BL2
.secondary_partition_base =
diff --git a/platform/ext/target/stm/common/stm32l5xx/secure/target_cfg.c b/platform/ext/target/stm/common/stm32l5xx/secure/target_cfg.c
index e6b78e1..219350f 100644
--- a/platform/ext/target/stm/common/stm32l5xx/secure/target_cfg.c
+++ b/platform/ext/target/stm/common/stm32l5xx/secure/target_cfg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 Arm Limited
+ * Copyright (c) 2018-2021 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -27,8 +27,8 @@
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
@@ -48,10 +48,10 @@
(uint32_t)(FLASH_BASE_NS + FLASH_AREA_1_OFFSET + FLASH_NS_PARTITION_SIZE - 1),
#endif /* 0 */
.veneer_base =
- (uint32_t) ®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
+ (uint32_t) ®ION_NAME(Image$$, ER_VENEER, $$Base),
.veneer_limit =
- (uint32_t) ®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t) ®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
};
diff --git a/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c b/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c
index 464d6e2..ba95148 100644
--- a/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c
+++ b/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -27,8 +27,6 @@
struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
#if TFM_LVL == 3
static uint32_t idx_boundary_handle = 0;
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
REGION_DECLARE(Image$$, PT_RO_START, $$Base);
REGION_DECLARE(Image$$, PT_RO_END, $$Base);
REGION_DECLARE(Image$$, PT_PRIV_RWZI_START, $$Base);
@@ -37,15 +35,6 @@
const static struct mpu_armv8m_region_cfg_t isolation_regions[] = {
{
0, /* will be updated before using */
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
- MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
- MPU_ARMV8M_XN_EXEC_OK,
- MPU_ARMV8M_AP_RO_PRIV_UNPRIV,
- MPU_ARMV8M_SH_NONE,
- },
- {
- 0, /* will be updated before using */
(uint32_t)®ION_NAME(Image$$, PT_RO_START, $$Base),
(uint32_t)®ION_NAME(Image$$, PT_RO_END, $$Base),
MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
@@ -68,8 +57,8 @@
};
#else /* TFM_LVL == 3 */
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Base);
+REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base);
@@ -87,8 +76,8 @@
/* Veneer region */
{
0, /* will be updated before using */
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
- (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+ (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
+ (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
MPU_ARMV8M_MAIR_ATTR_CODE_IDX,
MPU_ARMV8M_XN_EXEC_OK,
MPU_ARMV8M_AP_RO_PRIV_UNPRIV,
diff --git a/platform/ext/target/stm/common/stm32u5xx/secure/tfm_hal_isolation.c b/platform/ext/target/stm/common/stm32u5xx/secure/tfm_hal_isolation.c
index c9a72e5..35c882b 100644
--- a/platform/ext/target/stm/common/stm32u5xx/secure/tfm_hal_isolation.c
+++ b/platform/ext/target/stm/common/stm32u5xx/secure/tfm_hal_isolation.c
@@ -48,7 +48,7 @@
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base);
-REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+REGION_DECLARE(Image$$, ER_VENEER, $$Limit);
const struct mpu_armv8m_region_cfg_t region_cfg[] = {
/* TFM Core unprivileged code region */
diff --git a/platform/ext/target/stm/nucleo_l552ze_q/include/region_defs.h b/platform/ext/target/stm/nucleo_l552ze_q/include/region_defs.h
index 7286809..40218ee 100644
--- a/platform/ext/target/stm/nucleo_l552ze_q/include/region_defs.h
+++ b/platform/ext/target/stm/nucleo_l552ze_q/include/region_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018 ARM Limited
+ * Copyright (c) 2017-2021 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -105,8 +105,6 @@
#define IMAGE_NS_CODE_SIZE \
(FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-#define CMSE_VENEER_REGION_SIZE (0x00000340)
-
/* Use SRAM1 memory to store Code data */
#define S_ROM_ALIAS_BASE (_FLASH_BASE_S)
#define NS_ROM_ALIAS_BASE (_FLASH_BASE_NS)
@@ -126,15 +124,16 @@
#define S_IMAGE_PRIMARY_AREA_OFFSET (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
-#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_LIMIT ((S_CODE_START + S_CODE_SIZE) -1)
#define S_DATA_START (S_RAM_ALIAS(NS_TOTAL_RAM_SIZE))
#define S_DATA_SIZE (S_TOTAL_RAM_SIZE)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
-/* CMSE Veneers region */
-#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+/* Size of vector table: 124 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x1F4)
+
/* Non-secure regions */
/* Secure regions , the end of secure regions must be aligned on page size for dual bank 0x800*/
diff --git a/platform/ext/target/stm/stm32l562e_dk/include/region_defs.h b/platform/ext/target/stm/stm32l562e_dk/include/region_defs.h
index bc55af5..497c756 100644
--- a/platform/ext/target/stm/stm32l562e_dk/include/region_defs.h
+++ b/platform/ext/target/stm/stm32l562e_dk/include/region_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018 ARM Limited
+ * Copyright (c) 2017-2021 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -105,9 +105,6 @@
#define IMAGE_NS_CODE_SIZE \
(FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-
-#define CMSE_VENEER_REGION_SIZE (0x00000340)
-
/* Use SRAM1 memory to store Code data */
#define S_ROM_ALIAS_BASE (_FLASH_BASE_S)
#define NS_ROM_ALIAS_BASE (_FLASH_BASE_NS)
@@ -127,15 +124,16 @@
#define S_IMAGE_PRIMARY_AREA_OFFSET (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
-#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_LIMIT ((S_CODE_START + S_CODE_SIZE) -1)
#define S_DATA_START (S_RAM_ALIAS(NS_TOTAL_RAM_SIZE))
#define S_DATA_SIZE (S_TOTAL_RAM_SIZE)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
-/* CMSE Veneers region */
-#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+/* Size of vector table: 124 interrupt handlers + 4 bytes MPS initial value */
+#define S_CODE_VECTOR_TABLE_SIZE (0x1F4)
+
/* Non-secure regions */
/* Secure regions , the end of secure regions must be aligned on page size for dual bank 0x800*/