Platform: Implement CMSIS flash driver for Musca
-- This patch implements CMSIS compliant flash driver
on Musca A1 test chip board
-- Introduces #defines needed to implement
SST flash interface on top of CMSIS flash driver.
-- Redirects SST storage to Code SRAM
instead of storing it in flash.
-- Reduces the heap size in BL2
-- Increases the stack size for Musca A1
as it was too small to run the regression tests.
-- Removes dead code related to configuring sau and
mpc for code SRAM
Change-Id: Ic810fc24d768200463184233de9bbb389ec413f8
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
diff --git a/platform/ext/musca_a.cmake b/platform/ext/musca_a.cmake
index 17b3141..d90aa26 100755
--- a/platform/ext/musca_a.cmake
+++ b/platform/ext/musca_a.cmake
@@ -111,6 +111,10 @@
if (NOT DEFINED BUILD_FLASH)
message(FATAL_ERROR "Configuration variable BUILD_FLASH (true|false) is undefined!")
elseif(BUILD_FLASH)
- list(APPEND ALL_SRC_C "${PLATFORM_DIR}/common/flash_memory_mapped.c")
- embedded_include_directories(PATH "${PLATFORM_DIR}/common" ABSOLUTE)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/CMSIS_Driver/Driver_Flash.c")
+ # As the SST area is going to be in RAM, it is required to set SST_RAM_FS to be sure the
+ # SST service knows that when it starts the SST area does not contain any valid block and
+ # it needs to create an empty one.
+ set(SST_RAM_FS True)
+ embedded_include_directories(PATH "${PLATFORM_DIR}/target/musca_a/CMSIS_Driver" ABSOLUTE)
endif()
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Config/RTE_Device.h b/platform/ext/target/musca_a/CMSIS_Driver/Config/RTE_Device.h
index 7235c79..11e5d07 100755
--- a/platform/ext/target/musca_a/CMSIS_Driver/Config/RTE_Device.h
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Config/RTE_Device.h
@@ -114,4 +114,9 @@
#define RTE_APB_PPCEXP3 0
// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP3]
+// <e> FLASH (Flash Memory) [Driver_FLASH0]
+// <i> Configuration settings for Driver_FLASH0 in component ::Drivers:FLASH
+#define RTE_FLASH0 1
+// </e> FLASH (Flash Memory) [Driver_FLASH0]
+
#endif /* __RTE_DEVICE_H */
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Driver_Flash.c b/platform/ext/target/musca_a/CMSIS_Driver/Driver_Flash.c
new file mode 100755
index 0000000..a5c6e0e
--- /dev/null
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Driver_Flash.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include "Driver_Flash.h"
+#include "platform_retarget.h"
+#include "RTE_Device.h"
+#include "flash_layout.h"
+#include "region_defs.h"
+
+#ifndef ARG_UNUSED
+#define ARG_UNUSED(arg) ((void)arg)
+#endif
+
+/* Driver version */
+#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)
+
+/*
+ * ARM FLASH device structure
+ */
+struct arm_flash_dev_t {
+ const uint32_t memory_base; /*!< FLASH memory base address */
+ ARM_FLASH_INFO *data; /*!< FLASH data */
+};
+
+/* Flash Status */
+static ARM_FLASH_STATUS FlashStatus = {0, 0, 0};
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_FLASH_API_VERSION,
+ ARM_FLASH_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_FLASH_CAPABILITIES DriverCapabilities = {
+ 0, /* event_ready */
+ 2, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */
+ 1 /* erase_chip */
+};
+
+static int32_t is_range_valid(struct arm_flash_dev_t *flash_dev,
+ uint32_t offset)
+{
+ uint32_t flash_limit = 0;
+ int32_t rc = 0;
+
+ flash_limit = (flash_dev->data->sector_count * flash_dev->data->sector_size)
+ - 1;
+
+ if (offset > flash_limit) {
+ rc = -1;
+ }
+ return rc;
+}
+
+static int32_t is_write_aligned(struct arm_flash_dev_t *flash_dev,
+ uint32_t param)
+{
+ int32_t rc = 0;
+
+ if ((param % flash_dev->data->program_unit) != 0) {
+ rc = -1;
+ }
+ return rc;
+}
+
+static int32_t is_sector_aligned(struct arm_flash_dev_t *flash_dev,
+ uint32_t offset)
+{
+ int32_t rc = 0;
+
+ if ((offset % flash_dev->data->sector_size) != 0) {
+ rc = -1;
+ }
+ return rc;
+}
+
+#if (RTE_FLASH0)
+static ARM_FLASH_INFO ARM_FLASH0_DEV_DATA = {
+ .sector_info = NULL, /* Uniform sector layout */
+ .sector_count = FLASH0_SIZE / FLASH0_SECTOR_SIZE,
+ .sector_size = FLASH0_SECTOR_SIZE,
+ .page_size = FLASH0_PAGE_SIZE,
+ .program_unit = FLASH0_PROGRAM_UNIT,
+ .erased_value = 0xFF};
+
+static struct arm_flash_dev_t ARM_FLASH0_DEV = {
+#if (__DOMAIN_NS == 1)
+ .memory_base = FLASH0_BASE_NS,
+#else
+ .memory_base = FLASH0_BASE_S,
+#endif /* __DOMAIN_NS == 1 */
+ .data = &(ARM_FLASH0_DEV_DATA)};
+
+struct arm_flash_dev_t *FLASH0_DEV = &ARM_FLASH0_DEV;
+
+/*
+ * Functions
+ */
+
+static ARM_DRIVER_VERSION ARM_Flash_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void)
+{
+ return DriverCapabilities;
+}
+
+static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event)
+{
+ ARG_UNUSED(cb_event);
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state)
+{
+ switch (state) {
+ case ARM_POWER_FULL:
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+ break;
+
+ case ARM_POWER_OFF:
+ case ARM_POWER_LOW:
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+}
+
+static int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt)
+{
+ volatile uint32_t mem_base = FLASH0_DEV->memory_base;
+ uint32_t start_addr = mem_base + addr;
+ int32_t rc = 0;
+
+ /* Check flash memory boundaries */
+ rc = is_range_valid(FLASH0_DEV, addr + cnt);
+ if (rc != 0) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Redirecting SST storage to code sram */
+ if(addr >= SST_FLASH_AREA_ADDR &&
+ addr <= SST_FLASH_AREA_ADDR + FLASH_SST_AREA_SIZE) {
+ start_addr = S_CODE_SRAM_ALIAS_BASE + addr;
+ }
+
+ /* Flash interface just emulated over SRAM, use memcpy */
+ memcpy(data, (void *)start_addr, cnt);
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, uint32_t cnt)
+{
+ volatile uint32_t mem_base = FLASH0_DEV->memory_base;
+ uint32_t start_addr = mem_base + addr;
+ int32_t rc = 0;
+
+ /* Check flash memory boundaries and alignment with minimal write size */
+ rc = is_range_valid(FLASH0_DEV, addr + cnt);
+ rc |= is_write_aligned(FLASH0_DEV, addr);
+ rc |= is_write_aligned(FLASH0_DEV, cnt);
+ if (rc != 0) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Redirecting SST storage to code sram */
+ if(addr >= SST_FLASH_AREA_ADDR &&
+ addr <= SST_FLASH_AREA_ADDR + FLASH_SST_AREA_SIZE) {
+ start_addr = S_CODE_SRAM_ALIAS_BASE + addr;
+ }
+
+ /* Flash interface just emulated over SRAM, use memcpy */
+ memcpy((void *)start_addr, data, cnt);
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_EraseSector(uint32_t addr)
+{
+ volatile uint32_t mem_base = FLASH0_DEV->memory_base;
+ uint32_t start_addr = mem_base + addr;
+ uint32_t rc = 0;
+
+ rc = is_range_valid(FLASH0_DEV, addr);
+ rc |= is_sector_aligned(FLASH0_DEV, addr);
+ if (rc != 0) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Redirecting SST storage to code sram */
+ if(addr >= SST_FLASH_AREA_ADDR &&
+ addr <= SST_FLASH_AREA_ADDR + FLASH_SST_AREA_SIZE) {
+ start_addr = S_CODE_SRAM_ALIAS_BASE + addr;
+ }
+
+ /* Flash interface just emulated over SRAM, use memset */
+ memset((void *)start_addr,
+ FLASH0_DEV->data->erased_value,
+ FLASH0_DEV->data->sector_size);
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_EraseChip(void)
+{
+ uint32_t i;
+ uint32_t addr = FLASH0_DEV->memory_base;
+ int32_t rc = ARM_DRIVER_ERROR_UNSUPPORTED;
+
+ /* Check driver capability erase_chip bit */
+ if (DriverCapabilities.erase_chip == 1) {
+ for (i = 0; i < FLASH0_DEV->data->sector_count; i++) {
+ /* Redirecting SST storage to code sram */
+ if(addr >= SST_FLASH_AREA_ADDR &&
+ addr <= SST_FLASH_AREA_ADDR + FLASH_SST_AREA_SIZE) {
+ memset((void *)addr - FLASH0_DEV->memory_base
+ + S_CODE_SRAM_ALIAS_BASE,
+ FLASH0_DEV->data->erased_value,
+ FLASH0_DEV->data->sector_size);
+ } else {
+ /* Flash interface just emulated over SRAM, use memset */
+ memset((void *)addr,
+ FLASH0_DEV->data->erased_value,
+ FLASH0_DEV->data->sector_size);
+ }
+ addr += FLASH0_DEV->data->sector_size;
+ rc = ARM_DRIVER_OK;
+ }
+ }
+ return rc;
+}
+
+static ARM_FLASH_STATUS ARM_Flash_GetStatus(void)
+{
+ return FlashStatus;
+}
+
+static ARM_FLASH_INFO * ARM_Flash_GetInfo(void)
+{
+ return FLASH0_DEV->data;
+}
+
+ARM_DRIVER_FLASH Driver_FLASH0 = {
+ ARM_Flash_GetVersion,
+ ARM_Flash_GetCapabilities,
+ ARM_Flash_Initialize,
+ ARM_Flash_Uninitialize,
+ ARM_Flash_PowerControl,
+ ARM_Flash_ReadData,
+ ARM_Flash_ProgramData,
+ ARM_Flash_EraseSector,
+ ARM_Flash_EraseChip,
+ ARM_Flash_GetStatus,
+ ARM_Flash_GetInfo
+};
+#endif /* RTE_FLASH0 */
diff --git a/platform/ext/target/musca_a/Device/Include/platform_retarget.h b/platform/ext/target/musca_a/Device/Include/platform_retarget.h
index 2580aae..b7c1a1b 100755
--- a/platform/ext/target/musca_a/Device/Include/platform_retarget.h
+++ b/platform/ext/target/musca_a/Device/Include/platform_retarget.h
@@ -60,5 +60,11 @@
#define MPC_QSPI_RANGE_LIMIT_NS (0x00240000)
#define MPC_QSPI_RANGE_BASE_S (0x10200000)
#define MPC_QSPI_RANGE_LIMIT_S (0x10240000)
+#define FLASH0_BASE_S (MPC_QSPI_RANGE_BASE_S)
+#define FLASH0_BASE_NS (MPC_QSPI_RANGE_BASE_NS)
+#define FLASH0_SIZE (0x00800000) /* 8 MB */
+#define FLASH0_SECTOR_SIZE (0x00001000) /* 4 kB */
+#define FLASH0_PAGE_SIZE (0x00001000) /* 4 kB */
+#define FLASH0_PROGRAM_UNIT (0x4) /* Minimum write size */
#endif /* __ARM_LTD_MUSCA_RETARGET_H__ */
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_bl2.s b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_bl2.s
index d26e329..8b035c6 100755
--- a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_bl2.s
+++ b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_bl2.s
@@ -38,7 +38,7 @@
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
-Heap_Size EQU 0x00010000
+Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s
index b375d36..f8c46a6 100755
--- a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s
+++ b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s
@@ -26,7 +26,9 @@
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
-Stack_Size EQU 0x00001000
+; NOTE: The stack size needs to be re-evaluated as soon as the new mechanism
+; to run the secure tests, based on a test service, is introduced.
+Stack_Size EQU 0x00002000
MSP_STACK_SIZE EQU 0x00000800
AREA STACK, NOINIT, READWRITE, ALIGN=3
diff --git a/platform/ext/target/musca_a/partition/flash_layout.h b/platform/ext/target/musca_a/partition/flash_layout.h
index 12c5638..3267a8c 100755
--- a/platform/ext/target/musca_a/partition/flash_layout.h
+++ b/platform/ext/target/musca_a/partition/flash_layout.h
@@ -18,22 +18,47 @@
#define __FLASH_LAYOUT_H__
/* Flash layout on Musca with BL2:
- * 0x0020_0000 BL2 - MCUBoot
- * 0x0021_0000 Flash_area_image_0:
+ * 0x0020_0000 BL2 - MCUBoot(64 KB)
+ * 0x0021_0000 Flash_area_image_0(192 KB)
* 0x0021_0000 Secure image primary
* 0x0023_0000 Non-secure image primary
- * 0x0024_0000 Flash_area_image_1:
+ * 0x0024_0000 Flash_area_image_1(192 KB)
* 0x0024_0000 Secure image secondary
* 0x0026_0000 Non-secure image secondary
- * 0x0027_0000 Scratch area
+ * 0x0027_0000 Scratch area(192 KB)
+ * 0x002A_0000 Secure Storage Area (0.02 MB)
+ * 0x002A_5000 Unused
+ *
+ * Flash layout on Musca, if BL2 not defined:
+ * 0x0020_0000 Secure image
+ * 0x0022_0000 Non-secure image
*/
-#define FLASH_BASE_ADDRESS (0x00200000)
-#define FLASH_ALIGN (1)
+/* This header file is included from linker scatter file as well, where only a
+ * limited C constructs are allowed. Therefore it is not possible to include
+ * here the platform_retarget.h to access flash related defines. To resolve this
+ * some of the values are redefined here with different names, these are marked
+ * with comment.
+ */
+
+/* The size of a partition. This should be large enough to contain a S or NS
+ * sw binary. Each FLASH_AREA_IMAGE contains two partitions. See Flash layout
+ * above.
+ */
#define FLASH_PARTITION_SIZE (0x20000) /* 128KB */
-#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000)
+/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */
+#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 kB */
+/* Same as FLASH0_SIZE */
+#define FLASH_TOTAL_SIZE (0x00800000) /* 8 MB */
+/* Flash layout info for BL2 bootloader */
+#define FLASH_BASE_ADDRESS (0x10200000) /* same as FLASH0_BASE_S */
+
+/* Offset and size definitions of the flash partitions that are handled by the
+ * bootloader. The image swapping is done between IMAGE_0 and IMAGE_1, SCRATCH
+ * is used as a temporary storage during image swapping.
+ */
#define FLASH_AREA_BL2_OFFSET (0x0)
#ifdef BL2
#define FLASH_AREA_BL2_SIZE (0x10000) /* 64KB */
@@ -55,6 +80,15 @@
FLASH_AREA_IMAGE_1_SIZE)
#define FLASH_AREA_IMAGE_SCRATCH_SIZE (FLASH_AREA_IMAGE_SIZE)
+/*
+ * Note: Though the SST_FLASH_AREA_ADDR is pointing to offset in flash, but
+ * the actual contents of SST is stored in Code SRAM. See Driver_Flash.c for
+ * more details.
+ */
+#define FLASH_SST_AREA_OFFSET (FLASH_AREA_IMAGE_SCRATCH_OFFSET + \
+ FLASH_AREA_IMAGE_SCRATCH_SIZE)
+#define FLASH_SST_AREA_SIZE (0x5000) /* 20 KB */
+
/* Offset and size definition in flash area, used by assemble.py */
#define SECURE_IMAGE_OFFSET 0x0
#define SECURE_IMAGE_MAX_SIZE 0x20000
@@ -62,4 +96,20 @@
#define NON_SECURE_IMAGE_OFFSET 0x20000
#define NON_SECURE_IMAGE_MAX_SIZE 0x20000
+/* Flash device name used by BL2 and SST
+ * Name is defined in flash driver file: Driver_Flash.c
+ */
+#define FLASH_DEV_NAME Driver_FLASH0
+
+/* Secure Storage (SST) Service definitions */
+/* In this target the CMSIS driver requires only the offset from the base
+ * address instead of the full memory address.
+ */
+#define SST_FLASH_AREA_ADDR FLASH_SST_AREA_OFFSET
+#define SST_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
+/* The sectors must be in consecutive memory location */
+#define SST_NBR_OF_SECTORS (FLASH_SST_AREA_SIZE / SST_SECTOR_SIZE)
+/* Specifies the smallest flash programmable unit in bytes */
+#define SST_FLASH_PROGRAM_UNIT 0x4
+
#endif /* __FLASH_LAYOUT_H__ */
diff --git a/platform/ext/target/musca_a/partition/region_defs.h b/platform/ext/target/musca_a/partition/region_defs.h
index aa40bc9..89dbbf9 100755
--- a/platform/ext/target/musca_a/partition/region_defs.h
+++ b/platform/ext/target/musca_a/partition/region_defs.h
@@ -19,7 +19,7 @@
#include "flash_layout.h"
-#define TOTAL_ROM_SIZE (0x00040000) /* 256KB */
+#define TOTAL_ROM_SIZE (0x00200000) /* 2 MB */
#define TOTAL_RAM_SIZE (0x00020000) /* 128KB */
/*
@@ -27,22 +27,6 @@
* of partitions is defined in accordance with this constraint.
*/
-/*Flash partitions on Musca with BL2:
- * 0x0020_0000 BL2 - MCUBoot
- * 0x0021_0000 Flash_area_image_0:
- * 0x0021_0000 Secure image primary
- * 0x0023_0000 Non-secure image primary
- * 0x0024_0000 Flash_area_image_1:
- * 0x0024_0000 Secure image secondary
- * 0x0026_0000 Non-secure image secondary
- * 0x0027_0000 Scratch area
-
- *
- * Flash partitions on bare metal, if BL2 not defined:
- * 0x0020_0000 Secure image
- * 0x0022_0000 Non-secure image
- */
-
#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_IMAGE_0_OFFSET)
#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (S_IMAGE_PRIMARY_PARTITION_OFFSET + \
FLASH_PARTITION_SIZE)
@@ -50,8 +34,8 @@
/*
* Boot partition structure if MCUBoot is used:
* 0x0_0000 Bootloader header
- * 0x0_0200 Image area
- * 0x7_0000 Trailer
+ * 0x0_0400 Image area
+ * 0x1_FC00 Trailer
*/
/* IMAGE_CODE_SIZE is the space available for the software binary image.
* It is less than the FLASH_PARTITION_SIZE because we reserve space
@@ -112,24 +96,15 @@
#define NS_PARTITION_START \
(NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
+#define NS_PARTITION_LIMIT \
+ (NS_PARTITION_START + FLASH_PARTITION_SIZE \
+ - FLASH_AREA_BL2_SIZE - 1)
+
/* Code SRAM area */
#define TOTAL_CODE_SRAM_SIZE (TOTAL_ROM_SIZE)
#define S_CODE_SRAM_ALIAS_BASE (0x10000000)
#define NS_CODE_SRAM_ALIAS_BASE (0x00000000)
-#define BL2_CODE_SRAM_EXEC_BASE (S_CODE_SRAM_ALIAS_BASE)
-#define S_CODE_SRAM_EXEC_BASE (S_CODE_SRAM_ALIAS_BASE)
-#define S_CODE_SRAM_EXEC_LIMIT (S_CODE_SRAM_EXEC_BASE + \
- (TOTAL_CODE_SRAM_SIZE/2) - 1)
-#define NS_CODE_SRAM_EXEC_BASE (NS_CODE_SRAM_ALIAS_BASE + \
- (TOTAL_CODE_SRAM_SIZE/2))
-#define NS_CODE_SRAM_EXEC_LIMIT (NS_CODE_SRAM_EXEC_BASE + \
- (TOTAL_CODE_SRAM_SIZE/2) - 1)
-
-#define NS_PARTITION_LIMIT \
- (NS_PARTITION_START + FLASH_PARTITION_SIZE \
- - FLASH_AREA_BL2_SIZE - 1)
-
#define NS_DATA_START (NS_RAM_ALIAS(TOTAL_RAM_SIZE/2))
#define NS_DATA_SIZE (TOTAL_RAM_SIZE/2)
#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE -1)
diff --git a/platform/ext/target/musca_a/target_cfg.c b/platform/ext/target/musca_a/target_cfg.c
index c80bc86..3bd0755 100755
--- a/platform/ext/target/musca_a/target_cfg.c
+++ b/platform/ext/target/musca_a/target_cfg.c
@@ -139,19 +139,6 @@
SAU->RBAR = (NS_PARTITION_START & SAU_RBAR_BADDR_Msk);
SAU->RLAR = (NS_PARTITION_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
-/*
- * If __USE_BOTH_CODE_MEMORY is defined the code is copied from QSPI flash to
- * CODE SRAM before executing, SAU needs to be configured accordingly.
- * If __USE_BOTH_CODE_MEMORY is undefined then the code will be executed from
- * QSPI flash directly, no such configuration is needed for CODE SRAM
- */
-#ifdef __USE_BOTH_CODE_MEMORY
- SAU->RNR = TFM_NS_REGION_CODE_SRAM;
- SAU->RBAR = (NS_CODE_SRAM_EXEC_BASE & SAU_RBAR_BADDR_Msk);
- SAU->RLAR = (NS_CODE_SRAM_EXEC_LIMIT & SAU_RLAR_LADDR_Msk) |
- SAU_RLAR_ENABLE_Msk;
-#endif
-
SAU->RNR = TFM_NS_REGION_DATA;
SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk);
SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
@@ -188,23 +175,6 @@
NS_PARTITION_LIMIT,
ARM_MPC_ATTR_NONSECURE);
- Driver_SRAM1_MPC.Initialize();
-/*
- * If __USE_BOTH_CODE_MEMORY is defined the code is copied from QSPI flash to
- * CODE SRAM before executing, MPC needs to be configured accordingly.
- * If __USE_BOTH_CODE_MEMORY is undefined then the code will be executed from
- * QSPI flash directly
- */
-#ifdef __USE_BOTH_CODE_MEMORY
- Driver_SRAM1_MPC.ConfigRegion(NS_CODE_SRAM_EXEC_BASE,
- NS_CODE_SRAM_EXEC_LIMIT,
- ARM_MPC_ATTR_NONSECURE);
-#else
- Driver_SRAM1_MPC.ConfigRegion(NS_PARTITION_START,
- NS_PARTITION_LIMIT,
- ARM_MPC_ATTR_NONSECURE);
-#endif
-
mpc_data_region0->Initialize();
mpc_data_region0->ConfigRegion(MPC_ISRAM0_RANGE_BASE_S,
MPC_ISRAM0_RANGE_LIMIT_S,
@@ -227,7 +197,6 @@
/* Lock down the MPC configuration */
Driver_QSPI_MPC.LockDown();
- Driver_SRAM1_MPC.LockDown();
mpc_data_region0->LockDown();
mpc_data_region1->LockDown();
mpc_data_region2->LockDown();