Change file format from Windows to Linux
It uses "\r\n" as line break in Windows files which is different with
Linux file. In Linux, one line is ended by "\n". So the line break for
some files Windows format are shown as "^M" in the Linux system.
Change-Id: I5c85895c65f26ee0c32879e4daed297b74680c09
Signed-off-by: Edison Ai <edison.ai@arm.com>
diff --git a/platform/ext/cmsis/cmsis_gcc.h b/platform/ext/cmsis/cmsis_gcc.h
index d0526f1..ec28b86 100644
--- a/platform/ext/cmsis/cmsis_gcc.h
+++ b/platform/ext/cmsis/cmsis_gcc.h
@@ -1,2026 +1,2026 @@
-/**************************************************************************//**
- * @file cmsis_gcc.h
- * @brief CMSIS compiler GCC header file
- * @version V5.0.2
- * @date 13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_GCC_H
-#define __CMSIS_GCC_H
-
-/* ignore some GCC warnings */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-/* Fallback for __has_builtin */
-#ifndef __has_builtin
- #define __has_builtin(x) (0)
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef __ASM
- #define __ASM __asm
-#endif
-#ifndef __INLINE
- #define __INLINE inline
-#endif
-#ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
-#endif
-#ifndef __STATIC_FORCEINLINE
- #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
-#endif
-#ifndef __NO_RETURN
- #define __NO_RETURN __attribute__((noreturn))
-#endif
-#ifndef __USED
- #define __USED __attribute__((used))
-#endif
-#ifndef __WEAK
- #define __WEAK __attribute__((weak))
-#endif
-#ifndef __PACKED
- #define __PACKED __attribute__((packed, aligned(1)))
-#endif
-#ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
-#endif
-#ifndef __PACKED_UNION
- #define __PACKED_UNION union __attribute__((packed, aligned(1)))
-#endif
-#ifndef __UNALIGNED_UINT32 /* deprecated */
- #pragma GCC diagnostic push
- #pragma GCC diagnostic ignored "-Wpacked"
- #pragma GCC diagnostic ignored "-Wattributes"
- struct __attribute__((packed)) T_UINT32 { uint32_t v; };
- #pragma GCC diagnostic pop
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef __UNALIGNED_UINT16_WRITE
- #pragma GCC diagnostic push
- #pragma GCC diagnostic ignored "-Wpacked"
- #pragma GCC diagnostic ignored "-Wattributes"
- __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
- #pragma GCC diagnostic pop
- #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef __UNALIGNED_UINT16_READ
- #pragma GCC diagnostic push
- #pragma GCC diagnostic ignored "-Wpacked"
- #pragma GCC diagnostic ignored "-Wattributes"
- __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
- #pragma GCC diagnostic pop
- #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef __UNALIGNED_UINT32_WRITE
- #pragma GCC diagnostic push
- #pragma GCC diagnostic ignored "-Wpacked"
- #pragma GCC diagnostic ignored "-Wattributes"
- __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
- #pragma GCC diagnostic pop
- #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef __UNALIGNED_UINT32_READ
- #pragma GCC diagnostic push
- #pragma GCC diagnostic ignored "-Wpacked"
- #pragma GCC diagnostic ignored "-Wattributes"
- __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
- #pragma GCC diagnostic pop
- #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef __ALIGNED
- #define __ALIGNED(x) __attribute__((aligned(x)))
-#endif
-#ifndef __RESTRICT
- #define __RESTRICT __restrict
-#endif
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Control Register (non-secure)
- \details Returns the content of the non-secure Control Register when in secure mode.
- \return non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Control Register (non-secure)
- \details Writes the given value to the non-secure Control Register when in secure state.
- \param [in] control Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
- __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
- \return PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
- \return MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
- \return SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Set Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
- \param [in] topOfStack Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
- __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Priority Mask (non-secure)
- \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
- \return Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Priority Mask (non-secure)
- \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
- \param [in] priMask Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
- __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Base Priority (non-secure)
- \details Returns the current value of the non-secure Base Priority register when in secure state.
- \return Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Base Priority (non-secure)
- \details Assigns the given value to the non-secure Base Priority register when in secure state.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Fault Mask (non-secure)
- \details Returns the current value of the non-secure Fault Mask register when in secure state.
- \return Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Fault Mask (non-secure)
- \details Assigns the given value to the non-secure Fault Mask register when in secure state.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-
-/**
- \brief Get Process Stack Pointer Limit
- \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
- \return PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psplim" : "=r" (result) );
- return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Get Process Stack Pointer Limit (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \return PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer Limit
- \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
- __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
- __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer Limit
- \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
- \return MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
- return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Get Main Stack Pointer Limit (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
- \return MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer Limit
- \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
- \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
- __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Set Main Stack Pointer Limit (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
- \param [in] MainStackPtrLimit Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
- __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
- /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
- return __builtin_arm_get_fpscr();
-#else
- uint32_t result;
-
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- return(result);
-#endif
-#else
- return(0U);
-#endif
-}
-
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
- /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
- __builtin_arm_set_fpscr(fpscr);
-#else
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
-#endif
-#else
- (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
- \brief No Operation
- \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP() __ASM volatile ("nop")
-
-/**
- \brief Wait For Interrupt
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI() __ASM volatile ("wfi")
-
-
-/**
- \brief Wait For Event
- \details Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE() __ASM volatile ("wfe")
-
-
-/**
- \brief Send Event
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV() __ASM volatile ("sev")
-
-
-/**
- \brief Instruction Synchronization Barrier
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or memory,
- after the instruction has been completed.
- */
-__STATIC_FORCEINLINE void __ISB(void)
-{
- __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/**
- \brief Data Synchronization Barrier
- \details Acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__STATIC_FORCEINLINE void __DSB(void)
-{
- __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/**
- \brief Data Memory Barrier
- \details Ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__STATIC_FORCEINLINE void __DMB(void)
-{
- __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/**
- \brief Reverse byte order (32 bit)
- \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
- return __builtin_bswap32(value);
-#else
- uint32_t result;
-
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return result;
-#endif
-}
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return result;
-}
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- return (int16_t)__builtin_bswap16(value);
-#else
- int16_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return result;
-#endif
-}
-
-
-/**
- \brief Rotate Right in unsigned value (32 bit)
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
- \param [in] op1 Value to rotate
- \param [in] op2 Number of Bits to rotate
- \return Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- op2 %= 32U;
- if (op2 == 0U)
- {
- return op1;
- }
- return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
- \brief Breakpoint
- \details Causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-/**
- \brief Reverse bit order of value
- \details Reverses the bit order of the given value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
- uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
-
- result = value; /* r will be reversed bits of v; first get LSB of v */
- for (value >>= 1U; value != 0U; value >>= 1U)
- {
- result <<= 1U;
- result |= value & 1U;
- s--;
- }
- result <<= s; /* shift when v's highest bits are zero */
-#endif
- return result;
-}
-
-
-/**
- \brief Count leading zeros
- \details Counts the number of leading zeros of a data value.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-/**
- \brief LDR Exclusive (8 bit)
- \details Executes a exclusive LDR instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDR Exclusive (16 bit)
- \details Executes a exclusive LDR instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDR Exclusive (32 bit)
- \details Executes a exclusive LDR instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (8 bit)
- \details Executes a exclusive STR instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (16 bit)
- \details Executes a exclusive STR instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (32 bit)
- \details Executes a exclusive STR instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/**
- \brief Remove the exclusive lock
- \details Removes the exclusive lock which is created by LDREX.
- */
-__STATIC_FORCEINLINE void __CLREX(void)
-{
- __ASM volatile ("clrex" ::: "memory");
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] ARG1 Value to be saturated
- \param [in] ARG2 Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-__extension__ \
-({ \
- int32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] ARG1 Value to be saturated
- \param [in] ARG2 Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
- __extension__ \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/**
- \brief Rotate Right with Extend (32 bit)
- \details Moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to rotate
- \return Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/**
- \brief LDRT Unprivileged (8 bit)
- \details Executes a Unprivileged LDRT instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (16 bit)
- \details Executes a Unprivileged LDRT instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (32 bit)
- \details Executes a Unprivileged LDRT instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief STRT Unprivileged (8 bit)
- \details Executes a Unprivileged STRT instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (16 bit)
- \details Executes a Unprivileged STRT instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (32 bit)
- \details Executes a Unprivileged STRT instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
- if ((sat >= 1U) && (sat <= 32U))
- {
- const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
- const int32_t min = -1 - max ;
- if (val > max)
- {
- return max;
- }
- else if (val < min)
- {
- return min;
- }
- }
- return val;
-}
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
- if (sat <= 31U)
- {
- const uint32_t max = ((1U << sat) - 1U);
- if (val > (int32_t)max)
- {
- return max;
- }
- else if (val < 0)
- {
- return 0U;
- }
- }
- return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-/**
- \brief Load-Acquire (8 bit)
- \details Executes a LDAB instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result);
-}
-
-
-/**
- \brief Load-Acquire (16 bit)
- \details Executes a LDAH instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result);
-}
-
-
-/**
- \brief Load-Acquire (32 bit)
- \details Executes a LDA instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief Store-Release (8 bit)
- \details Executes a STLB instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (16 bit)
- \details Executes a STLH instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (32 bit)
- \details Executes a STL instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Load-Acquire Exclusive (8 bit)
- \details Executes a LDAB exclusive instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result);
-}
-
-
-/**
- \brief Load-Acquire Exclusive (16 bit)
- \details Executes a LDAH exclusive instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result);
-}
-
-
-/**
- \brief Load-Acquire Exclusive (32 bit)
- \details Executes a LDA exclusive instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief Store-Release Exclusive (8 bit)
- \details Executes a STLB exclusive instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief Store-Release Exclusive (16 bit)
- \details Executes a STLH exclusive instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief Store-Release Exclusive (32 bit)
- \details Executes a STL exclusive instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
-
-__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- int32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#pragma GCC diagnostic pop
-
-#endif /* __CMSIS_GCC_H */
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.0.2
+ * @date 13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/platform/ext/common/uart_stdout.c b/platform/ext/common/uart_stdout.c
index 7a41f1e..dea538f 100644
--- a/platform/ext/common/uart_stdout.c
+++ b/platform/ext/common/uart_stdout.c
@@ -1,86 +1,86 @@
-/*
- * Copyright (c) 2017-2018 ARM Limited
- *
- * Licensed under the Apace License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apace.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "uart_stdout.h"
-
-#include <assert.h>
-#include <stdio.h>
-#include <string.h>
-#include "Driver_USART.h"
-#include "target_cfg.h"
-
-#define ASSERT_HIGH(X) assert(X == ARM_DRIVER_OK)
-
-/* Imports USART driver */
-extern ARM_DRIVER_USART TFM_DRIVER_STDIO;
-
-/* Struct FILE is implemented in stdio.h. Used to redirect printf to
- * TFM_DRIVER_STDIO
- */
-FILE __stdout;
-
-static void uart_putc(unsigned char c)
-{
- int32_t ret = ARM_DRIVER_OK;
-
- ret = TFM_DRIVER_STDIO.Send(&c, 1);
- ASSERT_HIGH(ret);
-}
-
-/* Redirects printf to TFM_DRIVER_STDIO in case of ARMCLANG*/
-#if defined(__ARMCC_VERSION)
-/* __ARMCC_VERSION is only defined starting from Arm compiler version 6 */
-int fputc(int ch, FILE *f)
-{
- /* Send byte to USART */
- uart_putc(ch);
-
- /* Return character written */
- return ch;
-}
-#elif defined(__GNUC__)
-/* Redirects printf to TFM_DRIVER_STDIO in case of GNUARM */
-int _write(int fd, char *str, int len)
-{
- int i;
-
- for (i = 0; i < len; i++) {
- /* Send byte to USART */
- uart_putc(str[i]);
- }
-
- /* Return the number of characters written */
- return len;
-}
-#endif
-
-void stdio_init(void)
-{
- int32_t ret = ARM_DRIVER_OK;
- ret = TFM_DRIVER_STDIO.Initialize(NULL);
- ASSERT_HIGH(ret);
-
- ret = TFM_DRIVER_STDIO.Control(ARM_USART_MODE_ASYNCHRONOUS, 115200);
- ASSERT_HIGH(ret);
-}
-
-void stdio_uninit(void)
-{
- int32_t ret = ARM_DRIVER_OK;
- ret = TFM_DRIVER_STDIO.Uninitialize();
- ASSERT_HIGH(ret);
-}
-
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apace License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apace.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "uart_stdout.h"
+
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+#include "Driver_USART.h"
+#include "target_cfg.h"
+
+#define ASSERT_HIGH(X) assert(X == ARM_DRIVER_OK)
+
+/* Imports USART driver */
+extern ARM_DRIVER_USART TFM_DRIVER_STDIO;
+
+/* Struct FILE is implemented in stdio.h. Used to redirect printf to
+ * TFM_DRIVER_STDIO
+ */
+FILE __stdout;
+
+static void uart_putc(unsigned char c)
+{
+ int32_t ret = ARM_DRIVER_OK;
+
+ ret = TFM_DRIVER_STDIO.Send(&c, 1);
+ ASSERT_HIGH(ret);
+}
+
+/* Redirects printf to TFM_DRIVER_STDIO in case of ARMCLANG*/
+#if defined(__ARMCC_VERSION)
+/* __ARMCC_VERSION is only defined starting from Arm compiler version 6 */
+int fputc(int ch, FILE *f)
+{
+ /* Send byte to USART */
+ uart_putc(ch);
+
+ /* Return character written */
+ return ch;
+}
+#elif defined(__GNUC__)
+/* Redirects printf to TFM_DRIVER_STDIO in case of GNUARM */
+int _write(int fd, char *str, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ /* Send byte to USART */
+ uart_putc(str[i]);
+ }
+
+ /* Return the number of characters written */
+ return len;
+}
+#endif
+
+void stdio_init(void)
+{
+ int32_t ret = ARM_DRIVER_OK;
+ ret = TFM_DRIVER_STDIO.Initialize(NULL);
+ ASSERT_HIGH(ret);
+
+ ret = TFM_DRIVER_STDIO.Control(ARM_USART_MODE_ASYNCHRONOUS, 115200);
+ ASSERT_HIGH(ret);
+}
+
+void stdio_uninit(void)
+{
+ int32_t ret = ARM_DRIVER_OK;
+ ret = TFM_DRIVER_STDIO.Uninitialize();
+ ASSERT_HIGH(ret);
+}
+
diff --git a/platform/ext/common/uart_stdout.h b/platform/ext/common/uart_stdout.h
index 5d79398..8feff31 100644
--- a/platform/ext/common/uart_stdout.h
+++ b/platform/ext/common/uart_stdout.h
@@ -1,43 +1,43 @@
-/*
- * Copyright (c) 2017-2018 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __UART_STDOUT_H__
-#define __UART_STDOUT_H__
-
-#include <stdint.h>
-
-/**
- * \brief UART channels that
- * can be used from TFM
- */
-enum uart_channel {
- UART0_CHANNEL = 0,
- UART1_CHANNEL,
- UART_INVALID
-};
-
-/**
- * \brief Initializes the STDIO.
- *
- */
-void stdio_init(void);
-
-/**
- * \brief Uninitializes the STDIO.
- */
-void stdio_uninit(void);
-
-#endif /* __UART_STDOUT_H__ */
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __UART_STDOUT_H__
+#define __UART_STDOUT_H__
+
+#include <stdint.h>
+
+/**
+ * \brief UART channels that
+ * can be used from TFM
+ */
+enum uart_channel {
+ UART0_CHANNEL = 0,
+ UART1_CHANNEL,
+ UART_INVALID
+};
+
+/**
+ * \brief Initializes the STDIO.
+ *
+ */
+void stdio_init(void);
+
+/**
+ * \brief Uninitializes the STDIO.
+ */
+void stdio_uninit(void);
+
+#endif /* __UART_STDOUT_H__ */
diff --git a/platform/ext/driver/Driver_MPC.h b/platform/ext/driver/Driver_MPC.h
index 994dfda..9ed84ba 100644
--- a/platform/ext/driver/Driver_MPC.h
+++ b/platform/ext/driver/Driver_MPC.h
@@ -1,115 +1,115 @@
-/*
- * Copyright (c) 2016-2018 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef __DRIVER_MPC_H
-#define __DRIVER_MPC_H
-
-#include "Driver_Common.h"
-
-/* API version */
-#define ARM_MPC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
-
-/* Error code returned by the driver functions */
-#define ARM_MPC_ERR_NOT_INIT (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< MPC not initialized */
-#define ARM_MPC_ERR_NOT_IN_RANGE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Address does not belong to a range controlled by the MPC */
-#define ARM_MPC_ERR_NOT_ALIGNED (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Address is not aligned on the block size of this MPC */
-#define ARM_MPC_ERR_INVALID_RANGE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< The given address range to configure is invalid
-#define ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< The given range cannot be accessed with the wanted security attributes */
-#define ARM_MPC_ERR_UNSPECIFIED (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Unspecified error */
-
-/* Security attribute used in various place of the API */
-typedef enum _ARM_MPC_SEC_ATTR {
- ARM_MPC_ATTR_SECURE, ///< Secure attribute
- ARM_MPC_ATTR_NONSECURE, ///< Non-secure attribute
- /* Used when getting the configuration of a memory range and some blocks are
- * secure whereas some other are non secure */
- ARM_MPC_ATTR_MIXED, ///< Mixed attribute
-} ARM_MPC_SEC_ATTR;
-
-/* Function documentation */
-/**
- \fn ARM_DRIVER_VERSION ARM_MPC_GetVersion (void)
- \brief Get driver version.
- \return \ref ARM_DRIVER_VERSION
-
- \fn int32_t ARM_MPC_Initialize (void)
- \brief Initialize MPC Interface.
- \return Returns error code.
-
- \fn int32_t ARM_MPC_Uninitialize (void)
- \brief De-initialize MPC Interface. The controlled memory region
- should not be accessed after a call to this function, as
- it is allowed to configure everything to be secure (to
- prevent information leak for example).
- \return Returns error code.
-
- \fn int32_t ARM_MPC_GetBlockSize (uint32_t* blk_size)
- \brief Get the block size of the MPC. All regions must be aligned
- on this block size (base address and limit+1 address).
- \param[out] blk_size: The block size in bytes.
- \return Returns error code.
-
- \fn int32_t ARM_MPC_GetCtrlConfig (uint32_t* ctrl_val)
- \brief Get some information on how the MPC IP is configured.
- \param[out] ctrl_val: MPC control configuration
- \return Returns error code.
-
- \fn int32_t ARM_MPC_SetCtrlConfig (uint32_t ctrl)
- \brief Set new control configuration for the MPC IP.
- \param[in] ctrl: New control configuration.
- \return Returns error code.
-
- \fn int32_t ARM_MPC_ConfigRegion (uintptr_t base,
- uintptr_t limit,
- ARM_MPC_SEC_ATTR attr)
- \brief Configure a memory region (base and limit included).
- Both base and limit addresses must belong to the same
- memory range, and this range must be managed by this MPC.
- Also, some ranges are only allowed to be configured as
- secure/non-secure, because of hardware requirements
- (security aliases), and only a relevant security attribute
- is therefore allowed for such ranges.
- \param[in] base: Base address of the region to configure. This
- bound is included in the configured region.
- This must be aligned on the block size of this MPC.
- \param[in] limit: Limit address of the region to configure. This
- bound is included in the configured region.
- Limit+1 must be aligned on the block size of this MPC.
- \param[in] attr: Wanted security attribute of the region.
- \return Returns error code.
-
- \fn int32_t ARM_MPC_GetRegionConfig (uintptr_t base,
- uintptr_t limit,
- ARM_MPC_SEC_ATTR *attr)
- \brief Gets a memory region (base and limit included).
- \param[in] base: Base address of the region to poll. This
- bound is included. It does not need to be aligned
- in any way.
- \param[in] limit: Limit address of the region to poll. This
- bound is included. (limit+1) does not need to be aligned
- in any way.
- \param[out] attr: Security attribute of the region.
- If the region has mixed secure/non-secure,
- a special value is returned (\ref ARM_MPC_SEC_ATTR).
-
- In case base and limit+1 addresses are not aligned on
- the block size, the enclosing region with base and
- limit+1 aligned on block size will be queried.
- In case of early termination of the function (error), the
- security attribute will be set to ARM_MPC_ATTR_MIXED.
- \return Returns error code.
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __DRIVER_MPC_H
+#define __DRIVER_MPC_H
+
+#include "Driver_Common.h"
+
+/* API version */
+#define ARM_MPC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
+
+/* Error code returned by the driver functions */
+#define ARM_MPC_ERR_NOT_INIT (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< MPC not initialized */
+#define ARM_MPC_ERR_NOT_IN_RANGE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Address does not belong to a range controlled by the MPC */
+#define ARM_MPC_ERR_NOT_ALIGNED (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Address is not aligned on the block size of this MPC */
+#define ARM_MPC_ERR_INVALID_RANGE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< The given address range to configure is invalid
+#define ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< The given range cannot be accessed with the wanted security attributes */
+#define ARM_MPC_ERR_UNSPECIFIED (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Unspecified error */
+
+/* Security attribute used in various place of the API */
+typedef enum _ARM_MPC_SEC_ATTR {
+ ARM_MPC_ATTR_SECURE, ///< Secure attribute
+ ARM_MPC_ATTR_NONSECURE, ///< Non-secure attribute
+ /* Used when getting the configuration of a memory range and some blocks are
+ * secure whereas some other are non secure */
+ ARM_MPC_ATTR_MIXED, ///< Mixed attribute
+} ARM_MPC_SEC_ATTR;
+
+/* Function documentation */
+/**
+ \fn ARM_DRIVER_VERSION ARM_MPC_GetVersion (void)
+ \brief Get driver version.
+ \return \ref ARM_DRIVER_VERSION
+
+ \fn int32_t ARM_MPC_Initialize (void)
+ \brief Initialize MPC Interface.
+ \return Returns error code.
+
+ \fn int32_t ARM_MPC_Uninitialize (void)
+ \brief De-initialize MPC Interface. The controlled memory region
+ should not be accessed after a call to this function, as
+ it is allowed to configure everything to be secure (to
+ prevent information leak for example).
+ \return Returns error code.
+
+ \fn int32_t ARM_MPC_GetBlockSize (uint32_t* blk_size)
+ \brief Get the block size of the MPC. All regions must be aligned
+ on this block size (base address and limit+1 address).
+ \param[out] blk_size: The block size in bytes.
+ \return Returns error code.
+
+ \fn int32_t ARM_MPC_GetCtrlConfig (uint32_t* ctrl_val)
+ \brief Get some information on how the MPC IP is configured.
+ \param[out] ctrl_val: MPC control configuration
+ \return Returns error code.
+
+ \fn int32_t ARM_MPC_SetCtrlConfig (uint32_t ctrl)
+ \brief Set new control configuration for the MPC IP.
+ \param[in] ctrl: New control configuration.
+ \return Returns error code.
+
+ \fn int32_t ARM_MPC_ConfigRegion (uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+ \brief Configure a memory region (base and limit included).
+ Both base and limit addresses must belong to the same
+ memory range, and this range must be managed by this MPC.
+ Also, some ranges are only allowed to be configured as
+ secure/non-secure, because of hardware requirements
+ (security aliases), and only a relevant security attribute
+ is therefore allowed for such ranges.
+ \param[in] base: Base address of the region to configure. This
+ bound is included in the configured region.
+ This must be aligned on the block size of this MPC.
+ \param[in] limit: Limit address of the region to configure. This
+ bound is included in the configured region.
+ Limit+1 must be aligned on the block size of this MPC.
+ \param[in] attr: Wanted security attribute of the region.
+ \return Returns error code.
+
+ \fn int32_t ARM_MPC_GetRegionConfig (uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+ \brief Gets a memory region (base and limit included).
+ \param[in] base: Base address of the region to poll. This
+ bound is included. It does not need to be aligned
+ in any way.
+ \param[in] limit: Limit address of the region to poll. This
+ bound is included. (limit+1) does not need to be aligned
+ in any way.
+ \param[out] attr: Security attribute of the region.
+ If the region has mixed secure/non-secure,
+ a special value is returned (\ref ARM_MPC_SEC_ATTR).
+
+ In case base and limit+1 addresses are not aligned on
+ the block size, the enclosing region with base and
+ limit+1 aligned on block size will be queried.
+ In case of early termination of the function (error), the
+ security attribute will be set to ARM_MPC_ATTR_MIXED.
+ \return Returns error code.
\fn int32_t ARM_MPC_EnableInterrupt (void)
\brief Enable MPC interrupt.
@@ -128,12 +128,12 @@
\fn int32_t ARM_MPC_LockDown (void)
\brief Lock down the MPC configuration.
\return Returns error code.
-*/
-
-/**
- * \brief Access structure of the MPC Driver.
- */
-typedef struct _ARM_DRIVER_MPC {
+*/
+
+/**
+ * \brief Access structure of the MPC Driver.
+ */
+typedef struct _ARM_DRIVER_MPC {
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_MPC_GetVersion : Get driver version.
int32_t (*Initialize) (void); ///< Pointer to \ref ARM_MPC_Initialize : Initialize the MPC Interface.
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_MPC_Uninitialize : De-initialize the MPC Interface.
@@ -147,7 +147,7 @@
void (*ClearInterrupt) (void); ///< Pointer to \ref ARM_MPC_ClearInterrupt : Clear MPC interrupt.
uint32_t (*InterruptState) (void); ///< Pointer to \ref ARM_MPC_InterruptState : MPC interrupt State.
int32_t (*LockDown) (void); ///< Pointer to \ref ARM_MPC_LockDown : Lock down the MPC configuration.
-} const ARM_DRIVER_MPC;
-
-#endif /* __DRIVER_MPC_H */
-
+} const ARM_DRIVER_MPC;
+
+#endif /* __DRIVER_MPC_H */
+
diff --git a/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_bl2.S b/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_bl2.S
index d5ad2ab..1816a0c 100644
--- a/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_bl2.S
+++ b/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_bl2.S
@@ -1,439 +1,439 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.3.1 startup_ARMCM23.S
-; */
-
- .syntax unified
- .arch armv8-m.base
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
-
- /* Core interrupts */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* External interrupts */
- .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
- .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
- .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
- .long TIMER0_Handler /* 3: TIMER 0 Handler */
- .long TIMER1_Handler /* 4: TIMER 1 Handler */
- .long DUALTIMER_Handler /* 5: Dual Timer Handler */
- .long 0 /* 6: Reserved */
- .long 0 /* 7: Reserved */
- .long 0 /* 8: Reserved */
- .long MPC_Handler /* 9: MPC Combined (Secure) Handler */
- .long PPC_Handler /* 10: PPC Combined (Secure) Handler */
- .long MSC_Handler /* 11: MSC Combined (Secure) Handler */
- .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */
- .long 0 /* 13: Reserved */
- .long 0 /* 14: Reserved */
- .long 0 /* 15: Reserved */
- .long 0 /* 16: Reserved */
- .long 0 /* 17: Reserved */
- .long 0 /* 18: Reserved */
- .long 0 /* 19: Reserved */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long 0 /* 28: Reserved */
- .long 0 /* 29: Reserved */
- .long 0 /* 30: Reserved */
- .long 0 /* 31: Reserved */
- .long UARTRX0_Handler /* 32: UART 0 RX Handler */
- .long UARTTX0_Handler /* 33: UART 0 TX Handler */
- .long UARTRX1_Handler /* 34: UART 1 RX Handler */
- .long UARTTX1_Handler /* 35: UART 1 TX Handler */
- .long UARTRX2_Handler /* 36: UART 2 RX Handler */
- .long UARTTX2_Handler /* 37: UART 2 TX Handler */
- .long UARTRX3_Handler /* 38: UART 3 RX Handler */
- .long UARTTX3_Handler /* 39: UART 3 TX Handler */
- .long UARTRX4_Handler /* 40: UART 4 RX Handler */
- .long UARTTX4_Handler /* 41: UART 4 TX Handler */
- .long UART0_Handler /* 42: UART 0 combined Handler */
- .long UART1_Handler /* 43: UART 1 combined Handler */
- .long UART2_Handler /* 44: UART 2 combined Handler */
- .long UART3_Handler /* 45: UART 3 combined Handler */
- .long UART4_Handler /* 46: UART 4 combined Handler */
- .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
- .long ETHERNET_Handler /* 48: Ethernet Handler */
- .long I2S_Handler /* 49: I2S Handler */
- .long TSC_Handler /* 50: Touch Screen Handler */
- .long SPI0_Handler /* 51: SPI 0 Handler */
- .long SPI1_Handler /* 52: SPI 1 Handler */
- .long SPI2_Handler /* 53: SPI 2 Handler */
- .long SPI3_Handler /* 54: SPI 3 Handler */
- .long SPI4_Handler /* 55: SPI 4 Handler */
- .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
- .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
- .long DMA0_Handler /* 58: DMA 0 Combined Handler */
- .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
- .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
- .long DMA1_Handler /* 61: DMA 1 Combined Handler */
- .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
- .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
- .long DMA2_Handler /* 64: DMA 2 Combined Handler */
- .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
- .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
- .long DMA3_Handler /* 67: DMA 3 Combined Handler */
- .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
- .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
- .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
- .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
- .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
- .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
- .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
- .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
- .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
- .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
- .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
- .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
- .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
- .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
- .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
- .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
- .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
- .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
- .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
- .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
- .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
- .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
- .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
- .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
- .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
- .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
- .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
- .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
- .long GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
- .long GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
- .long GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
- .long GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
- .long GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
- .long GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
- .long GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
- .long GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
- .long GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
- .long GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
- .long GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
- .long GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
- .long GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
- .long GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
- .long GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
- .long GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
- .long GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
- .long GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
- .long GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
- .long GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
- .long GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
- .long GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
- .long GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
- .long GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
- .long GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
- .long GPIO3_1_Handler /* 121: GPIO 3_1 Handler */
- .long GPIO3_2_Handler /* 122: GPIO 3_2 Handler */
- .long GPIO3_3_Handler /* 123: GPIO 3_3 Handler */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- blt .L_loop0_0_done
- ldr r0, [r1, r3]
- str r0, [r2, r3]
- b .L_loop0_0
-
-.L_loop0_0_done:
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
- subs r3, r2
- ble .L_loop1_done
-
-.L_loop1:
- subs r3, #4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .L_loop1
-
-.L_loop1_done:
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- blt .L_loop2_0_done
- str r0, [r1, r2]
- b .L_loop2_0
-.L_loop2_0_done:
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-
- subs r2, r1
- ble .L_loop3_done
-
-.L_loop3:
- subs r2, #4
- str r0, [r1, r2]
- bgt .L_loop3
-.L_loop3_done:
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- bl SystemInit
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- /* Core interrupts */
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
-
- /* External interrupts */
- def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
- def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
- def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
- def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
- def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
- def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
- def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */
- def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */
- def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */
- def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */
- def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
- def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
- def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
- def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
- def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
- def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
- def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
- def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
- def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
- def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
- def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
- def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
- def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
- def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
- def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
- def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
- def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
- def_irq_handler I2S_Handler /* 49: I2S Handler */
- def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
- def_irq_handler SPI0_Handler /* 51: SPI 0 Handler */
- def_irq_handler SPI1_Handler /* 52: SPI 1 Handler */
- def_irq_handler SPI2_Handler /* 53: SPI 2 Handler */
- def_irq_handler SPI3_Handler /* 54: SPI 3 Handler */
- def_irq_handler SPI4_Handler /* 55: SPI 4 Handler */
- def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
- def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
- def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */
- def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
- def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
- def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */
- def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
- def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
- def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */
- def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
- def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
- def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */
- def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
- def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
- def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
- def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
- def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
- def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
- def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
- def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
- def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
- def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
- def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
- def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
- def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
- def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
- def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
- def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
- def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
- def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
- def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
- def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
- def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
- def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
- def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
- def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
- def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
- def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
- def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
- def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
- def_irq_handler GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
- def_irq_handler GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
- def_irq_handler GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
- def_irq_handler GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
- def_irq_handler GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
- def_irq_handler GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
- def_irq_handler GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
- def_irq_handler GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
- def_irq_handler GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
- def_irq_handler GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
- def_irq_handler GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
- def_irq_handler GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
- def_irq_handler GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
- def_irq_handler GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
- def_irq_handler GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
- def_irq_handler GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
- def_irq_handler GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
- def_irq_handler GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
- def_irq_handler GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
- def_irq_handler GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
- def_irq_handler GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
- def_irq_handler GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
- def_irq_handler GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
- def_irq_handler GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
- def_irq_handler GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
- def_irq_handler GPIO3_1_Handler /* 121: GPIO 3_1 Handler */
- def_irq_handler GPIO3_2_Handler /* 122: GPIO 3_2 Handler */
- def_irq_handler GPIO3_3_Handler /* 123: GPIO 3_3 Handler */
-
- .end
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.3.1 startup_ARMCM23.S
+; */
+
+ .syntax unified
+ .arch armv8-m.base
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+
+ /* Core interrupts */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ .long TIMER0_Handler /* 3: TIMER 0 Handler */
+ .long TIMER1_Handler /* 4: TIMER 1 Handler */
+ .long DUALTIMER_Handler /* 5: Dual Timer Handler */
+ .long 0 /* 6: Reserved */
+ .long 0 /* 7: Reserved */
+ .long 0 /* 8: Reserved */
+ .long MPC_Handler /* 9: MPC Combined (Secure) Handler */
+ .long PPC_Handler /* 10: PPC Combined (Secure) Handler */
+ .long MSC_Handler /* 11: MSC Combined (Secure) Handler */
+ .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */
+ .long 0 /* 13: Reserved */
+ .long 0 /* 14: Reserved */
+ .long 0 /* 15: Reserved */
+ .long 0 /* 16: Reserved */
+ .long 0 /* 17: Reserved */
+ .long 0 /* 18: Reserved */
+ .long 0 /* 19: Reserved */
+ .long 0 /* 20: Reserved */
+ .long 0 /* 21: Reserved */
+ .long 0 /* 22: Reserved */
+ .long 0 /* 23: Reserved */
+ .long 0 /* 24: Reserved */
+ .long 0 /* 25: Reserved */
+ .long 0 /* 26: Reserved */
+ .long 0 /* 27: Reserved */
+ .long 0 /* 28: Reserved */
+ .long 0 /* 29: Reserved */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+ .long UARTRX0_Handler /* 32: UART 0 RX Handler */
+ .long UARTTX0_Handler /* 33: UART 0 TX Handler */
+ .long UARTRX1_Handler /* 34: UART 1 RX Handler */
+ .long UARTTX1_Handler /* 35: UART 1 TX Handler */
+ .long UARTRX2_Handler /* 36: UART 2 RX Handler */
+ .long UARTTX2_Handler /* 37: UART 2 TX Handler */
+ .long UARTRX3_Handler /* 38: UART 3 RX Handler */
+ .long UARTTX3_Handler /* 39: UART 3 TX Handler */
+ .long UARTRX4_Handler /* 40: UART 4 RX Handler */
+ .long UARTTX4_Handler /* 41: UART 4 TX Handler */
+ .long UART0_Handler /* 42: UART 0 combined Handler */
+ .long UART1_Handler /* 43: UART 1 combined Handler */
+ .long UART2_Handler /* 44: UART 2 combined Handler */
+ .long UART3_Handler /* 45: UART 3 combined Handler */
+ .long UART4_Handler /* 46: UART 4 combined Handler */
+ .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ .long ETHERNET_Handler /* 48: Ethernet Handler */
+ .long I2S_Handler /* 49: I2S Handler */
+ .long TSC_Handler /* 50: Touch Screen Handler */
+ .long SPI0_Handler /* 51: SPI 0 Handler */
+ .long SPI1_Handler /* 52: SPI 1 Handler */
+ .long SPI2_Handler /* 53: SPI 2 Handler */
+ .long SPI3_Handler /* 54: SPI 3 Handler */
+ .long SPI4_Handler /* 55: SPI 4 Handler */
+ .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
+ .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
+ .long DMA0_Handler /* 58: DMA 0 Combined Handler */
+ .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
+ .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
+ .long DMA1_Handler /* 61: DMA 1 Combined Handler */
+ .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
+ .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
+ .long DMA2_Handler /* 64: DMA 2 Combined Handler */
+ .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
+ .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
+ .long DMA3_Handler /* 67: DMA 3 Combined Handler */
+ .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+ .long GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
+ .long GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
+ .long GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
+ .long GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
+ .long GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
+ .long GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
+ .long GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
+ .long GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
+ .long GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
+ .long GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
+ .long GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
+ .long GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
+ .long GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
+ .long GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
+ .long GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
+ .long GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
+ .long GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
+ .long GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
+ .long GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
+ .long GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
+ .long GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
+ .long GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
+ .long GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
+ .long GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
+ .long GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
+ .long GPIO3_1_Handler /* 121: GPIO 3_1 Handler */
+ .long GPIO3_2_Handler /* 122: GPIO 3_2 Handler */
+ .long GPIO3_3_Handler /* 123: GPIO 3_3 Handler */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ bl SystemInit
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ /* Core interrupts */
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* External interrupts */
+ def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
+ def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
+ def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
+ def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */
+ def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */
+ def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */
+ def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */
+ def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
+ def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
+ def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
+ def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
+ def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
+ def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
+ def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
+ def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
+ def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
+ def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
+ def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
+ def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
+ def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
+ def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
+ def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
+ def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
+ def_irq_handler I2S_Handler /* 49: I2S Handler */
+ def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
+ def_irq_handler SPI0_Handler /* 51: SPI 0 Handler */
+ def_irq_handler SPI1_Handler /* 52: SPI 1 Handler */
+ def_irq_handler SPI2_Handler /* 53: SPI 2 Handler */
+ def_irq_handler SPI3_Handler /* 54: SPI 3 Handler */
+ def_irq_handler SPI4_Handler /* 55: SPI 4 Handler */
+ def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
+ def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
+ def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */
+ def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
+ def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
+ def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */
+ def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
+ def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
+ def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */
+ def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
+ def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
+ def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */
+ def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+ def_irq_handler GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
+ def_irq_handler GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
+ def_irq_handler GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
+ def_irq_handler GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
+ def_irq_handler GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
+ def_irq_handler GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
+ def_irq_handler GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
+ def_irq_handler GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
+ def_irq_handler GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
+ def_irq_handler GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
+ def_irq_handler GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
+ def_irq_handler GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
+ def_irq_handler GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
+ def_irq_handler GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
+ def_irq_handler GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
+ def_irq_handler GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
+ def_irq_handler GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
+ def_irq_handler GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
+ def_irq_handler GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
+ def_irq_handler GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
+ def_irq_handler GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
+ def_irq_handler GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
+ def_irq_handler GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
+ def_irq_handler GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
+ def_irq_handler GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
+ def_irq_handler GPIO3_1_Handler /* 121: GPIO 3_1 Handler */
+ def_irq_handler GPIO3_2_Handler /* 122: GPIO 3_2 Handler */
+ def_irq_handler GPIO3_3_Handler /* 123: GPIO 3_3 Handler */
+
+ .end
diff --git a/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_ns.S b/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_ns.S
index 3b10898..023f914 100644
--- a/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_ns.S
+++ b/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_ns.S
@@ -1,442 +1,442 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.3.1 startup_ARMCM23.S
-; */
-
- .syntax unified
- .arch armv8-m.base
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
-
- /* Core interrupts */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* External interrupts */
- .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
- .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
- .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
- .long TIMER0_Handler /* 3: TIMER 0 Handler */
- .long TIMER1_Handler /* 4: TIMER 1 Handler */
- .long DUALTIMER_Handler /* 5: Dual Timer Handler */
- .long 0 /* 6: Reserved */
- .long 0 /* 7: Reserved */
- .long 0 /* 8: Reserved */
- .long 0 /* 9: Reserved */
- .long 0 /* 10: Reserved */
- .long 0 /* 11: Reserved */
- .long 0 /* 12: Reserved */
- .long 0 /* 13: Reserved */
- .long 0 /* 14: Reserved */
- .long 0 /* 15: Reserved */
- .long 0 /* 16: Reserved */
- .long 0 /* 17: Reserved */
- .long 0 /* 18: Reserved */
- .long 0 /* 19: Reserved */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long 0 /* 28: Reserved */
- .long 0 /* 29: Reserved */
- .long 0 /* 30: Reserved */
- .long 0 /* 31: Reserved */
- .long UARTRX0_Handler /* 32: UART 0 RX Handler */
- .long UARTTX0_Handler /* 33: UART 0 TX Handler */
- .long UARTRX1_Handler /* 34: UART 1 RX Handler */
- .long UARTTX1_Handler /* 35: UART 1 TX Handler */
- .long UARTRX2_Handler /* 36: UART 2 RX Handler */
- .long UARTTX2_Handler /* 37: UART 2 TX Handler */
- .long UARTRX3_Handler /* 38: UART 3 RX Handler */
- .long UARTTX3_Handler /* 39: UART 3 TX Handler */
- .long UARTRX4_Handler /* 40: UART 4 RX Handler */
- .long UARTTX4_Handler /* 41: UART 4 TX Handler */
- .long UART0_Handler /* 42: UART 0 combined Handler */
- .long UART1_Handler /* 43: UART 1 combined Handler */
- .long UART2_Handler /* 44: UART 2 combined Handler */
- .long UART3_Handler /* 45: UART 3 combined Handler */
- .long UART4_Handler /* 46: UART 4 combined Handler */
- .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
- .long ETHERNET_Handler /* 48: Ethernet Handler */
- .long I2S_Handler /* 49: I2S Handler */
- .long TSC_Handler /* 50: Touch Screen Handler */
- .long SPI0_Handler /* 51: SPI 0 Handler */
- .long SPI1_Handler /* 52: SPI 1 Handler */
- .long SPI2_Handler /* 53: SPI 2 Handler */
- .long SPI3_Handler /* 54: SPI 3 Handler */
- .long SPI4_Handler /* 55: SPI 4 Handler */
- .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
- .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
- .long DMA0_Handler /* 58: DMA 0 Combined Handler */
- .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
- .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
- .long DMA1_Handler /* 61: DMA 1 Combined Handler */
- .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
- .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
- .long DMA2_Handler /* 64: DMA 2 Combined Handler */
- .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
- .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
- .long DMA3_Handler /* 67: DMA 3 Combined Handler */
- .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
- .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
- .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
- .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
- .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
- .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
- .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
- .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
- .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
- .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
- .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
- .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
- .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
- .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
- .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
- .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
- .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
- .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
- .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
- .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
- .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
- .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
- .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
- .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
- .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
- .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
- .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
- .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
- .long GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
- .long GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
- .long GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
- .long GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
- .long GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
- .long GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
- .long GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
- .long GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
- .long GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
- .long GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
- .long GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
- .long GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
- .long GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
- .long GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
- .long GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
- .long GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
- .long GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
- .long GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
- .long GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
- .long GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
- .long GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
- .long GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
- .long GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
- .long GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
- .long GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
- .long GPIO3_1_Handler /* 121: GPIO 3_1 Handler */
- .long GPIO3_2_Handler /* 122: GPIO 3_2 Handler */
- .long GPIO3_3_Handler /* 123: GPIO 3_3 Handler */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- blt .L_loop0_0_done
- ldr r0, [r1, r3]
- str r0, [r2, r3]
- b .L_loop0_0
-
-.L_loop0_0_done:
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
- subs r3, r2
- ble .L_loop1_done
-
-.L_loop1:
- subs r3, #4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .L_loop1
-
-.L_loop1_done:
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- blt .L_loop2_0_done
- str r0, [r1, r2]
- b .L_loop2_0
-.L_loop2_0_done:
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-
- subs r2, r1
- ble .L_loop3_done
-
-.L_loop3:
- subs r2, #4
- str r0, [r1, r2]
- bgt .L_loop3
-.L_loop3_done:
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- mrs r0, control /* Get control value */
- movs r1, #1
- orrs r0, r0, r1 /* Select switch to unprivileged mode */
- movs r1, #2
- orrs r0, r0, r1 /* Select switch to PSP */
- msr control, r0
- ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
- msr psp, r0
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- /* Core interrupts */
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
-
- /* External interrupts */
- def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
- def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
- def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
- def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
- def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
- def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
- def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
- def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
- def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
- def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
- def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
- def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
- def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
- def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
- def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
- def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
- def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
- def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
- def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
- def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
- def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
- def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
- def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
- def_irq_handler I2S_Handler /* 49: I2S Handler */
- def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
- def_irq_handler SPI0_Handler /* 51: SPI 0 Handler */
- def_irq_handler SPI1_Handler /* 52: SPI 1 Handler */
- def_irq_handler SPI2_Handler /* 53: SPI 2 Handler */
- def_irq_handler SPI3_Handler /* 54: SPI 3 Handler */
- def_irq_handler SPI4_Handler /* 55: SPI 4 Handler */
- def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
- def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
- def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */
- def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
- def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
- def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */
- def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
- def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
- def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */
- def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
- def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
- def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */
- def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
- def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
- def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
- def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
- def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
- def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
- def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
- def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
- def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
- def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
- def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
- def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
- def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
- def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
- def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
- def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
- def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
- def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
- def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
- def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
- def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
- def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
- def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
- def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
- def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
- def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
- def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
- def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
- def_irq_handler GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
- def_irq_handler GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
- def_irq_handler GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
- def_irq_handler GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
- def_irq_handler GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
- def_irq_handler GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
- def_irq_handler GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
- def_irq_handler GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
- def_irq_handler GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
- def_irq_handler GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
- def_irq_handler GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
- def_irq_handler GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
- def_irq_handler GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
- def_irq_handler GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
- def_irq_handler GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
- def_irq_handler GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
- def_irq_handler GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
- def_irq_handler GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
- def_irq_handler GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
- def_irq_handler GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
- def_irq_handler GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
- def_irq_handler GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
- def_irq_handler GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
- def_irq_handler GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
- def_irq_handler GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
- def_irq_handler GPIO3_1_Handler /* 121: GPIO 3_1 Handler */
- def_irq_handler GPIO3_2_Handler /* 122: GPIO 3_2 Handler */
- def_irq_handler GPIO3_3_Handler /* 123: GPIO 3_3 Handler */
-
- .end
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.3.1 startup_ARMCM23.S
+; */
+
+ .syntax unified
+ .arch armv8-m.base
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+
+ /* Core interrupts */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ .long TIMER0_Handler /* 3: TIMER 0 Handler */
+ .long TIMER1_Handler /* 4: TIMER 1 Handler */
+ .long DUALTIMER_Handler /* 5: Dual Timer Handler */
+ .long 0 /* 6: Reserved */
+ .long 0 /* 7: Reserved */
+ .long 0 /* 8: Reserved */
+ .long 0 /* 9: Reserved */
+ .long 0 /* 10: Reserved */
+ .long 0 /* 11: Reserved */
+ .long 0 /* 12: Reserved */
+ .long 0 /* 13: Reserved */
+ .long 0 /* 14: Reserved */
+ .long 0 /* 15: Reserved */
+ .long 0 /* 16: Reserved */
+ .long 0 /* 17: Reserved */
+ .long 0 /* 18: Reserved */
+ .long 0 /* 19: Reserved */
+ .long 0 /* 20: Reserved */
+ .long 0 /* 21: Reserved */
+ .long 0 /* 22: Reserved */
+ .long 0 /* 23: Reserved */
+ .long 0 /* 24: Reserved */
+ .long 0 /* 25: Reserved */
+ .long 0 /* 26: Reserved */
+ .long 0 /* 27: Reserved */
+ .long 0 /* 28: Reserved */
+ .long 0 /* 29: Reserved */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+ .long UARTRX0_Handler /* 32: UART 0 RX Handler */
+ .long UARTTX0_Handler /* 33: UART 0 TX Handler */
+ .long UARTRX1_Handler /* 34: UART 1 RX Handler */
+ .long UARTTX1_Handler /* 35: UART 1 TX Handler */
+ .long UARTRX2_Handler /* 36: UART 2 RX Handler */
+ .long UARTTX2_Handler /* 37: UART 2 TX Handler */
+ .long UARTRX3_Handler /* 38: UART 3 RX Handler */
+ .long UARTTX3_Handler /* 39: UART 3 TX Handler */
+ .long UARTRX4_Handler /* 40: UART 4 RX Handler */
+ .long UARTTX4_Handler /* 41: UART 4 TX Handler */
+ .long UART0_Handler /* 42: UART 0 combined Handler */
+ .long UART1_Handler /* 43: UART 1 combined Handler */
+ .long UART2_Handler /* 44: UART 2 combined Handler */
+ .long UART3_Handler /* 45: UART 3 combined Handler */
+ .long UART4_Handler /* 46: UART 4 combined Handler */
+ .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ .long ETHERNET_Handler /* 48: Ethernet Handler */
+ .long I2S_Handler /* 49: I2S Handler */
+ .long TSC_Handler /* 50: Touch Screen Handler */
+ .long SPI0_Handler /* 51: SPI 0 Handler */
+ .long SPI1_Handler /* 52: SPI 1 Handler */
+ .long SPI2_Handler /* 53: SPI 2 Handler */
+ .long SPI3_Handler /* 54: SPI 3 Handler */
+ .long SPI4_Handler /* 55: SPI 4 Handler */
+ .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
+ .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
+ .long DMA0_Handler /* 58: DMA 0 Combined Handler */
+ .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
+ .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
+ .long DMA1_Handler /* 61: DMA 1 Combined Handler */
+ .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
+ .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
+ .long DMA2_Handler /* 64: DMA 2 Combined Handler */
+ .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
+ .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
+ .long DMA3_Handler /* 67: DMA 3 Combined Handler */
+ .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+ .long GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
+ .long GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
+ .long GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
+ .long GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
+ .long GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
+ .long GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
+ .long GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
+ .long GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
+ .long GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
+ .long GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
+ .long GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
+ .long GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
+ .long GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
+ .long GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
+ .long GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
+ .long GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
+ .long GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
+ .long GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
+ .long GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
+ .long GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
+ .long GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
+ .long GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
+ .long GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
+ .long GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
+ .long GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
+ .long GPIO3_1_Handler /* 121: GPIO 3_1 Handler */
+ .long GPIO3_2_Handler /* 122: GPIO 3_2 Handler */
+ .long GPIO3_3_Handler /* 123: GPIO 3_3 Handler */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ mrs r0, control /* Get control value */
+ movs r1, #1
+ orrs r0, r0, r1 /* Select switch to unprivileged mode */
+ movs r1, #2
+ orrs r0, r0, r1 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+ msr psp, r0
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ /* Core interrupts */
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* External interrupts */
+ def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
+ def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
+ def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
+ def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
+ def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
+ def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
+ def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
+ def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
+ def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
+ def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
+ def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
+ def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
+ def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
+ def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
+ def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
+ def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
+ def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
+ def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
+ def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
+ def_irq_handler I2S_Handler /* 49: I2S Handler */
+ def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
+ def_irq_handler SPI0_Handler /* 51: SPI 0 Handler */
+ def_irq_handler SPI1_Handler /* 52: SPI 1 Handler */
+ def_irq_handler SPI2_Handler /* 53: SPI 2 Handler */
+ def_irq_handler SPI3_Handler /* 54: SPI 3 Handler */
+ def_irq_handler SPI4_Handler /* 55: SPI 4 Handler */
+ def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
+ def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
+ def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */
+ def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
+ def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
+ def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */
+ def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
+ def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
+ def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */
+ def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
+ def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
+ def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */
+ def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+ def_irq_handler GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
+ def_irq_handler GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
+ def_irq_handler GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
+ def_irq_handler GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
+ def_irq_handler GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
+ def_irq_handler GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
+ def_irq_handler GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
+ def_irq_handler GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
+ def_irq_handler GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
+ def_irq_handler GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
+ def_irq_handler GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
+ def_irq_handler GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
+ def_irq_handler GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
+ def_irq_handler GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
+ def_irq_handler GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
+ def_irq_handler GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
+ def_irq_handler GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
+ def_irq_handler GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
+ def_irq_handler GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
+ def_irq_handler GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
+ def_irq_handler GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
+ def_irq_handler GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
+ def_irq_handler GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
+ def_irq_handler GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
+ def_irq_handler GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
+ def_irq_handler GPIO3_1_Handler /* 121: GPIO 3_1 Handler */
+ def_irq_handler GPIO3_2_Handler /* 122: GPIO 3_2 Handler */
+ def_irq_handler GPIO3_3_Handler /* 123: GPIO 3_3 Handler */
+
+ .end
diff --git a/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S b/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S
index df87164..fefc1cc 100644
--- a/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S
+++ b/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S
@@ -1,447 +1,447 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.3.1 startup_ARMCM23.S
-; */
-
- .syntax unified
- .arch armv8-m.base
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
-
- /* Core interrupts */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* External interrupts */
- .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
- .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
- .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
- .long TIMER0_Handler /* 3: TIMER 0 Handler */
- .long TIMER1_Handler /* 4: TIMER 1 Handler */
- .long DUALTIMER_Handler /* 5: Dual Timer Handler */
- .long 0 /* 6: Reserved */
- .long 0 /* 7: Reserved */
- .long 0 /* 8: Reserved */
- .long MPC_Handler /* 9: MPC Combined (Secure) Handler */
- .long PPC_Handler /* 10: PPC Combined (Secure) Handler */
- .long MSC_Handler /* 11: MSC Combined (Secure) Handler */
- .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */
- .long 0 /* 13: Reserved */
- .long 0 /* 14: Reserved */
- .long 0 /* 15: Reserved */
- .long 0 /* 16: Reserved */
- .long 0 /* 17: Reserved */
- .long 0 /* 18: Reserved */
- .long 0 /* 19: Reserved */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long 0 /* 28: Reserved */
- .long 0 /* 29: Reserved */
- .long 0 /* 30: Reserved */
- .long 0 /* 31: Reserved */
- .long UARTRX0_Handler /* 32: UART 0 RX Handler */
- .long UARTTX0_Handler /* 33: UART 0 TX Handler */
- .long UARTRX1_Handler /* 34: UART 1 RX Handler */
- .long UARTTX1_Handler /* 35: UART 1 TX Handler */
- .long UARTRX2_Handler /* 36: UART 2 RX Handler */
- .long UARTTX2_Handler /* 37: UART 2 TX Handler */
- .long UARTRX3_Handler /* 38: UART 3 RX Handler */
- .long UARTTX3_Handler /* 39: UART 3 TX Handler */
- .long UARTRX4_Handler /* 40: UART 4 RX Handler */
- .long UARTTX4_Handler /* 41: UART 4 TX Handler */
- .long UART0_Handler /* 42: UART 0 combined Handler */
- .long UART1_Handler /* 43: UART 1 combined Handler */
- .long UART2_Handler /* 44: UART 2 combined Handler */
- .long UART3_Handler /* 45: UART 3 combined Handler */
- .long UART4_Handler /* 46: UART 4 combined Handler */
- .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
- .long ETHERNET_Handler /* 48: Ethernet Handler */
- .long I2S_Handler /* 49: I2S Handler */
- .long TSC_Handler /* 50: Touch Screen Handler */
- .long SPI0_Handler /* 51: SPI 0 Handler */
- .long SPI1_Handler /* 52: SPI 1 Handler */
- .long SPI2_Handler /* 53: SPI 2 Handler */
- .long SPI3_Handler /* 54: SPI 3 Handler */
- .long SPI4_Handler /* 55: SPI 4 Handler */
- .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
- .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
- .long DMA0_Handler /* 58: DMA 0 Combined Handler */
- .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
- .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
- .long DMA1_Handler /* 61: DMA 1 Combined Handler */
- .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
- .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
- .long DMA2_Handler /* 64: DMA 2 Combined Handler */
- .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
- .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
- .long DMA3_Handler /* 67: DMA 3 Combined Handler */
- .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
- .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
- .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
- .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
- .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
- .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
- .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
- .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
- .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
- .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
- .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
- .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
- .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
- .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
- .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
- .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
- .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
- .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
- .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
- .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
- .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
- .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
- .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
- .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
- .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
- .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
- .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
- .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
- .long GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
- .long GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
- .long GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
- .long GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
- .long GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
- .long GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
- .long GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
- .long GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
- .long GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
- .long GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
- .long GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
- .long GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
- .long GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
- .long GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
- .long GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
- .long GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
- .long GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
- .long GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
- .long GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
- .long GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
- .long GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
- .long GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
- .long GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
- .long GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
- .long GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
- .long GPIO3_1_Handler /* 121: GPIO 3_1 Handler */
- .long GPIO3_2_Handler /* 122: GPIO 3_2 Handler */
- .long GPIO3_3_Handler /* 123: GPIO 3_3 Handler */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- blt .L_loop0_0_done
- ldr r0, [r1, r3]
- str r0, [r2, r3]
- b .L_loop0_0
-
-.L_loop0_0_done:
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
- subs r3, r2
- ble .L_loop1_done
-
-.L_loop1:
- subs r3, #4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .L_loop1
-
-.L_loop1_done:
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- blt .L_loop2_0_done
- str r0, [r1, r2]
- b .L_loop2_0
-.L_loop2_0_done:
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-
- subs r2, r1
- ble .L_loop3_done
-
-.L_loop3:
- subs r2, #4
- str r0, [r1, r2]
- bgt .L_loop3
-.L_loop3_done:
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- cpsid i /* Disable IRQs */
- bl SystemInit
-
- mrs r0, control /* Get control value */
- movs r1, #2
- orrs r0, r0, r1 /* Select switch to PSP */
- msr control, r0
- ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
- msr psp, r0
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- /* Core interrupts */
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
-
- /* External interrupts */
- def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
- def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
- def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
- def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
- def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
- def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
- def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */
- def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */
- def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */
- def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */
- def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
- def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
- def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
- def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
- def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
- def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
- def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
- def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
- def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
- def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
- def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
- def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
- def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
- def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
- def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
- def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
- def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
- def_irq_handler I2S_Handler /* 49: I2S Handler */
- def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
- def_irq_handler SPI0_Handler /* 51: SPI 0 Handler */
- def_irq_handler SPI1_Handler /* 52: SPI 1 Handler */
- def_irq_handler SPI2_Handler /* 53: SPI 2 Handler */
- def_irq_handler SPI3_Handler /* 54: SPI 3 Handler */
- def_irq_handler SPI4_Handler /* 55: SPI 4 Handler */
- def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
- def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
- def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */
- def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
- def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
- def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */
- def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
- def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
- def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */
- def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
- def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
- def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */
- def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
- def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
- def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
- def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
- def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
- def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
- def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
- def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
- def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
- def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
- def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
- def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
- def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
- def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
- def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
- def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
- def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
- def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
- def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
- def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
- def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
- def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
- def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
- def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
- def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
- def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
- def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
- def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
- def_irq_handler GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
- def_irq_handler GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
- def_irq_handler GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
- def_irq_handler GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
- def_irq_handler GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
- def_irq_handler GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
- def_irq_handler GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
- def_irq_handler GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
- def_irq_handler GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
- def_irq_handler GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
- def_irq_handler GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
- def_irq_handler GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
- def_irq_handler GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
- def_irq_handler GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
- def_irq_handler GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
- def_irq_handler GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
- def_irq_handler GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
- def_irq_handler GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
- def_irq_handler GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
- def_irq_handler GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
- def_irq_handler GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
- def_irq_handler GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
- def_irq_handler GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
- def_irq_handler GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
- def_irq_handler GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
- def_irq_handler GPIO3_1_Handler /* 121: GPIO 3_1 Handler */
- def_irq_handler GPIO3_2_Handler /* 122: GPIO 3_2 Handler */
- def_irq_handler GPIO3_3_Handler /* 123: GPIO 3_3 Handler */
-
- .end
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.3.1 startup_ARMCM23.S
+; */
+
+ .syntax unified
+ .arch armv8-m.base
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+
+ /* Core interrupts */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ .long TIMER0_Handler /* 3: TIMER 0 Handler */
+ .long TIMER1_Handler /* 4: TIMER 1 Handler */
+ .long DUALTIMER_Handler /* 5: Dual Timer Handler */
+ .long 0 /* 6: Reserved */
+ .long 0 /* 7: Reserved */
+ .long 0 /* 8: Reserved */
+ .long MPC_Handler /* 9: MPC Combined (Secure) Handler */
+ .long PPC_Handler /* 10: PPC Combined (Secure) Handler */
+ .long MSC_Handler /* 11: MSC Combined (Secure) Handler */
+ .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */
+ .long 0 /* 13: Reserved */
+ .long 0 /* 14: Reserved */
+ .long 0 /* 15: Reserved */
+ .long 0 /* 16: Reserved */
+ .long 0 /* 17: Reserved */
+ .long 0 /* 18: Reserved */
+ .long 0 /* 19: Reserved */
+ .long 0 /* 20: Reserved */
+ .long 0 /* 21: Reserved */
+ .long 0 /* 22: Reserved */
+ .long 0 /* 23: Reserved */
+ .long 0 /* 24: Reserved */
+ .long 0 /* 25: Reserved */
+ .long 0 /* 26: Reserved */
+ .long 0 /* 27: Reserved */
+ .long 0 /* 28: Reserved */
+ .long 0 /* 29: Reserved */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+ .long UARTRX0_Handler /* 32: UART 0 RX Handler */
+ .long UARTTX0_Handler /* 33: UART 0 TX Handler */
+ .long UARTRX1_Handler /* 34: UART 1 RX Handler */
+ .long UARTTX1_Handler /* 35: UART 1 TX Handler */
+ .long UARTRX2_Handler /* 36: UART 2 RX Handler */
+ .long UARTTX2_Handler /* 37: UART 2 TX Handler */
+ .long UARTRX3_Handler /* 38: UART 3 RX Handler */
+ .long UARTTX3_Handler /* 39: UART 3 TX Handler */
+ .long UARTRX4_Handler /* 40: UART 4 RX Handler */
+ .long UARTTX4_Handler /* 41: UART 4 TX Handler */
+ .long UART0_Handler /* 42: UART 0 combined Handler */
+ .long UART1_Handler /* 43: UART 1 combined Handler */
+ .long UART2_Handler /* 44: UART 2 combined Handler */
+ .long UART3_Handler /* 45: UART 3 combined Handler */
+ .long UART4_Handler /* 46: UART 4 combined Handler */
+ .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ .long ETHERNET_Handler /* 48: Ethernet Handler */
+ .long I2S_Handler /* 49: I2S Handler */
+ .long TSC_Handler /* 50: Touch Screen Handler */
+ .long SPI0_Handler /* 51: SPI 0 Handler */
+ .long SPI1_Handler /* 52: SPI 1 Handler */
+ .long SPI2_Handler /* 53: SPI 2 Handler */
+ .long SPI3_Handler /* 54: SPI 3 Handler */
+ .long SPI4_Handler /* 55: SPI 4 Handler */
+ .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
+ .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
+ .long DMA0_Handler /* 58: DMA 0 Combined Handler */
+ .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
+ .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
+ .long DMA1_Handler /* 61: DMA 1 Combined Handler */
+ .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
+ .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
+ .long DMA2_Handler /* 64: DMA 2 Combined Handler */
+ .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
+ .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
+ .long DMA3_Handler /* 67: DMA 3 Combined Handler */
+ .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+ .long GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
+ .long GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
+ .long GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
+ .long GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
+ .long GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
+ .long GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
+ .long GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
+ .long GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
+ .long GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
+ .long GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
+ .long GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
+ .long GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
+ .long GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
+ .long GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
+ .long GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
+ .long GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
+ .long GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
+ .long GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
+ .long GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
+ .long GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
+ .long GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
+ .long GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
+ .long GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
+ .long GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
+ .long GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
+ .long GPIO3_1_Handler /* 121: GPIO 3_1 Handler */
+ .long GPIO3_2_Handler /* 122: GPIO 3_2 Handler */
+ .long GPIO3_3_Handler /* 123: GPIO 3_3 Handler */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ cpsid i /* Disable IRQs */
+ bl SystemInit
+
+ mrs r0, control /* Get control value */
+ movs r1, #2
+ orrs r0, r0, r1 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+ msr psp, r0
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ /* Core interrupts */
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* External interrupts */
+ def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
+ def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
+ def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
+ def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */
+ def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */
+ def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */
+ def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */
+ def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
+ def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
+ def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
+ def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
+ def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
+ def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
+ def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
+ def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
+ def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
+ def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
+ def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
+ def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
+ def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
+ def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
+ def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
+ def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
+ def_irq_handler I2S_Handler /* 49: I2S Handler */
+ def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
+ def_irq_handler SPI0_Handler /* 51: SPI 0 Handler */
+ def_irq_handler SPI1_Handler /* 52: SPI 1 Handler */
+ def_irq_handler SPI2_Handler /* 53: SPI 2 Handler */
+ def_irq_handler SPI3_Handler /* 54: SPI 3 Handler */
+ def_irq_handler SPI4_Handler /* 55: SPI 4 Handler */
+ def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
+ def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
+ def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */
+ def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
+ def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
+ def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */
+ def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
+ def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
+ def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */
+ def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
+ def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
+ def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */
+ def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+ def_irq_handler GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
+ def_irq_handler GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
+ def_irq_handler GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
+ def_irq_handler GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
+ def_irq_handler GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
+ def_irq_handler GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
+ def_irq_handler GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
+ def_irq_handler GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
+ def_irq_handler GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
+ def_irq_handler GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
+ def_irq_handler GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
+ def_irq_handler GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
+ def_irq_handler GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
+ def_irq_handler GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
+ def_irq_handler GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
+ def_irq_handler GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
+ def_irq_handler GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
+ def_irq_handler GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
+ def_irq_handler GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
+ def_irq_handler GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
+ def_irq_handler GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
+ def_irq_handler GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
+ def_irq_handler GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
+ def_irq_handler GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
+ def_irq_handler GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
+ def_irq_handler GPIO3_1_Handler /* 121: GPIO 3_1 Handler */
+ def_irq_handler GPIO3_2_Handler /* 122: GPIO 3_2 Handler */
+ def_irq_handler GPIO3_3_Handler /* 123: GPIO 3_3 Handler */
+
+ .end
diff --git a/platform/ext/target/mps2/an519/spm_hal.c b/platform/ext/target/mps2/an519/spm_hal.c
index 1dd7be3..9899fa7 100644
--- a/platform/ext/target/mps2/an519/spm_hal.c
+++ b/platform/ext/target/mps2/an519/spm_hal.c
@@ -1,324 +1,324 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#include <stdio.h>
-#include "platform/include/tfm_spm_hal.h"
-#include "spm_api.h"
-#include "spm_db.h"
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdio.h>
+#include "platform/include/tfm_spm_hal.h"
+#include "spm_api.h"
+#include "spm_db.h"
#include "tfm_platform_core_api.h"
-#include "target_cfg.h"
-#include "Driver_MPC.h"
-#include "mpu_armv8m_drv.h"
-#include "region_defs.h"
-#include "secure_utilities.h"
-
-/* Import MPC driver */
-extern ARM_DRIVER_MPC Driver_SRAM1_MPC;
-
-/* Get address of memory regions to configure MPU */
-extern const struct memory_region_limits memory_regions;
-
-struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
-
-void tfm_spm_hal_init_isolation_hw(void)
-{
- /* Configures non-secure memory spaces in the target */
- sau_and_idau_cfg();
- mpc_init_cfg();
- ppc_init_cfg();
-}
-
-void tfm_spm_hal_configure_default_isolation(
- const struct tfm_spm_partition_platform_data_t *platform_data)
-{
- if (platform_data) {
- if (platform_data->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) {
- ppc_configure_to_secure(platform_data->periph_ppc_bank,
- platform_data->periph_ppc_loc);
- }
- }
-}
-
-#if TFM_LVL != 1
-
-#define MPU_REGION_VENEERS 0
-#define MPU_REGION_TFM_UNPRIV_CODE 1
-#define MPU_REGION_TFM_UNPRIV_DATA 2
-#define MPU_REGION_NS_DATA 3
-#define PARTITION_REGION_RO 4
-#define PARTITION_REGION_RW_STACK 5
-#define PARTITION_REGION_PERIPH 6
-#define PARTITION_REGION_SHARE 7
-
-REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
-REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
-REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
-REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
-REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
-REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
-
-static enum spm_err_t tfm_spm_mpu_init(void)
-{
- struct mpu_armv8m_region_cfg_t region_cfg;
-
- mpu_armv8m_clean(&dev_mpu_s);
-
- /* Veneer region */
- region_cfg.region_nr = MPU_REGION_VENEERS;
- region_cfg.region_base = memory_regions.veneer_base;
- region_cfg.region_limit = memory_regions.veneer_limit;
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- /* TFM Core unprivileged code region */
- region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_CODE;
- region_cfg.region_base =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
- region_cfg.region_limit =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- /* TFM Core unprivileged data region */
- region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_DATA;
- region_cfg.region_base =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
- region_cfg.region_limit =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- /* TFM Core unprivileged non-secure data region */
- region_cfg.region_nr = MPU_REGION_NS_DATA;
- region_cfg.region_base = NS_DATA_START;
- region_cfg.region_limit = NS_DATA_LIMIT;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return SPM_ERR_OK;
-}
-
-enum spm_err_t tfm_spm_hal_partition_sandbox_config(
- const struct tfm_spm_partition_memory_data_t *memory_data,
- const struct tfm_spm_partition_platform_data_t *platform_data)
-{
- /* This function takes a partition id and enables the
- * SPM partition for that partition
- */
-
- struct mpu_armv8m_region_cfg_t region_cfg;
-
- mpu_armv8m_disable(&dev_mpu_s);
-
- /* Configure Regions */
- if (memory_data->ro_start) {
- /* RO region */
- region_cfg.region_nr = PARTITION_REGION_RO;
- region_cfg.region_base = memory_data->ro_start;
- region_cfg.region_limit = memory_data->ro_limit;
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
-
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
- != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
- }
-
- /* RW, ZI and stack as one region */
- region_cfg.region_nr = PARTITION_REGION_RW_STACK;
- region_cfg.region_base = memory_data->rw_start;
- region_cfg.region_limit = memory_data->stack_top;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
-
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- if (platform_data) {
- /* Peripheral */
- region_cfg.region_nr = PARTITION_REGION_PERIPH;
- region_cfg.region_base = platform_data->periph_start;
- region_cfg.region_limit = platform_data->periph_limit;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
- != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- ppc_en_secure_unpriv(platform_data->periph_ppc_bank,
- platform_data->periph_ppc_loc);
- }
-
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return SPM_ERR_OK;
-}
-
-enum spm_err_t tfm_spm_hal_partition_sandbox_deconfig(
- const struct tfm_spm_partition_memory_data_t *memory_data,
- const struct tfm_spm_partition_platform_data_t *platform_data)
-{
- /* This function takes a partition id and disables the
- * SPM partition for that partition
- */
-
- if (platform_data) {
- /* Peripheral */
- ppc_clr_secure_unpriv(platform_data->periph_ppc_bank,
- platform_data->periph_ppc_loc);
- }
-
- mpu_armv8m_disable(&dev_mpu_s);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RO);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RW_STACK);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_PERIPH);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return SPM_ERR_OK;
-}
-
-/**
- * Set share region to which the partition needs access
- */
-enum spm_err_t tfm_spm_hal_set_share_region(
- enum tfm_buffer_share_region_e share)
-{
- struct mpu_armv8m_region_cfg_t region_cfg;
- enum spm_err_t res = SPM_ERR_INVALID_CONFIG;
- uint32_t scratch_base =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
- uint32_t scratch_limit =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
-
- mpu_armv8m_disable(&dev_mpu_s);
-
- if (share == TFM_BUFFER_SHARE_DISABLE) {
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
- } else {
-
- region_cfg.region_nr = PARTITION_REGION_SHARE;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- switch (share) {
- case TFM_BUFFER_SHARE_SCRATCH:
- /* Use scratch area for SP-to-SP data sharing */
- region_cfg.region_base = scratch_base;
- region_cfg.region_limit = scratch_limit;
- res = SPM_ERR_OK;
- break;
- case TFM_BUFFER_SHARE_NS_CODE:
- region_cfg.region_base = memory_regions.non_secure_partition_base;
- region_cfg.region_limit = memory_regions.non_secure_partition_limit;
- /* Only allow read access to NS code region and keep
- * exec.never attribute
- */
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- res = SPM_ERR_OK;
- break;
- default:
- /* Leave res to be set to SPM_ERR_INVALID_CONFIG */
- break;
- }
- if (res == SPM_ERR_OK) {
- mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg);
- }
- }
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return res;
-}
-
-#endif /* TFM_LVL != 1 */
-
-void tfm_spm_hal_setup_isolation_hw(void)
-{
-#if TFM_LVL != 1
- if (tfm_spm_mpu_init() != SPM_ERR_OK) {
- ERROR_MSG("Failed to set up initial MPU configuration! Halting.");
- while (1) {
- ;
- }
- }
-#endif
-}
-
-void MPC_Handler(void)
-{
- /* Clear MPC interrupt flag and pending MPC IRQ */
- Driver_SRAM1_MPC.ClearInterrupt();
- NVIC_ClearPendingIRQ(MPC_IRQn);
-
- /* Print fault message and block execution */
- LOG_MSG("Oops... MPC fault!!!");
-
- /* Inform TF-M core that isolation boundary has been violated */
- tfm_access_violation_handler();
-}
-
-void PPC_Handler(void)
-{
- /*
- * Due to an issue on the FVP, the PPC fault doesn't trigger a
- * PPC IRQ which is handled by the PPC_handler.
- * In the FVP execution, this code is not execute.
- */
-
- /* Clear PPC interrupt flag and pending PPC IRQ */
- ppc_clear_irq();
- NVIC_ClearPendingIRQ(PPC_IRQn);
-
- /* Print fault message*/
- LOG_MSG("Oops... PPC fault!!!");
-
- /* Inform TF-M core that isolation boundary has been violated */
- tfm_access_violation_handler();
-}
-
-uint32_t tfm_spm_hal_get_ns_VTOR(void)
-{
- return memory_regions.non_secure_code_start;
-}
-
-uint32_t tfm_spm_hal_get_ns_MSP(void)
-{
- return *((uint32_t *)memory_regions.non_secure_code_start);
-}
-
-uint32_t tfm_spm_hal_get_ns_entry_point(void)
-{
- return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
-}
+#include "target_cfg.h"
+#include "Driver_MPC.h"
+#include "mpu_armv8m_drv.h"
+#include "region_defs.h"
+#include "secure_utilities.h"
+
+/* Import MPC driver */
+extern ARM_DRIVER_MPC Driver_SRAM1_MPC;
+
+/* Get address of memory regions to configure MPU */
+extern const struct memory_region_limits memory_regions;
+
+struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
+
+void tfm_spm_hal_init_isolation_hw(void)
+{
+ /* Configures non-secure memory spaces in the target */
+ sau_and_idau_cfg();
+ mpc_init_cfg();
+ ppc_init_cfg();
+}
+
+void tfm_spm_hal_configure_default_isolation(
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ if (platform_data) {
+ if (platform_data->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) {
+ ppc_configure_to_secure(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+ }
+}
+
+#if TFM_LVL != 1
+
+#define MPU_REGION_VENEERS 0
+#define MPU_REGION_TFM_UNPRIV_CODE 1
+#define MPU_REGION_TFM_UNPRIV_DATA 2
+#define MPU_REGION_NS_DATA 3
+#define PARTITION_REGION_RO 4
+#define PARTITION_REGION_RW_STACK 5
+#define PARTITION_REGION_PERIPH 6
+#define PARTITION_REGION_SHARE 7
+
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
+
+static enum spm_err_t tfm_spm_mpu_init(void)
+{
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_armv8m_clean(&dev_mpu_s);
+
+ /* Veneer region */
+ region_cfg.region_nr = MPU_REGION_VENEERS;
+ region_cfg.region_base = memory_regions.veneer_base;
+ region_cfg.region_limit = memory_regions.veneer_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged code region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_CODE;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged data region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_DATA;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged non-secure data region */
+ region_cfg.region_nr = MPU_REGION_NS_DATA;
+ region_cfg.region_base = NS_DATA_START;
+ region_cfg.region_limit = NS_DATA_LIMIT;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+enum spm_err_t tfm_spm_hal_partition_sandbox_config(
+ const struct tfm_spm_partition_memory_data_t *memory_data,
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ /* This function takes a partition id and enables the
+ * SPM partition for that partition
+ */
+
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_armv8m_disable(&dev_mpu_s);
+
+ /* Configure Regions */
+ if (memory_data->ro_start) {
+ /* RO region */
+ region_cfg.region_nr = PARTITION_REGION_RO;
+ region_cfg.region_base = memory_data->ro_start;
+ region_cfg.region_limit = memory_data->ro_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
+ != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+ }
+
+ /* RW, ZI and stack as one region */
+ region_cfg.region_nr = PARTITION_REGION_RW_STACK;
+ region_cfg.region_base = memory_data->rw_start;
+ region_cfg.region_limit = memory_data->stack_top;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ if (platform_data) {
+ /* Peripheral */
+ region_cfg.region_nr = PARTITION_REGION_PERIPH;
+ region_cfg.region_base = platform_data->periph_start;
+ region_cfg.region_limit = platform_data->periph_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
+ != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ ppc_en_secure_unpriv(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+enum spm_err_t tfm_spm_hal_partition_sandbox_deconfig(
+ const struct tfm_spm_partition_memory_data_t *memory_data,
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ /* This function takes a partition id and disables the
+ * SPM partition for that partition
+ */
+
+ if (platform_data) {
+ /* Peripheral */
+ ppc_clr_secure_unpriv(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+
+ mpu_armv8m_disable(&dev_mpu_s);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RO);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RW_STACK);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_PERIPH);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+/**
+ * Set share region to which the partition needs access
+ */
+enum spm_err_t tfm_spm_hal_set_share_region(
+ enum tfm_buffer_share_region_e share)
+{
+ struct mpu_armv8m_region_cfg_t region_cfg;
+ enum spm_err_t res = SPM_ERR_INVALID_CONFIG;
+ uint32_t scratch_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
+ uint32_t scratch_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
+
+ mpu_armv8m_disable(&dev_mpu_s);
+
+ if (share == TFM_BUFFER_SHARE_DISABLE) {
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
+ } else {
+
+ region_cfg.region_nr = PARTITION_REGION_SHARE;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ switch (share) {
+ case TFM_BUFFER_SHARE_SCRATCH:
+ /* Use scratch area for SP-to-SP data sharing */
+ region_cfg.region_base = scratch_base;
+ region_cfg.region_limit = scratch_limit;
+ res = SPM_ERR_OK;
+ break;
+ case TFM_BUFFER_SHARE_NS_CODE:
+ region_cfg.region_base = memory_regions.non_secure_partition_base;
+ region_cfg.region_limit = memory_regions.non_secure_partition_limit;
+ /* Only allow read access to NS code region and keep
+ * exec.never attribute
+ */
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ res = SPM_ERR_OK;
+ break;
+ default:
+ /* Leave res to be set to SPM_ERR_INVALID_CONFIG */
+ break;
+ }
+ if (res == SPM_ERR_OK) {
+ mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg);
+ }
+ }
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return res;
+}
+
+#endif /* TFM_LVL != 1 */
+
+void tfm_spm_hal_setup_isolation_hw(void)
+{
+#if TFM_LVL != 1
+ if (tfm_spm_mpu_init() != SPM_ERR_OK) {
+ ERROR_MSG("Failed to set up initial MPU configuration! Halting.");
+ while (1) {
+ ;
+ }
+ }
+#endif
+}
+
+void MPC_Handler(void)
+{
+ /* Clear MPC interrupt flag and pending MPC IRQ */
+ Driver_SRAM1_MPC.ClearInterrupt();
+ NVIC_ClearPendingIRQ(MPC_IRQn);
+
+ /* Print fault message and block execution */
+ LOG_MSG("Oops... MPC fault!!!");
+
+ /* Inform TF-M core that isolation boundary has been violated */
+ tfm_access_violation_handler();
+}
+
+void PPC_Handler(void)
+{
+ /*
+ * Due to an issue on the FVP, the PPC fault doesn't trigger a
+ * PPC IRQ which is handled by the PPC_handler.
+ * In the FVP execution, this code is not execute.
+ */
+
+ /* Clear PPC interrupt flag and pending PPC IRQ */
+ ppc_clear_irq();
+ NVIC_ClearPendingIRQ(PPC_IRQn);
+
+ /* Print fault message*/
+ LOG_MSG("Oops... PPC fault!!!");
+
+ /* Inform TF-M core that isolation boundary has been violated */
+ tfm_access_violation_handler();
+}
+
+uint32_t tfm_spm_hal_get_ns_VTOR(void)
+{
+ return memory_regions.non_secure_code_start;
+}
+
+uint32_t tfm_spm_hal_get_ns_MSP(void)
+{
+ return *((uint32_t *)memory_regions.non_secure_code_start);
+}
+
+uint32_t tfm_spm_hal_get_ns_entry_point(void)
+{
+ return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
+}
diff --git a/platform/ext/target/mps2/an519/tfm_peripherals_def.h b/platform/ext/target/mps2/an519/tfm_peripherals_def.h
index ee8c354..340a19c 100644
--- a/platform/ext/target/mps2/an519/tfm_peripherals_def.h
+++ b/platform/ext/target/mps2/an519/tfm_peripherals_def.h
@@ -1,21 +1,21 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef __TFM_PERIPHERALS_DEF_H__
-#define __TFM_PERIPHERALS_DEF_H__
-
-struct tfm_spm_partition_platform_data_t;
-
-extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
-extern struct tfm_spm_partition_platform_data_t tfm_peripheral_uart1;
-extern struct tfm_spm_partition_platform_data_t tfm_peripheral_fpga_io;
-
-#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart)
-#define TFM_PERIPHERAL_UART1 (&tfm_peripheral_uart1)
-#define TFM_PERIPHERAL_FPGA_IO (&tfm_peripheral_fpga_io)
-
-#endif /* __TFM_PERIPHERALS_DEF_H__ */
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __TFM_PERIPHERALS_DEF_H__
+#define __TFM_PERIPHERALS_DEF_H__
+
+struct tfm_spm_partition_platform_data_t;
+
+extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
+extern struct tfm_spm_partition_platform_data_t tfm_peripheral_uart1;
+extern struct tfm_spm_partition_platform_data_t tfm_peripheral_fpga_io;
+
+#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart)
+#define TFM_PERIPHERAL_UART1 (&tfm_peripheral_uart1)
+#define TFM_PERIPHERAL_FPGA_IO (&tfm_peripheral_fpga_io)
+
+#endif /* __TFM_PERIPHERALS_DEF_H__ */
diff --git a/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_ns.s b/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_ns.s
index a506754..3004c01 100644
--- a/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_ns.s
+++ b/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_ns.s
@@ -1,370 +1,370 @@
-;/*
-; * Copyright (c) 2016-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-;
-; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
- IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; Core IoT Interrupts
- DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
- DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
- DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
- DCD TIMER0_Handler ; - 3 TIMER 0 Handler
- DCD TIMER1_Handler ; - 4 TIMER 1 Handler
- DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
- DCD 0 ; Reserved - 6
- DCD 0 ; Reserved - 7
- DCD 0 ; Reserved - 8
- DCD 0 ; Reserved - 9
- DCD 0 ; Reserved - 10
- DCD 0 ; Reserved - 11
- DCD 0 ; Reserved - 12
- DCD 0 ; Reserved - 13
- DCD 0 ; Reserved - 14
- DCD 0 ; Reserved - 15
- DCD 0 ; Reserved - 16
- DCD 0 ; Reserved - 17
- DCD 0 ; Reserved - 18
- DCD 0 ; Reserved - 19
- DCD 0 ; Reserved - 20
- DCD 0 ; Reserved - 21
- DCD 0 ; Reserved - 22
- DCD 0 ; Reserved - 23
- DCD 0 ; Reserved - 24
- DCD 0 ; Reserved - 25
- DCD 0 ; Reserved - 26
- DCD 0 ; Reserved - 27
- DCD 0 ; Reserved - 28
- DCD 0 ; Reserved - 29
- DCD 0 ; Reserved - 30
- DCD 0 ; Reserved - 31
- ; External Interrupts
- DCD UARTRX0_Handler ; 32 UART 0 RX Handler
- DCD UARTTX0_Handler ; 33 UART 0 TX Handler
- DCD UARTRX1_Handler ; 34 UART 1 RX Handler
- DCD UARTTX1_Handler ; 35 UART 1 TX Handler
- DCD UARTRX2_Handler ; 36 UART 2 RX Handler
- DCD UARTTX2_Handler ; 37 UART 2 TX Handler
- DCD UARTRX3_Handler ; 38 UART 3 RX Handler
- DCD UARTTX3_Handler ; 39 UART 3 TX Handler
- DCD UARTRX4_Handler ; 40 UART 4 RX Handler
- DCD UARTTX4_Handler ; 41 UART 4 TX Handler
- DCD UART0_Handler ; 42 UART 0 combined Handler
- DCD UART1_Handler ; 43 UART 1 combined Handler
- DCD UART2_Handler ; 44 UART 0 combined Handler
- DCD UART3_Handler ; 45 UART 1 combined Handler
- DCD UART4_Handler ; 46 UART 0 combined Handler
- DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
- DCD ETHERNET_Handler ; 48 Ethernet Handler
- DCD I2S_Handler ; 49 I2S Handler
- DCD TSC_Handler ; 50 Touch Screen Handler
- DCD SPI0_Handler ; 51 SPI 0 Handler
- DCD SPI1_Handler ; 52 SPI 1 Handler
- DCD SPI2_Handler ; 53 SPI 2 Handler
- DCD SPI3_Handler ; 54 SPI 3 Handler
- DCD SPI4_Handler ; 55 SPI 4 Handler
- DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
- DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
- DCD DMA0_Handler ; 58 DMA 0 Combined Handler
- DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
- DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
- DCD DMA1_Handler ; 61 DMA 1 Combined Handler
- DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
- DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
- DCD DMA2_Handler ; 64 DMA 2 Combined Handler
- DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
- DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
- DCD DMA3_Handler ; 67 DMA 3 Combined Handler
- DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
- DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
- DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
- DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
- DCD GPIO0_0_Handler ; 72,
- DCD GPIO0_1_Handler ; 73,
- DCD GPIO0_2_Handler ; 74,
- DCD GPIO0_3_Handler ; 75,
- DCD GPIO0_4_Handler ; 76,
- DCD GPIO0_5_Handler ; 77,
- DCD GPIO0_6_Handler ; 78,
- DCD GPIO0_7_Handler ; 79,
- DCD GPIO0_8_Handler ; 80,
- DCD GPIO0_9_Handler ; 81,
- DCD GPIO0_10_Handler ; 82,
- DCD GPIO0_11_Handler ; 83,
- DCD GPIO0_12_Handler ; 84,
- DCD GPIO0_13_Handler ; 85,
- DCD GPIO0_14_Handler ; 86,
- DCD GPIO0_15_Handler ; 87,
- DCD GPIO1_0_Handler ; 88,
- DCD GPIO1_1_Handler ; 89,
- DCD GPIO1_2_Handler ; 90,
- DCD GPIO1_3_Handler ; 91,
- DCD GPIO1_4_Handler ; 92,
- DCD GPIO1_5_Handler ; 93,
- DCD GPIO1_6_Handler ; 94,
- DCD GPIO1_7_Handler ; 95,
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- MRS R0, control ; Get control value
- ORR R0, R0, #1 ; Select switch to unprivilage mode
- ORR R0, R0, #2 ; Select switch to PSP
- MSR control, R0
- LDR R0, =__main
- BX R0
- ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-; Core IoT Interrupts
- EXPORT NONSEC_WATCHDOG_RESET_Handler [WEAK] ; - 0 Non-Secure Watchdog Reset Handler
- EXPORT NONSEC_WATCHDOG_Handler [WEAK] ; - 1 Non-Secure Watchdog Handler
- EXPORT S32K_TIMER_Handler [WEAK] ; - 2 S32K Timer Handler
- EXPORT TIMER0_Handler [WEAK] ; - 3 TIMER 0 Handler
- EXPORT TIMER1_Handler [WEAK] ; - 4 TIMER 1 Handler
- EXPORT DUALTIMER_Handler [WEAK] ; - 5 Dual Timer Handler
-; External Interrupts
- EXPORT UARTRX0_Handler [WEAK] ; 32 UART 0 RX Handler
- EXPORT UARTTX0_Handler [WEAK] ; 33 UART 0 TX Handler
- EXPORT UARTRX1_Handler [WEAK] ; 34 UART 1 RX Handler
- EXPORT UARTTX1_Handler [WEAK] ; 35 UART 1 TX Handler
- EXPORT UARTRX2_Handler [WEAK] ; 36 UART 2 RX Handler
- EXPORT UARTTX2_Handler [WEAK] ; 37 UART 2 TX Handler
- EXPORT UARTRX3_Handler [WEAK] ; 38 UART 3 RX Handler
- EXPORT UARTTX3_Handler [WEAK] ; 39 UART 3 TX Handler
- EXPORT UARTRX4_Handler [WEAK] ; 40 UART 4 RX Handler
- EXPORT UARTTX4_Handler [WEAK] ; 41 UART 4 TX Handler
- EXPORT UART0_Handler [WEAK] ; 42 UART 0 combined Handler
- EXPORT UART1_Handler [WEAK] ; 43 UART 1 combined Handler
- EXPORT UART2_Handler [WEAK] ; 44 UART 2 combined Handler
- EXPORT UART3_Handler [WEAK] ; 45 UART 3 combined Handler
- EXPORT UART4_Handler [WEAK] ; 46 UART 4 combined Handler
- EXPORT UARTOVF_Handler [WEAK] ; 47 UART 0,1,2,3,4 Overflow Handler
- EXPORT ETHERNET_Handler [WEAK] ; 48 Ethernet Handler
- EXPORT I2S_Handler [WEAK] ; 49 I2S Handler
- EXPORT TSC_Handler [WEAK] ; 50 Touch Screen Handler
- EXPORT SPI0_Handler [WEAK] ; 51 SPI 0 Handler
- EXPORT SPI1_Handler [WEAK] ; 52 SPI 1 Handler
- EXPORT SPI2_Handler [WEAK] ; 53 SPI 2 Handler
- EXPORT SPI3_Handler [WEAK] ; 54 SPI 3 Handler
- EXPORT SPI4_Handler [WEAK] ; 55 SPI 4 Handler
- EXPORT DMA0_ERROR_Handler [WEAK] ; 56 DMA 0 Error Handler
- EXPORT DMA0_TC_Handler [WEAK] ; 57 DMA 0 Terminal Count Handler
- EXPORT DMA0_Handler [WEAK] ; 58 DMA 0 Combined Handler
- EXPORT DMA1_ERROR_Handler [WEAK] ; 59 DMA 1 Error Handler
- EXPORT DMA1_TC_Handler [WEAK] ; 60 DMA 1 Terminal Count Handler
- EXPORT DMA1_Handler [WEAK] ; 61 DMA 1 Combined Handler
- EXPORT DMA2_ERROR_Handler [WEAK] ; 62 DMA 2 Error Handler
- EXPORT DMA2_TC_Handler [WEAK] ; 63 DMA 2 Terminal Count Handler
- EXPORT DMA2_Handler [WEAK] ; 64 DMA 2 Combined Handler
- EXPORT DMA3_ERROR_Handler [WEAK] ; 65 DMA 3 Error Handler
- EXPORT DMA3_TC_Handler [WEAK] ; 66 DMA 3 Terminal Count Handler
- EXPORT DMA3_Handler [WEAK] ; 67 DMA 3 Combined Handler
- EXPORT GPIO0_Handler [WEAK] ; 68 GPIO 0 Comboned Handler
- EXPORT GPIO1_Handler [WEAK] ; 69 GPIO 1 Comboned Handler
- EXPORT GPIO2_Handler [WEAK] ; 70 GPIO 2 Comboned Handler
- EXPORT GPIO3_Handler [WEAK] ; 71 GPIO 3 Comboned Handler
- EXPORT GPIO0_0_Handler [WEAK] ; 72 GPIO 1 has 16 individual Handlers
- EXPORT GPIO0_1_Handler [WEAK] ; 73
- EXPORT GPIO0_2_Handler [WEAK] ; 74
- EXPORT GPIO0_3_Handler [WEAK] ; 75
- EXPORT GPIO0_4_Handler [WEAK] ; 76
- EXPORT GPIO0_5_Handler [WEAK] ; 77
- EXPORT GPIO0_6_Handler [WEAK] ; 78
- EXPORT GPIO0_7_Handler [WEAK] ; 79
- EXPORT GPIO0_8_Handler [WEAK] ; 80
- EXPORT GPIO0_9_Handler [WEAK] ; 81
- EXPORT GPIO0_10_Handler [WEAK] ; 82
- EXPORT GPIO0_11_Handler [WEAK] ; 83
- EXPORT GPIO0_12_Handler [WEAK] ; 84
- EXPORT GPIO0_13_Handler [WEAK] ; 85
- EXPORT GPIO0_14_Handler [WEAK] ; 86
- EXPORT GPIO0_15_Handler [WEAK] ; 87
- EXPORT GPIO1_0_Handler [WEAK] ; 88 GPIO 1 has 8 individual Handlers
- EXPORT GPIO1_1_Handler [WEAK] ; 89
- EXPORT GPIO1_2_Handler [WEAK] ; 90
- EXPORT GPIO1_3_Handler [WEAK] ; 91
- EXPORT GPIO1_4_Handler [WEAK] ; 92
- EXPORT GPIO1_5_Handler [WEAK] ; 93
- EXPORT GPIO1_6_Handler [WEAK] ; 94
- EXPORT GPIO1_7_Handler [WEAK] ; 95
-
-; Core IoT Interrupts
-NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
-NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
-S32K_TIMER_Handler ; - 2 S32K Timer Handler
-TIMER0_Handler ; - 3 TIMER 0 Handler
-TIMER1_Handler ; - 4 TIMER 1 Handler
-DUALTIMER_Handler ; - 5 Dual Timer Handler
-; External Interrupts
-UARTRX0_Handler ; 32 UART 0 RX Handler
-UARTTX0_Handler ; 33 UART 0 TX Handler
-UARTRX1_Handler ; 34 UART 1 RX Handler
-UARTTX1_Handler ; 35 UART 1 TX Handler
-UARTRX2_Handler ; 36 UART 2 RX Handler
-UARTTX2_Handler ; 37 UART 2 TX Handler
-UARTRX3_Handler ; 38 UART 3 RX Handler
-UARTTX3_Handler ; 39 UART 3 TX Handler
-UARTRX4_Handler ; 40 UART 4 RX Handler
-UARTTX4_Handler ; 41 UART 4 TX Handler
-UART0_Handler ; 42 UART 0 combined Handler
-UART1_Handler ; 43 UART 1 combined Handler
-UART2_Handler ; 44 UART 2 combined Handler
-UART3_Handler ; 45 UART 3 combined Handler
-UART4_Handler ; 46 UART 4 combined Handler
-UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
-ETHERNET_Handler ; 48 Ethernet Handler
-I2S_Handler ; 49 I2S Handler
-TSC_Handler ; 50 Touch Screen Handler
-SPI0_Handler ; 51 SPI 0 Handler
-SPI1_Handler ; 52 SPI 1 Handler
-SPI2_Handler ; 53 SPI 2 Handler
-SPI3_Handler ; 54 SPI 3 Handler
-SPI4_Handler ; 55 SPI 4 Handler
-DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
-DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
-DMA0_Handler ; 58 DMA 0 Combined Handler
-DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
-DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
-DMA1_Handler ; 61 DMA 1 Combined Handler
-DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
-DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
-DMA2_Handler ; 64 DMA 2 Combined Handler
-DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
-DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
-DMA3_Handler ; 67 DMA 3 Combined Handler
-GPIO0_Handler ; 68 GPIO 0 Comboned Handler
-GPIO1_Handler ; 69 GPIO 1 Comboned Handler
-GPIO2_Handler ; 70 GPIO 2 Comboned Handler
-GPIO3_Handler ; 71 GPIO 3 Comboned Handler
-GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
-GPIO0_1_Handler ; 73
-GPIO0_2_Handler ; 74
-GPIO0_3_Handler ; 75
-GPIO0_4_Handler ; 76
-GPIO0_5_Handler ; 77
-GPIO0_6_Handler ; 78
-GPIO0_7_Handler ; 79
-GPIO0_8_Handler ; 80
-GPIO0_9_Handler ; 81
-GPIO0_10_Handler ; 82
-GPIO0_11_Handler ; 83
-GPIO0_12_Handler ; 84
-GPIO0_13_Handler ; 85
-GPIO0_14_Handler ; 86
-GPIO0_15_Handler ; 87
-GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
-GPIO1_1_Handler ; 89
-GPIO1_2_Handler ; 90
-GPIO1_3_Handler ; 91
-GPIO1_4_Handler ; 92
-GPIO1_5_Handler ; 93
-GPIO1_6_Handler ; 94
-GPIO1_7_Handler ; 95
- B .
-
- ENDP
-
- ALIGN
-
- END
+;/*
+; * Copyright (c) 2016-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD 0 ; Reserved - 9
+ DCD 0 ; Reserved - 10
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ MRS R0, control ; Get control value
+ ORR R0, R0, #1 ; Select switch to unprivilage mode
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; Core IoT Interrupts
+ EXPORT NONSEC_WATCHDOG_RESET_Handler [WEAK] ; - 0 Non-Secure Watchdog Reset Handler
+ EXPORT NONSEC_WATCHDOG_Handler [WEAK] ; - 1 Non-Secure Watchdog Handler
+ EXPORT S32K_TIMER_Handler [WEAK] ; - 2 S32K Timer Handler
+ EXPORT TIMER0_Handler [WEAK] ; - 3 TIMER 0 Handler
+ EXPORT TIMER1_Handler [WEAK] ; - 4 TIMER 1 Handler
+ EXPORT DUALTIMER_Handler [WEAK] ; - 5 Dual Timer Handler
+; External Interrupts
+ EXPORT UARTRX0_Handler [WEAK] ; 32 UART 0 RX Handler
+ EXPORT UARTTX0_Handler [WEAK] ; 33 UART 0 TX Handler
+ EXPORT UARTRX1_Handler [WEAK] ; 34 UART 1 RX Handler
+ EXPORT UARTTX1_Handler [WEAK] ; 35 UART 1 TX Handler
+ EXPORT UARTRX2_Handler [WEAK] ; 36 UART 2 RX Handler
+ EXPORT UARTTX2_Handler [WEAK] ; 37 UART 2 TX Handler
+ EXPORT UARTRX3_Handler [WEAK] ; 38 UART 3 RX Handler
+ EXPORT UARTTX3_Handler [WEAK] ; 39 UART 3 TX Handler
+ EXPORT UARTRX4_Handler [WEAK] ; 40 UART 4 RX Handler
+ EXPORT UARTTX4_Handler [WEAK] ; 41 UART 4 TX Handler
+ EXPORT UART0_Handler [WEAK] ; 42 UART 0 combined Handler
+ EXPORT UART1_Handler [WEAK] ; 43 UART 1 combined Handler
+ EXPORT UART2_Handler [WEAK] ; 44 UART 2 combined Handler
+ EXPORT UART3_Handler [WEAK] ; 45 UART 3 combined Handler
+ EXPORT UART4_Handler [WEAK] ; 46 UART 4 combined Handler
+ EXPORT UARTOVF_Handler [WEAK] ; 47 UART 0,1,2,3,4 Overflow Handler
+ EXPORT ETHERNET_Handler [WEAK] ; 48 Ethernet Handler
+ EXPORT I2S_Handler [WEAK] ; 49 I2S Handler
+ EXPORT TSC_Handler [WEAK] ; 50 Touch Screen Handler
+ EXPORT SPI0_Handler [WEAK] ; 51 SPI 0 Handler
+ EXPORT SPI1_Handler [WEAK] ; 52 SPI 1 Handler
+ EXPORT SPI2_Handler [WEAK] ; 53 SPI 2 Handler
+ EXPORT SPI3_Handler [WEAK] ; 54 SPI 3 Handler
+ EXPORT SPI4_Handler [WEAK] ; 55 SPI 4 Handler
+ EXPORT DMA0_ERROR_Handler [WEAK] ; 56 DMA 0 Error Handler
+ EXPORT DMA0_TC_Handler [WEAK] ; 57 DMA 0 Terminal Count Handler
+ EXPORT DMA0_Handler [WEAK] ; 58 DMA 0 Combined Handler
+ EXPORT DMA1_ERROR_Handler [WEAK] ; 59 DMA 1 Error Handler
+ EXPORT DMA1_TC_Handler [WEAK] ; 60 DMA 1 Terminal Count Handler
+ EXPORT DMA1_Handler [WEAK] ; 61 DMA 1 Combined Handler
+ EXPORT DMA2_ERROR_Handler [WEAK] ; 62 DMA 2 Error Handler
+ EXPORT DMA2_TC_Handler [WEAK] ; 63 DMA 2 Terminal Count Handler
+ EXPORT DMA2_Handler [WEAK] ; 64 DMA 2 Combined Handler
+ EXPORT DMA3_ERROR_Handler [WEAK] ; 65 DMA 3 Error Handler
+ EXPORT DMA3_TC_Handler [WEAK] ; 66 DMA 3 Terminal Count Handler
+ EXPORT DMA3_Handler [WEAK] ; 67 DMA 3 Combined Handler
+ EXPORT GPIO0_Handler [WEAK] ; 68 GPIO 0 Comboned Handler
+ EXPORT GPIO1_Handler [WEAK] ; 69 GPIO 1 Comboned Handler
+ EXPORT GPIO2_Handler [WEAK] ; 70 GPIO 2 Comboned Handler
+ EXPORT GPIO3_Handler [WEAK] ; 71 GPIO 3 Comboned Handler
+ EXPORT GPIO0_0_Handler [WEAK] ; 72 GPIO 1 has 16 individual Handlers
+ EXPORT GPIO0_1_Handler [WEAK] ; 73
+ EXPORT GPIO0_2_Handler [WEAK] ; 74
+ EXPORT GPIO0_3_Handler [WEAK] ; 75
+ EXPORT GPIO0_4_Handler [WEAK] ; 76
+ EXPORT GPIO0_5_Handler [WEAK] ; 77
+ EXPORT GPIO0_6_Handler [WEAK] ; 78
+ EXPORT GPIO0_7_Handler [WEAK] ; 79
+ EXPORT GPIO0_8_Handler [WEAK] ; 80
+ EXPORT GPIO0_9_Handler [WEAK] ; 81
+ EXPORT GPIO0_10_Handler [WEAK] ; 82
+ EXPORT GPIO0_11_Handler [WEAK] ; 83
+ EXPORT GPIO0_12_Handler [WEAK] ; 84
+ EXPORT GPIO0_13_Handler [WEAK] ; 85
+ EXPORT GPIO0_14_Handler [WEAK] ; 86
+ EXPORT GPIO0_15_Handler [WEAK] ; 87
+ EXPORT GPIO1_0_Handler [WEAK] ; 88 GPIO 1 has 8 individual Handlers
+ EXPORT GPIO1_1_Handler [WEAK] ; 89
+ EXPORT GPIO1_2_Handler [WEAK] ; 90
+ EXPORT GPIO1_3_Handler [WEAK] ; 91
+ EXPORT GPIO1_4_Handler [WEAK] ; 92
+ EXPORT GPIO1_5_Handler [WEAK] ; 93
+ EXPORT GPIO1_6_Handler [WEAK] ; 94
+ EXPORT GPIO1_7_Handler [WEAK] ; 95
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TIMER0_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ ENDP
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s b/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s
index 1d7ede5..0ee9e00 100644
--- a/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s
+++ b/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s
@@ -1,388 +1,388 @@
-;/*
-; * Copyright (c) 2016-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-;
-; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
- IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD SecureFault_Handler ; Secure Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; Core IoT Interrupts
- DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
- DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
- DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
- DCD TIMER0_Handler ; - 3 TIMER 0 Handler
- DCD TIMER1_Handler ; - 4 TIMER 1 Handler
- DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
- DCD 0 ; Reserved - 6
- DCD 0 ; Reserved - 7
- DCD 0 ; Reserved - 8
- DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
- DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
- DCD 0 ; Reserved - 11
- DCD 0 ; Reserved - 12
- DCD 0 ; Reserved - 13
- DCD 0 ; Reserved - 14
- DCD 0 ; Reserved - 15
- DCD 0 ; Reserved - 16
- DCD 0 ; Reserved - 17
- DCD 0 ; Reserved - 18
- DCD 0 ; Reserved - 19
- DCD 0 ; Reserved - 20
- DCD 0 ; Reserved - 21
- DCD 0 ; Reserved - 22
- DCD 0 ; Reserved - 23
- DCD 0 ; Reserved - 24
- DCD 0 ; Reserved - 25
- DCD 0 ; Reserved - 26
- DCD 0 ; Reserved - 27
- DCD 0 ; Reserved - 28
- DCD 0 ; Reserved - 29
- DCD 0 ; Reserved - 30
- DCD 0 ; Reserved - 31
- ; External Interrupts
- DCD UARTRX0_Handler ; 32 UART 0 RX Handler
- DCD UARTTX0_Handler ; 33 UART 0 TX Handler
- DCD UARTRX1_Handler ; 34 UART 1 RX Handler
- DCD UARTTX1_Handler ; 35 UART 1 TX Handler
- DCD UARTRX2_Handler ; 36 UART 2 RX Handler
- DCD UARTTX2_Handler ; 37 UART 2 TX Handler
- DCD UARTRX3_Handler ; 38 UART 3 RX Handler
- DCD UARTTX3_Handler ; 39 UART 3 TX Handler
- DCD UARTRX4_Handler ; 40 UART 4 RX Handler
- DCD UARTTX4_Handler ; 41 UART 4 TX Handler
- DCD UART0_Handler ; 42 UART 0 combined Handler
- DCD UART1_Handler ; 43 UART 1 combined Handler
- DCD UART2_Handler ; 44 UART 0 combined Handler
- DCD UART3_Handler ; 45 UART 1 combined Handler
- DCD UART4_Handler ; 46 UART 0 combined Handler
- DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
- DCD ETHERNET_Handler ; 48 Ethernet Handler
- DCD I2S_Handler ; 49 I2S Handler
- DCD TSC_Handler ; 50 Touch Screen Handler
- DCD SPI0_Handler ; 51 SPI 0 Handler
- DCD SPI1_Handler ; 52 SPI 1 Handler
- DCD SPI2_Handler ; 53 SPI 2 Handler
- DCD SPI3_Handler ; 54 SPI 3 Handler
- DCD SPI4_Handler ; 55 SPI 4 Handler
- DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
- DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
- DCD DMA0_Handler ; 58 DMA 0 Combined Handler
- DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
- DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
- DCD DMA1_Handler ; 61 DMA 1 Combined Handler
- DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
- DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
- DCD DMA2_Handler ; 64 DMA 2 Combined Handler
- DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
- DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
- DCD DMA3_Handler ; 67 DMA 3 Combined Handler
- DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
- DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
- DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
- DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
- DCD GPIO0_0_Handler ; 72,
- DCD GPIO0_1_Handler ; 73,
- DCD GPIO0_2_Handler ; 74,
- DCD GPIO0_3_Handler ; 75,
- DCD GPIO0_4_Handler ; 76,
- DCD GPIO0_5_Handler ; 77,
- DCD GPIO0_6_Handler ; 78,
- DCD GPIO0_7_Handler ; 79,
- DCD GPIO0_8_Handler ; 80,
- DCD GPIO0_9_Handler ; 81,
- DCD GPIO0_10_Handler ; 82,
- DCD GPIO0_11_Handler ; 83,
- DCD GPIO0_12_Handler ; 84,
- DCD GPIO0_13_Handler ; 85,
- DCD GPIO0_14_Handler ; 86,
- DCD GPIO0_15_Handler ; 87,
- DCD GPIO1_0_Handler ; 88,
- DCD GPIO1_1_Handler ; 89,
- DCD GPIO1_2_Handler ; 90,
- DCD GPIO1_3_Handler ; 91,
- DCD GPIO1_4_Handler ; 92,
- DCD GPIO1_5_Handler ; 93,
- DCD GPIO1_6_Handler ; 94,
- DCD GPIO1_7_Handler ; 95,
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- CPSID i ; Disable IRQs
- LDR R0, =SystemInit
- BLX R0
- MRS R0, control ; Get control value
- ORR R0, R0, #2 ; Select switch to PSP
- MSR control, R0
- LDR R0, =__main
- BX R0
- ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-
-SecureFault_Handler\
- PROC
- EXPORT SecureFault_Handler [WEAK]
- B .
- ENDP
-
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- IMPORT SVCHandler_main
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-MPC_Handler PROC
- EXPORT MPC_Handler [WEAK]
- B .
- ENDP
-PPC_Handler PROC
- EXPORT PPC_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-; Core IoT Interrupts
- EXPORT NONSEC_WATCHDOG_RESET_Handler [WEAK] ; - 0 Non-Secure Watchdog Reset Handler
- EXPORT NONSEC_WATCHDOG_Handler [WEAK] ; - 1 Non-Secure Watchdog Handler
- EXPORT S32K_TIMER_Handler [WEAK] ; - 2 S32K Timer Handler
- EXPORT TIMER0_Handler [WEAK] ; - 3 TIMER 0 Handler
- EXPORT TIMER1_Handler [WEAK] ; - 4 TIMER 1 Handler
- EXPORT DUALTIMER_Handler [WEAK] ; - 5 Dual Timer Handler
-; External Interrupts
- EXPORT UARTRX0_Handler [WEAK] ; 32 UART 0 RX Handler
- EXPORT UARTTX0_Handler [WEAK] ; 33 UART 0 TX Handler
- EXPORT UARTRX1_Handler [WEAK] ; 34 UART 1 RX Handler
- EXPORT UARTTX1_Handler [WEAK] ; 35 UART 1 TX Handler
- EXPORT UARTRX2_Handler [WEAK] ; 36 UART 2 RX Handler
- EXPORT UARTTX2_Handler [WEAK] ; 37 UART 2 TX Handler
- EXPORT UARTRX3_Handler [WEAK] ; 38 UART 3 RX Handler
- EXPORT UARTTX3_Handler [WEAK] ; 39 UART 3 TX Handler
- EXPORT UARTRX4_Handler [WEAK] ; 40 UART 4 RX Handler
- EXPORT UARTTX4_Handler [WEAK] ; 41 UART 4 TX Handler
- EXPORT UART0_Handler [WEAK] ; 42 UART 0 combined Handler
- EXPORT UART1_Handler [WEAK] ; 43 UART 1 combined Handler
- EXPORT UART2_Handler [WEAK] ; 44 UART 2 combined Handler
- EXPORT UART3_Handler [WEAK] ; 45 UART 3 combined Handler
- EXPORT UART4_Handler [WEAK] ; 46 UART 4 combined Handler
- EXPORT UARTOVF_Handler [WEAK] ; 47 UART 0,1,2,3,4 Overflow Handler
- EXPORT ETHERNET_Handler [WEAK] ; 48 Ethernet Handler
- EXPORT I2S_Handler [WEAK] ; 49 I2S Handler
- EXPORT TSC_Handler [WEAK] ; 50 Touch Screen Handler
- EXPORT SPI0_Handler [WEAK] ; 51 SPI 0 Handler
- EXPORT SPI1_Handler [WEAK] ; 52 SPI 1 Handler
- EXPORT SPI2_Handler [WEAK] ; 53 SPI 2 Handler
- EXPORT SPI3_Handler [WEAK] ; 54 SPI 3 Handler
- EXPORT SPI4_Handler [WEAK] ; 55 SPI 4 Handler
- EXPORT DMA0_ERROR_Handler [WEAK] ; 56 DMA 0 Error Handler
- EXPORT DMA0_TC_Handler [WEAK] ; 57 DMA 0 Terminal Count Handler
- EXPORT DMA0_Handler [WEAK] ; 58 DMA 0 Combined Handler
- EXPORT DMA1_ERROR_Handler [WEAK] ; 59 DMA 1 Error Handler
- EXPORT DMA1_TC_Handler [WEAK] ; 60 DMA 1 Terminal Count Handler
- EXPORT DMA1_Handler [WEAK] ; 61 DMA 1 Combined Handler
- EXPORT DMA2_ERROR_Handler [WEAK] ; 62 DMA 2 Error Handler
- EXPORT DMA2_TC_Handler [WEAK] ; 63 DMA 2 Terminal Count Handler
- EXPORT DMA2_Handler [WEAK] ; 64 DMA 2 Combined Handler
- EXPORT DMA3_ERROR_Handler [WEAK] ; 65 DMA 3 Error Handler
- EXPORT DMA3_TC_Handler [WEAK] ; 66 DMA 3 Terminal Count Handler
- EXPORT DMA3_Handler [WEAK] ; 67 DMA 3 Combined Handler
- EXPORT GPIO0_Handler [WEAK] ; 68 GPIO 0 Comboned Handler
- EXPORT GPIO1_Handler [WEAK] ; 69 GPIO 1 Comboned Handler
- EXPORT GPIO2_Handler [WEAK] ; 70 GPIO 2 Comboned Handler
- EXPORT GPIO3_Handler [WEAK] ; 71 GPIO 3 Comboned Handler
- EXPORT GPIO0_0_Handler [WEAK] ; 72 GPIO 1 has 16 individual Handlers
- EXPORT GPIO0_1_Handler [WEAK] ; 73
- EXPORT GPIO0_2_Handler [WEAK] ; 74
- EXPORT GPIO0_3_Handler [WEAK] ; 75
- EXPORT GPIO0_4_Handler [WEAK] ; 76
- EXPORT GPIO0_5_Handler [WEAK] ; 77
- EXPORT GPIO0_6_Handler [WEAK] ; 78
- EXPORT GPIO0_7_Handler [WEAK] ; 79
- EXPORT GPIO0_8_Handler [WEAK] ; 80
- EXPORT GPIO0_9_Handler [WEAK] ; 81
- EXPORT GPIO0_10_Handler [WEAK] ; 82
- EXPORT GPIO0_11_Handler [WEAK] ; 83
- EXPORT GPIO0_12_Handler [WEAK] ; 84
- EXPORT GPIO0_13_Handler [WEAK] ; 85
- EXPORT GPIO0_14_Handler [WEAK] ; 86
- EXPORT GPIO0_15_Handler [WEAK] ; 87
- EXPORT GPIO1_0_Handler [WEAK] ; 88 GPIO 1 has 8 individual Handlers
- EXPORT GPIO1_1_Handler [WEAK] ; 89
- EXPORT GPIO1_2_Handler [WEAK] ; 90
- EXPORT GPIO1_3_Handler [WEAK] ; 91
- EXPORT GPIO1_4_Handler [WEAK] ; 92
- EXPORT GPIO1_5_Handler [WEAK] ; 93
- EXPORT GPIO1_6_Handler [WEAK] ; 94
- EXPORT GPIO1_7_Handler [WEAK] ; 95
-
-; Core IoT Interrupts
-NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
-NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
-S32K_TIMER_Handler ; - 2 S32K Timer Handler
-TIMER0_Handler ; - 3 TIMER 0 Handler
-TIMER1_Handler ; - 4 TIMER 1 Handler
-DUALTIMER_Handler ; - 5 Dual Timer Handler
-; External Interrupts
-UARTRX0_Handler ; 32 UART 0 RX Handler
-UARTTX0_Handler ; 33 UART 0 TX Handler
-UARTRX1_Handler ; 34 UART 1 RX Handler
-UARTTX1_Handler ; 35 UART 1 TX Handler
-UARTRX2_Handler ; 36 UART 2 RX Handler
-UARTTX2_Handler ; 37 UART 2 TX Handler
-UARTRX3_Handler ; 38 UART 3 RX Handler
-UARTTX3_Handler ; 39 UART 3 TX Handler
-UARTRX4_Handler ; 40 UART 4 RX Handler
-UARTTX4_Handler ; 41 UART 4 TX Handler
-UART0_Handler ; 42 UART 0 combined Handler
-UART1_Handler ; 43 UART 1 combined Handler
-UART2_Handler ; 44 UART 2 combined Handler
-UART3_Handler ; 45 UART 3 combined Handler
-UART4_Handler ; 46 UART 4 combined Handler
-UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
-ETHERNET_Handler ; 48 Ethernet Handler
-I2S_Handler ; 49 I2S Handler
-TSC_Handler ; 50 Touch Screen Handler
-SPI0_Handler ; 51 SPI 0 Handler
-SPI1_Handler ; 52 SPI 1 Handler
-SPI2_Handler ; 53 SPI 2 Handler
-SPI3_Handler ; 54 SPI 3 Handler
-SPI4_Handler ; 55 SPI 4 Handler
-DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
-DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
-DMA0_Handler ; 58 DMA 0 Combined Handler
-DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
-DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
-DMA1_Handler ; 61 DMA 1 Combined Handler
-DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
-DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
-DMA2_Handler ; 64 DMA 2 Combined Handler
-DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
-DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
-DMA3_Handler ; 67 DMA 3 Combined Handler
-GPIO0_Handler ; 68 GPIO 0 Comboned Handler
-GPIO1_Handler ; 69 GPIO 1 Comboned Handler
-GPIO2_Handler ; 70 GPIO 2 Comboned Handler
-GPIO3_Handler ; 71 GPIO 3 Comboned Handler
-GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
-GPIO0_1_Handler ; 73
-GPIO0_2_Handler ; 74
-GPIO0_3_Handler ; 75
-GPIO0_4_Handler ; 76
-GPIO0_5_Handler ; 77
-GPIO0_6_Handler ; 78
-GPIO0_7_Handler ; 79
-GPIO0_8_Handler ; 80
-GPIO0_9_Handler ; 81
-GPIO0_10_Handler ; 82
-GPIO0_11_Handler ; 83
-GPIO0_12_Handler ; 84
-GPIO0_13_Handler ; 85
-GPIO0_14_Handler ; 86
-GPIO0_15_Handler ; 87
-GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
-GPIO1_1_Handler ; 89
-GPIO1_2_Handler ; 90
-GPIO1_3_Handler ; 91
-GPIO1_4_Handler ; 92
-GPIO1_5_Handler ; 93
-GPIO1_6_Handler ; 94
-GPIO1_7_Handler ; 95
- B .
-
- ENDP
-
- ALIGN
-
- END
+;/*
+; * Copyright (c) 2016-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ CPSID i ; Disable IRQs
+ LDR R0, =SystemInit
+ BLX R0
+ MRS R0, control ; Get control value
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+
+SecureFault_Handler\
+ PROC
+ EXPORT SecureFault_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ IMPORT SVCHandler_main
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+MPC_Handler PROC
+ EXPORT MPC_Handler [WEAK]
+ B .
+ ENDP
+PPC_Handler PROC
+ EXPORT PPC_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; Core IoT Interrupts
+ EXPORT NONSEC_WATCHDOG_RESET_Handler [WEAK] ; - 0 Non-Secure Watchdog Reset Handler
+ EXPORT NONSEC_WATCHDOG_Handler [WEAK] ; - 1 Non-Secure Watchdog Handler
+ EXPORT S32K_TIMER_Handler [WEAK] ; - 2 S32K Timer Handler
+ EXPORT TIMER0_Handler [WEAK] ; - 3 TIMER 0 Handler
+ EXPORT TIMER1_Handler [WEAK] ; - 4 TIMER 1 Handler
+ EXPORT DUALTIMER_Handler [WEAK] ; - 5 Dual Timer Handler
+; External Interrupts
+ EXPORT UARTRX0_Handler [WEAK] ; 32 UART 0 RX Handler
+ EXPORT UARTTX0_Handler [WEAK] ; 33 UART 0 TX Handler
+ EXPORT UARTRX1_Handler [WEAK] ; 34 UART 1 RX Handler
+ EXPORT UARTTX1_Handler [WEAK] ; 35 UART 1 TX Handler
+ EXPORT UARTRX2_Handler [WEAK] ; 36 UART 2 RX Handler
+ EXPORT UARTTX2_Handler [WEAK] ; 37 UART 2 TX Handler
+ EXPORT UARTRX3_Handler [WEAK] ; 38 UART 3 RX Handler
+ EXPORT UARTTX3_Handler [WEAK] ; 39 UART 3 TX Handler
+ EXPORT UARTRX4_Handler [WEAK] ; 40 UART 4 RX Handler
+ EXPORT UARTTX4_Handler [WEAK] ; 41 UART 4 TX Handler
+ EXPORT UART0_Handler [WEAK] ; 42 UART 0 combined Handler
+ EXPORT UART1_Handler [WEAK] ; 43 UART 1 combined Handler
+ EXPORT UART2_Handler [WEAK] ; 44 UART 2 combined Handler
+ EXPORT UART3_Handler [WEAK] ; 45 UART 3 combined Handler
+ EXPORT UART4_Handler [WEAK] ; 46 UART 4 combined Handler
+ EXPORT UARTOVF_Handler [WEAK] ; 47 UART 0,1,2,3,4 Overflow Handler
+ EXPORT ETHERNET_Handler [WEAK] ; 48 Ethernet Handler
+ EXPORT I2S_Handler [WEAK] ; 49 I2S Handler
+ EXPORT TSC_Handler [WEAK] ; 50 Touch Screen Handler
+ EXPORT SPI0_Handler [WEAK] ; 51 SPI 0 Handler
+ EXPORT SPI1_Handler [WEAK] ; 52 SPI 1 Handler
+ EXPORT SPI2_Handler [WEAK] ; 53 SPI 2 Handler
+ EXPORT SPI3_Handler [WEAK] ; 54 SPI 3 Handler
+ EXPORT SPI4_Handler [WEAK] ; 55 SPI 4 Handler
+ EXPORT DMA0_ERROR_Handler [WEAK] ; 56 DMA 0 Error Handler
+ EXPORT DMA0_TC_Handler [WEAK] ; 57 DMA 0 Terminal Count Handler
+ EXPORT DMA0_Handler [WEAK] ; 58 DMA 0 Combined Handler
+ EXPORT DMA1_ERROR_Handler [WEAK] ; 59 DMA 1 Error Handler
+ EXPORT DMA1_TC_Handler [WEAK] ; 60 DMA 1 Terminal Count Handler
+ EXPORT DMA1_Handler [WEAK] ; 61 DMA 1 Combined Handler
+ EXPORT DMA2_ERROR_Handler [WEAK] ; 62 DMA 2 Error Handler
+ EXPORT DMA2_TC_Handler [WEAK] ; 63 DMA 2 Terminal Count Handler
+ EXPORT DMA2_Handler [WEAK] ; 64 DMA 2 Combined Handler
+ EXPORT DMA3_ERROR_Handler [WEAK] ; 65 DMA 3 Error Handler
+ EXPORT DMA3_TC_Handler [WEAK] ; 66 DMA 3 Terminal Count Handler
+ EXPORT DMA3_Handler [WEAK] ; 67 DMA 3 Combined Handler
+ EXPORT GPIO0_Handler [WEAK] ; 68 GPIO 0 Comboned Handler
+ EXPORT GPIO1_Handler [WEAK] ; 69 GPIO 1 Comboned Handler
+ EXPORT GPIO2_Handler [WEAK] ; 70 GPIO 2 Comboned Handler
+ EXPORT GPIO3_Handler [WEAK] ; 71 GPIO 3 Comboned Handler
+ EXPORT GPIO0_0_Handler [WEAK] ; 72 GPIO 1 has 16 individual Handlers
+ EXPORT GPIO0_1_Handler [WEAK] ; 73
+ EXPORT GPIO0_2_Handler [WEAK] ; 74
+ EXPORT GPIO0_3_Handler [WEAK] ; 75
+ EXPORT GPIO0_4_Handler [WEAK] ; 76
+ EXPORT GPIO0_5_Handler [WEAK] ; 77
+ EXPORT GPIO0_6_Handler [WEAK] ; 78
+ EXPORT GPIO0_7_Handler [WEAK] ; 79
+ EXPORT GPIO0_8_Handler [WEAK] ; 80
+ EXPORT GPIO0_9_Handler [WEAK] ; 81
+ EXPORT GPIO0_10_Handler [WEAK] ; 82
+ EXPORT GPIO0_11_Handler [WEAK] ; 83
+ EXPORT GPIO0_12_Handler [WEAK] ; 84
+ EXPORT GPIO0_13_Handler [WEAK] ; 85
+ EXPORT GPIO0_14_Handler [WEAK] ; 86
+ EXPORT GPIO0_15_Handler [WEAK] ; 87
+ EXPORT GPIO1_0_Handler [WEAK] ; 88 GPIO 1 has 8 individual Handlers
+ EXPORT GPIO1_1_Handler [WEAK] ; 89
+ EXPORT GPIO1_2_Handler [WEAK] ; 90
+ EXPORT GPIO1_3_Handler [WEAK] ; 91
+ EXPORT GPIO1_4_Handler [WEAK] ; 92
+ EXPORT GPIO1_5_Handler [WEAK] ; 93
+ EXPORT GPIO1_6_Handler [WEAK] ; 94
+ EXPORT GPIO1_7_Handler [WEAK] ; 95
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TIMER0_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ ENDP
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_bl2.S b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_bl2.S
index 0374bee..f31522a 100644
--- a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_bl2.S
+++ b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_bl2.S
@@ -1,402 +1,402 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.main
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
-
- /* Core interrupts */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* External interrupts */
- .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
- .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
- .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
- .long TIMER0_Handler /* 3: TIMER 0 Handler */
- .long TIMER1_Handler /* 4: TIMER 1 Handler */
- .long DUALTIMER_Handler /* 5: Dual Timer Handler */
- .long MHU0_Handler /* 6: Message Handling Unit 0 */
- .long MHU1_Handler /* 7: Message Handling Unit 1 */
- .long 0 /* 8: Reserved */
- .long MPC_Handler /* 9: MPC Combined (Secure) Handler */
- .long PPC_Handler /* 10: PPC Combined (Secure) Handler */
- .long MSC_Handler /* 11: MSC Combined (Secure) Handler */
- .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */
- .long INVALID_INSTR_CACHE_Handler /* 13: CPU Instruction Cache Invalidation Handler */
- .long 0 /* 14: Reserved */
- .long SYS_PPU_Handler /* 15: SYS PPU Handler */
- .long CPU0_PPU_Handler /* 16: CPU0 PPU Handler */
- .long CPU1_PPU_Handler /* 17: CPU1 PPU Handler */
- .long CPU0_DBG_PPU_Handler /* 18: CPU0 DBG PPU_Handler */
- .long CPU1_DBG_PPU_Handler /* 19: CPU1 DBG PPU_Handler */
- .long CRYPT_PPU_Handler /* 20: CRYPT PPU Handler */
- .long 0 /* 21: Reserved */
- .long RAM0_PPU_Handler /* 22: RAM0 PPU Handler */
- .long RAM1_PPU_Handler /* 23: RAM1 PPU Handler */
- .long RAM2_PPU_Handler /* 24: RAM2 PPU Handler */
- .long RAM3_PPU_Handler /* 25: RAM3 PPU Handler */
- .long DBG_PPU_Handler /* 26: DBG PPU Handler */
- .long 0 /* 27: Reserved */
- .long CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
- .long CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
- .long 0 /* 30: Reserved */
- .long 0 /* 31: Reserved */
- .long UARTRX0_Handler /* 32: UART 0 RX Handler */
- .long UARTTX0_Handler /* 33: UART 0 TX Handler */
- .long UARTRX1_Handler /* 34: UART 1 RX Handler */
- .long UARTTX1_Handler /* 35: UART 1 TX Handler */
- .long UARTRX2_Handler /* 36: UART 2 RX Handler */
- .long UARTTX2_Handler /* 37: UART 2 TX Handler */
- .long UARTRX3_Handler /* 38: UART 3 RX Handler */
- .long UARTTX3_Handler /* 39: UART 3 TX Handler */
- .long UARTRX4_Handler /* 40: UART 4 RX Handler */
- .long UARTTX4_Handler /* 41: UART 4 TX Handler */
- .long UART0_Handler /* 42: UART 0 combined Handler */
- .long UART1_Handler /* 43: UART 1 combined Handler */
- .long UART2_Handler /* 44: UART 2 combined Handler */
- .long UART3_Handler /* 45: UART 3 combined Handler */
- .long UART4_Handler /* 46: UART 4 combined Handler */
- .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
- .long ETHERNET_Handler /* 48: Ethernet Handler */
- .long I2S_Handler /* 49: I2S Handler */
- .long TSC_Handler /* 50: Touch Screen Handler */
- .long SPI0_Handler /* 51: SPI 0 Handler */
- .long SPI1_Handler /* 52: SPI 1 Handler */
- .long SPI2_Handler /* 53: SPI 2 Handler */
- .long SPI3_Handler /* 54: SPI 3 Handler */
- .long SPI4_Handler /* 55: SPI 4 Handler */
- .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
- .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
- .long DMA0_Handler /* 58: DMA 0 Combined Handler */
- .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
- .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
- .long DMA1_Handler /* 61: DMA 1 Combined Handler */
- .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
- .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
- .long DMA2_Handler /* 64: DMA 2 Combined Handler */
- .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
- .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
- .long DMA3_Handler /* 67: DMA 3 Combined Handler */
- .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
- .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
- .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
- .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
- .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
- .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
- .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
- .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
- .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
- .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
- .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
- .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
- .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
- .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
- .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
- .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
- .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
- .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
- .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
- .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
- .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
- .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
- .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
- .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
- .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
- .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
- .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
- .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
- /* Only run on core 0 */
- mov r0, #0x50000000
- add r0, #0x0001F000
- ldr r0, [r0]
- cmp r0,#0
-not_the_core_to_run_on:
- bne not_the_core_to_run_on
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
-
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- bl SystemInit
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- /* Core interrupts */
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
-
- /* External interrupts */
- def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
- def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
- def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
- def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
- def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
- def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
- def_irq_handler MHU0_Handler /* 6: Message Handling Unit 0 */
- def_irq_handler MHU1_Handler /* 7: Message Handling Unit 1 */
- def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */
- def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */
- def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */
- def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */
- def_irq_handler INVALID_INSTR_CACHE_Handler /* 13 CPU Instruction Cache Invalidation Handler */
- def_irq_handler SYS_PPU_Handler /* 15 SYS PPU Handler */
- def_irq_handler CPU0_PPU_Handler /* 16 CPU0 PPU Handler */
- def_irq_handler CPU1_PPU_Handler /* 17 CPU1 PPU Handler */
- def_irq_handler CPU0_DBG_PPU_Handler /* 18 CPU0 DBG PPU_Handler */
- def_irq_handler CPU1_DBG_PPU_Handler /* 19 CPU1 DBG PPU_Handler */
- def_irq_handler CRYPT_PPU_Handler /* 20 CRYPT PPU Handler */
- def_irq_handler RAM0_PPU_Handler /* 22 RAM0 PPU Handler */
- def_irq_handler RAM1_PPU_Handler /* 23 RAM1 PPU Handler */
- def_irq_handler RAM2_PPU_Handler /* 24 RAM2 PPU Handler */
- def_irq_handler RAM3_PPU_Handler /* 25 RAM3 PPU Handler */
- def_irq_handler DBG_PPU_Handler /* 26 DBG PPU Handler */
- def_irq_handler CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
- def_irq_handler CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
- def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
- def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
- def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
- def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
- def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
- def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
- def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
- def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
- def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
- def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
- def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
- def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
- def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
- def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
- def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
- def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
- def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
- def_irq_handler I2S_Handler /* 49: I2S Handler */
- def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
- def_irq_handler SPI0_Handler /* 51: SPI 0 Handler */
- def_irq_handler SPI1_Handler /* 52: SPI 1 Handler */
- def_irq_handler SPI2_Handler /* 53: SPI 2 Handler */
- def_irq_handler SPI3_Handler /* 54: SPI 3 Handler */
- def_irq_handler SPI4_Handler /* 55: SPI 4 Handler */
- def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
- def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
- def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */
- def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
- def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
- def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */
- def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
- def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
- def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */
- def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
- def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
- def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */
- def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
- def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
- def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
- def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
- def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
- def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
- def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
- def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
- def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
- def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
- def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
- def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
- def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
- def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
- def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
- def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
- def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
- def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
- def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
- def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
- def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
- def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
- def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
- def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
- def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
- def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
- def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
- def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
-
- .end
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
+; */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+
+ /* Core interrupts */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long SecureFault_Handler /* Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ .long TIMER0_Handler /* 3: TIMER 0 Handler */
+ .long TIMER1_Handler /* 4: TIMER 1 Handler */
+ .long DUALTIMER_Handler /* 5: Dual Timer Handler */
+ .long MHU0_Handler /* 6: Message Handling Unit 0 */
+ .long MHU1_Handler /* 7: Message Handling Unit 1 */
+ .long 0 /* 8: Reserved */
+ .long MPC_Handler /* 9: MPC Combined (Secure) Handler */
+ .long PPC_Handler /* 10: PPC Combined (Secure) Handler */
+ .long MSC_Handler /* 11: MSC Combined (Secure) Handler */
+ .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */
+ .long INVALID_INSTR_CACHE_Handler /* 13: CPU Instruction Cache Invalidation Handler */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_Handler /* 15: SYS PPU Handler */
+ .long CPU0_PPU_Handler /* 16: CPU0 PPU Handler */
+ .long CPU1_PPU_Handler /* 17: CPU1 PPU Handler */
+ .long CPU0_DBG_PPU_Handler /* 18: CPU0 DBG PPU_Handler */
+ .long CPU1_DBG_PPU_Handler /* 19: CPU1 DBG PPU_Handler */
+ .long CRYPT_PPU_Handler /* 20: CRYPT PPU Handler */
+ .long 0 /* 21: Reserved */
+ .long RAM0_PPU_Handler /* 22: RAM0 PPU Handler */
+ .long RAM1_PPU_Handler /* 23: RAM1 PPU Handler */
+ .long RAM2_PPU_Handler /* 24: RAM2 PPU Handler */
+ .long RAM3_PPU_Handler /* 25: RAM3 PPU Handler */
+ .long DBG_PPU_Handler /* 26: DBG PPU Handler */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
+ .long CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+ .long UARTRX0_Handler /* 32: UART 0 RX Handler */
+ .long UARTTX0_Handler /* 33: UART 0 TX Handler */
+ .long UARTRX1_Handler /* 34: UART 1 RX Handler */
+ .long UARTTX1_Handler /* 35: UART 1 TX Handler */
+ .long UARTRX2_Handler /* 36: UART 2 RX Handler */
+ .long UARTTX2_Handler /* 37: UART 2 TX Handler */
+ .long UARTRX3_Handler /* 38: UART 3 RX Handler */
+ .long UARTTX3_Handler /* 39: UART 3 TX Handler */
+ .long UARTRX4_Handler /* 40: UART 4 RX Handler */
+ .long UARTTX4_Handler /* 41: UART 4 TX Handler */
+ .long UART0_Handler /* 42: UART 0 combined Handler */
+ .long UART1_Handler /* 43: UART 1 combined Handler */
+ .long UART2_Handler /* 44: UART 2 combined Handler */
+ .long UART3_Handler /* 45: UART 3 combined Handler */
+ .long UART4_Handler /* 46: UART 4 combined Handler */
+ .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ .long ETHERNET_Handler /* 48: Ethernet Handler */
+ .long I2S_Handler /* 49: I2S Handler */
+ .long TSC_Handler /* 50: Touch Screen Handler */
+ .long SPI0_Handler /* 51: SPI 0 Handler */
+ .long SPI1_Handler /* 52: SPI 1 Handler */
+ .long SPI2_Handler /* 53: SPI 2 Handler */
+ .long SPI3_Handler /* 54: SPI 3 Handler */
+ .long SPI4_Handler /* 55: SPI 4 Handler */
+ .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
+ .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
+ .long DMA0_Handler /* 58: DMA 0 Combined Handler */
+ .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
+ .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
+ .long DMA1_Handler /* 61: DMA 1 Combined Handler */
+ .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
+ .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
+ .long DMA2_Handler /* 64: DMA 2 Combined Handler */
+ .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
+ .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
+ .long DMA3_Handler /* 67: DMA 3 Combined Handler */
+ .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+ /* Only run on core 0 */
+ mov r0, #0x50000000
+ add r0, #0x0001F000
+ ldr r0, [r0]
+ cmp r0,#0
+not_the_core_to_run_on:
+ bne not_the_core_to_run_on
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ bl SystemInit
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ /* Core interrupts */
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SecureFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* External interrupts */
+ def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
+ def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
+ def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
+ def_irq_handler MHU0_Handler /* 6: Message Handling Unit 0 */
+ def_irq_handler MHU1_Handler /* 7: Message Handling Unit 1 */
+ def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */
+ def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */
+ def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */
+ def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */
+ def_irq_handler INVALID_INSTR_CACHE_Handler /* 13 CPU Instruction Cache Invalidation Handler */
+ def_irq_handler SYS_PPU_Handler /* 15 SYS PPU Handler */
+ def_irq_handler CPU0_PPU_Handler /* 16 CPU0 PPU Handler */
+ def_irq_handler CPU1_PPU_Handler /* 17 CPU1 PPU Handler */
+ def_irq_handler CPU0_DBG_PPU_Handler /* 18 CPU0 DBG PPU_Handler */
+ def_irq_handler CPU1_DBG_PPU_Handler /* 19 CPU1 DBG PPU_Handler */
+ def_irq_handler CRYPT_PPU_Handler /* 20 CRYPT PPU Handler */
+ def_irq_handler RAM0_PPU_Handler /* 22 RAM0 PPU Handler */
+ def_irq_handler RAM1_PPU_Handler /* 23 RAM1 PPU Handler */
+ def_irq_handler RAM2_PPU_Handler /* 24 RAM2 PPU Handler */
+ def_irq_handler RAM3_PPU_Handler /* 25 RAM3 PPU Handler */
+ def_irq_handler DBG_PPU_Handler /* 26 DBG PPU Handler */
+ def_irq_handler CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
+ def_irq_handler CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
+ def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
+ def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
+ def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
+ def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
+ def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
+ def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
+ def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
+ def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
+ def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
+ def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
+ def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
+ def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
+ def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
+ def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
+ def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
+ def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
+ def_irq_handler I2S_Handler /* 49: I2S Handler */
+ def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
+ def_irq_handler SPI0_Handler /* 51: SPI 0 Handler */
+ def_irq_handler SPI1_Handler /* 52: SPI 1 Handler */
+ def_irq_handler SPI2_Handler /* 53: SPI 2 Handler */
+ def_irq_handler SPI3_Handler /* 54: SPI 3 Handler */
+ def_irq_handler SPI4_Handler /* 55: SPI 4 Handler */
+ def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
+ def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
+ def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */
+ def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
+ def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
+ def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */
+ def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
+ def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
+ def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */
+ def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
+ def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
+ def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */
+ def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+
+ .end
diff --git a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_ns.S b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_ns.S
index aa13bc1..ddf590d 100644
--- a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_ns.S
+++ b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_ns.S
@@ -1,396 +1,396 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.main
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
-
- /* Core interrupts */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* External interrupts */
- .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
- .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
- .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
- .long TIMER0_Handler /* 3: TIMER 0 Handler */
- .long TIMER1_Handler /* 4: TIMER 1 Handler */
- .long DUALTIMER_Handler /* 5: Dual Timer Handler */
- .long MHU0_Handler /* 6: Message Handling Unit 0 */
- .long MHU1_Handler /* 7: Message Handling Unit 1 */
- .long 0 /* 8: Reserved */
- .long 0 /* 9: Reserved */
- .long 0 /* 10: Reserved */
- .long MSC_Handler /* 11: MSC Combined (Secure) Handler */
- .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */
- .long INVALID_INSTR_CACHE_Handler /* 13: CPU Instruction Cache Invalidation Handler */
- .long 0 /* 14: Reserved */
- .long SYS_PPU_Handler /* 15: SYS PPU Handler */
- .long CPU0_PPU_Handler /* 16: CPU0 PPU Handler */
- .long CPU1_PPU_Handler /* 17: CPU1 PPU Handler */
- .long CPU0_DBG_PPU_Handler /* 18: CPU0 DBG PPU_Handler */
- .long CPU1_DBG_PPU_Handler /* 19: CPU1 DBG PPU_Handler */
- .long CRYPT_PPU_Handler /* 20: CRYPT PPU Handler */
- .long 0 /* 21: Reserved */
- .long RAM0_PPU_Handler /* 22: RAM0 PPU Handler */
- .long RAM1_PPU_Handler /* 23: RAM1 PPU Handler */
- .long RAM2_PPU_Handler /* 24: RAM2 PPU Handler */
- .long RAM3_PPU_Handler /* 25: RAM3 PPU Handler */
- .long DBG_PPU_Handler /* 26: DBG PPU Handler */
- .long 0 /* 27: Reserved */
- .long CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
- .long CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
- .long 0 /* 30: Reserved */
- .long 0 /* 31: Reserved */
- .long UARTRX0_Handler /* 32: UART 0 RX Handler */
- .long UARTTX0_Handler /* 33: UART 0 TX Handler */
- .long UARTRX1_Handler /* 34: UART 1 RX Handler */
- .long UARTTX1_Handler /* 35: UART 1 TX Handler */
- .long UARTRX2_Handler /* 36: UART 2 RX Handler */
- .long UARTTX2_Handler /* 37: UART 2 TX Handler */
- .long UARTRX3_Handler /* 38: UART 3 RX Handler */
- .long UARTTX3_Handler /* 39: UART 3 TX Handler */
- .long UARTRX4_Handler /* 40: UART 4 RX Handler */
- .long UARTTX4_Handler /* 41: UART 4 TX Handler */
- .long UART0_Handler /* 42: UART 0 combined Handler */
- .long UART1_Handler /* 43: UART 1 combined Handler */
- .long UART2_Handler /* 44: UART 2 combined Handler */
- .long UART3_Handler /* 45: UART 3 combined Handler */
- .long UART4_Handler /* 46: UART 4 combined Handler */
- .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
- .long ETHERNET_Handler /* 48: Ethernet Handler */
- .long I2S_Handler /* 49: I2S Handler */
- .long TSC_Handler /* 50: Touch Screen Handler */
- .long SPI0_Handler /* 51: SPI 0 Handler */
- .long SPI1_Handler /* 52: SPI 1 Handler */
- .long SPI2_Handler /* 53: SPI 2 Handler */
- .long SPI3_Handler /* 54: SPI 3 Handler */
- .long SPI4_Handler /* 55: SPI 4 Handler */
- .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
- .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
- .long DMA0_Handler /* 58: DMA 0 Combined Handler */
- .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
- .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
- .long DMA1_Handler /* 61: DMA 1 Combined Handler */
- .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
- .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
- .long DMA2_Handler /* 64: DMA 2 Combined Handler */
- .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
- .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
- .long DMA3_Handler /* 67: DMA 3 Combined Handler */
- .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
- .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
- .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
- .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
- .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
- .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
- .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
- .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
- .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
- .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
- .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
- .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
- .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
- .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
- .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
- .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
- .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
- .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
- .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
- .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
- .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
- .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
- .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
- .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
- .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
- .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
- .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
- .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
-
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- mrs r0, control /* Get control value */
- orr r0, r0, #1 /* Select switch to unprivilage mode */
- orr r0, r0, #2 /* Select switch to PSP */
- msr control, r0
- ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
- msr psp, r0
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- /* Core interrupts */
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
-
- /* External interrupts */
- def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
- def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
- def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
- def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
- def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
- def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
- def_irq_handler MHU0_Handler /* 6: Message Handling Unit 0 */
- def_irq_handler MHU1_Handler /* 7: Message Handling Unit 1 */
- def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */
- def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */
- def_irq_handler INVALID_INSTR_CACHE_Handler /* 13 CPU Instruction Cache Invalidation Handler */
- def_irq_handler SYS_PPU_Handler /* 15 SYS PPU Handler */
- def_irq_handler CPU0_PPU_Handler /* 16 CPU0 PPU Handler */
- def_irq_handler CPU1_PPU_Handler /* 17 CPU1 PPU Handler */
- def_irq_handler CPU0_DBG_PPU_Handler /* 18 CPU0 DBG PPU_Handler */
- def_irq_handler CPU1_DBG_PPU_Handler /* 19 CPU1 DBG PPU_Handler */
- def_irq_handler CRYPT_PPU_Handler /* 20 CRYPT PPU Handler */
- def_irq_handler RAM0_PPU_Handler /* 22 RAM0 PPU Handler */
- def_irq_handler RAM1_PPU_Handler /* 23 RAM1 PPU Handler */
- def_irq_handler RAM2_PPU_Handler /* 24 RAM2 PPU Handler */
- def_irq_handler RAM3_PPU_Handler /* 25 RAM3 PPU Handler */
- def_irq_handler DBG_PPU_Handler /* 26 DBG PPU Handler */
- def_irq_handler CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
- def_irq_handler CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
- def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
- def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
- def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
- def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
- def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
- def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
- def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
- def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
- def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
- def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
- def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
- def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
- def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
- def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
- def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
- def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
- def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
- def_irq_handler I2S_Handler /* 49: I2S Handler */
- def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
- def_irq_handler SPI0_Handler /* 51: SPI 0 Handler */
- def_irq_handler SPI1_Handler /* 52: SPI 1 Handler */
- def_irq_handler SPI2_Handler /* 53: SPI 2 Handler */
- def_irq_handler SPI3_Handler /* 54: SPI 3 Handler */
- def_irq_handler SPI4_Handler /* 55: SPI 4 Handler */
- def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
- def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
- def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */
- def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
- def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
- def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */
- def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
- def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
- def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */
- def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
- def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
- def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */
- def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
- def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
- def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
- def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
- def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
- def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
- def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
- def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
- def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
- def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
- def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
- def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
- def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
- def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
- def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
- def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
- def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
- def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
- def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
- def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
- def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
- def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
- def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
- def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
- def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
- def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
- def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
- def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
-
- .end
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
+; */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+
+ /* Core interrupts */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ .long TIMER0_Handler /* 3: TIMER 0 Handler */
+ .long TIMER1_Handler /* 4: TIMER 1 Handler */
+ .long DUALTIMER_Handler /* 5: Dual Timer Handler */
+ .long MHU0_Handler /* 6: Message Handling Unit 0 */
+ .long MHU1_Handler /* 7: Message Handling Unit 1 */
+ .long 0 /* 8: Reserved */
+ .long 0 /* 9: Reserved */
+ .long 0 /* 10: Reserved */
+ .long MSC_Handler /* 11: MSC Combined (Secure) Handler */
+ .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */
+ .long INVALID_INSTR_CACHE_Handler /* 13: CPU Instruction Cache Invalidation Handler */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_Handler /* 15: SYS PPU Handler */
+ .long CPU0_PPU_Handler /* 16: CPU0 PPU Handler */
+ .long CPU1_PPU_Handler /* 17: CPU1 PPU Handler */
+ .long CPU0_DBG_PPU_Handler /* 18: CPU0 DBG PPU_Handler */
+ .long CPU1_DBG_PPU_Handler /* 19: CPU1 DBG PPU_Handler */
+ .long CRYPT_PPU_Handler /* 20: CRYPT PPU Handler */
+ .long 0 /* 21: Reserved */
+ .long RAM0_PPU_Handler /* 22: RAM0 PPU Handler */
+ .long RAM1_PPU_Handler /* 23: RAM1 PPU Handler */
+ .long RAM2_PPU_Handler /* 24: RAM2 PPU Handler */
+ .long RAM3_PPU_Handler /* 25: RAM3 PPU Handler */
+ .long DBG_PPU_Handler /* 26: DBG PPU Handler */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
+ .long CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+ .long UARTRX0_Handler /* 32: UART 0 RX Handler */
+ .long UARTTX0_Handler /* 33: UART 0 TX Handler */
+ .long UARTRX1_Handler /* 34: UART 1 RX Handler */
+ .long UARTTX1_Handler /* 35: UART 1 TX Handler */
+ .long UARTRX2_Handler /* 36: UART 2 RX Handler */
+ .long UARTTX2_Handler /* 37: UART 2 TX Handler */
+ .long UARTRX3_Handler /* 38: UART 3 RX Handler */
+ .long UARTTX3_Handler /* 39: UART 3 TX Handler */
+ .long UARTRX4_Handler /* 40: UART 4 RX Handler */
+ .long UARTTX4_Handler /* 41: UART 4 TX Handler */
+ .long UART0_Handler /* 42: UART 0 combined Handler */
+ .long UART1_Handler /* 43: UART 1 combined Handler */
+ .long UART2_Handler /* 44: UART 2 combined Handler */
+ .long UART3_Handler /* 45: UART 3 combined Handler */
+ .long UART4_Handler /* 46: UART 4 combined Handler */
+ .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ .long ETHERNET_Handler /* 48: Ethernet Handler */
+ .long I2S_Handler /* 49: I2S Handler */
+ .long TSC_Handler /* 50: Touch Screen Handler */
+ .long SPI0_Handler /* 51: SPI 0 Handler */
+ .long SPI1_Handler /* 52: SPI 1 Handler */
+ .long SPI2_Handler /* 53: SPI 2 Handler */
+ .long SPI3_Handler /* 54: SPI 3 Handler */
+ .long SPI4_Handler /* 55: SPI 4 Handler */
+ .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
+ .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
+ .long DMA0_Handler /* 58: DMA 0 Combined Handler */
+ .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
+ .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
+ .long DMA1_Handler /* 61: DMA 1 Combined Handler */
+ .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
+ .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
+ .long DMA2_Handler /* 64: DMA 2 Combined Handler */
+ .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
+ .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
+ .long DMA3_Handler /* 67: DMA 3 Combined Handler */
+ .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ mrs r0, control /* Get control value */
+ orr r0, r0, #1 /* Select switch to unprivilage mode */
+ orr r0, r0, #2 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+ msr psp, r0
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ /* Core interrupts */
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* External interrupts */
+ def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
+ def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
+ def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
+ def_irq_handler MHU0_Handler /* 6: Message Handling Unit 0 */
+ def_irq_handler MHU1_Handler /* 7: Message Handling Unit 1 */
+ def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */
+ def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */
+ def_irq_handler INVALID_INSTR_CACHE_Handler /* 13 CPU Instruction Cache Invalidation Handler */
+ def_irq_handler SYS_PPU_Handler /* 15 SYS PPU Handler */
+ def_irq_handler CPU0_PPU_Handler /* 16 CPU0 PPU Handler */
+ def_irq_handler CPU1_PPU_Handler /* 17 CPU1 PPU Handler */
+ def_irq_handler CPU0_DBG_PPU_Handler /* 18 CPU0 DBG PPU_Handler */
+ def_irq_handler CPU1_DBG_PPU_Handler /* 19 CPU1 DBG PPU_Handler */
+ def_irq_handler CRYPT_PPU_Handler /* 20 CRYPT PPU Handler */
+ def_irq_handler RAM0_PPU_Handler /* 22 RAM0 PPU Handler */
+ def_irq_handler RAM1_PPU_Handler /* 23 RAM1 PPU Handler */
+ def_irq_handler RAM2_PPU_Handler /* 24 RAM2 PPU Handler */
+ def_irq_handler RAM3_PPU_Handler /* 25 RAM3 PPU Handler */
+ def_irq_handler DBG_PPU_Handler /* 26 DBG PPU Handler */
+ def_irq_handler CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
+ def_irq_handler CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
+ def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
+ def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
+ def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
+ def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
+ def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
+ def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
+ def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
+ def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
+ def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
+ def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
+ def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
+ def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
+ def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
+ def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
+ def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
+ def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
+ def_irq_handler I2S_Handler /* 49: I2S Handler */
+ def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
+ def_irq_handler SPI0_Handler /* 51: SPI 0 Handler */
+ def_irq_handler SPI1_Handler /* 52: SPI 1 Handler */
+ def_irq_handler SPI2_Handler /* 53: SPI 2 Handler */
+ def_irq_handler SPI3_Handler /* 54: SPI 3 Handler */
+ def_irq_handler SPI4_Handler /* 55: SPI 4 Handler */
+ def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
+ def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
+ def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */
+ def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
+ def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
+ def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */
+ def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
+ def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
+ def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */
+ def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
+ def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
+ def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */
+ def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+
+ .end
diff --git a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S
index 99d42a6..07fd8f8 100644
--- a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S
+++ b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S
@@ -1,401 +1,401 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.main
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
-
- /* Core interrupts */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* External interrupts */
- .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
- .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
- .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
- .long TIMER0_Handler /* 3: TIMER 0 Handler */
- .long TIMER1_Handler /* 4: TIMER 1 Handler */
- .long DUALTIMER_Handler /* 5: Dual Timer Handler */
- .long MHU0_Handler /* 6: Message Handling Unit 0 */
- .long MHU1_Handler /* 7: Message Handling Unit 1 */
- .long 0 /* 8: Reserved */
- .long MPC_Handler /* 9: MPC Combined (Secure) Handler */
- .long PPC_Handler /* 10: PPC Combined (Secure) Handler */
- .long MSC_Handler /* 11: MSC Combined (Secure) Handler */
- .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */
- .long INVALID_INSTR_CACHE_Handler /* 13: CPU Instruction Cache Invalidation Handler */
- .long 0 /* 14: Reserved */
- .long SYS_PPU_Handler /* 15: SYS PPU Handler */
- .long CPU0_PPU_Handler /* 16: CPU0 PPU Handler */
- .long CPU1_PPU_Handler /* 17: CPU1 PPU Handler */
- .long CPU0_DBG_PPU_Handler /* 18: CPU0 DBG PPU_Handler */
- .long CPU1_DBG_PPU_Handler /* 19: CPU1 DBG PPU_Handler */
- .long CRYPT_PPU_Handler /* 20: CRYPT PPU Handler */
- .long 0 /* 21: Reserved */
- .long RAM0_PPU_Handler /* 22: RAM0 PPU Handler */
- .long RAM1_PPU_Handler /* 23: RAM1 PPU Handler */
- .long RAM2_PPU_Handler /* 24: RAM2 PPU Handler */
- .long RAM3_PPU_Handler /* 25: RAM3 PPU Handler */
- .long DBG_PPU_Handler /* 26: DBG PPU Handler */
- .long 0 /* 27: Reserved */
- .long CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
- .long CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
- .long 0 /* 30: Reserved */
- .long 0 /* 31: Reserved */
- .long UARTRX0_Handler /* 32: UART 0 RX Handler */
- .long UARTTX0_Handler /* 33: UART 0 TX Handler */
- .long UARTRX1_Handler /* 34: UART 1 RX Handler */
- .long UARTTX1_Handler /* 35: UART 1 TX Handler */
- .long UARTRX2_Handler /* 36: UART 2 RX Handler */
- .long UARTTX2_Handler /* 37: UART 2 TX Handler */
- .long UARTRX3_Handler /* 38: UART 3 RX Handler */
- .long UARTTX3_Handler /* 39: UART 3 TX Handler */
- .long UARTRX4_Handler /* 40: UART 4 RX Handler */
- .long UARTTX4_Handler /* 41: UART 4 TX Handler */
- .long UART0_Handler /* 42: UART 0 combined Handler */
- .long UART1_Handler /* 43: UART 1 combined Handler */
- .long UART2_Handler /* 44: UART 2 combined Handler */
- .long UART3_Handler /* 45: UART 3 combined Handler */
- .long UART4_Handler /* 46: UART 4 combined Handler */
- .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
- .long ETHERNET_Handler /* 48: Ethernet Handler */
- .long I2S_Handler /* 49: I2S Handler */
- .long TSC_Handler /* 50: Touch Screen Handler */
- .long SPI0_Handler /* 51: SPI 0 Handler */
- .long SPI1_Handler /* 52: SPI 1 Handler */
- .long SPI2_Handler /* 53: SPI 2 Handler */
- .long SPI3_Handler /* 54: SPI 3 Handler */
- .long SPI4_Handler /* 55: SPI 4 Handler */
- .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
- .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
- .long DMA0_Handler /* 58: DMA 0 Combined Handler */
- .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
- .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
- .long DMA1_Handler /* 61: DMA 1 Combined Handler */
- .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
- .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
- .long DMA2_Handler /* 64: DMA 2 Combined Handler */
- .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
- .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
- .long DMA3_Handler /* 67: DMA 3 Combined Handler */
- .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
- .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
- .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
- .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
- .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
- .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
- .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
- .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
- .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
- .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
- .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
- .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
- .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
- .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
- .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
- .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
- .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
- .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
- .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
- .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
- .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
- .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
- .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
- .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
- .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
- .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
- .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
- .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
-
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- cpsid i /* Disable IRQs */
- bl SystemInit
-
- mrs r0, control /* Get control value */
- orr r0, r0, #2 /* Select switch to PSP */
- msr control, r0
- ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
- msr psp, r0
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- /* Core interrupts */
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
-
- /* External interrupts */
- def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
- def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
- def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
- def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
- def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
- def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
- def_irq_handler MHU0_Handler /* 6: Message Handling Unit 0 */
- def_irq_handler MHU1_Handler /* 7: Message Handling Unit 1 */
- def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */
- def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */
- def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */
- def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */
- def_irq_handler INVALID_INSTR_CACHE_Handler /* 13 CPU Instruction Cache Invalidation Handler */
- def_irq_handler SYS_PPU_Handler /* 15 SYS PPU Handler */
- def_irq_handler CPU0_PPU_Handler /* 16 CPU0 PPU Handler */
- def_irq_handler CPU1_PPU_Handler /* 17 CPU1 PPU Handler */
- def_irq_handler CPU0_DBG_PPU_Handler /* 18 CPU0 DBG PPU_Handler */
- def_irq_handler CPU1_DBG_PPU_Handler /* 19 CPU1 DBG PPU_Handler */
- def_irq_handler CRYPT_PPU_Handler /* 20 CRYPT PPU Handler */
- def_irq_handler RAM0_PPU_Handler /* 22 RAM0 PPU Handler */
- def_irq_handler RAM1_PPU_Handler /* 23 RAM1 PPU Handler */
- def_irq_handler RAM2_PPU_Handler /* 24 RAM2 PPU Handler */
- def_irq_handler RAM3_PPU_Handler /* 25 RAM3 PPU Handler */
- def_irq_handler DBG_PPU_Handler /* 26 DBG PPU Handler */
- def_irq_handler CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
- def_irq_handler CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
- def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
- def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
- def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
- def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
- def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
- def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
- def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
- def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
- def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
- def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
- def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
- def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
- def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
- def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
- def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
- def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
- def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
- def_irq_handler I2S_Handler /* 49: I2S Handler */
- def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
- def_irq_handler SPI0_Handler /* 51: SPI 0 Handler */
- def_irq_handler SPI1_Handler /* 52: SPI 1 Handler */
- def_irq_handler SPI2_Handler /* 53: SPI 2 Handler */
- def_irq_handler SPI3_Handler /* 54: SPI 3 Handler */
- def_irq_handler SPI4_Handler /* 55: SPI 4 Handler */
- def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
- def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
- def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */
- def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
- def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
- def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */
- def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
- def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
- def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */
- def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
- def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
- def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */
- def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
- def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
- def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
- def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
- def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
- def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
- def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
- def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
- def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
- def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
- def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
- def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
- def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
- def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
- def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
- def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
- def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
- def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
- def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
- def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
- def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
- def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
- def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
- def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
- def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
- def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
- def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
- def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
-
- .end
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
+; */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+
+ /* Core interrupts */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long SecureFault_Handler /* Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ .long TIMER0_Handler /* 3: TIMER 0 Handler */
+ .long TIMER1_Handler /* 4: TIMER 1 Handler */
+ .long DUALTIMER_Handler /* 5: Dual Timer Handler */
+ .long MHU0_Handler /* 6: Message Handling Unit 0 */
+ .long MHU1_Handler /* 7: Message Handling Unit 1 */
+ .long 0 /* 8: Reserved */
+ .long MPC_Handler /* 9: MPC Combined (Secure) Handler */
+ .long PPC_Handler /* 10: PPC Combined (Secure) Handler */
+ .long MSC_Handler /* 11: MSC Combined (Secure) Handler */
+ .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */
+ .long INVALID_INSTR_CACHE_Handler /* 13: CPU Instruction Cache Invalidation Handler */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_Handler /* 15: SYS PPU Handler */
+ .long CPU0_PPU_Handler /* 16: CPU0 PPU Handler */
+ .long CPU1_PPU_Handler /* 17: CPU1 PPU Handler */
+ .long CPU0_DBG_PPU_Handler /* 18: CPU0 DBG PPU_Handler */
+ .long CPU1_DBG_PPU_Handler /* 19: CPU1 DBG PPU_Handler */
+ .long CRYPT_PPU_Handler /* 20: CRYPT PPU Handler */
+ .long 0 /* 21: Reserved */
+ .long RAM0_PPU_Handler /* 22: RAM0 PPU Handler */
+ .long RAM1_PPU_Handler /* 23: RAM1 PPU Handler */
+ .long RAM2_PPU_Handler /* 24: RAM2 PPU Handler */
+ .long RAM3_PPU_Handler /* 25: RAM3 PPU Handler */
+ .long DBG_PPU_Handler /* 26: DBG PPU Handler */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
+ .long CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+ .long UARTRX0_Handler /* 32: UART 0 RX Handler */
+ .long UARTTX0_Handler /* 33: UART 0 TX Handler */
+ .long UARTRX1_Handler /* 34: UART 1 RX Handler */
+ .long UARTTX1_Handler /* 35: UART 1 TX Handler */
+ .long UARTRX2_Handler /* 36: UART 2 RX Handler */
+ .long UARTTX2_Handler /* 37: UART 2 TX Handler */
+ .long UARTRX3_Handler /* 38: UART 3 RX Handler */
+ .long UARTTX3_Handler /* 39: UART 3 TX Handler */
+ .long UARTRX4_Handler /* 40: UART 4 RX Handler */
+ .long UARTTX4_Handler /* 41: UART 4 TX Handler */
+ .long UART0_Handler /* 42: UART 0 combined Handler */
+ .long UART1_Handler /* 43: UART 1 combined Handler */
+ .long UART2_Handler /* 44: UART 2 combined Handler */
+ .long UART3_Handler /* 45: UART 3 combined Handler */
+ .long UART4_Handler /* 46: UART 4 combined Handler */
+ .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ .long ETHERNET_Handler /* 48: Ethernet Handler */
+ .long I2S_Handler /* 49: I2S Handler */
+ .long TSC_Handler /* 50: Touch Screen Handler */
+ .long SPI0_Handler /* 51: SPI 0 Handler */
+ .long SPI1_Handler /* 52: SPI 1 Handler */
+ .long SPI2_Handler /* 53: SPI 2 Handler */
+ .long SPI3_Handler /* 54: SPI 3 Handler */
+ .long SPI4_Handler /* 55: SPI 4 Handler */
+ .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
+ .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
+ .long DMA0_Handler /* 58: DMA 0 Combined Handler */
+ .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
+ .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
+ .long DMA1_Handler /* 61: DMA 1 Combined Handler */
+ .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
+ .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
+ .long DMA2_Handler /* 64: DMA 2 Combined Handler */
+ .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
+ .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
+ .long DMA3_Handler /* 67: DMA 3 Combined Handler */
+ .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ cpsid i /* Disable IRQs */
+ bl SystemInit
+
+ mrs r0, control /* Get control value */
+ orr r0, r0, #2 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+ msr psp, r0
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ /* Core interrupts */
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SecureFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* External interrupts */
+ def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
+ def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
+ def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
+ def_irq_handler MHU0_Handler /* 6: Message Handling Unit 0 */
+ def_irq_handler MHU1_Handler /* 7: Message Handling Unit 1 */
+ def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */
+ def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */
+ def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */
+ def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */
+ def_irq_handler INVALID_INSTR_CACHE_Handler /* 13 CPU Instruction Cache Invalidation Handler */
+ def_irq_handler SYS_PPU_Handler /* 15 SYS PPU Handler */
+ def_irq_handler CPU0_PPU_Handler /* 16 CPU0 PPU Handler */
+ def_irq_handler CPU1_PPU_Handler /* 17 CPU1 PPU Handler */
+ def_irq_handler CPU0_DBG_PPU_Handler /* 18 CPU0 DBG PPU_Handler */
+ def_irq_handler CPU1_DBG_PPU_Handler /* 19 CPU1 DBG PPU_Handler */
+ def_irq_handler CRYPT_PPU_Handler /* 20 CRYPT PPU Handler */
+ def_irq_handler RAM0_PPU_Handler /* 22 RAM0 PPU Handler */
+ def_irq_handler RAM1_PPU_Handler /* 23 RAM1 PPU Handler */
+ def_irq_handler RAM2_PPU_Handler /* 24 RAM2 PPU Handler */
+ def_irq_handler RAM3_PPU_Handler /* 25 RAM3 PPU Handler */
+ def_irq_handler DBG_PPU_Handler /* 26 DBG PPU Handler */
+ def_irq_handler CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
+ def_irq_handler CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
+ def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
+ def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
+ def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
+ def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
+ def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
+ def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
+ def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
+ def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
+ def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
+ def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
+ def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
+ def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
+ def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
+ def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
+ def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
+ def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
+ def_irq_handler I2S_Handler /* 49: I2S Handler */
+ def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
+ def_irq_handler SPI0_Handler /* 51: SPI 0 Handler */
+ def_irq_handler SPI1_Handler /* 52: SPI 1 Handler */
+ def_irq_handler SPI2_Handler /* 53: SPI 2 Handler */
+ def_irq_handler SPI3_Handler /* 54: SPI 3 Handler */
+ def_irq_handler SPI4_Handler /* 55: SPI 4 Handler */
+ def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */
+ def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */
+ def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */
+ def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */
+ def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */
+ def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */
+ def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */
+ def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */
+ def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */
+ def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */
+ def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */
+ def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */
+ def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+
+ .end
diff --git a/platform/ext/target/mps2/an521/spm_hal.c b/platform/ext/target/mps2/an521/spm_hal.c
index d95feed..159f671 100644
--- a/platform/ext/target/mps2/an521/spm_hal.c
+++ b/platform/ext/target/mps2/an521/spm_hal.c
@@ -1,324 +1,324 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#include <stdio.h>
-#include "platform/include/tfm_spm_hal.h"
-#include "spm_api.h"
-#include "spm_db.h"
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdio.h>
+#include "platform/include/tfm_spm_hal.h"
+#include "spm_api.h"
+#include "spm_db.h"
#include "tfm_platform_core_api.h"
-#include "target_cfg.h"
-#include "Driver_MPC.h"
-#include "mpu_armv8m_drv.h"
-#include "region_defs.h"
-#include "secure_utilities.h"
-
-/* Import MPC driver */
-extern ARM_DRIVER_MPC Driver_SRAM1_MPC;
-
-/* Get address of memory regions to configure MPU */
-extern const struct memory_region_limits memory_regions;
-
-struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
-
-void tfm_spm_hal_init_isolation_hw(void)
-{
- /* Configures non-secure memory spaces in the target */
- sau_and_idau_cfg();
- mpc_init_cfg();
- ppc_init_cfg();
-}
-
-void tfm_spm_hal_configure_default_isolation(
- const struct tfm_spm_partition_platform_data_t *platform_data)
-{
- if (platform_data) {
- if (platform_data->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) {
- ppc_configure_to_secure(platform_data->periph_ppc_bank,
- platform_data->periph_ppc_loc);
- }
- }
-}
-
-#if TFM_LVL != 1
-
-#define MPU_REGION_VENEERS 0
-#define MPU_REGION_TFM_UNPRIV_CODE 1
-#define MPU_REGION_TFM_UNPRIV_DATA 2
-#define MPU_REGION_NS_DATA 3
-#define PARTITION_REGION_RO 4
-#define PARTITION_REGION_RW_STACK 5
-#define PARTITION_REGION_PERIPH 6
-#define PARTITION_REGION_SHARE 7
-
-REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
-REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
-REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
-REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
-REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
-REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
-
-static enum spm_err_t tfm_spm_mpu_init(void)
-{
- struct mpu_armv8m_region_cfg_t region_cfg;
-
- mpu_armv8m_clean(&dev_mpu_s);
-
- /* Veneer region */
- region_cfg.region_nr = MPU_REGION_VENEERS;
- region_cfg.region_base = memory_regions.veneer_base;
- region_cfg.region_limit = memory_regions.veneer_limit;
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- /* TFM Core unprivileged code region */
- region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_CODE;
- region_cfg.region_base =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
- region_cfg.region_limit =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- /* TFM Core unprivileged data region */
- region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_DATA;
- region_cfg.region_base =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
- region_cfg.region_limit =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- /* TFM Core unprivileged non-secure data region */
- region_cfg.region_nr = MPU_REGION_NS_DATA;
- region_cfg.region_base = NS_DATA_START;
- region_cfg.region_limit = NS_DATA_LIMIT;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return SPM_ERR_OK;
-}
-
-enum spm_err_t tfm_spm_hal_partition_sandbox_config(
- const struct tfm_spm_partition_memory_data_t *memory_data,
- const struct tfm_spm_partition_platform_data_t *platform_data)
-{
- /* This function takes a partition id and enables the
- * SPM partition for that partition
- */
-
- struct mpu_armv8m_region_cfg_t region_cfg;
-
- mpu_armv8m_disable(&dev_mpu_s);
-
- /* Configure Regions */
- if (memory_data->ro_start) {
- /* RO region */
- region_cfg.region_nr = PARTITION_REGION_RO;
- region_cfg.region_base = memory_data->ro_start;
- region_cfg.region_limit = memory_data->ro_limit;
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
-
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
- != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
- }
-
- /* RW, ZI and stack as one region */
- region_cfg.region_nr = PARTITION_REGION_RW_STACK;
- region_cfg.region_base = memory_data->rw_start;
- region_cfg.region_limit = memory_data->stack_top;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
-
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- if (platform_data) {
- /* Peripheral */
- region_cfg.region_nr = PARTITION_REGION_PERIPH;
- region_cfg.region_base = platform_data->periph_start;
- region_cfg.region_limit = platform_data->periph_limit;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
- != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- ppc_en_secure_unpriv(platform_data->periph_ppc_bank,
- platform_data->periph_ppc_loc);
- }
-
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return SPM_ERR_OK;
-}
-
-enum spm_err_t tfm_spm_hal_partition_sandbox_deconfig(
- const struct tfm_spm_partition_memory_data_t *memory_data,
- const struct tfm_spm_partition_platform_data_t *platform_data)
-{
- /* This function takes a partition id and disables the
- * SPM partition for that partition
- */
-
- if (platform_data) {
- /* Peripheral */
- ppc_clr_secure_unpriv(platform_data->periph_ppc_bank,
- platform_data->periph_ppc_loc);
- }
-
- mpu_armv8m_disable(&dev_mpu_s);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RO);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RW_STACK);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_PERIPH);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return SPM_ERR_OK;
-}
-
-/**
- * Set share region to which the partition needs access
- */
-enum spm_err_t tfm_spm_hal_set_share_region(
- enum tfm_buffer_share_region_e share)
-{
- struct mpu_armv8m_region_cfg_t region_cfg;
- enum spm_err_t res = SPM_ERR_INVALID_CONFIG;
- uint32_t scratch_base =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
- uint32_t scratch_limit =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
-
- mpu_armv8m_disable(&dev_mpu_s);
-
- if (share == TFM_BUFFER_SHARE_DISABLE) {
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
- } else {
-
- region_cfg.region_nr = PARTITION_REGION_SHARE;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- switch (share) {
- case TFM_BUFFER_SHARE_SCRATCH:
- /* Use scratch area for SP-to-SP data sharing */
- region_cfg.region_base = scratch_base;
- region_cfg.region_limit = scratch_limit;
- res = SPM_ERR_OK;
- break;
- case TFM_BUFFER_SHARE_NS_CODE:
- region_cfg.region_base = memory_regions.non_secure_partition_base;
- region_cfg.region_limit = memory_regions.non_secure_partition_limit;
- /* Only allow read access to NS code region and keep
- * exec.never attribute
- */
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- res = SPM_ERR_OK;
- break;
- default:
- /* Leave res to be set to SPM_ERR_INVALID_CONFIG */
- break;
- }
- if (res == SPM_ERR_OK) {
- mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg);
- }
- }
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return res;
-}
-
-#endif /* TFM_LVL != 1 */
-
-void tfm_spm_hal_setup_isolation_hw(void)
-{
-#if TFM_LVL != 1
- if (tfm_spm_mpu_init() != SPM_ERR_OK) {
- ERROR_MSG("Failed to set up initial MPU configuration! Halting.");
- while (1) {
- ;
- }
- }
-#endif
-}
-
-void MPC_Handler(void)
-{
- /* Clear MPC interrupt flag and pending MPC IRQ */
- Driver_SRAM1_MPC.ClearInterrupt();
- NVIC_ClearPendingIRQ(MPC_IRQn);
-
- /* Print fault message and block execution */
- LOG_MSG("Oops... MPC fault!!!");
-
- /* Inform TF-M core that isolation boundary has been violated */
- tfm_access_violation_handler();
-}
-
-void PPC_Handler(void)
-{
- /*
- * Due to an issue on the FVP, the PPC fault doesn't trigger a
- * PPC IRQ which is handled by the PPC_handler.
- * In the FVP execution, this code is not execute.
- */
-
- /* Clear PPC interrupt flag and pending PPC IRQ */
- ppc_clear_irq();
- NVIC_ClearPendingIRQ(PPC_IRQn);
-
- /* Print fault message*/
- LOG_MSG("Oops... PPC fault!!!");
-
- /* Inform TF-M core that isolation boundary has been violated */
- tfm_access_violation_handler();
-}
-
-uint32_t tfm_spm_hal_get_ns_VTOR(void)
-{
- return memory_regions.non_secure_code_start;
-}
-
-uint32_t tfm_spm_hal_get_ns_MSP(void)
-{
- return *((uint32_t *)memory_regions.non_secure_code_start);
-}
-
-uint32_t tfm_spm_hal_get_ns_entry_point(void)
-{
- return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
-}
+#include "target_cfg.h"
+#include "Driver_MPC.h"
+#include "mpu_armv8m_drv.h"
+#include "region_defs.h"
+#include "secure_utilities.h"
+
+/* Import MPC driver */
+extern ARM_DRIVER_MPC Driver_SRAM1_MPC;
+
+/* Get address of memory regions to configure MPU */
+extern const struct memory_region_limits memory_regions;
+
+struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
+
+void tfm_spm_hal_init_isolation_hw(void)
+{
+ /* Configures non-secure memory spaces in the target */
+ sau_and_idau_cfg();
+ mpc_init_cfg();
+ ppc_init_cfg();
+}
+
+void tfm_spm_hal_configure_default_isolation(
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ if (platform_data) {
+ if (platform_data->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) {
+ ppc_configure_to_secure(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+ }
+}
+
+#if TFM_LVL != 1
+
+#define MPU_REGION_VENEERS 0
+#define MPU_REGION_TFM_UNPRIV_CODE 1
+#define MPU_REGION_TFM_UNPRIV_DATA 2
+#define MPU_REGION_NS_DATA 3
+#define PARTITION_REGION_RO 4
+#define PARTITION_REGION_RW_STACK 5
+#define PARTITION_REGION_PERIPH 6
+#define PARTITION_REGION_SHARE 7
+
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
+
+static enum spm_err_t tfm_spm_mpu_init(void)
+{
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_armv8m_clean(&dev_mpu_s);
+
+ /* Veneer region */
+ region_cfg.region_nr = MPU_REGION_VENEERS;
+ region_cfg.region_base = memory_regions.veneer_base;
+ region_cfg.region_limit = memory_regions.veneer_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged code region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_CODE;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged data region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_DATA;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged non-secure data region */
+ region_cfg.region_nr = MPU_REGION_NS_DATA;
+ region_cfg.region_base = NS_DATA_START;
+ region_cfg.region_limit = NS_DATA_LIMIT;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+enum spm_err_t tfm_spm_hal_partition_sandbox_config(
+ const struct tfm_spm_partition_memory_data_t *memory_data,
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ /* This function takes a partition id and enables the
+ * SPM partition for that partition
+ */
+
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_armv8m_disable(&dev_mpu_s);
+
+ /* Configure Regions */
+ if (memory_data->ro_start) {
+ /* RO region */
+ region_cfg.region_nr = PARTITION_REGION_RO;
+ region_cfg.region_base = memory_data->ro_start;
+ region_cfg.region_limit = memory_data->ro_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
+ != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+ }
+
+ /* RW, ZI and stack as one region */
+ region_cfg.region_nr = PARTITION_REGION_RW_STACK;
+ region_cfg.region_base = memory_data->rw_start;
+ region_cfg.region_limit = memory_data->stack_top;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ if (platform_data) {
+ /* Peripheral */
+ region_cfg.region_nr = PARTITION_REGION_PERIPH;
+ region_cfg.region_base = platform_data->periph_start;
+ region_cfg.region_limit = platform_data->periph_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
+ != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ ppc_en_secure_unpriv(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+enum spm_err_t tfm_spm_hal_partition_sandbox_deconfig(
+ const struct tfm_spm_partition_memory_data_t *memory_data,
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ /* This function takes a partition id and disables the
+ * SPM partition for that partition
+ */
+
+ if (platform_data) {
+ /* Peripheral */
+ ppc_clr_secure_unpriv(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+
+ mpu_armv8m_disable(&dev_mpu_s);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RO);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RW_STACK);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_PERIPH);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+/**
+ * Set share region to which the partition needs access
+ */
+enum spm_err_t tfm_spm_hal_set_share_region(
+ enum tfm_buffer_share_region_e share)
+{
+ struct mpu_armv8m_region_cfg_t region_cfg;
+ enum spm_err_t res = SPM_ERR_INVALID_CONFIG;
+ uint32_t scratch_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
+ uint32_t scratch_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
+
+ mpu_armv8m_disable(&dev_mpu_s);
+
+ if (share == TFM_BUFFER_SHARE_DISABLE) {
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
+ } else {
+
+ region_cfg.region_nr = PARTITION_REGION_SHARE;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ switch (share) {
+ case TFM_BUFFER_SHARE_SCRATCH:
+ /* Use scratch area for SP-to-SP data sharing */
+ region_cfg.region_base = scratch_base;
+ region_cfg.region_limit = scratch_limit;
+ res = SPM_ERR_OK;
+ break;
+ case TFM_BUFFER_SHARE_NS_CODE:
+ region_cfg.region_base = memory_regions.non_secure_partition_base;
+ region_cfg.region_limit = memory_regions.non_secure_partition_limit;
+ /* Only allow read access to NS code region and keep
+ * exec.never attribute
+ */
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ res = SPM_ERR_OK;
+ break;
+ default:
+ /* Leave res to be set to SPM_ERR_INVALID_CONFIG */
+ break;
+ }
+ if (res == SPM_ERR_OK) {
+ mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg);
+ }
+ }
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return res;
+}
+
+#endif /* TFM_LVL != 1 */
+
+void tfm_spm_hal_setup_isolation_hw(void)
+{
+#if TFM_LVL != 1
+ if (tfm_spm_mpu_init() != SPM_ERR_OK) {
+ ERROR_MSG("Failed to set up initial MPU configuration! Halting.");
+ while (1) {
+ ;
+ }
+ }
+#endif
+}
+
+void MPC_Handler(void)
+{
+ /* Clear MPC interrupt flag and pending MPC IRQ */
+ Driver_SRAM1_MPC.ClearInterrupt();
+ NVIC_ClearPendingIRQ(MPC_IRQn);
+
+ /* Print fault message and block execution */
+ LOG_MSG("Oops... MPC fault!!!");
+
+ /* Inform TF-M core that isolation boundary has been violated */
+ tfm_access_violation_handler();
+}
+
+void PPC_Handler(void)
+{
+ /*
+ * Due to an issue on the FVP, the PPC fault doesn't trigger a
+ * PPC IRQ which is handled by the PPC_handler.
+ * In the FVP execution, this code is not execute.
+ */
+
+ /* Clear PPC interrupt flag and pending PPC IRQ */
+ ppc_clear_irq();
+ NVIC_ClearPendingIRQ(PPC_IRQn);
+
+ /* Print fault message*/
+ LOG_MSG("Oops... PPC fault!!!");
+
+ /* Inform TF-M core that isolation boundary has been violated */
+ tfm_access_violation_handler();
+}
+
+uint32_t tfm_spm_hal_get_ns_VTOR(void)
+{
+ return memory_regions.non_secure_code_start;
+}
+
+uint32_t tfm_spm_hal_get_ns_MSP(void)
+{
+ return *((uint32_t *)memory_regions.non_secure_code_start);
+}
+
+uint32_t tfm_spm_hal_get_ns_entry_point(void)
+{
+ return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
+}
diff --git a/platform/ext/target/mps2/an521/tfm_peripherals_def.h b/platform/ext/target/mps2/an521/tfm_peripherals_def.h
index ee8c354..340a19c 100644
--- a/platform/ext/target/mps2/an521/tfm_peripherals_def.h
+++ b/platform/ext/target/mps2/an521/tfm_peripherals_def.h
@@ -1,21 +1,21 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef __TFM_PERIPHERALS_DEF_H__
-#define __TFM_PERIPHERALS_DEF_H__
-
-struct tfm_spm_partition_platform_data_t;
-
-extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
-extern struct tfm_spm_partition_platform_data_t tfm_peripheral_uart1;
-extern struct tfm_spm_partition_platform_data_t tfm_peripheral_fpga_io;
-
-#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart)
-#define TFM_PERIPHERAL_UART1 (&tfm_peripheral_uart1)
-#define TFM_PERIPHERAL_FPGA_IO (&tfm_peripheral_fpga_io)
-
-#endif /* __TFM_PERIPHERALS_DEF_H__ */
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __TFM_PERIPHERALS_DEF_H__
+#define __TFM_PERIPHERALS_DEF_H__
+
+struct tfm_spm_partition_platform_data_t;
+
+extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
+extern struct tfm_spm_partition_platform_data_t tfm_peripheral_uart1;
+extern struct tfm_spm_partition_platform_data_t tfm_peripheral_fpga_io;
+
+#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart)
+#define TFM_PERIPHERAL_UART1 (&tfm_peripheral_uart1)
+#define TFM_PERIPHERAL_FPGA_IO (&tfm_peripheral_fpga_io)
+
+#endif /* __TFM_PERIPHERALS_DEF_H__ */
diff --git a/platform/ext/target/mps2/smm_mps2.h b/platform/ext/target/mps2/smm_mps2.h
index fb907fe..2d6fabe 100644
--- a/platform/ext/target/mps2/smm_mps2.h
+++ b/platform/ext/target/mps2/smm_mps2.h
@@ -1,168 +1,168 @@
-/*
- * Copyright (c) 2016-2018 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __SMM_MPS2_H__
-#define __SMM_MPS2_H__
-
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SMM_MPS2_H__
+#define __SMM_MPS2_H__
+
#include "cmsis.h" /* device specific header file */
-
-/* FPGAIO register map structure */
-struct arm_mps2_fpgaio_t {
- volatile uint32_t LED; /* Offset: 0x000 (R/W) LED connections
- * [31:2] : Reserved
- * [1:0] : LEDs */
- volatile uint32_t RESERVED1[1];
- volatile uint32_t BUTTON; /* Offset: 0x008 (R/W) Buttons
- * [31:2] : Reserved
- * [1:0] : Buttons */
- volatile uint32_t RESERVED2[1];
- volatile uint32_t CLK1HZ; /* Offset: 0x010 (R/W) 1Hz up counter */
- volatile uint32_t CLK100HZ; /* Offset: 0x014 (R/W) 100Hz up counter */
- volatile uint32_t COUNTER; /* Offset: 0x018 (R/W) Cycle Up Counter
- * Increments when
- * 32bit prescale
- * counter reach
- * zero */
- volatile uint32_t RESERVED3[1];
- volatile uint32_t PRESCALE; /* Offset: 0x020 (R/W) Prescaler
- * Bit[31:0] : reload
- * value for prescale
- * counter */
- volatile uint32_t PSCNTR; /* Offset: 0x024 (R/W) 32bit Prescale
- * counter. Current
- * value of the
- * prescaler counter.
- *
- * The Cycle Up Counter increment when the
- * prescale down counter reach 0.
- * The prescaler counter is reloaded with
- * PRESCALE after reaching 0. */
- volatile uint32_t RESERVED4[9];
- volatile uint32_t MISC; /* Offset: 0x04C (R/W) Misc control
- * [31:10] : Reserved
- * [9] : SHIELD_1_SPI_nCS
- * [8] : SHIELD_0_SPI_nCS
- * [7] : ADC_SPI_nCS
- * [6] : CLCD_BL_CTRL
- * [5] : CLCD_RD
- * [4] : CLCD_RS
- * [3] : CLCD_RESET
- * [2] : RESERVED
- * [1] : SPI_nSS
- * [0] : CLCD_CS */
-};
-
-/* SCC register map structure */
-struct arm_mps2_scc_t {
- volatile uint32_t CFG_REG0; /* Offset: 0x000 (R/W) Remaps block RAM to
- * ZBT
- * [31:1] : Reserved
- * [0] 1 : REMAP BlockRam to ZBT */
- volatile uint32_t LEDS; /* Offset: 0x004 (R/W) Controls the MCC user
- * LEDs
- * [31:8] : Reserved
- * [7:0] : MCC LEDs */
- volatile uint32_t RESERVED0[1];
- volatile uint32_t SWITCHES; /* Offset: 0x00C (R/ ) Denotes the state
- * of the MCC user
- * switches
- * [31:8] : Reserved
- * [7:0] : These bits indicate state
- * of the MCC switches */
- volatile uint32_t CFG_REG4; /* Offset: 0x010 (R/ ) Denotes the board
- * revision
- * [31:4] : Reserved
- * [3:0] : Used by the MCC to pass
- * PCB revision.
- * 0 = A 1 = B */
- volatile uint32_t RESERVED1[35];
- volatile uint32_t SYS_CFGDATA_RTN; /* Offset: 0x0A0 (R/W) User data register
- * [31:0] : Data */
- volatile uint32_t SYS_CFGDATA_OUT; /* Offset: 0x0A4 (R/W) User data
- * register
- * [31:0] : Data */
- volatile uint32_t SYS_CFGCTRL; /* Offset: 0x0A8 (R/W) Control register
- * [31] : Start (generates
- * interrupt on write
- * to this bit)
- * [30] : R/W access
- * [29:26] : Reserved
- * [25:20] : Function value
- * [19:12] : Reserved
- * [11:0] : Device (value of
- * 0/1/2 for supported
- * clocks) */
- volatile uint32_t SYS_CFGSTAT; /* Offset: 0x0AC (R/W) Contains status
- * information
- * [31:2] : Reserved
- * [1] : Error
- * [0] : Complete */
- volatile uint32_t RESERVED2[20];
- volatile uint32_t SCC_DLL; /* Offset: 0x100 (R/W) DLL Lock Register
- * [31:24] : DLL LOCK MASK[7:0]
- * Indicate if the DLL
- * locked is masked
- * [23:16] : DLL LOCK MASK[7:0]
- * Indicate if the DLLs
- * are locked or
- * unlocked
- * [15:1] : Reserved
- * [0] : This bit indicates
- * if all enabled DLLs
- * are locked */
- volatile uint32_t RESERVED3[957];
- volatile uint32_t SCC_AID; /* Offset: 0xFF8 (R/ ) SCC AID Register
- * [31:24] : FPGA build number
- * [23:20] : V2MMPS2 target
- * board revision
- * (A = 0, B = 1)
- * [19:11] : Reserved
- * [10] : if “1” SCC_SW
- * register has been
- * implemented
- * [9] : if “1” SCC_LED
- * register has been
- * implemented
- * [8] : if “1” DLL lock
- * register has been
- * implemented
- * [7:0] : number of SCC
- * configuration
- * register */
- volatile uint32_t SCC_ID; /* Offset: 0xFFC (R/ ) Contains
- * information about
- * the FPGA image
- * [31:24] : Implementer ID:
- * 0x41 = ARM
- * [23:20] : Application note
- * IP variant number
- * [19:16] : IP Architecture:
- * 0x4 =AHB
- * [15:4] : Primary part number:
- * 386 = AN386
- * [3:0] : Application note IP
- * revision number */
-};
-
-/* Peripheral declaration */
-#define MPS2_FPGAIO ((struct arm_mps2_fpgaio_t*) MPS2_IO_FPGAIO_BASE_NS)
-#define MPS2_SCC ((struct arm_mps2_scc_t*) MPS2_IO_SCC_BASE_NS)
-
-/* Secure Peripheral declaration */
-#define SEC_MPS2_FPGAIO ((struct arm_mps2_fpgaio_t*) MPS2_IO_FPGAIO_BASE_S)
-#define SEC_MPS2_SCC ((struct arm_mps2_scc_t*) MPS2_IO_SCC_BASE_S)
-
-#endif /* __SMM_MPS2_H__ */
+
+/* FPGAIO register map structure */
+struct arm_mps2_fpgaio_t {
+ volatile uint32_t LED; /* Offset: 0x000 (R/W) LED connections
+ * [31:2] : Reserved
+ * [1:0] : LEDs */
+ volatile uint32_t RESERVED1[1];
+ volatile uint32_t BUTTON; /* Offset: 0x008 (R/W) Buttons
+ * [31:2] : Reserved
+ * [1:0] : Buttons */
+ volatile uint32_t RESERVED2[1];
+ volatile uint32_t CLK1HZ; /* Offset: 0x010 (R/W) 1Hz up counter */
+ volatile uint32_t CLK100HZ; /* Offset: 0x014 (R/W) 100Hz up counter */
+ volatile uint32_t COUNTER; /* Offset: 0x018 (R/W) Cycle Up Counter
+ * Increments when
+ * 32bit prescale
+ * counter reach
+ * zero */
+ volatile uint32_t RESERVED3[1];
+ volatile uint32_t PRESCALE; /* Offset: 0x020 (R/W) Prescaler
+ * Bit[31:0] : reload
+ * value for prescale
+ * counter */
+ volatile uint32_t PSCNTR; /* Offset: 0x024 (R/W) 32bit Prescale
+ * counter. Current
+ * value of the
+ * prescaler counter.
+ *
+ * The Cycle Up Counter increment when the
+ * prescale down counter reach 0.
+ * The prescaler counter is reloaded with
+ * PRESCALE after reaching 0. */
+ volatile uint32_t RESERVED4[9];
+ volatile uint32_t MISC; /* Offset: 0x04C (R/W) Misc control
+ * [31:10] : Reserved
+ * [9] : SHIELD_1_SPI_nCS
+ * [8] : SHIELD_0_SPI_nCS
+ * [7] : ADC_SPI_nCS
+ * [6] : CLCD_BL_CTRL
+ * [5] : CLCD_RD
+ * [4] : CLCD_RS
+ * [3] : CLCD_RESET
+ * [2] : RESERVED
+ * [1] : SPI_nSS
+ * [0] : CLCD_CS */
+};
+
+/* SCC register map structure */
+struct arm_mps2_scc_t {
+ volatile uint32_t CFG_REG0; /* Offset: 0x000 (R/W) Remaps block RAM to
+ * ZBT
+ * [31:1] : Reserved
+ * [0] 1 : REMAP BlockRam to ZBT */
+ volatile uint32_t LEDS; /* Offset: 0x004 (R/W) Controls the MCC user
+ * LEDs
+ * [31:8] : Reserved
+ * [7:0] : MCC LEDs */
+ volatile uint32_t RESERVED0[1];
+ volatile uint32_t SWITCHES; /* Offset: 0x00C (R/ ) Denotes the state
+ * of the MCC user
+ * switches
+ * [31:8] : Reserved
+ * [7:0] : These bits indicate state
+ * of the MCC switches */
+ volatile uint32_t CFG_REG4; /* Offset: 0x010 (R/ ) Denotes the board
+ * revision
+ * [31:4] : Reserved
+ * [3:0] : Used by the MCC to pass
+ * PCB revision.
+ * 0 = A 1 = B */
+ volatile uint32_t RESERVED1[35];
+ volatile uint32_t SYS_CFGDATA_RTN; /* Offset: 0x0A0 (R/W) User data register
+ * [31:0] : Data */
+ volatile uint32_t SYS_CFGDATA_OUT; /* Offset: 0x0A4 (R/W) User data
+ * register
+ * [31:0] : Data */
+ volatile uint32_t SYS_CFGCTRL; /* Offset: 0x0A8 (R/W) Control register
+ * [31] : Start (generates
+ * interrupt on write
+ * to this bit)
+ * [30] : R/W access
+ * [29:26] : Reserved
+ * [25:20] : Function value
+ * [19:12] : Reserved
+ * [11:0] : Device (value of
+ * 0/1/2 for supported
+ * clocks) */
+ volatile uint32_t SYS_CFGSTAT; /* Offset: 0x0AC (R/W) Contains status
+ * information
+ * [31:2] : Reserved
+ * [1] : Error
+ * [0] : Complete */
+ volatile uint32_t RESERVED2[20];
+ volatile uint32_t SCC_DLL; /* Offset: 0x100 (R/W) DLL Lock Register
+ * [31:24] : DLL LOCK MASK[7:0]
+ * Indicate if the DLL
+ * locked is masked
+ * [23:16] : DLL LOCK MASK[7:0]
+ * Indicate if the DLLs
+ * are locked or
+ * unlocked
+ * [15:1] : Reserved
+ * [0] : This bit indicates
+ * if all enabled DLLs
+ * are locked */
+ volatile uint32_t RESERVED3[957];
+ volatile uint32_t SCC_AID; /* Offset: 0xFF8 (R/ ) SCC AID Register
+ * [31:24] : FPGA build number
+ * [23:20] : V2MMPS2 target
+ * board revision
+ * (A = 0, B = 1)
+ * [19:11] : Reserved
+ * [10] : if “1” SCC_SW
+ * register has been
+ * implemented
+ * [9] : if “1” SCC_LED
+ * register has been
+ * implemented
+ * [8] : if “1” DLL lock
+ * register has been
+ * implemented
+ * [7:0] : number of SCC
+ * configuration
+ * register */
+ volatile uint32_t SCC_ID; /* Offset: 0xFFC (R/ ) Contains
+ * information about
+ * the FPGA image
+ * [31:24] : Implementer ID:
+ * 0x41 = ARM
+ * [23:20] : Application note
+ * IP variant number
+ * [19:16] : IP Architecture:
+ * 0x4 =AHB
+ * [15:4] : Primary part number:
+ * 386 = AN386
+ * [3:0] : Application note IP
+ * revision number */
+};
+
+/* Peripheral declaration */
+#define MPS2_FPGAIO ((struct arm_mps2_fpgaio_t*) MPS2_IO_FPGAIO_BASE_NS)
+#define MPS2_SCC ((struct arm_mps2_scc_t*) MPS2_IO_SCC_BASE_NS)
+
+/* Secure Peripheral declaration */
+#define SEC_MPS2_FPGAIO ((struct arm_mps2_fpgaio_t*) MPS2_IO_FPGAIO_BASE_S)
+#define SEC_MPS2_SCC ((struct arm_mps2_scc_t*) MPS2_IO_SCC_BASE_S)
+
+#endif /* __SMM_MPS2_H__ */
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_ns.s b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_ns.s
index 23c5227..5740902 100644
--- a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_ns.s
+++ b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_ns.s
@@ -1,244 +1,244 @@
-;/*
-; * Copyright (c) 2017-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-;
-; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
-; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
- IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors ;Core Interrupts
- DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
- ;SSE-200 Interrupts
- DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
- DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
- DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
- DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
- DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
- DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
- DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
- DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
- DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
- DCD 0 ; 9: Reserved
- DCD 0 ; 10: Reserved
- DCD 0 ; 11: Reserved
- DCD 0 ; 12: Reserved
- DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
- DCD 0 ; 14: Reserved
- DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
- DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
- DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
- DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
- DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
- DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
- DCD 0 ; 21: Reserved
- DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
- DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
- DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
- DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
- DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
- DCD 0 ; 27: Reserved
- DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
- DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
- DCD 0 ; 30: Reserved
- DCD 0 ; 31: Reserved
- ;Expansion Interrupts
- DCD 0 ; 32: Reserved
- DCD GpTimer_IRQHandler ; 33: General Purpose Timer
- DCD I2C0_IRQHandler ; 34: I2C0
- DCD I2C1_IRQHandler ; 35: I2C1
- DCD I2S_IRQHandler ; 36: I2S
- DCD SPI_IRQHandler ; 37: SPI
- DCD QSPI_IRQHandler ; 38: QSPI
- DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
- DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
- DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
- DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
- DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
- DCD UART0_IRQHandler ; 44: UART0 interrupt
- DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
- DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
- DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
- DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
- DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
- DCD UART1_IRQHandler ; 50: UART0 interrupt
- DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
- DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
- DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
- DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
- DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
- DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
- DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
- DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
- DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
- DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
- DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
- DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
- DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
- DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
- DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
- DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
- DCD Combined_IRQHandler ; 67: Combined interrupt
- DCD PVT_IRQHandler ; 68: PVT sensor interrupt
- DCD 0 ; 69: Reserved
- DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
- DCD RTC_IRQHandler ; 71: RTC interrupt
- DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
- DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
- DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
- DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
- DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
-; Reset Handler
- AREA |.text|, CODE, READONLY
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- MRS R0, control ; Get control value
- ORR R0, R0, #1 ; Select switch to unprivilage mode
- ORR R0, R0, #2 ; Select switch to PSP
- MSR control, R0
- LDR R0, =__main
- BX R0
- ENDP
-End_Of_Main
- B .
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
- MACRO
- Default_Handler $handler_name
-$handler_name PROC
- EXPORT $handler_name [WEAK]
- B .
- ENDP
- MEND
-
- Default_Handler NMI_Handler
- Default_Handler HardFault_Handler
- Default_Handler MemManage_Handler
- Default_Handler BusFault_Handler
- Default_Handler UsageFault_Handler
- Default_Handler SVC_Handler
- Default_Handler DebugMon_Handler
- Default_Handler PendSV_Handler
- Default_Handler SysTick_Handler
-
- Default_Handler NS_WATCHDOG_RESET_IRQHandler
- Default_Handler NS_WATCHDOG_IRQHandler
- Default_Handler S32K_TIMER_IRQHandler
- Default_Handler TIMER0_IRQHandler
- Default_Handler TIMER1_IRQHandler
- Default_Handler DUALTIMER_IRQHandler
- Default_Handler MHU0_IRQHandler
- Default_Handler MHU1_IRQHandler
- Default_Handler CRYPTOCELL_IRQHandler
- Default_Handler I_CACHE_INV_ERR_IRQHandler
- Default_Handler SYS_PPU_IRQHandler
- Default_Handler CPU0_PPU_IRQHandler
- Default_Handler CPU1_PPU_IRQHandler
- Default_Handler CPU0_DGB_PPU_IRQHandler
- Default_Handler CPU1_DGB_PPU_IRQHandler
- Default_Handler CRYPTOCELL_PPU_IRQHandler
- Default_Handler RAM0_PPU_IRQHandler
- Default_Handler RAM1_PPU_IRQHandler
- Default_Handler RAM2_PPU_IRQHandler
- Default_Handler RAM3_PPU_IRQHandler
- Default_Handler DEBUG_PPU_IRQHandler
- Default_Handler CPU0_CTI_IRQHandler
- Default_Handler CPU1_CTI_IRQHandler
-
- Default_Handler GpTimer_IRQHandler
- Default_Handler I2C0_IRQHandler
- Default_Handler I2C1_IRQHandler
- Default_Handler I2S_IRQHandler
- Default_Handler SPI_IRQHandler
- Default_Handler QSPI_IRQHandler
- Default_Handler UARTRX0_Handler
- Default_Handler UARTTX0_Handler
- Default_Handler UART0_RxTimeout_IRQHandler
- Default_Handler UART0_ModemStatus_IRQHandler
- Default_Handler UART0_Error_IRQHandler
- Default_Handler UART0_IRQHandler
- Default_Handler UARTRX1_Handler
- Default_Handler UARTTX1_Handler
- Default_Handler UART1_RxTimeout_IRQHandler
- Default_Handler UART1_ModemStatus_IRQHandler
- Default_Handler UART1_Error_IRQHandler
- Default_Handler UART1_IRQHandler
- Default_Handler GPIO_0_IRQHandler
- Default_Handler GPIO_1_IRQHandler
- Default_Handler GPIO_2_IRQHandler
- Default_Handler GPIO_3_IRQHandler
- Default_Handler GPIO_4_IRQHandler
- Default_Handler GPIO_5_IRQHandler
- Default_Handler GPIO_6_IRQHandler
- Default_Handler GPIO_7_IRQHandler
- Default_Handler GPIO_8_IRQHandler
- Default_Handler GPIO_9_IRQHandler
- Default_Handler GPIO_10_IRQHandler
- Default_Handler GPIO_11_IRQHandler
- Default_Handler GPIO_12_IRQHandler
- Default_Handler GPIO_13_IRQHandler
- Default_Handler GPIO_14_IRQHandler
- Default_Handler GPIO_15_IRQHandler
- Default_Handler Combined_IRQHandler
- Default_Handler PVT_IRQHandler
- Default_Handler PWM_0_IRQHandler
- Default_Handler RTC_IRQHandler
- Default_Handler GpTimer0_IRQHandler
- Default_Handler GpTimer1_IRQHandler
- Default_Handler PWM_1_IRQHandler
- Default_Handler PWM_2_IRQHandler
- Default_Handler IOMUX_IRQHandler
-
- ALIGN
-
- END
+;/*
+; * Copyright (c) 2017-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
+; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors ;Core Interrupts
+ DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ;SSE-200 Interrupts
+ DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
+ DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
+ DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
+ DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
+ DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
+ DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
+ DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
+ DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
+ DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
+ DCD 0 ; 9: Reserved
+ DCD 0 ; 10: Reserved
+ DCD 0 ; 11: Reserved
+ DCD 0 ; 12: Reserved
+ DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
+ DCD 0 ; 14: Reserved
+ DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
+ DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
+ DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
+ DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
+ DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
+ DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
+ DCD 0 ; 21: Reserved
+ DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
+ DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
+ DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
+ DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
+ DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
+ DCD 0 ; 27: Reserved
+ DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
+ DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
+ DCD 0 ; 30: Reserved
+ DCD 0 ; 31: Reserved
+ ;Expansion Interrupts
+ DCD 0 ; 32: Reserved
+ DCD GpTimer_IRQHandler ; 33: General Purpose Timer
+ DCD I2C0_IRQHandler ; 34: I2C0
+ DCD I2C1_IRQHandler ; 35: I2C1
+ DCD I2S_IRQHandler ; 36: I2S
+ DCD SPI_IRQHandler ; 37: SPI
+ DCD QSPI_IRQHandler ; 38: QSPI
+ DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
+ DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
+ DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
+ DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
+ DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
+ DCD UART0_IRQHandler ; 44: UART0 interrupt
+ DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
+ DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
+ DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
+ DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
+ DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
+ DCD UART1_IRQHandler ; 50: UART0 interrupt
+ DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
+ DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
+ DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
+ DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
+ DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
+ DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
+ DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
+ DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
+ DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
+ DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
+ DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
+ DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
+ DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
+ DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
+ DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
+ DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
+ DCD Combined_IRQHandler ; 67: Combined interrupt
+ DCD PVT_IRQHandler ; 68: PVT sensor interrupt
+ DCD 0 ; 69: Reserved
+ DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
+ DCD RTC_IRQHandler ; 71: RTC interrupt
+ DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
+ DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
+ DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
+ DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
+ DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ AREA |.text|, CODE, READONLY
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ MRS R0, control ; Get control value
+ ORR R0, R0, #1 ; Select switch to unprivilage mode
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+End_Of_Main
+ B .
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+ MACRO
+ Default_Handler $handler_name
+$handler_name PROC
+ EXPORT $handler_name [WEAK]
+ B .
+ ENDP
+ MEND
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler MemManage_Handler
+ Default_Handler BusFault_Handler
+ Default_Handler UsageFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler DebugMon_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+ Default_Handler NS_WATCHDOG_RESET_IRQHandler
+ Default_Handler NS_WATCHDOG_IRQHandler
+ Default_Handler S32K_TIMER_IRQHandler
+ Default_Handler TIMER0_IRQHandler
+ Default_Handler TIMER1_IRQHandler
+ Default_Handler DUALTIMER_IRQHandler
+ Default_Handler MHU0_IRQHandler
+ Default_Handler MHU1_IRQHandler
+ Default_Handler CRYPTOCELL_IRQHandler
+ Default_Handler I_CACHE_INV_ERR_IRQHandler
+ Default_Handler SYS_PPU_IRQHandler
+ Default_Handler CPU0_PPU_IRQHandler
+ Default_Handler CPU1_PPU_IRQHandler
+ Default_Handler CPU0_DGB_PPU_IRQHandler
+ Default_Handler CPU1_DGB_PPU_IRQHandler
+ Default_Handler CRYPTOCELL_PPU_IRQHandler
+ Default_Handler RAM0_PPU_IRQHandler
+ Default_Handler RAM1_PPU_IRQHandler
+ Default_Handler RAM2_PPU_IRQHandler
+ Default_Handler RAM3_PPU_IRQHandler
+ Default_Handler DEBUG_PPU_IRQHandler
+ Default_Handler CPU0_CTI_IRQHandler
+ Default_Handler CPU1_CTI_IRQHandler
+
+ Default_Handler GpTimer_IRQHandler
+ Default_Handler I2C0_IRQHandler
+ Default_Handler I2C1_IRQHandler
+ Default_Handler I2S_IRQHandler
+ Default_Handler SPI_IRQHandler
+ Default_Handler QSPI_IRQHandler
+ Default_Handler UARTRX0_Handler
+ Default_Handler UARTTX0_Handler
+ Default_Handler UART0_RxTimeout_IRQHandler
+ Default_Handler UART0_ModemStatus_IRQHandler
+ Default_Handler UART0_Error_IRQHandler
+ Default_Handler UART0_IRQHandler
+ Default_Handler UARTRX1_Handler
+ Default_Handler UARTTX1_Handler
+ Default_Handler UART1_RxTimeout_IRQHandler
+ Default_Handler UART1_ModemStatus_IRQHandler
+ Default_Handler UART1_Error_IRQHandler
+ Default_Handler UART1_IRQHandler
+ Default_Handler GPIO_0_IRQHandler
+ Default_Handler GPIO_1_IRQHandler
+ Default_Handler GPIO_2_IRQHandler
+ Default_Handler GPIO_3_IRQHandler
+ Default_Handler GPIO_4_IRQHandler
+ Default_Handler GPIO_5_IRQHandler
+ Default_Handler GPIO_6_IRQHandler
+ Default_Handler GPIO_7_IRQHandler
+ Default_Handler GPIO_8_IRQHandler
+ Default_Handler GPIO_9_IRQHandler
+ Default_Handler GPIO_10_IRQHandler
+ Default_Handler GPIO_11_IRQHandler
+ Default_Handler GPIO_12_IRQHandler
+ Default_Handler GPIO_13_IRQHandler
+ Default_Handler GPIO_14_IRQHandler
+ Default_Handler GPIO_15_IRQHandler
+ Default_Handler Combined_IRQHandler
+ Default_Handler PVT_IRQHandler
+ Default_Handler PWM_0_IRQHandler
+ Default_Handler RTC_IRQHandler
+ Default_Handler GpTimer0_IRQHandler
+ Default_Handler GpTimer1_IRQHandler
+ Default_Handler PWM_1_IRQHandler
+ Default_Handler PWM_2_IRQHandler
+ Default_Handler IOMUX_IRQHandler
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s
index bff2a82..c618ef3 100644
--- a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s
+++ b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s
@@ -1,252 +1,252 @@
-;/*
-; * Copyright (c) 2017-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-;
-; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
-; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
- IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors ;Core Interrupts
- DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD SecureFault_Handler ; Secure Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
- ;SSE-200 Interrupts
- DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
- DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
- DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
- DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
- DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
- DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
- DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
- DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
- DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
- DCD MPC_Handler ; 9: Secure Combined MPC Interrupt
- DCD PPC_Handler ; 10: Secure Combined PPC Interrupt
- DCD S_MSC_COMBINED_IRQHandler ; 11: Secure Combined MSC Interrupt
- DCD S_BRIDGE_ERR_IRQHandler ; 12: Secure Bridge Error Combined Interrupt
- DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
- DCD 0 ; 14: Reserved
- DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
- DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
- DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
- DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
- DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
- DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
- DCD 0 ; 21: Reserved
- DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
- DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
- DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
- DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
- DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
- DCD 0 ; 27: Reserved
- DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
- DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
- DCD 0 ; 30: Reserved
- DCD 0 ; 31: Reserved
- ;Expansion Interrupts
- DCD 0 ; 32: Reserved
- DCD GpTimer_IRQHandler ; 33: General Purpose Timer
- DCD I2C0_IRQHandler ; 34: I2C0
- DCD I2C1_IRQHandler ; 35: I2C1
- DCD I2S_IRQHandler ; 36: I2S
- DCD SPI_IRQHandler ; 37: SPI
- DCD QSPI_IRQHandler ; 38: QSPI
- DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
- DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
- DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
- DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
- DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
- DCD UART0_IRQHandler ; 44: UART0 interrupt
- DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
- DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
- DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
- DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
- DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
- DCD UART1_IRQHandler ; 50: UART0 interrupt
- DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
- DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
- DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
- DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
- DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
- DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
- DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
- DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
- DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
- DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
- DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
- DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
- DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
- DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
- DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
- DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
- DCD Combined_IRQHandler ; 67: Combined interrupt
- DCD PVT_IRQHandler ; 68: PVT sensor interrupt
- DCD 0 ; 69: Reserved
- DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
- DCD RTC_IRQHandler ; 71: RTC interrupt
- DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
- DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
- DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
- DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
- DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
-; Reset Handler
- AREA |.text|, CODE, READONLY
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- CPSID i ; Disable IRQs
- LDR R0, =SystemInit
- BLX R0
- MRS R0, control ; Get control value
- ORR R0, R0, #2 ; Select switch to PSP
- MSR control, R0
- LDR R0, =__main
- BX R0
- ENDP
-End_Of_Main
- B .
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
- MACRO
- Default_Handler $handler_name
-$handler_name PROC
- EXPORT $handler_name [WEAK]
- B .
- ENDP
- MEND
-
- Default_Handler NMI_Handler
- Default_Handler HardFault_Handler
- Default_Handler MemManage_Handler
- Default_Handler BusFault_Handler
- Default_Handler UsageFault_Handler
- Default_Handler SecureFault_Handler
- Default_Handler SVC_Handler
- Default_Handler DebugMon_Handler
- Default_Handler PendSV_Handler
- Default_Handler SysTick_Handler
-
- Default_Handler NS_WATCHDOG_RESET_IRQHandler
- Default_Handler NS_WATCHDOG_IRQHandler
- Default_Handler S32K_TIMER_IRQHandler
- Default_Handler TIMER0_IRQHandler
- Default_Handler TIMER1_IRQHandler
- Default_Handler DUALTIMER_IRQHandler
- Default_Handler MHU0_IRQHandler
- Default_Handler MHU1_IRQHandler
- Default_Handler CRYPTOCELL_IRQHandler
- Default_Handler MPC_Handler
- Default_Handler PPC_Handler
- Default_Handler S_MSC_COMBINED_IRQHandler
- Default_Handler S_BRIDGE_ERR_IRQHandler
- Default_Handler I_CACHE_INV_ERR_IRQHandler
- Default_Handler SYS_PPU_IRQHandler
- Default_Handler CPU0_PPU_IRQHandler
- Default_Handler CPU1_PPU_IRQHandler
- Default_Handler CPU0_DGB_PPU_IRQHandler
- Default_Handler CPU1_DGB_PPU_IRQHandler
- Default_Handler CRYPTOCELL_PPU_IRQHandler
- Default_Handler RAM0_PPU_IRQHandler
- Default_Handler RAM1_PPU_IRQHandler
- Default_Handler RAM2_PPU_IRQHandler
- Default_Handler RAM3_PPU_IRQHandler
- Default_Handler DEBUG_PPU_IRQHandler
- Default_Handler CPU0_CTI_IRQHandler
- Default_Handler CPU1_CTI_IRQHandler
-
- Default_Handler GpTimer_IRQHandler
- Default_Handler I2C0_IRQHandler
- Default_Handler I2C1_IRQHandler
- Default_Handler I2S_IRQHandler
- Default_Handler SPI_IRQHandler
- Default_Handler QSPI_IRQHandler
- Default_Handler UARTRX0_Handler
- Default_Handler UARTTX0_Handler
- Default_Handler UART0_RxTimeout_IRQHandler
- Default_Handler UART0_ModemStatus_IRQHandler
- Default_Handler UART0_Error_IRQHandler
- Default_Handler UART0_IRQHandler
- Default_Handler UARTRX1_Handler
- Default_Handler UARTTX1_Handler
- Default_Handler UART1_RxTimeout_IRQHandler
- Default_Handler UART1_ModemStatus_IRQHandler
- Default_Handler UART1_Error_IRQHandler
- Default_Handler UART1_IRQHandler
- Default_Handler GPIO_0_IRQHandler
- Default_Handler GPIO_1_IRQHandler
- Default_Handler GPIO_2_IRQHandler
- Default_Handler GPIO_3_IRQHandler
- Default_Handler GPIO_4_IRQHandler
- Default_Handler GPIO_5_IRQHandler
- Default_Handler GPIO_6_IRQHandler
- Default_Handler GPIO_7_IRQHandler
- Default_Handler GPIO_8_IRQHandler
- Default_Handler GPIO_9_IRQHandler
- Default_Handler GPIO_10_IRQHandler
- Default_Handler GPIO_11_IRQHandler
- Default_Handler GPIO_12_IRQHandler
- Default_Handler GPIO_13_IRQHandler
- Default_Handler GPIO_14_IRQHandler
- Default_Handler GPIO_15_IRQHandler
- Default_Handler Combined_IRQHandler
- Default_Handler PVT_IRQHandler
- Default_Handler PWM_0_IRQHandler
- Default_Handler RTC_IRQHandler
- Default_Handler GpTimer0_IRQHandler
- Default_Handler GpTimer1_IRQHandler
- Default_Handler PWM_1_IRQHandler
- Default_Handler PWM_2_IRQHandler
- Default_Handler IOMUX_IRQHandler
-
- ALIGN
-
- END
+;/*
+; * Copyright (c) 2017-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
+; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors ;Core Interrupts
+ DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ;SSE-200 Interrupts
+ DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
+ DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
+ DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
+ DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
+ DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
+ DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
+ DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
+ DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
+ DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
+ DCD MPC_Handler ; 9: Secure Combined MPC Interrupt
+ DCD PPC_Handler ; 10: Secure Combined PPC Interrupt
+ DCD S_MSC_COMBINED_IRQHandler ; 11: Secure Combined MSC Interrupt
+ DCD S_BRIDGE_ERR_IRQHandler ; 12: Secure Bridge Error Combined Interrupt
+ DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
+ DCD 0 ; 14: Reserved
+ DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
+ DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
+ DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
+ DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
+ DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
+ DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
+ DCD 0 ; 21: Reserved
+ DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
+ DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
+ DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
+ DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
+ DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
+ DCD 0 ; 27: Reserved
+ DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
+ DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
+ DCD 0 ; 30: Reserved
+ DCD 0 ; 31: Reserved
+ ;Expansion Interrupts
+ DCD 0 ; 32: Reserved
+ DCD GpTimer_IRQHandler ; 33: General Purpose Timer
+ DCD I2C0_IRQHandler ; 34: I2C0
+ DCD I2C1_IRQHandler ; 35: I2C1
+ DCD I2S_IRQHandler ; 36: I2S
+ DCD SPI_IRQHandler ; 37: SPI
+ DCD QSPI_IRQHandler ; 38: QSPI
+ DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
+ DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
+ DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
+ DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
+ DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
+ DCD UART0_IRQHandler ; 44: UART0 interrupt
+ DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
+ DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
+ DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
+ DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
+ DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
+ DCD UART1_IRQHandler ; 50: UART0 interrupt
+ DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
+ DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
+ DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
+ DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
+ DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
+ DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
+ DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
+ DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
+ DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
+ DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
+ DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
+ DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
+ DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
+ DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
+ DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
+ DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
+ DCD Combined_IRQHandler ; 67: Combined interrupt
+ DCD PVT_IRQHandler ; 68: PVT sensor interrupt
+ DCD 0 ; 69: Reserved
+ DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
+ DCD RTC_IRQHandler ; 71: RTC interrupt
+ DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
+ DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
+ DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
+ DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
+ DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ AREA |.text|, CODE, READONLY
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ CPSID i ; Disable IRQs
+ LDR R0, =SystemInit
+ BLX R0
+ MRS R0, control ; Get control value
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+End_Of_Main
+ B .
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+ MACRO
+ Default_Handler $handler_name
+$handler_name PROC
+ EXPORT $handler_name [WEAK]
+ B .
+ ENDP
+ MEND
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler MemManage_Handler
+ Default_Handler BusFault_Handler
+ Default_Handler UsageFault_Handler
+ Default_Handler SecureFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler DebugMon_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+ Default_Handler NS_WATCHDOG_RESET_IRQHandler
+ Default_Handler NS_WATCHDOG_IRQHandler
+ Default_Handler S32K_TIMER_IRQHandler
+ Default_Handler TIMER0_IRQHandler
+ Default_Handler TIMER1_IRQHandler
+ Default_Handler DUALTIMER_IRQHandler
+ Default_Handler MHU0_IRQHandler
+ Default_Handler MHU1_IRQHandler
+ Default_Handler CRYPTOCELL_IRQHandler
+ Default_Handler MPC_Handler
+ Default_Handler PPC_Handler
+ Default_Handler S_MSC_COMBINED_IRQHandler
+ Default_Handler S_BRIDGE_ERR_IRQHandler
+ Default_Handler I_CACHE_INV_ERR_IRQHandler
+ Default_Handler SYS_PPU_IRQHandler
+ Default_Handler CPU0_PPU_IRQHandler
+ Default_Handler CPU1_PPU_IRQHandler
+ Default_Handler CPU0_DGB_PPU_IRQHandler
+ Default_Handler CPU1_DGB_PPU_IRQHandler
+ Default_Handler CRYPTOCELL_PPU_IRQHandler
+ Default_Handler RAM0_PPU_IRQHandler
+ Default_Handler RAM1_PPU_IRQHandler
+ Default_Handler RAM2_PPU_IRQHandler
+ Default_Handler RAM3_PPU_IRQHandler
+ Default_Handler DEBUG_PPU_IRQHandler
+ Default_Handler CPU0_CTI_IRQHandler
+ Default_Handler CPU1_CTI_IRQHandler
+
+ Default_Handler GpTimer_IRQHandler
+ Default_Handler I2C0_IRQHandler
+ Default_Handler I2C1_IRQHandler
+ Default_Handler I2S_IRQHandler
+ Default_Handler SPI_IRQHandler
+ Default_Handler QSPI_IRQHandler
+ Default_Handler UARTRX0_Handler
+ Default_Handler UARTTX0_Handler
+ Default_Handler UART0_RxTimeout_IRQHandler
+ Default_Handler UART0_ModemStatus_IRQHandler
+ Default_Handler UART0_Error_IRQHandler
+ Default_Handler UART0_IRQHandler
+ Default_Handler UARTRX1_Handler
+ Default_Handler UARTTX1_Handler
+ Default_Handler UART1_RxTimeout_IRQHandler
+ Default_Handler UART1_ModemStatus_IRQHandler
+ Default_Handler UART1_Error_IRQHandler
+ Default_Handler UART1_IRQHandler
+ Default_Handler GPIO_0_IRQHandler
+ Default_Handler GPIO_1_IRQHandler
+ Default_Handler GPIO_2_IRQHandler
+ Default_Handler GPIO_3_IRQHandler
+ Default_Handler GPIO_4_IRQHandler
+ Default_Handler GPIO_5_IRQHandler
+ Default_Handler GPIO_6_IRQHandler
+ Default_Handler GPIO_7_IRQHandler
+ Default_Handler GPIO_8_IRQHandler
+ Default_Handler GPIO_9_IRQHandler
+ Default_Handler GPIO_10_IRQHandler
+ Default_Handler GPIO_11_IRQHandler
+ Default_Handler GPIO_12_IRQHandler
+ Default_Handler GPIO_13_IRQHandler
+ Default_Handler GPIO_14_IRQHandler
+ Default_Handler GPIO_15_IRQHandler
+ Default_Handler Combined_IRQHandler
+ Default_Handler PVT_IRQHandler
+ Default_Handler PWM_0_IRQHandler
+ Default_Handler RTC_IRQHandler
+ Default_Handler GpTimer0_IRQHandler
+ Default_Handler GpTimer1_IRQHandler
+ Default_Handler PWM_1_IRQHandler
+ Default_Handler PWM_2_IRQHandler
+ Default_Handler IOMUX_IRQHandler
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_bl2.S b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_bl2.S
index 06b06fd..7c1e449 100644
--- a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_bl2.S
+++ b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_bl2.S
@@ -1,364 +1,364 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.main
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* Core interrupts */
- .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
- .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
- .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
- .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
- .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
- .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
- .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
- .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
- .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
- .long MPC_Handler /* 9: Secure Combined MPC Interrupt */
- .long PPC_Handler /* 10: Secure Combined PPC Interrupt */
- .long S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
- .long S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
- .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
- .long 0 /* 14: Reserved */
- .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
- .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
- .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
- .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
- .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
- .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
- .long 0 /* 21: Reserved */
- .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
- .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
- .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
- .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
- .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
- .long 0 /* 27: Reserved */
- .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
- .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
- .long 0 /* 30: Reserved */
- .long 0 /* 31: Reserved */
-
- /* External interrupts */
- .long 0 /* 32: Reserved */
- .long GpTimer_IRQHandler /* 33: General Purpose Timer */
- .long I2C0_IRQHandler /* 34: I2C0 */
- .long I2C1_IRQHandler /* 35: I2C1 */
- .long I2S_IRQHandler /* 36: I2S */
- .long SPI_IRQHandler /* 37: SPI */
- .long QSPI_IRQHandler /* 38: QSPI */
- .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
- .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
- .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
- .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
- .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
- .long UART0_IRQHandler /* 44: UART0 interrupt */
- .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
- .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
- .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
- .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
- .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
- .long UART1_IRQHandler /* 50: UART0 interrupt */
- .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
- .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
- .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
- .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
- .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
- .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
- .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
- .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
- .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
- .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
- .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
- .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
- .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
- .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
- .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
- .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
- .long Combined_IRQHandler /* 67: Combined interrupt */
- .long PVT_IRQHandler /* 68: PVT sensor interrupt */
- .long 0 /* 69: Reserved */
- .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
- .long RTC_IRQHandler /* 71: RTC interrupt */
- .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
- .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
- .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
- .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
- .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
- /* Only run on core 0 */
- mov r0, #0x50000000
- add r0, #0x0001F000
- ldr r0, [r0]
- cmp r0,#0
-not_the_core_to_run_on:
- bne not_the_core_to_run_on
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
-
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- bl SystemInit
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
-
- /* Core interrupts */
- def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
- def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
- def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
- def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
- def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
- def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
- def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
- def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
- def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
- def_irq_handler MPC_Handler /* 9: Secure Combined MPC Interrupt */
- def_irq_handler PPC_Handler /* 10: Secure Combined PPC Interrupt */
- def_irq_handler S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
- def_irq_handler S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
- def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
- def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
- def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
- def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
- def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
- def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
- def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
- def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
- def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
- def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
- def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
- def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
- def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
- def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
-
- /* External interrupts */
- def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
- def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
- def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
- def_irq_handler I2S_IRQHandler /* 36: I2S */
- def_irq_handler SPI_IRQHandler /* 37: SPI */
- def_irq_handler QSPI_IRQHandler /* 38: QSPI */
- def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
- def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
- def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
- def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
- def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
- def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
- def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
- def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
- def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
- def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
- def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
- def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
- def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
- def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
- def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
- def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
- def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
- def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
- def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
- def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
- def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
- def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
- def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
- def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
- def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
- def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
- def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
- def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
- def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
- def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
- def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
- def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
- def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
- def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
- def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
- def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
- def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
-
- .end
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
+; */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long SecureFault_Handler /* Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* Core interrupts */
+ .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ .long MPC_Handler /* 9: Secure Combined MPC Interrupt */
+ .long PPC_Handler /* 10: Secure Combined PPC Interrupt */
+ .long S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
+ .long S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
+ .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ .long 0 /* 21: Reserved */
+ .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+
+ /* External interrupts */
+ .long 0 /* 32: Reserved */
+ .long GpTimer_IRQHandler /* 33: General Purpose Timer */
+ .long I2C0_IRQHandler /* 34: I2C0 */
+ .long I2C1_IRQHandler /* 35: I2C1 */
+ .long I2S_IRQHandler /* 36: I2S */
+ .long SPI_IRQHandler /* 37: SPI */
+ .long QSPI_IRQHandler /* 38: QSPI */
+ .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ .long UART0_IRQHandler /* 44: UART0 interrupt */
+ .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ .long UART1_IRQHandler /* 50: UART0 interrupt */
+ .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ .long Combined_IRQHandler /* 67: Combined interrupt */
+ .long PVT_IRQHandler /* 68: PVT sensor interrupt */
+ .long 0 /* 69: Reserved */
+ .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ .long RTC_IRQHandler /* 71: RTC interrupt */
+ .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+ /* Only run on core 0 */
+ mov r0, #0x50000000
+ add r0, #0x0001F000
+ ldr r0, [r0]
+ cmp r0,#0
+not_the_core_to_run_on:
+ bne not_the_core_to_run_on
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ bl SystemInit
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SecureFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* Core interrupts */
+ def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ def_irq_handler MPC_Handler /* 9: Secure Combined MPC Interrupt */
+ def_irq_handler PPC_Handler /* 10: Secure Combined PPC Interrupt */
+ def_irq_handler S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
+ def_irq_handler S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
+ def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+
+ /* External interrupts */
+ def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
+ def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
+ def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
+ def_irq_handler I2S_IRQHandler /* 36: I2S */
+ def_irq_handler SPI_IRQHandler /* 37: SPI */
+ def_irq_handler QSPI_IRQHandler /* 38: QSPI */
+ def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
+ def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
+ def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
+ def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
+ def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
+ def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .end
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_ns.S b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_ns.S
index 299cd5f..9a69d8b 100644
--- a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_ns.S
+++ b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_ns.S
@@ -1,356 +1,356 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.main
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* Core interrupts */
- .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
- .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
- .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
- .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
- .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
- .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
- .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
- .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
- .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
- .long 0 /* 9: Reserved */
- .long 0 /* 10: Reserved */
- .long 0 /* 11: Reserved */
- .long 0 /* 12: Reserved */
- .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
- .long 0 /* 14: Reserved */
- .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
- .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
- .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
- .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
- .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
- .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
- .long 0 /* 21: Reserved */
- .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
- .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
- .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
- .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
- .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
- .long 0 /* 27: Reserved */
- .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
- .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
- .long 0 /* 30: Reserved */
- .long 0 /* 31: Reserved */
-
- /* External interrupts */
- .long 0 /* 32: Reserved */
- .long GpTimer_IRQHandler /* 33: General Purpose Timer */
- .long I2C0_IRQHandler /* 34: I2C0 */
- .long I2C1_IRQHandler /* 35: I2C1 */
- .long I2S_IRQHandler /* 36: I2S */
- .long SPI_IRQHandler /* 37: SPI */
- .long QSPI_IRQHandler /* 38: QSPI */
- .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
- .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
- .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
- .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
- .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
- .long UART0_IRQHandler /* 44: UART0 interrupt */
- .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
- .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
- .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
- .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
- .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
- .long UART1_IRQHandler /* 50: UART0 interrupt */
- .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
- .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
- .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
- .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
- .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
- .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
- .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
- .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
- .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
- .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
- .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
- .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
- .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
- .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
- .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
- .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
- .long Combined_IRQHandler /* 67: Combined interrupt */
- .long PVT_IRQHandler /* 68: PVT sensor interrupt */
- .long 0 /* 69: Reserved */
- .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
- .long RTC_IRQHandler /* 71: RTC interrupt */
- .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
- .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
- .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
- .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
- .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
-
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- mrs r0, control /* Get control value */
- orr r0, r0, #1 /* Select switch to unprivilage mode */
- orr r0, r0, #2 /* Select switch to PSP */
- msr control, r0
- ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
- msr psp, r0
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
-
- /* Core interrupts */
- def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
- def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
- def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
- def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
- def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
- def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
- def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
- def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
- def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
- def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
- def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
- def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
- def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
- def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
- def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
- def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
- def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
- def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
- def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
- def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
- def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
- def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
- def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
-
- /* External interrupts */
- def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
- def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
- def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
- def_irq_handler I2S_IRQHandler /* 36: I2S */
- def_irq_handler SPI_IRQHandler /* 37: SPI */
- def_irq_handler QSPI_IRQHandler /* 38: QSPI */
- def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
- def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
- def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
- def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
- def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
- def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
- def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
- def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
- def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
- def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
- def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
- def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
- def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
- def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
- def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
- def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
- def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
- def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
- def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
- def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
- def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
- def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
- def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
- def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
- def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
- def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
- def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
- def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
- def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
- def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
- def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
- def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
- def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
- def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
- def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
- def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
- def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
-
- .end
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
+; */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* Core interrupts */
+ .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ .long 0 /* 9: Reserved */
+ .long 0 /* 10: Reserved */
+ .long 0 /* 11: Reserved */
+ .long 0 /* 12: Reserved */
+ .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ .long 0 /* 21: Reserved */
+ .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+
+ /* External interrupts */
+ .long 0 /* 32: Reserved */
+ .long GpTimer_IRQHandler /* 33: General Purpose Timer */
+ .long I2C0_IRQHandler /* 34: I2C0 */
+ .long I2C1_IRQHandler /* 35: I2C1 */
+ .long I2S_IRQHandler /* 36: I2S */
+ .long SPI_IRQHandler /* 37: SPI */
+ .long QSPI_IRQHandler /* 38: QSPI */
+ .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ .long UART0_IRQHandler /* 44: UART0 interrupt */
+ .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ .long UART1_IRQHandler /* 50: UART0 interrupt */
+ .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ .long Combined_IRQHandler /* 67: Combined interrupt */
+ .long PVT_IRQHandler /* 68: PVT sensor interrupt */
+ .long 0 /* 69: Reserved */
+ .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ .long RTC_IRQHandler /* 71: RTC interrupt */
+ .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ mrs r0, control /* Get control value */
+ orr r0, r0, #1 /* Select switch to unprivilage mode */
+ orr r0, r0, #2 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+ msr psp, r0
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* Core interrupts */
+ def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+
+ /* External interrupts */
+ def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
+ def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
+ def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
+ def_irq_handler I2S_IRQHandler /* 36: I2S */
+ def_irq_handler SPI_IRQHandler /* 37: SPI */
+ def_irq_handler QSPI_IRQHandler /* 38: QSPI */
+ def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
+ def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
+ def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
+ def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
+ def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
+ def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .end
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_s.S b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_s.S
index 152d64c..a24ac31 100644
--- a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_s.S
+++ b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_s.S
@@ -1,363 +1,363 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.main
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* Core interrupts */
- .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
- .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
- .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
- .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
- .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
- .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
- .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
- .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
- .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
- .long MPC_Handler /* 9: Secure Combined MPC Interrupt */
- .long PPC_Handler /* 10: Secure Combined PPC Interrupt */
- .long S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
- .long S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
- .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
- .long 0 /* 14: Reserved */
- .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
- .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
- .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
- .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
- .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
- .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
- .long 0 /* 21: Reserved */
- .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
- .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
- .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
- .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
- .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
- .long 0 /* 27: Reserved */
- .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
- .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
- .long 0 /* 30: Reserved */
- .long 0 /* 31: Reserved */
-
- /* External interrupts */
- .long 0 /* 32: Reserved */
- .long GpTimer_IRQHandler /* 33: General Purpose Timer */
- .long I2C0_IRQHandler /* 34: I2C0 */
- .long I2C1_IRQHandler /* 35: I2C1 */
- .long I2S_IRQHandler /* 36: I2S */
- .long SPI_IRQHandler /* 37: SPI */
- .long QSPI_IRQHandler /* 38: QSPI */
- .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
- .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
- .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
- .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
- .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
- .long UART0_IRQHandler /* 44: UART0 interrupt */
- .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
- .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
- .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
- .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
- .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
- .long UART1_IRQHandler /* 50: UART0 interrupt */
- .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
- .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
- .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
- .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
- .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
- .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
- .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
- .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
- .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
- .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
- .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
- .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
- .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
- .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
- .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
- .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
- .long Combined_IRQHandler /* 67: Combined interrupt */
- .long PVT_IRQHandler /* 68: PVT sensor interrupt */
- .long 0 /* 69: Reserved */
- .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
- .long RTC_IRQHandler /* 71: RTC interrupt */
- .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
- .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
- .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
- .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
- .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
-
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- cpsid i /* Disable IRQs */
- bl SystemInit
-
- mrs r0, control /* Get control value */
- orr r0, r0, #2 /* Select switch to PSP */
- msr control, r0
- ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
- msr psp, r0
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
-
- /* Core interrupts */
- def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
- def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
- def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
- def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
- def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
- def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
- def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
- def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
- def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
- def_irq_handler MPC_Handler /* 9: Secure Combined MPC Interrupt */
- def_irq_handler PPC_Handler /* 10: Secure Combined PPC Interrupt */
- def_irq_handler S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
- def_irq_handler S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
- def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
- def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
- def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
- def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
- def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
- def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
- def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
- def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
- def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
- def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
- def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
- def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
- def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
- def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
-
- /* External interrupts */
- def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
- def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
- def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
- def_irq_handler I2S_IRQHandler /* 36: I2S */
- def_irq_handler SPI_IRQHandler /* 37: SPI */
- def_irq_handler QSPI_IRQHandler /* 38: QSPI */
- def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
- def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
- def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
- def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
- def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
- def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
- def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
- def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
- def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
- def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
- def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
- def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
- def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
- def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
- def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
- def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
- def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
- def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
- def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
- def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
- def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
- def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
- def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
- def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
- def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
- def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
- def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
- def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
- def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
- def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
- def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
- def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
- def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
- def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
- def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
- def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
- def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
-
- .end
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
+; */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long SecureFault_Handler /* Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* Core interrupts */
+ .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ .long MPC_Handler /* 9: Secure Combined MPC Interrupt */
+ .long PPC_Handler /* 10: Secure Combined PPC Interrupt */
+ .long S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
+ .long S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
+ .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ .long 0 /* 21: Reserved */
+ .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+
+ /* External interrupts */
+ .long 0 /* 32: Reserved */
+ .long GpTimer_IRQHandler /* 33: General Purpose Timer */
+ .long I2C0_IRQHandler /* 34: I2C0 */
+ .long I2C1_IRQHandler /* 35: I2C1 */
+ .long I2S_IRQHandler /* 36: I2S */
+ .long SPI_IRQHandler /* 37: SPI */
+ .long QSPI_IRQHandler /* 38: QSPI */
+ .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ .long UART0_IRQHandler /* 44: UART0 interrupt */
+ .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ .long UART1_IRQHandler /* 50: UART0 interrupt */
+ .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ .long Combined_IRQHandler /* 67: Combined interrupt */
+ .long PVT_IRQHandler /* 68: PVT sensor interrupt */
+ .long 0 /* 69: Reserved */
+ .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ .long RTC_IRQHandler /* 71: RTC interrupt */
+ .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ cpsid i /* Disable IRQs */
+ bl SystemInit
+
+ mrs r0, control /* Get control value */
+ orr r0, r0, #2 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+ msr psp, r0
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SecureFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* Core interrupts */
+ def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ def_irq_handler MPC_Handler /* 9: Secure Combined MPC Interrupt */
+ def_irq_handler PPC_Handler /* 10: Secure Combined PPC Interrupt */
+ def_irq_handler S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
+ def_irq_handler S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
+ def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+
+ /* External interrupts */
+ def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
+ def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
+ def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
+ def_irq_handler I2S_IRQHandler /* 36: I2S */
+ def_irq_handler SPI_IRQHandler /* 37: SPI */
+ def_irq_handler QSPI_IRQHandler /* 38: QSPI */
+ def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
+ def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
+ def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
+ def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
+ def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
+ def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .end
diff --git a/platform/ext/target/musca_a/spm_hal.c b/platform/ext/target/musca_a/spm_hal.c
index 53e51d6..a3fef1f 100644
--- a/platform/ext/target/musca_a/spm_hal.c
+++ b/platform/ext/target/musca_a/spm_hal.c
@@ -1,324 +1,324 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#include <stdio.h>
-#include "platform/include/tfm_spm_hal.h"
-#include "spm_api.h"
-#include "spm_db.h"
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdio.h>
+#include "platform/include/tfm_spm_hal.h"
+#include "spm_api.h"
+#include "spm_db.h"
#include "tfm_platform_core_api.h"
-#include "target_cfg.h"
-#include "Driver_MPC.h"
-#include "mpu_armv8m_drv.h"
-#include "region_defs.h"
-#include "secure_utilities.h"
-
-/* Import MPC driver */
-extern ARM_DRIVER_MPC Driver_CODE_SRAM_MPC;
-
-/* Get address of memory regions to configure MPU */
-extern const struct memory_region_limits memory_regions;
-
-struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
-
-void tfm_spm_hal_init_isolation_hw(void)
-{
- /* Configures non-secure memory spaces in the target */
- sau_and_idau_cfg();
- mpc_init_cfg();
- ppc_init_cfg();
-}
-
-void tfm_spm_hal_configure_default_isolation(
- const struct tfm_spm_partition_platform_data_t *platform_data)
-{
- if (platform_data) {
- if (platform_data->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) {
- ppc_configure_to_secure(platform_data->periph_ppc_bank,
- platform_data->periph_ppc_loc);
- }
- }
-}
-
-#if TFM_LVL != 1
-
-#define MPU_REGION_VENEERS 0
-#define MPU_REGION_TFM_UNPRIV_CODE 1
-#define MPU_REGION_TFM_UNPRIV_DATA 2
-#define MPU_REGION_NS_DATA 3
-#define PARTITION_REGION_RO 4
-#define PARTITION_REGION_RW_STACK 5
-#define PARTITION_REGION_PERIPH 6
-#define PARTITION_REGION_SHARE 7
-
-REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
-REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
-REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
-REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
-REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
-REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
-
-static enum spm_err_t tfm_spm_mpu_init(void)
-{
- struct mpu_armv8m_region_cfg_t region_cfg;
-
- mpu_armv8m_clean(&dev_mpu_s);
-
- /* Veneer region */
- region_cfg.region_nr = MPU_REGION_VENEERS;
- region_cfg.region_base = memory_regions.veneer_base;
- region_cfg.region_limit = memory_regions.veneer_limit;
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- /* TFM Core unprivileged code region */
- region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_CODE;
- region_cfg.region_base =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
- region_cfg.region_limit =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- /* TFM Core unprivileged data region */
- region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_DATA;
- region_cfg.region_base =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
- region_cfg.region_limit =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- /* TFM Core unprivileged non-secure data region */
- region_cfg.region_nr = MPU_REGION_NS_DATA;
- region_cfg.region_base = NS_DATA_START;
- region_cfg.region_limit = NS_DATA_LIMIT;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return SPM_ERR_OK;
-}
-
-enum spm_err_t tfm_spm_hal_partition_sandbox_config(
- const struct tfm_spm_partition_memory_data_t *memory_data,
- const struct tfm_spm_partition_platform_data_t *platform_data)
-{
- /* This function takes a partition id and enables the
- * SPM partition for that partition
- */
-
- struct mpu_armv8m_region_cfg_t region_cfg;
-
- mpu_armv8m_disable(&dev_mpu_s);
-
- /* Configure Regions */
- if (memory_data->ro_start) {
- /* RO region */
- region_cfg.region_nr = PARTITION_REGION_RO;
- region_cfg.region_base = memory_data->ro_start;
- region_cfg.region_limit = memory_data->ro_limit;
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
-
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
- != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
- }
-
- /* RW, ZI and stack as one region */
- region_cfg.region_nr = PARTITION_REGION_RW_STACK;
- region_cfg.region_base = memory_data->rw_start;
- region_cfg.region_limit = memory_data->stack_top;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
-
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- if (platform_data) {
- /* Peripheral */
- region_cfg.region_nr = PARTITION_REGION_PERIPH;
- region_cfg.region_base = platform_data->periph_start;
- region_cfg.region_limit = platform_data->periph_limit;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
- != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- ppc_en_secure_unpriv(platform_data->periph_ppc_bank,
- platform_data->periph_ppc_loc);
- }
-
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return SPM_ERR_OK;
-}
-
-enum spm_err_t tfm_spm_hal_partition_sandbox_deconfig(
- const struct tfm_spm_partition_memory_data_t *memory_data,
- const struct tfm_spm_partition_platform_data_t *platform_data)
-{
- /* This function takes a partition id and disables the
- * SPM partition for that partition
- */
-
- if (platform_data) {
- /* Peripheral */
- ppc_clr_secure_unpriv(platform_data->periph_ppc_bank,
- platform_data->periph_ppc_loc);
- }
-
- mpu_armv8m_disable(&dev_mpu_s);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RO);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RW_STACK);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_PERIPH);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return SPM_ERR_OK;
-}
-
-/**
- * Set share region to which the partition needs access
- */
-enum spm_err_t tfm_spm_hal_set_share_region(
- enum tfm_buffer_share_region_e share)
-{
- struct mpu_armv8m_region_cfg_t region_cfg;
- enum spm_err_t res = SPM_ERR_INVALID_CONFIG;
- uint32_t scratch_base =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
- uint32_t scratch_limit =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
-
- mpu_armv8m_disable(&dev_mpu_s);
-
- if (share == TFM_BUFFER_SHARE_DISABLE) {
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
- } else {
-
- region_cfg.region_nr = PARTITION_REGION_SHARE;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- switch (share) {
- case TFM_BUFFER_SHARE_SCRATCH:
- /* Use scratch area for SP-to-SP data sharing */
- region_cfg.region_base = scratch_base;
- region_cfg.region_limit = scratch_limit;
- res = SPM_ERR_OK;
- break;
- case TFM_BUFFER_SHARE_NS_CODE:
- region_cfg.region_base = memory_regions.non_secure_partition_base;
- region_cfg.region_limit = memory_regions.non_secure_partition_limit;
- /* Only allow read access to NS code region and keep
- * exec.never attribute
- */
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- res = SPM_ERR_OK;
- break;
- default:
- /* Leave res to be set to SPM_ERR_INVALID_CONFIG */
- break;
- }
- if (res == SPM_ERR_OK) {
- mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg);
- }
- }
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return res;
-}
-
-#endif /* TFM_LVL != 1 */
-
-void tfm_spm_hal_setup_isolation_hw(void)
-{
-#if TFM_LVL != 1
- if (tfm_spm_mpu_init() != SPM_ERR_OK) {
- ERROR_MSG("Failed to set up initial MPU configuration! Halting.");
- while (1) {
- ;
- }
- }
-#endif
-}
-
-void MPC_Handler(void)
-{
- /* Clear MPC interrupt flag and pending MPC IRQ */
- Driver_CODE_SRAM_MPC.ClearInterrupt();
- NVIC_ClearPendingIRQ(S_MPC_COMBINED_IRQn);
-
- /* Print fault message and block execution */
- LOG_MSG("Oops... MPC fault!!!");
-
- /* Inform TF-M core that isolation boundary has been violated */
- tfm_access_violation_handler();
-}
-
-void PPC_Handler(void)
-{
- /*
- * Due to an issue on the FVP, the PPC fault doesn't trigger a
- * PPC IRQ which is handled by the PPC_handler.
- * In the FVP execution, this code is not execute.
- */
-
- /* Clear PPC interrupt flag and pending PPC IRQ */
- ppc_clear_irq();
- NVIC_ClearPendingIRQ(S_PPC_COMBINED_IRQn);
-
- /* Print fault message*/
- LOG_MSG("Oops... PPC fault!!!");
-
- /* Inform TF-M core that isolation boundary has been violated */
- tfm_access_violation_handler();
-}
-
-uint32_t tfm_spm_hal_get_ns_VTOR(void)
-{
- return memory_regions.non_secure_code_start;
-}
-
-uint32_t tfm_spm_hal_get_ns_MSP(void)
-{
- return *((uint32_t *)memory_regions.non_secure_code_start);
-}
-
-uint32_t tfm_spm_hal_get_ns_entry_point(void)
-{
- return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
-}
+#include "target_cfg.h"
+#include "Driver_MPC.h"
+#include "mpu_armv8m_drv.h"
+#include "region_defs.h"
+#include "secure_utilities.h"
+
+/* Import MPC driver */
+extern ARM_DRIVER_MPC Driver_CODE_SRAM_MPC;
+
+/* Get address of memory regions to configure MPU */
+extern const struct memory_region_limits memory_regions;
+
+struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
+
+void tfm_spm_hal_init_isolation_hw(void)
+{
+ /* Configures non-secure memory spaces in the target */
+ sau_and_idau_cfg();
+ mpc_init_cfg();
+ ppc_init_cfg();
+}
+
+void tfm_spm_hal_configure_default_isolation(
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ if (platform_data) {
+ if (platform_data->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) {
+ ppc_configure_to_secure(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+ }
+}
+
+#if TFM_LVL != 1
+
+#define MPU_REGION_VENEERS 0
+#define MPU_REGION_TFM_UNPRIV_CODE 1
+#define MPU_REGION_TFM_UNPRIV_DATA 2
+#define MPU_REGION_NS_DATA 3
+#define PARTITION_REGION_RO 4
+#define PARTITION_REGION_RW_STACK 5
+#define PARTITION_REGION_PERIPH 6
+#define PARTITION_REGION_SHARE 7
+
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
+
+static enum spm_err_t tfm_spm_mpu_init(void)
+{
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_armv8m_clean(&dev_mpu_s);
+
+ /* Veneer region */
+ region_cfg.region_nr = MPU_REGION_VENEERS;
+ region_cfg.region_base = memory_regions.veneer_base;
+ region_cfg.region_limit = memory_regions.veneer_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged code region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_CODE;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged data region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_DATA;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged non-secure data region */
+ region_cfg.region_nr = MPU_REGION_NS_DATA;
+ region_cfg.region_base = NS_DATA_START;
+ region_cfg.region_limit = NS_DATA_LIMIT;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+enum spm_err_t tfm_spm_hal_partition_sandbox_config(
+ const struct tfm_spm_partition_memory_data_t *memory_data,
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ /* This function takes a partition id and enables the
+ * SPM partition for that partition
+ */
+
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_armv8m_disable(&dev_mpu_s);
+
+ /* Configure Regions */
+ if (memory_data->ro_start) {
+ /* RO region */
+ region_cfg.region_nr = PARTITION_REGION_RO;
+ region_cfg.region_base = memory_data->ro_start;
+ region_cfg.region_limit = memory_data->ro_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
+ != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+ }
+
+ /* RW, ZI and stack as one region */
+ region_cfg.region_nr = PARTITION_REGION_RW_STACK;
+ region_cfg.region_base = memory_data->rw_start;
+ region_cfg.region_limit = memory_data->stack_top;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ if (platform_data) {
+ /* Peripheral */
+ region_cfg.region_nr = PARTITION_REGION_PERIPH;
+ region_cfg.region_base = platform_data->periph_start;
+ region_cfg.region_limit = platform_data->periph_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
+ != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ ppc_en_secure_unpriv(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+enum spm_err_t tfm_spm_hal_partition_sandbox_deconfig(
+ const struct tfm_spm_partition_memory_data_t *memory_data,
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ /* This function takes a partition id and disables the
+ * SPM partition for that partition
+ */
+
+ if (platform_data) {
+ /* Peripheral */
+ ppc_clr_secure_unpriv(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+
+ mpu_armv8m_disable(&dev_mpu_s);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RO);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RW_STACK);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_PERIPH);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+/**
+ * Set share region to which the partition needs access
+ */
+enum spm_err_t tfm_spm_hal_set_share_region(
+ enum tfm_buffer_share_region_e share)
+{
+ struct mpu_armv8m_region_cfg_t region_cfg;
+ enum spm_err_t res = SPM_ERR_INVALID_CONFIG;
+ uint32_t scratch_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
+ uint32_t scratch_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
+
+ mpu_armv8m_disable(&dev_mpu_s);
+
+ if (share == TFM_BUFFER_SHARE_DISABLE) {
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
+ } else {
+
+ region_cfg.region_nr = PARTITION_REGION_SHARE;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ switch (share) {
+ case TFM_BUFFER_SHARE_SCRATCH:
+ /* Use scratch area for SP-to-SP data sharing */
+ region_cfg.region_base = scratch_base;
+ region_cfg.region_limit = scratch_limit;
+ res = SPM_ERR_OK;
+ break;
+ case TFM_BUFFER_SHARE_NS_CODE:
+ region_cfg.region_base = memory_regions.non_secure_partition_base;
+ region_cfg.region_limit = memory_regions.non_secure_partition_limit;
+ /* Only allow read access to NS code region and keep
+ * exec.never attribute
+ */
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ res = SPM_ERR_OK;
+ break;
+ default:
+ /* Leave res to be set to SPM_ERR_INVALID_CONFIG */
+ break;
+ }
+ if (res == SPM_ERR_OK) {
+ mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg);
+ }
+ }
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return res;
+}
+
+#endif /* TFM_LVL != 1 */
+
+void tfm_spm_hal_setup_isolation_hw(void)
+{
+#if TFM_LVL != 1
+ if (tfm_spm_mpu_init() != SPM_ERR_OK) {
+ ERROR_MSG("Failed to set up initial MPU configuration! Halting.");
+ while (1) {
+ ;
+ }
+ }
+#endif
+}
+
+void MPC_Handler(void)
+{
+ /* Clear MPC interrupt flag and pending MPC IRQ */
+ Driver_CODE_SRAM_MPC.ClearInterrupt();
+ NVIC_ClearPendingIRQ(S_MPC_COMBINED_IRQn);
+
+ /* Print fault message and block execution */
+ LOG_MSG("Oops... MPC fault!!!");
+
+ /* Inform TF-M core that isolation boundary has been violated */
+ tfm_access_violation_handler();
+}
+
+void PPC_Handler(void)
+{
+ /*
+ * Due to an issue on the FVP, the PPC fault doesn't trigger a
+ * PPC IRQ which is handled by the PPC_handler.
+ * In the FVP execution, this code is not execute.
+ */
+
+ /* Clear PPC interrupt flag and pending PPC IRQ */
+ ppc_clear_irq();
+ NVIC_ClearPendingIRQ(S_PPC_COMBINED_IRQn);
+
+ /* Print fault message*/
+ LOG_MSG("Oops... PPC fault!!!");
+
+ /* Inform TF-M core that isolation boundary has been violated */
+ tfm_access_violation_handler();
+}
+
+uint32_t tfm_spm_hal_get_ns_VTOR(void)
+{
+ return memory_regions.non_secure_code_start;
+}
+
+uint32_t tfm_spm_hal_get_ns_MSP(void)
+{
+ return *((uint32_t *)memory_regions.non_secure_code_start);
+}
+
+uint32_t tfm_spm_hal_get_ns_entry_point(void)
+{
+ return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
+}
diff --git a/platform/ext/target/musca_a/tfm_peripherals_def.h b/platform/ext/target/musca_a/tfm_peripherals_def.h
index 0f5bca9..ab5f174 100644
--- a/platform/ext/target/musca_a/tfm_peripherals_def.h
+++ b/platform/ext/target/musca_a/tfm_peripherals_def.h
@@ -1,17 +1,17 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef __TFM_PERIPHERALS_DEF_H__
-#define __TFM_PERIPHERALS_DEF_H__
-
-struct tfm_spm_partition_platform_data_t;
-
-extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
-
-#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart)
-
-#endif /* __TFM_PERIPHERALS_DEF_H__ */
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __TFM_PERIPHERALS_DEF_H__
+#define __TFM_PERIPHERALS_DEF_H__
+
+struct tfm_spm_partition_platform_data_t;
+
+extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
+
+#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart)
+
+#endif /* __TFM_PERIPHERALS_DEF_H__ */
diff --git a/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_ns.s b/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_ns.s
index 8c1cc5a..1789c5a 100644
--- a/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_ns.s
+++ b/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_ns.s
@@ -1,244 +1,244 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-;
-; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
-; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
- IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors ;Core Interrupts
- DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
- ;SSE-200 Interrupts
- DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
- DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
- DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
- DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
- DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
- DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
- DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
- DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
- DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
- DCD 0 ; 9: Reserved
- DCD 0 ; 10: Reserved
- DCD 0 ; 11: Reserved
- DCD 0 ; 12: Reserved
- DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
- DCD 0 ; 14: Reserved
- DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
- DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
- DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
- DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
- DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
- DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
- DCD 0 ; 21: Reserved
- DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
- DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
- DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
- DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
- DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
- DCD 0 ; 27: Reserved
- DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
- DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
- DCD 0 ; 30: Reserved
- DCD 0 ; 31: Reserved
- ;Expansion Interrupts
- DCD 0 ; 32: Reserved
- DCD GpTimer_IRQHandler ; 33: General Purpose Timer
- DCD I2C0_IRQHandler ; 34: I2C0
- DCD I2C1_IRQHandler ; 35: I2C1
- DCD I2S_IRQHandler ; 36: I2S
- DCD SPI_IRQHandler ; 37: SPI
- DCD QSPI_IRQHandler ; 38: QSPI
- DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
- DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
- DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
- DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
- DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
- DCD UART0_IRQHandler ; 44: UART0 interrupt
- DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
- DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
- DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
- DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
- DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
- DCD UART1_IRQHandler ; 50: UART0 interrupt
- DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
- DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
- DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
- DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
- DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
- DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
- DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
- DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
- DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
- DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
- DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
- DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
- DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
- DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
- DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
- DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
- DCD Combined_IRQHandler ; 67: Combined interrupt
- DCD PVT_IRQHandler ; 68: PVT sensor interrupt
- DCD 0 ; 69: Reserved
- DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
- DCD RTC_IRQHandler ; 71: RTC interrupt
- DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
- DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
- DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
- DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
- DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
-; Reset Handler
- AREA |.text|, CODE, READONLY
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- MRS R0, control ; Get control value
- ORR R0, R0, #1 ; Select switch to unprivilage mode
- ORR R0, R0, #2 ; Select switch to PSP
- MSR control, R0
- LDR R0, =__main
- BX R0
- ENDP
-End_Of_Main
- B .
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
- MACRO
- Default_Handler $handler_name
-$handler_name PROC
- EXPORT $handler_name [WEAK]
- B .
- ENDP
- MEND
-
- Default_Handler NMI_Handler
- Default_Handler HardFault_Handler
- Default_Handler MemManage_Handler
- Default_Handler BusFault_Handler
- Default_Handler UsageFault_Handler
- Default_Handler SVC_Handler
- Default_Handler DebugMon_Handler
- Default_Handler PendSV_Handler
- Default_Handler SysTick_Handler
-
- Default_Handler NS_WATCHDOG_RESET_IRQHandler
- Default_Handler NS_WATCHDOG_IRQHandler
- Default_Handler S32K_TIMER_IRQHandler
- Default_Handler TIMER0_IRQHandler
- Default_Handler TIMER1_IRQHandler
- Default_Handler DUALTIMER_IRQHandler
- Default_Handler MHU0_IRQHandler
- Default_Handler MHU1_IRQHandler
- Default_Handler CRYPTOCELL_IRQHandler
- Default_Handler I_CACHE_INV_ERR_IRQHandler
- Default_Handler SYS_PPU_IRQHandler
- Default_Handler CPU0_PPU_IRQHandler
- Default_Handler CPU1_PPU_IRQHandler
- Default_Handler CPU0_DGB_PPU_IRQHandler
- Default_Handler CPU1_DGB_PPU_IRQHandler
- Default_Handler CRYPTOCELL_PPU_IRQHandler
- Default_Handler RAM0_PPU_IRQHandler
- Default_Handler RAM1_PPU_IRQHandler
- Default_Handler RAM2_PPU_IRQHandler
- Default_Handler RAM3_PPU_IRQHandler
- Default_Handler DEBUG_PPU_IRQHandler
- Default_Handler CPU0_CTI_IRQHandler
- Default_Handler CPU1_CTI_IRQHandler
-
- Default_Handler GpTimer_IRQHandler
- Default_Handler I2C0_IRQHandler
- Default_Handler I2C1_IRQHandler
- Default_Handler I2S_IRQHandler
- Default_Handler SPI_IRQHandler
- Default_Handler QSPI_IRQHandler
- Default_Handler UARTRX0_Handler
- Default_Handler UARTTX0_Handler
- Default_Handler UART0_RxTimeout_IRQHandler
- Default_Handler UART0_ModemStatus_IRQHandler
- Default_Handler UART0_Error_IRQHandler
- Default_Handler UART0_IRQHandler
- Default_Handler UARTRX1_Handler
- Default_Handler UARTTX1_Handler
- Default_Handler UART1_RxTimeout_IRQHandler
- Default_Handler UART1_ModemStatus_IRQHandler
- Default_Handler UART1_Error_IRQHandler
- Default_Handler UART1_IRQHandler
- Default_Handler GPIO_0_IRQHandler
- Default_Handler GPIO_1_IRQHandler
- Default_Handler GPIO_2_IRQHandler
- Default_Handler GPIO_3_IRQHandler
- Default_Handler GPIO_4_IRQHandler
- Default_Handler GPIO_5_IRQHandler
- Default_Handler GPIO_6_IRQHandler
- Default_Handler GPIO_7_IRQHandler
- Default_Handler GPIO_8_IRQHandler
- Default_Handler GPIO_9_IRQHandler
- Default_Handler GPIO_10_IRQHandler
- Default_Handler GPIO_11_IRQHandler
- Default_Handler GPIO_12_IRQHandler
- Default_Handler GPIO_13_IRQHandler
- Default_Handler GPIO_14_IRQHandler
- Default_Handler GPIO_15_IRQHandler
- Default_Handler Combined_IRQHandler
- Default_Handler PVT_IRQHandler
- Default_Handler PWM_0_IRQHandler
- Default_Handler RTC_IRQHandler
- Default_Handler GpTimer0_IRQHandler
- Default_Handler GpTimer1_IRQHandler
- Default_Handler PWM_1_IRQHandler
- Default_Handler PWM_2_IRQHandler
- Default_Handler IOMUX_IRQHandler
-
- ALIGN
-
- END
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
+; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors ;Core Interrupts
+ DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ;SSE-200 Interrupts
+ DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
+ DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
+ DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
+ DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
+ DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
+ DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
+ DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
+ DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
+ DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
+ DCD 0 ; 9: Reserved
+ DCD 0 ; 10: Reserved
+ DCD 0 ; 11: Reserved
+ DCD 0 ; 12: Reserved
+ DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
+ DCD 0 ; 14: Reserved
+ DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
+ DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
+ DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
+ DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
+ DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
+ DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
+ DCD 0 ; 21: Reserved
+ DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
+ DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
+ DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
+ DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
+ DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
+ DCD 0 ; 27: Reserved
+ DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
+ DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
+ DCD 0 ; 30: Reserved
+ DCD 0 ; 31: Reserved
+ ;Expansion Interrupts
+ DCD 0 ; 32: Reserved
+ DCD GpTimer_IRQHandler ; 33: General Purpose Timer
+ DCD I2C0_IRQHandler ; 34: I2C0
+ DCD I2C1_IRQHandler ; 35: I2C1
+ DCD I2S_IRQHandler ; 36: I2S
+ DCD SPI_IRQHandler ; 37: SPI
+ DCD QSPI_IRQHandler ; 38: QSPI
+ DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
+ DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
+ DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
+ DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
+ DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
+ DCD UART0_IRQHandler ; 44: UART0 interrupt
+ DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
+ DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
+ DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
+ DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
+ DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
+ DCD UART1_IRQHandler ; 50: UART0 interrupt
+ DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
+ DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
+ DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
+ DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
+ DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
+ DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
+ DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
+ DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
+ DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
+ DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
+ DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
+ DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
+ DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
+ DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
+ DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
+ DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
+ DCD Combined_IRQHandler ; 67: Combined interrupt
+ DCD PVT_IRQHandler ; 68: PVT sensor interrupt
+ DCD 0 ; 69: Reserved
+ DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
+ DCD RTC_IRQHandler ; 71: RTC interrupt
+ DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
+ DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
+ DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
+ DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
+ DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ AREA |.text|, CODE, READONLY
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ MRS R0, control ; Get control value
+ ORR R0, R0, #1 ; Select switch to unprivilage mode
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+End_Of_Main
+ B .
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+ MACRO
+ Default_Handler $handler_name
+$handler_name PROC
+ EXPORT $handler_name [WEAK]
+ B .
+ ENDP
+ MEND
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler MemManage_Handler
+ Default_Handler BusFault_Handler
+ Default_Handler UsageFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler DebugMon_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+ Default_Handler NS_WATCHDOG_RESET_IRQHandler
+ Default_Handler NS_WATCHDOG_IRQHandler
+ Default_Handler S32K_TIMER_IRQHandler
+ Default_Handler TIMER0_IRQHandler
+ Default_Handler TIMER1_IRQHandler
+ Default_Handler DUALTIMER_IRQHandler
+ Default_Handler MHU0_IRQHandler
+ Default_Handler MHU1_IRQHandler
+ Default_Handler CRYPTOCELL_IRQHandler
+ Default_Handler I_CACHE_INV_ERR_IRQHandler
+ Default_Handler SYS_PPU_IRQHandler
+ Default_Handler CPU0_PPU_IRQHandler
+ Default_Handler CPU1_PPU_IRQHandler
+ Default_Handler CPU0_DGB_PPU_IRQHandler
+ Default_Handler CPU1_DGB_PPU_IRQHandler
+ Default_Handler CRYPTOCELL_PPU_IRQHandler
+ Default_Handler RAM0_PPU_IRQHandler
+ Default_Handler RAM1_PPU_IRQHandler
+ Default_Handler RAM2_PPU_IRQHandler
+ Default_Handler RAM3_PPU_IRQHandler
+ Default_Handler DEBUG_PPU_IRQHandler
+ Default_Handler CPU0_CTI_IRQHandler
+ Default_Handler CPU1_CTI_IRQHandler
+
+ Default_Handler GpTimer_IRQHandler
+ Default_Handler I2C0_IRQHandler
+ Default_Handler I2C1_IRQHandler
+ Default_Handler I2S_IRQHandler
+ Default_Handler SPI_IRQHandler
+ Default_Handler QSPI_IRQHandler
+ Default_Handler UARTRX0_Handler
+ Default_Handler UARTTX0_Handler
+ Default_Handler UART0_RxTimeout_IRQHandler
+ Default_Handler UART0_ModemStatus_IRQHandler
+ Default_Handler UART0_Error_IRQHandler
+ Default_Handler UART0_IRQHandler
+ Default_Handler UARTRX1_Handler
+ Default_Handler UARTTX1_Handler
+ Default_Handler UART1_RxTimeout_IRQHandler
+ Default_Handler UART1_ModemStatus_IRQHandler
+ Default_Handler UART1_Error_IRQHandler
+ Default_Handler UART1_IRQHandler
+ Default_Handler GPIO_0_IRQHandler
+ Default_Handler GPIO_1_IRQHandler
+ Default_Handler GPIO_2_IRQHandler
+ Default_Handler GPIO_3_IRQHandler
+ Default_Handler GPIO_4_IRQHandler
+ Default_Handler GPIO_5_IRQHandler
+ Default_Handler GPIO_6_IRQHandler
+ Default_Handler GPIO_7_IRQHandler
+ Default_Handler GPIO_8_IRQHandler
+ Default_Handler GPIO_9_IRQHandler
+ Default_Handler GPIO_10_IRQHandler
+ Default_Handler GPIO_11_IRQHandler
+ Default_Handler GPIO_12_IRQHandler
+ Default_Handler GPIO_13_IRQHandler
+ Default_Handler GPIO_14_IRQHandler
+ Default_Handler GPIO_15_IRQHandler
+ Default_Handler Combined_IRQHandler
+ Default_Handler PVT_IRQHandler
+ Default_Handler PWM_0_IRQHandler
+ Default_Handler RTC_IRQHandler
+ Default_Handler GpTimer0_IRQHandler
+ Default_Handler GpTimer1_IRQHandler
+ Default_Handler PWM_1_IRQHandler
+ Default_Handler PWM_2_IRQHandler
+ Default_Handler IOMUX_IRQHandler
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_s.s b/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_s.s
index 7a9fdb1..b22ed34 100644
--- a/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_s.s
+++ b/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_s.s
@@ -1,252 +1,252 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-;
-; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
-; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
- IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors ;Core Interrupts
- DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD SecureFault_Handler ; Secure Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
- ;SSE-200 Interrupts
- DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
- DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
- DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
- DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
- DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
- DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
- DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
- DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
- DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
- DCD MPC_Handler ; 9: Secure Combined MPC Interrupt
- DCD PPC_Handler ; 10: Secure Combined PPC Interrupt
- DCD S_MSC_COMBINED_IRQHandler ; 11: Secure Combined MSC Interrupt
- DCD S_BRIDGE_ERR_IRQHandler ; 12: Secure Bridge Error Combined Interrupt
- DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
- DCD 0 ; 14: Reserved
- DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
- DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
- DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
- DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
- DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
- DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
- DCD 0 ; 21: Reserved
- DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
- DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
- DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
- DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
- DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
- DCD 0 ; 27: Reserved
- DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
- DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
- DCD 0 ; 30: Reserved
- DCD 0 ; 31: Reserved
- ;Expansion Interrupts
- DCD 0 ; 32: Reserved
- DCD GpTimer_IRQHandler ; 33: General Purpose Timer
- DCD I2C0_IRQHandler ; 34: I2C0
- DCD I2C1_IRQHandler ; 35: I2C1
- DCD I2S_IRQHandler ; 36: I2S
- DCD SPI_IRQHandler ; 37: SPI
- DCD QSPI_IRQHandler ; 38: QSPI
- DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
- DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
- DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
- DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
- DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
- DCD UART0_IRQHandler ; 44: UART0 interrupt
- DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
- DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
- DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
- DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
- DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
- DCD UART1_IRQHandler ; 50: UART0 interrupt
- DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
- DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
- DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
- DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
- DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
- DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
- DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
- DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
- DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
- DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
- DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
- DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
- DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
- DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
- DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
- DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
- DCD Combined_IRQHandler ; 67: Combined interrupt
- DCD PVT_IRQHandler ; 68: PVT sensor interrupt
- DCD 0 ; 69: Reserved
- DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
- DCD RTC_IRQHandler ; 71: RTC interrupt
- DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
- DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
- DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
- DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
- DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
-; Reset Handler
- AREA |.text|, CODE, READONLY
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- CPSID i ; Disable IRQs
- LDR R0, =SystemInit
- BLX R0
- MRS R0, control ; Get control value
- ORR R0, R0, #2 ; Select switch to PSP
- MSR control, R0
- LDR R0, =__main
- BX R0
- ENDP
-End_Of_Main
- B .
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
- MACRO
- Default_Handler $handler_name
-$handler_name PROC
- EXPORT $handler_name [WEAK]
- B .
- ENDP
- MEND
-
- Default_Handler NMI_Handler
- Default_Handler HardFault_Handler
- Default_Handler MemManage_Handler
- Default_Handler BusFault_Handler
- Default_Handler UsageFault_Handler
- Default_Handler SecureFault_Handler
- Default_Handler SVC_Handler
- Default_Handler DebugMon_Handler
- Default_Handler PendSV_Handler
- Default_Handler SysTick_Handler
-
- Default_Handler NS_WATCHDOG_RESET_IRQHandler
- Default_Handler NS_WATCHDOG_IRQHandler
- Default_Handler S32K_TIMER_IRQHandler
- Default_Handler TIMER0_IRQHandler
- Default_Handler TIMER1_IRQHandler
- Default_Handler DUALTIMER_IRQHandler
- Default_Handler MHU0_IRQHandler
- Default_Handler MHU1_IRQHandler
- Default_Handler CRYPTOCELL_IRQHandler
- Default_Handler MPC_Handler
- Default_Handler PPC_Handler
- Default_Handler S_MSC_COMBINED_IRQHandler
- Default_Handler S_BRIDGE_ERR_IRQHandler
- Default_Handler I_CACHE_INV_ERR_IRQHandler
- Default_Handler SYS_PPU_IRQHandler
- Default_Handler CPU0_PPU_IRQHandler
- Default_Handler CPU1_PPU_IRQHandler
- Default_Handler CPU0_DGB_PPU_IRQHandler
- Default_Handler CPU1_DGB_PPU_IRQHandler
- Default_Handler CRYPTOCELL_PPU_IRQHandler
- Default_Handler RAM0_PPU_IRQHandler
- Default_Handler RAM1_PPU_IRQHandler
- Default_Handler RAM2_PPU_IRQHandler
- Default_Handler RAM3_PPU_IRQHandler
- Default_Handler DEBUG_PPU_IRQHandler
- Default_Handler CPU0_CTI_IRQHandler
- Default_Handler CPU1_CTI_IRQHandler
-
- Default_Handler GpTimer_IRQHandler
- Default_Handler I2C0_IRQHandler
- Default_Handler I2C1_IRQHandler
- Default_Handler I2S_IRQHandler
- Default_Handler SPI_IRQHandler
- Default_Handler QSPI_IRQHandler
- Default_Handler UARTRX0_Handler
- Default_Handler UARTTX0_Handler
- Default_Handler UART0_RxTimeout_IRQHandler
- Default_Handler UART0_ModemStatus_IRQHandler
- Default_Handler UART0_Error_IRQHandler
- Default_Handler UART0_IRQHandler
- Default_Handler UARTRX1_Handler
- Default_Handler UARTTX1_Handler
- Default_Handler UART1_RxTimeout_IRQHandler
- Default_Handler UART1_ModemStatus_IRQHandler
- Default_Handler UART1_Error_IRQHandler
- Default_Handler UART1_IRQHandler
- Default_Handler GPIO_0_IRQHandler
- Default_Handler GPIO_1_IRQHandler
- Default_Handler GPIO_2_IRQHandler
- Default_Handler GPIO_3_IRQHandler
- Default_Handler GPIO_4_IRQHandler
- Default_Handler GPIO_5_IRQHandler
- Default_Handler GPIO_6_IRQHandler
- Default_Handler GPIO_7_IRQHandler
- Default_Handler GPIO_8_IRQHandler
- Default_Handler GPIO_9_IRQHandler
- Default_Handler GPIO_10_IRQHandler
- Default_Handler GPIO_11_IRQHandler
- Default_Handler GPIO_12_IRQHandler
- Default_Handler GPIO_13_IRQHandler
- Default_Handler GPIO_14_IRQHandler
- Default_Handler GPIO_15_IRQHandler
- Default_Handler Combined_IRQHandler
- Default_Handler PVT_IRQHandler
- Default_Handler PWM_0_IRQHandler
- Default_Handler RTC_IRQHandler
- Default_Handler GpTimer0_IRQHandler
- Default_Handler GpTimer1_IRQHandler
- Default_Handler PWM_1_IRQHandler
- Default_Handler PWM_2_IRQHandler
- Default_Handler IOMUX_IRQHandler
-
- ALIGN
-
- END
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
+; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors ;Core Interrupts
+ DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ;SSE-200 Interrupts
+ DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
+ DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
+ DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
+ DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
+ DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
+ DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
+ DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
+ DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
+ DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
+ DCD MPC_Handler ; 9: Secure Combined MPC Interrupt
+ DCD PPC_Handler ; 10: Secure Combined PPC Interrupt
+ DCD S_MSC_COMBINED_IRQHandler ; 11: Secure Combined MSC Interrupt
+ DCD S_BRIDGE_ERR_IRQHandler ; 12: Secure Bridge Error Combined Interrupt
+ DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
+ DCD 0 ; 14: Reserved
+ DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
+ DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
+ DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
+ DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
+ DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
+ DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
+ DCD 0 ; 21: Reserved
+ DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
+ DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
+ DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
+ DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
+ DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
+ DCD 0 ; 27: Reserved
+ DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
+ DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
+ DCD 0 ; 30: Reserved
+ DCD 0 ; 31: Reserved
+ ;Expansion Interrupts
+ DCD 0 ; 32: Reserved
+ DCD GpTimer_IRQHandler ; 33: General Purpose Timer
+ DCD I2C0_IRQHandler ; 34: I2C0
+ DCD I2C1_IRQHandler ; 35: I2C1
+ DCD I2S_IRQHandler ; 36: I2S
+ DCD SPI_IRQHandler ; 37: SPI
+ DCD QSPI_IRQHandler ; 38: QSPI
+ DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
+ DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
+ DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
+ DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
+ DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
+ DCD UART0_IRQHandler ; 44: UART0 interrupt
+ DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
+ DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
+ DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
+ DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
+ DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
+ DCD UART1_IRQHandler ; 50: UART0 interrupt
+ DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
+ DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
+ DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
+ DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
+ DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
+ DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
+ DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
+ DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
+ DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
+ DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
+ DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
+ DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
+ DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
+ DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
+ DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
+ DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
+ DCD Combined_IRQHandler ; 67: Combined interrupt
+ DCD PVT_IRQHandler ; 68: PVT sensor interrupt
+ DCD 0 ; 69: Reserved
+ DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
+ DCD RTC_IRQHandler ; 71: RTC interrupt
+ DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
+ DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
+ DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
+ DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
+ DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ AREA |.text|, CODE, READONLY
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ CPSID i ; Disable IRQs
+ LDR R0, =SystemInit
+ BLX R0
+ MRS R0, control ; Get control value
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+End_Of_Main
+ B .
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+ MACRO
+ Default_Handler $handler_name
+$handler_name PROC
+ EXPORT $handler_name [WEAK]
+ B .
+ ENDP
+ MEND
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler MemManage_Handler
+ Default_Handler BusFault_Handler
+ Default_Handler UsageFault_Handler
+ Default_Handler SecureFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler DebugMon_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+ Default_Handler NS_WATCHDOG_RESET_IRQHandler
+ Default_Handler NS_WATCHDOG_IRQHandler
+ Default_Handler S32K_TIMER_IRQHandler
+ Default_Handler TIMER0_IRQHandler
+ Default_Handler TIMER1_IRQHandler
+ Default_Handler DUALTIMER_IRQHandler
+ Default_Handler MHU0_IRQHandler
+ Default_Handler MHU1_IRQHandler
+ Default_Handler CRYPTOCELL_IRQHandler
+ Default_Handler MPC_Handler
+ Default_Handler PPC_Handler
+ Default_Handler S_MSC_COMBINED_IRQHandler
+ Default_Handler S_BRIDGE_ERR_IRQHandler
+ Default_Handler I_CACHE_INV_ERR_IRQHandler
+ Default_Handler SYS_PPU_IRQHandler
+ Default_Handler CPU0_PPU_IRQHandler
+ Default_Handler CPU1_PPU_IRQHandler
+ Default_Handler CPU0_DGB_PPU_IRQHandler
+ Default_Handler CPU1_DGB_PPU_IRQHandler
+ Default_Handler CRYPTOCELL_PPU_IRQHandler
+ Default_Handler RAM0_PPU_IRQHandler
+ Default_Handler RAM1_PPU_IRQHandler
+ Default_Handler RAM2_PPU_IRQHandler
+ Default_Handler RAM3_PPU_IRQHandler
+ Default_Handler DEBUG_PPU_IRQHandler
+ Default_Handler CPU0_CTI_IRQHandler
+ Default_Handler CPU1_CTI_IRQHandler
+
+ Default_Handler GpTimer_IRQHandler
+ Default_Handler I2C0_IRQHandler
+ Default_Handler I2C1_IRQHandler
+ Default_Handler I2S_IRQHandler
+ Default_Handler SPI_IRQHandler
+ Default_Handler QSPI_IRQHandler
+ Default_Handler UARTRX0_Handler
+ Default_Handler UARTTX0_Handler
+ Default_Handler UART0_RxTimeout_IRQHandler
+ Default_Handler UART0_ModemStatus_IRQHandler
+ Default_Handler UART0_Error_IRQHandler
+ Default_Handler UART0_IRQHandler
+ Default_Handler UARTRX1_Handler
+ Default_Handler UARTTX1_Handler
+ Default_Handler UART1_RxTimeout_IRQHandler
+ Default_Handler UART1_ModemStatus_IRQHandler
+ Default_Handler UART1_Error_IRQHandler
+ Default_Handler UART1_IRQHandler
+ Default_Handler GPIO_0_IRQHandler
+ Default_Handler GPIO_1_IRQHandler
+ Default_Handler GPIO_2_IRQHandler
+ Default_Handler GPIO_3_IRQHandler
+ Default_Handler GPIO_4_IRQHandler
+ Default_Handler GPIO_5_IRQHandler
+ Default_Handler GPIO_6_IRQHandler
+ Default_Handler GPIO_7_IRQHandler
+ Default_Handler GPIO_8_IRQHandler
+ Default_Handler GPIO_9_IRQHandler
+ Default_Handler GPIO_10_IRQHandler
+ Default_Handler GPIO_11_IRQHandler
+ Default_Handler GPIO_12_IRQHandler
+ Default_Handler GPIO_13_IRQHandler
+ Default_Handler GPIO_14_IRQHandler
+ Default_Handler GPIO_15_IRQHandler
+ Default_Handler Combined_IRQHandler
+ Default_Handler PVT_IRQHandler
+ Default_Handler PWM_0_IRQHandler
+ Default_Handler RTC_IRQHandler
+ Default_Handler GpTimer0_IRQHandler
+ Default_Handler GpTimer1_IRQHandler
+ Default_Handler PWM_1_IRQHandler
+ Default_Handler PWM_2_IRQHandler
+ Default_Handler IOMUX_IRQHandler
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_bl2.S b/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_bl2.S
index 06b06fd..7c1e449 100644
--- a/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_bl2.S
+++ b/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_bl2.S
@@ -1,364 +1,364 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.main
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* Core interrupts */
- .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
- .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
- .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
- .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
- .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
- .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
- .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
- .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
- .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
- .long MPC_Handler /* 9: Secure Combined MPC Interrupt */
- .long PPC_Handler /* 10: Secure Combined PPC Interrupt */
- .long S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
- .long S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
- .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
- .long 0 /* 14: Reserved */
- .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
- .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
- .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
- .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
- .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
- .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
- .long 0 /* 21: Reserved */
- .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
- .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
- .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
- .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
- .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
- .long 0 /* 27: Reserved */
- .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
- .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
- .long 0 /* 30: Reserved */
- .long 0 /* 31: Reserved */
-
- /* External interrupts */
- .long 0 /* 32: Reserved */
- .long GpTimer_IRQHandler /* 33: General Purpose Timer */
- .long I2C0_IRQHandler /* 34: I2C0 */
- .long I2C1_IRQHandler /* 35: I2C1 */
- .long I2S_IRQHandler /* 36: I2S */
- .long SPI_IRQHandler /* 37: SPI */
- .long QSPI_IRQHandler /* 38: QSPI */
- .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
- .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
- .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
- .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
- .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
- .long UART0_IRQHandler /* 44: UART0 interrupt */
- .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
- .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
- .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
- .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
- .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
- .long UART1_IRQHandler /* 50: UART0 interrupt */
- .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
- .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
- .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
- .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
- .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
- .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
- .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
- .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
- .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
- .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
- .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
- .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
- .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
- .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
- .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
- .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
- .long Combined_IRQHandler /* 67: Combined interrupt */
- .long PVT_IRQHandler /* 68: PVT sensor interrupt */
- .long 0 /* 69: Reserved */
- .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
- .long RTC_IRQHandler /* 71: RTC interrupt */
- .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
- .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
- .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
- .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
- .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
- /* Only run on core 0 */
- mov r0, #0x50000000
- add r0, #0x0001F000
- ldr r0, [r0]
- cmp r0,#0
-not_the_core_to_run_on:
- bne not_the_core_to_run_on
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
-
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- bl SystemInit
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
-
- /* Core interrupts */
- def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
- def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
- def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
- def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
- def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
- def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
- def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
- def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
- def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
- def_irq_handler MPC_Handler /* 9: Secure Combined MPC Interrupt */
- def_irq_handler PPC_Handler /* 10: Secure Combined PPC Interrupt */
- def_irq_handler S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
- def_irq_handler S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
- def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
- def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
- def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
- def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
- def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
- def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
- def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
- def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
- def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
- def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
- def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
- def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
- def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
- def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
-
- /* External interrupts */
- def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
- def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
- def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
- def_irq_handler I2S_IRQHandler /* 36: I2S */
- def_irq_handler SPI_IRQHandler /* 37: SPI */
- def_irq_handler QSPI_IRQHandler /* 38: QSPI */
- def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
- def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
- def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
- def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
- def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
- def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
- def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
- def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
- def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
- def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
- def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
- def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
- def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
- def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
- def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
- def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
- def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
- def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
- def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
- def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
- def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
- def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
- def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
- def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
- def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
- def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
- def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
- def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
- def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
- def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
- def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
- def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
- def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
- def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
- def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
- def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
- def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
-
- .end
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
+; */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long SecureFault_Handler /* Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* Core interrupts */
+ .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ .long MPC_Handler /* 9: Secure Combined MPC Interrupt */
+ .long PPC_Handler /* 10: Secure Combined PPC Interrupt */
+ .long S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
+ .long S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
+ .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ .long 0 /* 21: Reserved */
+ .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+
+ /* External interrupts */
+ .long 0 /* 32: Reserved */
+ .long GpTimer_IRQHandler /* 33: General Purpose Timer */
+ .long I2C0_IRQHandler /* 34: I2C0 */
+ .long I2C1_IRQHandler /* 35: I2C1 */
+ .long I2S_IRQHandler /* 36: I2S */
+ .long SPI_IRQHandler /* 37: SPI */
+ .long QSPI_IRQHandler /* 38: QSPI */
+ .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ .long UART0_IRQHandler /* 44: UART0 interrupt */
+ .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ .long UART1_IRQHandler /* 50: UART0 interrupt */
+ .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ .long Combined_IRQHandler /* 67: Combined interrupt */
+ .long PVT_IRQHandler /* 68: PVT sensor interrupt */
+ .long 0 /* 69: Reserved */
+ .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ .long RTC_IRQHandler /* 71: RTC interrupt */
+ .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+ /* Only run on core 0 */
+ mov r0, #0x50000000
+ add r0, #0x0001F000
+ ldr r0, [r0]
+ cmp r0,#0
+not_the_core_to_run_on:
+ bne not_the_core_to_run_on
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ bl SystemInit
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SecureFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* Core interrupts */
+ def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ def_irq_handler MPC_Handler /* 9: Secure Combined MPC Interrupt */
+ def_irq_handler PPC_Handler /* 10: Secure Combined PPC Interrupt */
+ def_irq_handler S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
+ def_irq_handler S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
+ def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+
+ /* External interrupts */
+ def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
+ def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
+ def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
+ def_irq_handler I2S_IRQHandler /* 36: I2S */
+ def_irq_handler SPI_IRQHandler /* 37: SPI */
+ def_irq_handler QSPI_IRQHandler /* 38: QSPI */
+ def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
+ def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
+ def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
+ def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
+ def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
+ def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .end
diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_ns.S b/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_ns.S
index 299cd5f..9a69d8b 100644
--- a/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_ns.S
+++ b/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_ns.S
@@ -1,356 +1,356 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.main
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* Core interrupts */
- .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
- .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
- .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
- .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
- .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
- .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
- .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
- .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
- .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
- .long 0 /* 9: Reserved */
- .long 0 /* 10: Reserved */
- .long 0 /* 11: Reserved */
- .long 0 /* 12: Reserved */
- .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
- .long 0 /* 14: Reserved */
- .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
- .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
- .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
- .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
- .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
- .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
- .long 0 /* 21: Reserved */
- .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
- .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
- .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
- .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
- .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
- .long 0 /* 27: Reserved */
- .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
- .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
- .long 0 /* 30: Reserved */
- .long 0 /* 31: Reserved */
-
- /* External interrupts */
- .long 0 /* 32: Reserved */
- .long GpTimer_IRQHandler /* 33: General Purpose Timer */
- .long I2C0_IRQHandler /* 34: I2C0 */
- .long I2C1_IRQHandler /* 35: I2C1 */
- .long I2S_IRQHandler /* 36: I2S */
- .long SPI_IRQHandler /* 37: SPI */
- .long QSPI_IRQHandler /* 38: QSPI */
- .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
- .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
- .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
- .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
- .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
- .long UART0_IRQHandler /* 44: UART0 interrupt */
- .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
- .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
- .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
- .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
- .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
- .long UART1_IRQHandler /* 50: UART0 interrupt */
- .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
- .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
- .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
- .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
- .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
- .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
- .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
- .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
- .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
- .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
- .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
- .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
- .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
- .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
- .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
- .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
- .long Combined_IRQHandler /* 67: Combined interrupt */
- .long PVT_IRQHandler /* 68: PVT sensor interrupt */
- .long 0 /* 69: Reserved */
- .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
- .long RTC_IRQHandler /* 71: RTC interrupt */
- .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
- .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
- .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
- .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
- .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
-
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- mrs r0, control /* Get control value */
- orr r0, r0, #1 /* Select switch to unprivilage mode */
- orr r0, r0, #2 /* Select switch to PSP */
- msr control, r0
- ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
- msr psp, r0
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
-
- /* Core interrupts */
- def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
- def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
- def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
- def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
- def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
- def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
- def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
- def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
- def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
- def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
- def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
- def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
- def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
- def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
- def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
- def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
- def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
- def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
- def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
- def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
- def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
- def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
- def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
-
- /* External interrupts */
- def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
- def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
- def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
- def_irq_handler I2S_IRQHandler /* 36: I2S */
- def_irq_handler SPI_IRQHandler /* 37: SPI */
- def_irq_handler QSPI_IRQHandler /* 38: QSPI */
- def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
- def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
- def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
- def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
- def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
- def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
- def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
- def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
- def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
- def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
- def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
- def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
- def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
- def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
- def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
- def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
- def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
- def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
- def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
- def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
- def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
- def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
- def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
- def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
- def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
- def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
- def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
- def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
- def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
- def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
- def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
- def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
- def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
- def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
- def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
- def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
- def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
-
- .end
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
+; */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* Core interrupts */
+ .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ .long 0 /* 9: Reserved */
+ .long 0 /* 10: Reserved */
+ .long 0 /* 11: Reserved */
+ .long 0 /* 12: Reserved */
+ .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ .long 0 /* 21: Reserved */
+ .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+
+ /* External interrupts */
+ .long 0 /* 32: Reserved */
+ .long GpTimer_IRQHandler /* 33: General Purpose Timer */
+ .long I2C0_IRQHandler /* 34: I2C0 */
+ .long I2C1_IRQHandler /* 35: I2C1 */
+ .long I2S_IRQHandler /* 36: I2S */
+ .long SPI_IRQHandler /* 37: SPI */
+ .long QSPI_IRQHandler /* 38: QSPI */
+ .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ .long UART0_IRQHandler /* 44: UART0 interrupt */
+ .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ .long UART1_IRQHandler /* 50: UART0 interrupt */
+ .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ .long Combined_IRQHandler /* 67: Combined interrupt */
+ .long PVT_IRQHandler /* 68: PVT sensor interrupt */
+ .long 0 /* 69: Reserved */
+ .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ .long RTC_IRQHandler /* 71: RTC interrupt */
+ .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ mrs r0, control /* Get control value */
+ orr r0, r0, #1 /* Select switch to unprivilage mode */
+ orr r0, r0, #2 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+ msr psp, r0
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* Core interrupts */
+ def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+
+ /* External interrupts */
+ def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
+ def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
+ def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
+ def_irq_handler I2S_IRQHandler /* 36: I2S */
+ def_irq_handler SPI_IRQHandler /* 37: SPI */
+ def_irq_handler QSPI_IRQHandler /* 38: QSPI */
+ def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
+ def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
+ def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
+ def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
+ def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
+ def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .end
diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_s.S b/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_s.S
index 152d64c..a24ac31 100644
--- a/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_s.S
+++ b/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_s.S
@@ -1,363 +1,363 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.main
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* Core interrupts */
- .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
- .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
- .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
- .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
- .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
- .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
- .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
- .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
- .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
- .long MPC_Handler /* 9: Secure Combined MPC Interrupt */
- .long PPC_Handler /* 10: Secure Combined PPC Interrupt */
- .long S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
- .long S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
- .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
- .long 0 /* 14: Reserved */
- .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
- .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
- .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
- .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
- .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
- .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
- .long 0 /* 21: Reserved */
- .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
- .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
- .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
- .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
- .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
- .long 0 /* 27: Reserved */
- .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
- .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
- .long 0 /* 30: Reserved */
- .long 0 /* 31: Reserved */
-
- /* External interrupts */
- .long 0 /* 32: Reserved */
- .long GpTimer_IRQHandler /* 33: General Purpose Timer */
- .long I2C0_IRQHandler /* 34: I2C0 */
- .long I2C1_IRQHandler /* 35: I2C1 */
- .long I2S_IRQHandler /* 36: I2S */
- .long SPI_IRQHandler /* 37: SPI */
- .long QSPI_IRQHandler /* 38: QSPI */
- .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
- .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
- .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
- .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
- .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
- .long UART0_IRQHandler /* 44: UART0 interrupt */
- .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
- .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
- .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
- .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
- .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
- .long UART1_IRQHandler /* 50: UART0 interrupt */
- .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
- .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
- .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
- .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
- .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
- .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
- .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
- .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
- .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
- .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
- .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
- .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
- .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
- .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
- .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
- .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
- .long Combined_IRQHandler /* 67: Combined interrupt */
- .long PVT_IRQHandler /* 68: PVT sensor interrupt */
- .long 0 /* 69: Reserved */
- .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
- .long RTC_IRQHandler /* 71: RTC interrupt */
- .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
- .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
- .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
- .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
- .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
-
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- cpsid i /* Disable IRQs */
- bl SystemInit
-
- mrs r0, control /* Get control value */
- orr r0, r0, #2 /* Select switch to PSP */
- msr control, r0
- ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
- msr psp, r0
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
-
- /* Core interrupts */
- def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
- def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
- def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
- def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
- def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
- def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
- def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
- def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
- def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
- def_irq_handler MPC_Handler /* 9: Secure Combined MPC Interrupt */
- def_irq_handler PPC_Handler /* 10: Secure Combined PPC Interrupt */
- def_irq_handler S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
- def_irq_handler S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
- def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
- def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
- def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
- def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
- def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
- def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
- def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
- def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
- def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
- def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
- def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
- def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
- def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
- def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
-
- /* External interrupts */
- def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
- def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
- def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
- def_irq_handler I2S_IRQHandler /* 36: I2S */
- def_irq_handler SPI_IRQHandler /* 37: SPI */
- def_irq_handler QSPI_IRQHandler /* 38: QSPI */
- def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
- def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
- def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
- def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
- def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
- def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
- def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
- def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
- def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
- def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
- def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
- def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
- def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
- def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
- def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
- def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
- def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
- def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
- def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
- def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
- def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
- def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
- def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
- def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
- def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
- def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
- def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
- def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
- def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
- def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
- def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
- def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
- def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
- def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
- def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
- def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
- def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
-
- .end
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
+; */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long SecureFault_Handler /* Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* Core interrupts */
+ .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ .long MPC_Handler /* 9: Secure Combined MPC Interrupt */
+ .long PPC_Handler /* 10: Secure Combined PPC Interrupt */
+ .long S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
+ .long S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
+ .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ .long 0 /* 21: Reserved */
+ .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+
+ /* External interrupts */
+ .long 0 /* 32: Reserved */
+ .long GpTimer_IRQHandler /* 33: General Purpose Timer */
+ .long I2C0_IRQHandler /* 34: I2C0 */
+ .long I2C1_IRQHandler /* 35: I2C1 */
+ .long I2S_IRQHandler /* 36: I2S */
+ .long SPI_IRQHandler /* 37: SPI */
+ .long QSPI_IRQHandler /* 38: QSPI */
+ .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ .long UART0_IRQHandler /* 44: UART0 interrupt */
+ .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ .long UART1_IRQHandler /* 50: UART0 interrupt */
+ .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ .long Combined_IRQHandler /* 67: Combined interrupt */
+ .long PVT_IRQHandler /* 68: PVT sensor interrupt */
+ .long 0 /* 69: Reserved */
+ .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ .long RTC_IRQHandler /* 71: RTC interrupt */
+ .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ cpsid i /* Disable IRQs */
+ bl SystemInit
+
+ mrs r0, control /* Get control value */
+ orr r0, r0, #2 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+ msr psp, r0
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SecureFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* Core interrupts */
+ def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ def_irq_handler MPC_Handler /* 9: Secure Combined MPC Interrupt */
+ def_irq_handler PPC_Handler /* 10: Secure Combined PPC Interrupt */
+ def_irq_handler S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
+ def_irq_handler S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
+ def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+
+ /* External interrupts */
+ def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
+ def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
+ def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
+ def_irq_handler I2S_IRQHandler /* 36: I2S */
+ def_irq_handler SPI_IRQHandler /* 37: SPI */
+ def_irq_handler QSPI_IRQHandler /* 38: QSPI */
+ def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
+ def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
+ def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
+ def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
+ def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
+ def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .end
diff --git a/platform/ext/target/musca_b1/spm_hal.c b/platform/ext/target/musca_b1/spm_hal.c
index 53e51d6..a3fef1f 100644
--- a/platform/ext/target/musca_b1/spm_hal.c
+++ b/platform/ext/target/musca_b1/spm_hal.c
@@ -1,324 +1,324 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#include <stdio.h>
-#include "platform/include/tfm_spm_hal.h"
-#include "spm_api.h"
-#include "spm_db.h"
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdio.h>
+#include "platform/include/tfm_spm_hal.h"
+#include "spm_api.h"
+#include "spm_db.h"
#include "tfm_platform_core_api.h"
-#include "target_cfg.h"
-#include "Driver_MPC.h"
-#include "mpu_armv8m_drv.h"
-#include "region_defs.h"
-#include "secure_utilities.h"
-
-/* Import MPC driver */
-extern ARM_DRIVER_MPC Driver_CODE_SRAM_MPC;
-
-/* Get address of memory regions to configure MPU */
-extern const struct memory_region_limits memory_regions;
-
-struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
-
-void tfm_spm_hal_init_isolation_hw(void)
-{
- /* Configures non-secure memory spaces in the target */
- sau_and_idau_cfg();
- mpc_init_cfg();
- ppc_init_cfg();
-}
-
-void tfm_spm_hal_configure_default_isolation(
- const struct tfm_spm_partition_platform_data_t *platform_data)
-{
- if (platform_data) {
- if (platform_data->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) {
- ppc_configure_to_secure(platform_data->periph_ppc_bank,
- platform_data->periph_ppc_loc);
- }
- }
-}
-
-#if TFM_LVL != 1
-
-#define MPU_REGION_VENEERS 0
-#define MPU_REGION_TFM_UNPRIV_CODE 1
-#define MPU_REGION_TFM_UNPRIV_DATA 2
-#define MPU_REGION_NS_DATA 3
-#define PARTITION_REGION_RO 4
-#define PARTITION_REGION_RW_STACK 5
-#define PARTITION_REGION_PERIPH 6
-#define PARTITION_REGION_SHARE 7
-
-REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
-REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
-REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
-REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
-REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
-REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
-
-static enum spm_err_t tfm_spm_mpu_init(void)
-{
- struct mpu_armv8m_region_cfg_t region_cfg;
-
- mpu_armv8m_clean(&dev_mpu_s);
-
- /* Veneer region */
- region_cfg.region_nr = MPU_REGION_VENEERS;
- region_cfg.region_base = memory_regions.veneer_base;
- region_cfg.region_limit = memory_regions.veneer_limit;
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- /* TFM Core unprivileged code region */
- region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_CODE;
- region_cfg.region_base =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
- region_cfg.region_limit =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- /* TFM Core unprivileged data region */
- region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_DATA;
- region_cfg.region_base =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
- region_cfg.region_limit =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- /* TFM Core unprivileged non-secure data region */
- region_cfg.region_nr = MPU_REGION_NS_DATA;
- region_cfg.region_base = NS_DATA_START;
- region_cfg.region_limit = NS_DATA_LIMIT;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return SPM_ERR_OK;
-}
-
-enum spm_err_t tfm_spm_hal_partition_sandbox_config(
- const struct tfm_spm_partition_memory_data_t *memory_data,
- const struct tfm_spm_partition_platform_data_t *platform_data)
-{
- /* This function takes a partition id and enables the
- * SPM partition for that partition
- */
-
- struct mpu_armv8m_region_cfg_t region_cfg;
-
- mpu_armv8m_disable(&dev_mpu_s);
-
- /* Configure Regions */
- if (memory_data->ro_start) {
- /* RO region */
- region_cfg.region_nr = PARTITION_REGION_RO;
- region_cfg.region_base = memory_data->ro_start;
- region_cfg.region_limit = memory_data->ro_limit;
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
-
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
- != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
- }
-
- /* RW, ZI and stack as one region */
- region_cfg.region_nr = PARTITION_REGION_RW_STACK;
- region_cfg.region_base = memory_data->rw_start;
- region_cfg.region_limit = memory_data->stack_top;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
-
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- if (platform_data) {
- /* Peripheral */
- region_cfg.region_nr = PARTITION_REGION_PERIPH;
- region_cfg.region_base = platform_data->periph_start;
- region_cfg.region_limit = platform_data->periph_limit;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
- != MPU_ARMV8M_OK) {
- return SPM_ERR_INVALID_CONFIG;
- }
-
- ppc_en_secure_unpriv(platform_data->periph_ppc_bank,
- platform_data->periph_ppc_loc);
- }
-
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return SPM_ERR_OK;
-}
-
-enum spm_err_t tfm_spm_hal_partition_sandbox_deconfig(
- const struct tfm_spm_partition_memory_data_t *memory_data,
- const struct tfm_spm_partition_platform_data_t *platform_data)
-{
- /* This function takes a partition id and disables the
- * SPM partition for that partition
- */
-
- if (platform_data) {
- /* Peripheral */
- ppc_clr_secure_unpriv(platform_data->periph_ppc_bank,
- platform_data->periph_ppc_loc);
- }
-
- mpu_armv8m_disable(&dev_mpu_s);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RO);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RW_STACK);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_PERIPH);
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return SPM_ERR_OK;
-}
-
-/**
- * Set share region to which the partition needs access
- */
-enum spm_err_t tfm_spm_hal_set_share_region(
- enum tfm_buffer_share_region_e share)
-{
- struct mpu_armv8m_region_cfg_t region_cfg;
- enum spm_err_t res = SPM_ERR_INVALID_CONFIG;
- uint32_t scratch_base =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
- uint32_t scratch_limit =
- (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
-
- mpu_armv8m_disable(&dev_mpu_s);
-
- if (share == TFM_BUFFER_SHARE_DISABLE) {
- mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
- } else {
-
- region_cfg.region_nr = PARTITION_REGION_SHARE;
- region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
- region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
- region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
- switch (share) {
- case TFM_BUFFER_SHARE_SCRATCH:
- /* Use scratch area for SP-to-SP data sharing */
- region_cfg.region_base = scratch_base;
- region_cfg.region_limit = scratch_limit;
- res = SPM_ERR_OK;
- break;
- case TFM_BUFFER_SHARE_NS_CODE:
- region_cfg.region_base = memory_regions.non_secure_partition_base;
- region_cfg.region_limit = memory_regions.non_secure_partition_limit;
- /* Only allow read access to NS code region and keep
- * exec.never attribute
- */
- region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
- res = SPM_ERR_OK;
- break;
- default:
- /* Leave res to be set to SPM_ERR_INVALID_CONFIG */
- break;
- }
- if (res == SPM_ERR_OK) {
- mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg);
- }
- }
- mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
- HARDFAULT_NMI_ENABLE);
-
- return res;
-}
-
-#endif /* TFM_LVL != 1 */
-
-void tfm_spm_hal_setup_isolation_hw(void)
-{
-#if TFM_LVL != 1
- if (tfm_spm_mpu_init() != SPM_ERR_OK) {
- ERROR_MSG("Failed to set up initial MPU configuration! Halting.");
- while (1) {
- ;
- }
- }
-#endif
-}
-
-void MPC_Handler(void)
-{
- /* Clear MPC interrupt flag and pending MPC IRQ */
- Driver_CODE_SRAM_MPC.ClearInterrupt();
- NVIC_ClearPendingIRQ(S_MPC_COMBINED_IRQn);
-
- /* Print fault message and block execution */
- LOG_MSG("Oops... MPC fault!!!");
-
- /* Inform TF-M core that isolation boundary has been violated */
- tfm_access_violation_handler();
-}
-
-void PPC_Handler(void)
-{
- /*
- * Due to an issue on the FVP, the PPC fault doesn't trigger a
- * PPC IRQ which is handled by the PPC_handler.
- * In the FVP execution, this code is not execute.
- */
-
- /* Clear PPC interrupt flag and pending PPC IRQ */
- ppc_clear_irq();
- NVIC_ClearPendingIRQ(S_PPC_COMBINED_IRQn);
-
- /* Print fault message*/
- LOG_MSG("Oops... PPC fault!!!");
-
- /* Inform TF-M core that isolation boundary has been violated */
- tfm_access_violation_handler();
-}
-
-uint32_t tfm_spm_hal_get_ns_VTOR(void)
-{
- return memory_regions.non_secure_code_start;
-}
-
-uint32_t tfm_spm_hal_get_ns_MSP(void)
-{
- return *((uint32_t *)memory_regions.non_secure_code_start);
-}
-
-uint32_t tfm_spm_hal_get_ns_entry_point(void)
-{
- return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
-}
+#include "target_cfg.h"
+#include "Driver_MPC.h"
+#include "mpu_armv8m_drv.h"
+#include "region_defs.h"
+#include "secure_utilities.h"
+
+/* Import MPC driver */
+extern ARM_DRIVER_MPC Driver_CODE_SRAM_MPC;
+
+/* Get address of memory regions to configure MPU */
+extern const struct memory_region_limits memory_regions;
+
+struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE };
+
+void tfm_spm_hal_init_isolation_hw(void)
+{
+ /* Configures non-secure memory spaces in the target */
+ sau_and_idau_cfg();
+ mpc_init_cfg();
+ ppc_init_cfg();
+}
+
+void tfm_spm_hal_configure_default_isolation(
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ if (platform_data) {
+ if (platform_data->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) {
+ ppc_configure_to_secure(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+ }
+}
+
+#if TFM_LVL != 1
+
+#define MPU_REGION_VENEERS 0
+#define MPU_REGION_TFM_UNPRIV_CODE 1
+#define MPU_REGION_TFM_UNPRIV_DATA 2
+#define MPU_REGION_NS_DATA 3
+#define PARTITION_REGION_RO 4
+#define PARTITION_REGION_RW_STACK 5
+#define PARTITION_REGION_PERIPH 6
+#define PARTITION_REGION_SHARE 7
+
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
+
+static enum spm_err_t tfm_spm_mpu_init(void)
+{
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_armv8m_clean(&dev_mpu_s);
+
+ /* Veneer region */
+ region_cfg.region_nr = MPU_REGION_VENEERS;
+ region_cfg.region_base = memory_regions.veneer_base;
+ region_cfg.region_limit = memory_regions.veneer_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged code region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_CODE;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged data region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_DATA;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$RW$$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_RO_DATA, $$ZI$$Limit);
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged non-secure data region */
+ region_cfg.region_nr = MPU_REGION_NS_DATA;
+ region_cfg.region_base = NS_DATA_START;
+ region_cfg.region_limit = NS_DATA_LIMIT;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+enum spm_err_t tfm_spm_hal_partition_sandbox_config(
+ const struct tfm_spm_partition_memory_data_t *memory_data,
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ /* This function takes a partition id and enables the
+ * SPM partition for that partition
+ */
+
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_armv8m_disable(&dev_mpu_s);
+
+ /* Configure Regions */
+ if (memory_data->ro_start) {
+ /* RO region */
+ region_cfg.region_nr = PARTITION_REGION_RO;
+ region_cfg.region_base = memory_data->ro_start;
+ region_cfg.region_limit = memory_data->ro_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
+ != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+ }
+
+ /* RW, ZI and stack as one region */
+ region_cfg.region_nr = PARTITION_REGION_RW_STACK;
+ region_cfg.region_base = memory_data->rw_start;
+ region_cfg.region_limit = memory_data->stack_top;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ if (platform_data) {
+ /* Peripheral */
+ region_cfg.region_nr = PARTITION_REGION_PERIPH;
+ region_cfg.region_base = platform_data->periph_start;
+ region_cfg.region_limit = platform_data->periph_limit;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg)
+ != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ ppc_en_secure_unpriv(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+enum spm_err_t tfm_spm_hal_partition_sandbox_deconfig(
+ const struct tfm_spm_partition_memory_data_t *memory_data,
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ /* This function takes a partition id and disables the
+ * SPM partition for that partition
+ */
+
+ if (platform_data) {
+ /* Peripheral */
+ ppc_clr_secure_unpriv(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+
+ mpu_armv8m_disable(&dev_mpu_s);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RO);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_RW_STACK);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_PERIPH);
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+/**
+ * Set share region to which the partition needs access
+ */
+enum spm_err_t tfm_spm_hal_set_share_region(
+ enum tfm_buffer_share_region_e share)
+{
+ struct mpu_armv8m_region_cfg_t region_cfg;
+ enum spm_err_t res = SPM_ERR_INVALID_CONFIG;
+ uint32_t scratch_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
+ uint32_t scratch_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
+
+ mpu_armv8m_disable(&dev_mpu_s);
+
+ if (share == TFM_BUFFER_SHARE_DISABLE) {
+ mpu_armv8m_region_disable(&dev_mpu_s, PARTITION_REGION_SHARE);
+ } else {
+
+ region_cfg.region_nr = PARTITION_REGION_SHARE;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ switch (share) {
+ case TFM_BUFFER_SHARE_SCRATCH:
+ /* Use scratch area for SP-to-SP data sharing */
+ region_cfg.region_base = scratch_base;
+ region_cfg.region_limit = scratch_limit;
+ res = SPM_ERR_OK;
+ break;
+ case TFM_BUFFER_SHARE_NS_CODE:
+ region_cfg.region_base = memory_regions.non_secure_partition_base;
+ region_cfg.region_limit = memory_regions.non_secure_partition_limit;
+ /* Only allow read access to NS code region and keep
+ * exec.never attribute
+ */
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ res = SPM_ERR_OK;
+ break;
+ default:
+ /* Leave res to be set to SPM_ERR_INVALID_CONFIG */
+ break;
+ }
+ if (res == SPM_ERR_OK) {
+ mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg);
+ }
+ }
+ mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
+ HARDFAULT_NMI_ENABLE);
+
+ return res;
+}
+
+#endif /* TFM_LVL != 1 */
+
+void tfm_spm_hal_setup_isolation_hw(void)
+{
+#if TFM_LVL != 1
+ if (tfm_spm_mpu_init() != SPM_ERR_OK) {
+ ERROR_MSG("Failed to set up initial MPU configuration! Halting.");
+ while (1) {
+ ;
+ }
+ }
+#endif
+}
+
+void MPC_Handler(void)
+{
+ /* Clear MPC interrupt flag and pending MPC IRQ */
+ Driver_CODE_SRAM_MPC.ClearInterrupt();
+ NVIC_ClearPendingIRQ(S_MPC_COMBINED_IRQn);
+
+ /* Print fault message and block execution */
+ LOG_MSG("Oops... MPC fault!!!");
+
+ /* Inform TF-M core that isolation boundary has been violated */
+ tfm_access_violation_handler();
+}
+
+void PPC_Handler(void)
+{
+ /*
+ * Due to an issue on the FVP, the PPC fault doesn't trigger a
+ * PPC IRQ which is handled by the PPC_handler.
+ * In the FVP execution, this code is not execute.
+ */
+
+ /* Clear PPC interrupt flag and pending PPC IRQ */
+ ppc_clear_irq();
+ NVIC_ClearPendingIRQ(S_PPC_COMBINED_IRQn);
+
+ /* Print fault message*/
+ LOG_MSG("Oops... PPC fault!!!");
+
+ /* Inform TF-M core that isolation boundary has been violated */
+ tfm_access_violation_handler();
+}
+
+uint32_t tfm_spm_hal_get_ns_VTOR(void)
+{
+ return memory_regions.non_secure_code_start;
+}
+
+uint32_t tfm_spm_hal_get_ns_MSP(void)
+{
+ return *((uint32_t *)memory_regions.non_secure_code_start);
+}
+
+uint32_t tfm_spm_hal_get_ns_entry_point(void)
+{
+ return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
+}
diff --git a/platform/ext/target/musca_b1/tfm_peripherals_def.h b/platform/ext/target/musca_b1/tfm_peripherals_def.h
index c8b34df..d9bcc1d 100644
--- a/platform/ext/target/musca_b1/tfm_peripherals_def.h
+++ b/platform/ext/target/musca_b1/tfm_peripherals_def.h
@@ -1,25 +1,25 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef __TFM_PERIPHERALS_DEF_H__
-#define __TFM_PERIPHERALS_DEF_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct tfm_spm_partition_platform_data_t;
-
-extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
-
-#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __TFM_PERIPHERALS_DEF_H__ */
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __TFM_PERIPHERALS_DEF_H__
+#define __TFM_PERIPHERALS_DEF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct tfm_spm_partition_platform_data_t;
+
+extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
+
+#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TFM_PERIPHERALS_DEF_H__ */