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Yann Gautierc9d75b32019-02-14 11:13:25 +01001/*
2 * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
Yann Gautier6f4572b2019-02-14 11:14:18 +01003 * Copyright (c) 2018-2019, Linaro Limited
Yann Gautierc9d75b32019-02-14 11:13:25 +01004 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef STM32MP_COMMON_H
9#define STM32MP_COMMON_H
10
Yann Gautier3f9c9782019-02-14 11:13:39 +010011#include <stdbool.h>
12
Yann Gautier6f4572b2019-02-14 11:14:18 +010013#include <arch_helpers.h>
14
Yann Gautierc9d75b32019-02-14 11:13:25 +010015/* Functions to save and get boot context address given by ROM code */
Yann Gautier3f9c9782019-02-14 11:13:39 +010016void stm32mp_save_boot_ctx_address(uintptr_t address);
17uintptr_t stm32mp_get_boot_ctx_address(void);
Yann Gautierc9d75b32019-02-14 11:13:25 +010018
Yann Gautierb2182cd2019-06-04 18:23:10 +020019bool stm32mp_is_single_core(void);
20
Yann Gautier7ae58c62019-02-14 11:01:20 +010021/* Return the base address of the DDR controller */
22uintptr_t stm32mp_ddrctrl_base(void);
23
24/* Return the base address of the DDR PHY */
25uintptr_t stm32mp_ddrphyc_base(void);
26
27/* Return the base address of the PWR peripheral */
28uintptr_t stm32mp_pwr_base(void);
29
30/* Return the base address of the RCC peripheral */
31uintptr_t stm32mp_rcc_base(void);
32
Yann Gautiere463d3f2019-05-22 19:13:51 +020033/* Check MMU status to allow spinlock use */
34bool stm32mp_lock_available(void);
35
Yann Gautier73680c22019-06-04 18:06:34 +020036/* Get IWDG platform instance ID from peripheral IO memory base address */
37uint32_t stm32_iwdg_get_instance(uintptr_t base);
38
39/* Return bitflag mask for expected IWDG configuration from OTP content */
40uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst);
41
42#if defined(IMAGE_BL2)
43/* Update OTP shadow registers with IWDG configuration from device tree */
44uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags);
45#endif
46
Yann Gautierc9d75b32019-02-14 11:13:25 +010047/*
48 * Platform util functions for the GPIO driver
49 * @bank: Target GPIO bank ID as per DT bindings
50 *
51 * Platform shall implement these functions to provide to stm32_gpio
52 * driver the resource reference for a target GPIO bank. That are
53 * memory mapped interface base address, interface offset (see below)
54 * and clock identifier.
55 *
56 * stm32_get_gpio_bank_offset() returns a bank offset that is used to
57 * check DT configuration matches platform implementation of the banks
58 * description.
59 */
60uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
61unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
62uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
63
Yann Gautierdec286d2019-06-04 18:02:37 +020064/* Print CPU information */
65void stm32mp_print_cpuinfo(void);
66
Yann Gautier10e7a9e2019-05-13 18:34:48 +020067/* Print board information */
68void stm32mp_print_boardinfo(void);
69
Yann Gautier3f9c9782019-02-14 11:13:39 +010070/*
71 * Util for clock gating and to get clock rate for stm32 and platform drivers
72 * @id: Target clock ID, ID used in clock DT bindings
73 */
74bool stm32mp_clk_is_enabled(unsigned long id);
Yann Gautier0d216802019-02-14 10:53:33 +010075void stm32mp_clk_enable(unsigned long id);
76void stm32mp_clk_disable(unsigned long id);
Yann Gautier3f9c9782019-02-14 11:13:39 +010077unsigned long stm32mp_clk_get_rate(unsigned long id);
78
Yann Gautierc9d75b32019-02-14 11:13:25 +010079/* Initialise the IO layer and register platform IO devices */
Yann Gautier3f9c9782019-02-14 11:13:39 +010080void stm32mp_io_setup(void);
Yann Gautierc9d75b32019-02-14 11:13:25 +010081
Yann Gautier6f4572b2019-02-14 11:14:18 +010082static inline uint64_t arm_cnt_us2cnt(uint32_t us)
83{
84 return ((uint64_t)us * (uint64_t)read_cntfrq()) / 1000000ULL;
85}
86
87static inline uint64_t timeout_init_us(uint32_t us)
88{
89 return read_cntpct_el0() + arm_cnt_us2cnt(us);
90}
91
92static inline bool timeout_elapsed(uint64_t expire)
93{
94 return read_cntpct_el0() > expire;
95}
96
Yann Gautierc9d75b32019-02-14 11:13:25 +010097#endif /* STM32MP_COMMON_H */