diff --git a/plat/st/stm32mp1/stm32mp1_security.c b/plat/st/stm32mp1/stm32mp1_security.c
index 0ad43e4..1cd56c6 100644
--- a/plat/st/stm32mp1/stm32mp1_security.c
+++ b/plat/st/stm32mp1/stm32mp1_security.c
@@ -14,6 +14,19 @@
 #include <dt-bindings/clock/stm32mp1-clks.h>
 #include <lib/mmio.h>
 
+#define TZC_REGION_NSEC_ALL_ACCESS_RDWR \
+	TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \
+	TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) | \
+	TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \
+	TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \
+	TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_M4_ID) | \
+	TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \
+	TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \
+	TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \
+	TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \
+	TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \
+	TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID)
+
 /*******************************************************************************
  * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
  * and allow Non-Secure masters full access.
@@ -23,31 +36,23 @@
 	unsigned long long region_base, region_top;
 	unsigned long long ddr_base = STM32MP_DDR_BASE;
 	unsigned long long ddr_size = (unsigned long long)dt_get_ddr_size();
+	unsigned long long ddr_top = ddr_base + (ddr_size - 1U);
 
 	tzc400_init(STM32MP1_TZC_BASE);
 
 	tzc400_disable_filters();
 
-	/* Region 1 set to cover all DRAM at 0xC000_0000. Apply the
+	/*
+	 * Region 1 set to cover all DRAM at 0xC000_0000. Apply the
 	 * same configuration to all filters in the TZC.
 	 */
 	region_base = ddr_base;
-	region_top = ddr_base + (ddr_size - 1U);
+	region_top = ddr_top;
 	tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
-			region_base,
-			region_top,
-			TZC_REGION_S_RDWR,
-			TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
-			TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) |
-			TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) |
-			TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) |
-			TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_M4_ID) |
-			TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) |
-			TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) |
-			TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) |
-			TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) |
-			TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) |
-			TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID));
+				region_base,
+				region_top,
+				TZC_REGION_S_NONE,
+				TZC_REGION_NSEC_ALL_ACCESS_RDWR);
 
 	/* Raise an exception if a NS device tries to access secure memory */
 	tzc400_set_action(TZC_ACTION_ERR);
@@ -69,15 +74,12 @@
 
 	tzc400_disable_filters();
 
-	/*
-	 * Region 1 set to cover Non-Secure DRAM at 0x8000_0000. Apply the
-	 * same configuration to all filters in the TZC.
-	 */
+	/* Region 1 set to cover Non-Secure DRAM at 0xC000_0000 */
 	tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
 				STM32MP_DDR_BASE,
 				STM32MP_DDR_BASE +
 				(STM32MP_DDR_MAX_SIZE - 1U),
-				TZC_REGION_S_RDWR,
+				TZC_REGION_S_NONE,
 				TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
 				TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID));