Merge changes Icf1ea76c,I9ca3f278 into integration
* changes:
imx8: Replace PLAT_IMX8* with automatic PLAT_imx8*
plat: imx8mq: Implement IMX_SIP_GET_SOC_INFO
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 1734d7e..6ffd995 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -352,28 +352,6 @@
mov x5, xzr
mov x6, sp
- /* Get the unique owning entity number */
- ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
- ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
- orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
-
- /* Load descriptor index from array of indices */
- adr x14, rt_svc_descs_indices
- ldrb w15, [x14, x16]
-
- /* Any index greater than 127 is invalid. Check bit 7. */
- tbnz w15, 7, smc_unknown
-
- /*
- * Get the descriptor using the index
- * x11 = (base + off), w15 = index
- *
- * handler = (base + off) + (index << log2(size))
- */
- adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
- lsl w10, w15, #RT_SVC_SIZE_LOG2
- ldr x15, [x11, w10, uxtw]
-
/*
* Restore the saved C runtime stack value which will become the new
* SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
@@ -400,6 +378,28 @@
mov sp, x12
+ /* Get the unique owning entity number */
+ ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
+ ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
+ orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
+
+ /* Load descriptor index from array of indices */
+ adr x14, rt_svc_descs_indices
+ ldrb w15, [x14, x16]
+
+ /* Any index greater than 127 is invalid. Check bit 7. */
+ tbnz w15, 7, smc_unknown
+
+ /*
+ * Get the descriptor using the index
+ * x11 = (base + off), w15 = index
+ *
+ * handler = (base + off) + (index << log2(size))
+ */
+ adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
+ lsl w10, w15, #RT_SVC_SIZE_LOG2
+ ldr x15, [x11, w10, uxtw]
+
/*
* Call the Secure Monitor Call handler and then drop directly into
* el3_exit() which will program any remaining architectural state
@@ -414,15 +414,14 @@
smc_unknown:
/*
- * Unknown SMC call. Populate return value with SMC_UNK, restore
- * GP registers, and return to caller.
+ * Unknown SMC call. Populate return value with SMC_UNK and call
+ * el3_exit() which will restore the remaining architectural state
+ * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET
+ * to the desired lower EL.
*/
mov x0, #SMC_UNK
- str x0, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
-#if CTX_INCLUDE_PAUTH_REGS
- bl pauth_context_restore
-#endif
- b restore_gp_registers_eret
+ str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
+ b el3_exit
smc_prohibited:
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
diff --git a/docs/Makefile b/docs/Makefile
new file mode 100644
index 0000000..eed3a08
--- /dev/null
+++ b/docs/Makefile
@@ -0,0 +1,25 @@
+#
+# Copyright (c) 2019, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line.
+SPHINXOPTS =
+SPHINXBUILD = sphinx-build
+SPHINXPROJ = TrustedFirmware-A
+SOURCEDIR = .
+BUILDDIR = build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+ @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+ @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
diff --git a/acknowledgements.rst b/docs/acknowledgements.rst
similarity index 100%
rename from acknowledgements.rst
rename to docs/acknowledgements.rst
diff --git a/docs/change-log.rst b/docs/change-log.rst
index 1aca22b..6893582 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -2417,15 +2417,15 @@
*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
.. _SDEI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
-.. _PSCI Integration Guide: psci-lib-integration-guide.rst
+.. _PSCI Integration Guide: ./getting_started/psci-lib-integration-guide.rst
.. _Developer Certificate of Origin: ../dco.txt
-.. _Contribution Guide: ../contributing.rst
-.. _Authentication framework: auth-framework.rst
-.. _Firmware Update: firmware-update.rst
-.. _TF-A Reset Design: reset-design.rst
-.. _Power Domain Topology Design: psci-pd-tree.rst
+.. _Contribution Guide: ./contributing.rst
+.. _Authentication framework: ./design/auth-framework.rst
+.. _Firmware Update: ./design/firmware-update.rst
+.. _TF-A Reset Design: ./design/reset-design.rst
+.. _Power Domain Topology Design: ./design/psci-pd-tree.rst
.. _TF-A wiki on GitHub: https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Image-Terminology
-.. _Authentication Framework: auth-framework.rst
-.. _OP-TEE Dispatcher: optee-dispatcher.rst
+.. _Authentication Framework: ./design/auth-framework.rst
+.. _OP-TEE Dispatcher: ./spd/optee-dispatcher.rst
.. _tf-issue#501: https://github.com/ARM-software/tf-issues/issues/501
.. _PR#1002: https://github.com/ARM-software/arm-trusted-firmware/pull/1002#issuecomment-312650193
diff --git a/docs/arm-sip-service.rst b/docs/components/arm-sip-service.rst
similarity index 100%
rename from docs/arm-sip-service.rst
rename to docs/components/arm-sip-service.rst
diff --git a/docs/exception-handling.rst b/docs/components/exception-handling.rst
similarity index 99%
rename from docs/exception-handling.rst
rename to docs/components/exception-handling.rst
index b7cd69d..e3684f1 100644
--- a/docs/exception-handling.rst
+++ b/docs/components/exception-handling.rst
@@ -2,8 +2,7 @@
==================================================
-.. section-numbering::
- :suffix: .
+
.. contents::
:depth: 2
@@ -117,7 +116,7 @@
.. _ehf-figure:
-.. image:: draw.io/ehf.svg
+.. image:: ../draw.io/ehf.svg
A priority level is *active* when a handler at that priority level is currently
executing in EL3, or has delegated the execution to a lower EL. For interrupts,
diff --git a/docs/firmware-update.rst b/docs/components/firmware-update.rst
similarity index 99%
rename from docs/firmware-update.rst
rename to docs/components/firmware-update.rst
index 1f07f76..f3ad6af 100644
--- a/docs/firmware-update.rst
+++ b/docs/components/firmware-update.rst
@@ -2,8 +2,7 @@
=================================================
-.. section-numbering::
- :suffix: .
+
.. contents::
@@ -403,7 +402,7 @@
*Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.*
.. _Trusted Board Boot: ./trusted-board-boot.rst
-.. _Porting Guide: ./porting-guide.rst
+.. _Porting Guide: ../getting_started/porting-guide.rst
.. _here: https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Image-Terminology
.. _Authentication Framework Design: ./auth-framework.rst
.. _Universally Unique Identifier: https://tools.ietf.org/rfc/rfc4122.txt
diff --git a/docs/components/index.rst b/docs/components/index.rst
new file mode 100644
index 0000000..f1904c0
--- /dev/null
+++ b/docs/components/index.rst
@@ -0,0 +1,18 @@
+Components
+==========
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+ :numbered:
+
+ spd/index
+ arm-sip-service
+ exception-handling
+ firmware-update
+ platform-interrupt-controller-API
+ ras
+ romlib-design
+ sdei
+ secure-partition-manager-design
+ xlat-tables-lib-v2-design
diff --git a/docs/platform-interrupt-controller-API.rst b/docs/components/platform-interrupt-controller-API.rst
similarity index 98%
rename from docs/platform-interrupt-controller-API.rst
rename to docs/components/platform-interrupt-controller-API.rst
index ad68709..42d92be 100644
--- a/docs/platform-interrupt-controller-API.rst
+++ b/docs/components/platform-interrupt-controller-API.rst
@@ -1,8 +1,7 @@
Platform Interrupt Controller API documentation
===============================================
-.. section-numbering::
- :suffix: .
+
.. contents::
@@ -10,7 +9,7 @@
abstracts the runtime configuration and control of interrupt controller from the
generic code. The mandatory APIs are described in the `porting guide`__.
-.. __: porting-guide.rst#interrupt-management-framework-in-bl31
+.. __: ../getting_started/porting-guide.rst#interrupt-management-framework-in-bl31
Function: unsigned int plat_ic_get_running_priority(void); [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/ras.rst b/docs/components/ras.rst
similarity index 98%
rename from docs/ras.rst
rename to docs/components/ras.rst
index ac4d019..f329fb0 100644
--- a/docs/ras.rst
+++ b/docs/components/ras.rst
@@ -1,8 +1,7 @@
RAS support in Trusted Firmware-A
=================================
-.. section-numbering::
- :suffix: .
+
.. contents::
:depth: 2
@@ -45,7 +44,7 @@
.. _ras-figure:
-.. image:: draw.io/ras.svg
+.. image:: ../draw.io/ras.svg
See more on `Engaging the RAS framework`_.
@@ -56,7 +55,7 @@
Uncontainable Errors, Double Fault, and errors rising from EL3 execution. Please
refer to the porting guide for the `RAS platform API descriptions`__.
-.. __: porting-guide.rst#external-abort-handling-and-ras-support
+.. __: ../getting_started/porting-guide.rst#external-abort-handling-and-ras-support
Registering RAS error records
-----------------------------
diff --git a/docs/romlib-design.rst b/docs/components/romlib-design.rst
similarity index 100%
rename from docs/romlib-design.rst
rename to docs/components/romlib-design.rst
diff --git a/docs/sdei.rst b/docs/components/sdei.rst
similarity index 97%
rename from docs/sdei.rst
rename to docs/components/sdei.rst
index c524817..aca1ccb 100644
--- a/docs/sdei.rst
+++ b/docs/components/sdei.rst
@@ -1,9 +1,5 @@
-Software Delegated Exception Interface
-======================================
-
-
-.. section-numbering::
- :suffix: .
+SDEI: Software Delegated Exception Interface
+============================================
.. contents::
:depth: 2
@@ -33,7 +29,7 @@
at EL2 and an event dispatch resulting from the triggering of a bound interrupt.
A commentary is provided below:
-.. image:: plantuml/sdei_general.svg
+.. image:: ../plantuml/sdei_general.svg
As part of initialisation, the SDEI client binds a Non-secure interrupt [1], and
the SDEI dispatcher returns a platform dynamic event number [2]. The client then
@@ -241,7 +237,7 @@
The following figure depicts a scenario involving explicit dispatch of SDEI
event. A commentary is provided below:
-.. image:: plantuml/sdei_explicit_dispatch.svg
+.. image:: ../plantuml/sdei_explicit_dispatch.svg
As part of initialisation, the SDEI client registers a handler for a platform
event [1], enables the event [3], and unmasks the current PE [5]. Note that,
@@ -376,4 +372,4 @@
*Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.*
.. _SDEI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
-.. _SDEI porting requirements: porting-guide.rst#sdei-porting-requirements
+.. _SDEI porting requirements: ../getting_started/porting-guide.rst#sdei-porting-requirements
diff --git a/docs/secure-partition-manager-design.rst b/docs/components/secure-partition-manager-design.rst
similarity index 99%
rename from docs/secure-partition-manager-design.rst
rename to docs/components/secure-partition-manager-design.rst
index 3c301d0..2c32eba 100644
--- a/docs/secure-partition-manager-design.rst
+++ b/docs/components/secure-partition-manager-design.rst
@@ -2,8 +2,7 @@
Secure Partition Manager Design
*******************************
-.. section-numbering::
- :suffix: .
+
.. contents::
@@ -820,5 +819,5 @@
.. _SDEI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
-.. |Image 1| image:: diagrams/secure_sw_stack_tos.png
-.. |Image 2| image:: diagrams/secure_sw_stack_sp.png
+.. |Image 1| image:: ../diagrams/secure_sw_stack_tos.png
+.. |Image 2| image:: ../diagrams/secure_sw_stack_sp.png
diff --git a/docs/components/spd/index.rst b/docs/components/spd/index.rst
new file mode 100644
index 0000000..e03bfe3
--- /dev/null
+++ b/docs/components/spd/index.rst
@@ -0,0 +1,11 @@
+Secure Payload Dispatcher (SPD)
+===============================
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+ :numbered:
+
+ optee-dispatcher
+ tlk-dispatcher
+ trusty-dispatcher
diff --git a/docs/spd/optee-dispatcher.rst b/docs/components/spd/optee-dispatcher.rst
similarity index 100%
rename from docs/spd/optee-dispatcher.rst
rename to docs/components/spd/optee-dispatcher.rst
diff --git a/docs/spd/tlk-dispatcher.rst b/docs/components/spd/tlk-dispatcher.rst
similarity index 100%
rename from docs/spd/tlk-dispatcher.rst
rename to docs/components/spd/tlk-dispatcher.rst
diff --git a/docs/spd/trusty-dispatcher.rst b/docs/components/spd/trusty-dispatcher.rst
similarity index 100%
rename from docs/spd/trusty-dispatcher.rst
rename to docs/components/spd/trusty-dispatcher.rst
diff --git a/docs/xlat-tables-lib-v2-design.rst b/docs/components/xlat-tables-lib-v2-design.rst
similarity index 96%
rename from docs/xlat-tables-lib-v2-design.rst
rename to docs/components/xlat-tables-lib-v2-design.rst
index dbed7f8..d55f010 100644
--- a/docs/xlat-tables-lib-v2-design.rst
+++ b/docs/components/xlat-tables-lib-v2-design.rst
@@ -2,8 +2,7 @@
=================================
-.. section-numbering::
- :suffix: .
+
.. contents::
@@ -416,13 +415,13 @@
*Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.*
-.. _lib/xlat_tables_v2: ../lib/xlat_tables_v2
-.. _lib/xlat_tables: ../lib/xlat_tables
-.. _xlat_tables_v2.h: ../include/lib/xlat_tables/xlat_tables_v2.h
-.. _xlat_tables_context.c: ../lib/xlat_tables_v2/xlat_tables_context.c
-.. _xlat_tables_core.c: ../lib/xlat_tables_v2/xlat_tables_core.c
-.. _xlat_tables_utils.c: ../lib/xlat_tables_v2/xlat_tables_utils.c
-.. _aarch32/xlat_tables_arch.c: ../lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
-.. _aarch64/xlat_tables_arch.c: ../lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
-.. _Porting Guide: porting-guide.rst
-.. |Alignment Example| image:: ./diagrams/xlat_align.png?raw=true
+.. _lib/xlat_tables_v2: ../../lib/xlat_tables_v2
+.. _lib/xlat_tables: ../../lib/xlat_tables
+.. _xlat_tables_v2.h: ../../include/lib/xlat_tables/xlat_tables_v2.h
+.. _xlat_tables_context.c: ../../lib/xlat_tables_v2/xlat_tables_context.c
+.. _xlat_tables_core.c: ../../lib/xlat_tables_v2/xlat_tables_core.c
+.. _xlat_tables_utils.c: ../../lib/xlat_tables_v2/xlat_tables_utils.c
+.. _aarch32/xlat_tables_arch.c: ../../lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
+.. _aarch64/xlat_tables_arch.c: ../../lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
+.. _Porting Guide: ../getting_started/porting-guide.rst
+.. |Alignment Example| image:: ../diagrams/xlat_align.png?raw=true
diff --git a/docs/conf.py b/docs/conf.py
new file mode 100644
index 0000000..0fcc50d
--- /dev/null
+++ b/docs/conf.py
@@ -0,0 +1,72 @@
+# -*- coding: utf-8 -*-
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+# Configuration file for the Sphinx documentation builder.
+#
+# See the options documentation at http://www.sphinx-doc.org/en/master/config
+
+# -- Project information -----------------------------------------------------
+
+project = 'Trusted Firmware-A'
+
+version = '2.1'
+release = version # We don't need these to be distinct
+
+
+# -- General configuration ---------------------------------------------------
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = []
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# The suffix(es) of source filenames.
+source_suffix = '.rst'
+
+# The master toctree document.
+master_doc = 'index'
+
+# The language for content autogenerated by Sphinx. Refer to documentation
+# for a list of supported languages.
+#
+# This is also used if you do content translation via gettext catalogs.
+# Usually you set "language" from the command line for these cases.
+language = None
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This pattern also affects html_static_path and html_extra_path .
+exclude_patterns = []
+
+# The name of the Pygments (syntax highlighting) style to use.
+pygments_style = 'sphinx'
+
+
+# -- Options for HTML output -------------------------------------------------
+
+# Don't show the "Built with Sphinx" footer
+html_show_sphinx = False
+
+# Don't show copyright info in the footer (we have this content in the page)
+html_show_copyright = False
+
+# The theme to use for HTML and HTML Help pages. See the documentation for
+# a list of builtin themes.
+html_theme = "sphinx_rtd_theme"
+
+# The logo to display in the sidebar
+html_logo = 'resources/TrustedFirmware-Logo_standard-white.png'
+
+# Options for the "sphinx-rtd-theme" theme
+html_theme_options = {
+ 'collapse_navigation': False, # Can expand and collapse sidebar entries
+ 'prev_next_buttons_location': 'both', # Top and bottom of the page
+ 'style_external_links': True # Display an icon next to external links
+}
diff --git a/docs/contents.rst b/docs/contents.rst
deleted file mode 100644
index 4b3f74f..0000000
--- a/docs/contents.rst
+++ /dev/null
@@ -1,165 +0,0 @@
-Trusted Firmware-A Documentation Contents
-=========================================
-
-This document serves as a list of the documentation that is included with the
-Trusted Firmware-A source.
-
-Introduction
-------------
-
-`About Trusted Firmware-A`_
-
-Getting Started
----------------
-
-`Frequently-Asked Questions (FAQ)`_
-
-`Image Terminology`_
-
-`Porting Guide`_
-
-`User Guide`_
-
-Contributing
-------------
-
-`Coding Style and Guidelines`_
-
-`Contributor Acknowledgements`_
-
-`Contributor's Guide`_
-
-`License`_
-
-`Maintainers`_
-
-Processes and Policies
-----------------------
-
-`Platform Compatibility Policy`_
-
-`Release Processes`_
-
-Secure Payload Dispatch
------------------------
-
-`OP-TEE Dispatcher`_
-
-`Trusted Little Kernel (TLK) Dispatcher`_
-
-`Trusty Dispatcher`_
-
-System Design and Components
-----------------------------
-
-`Arm CPU Specific Build Macros`_
-
-`Arm SiP Services`_
-
-`Authentication Framework & Chain of Trust`_
-
-`CPU Reset`_
-
-`EL3 Runtime Service Writer’s Guide`_
-
-`Exception Handling Framework`_
-
-`Firmware Design Overview`_
-
-`Firmware Update (FWU)`_
-
-`Interrupt Management Framework`_
-
-`Library at ROM`_
-
-`Platform Interrupt Controller API`_
-
-`PSCI Library Integration Guide for Armv8-A AArch32 systems`_
-
-`PSCI Power Domain Tree design`_
-
-`Reliability, Availability, and Serviceability (RAS) Extensions`_
-
-`Secure Partition Manager`_
-
-`Software Delegated Exception Interface`_
-
-`Translation (XLAT) Tables Library`_
-
-`Trusted Board Boot Design Guide`_
-
-Performance and Testing
------------------------
-
-`PSCI Performance Measurements on Arm Juno Development Platform`_
-
-Security and Advisories
------------------------
-
-`Security Processes`_
-
-`TFV-1`_
-
-`TFV-2`_
-
-`TFV-3`_
-
-`TFV-4`_
-
-`TFV-5`_
-
-`TFV-6`_
-
-`TFV-7`_
-
-`TFV-8`_
-
-Other Documents
----------------
-
-`Change Log`_
-
-.. _About Trusted Firmware-A: ../readme.rst
-.. _Frequently-Asked Questions (FAQ): ./frequently-asked-questions.rst
-.. _Image Terminology: ./image-terminology.rst
-.. _Porting Guide: ./porting-guide.rst
-.. _User Guide: ./user-guide.rst
-.. _Coding Style and Guidelines: ./coding-guidelines.rst
-.. _Contributor Acknowledgements: ../acknowledgements.rst
-.. _`Contributor's Guide`: ../contributing.rst
-.. _License: ../license.rst
-.. _Maintainers: ../maintainers.rst
-.. _Platform Compatibility Policy: ./platform-compatibility-policy.rst
-.. _Release Processes: ./release-information.rst
-.. _Arm SiP Services: ./arm-sip-service.rst
-.. _Exception Handling Framework: ./exception-handling.rst
-.. _Firmware Update (FWU): ./firmware-update.rst
-.. _Interrupt Management Framework: ./interrupt-framework-design.rst
-.. _Library at ROM: ./romlib-design.rst
-.. _Platform Interrupt Controller API: ./platform-interrupt-controller-API.rst
-.. _`Reliability, Availability, and Serviceability (RAS) Extensions`: ./ras.rst
-.. _Secure Partition Manager: ./secure-partition-manager-design.rst
-.. _Software Delegated Exception Interface: ./sdei.rst
-.. _Translation (XLAT) Tables Library: ./xlat-tables-lib-v2-design.rst
-.. _OP-TEE Dispatcher: ./spd/optee-dispatcher.rst
-.. _Trusted Little Kernel (TLK) Dispatcher: ./spd/tlk-dispatcher.rst
-.. _Trusty Dispatcher: ./spd/trusty-dispatcher.rst
-.. _Arm CPU Specific Build Macros: ./cpu-specific-build-macros.rst
-.. _`Authentication Framework & Chain of Trust`: ./auth-framework.rst
-.. _CPU Reset: ./reset-design.rst
-.. _`EL3 Runtime Service Writer’s Guide`: ./rt-svc-writers-guide.rst
-.. _Firmware Design Overview: ./firmware-design.rst
-.. _PSCI Library Integration Guide for Armv8-A AArch32 systems: ./psci-lib-integration-guide.rst
-.. _PSCI Power Domain Tree design: ./psci-pd-tree.rst
-.. _Trusted Board Boot Design Guide: ./trusted-board-boot.rst
-.. _PSCI Performance Measurements on Arm Juno Development Platform: ./psci-performance-juno.rst
-.. _Security Processes: ./security-center.rst
-.. _Change Log: ./change-log.rst
-.. _TFV-1: ./security_advisories/security-advisory-tfv-1.rst
-.. _TFV-2: ./security_advisories/security-advisory-tfv-2.rst
-.. _TFV-3: ./security_advisories/security-advisory-tfv-3.rst
-.. _TFV-4: ./security_advisories/security-advisory-tfv-4.rst
-.. _TFV-5: ./security_advisories/security-advisory-tfv-5.rst
-.. _TFV-6: ./security_advisories/security-advisory-tfv-6.rst
-.. _TFV-7: ./security_advisories/security-advisory-tfv-7.rst
-.. _TFV-8: ./security_advisories/security-advisory-tfv-8.rst
diff --git a/docs/auth-framework.rst b/docs/design/auth-framework.rst
similarity index 99%
rename from docs/auth-framework.rst
rename to docs/design/auth-framework.rst
index 0142fbd..1bc5015 100644
--- a/docs/auth-framework.rst
+++ b/docs/design/auth-framework.rst
@@ -2,8 +2,7 @@
============================
-.. section-numbering::
- :suffix: .
+
.. contents::
@@ -968,5 +967,5 @@
*Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.*
.. _Trusted Board Boot: ./trusted-board-boot.rst
-.. _Platform Porting Guide: ./porting-guide.rst
+.. _Platform Porting Guide: ../getting_started/porting-guide.rst
.. _TBBR-Client specification: https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
diff --git a/docs/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
similarity index 99%
rename from docs/cpu-specific-build-macros.rst
rename to docs/design/cpu-specific-build-macros.rst
index 493e07e..d099ebe 100644
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -2,8 +2,7 @@
=============================
-.. section-numbering::
- :suffix: .
+
.. contents::
diff --git a/docs/firmware-design.rst b/docs/design/firmware-design.rst
similarity index 99%
rename from docs/firmware-design.rst
rename to docs/design/firmware-design.rst
index 8384c9c..e7107ba 100644
--- a/docs/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -2,8 +2,7 @@
=========================
-.. section-numbering::
- :suffix: .
+
.. contents::
@@ -2665,19 +2664,19 @@
*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
.. _Reset Design: ./reset-design.rst
-.. _Porting Guide: ./porting-guide.rst
+.. _Porting Guide: ../getting_started/porting-guide.rst
.. _Firmware Update: ./firmware-update.rst
.. _PSCI PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
.. _SMC calling convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
-.. _PSCI Library integration guide: ./psci-lib-integration-guide.rst
+.. _PSCI Library integration guide: ../getting_started/psci-lib-integration-guide.rst
.. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
-.. _here: ./psci-lib-integration-guide.rst
+.. _here: ../getting_started/psci-lib-integration-guide.rst
.. _cpu-specific-build-macros.rst: ./cpu-specific-build-macros.rst
.. _CPUBM: ./cpu-specific-build-macros.rst
.. _Arm ARM: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html
-.. _User Guide: ./user-guide.rst
+.. _User Guide: ../getting_started/user-guide.rst
.. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
.. _TF-A Interrupt Management Design guide: ./interrupt-framework-design.rst
.. _Xlat_tables design: xlat-tables-lib-v2-design.rst
diff --git a/docs/design/index.rst b/docs/design/index.rst
new file mode 100644
index 0000000..a51a4eb
--- /dev/null
+++ b/docs/design/index.rst
@@ -0,0 +1,15 @@
+System Design
+=============
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+ :numbered:
+
+ auth-framework
+ cpu-specific-build-macros
+ firmware-design
+ interrupt-framework-design
+ psci-pd-tree
+ reset-design
+ trusted-board-boot
diff --git a/docs/interrupt-framework-design.rst b/docs/design/interrupt-framework-design.rst
similarity index 99%
rename from docs/interrupt-framework-design.rst
rename to docs/design/interrupt-framework-design.rst
index 58130cd..e4ec65a 100644
--- a/docs/interrupt-framework-design.rst
+++ b/docs/design/interrupt-framework-design.rst
@@ -2,8 +2,7 @@
====================================================
-.. section-numbering::
- :suffix: .
+
.. contents::
@@ -1018,7 +1017,7 @@
*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
-.. _Porting Guide: ./porting-guide.rst
+.. _Porting Guide: ../getting_started/porting-guide.rst
.. _SMC calling convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
.. |Image 1| image:: diagrams/sec-int-handling.png?raw=true
diff --git a/docs/psci-pd-tree.rst b/docs/design/psci-pd-tree.rst
similarity index 99%
rename from docs/psci-pd-tree.rst
rename to docs/design/psci-pd-tree.rst
index 9653725..2e2163a 100644
--- a/docs/psci-pd-tree.rst
+++ b/docs/design/psci-pd-tree.rst
@@ -2,8 +2,7 @@
=============================
-.. section-numbering::
- :suffix: .
+
.. contents::
diff --git a/docs/reset-design.rst b/docs/design/reset-design.rst
similarity index 94%
rename from docs/reset-design.rst
rename to docs/design/reset-design.rst
index 44ab609..1473851 100644
--- a/docs/reset-design.rst
+++ b/docs/design/reset-design.rst
@@ -2,8 +2,7 @@
===============================
-.. section-numbering::
- :suffix: .
+
.. contents::
@@ -158,9 +157,9 @@
*Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.*
.. _Firmware Design: firmware-design.rst
-.. _User Guide: user-guide.rst
+.. _User Guide: ../getting_started/user-guide.rst
-.. |Default reset code flow| image:: diagrams/default_reset_code.png?raw=true
-.. |Reset code flow with programmable reset address| image:: diagrams/reset_code_no_boot_type_check.png?raw=true
-.. |Reset code flow with single CPU released out of reset| image:: diagrams/reset_code_no_cpu_check.png?raw=true
-.. |Reset code flow with programmable reset address and single CPU released out of reset| image:: diagrams/reset_code_no_checks.png?raw=true
+.. |Default reset code flow| image:: ../diagrams/default_reset_code.png?raw=true
+.. |Reset code flow with programmable reset address| image:: ../diagrams/reset_code_no_boot_type_check.png?raw=true
+.. |Reset code flow with single CPU released out of reset| image:: ../diagrams/reset_code_no_cpu_check.png?raw=true
+.. |Reset code flow with programmable reset address and single CPU released out of reset| image:: ../diagrams/reset_code_no_checks.png?raw=true
diff --git a/docs/trusted-board-boot.rst b/docs/design/trusted-board-boot.rst
similarity index 98%
rename from docs/trusted-board-boot.rst
rename to docs/design/trusted-board-boot.rst
index 3ba9636..ae21bf0 100644
--- a/docs/trusted-board-boot.rst
+++ b/docs/design/trusted-board-boot.rst
@@ -2,8 +2,7 @@
===============================
-.. section-numbering::
- :suffix: .
+
.. contents::
@@ -234,7 +233,7 @@
.. _Firmware Update: firmware-update.rst
.. _X.509 v3: https://tools.ietf.org/rfc/rfc5280.txt
-.. _User Guide: user-guide.rst
+.. _User Guide: ../getting_started/user-guide.rst
.. _Auth Framework: auth-framework.rst
.. _TBBR-client: https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
.. _Trusted Board Boot Requirements (TBBR): `TBBR-client`_
diff --git a/docs/image-terminology.rst b/docs/getting_started/image-terminology.rst
similarity index 100%
rename from docs/image-terminology.rst
rename to docs/getting_started/image-terminology.rst
diff --git a/docs/getting_started/index.rst b/docs/getting_started/index.rst
new file mode 100644
index 0000000..23608f8
--- /dev/null
+++ b/docs/getting_started/index.rst
@@ -0,0 +1,13 @@
+Getting Started
+===============
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+ :numbered:
+
+ user-guide
+ image-terminology
+ porting-guide
+ psci-lib-integration-guide
+ rt-svc-writers-guide
diff --git a/docs/porting-guide.rst b/docs/getting_started/porting-guide.rst
similarity index 99%
rename from docs/porting-guide.rst
rename to docs/getting_started/porting-guide.rst
index 6244a63..cad8b5c 100644
--- a/docs/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -2,13 +2,9 @@
================================
-.. section-numbering::
- :suffix: .
.. contents::
---------------
-
Introduction
------------
@@ -2366,7 +2362,7 @@
See also: `Interrupt Controller Abstraction APIs`__.
-.. __: platform-interrupt-controller-API.rst
+.. __: ../design/platform-interrupt-controller-API.rst
Function : plat_interrupt_type_to_line() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -2493,7 +2489,7 @@
The actual interrupt number shall be extracted from this raw value using the API
`plat_ic_get_interrupt_id()`__.
-.. __: platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional
+.. __: ../design/platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional
This function in Arm standard platforms using GICv2, reads the *Interrupt
Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
diff --git a/docs/psci-lib-integration-guide.rst b/docs/getting_started/psci-lib-integration-guide.rst
similarity index 97%
rename from docs/psci-lib-integration-guide.rst
rename to docs/getting_started/psci-lib-integration-guide.rst
index 555d347..c8cf3f3 100644
--- a/docs/psci-lib-integration-guide.rst
+++ b/docs/getting_started/psci-lib-integration-guide.rst
@@ -2,8 +2,6 @@
==========================================================
-.. section-numbering::
- :suffix: .
.. contents::
@@ -127,7 +125,7 @@
----------------------
The PSCI library implements the `PSCI Specification`_. The interfaces
-to this library are declared in ``psci.h`` and are as listed below:
+to this library are declared in ``psci_lib.h`` and are as listed below:
.. code:: c
@@ -186,7 +184,7 @@
This function is to be called by the primary CPU during cold boot before
any other interface to the PSCI library. It takes ``lib_args``, a const pointer
to ``psci_lib_args_t``, as the argument. The ``psci_lib_args_t`` is a versioned
-structure and is declared in ``psci.h`` header as follows:
+structure and is declared in ``psci_lib.h`` header as follows:
.. code:: c
@@ -200,9 +198,9 @@
The first field ``h``, of ``param_header_t`` type, provides the version
information. The second field ``mailbox_ep`` is the warm boot entrypoint address
and is used to configure the platform mailbox. Helper macros are provided in
-psci.h to construct the ``lib_args`` argument statically or during runtime. Prior
-to calling the ``psci_setup()`` interface, the platform setup for cold boot
-must have completed. Major actions performed by this interface are:
+``psci_lib.h`` to construct the ``lib_args`` argument statically or during
+runtime. Prior to calling the ``psci_setup()`` interface, the platform setup for
+cold boot must have completed. Major actions performed by this interface are:
- Initializes architecture.
- Initializes PSCI power domain and state coordination data structures.
@@ -550,5 +548,5 @@
.. _SMCCC: https://silver.arm.com/download/ARM_and_AMBA_Architecture/AR570-DA-80002-r0p0-00rel0/ARM_DEN0028A_SMC_Calling_Convention.pdf
.. _PSCI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
.. _PSCI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
-.. _Porting Guide: porting-guide.rst
-.. _Firmware Design: ./firmware-design.rst
+.. _Porting Guide: ../getting_started/porting-guide.rst
+.. _Firmware Design: ../design/firmware-design.rst
diff --git a/docs/rt-svc-writers-guide.rst b/docs/getting_started/rt-svc-writers-guide.rst
similarity index 97%
rename from docs/rt-svc-writers-guide.rst
rename to docs/getting_started/rt-svc-writers-guide.rst
index 4d4066c..f4d786c 100644
--- a/docs/rt-svc-writers-guide.rst
+++ b/docs/getting_started/rt-svc-writers-guide.rst
@@ -2,13 +2,9 @@
=====================================================
-.. section-numbering::
- :suffix: .
.. contents::
---------------
-
Introduction
------------
@@ -307,9 +303,9 @@
.. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
-.. _Firmware Design: ./firmware-design.rst
-.. _services: ../services
-.. _lib/psci: ../lib/psci
-.. _runtime_svc.h: ../include/common/runtime_svc.h
-.. _smccc.h: ../include/lib/smccc.h
-.. _std_svc_setup.c: ../services/std_svc/std_svc_setup.c
+.. _Firmware Design: ../designb_documents/firmware-design.rst
+.. _services: ../../services
+.. _lib/psci: ../../lib/psci
+.. _runtime_svc.h: ../../include/common/runtime_svc.h
+.. _smccc.h: ../../include/lib/smccc.h
+.. _std_svc_setup.c: ../../services/std_svc/std_svc_setup.c
diff --git a/docs/user-guide.rst b/docs/getting_started/user-guide.rst
similarity index 99%
rename from docs/user-guide.rst
rename to docs/getting_started/user-guide.rst
index b67a82d..3cc5f3c 100644
--- a/docs/user-guide.rst
+++ b/docs/getting_started/user-guide.rst
@@ -2,8 +2,7 @@
=============================
-.. section-numbering::
- :suffix: .
+
.. contents::
@@ -1668,7 +1667,7 @@
Arm FVPs without shifted affinities, and that do not support threaded CPU cores
(64-bit host machine only).
-The FVP models used are Version 11.5 Build 33, unless otherwise stated.
+The FVP models used are Version 11.6 Build 45, unless otherwise stated.
- ``FVP_Base_AEMv8A-AEMv8A``
- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
@@ -1688,14 +1687,14 @@
- ``FVP_Base_Cortex-A73x4``
- ``FVP_Base_Cortex-A75x4``
- ``FVP_Base_Cortex-A76x4``
-- ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
-- ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
-- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
+- ``FVP_Base_Cortex-A76AEx4``
+- ``FVP_Base_Cortex-A76AEx8``
+- ``FVP_Base_Neoverse-N1x4``
- ``FVP_Base_Deimos``
- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
- ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
- ``FVP_RD_E1Edge`` (Version 11.3 build 42)
-- ``FVP_RD_N1Edge`` (Version 11.3 build 42)
+- ``FVP_RD_N1Edge``
- ``Foundation_Platform``
The latest version of the AArch32 build of TF-A has been tested on the following
diff --git a/docs/index.rst b/docs/index.rst
new file mode 100644
index 0000000..8eecb3c
--- /dev/null
+++ b/docs/index.rst
@@ -0,0 +1,314 @@
+Trusted Firmware-A Documentation
+================================
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+
+ Home<self>
+ getting_started/index
+ process/index
+ components/index
+ design/index
+ plat/index
+ perf/index
+ security_advisories/index
+ change-log
+ maintainers
+ acknowledgements
+ license
+
+Trusted Firmware-A (TF-A) provides a reference implementation of secure world
+software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing
+at Exception Level 3 (EL3). It implements various Arm interface standards,
+such as:
+
+- The `Power State Coordination Interface (PSCI)`_
+- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)`_
+- `SMC Calling Convention`_
+- `System Control and Management Interface (SCMI)`_
+- `Software Delegated Exception Interface (SDEI)`_
+
+Where possible, the code is designed for reuse or porting to other Armv7-A and
+Armv8-A model and hardware platforms.
+
+This release provides a suitable starting point for productization of secure
+world boot and runtime firmware, in either the AArch32 or AArch64 execution
+states.
+
+Users are encouraged to do their own security validation, including penetration
+testing, on any secure world code derived from TF-A.
+
+Arm will continue development in collaboration with interested parties to
+provide a full reference implementation of Secure Monitor code and Arm standards
+to the benefit of all developers working with Armv7-A and Armv8-A TrustZone
+technology.
+
+Functionality
+-------------
+
+- Initialization of the secure world, for example exception vectors, control
+ registers and interrupts for the platform.
+
+- Library support for CPU specific reset and power down sequences. This
+ includes support for errata workarounds and the latest Arm DynamIQ CPUs.
+
+- Drivers to enable standard initialization of Arm System IP, for example
+ Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI),
+ Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone
+ Controller (TZC).
+
+- A generic `SCMI`_ driver to interface with conforming power controllers, for
+ example the Arm System Control Processor (SCP).
+
+- SMC (Secure Monitor Call) handling, conforming to the `SMC Calling
+ Convention`_ using an EL3 runtime services framework.
+
+- `PSCI`_ library support for CPU, cluster and system power management
+ use-cases.
+ This library is pre-integrated with the AArch64 EL3 Runtime Software, and
+ is also suitable for integration with other AArch32 EL3 Runtime Software,
+ for example an AArch32 Secure OS.
+
+- A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate `PSCI`_ library
+ integration with AArch32 EL3 Runtime Software.
+
+- Secure Monitor library code such as world switching, EL1 context management
+ and interrupt routing.
+ When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
+ AArch64 EL3 Runtime Software must be integrated with a Secure Payload
+ Dispatcher (SPD) component to customize the interaction with the SP.
+
+- A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP
+ interaction with PSCI.
+
+- SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_
+ and `Trusty Secure OS`_.
+
+- A Trusted Board Boot implementation, conforming to all mandatory TBBR
+ requirements. This includes image authentication, Firmware Update (or
+ recovery mode), and packaging of the various firmware images into a
+ Firmware Image Package (FIP).
+
+- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of
+ its hardware Root of Trust and crypto acceleration services.
+
+- Reliability, Availability, and Serviceability (RAS) functionality, including
+
+ - A Secure Partition Manager (SPM) to manage Secure Partitions in
+ Secure-EL0, which can be used to implement simple management and
+ security services.
+
+ - An SDEI dispatcher to route interrupt-based SDEI events.
+
+ - An Exception Handling Framework (EHF) that allows dispatching of EL3
+ interrupts to their registered handlers, to facilitate firmware-first
+ error handling.
+
+- A dynamic configuration framework that enables each of the firmware images
+ to be configured at runtime if required by the platform. It also enables
+ loading of a hardware configuration (for example, a kernel device tree)
+ as part of the FIP, to be passed through the firmware stages.
+
+- Support for alternative boot flows, for example to support platforms where
+ the EL3 Runtime Software is loaded using other firmware or a separate
+ secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
+ at EL3.
+
+- Support for the GCC, LLVM and Arm Compiler 6 toolchains.
+
+- Support for combining several libraries into a "romlib" image that may be
+ shared across images to reduce memory footprint. The romlib image is stored
+ in ROM but is accessed through a jump-table that may be stored
+ in read-write memory, allowing for the library code to be patched.
+
+- A prototype implementation of a Secure Partition Manager (SPM) that is based
+ on the SPCI Alpha 1 and SPRT draft specifications.
+
+- Support for ARMv8.3 pointer authentication in the normal and secure worlds.
+ The use of pointer authentication in the normal world is enabled whenever
+ architectural support is available, without the need for additional build
+ flags. Use of pointer authentication in the secure world remains an
+ experimental configuration at this time and requires the ``ENABLE_PAUTH``
+ build flag to be set.
+
+- Position-Independent Executable (PIE) support. Initially for BL31 only, with
+ further support to be added in a future release.
+
+For a full description of functionality and implementation details, please
+see the `Firmware Design`_ and supporting documentation. The `Change Log`_
+provides details of changes made since the last release.
+
+Platforms
+---------
+
+Various AArch32 and AArch64 builds of this release have been tested on r0, r1
+and r2 variants of the `Juno Arm Development Platform`_.
+
+The latest version of the AArch64 build of TF-A has been tested on the following
+Arm FVPs without shifted affinities, and that do not support threaded CPU cores
+(64-bit host machine only).
+
+The FVP models used are Version 11.5 Build 33, unless otherwise stated.
+
+- ``FVP_Base_AEMv8A-AEMv8A``
+- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
+- ``FVP_Base_RevC-2xAEMv8A``
+- ``FVP_Base_Cortex-A32x4``
+- ``FVP_Base_Cortex-A35x4``
+- ``FVP_Base_Cortex-A53x4``
+- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
+- ``FVP_Base_Cortex-A55x4``
+- ``FVP_Base_Cortex-A57x1-A53x1``
+- ``FVP_Base_Cortex-A57x2-A53x4``
+- ``FVP_Base_Cortex-A57x4-A53x4``
+- ``FVP_Base_Cortex-A57x4``
+- ``FVP_Base_Cortex-A72x4-A53x4``
+- ``FVP_Base_Cortex-A72x4``
+- ``FVP_Base_Cortex-A73x4-A53x4``
+- ``FVP_Base_Cortex-A73x4``
+- ``FVP_Base_Cortex-A75x4``
+- ``FVP_Base_Cortex-A76x4``
+- ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
+- ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
+- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
+- ``FVP_Base_Deimos``
+- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
+- ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
+- ``FVP_RD_E1Edge`` (Version 11.3 build 42)
+- ``FVP_RD_N1Edge`` (Version 11.3 build 42)
+- ``Foundation_Platform``
+
+The latest version of the AArch32 build of TF-A has been tested on the following
+Arm FVPs without shifted affinities, and that do not support threaded CPU cores
+(64-bit host machine only).
+
+- ``FVP_Base_AEMv8A-AEMv8A``
+- ``FVP_Base_Cortex-A32x4``
+
+NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities.
+
+The Foundation FVP can be downloaded free of charge. The Base FVPs can be
+licensed from Arm. See the `Arm FVP website`_.
+
+All the above platforms have been tested with `Linaro Release 18.04`_.
+
+This release also contains the following platform support:
+
+- Allwinner sun50i_a64 and sun50i_h6
+- Amlogic Meson S905 (GXBB)
+- Arm Juno Software Development Platform
+- Arm Neoverse N1 System Development Platform (N1SDP)
+- Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
+- Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP
+- Arm SGI-575 and SGM-775
+- Arm Versatile Express FVP
+- HiKey, HiKey960 and Poplar boards
+- Intel Stratix 10 SoC FPGA
+- Marvell Armada 3700 and 8K
+- MediaTek MT6795 and MT8173 SoCs
+- NVIDIA T132, T186 and T210 SoCs
+- NXP QorIQ LS1043A, i.MX8MM, i.MX8MQ, i.MX8QX, i.MX8QM and i.MX7Solo WaRP7
+- QEMU
+- Raspberry Pi 3
+- Renesas R-Car Generation 3
+- RockChip RK3328, RK3368 and RK3399 SoCs
+- Socionext UniPhier SoC family and SynQuacer SC2A11 SoCs
+- STMicroelectronics STM32MP1
+- Texas Instruments K3 SoCs
+- Xilinx Versal and Zynq UltraScale + MPSoC
+
+Still to come
+-------------
+
+- Support for additional platforms.
+
+- Refinements to Position Independent Executable (PIE) support.
+
+- Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT
+ specifications continue to evolve.
+
+- Documentation enhancements.
+
+- Ongoing support for new architectural features, CPUs and System IP.
+
+- Ongoing support for new Arm system architecture specifications.
+
+- Ongoing security hardening, optimization and quality improvements.
+
+For a full list of detailed issues in the current code, please see the `Change
+Log`_ and the `issue tracker`_.
+
+Getting started
+---------------
+
+See the `User Guide`_ for instructions on how to download, install, build and
+use TF-A with the Arm `FVP`_\ s.
+
+See the `Firmware Design`_ for information on how TF-A works.
+
+See the `Porting Guide`_ as well for information about how to use this
+software on another Armv7-A or Armv8-A platform.
+
+See the `Contributing Guidelines`_ for information on how to contribute to this
+project and the `Acknowledgments`_ file for a list of contributors to the
+project.
+
+IRC channel
+~~~~~~~~~~~
+
+Development discussion takes place on the #trusted-firmware-a channel
+on the Freenode IRC network. This is not an official support channel.
+If you have an issue to raise, please use the `issue tracker`_.
+
+Feedback and support
+~~~~~~~~~~~~~~~~~~~~
+
+Arm welcomes any feedback on TF-A. If you think you have found a security
+vulnerability, please report this using the process defined in the TF-A
+`Security Center`_. For all other feedback, please use the
+`issue tracker`_.
+
+Arm licensees may contact Arm directly via their partner managers.
+
+--------------
+
+*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
+
+.. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile
+.. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php
+.. _Power State Coordination Interface (PSCI): PSCI_
+.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
+.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
+.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
+.. _System Control and Management Interface (SCMI): SCMI_
+.. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
+.. _Software Delegated Exception Interface (SDEI): SDEI_
+.. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
+.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
+.. _Arm FVP website: FVP_
+.. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms
+.. _Linaro Release 18.04: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease18.04
+.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
+.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
+.. _Trusty Secure OS: https://source.android.com/security/trusty
+.. _trustedfirmware.org: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+.. _issue tracker: https://issues.trustedfirmware.org
+.. _Security Center: ./docs/security-center.rst
+.. _license: ./license.rst
+.. _Contributing Guidelines: ./contributing.rst
+.. _Acknowledgments: ./acknowledgements.rst
+.. _Firmware Design: ./docs/firmware-design.rst
+.. _Change Log: ./docs/change-log.rst
+.. _User Guide: ./docs/user-guide.rst
+.. _Porting Guide: ./docs/porting-guide.rst
+.. _FreeBSD: http://www.freebsd.org
+.. _SCC: http://www.simple-cc.org/
+.. _Security Advisory TFV-1: ./docs/security_advisories/security-advisory-tfv-1.rst
+.. _Security Advisory TFV-2: ./docs/security_advisories/security-advisory-tfv-2.rst
+.. _Security Advisory TFV-3: ./docs/security_advisories/security-advisory-tfv-3.rst
+.. _Security Advisory TFV-4: ./docs/security_advisories/security-advisory-tfv-4.rst
+.. _Security Advisory TFV-5: ./docs/security_advisories/security-advisory-tfv-5.rst
+.. _Security Advisory TFV-6: ./docs/security_advisories/security-advisory-tfv-6.rst
+.. _Security Advisory TFV-7: ./docs/security_advisories/security-advisory-tfv-7.rst
+.. _Security Advisory TFV-8: ./docs/security_advisories/security-advisory-tfv-8.rst
diff --git a/docs/license.rst b/docs/license.rst
new file mode 100644
index 0000000..b62286f
--- /dev/null
+++ b/docs/license.rst
@@ -0,0 +1,80 @@
+License
+=======
+
+The software is provided under a BSD-3-Clause license (below). Contributions to
+this project are accepted under the same license with developer sign-off as
+described in the :ref:`contributor_guide`.
+
+::
+
+ Copyright (c) [XXXX-]YYYY, <OWNER>. All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without modification,
+ are permitted provided that the following conditions are met:
+
+ - Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+ - Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+ - Neither the name of Arm nor the names of its contributors may be used to
+ endorse or promote products derived from this software without specific
+ prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+SPDX Identifiers
+----------------
+
+Individual files contain the following tag instead of the full license text.
+
+::
+
+ SPDX-License-Identifier: BSD-3-Clause
+
+This enables machine processing of license information based on the SPDX
+License Identifiers that are here available: http://spdx.org/licenses/
+
+
+Other Projects
+--------------
+
+This project contains code from other projects as listed below. The original
+license text is included in those source files.
+
+- The libc source code is derived from `FreeBSD`_ and `SCC`_. FreeBSD uses
+ various BSD licenses, including BSD-3-Clause and BSD-2-Clause. The SCC code
+ is used under the BSD-3-Clause license with the author's permission.
+
+- The libfdt source code is disjunctively dual licensed
+ (GPL-2.0+ OR BSD-2-Clause). It is used by this project under the terms of
+ the BSD-2-Clause license. Any contributions to this code must be made under
+ the terms of both licenses.
+
+- The LLVM compiler-rt source code is disjunctively dual licensed
+ (NCSA OR MIT). It is used by this project under the terms of the NCSA
+ license (also known as the University of Illinois/NCSA Open Source License),
+ which is a permissive license compatible with BSD-3-Clause. Any
+ contributions to this code must be made under the terms of both licenses.
+
+- The zlib source code is licensed under the Zlib license, which is a
+ permissive license compatible with BSD-3-Clause.
+
+- Some STMicroelectronics platform source code is disjunctively dual licensed
+ (GPL-2.0+ OR BSD-3-Clause). It is used by this project under the terms of the
+ BSD-3-Clause license. Any contributions to this code must be made under the
+ terms of both licenses.
+
+.. _FreeBSD: http://www.freebsd.org
+.. _SCC: http://www.simple-cc.org/
\ No newline at end of file
diff --git a/maintainers.rst b/docs/maintainers.rst
similarity index 100%
rename from maintainers.rst
rename to docs/maintainers.rst
diff --git a/docs/perf/index.rst b/docs/perf/index.rst
new file mode 100644
index 0000000..50833b8
--- /dev/null
+++ b/docs/perf/index.rst
@@ -0,0 +1,9 @@
+Performance & Testing
+=====================
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+ :numbered:
+
+ psci-performance-juno
diff --git a/docs/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst
similarity index 100%
rename from docs/psci-performance-juno.rst
rename to docs/perf/psci-performance-juno.rst
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
new file mode 100644
index 0000000..3a917f3
--- /dev/null
+++ b/docs/plat/index.rst
@@ -0,0 +1,29 @@
+Platform Ports
+==============
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+ :numbered:
+
+ allwinner
+ fvp_ve
+ imx8
+ imx8m
+ intel-stratix10
+ ls1043a
+ meson-gxbb
+ meson-gxl
+ mt8183
+ nvidia-tegra
+ poplar
+ qemu
+ rcar-gen3
+ rockchip
+ rpi3
+ socionext-uniphier
+ stm32mp1
+ synquacer
+ ti-k3
+ warp7
+ xilinx-zynqmp
diff --git a/docs/marvell/build.txt b/docs/plat/marvell/build.txt
similarity index 100%
rename from docs/marvell/build.txt
rename to docs/plat/marvell/build.txt
diff --git a/docs/marvell/misc/mvebu-a8k-addr-map.txt b/docs/plat/marvell/misc/mvebu-a8k-addr-map.txt
similarity index 100%
rename from docs/marvell/misc/mvebu-a8k-addr-map.txt
rename to docs/plat/marvell/misc/mvebu-a8k-addr-map.txt
diff --git a/docs/marvell/misc/mvebu-amb.txt b/docs/plat/marvell/misc/mvebu-amb.txt
similarity index 100%
rename from docs/marvell/misc/mvebu-amb.txt
rename to docs/plat/marvell/misc/mvebu-amb.txt
diff --git a/docs/marvell/misc/mvebu-ccu.txt b/docs/plat/marvell/misc/mvebu-ccu.txt
similarity index 100%
rename from docs/marvell/misc/mvebu-ccu.txt
rename to docs/plat/marvell/misc/mvebu-ccu.txt
diff --git a/docs/marvell/misc/mvebu-io-win.txt b/docs/plat/marvell/misc/mvebu-io-win.txt
similarity index 100%
rename from docs/marvell/misc/mvebu-io-win.txt
rename to docs/plat/marvell/misc/mvebu-io-win.txt
diff --git a/docs/marvell/misc/mvebu-iob.txt b/docs/plat/marvell/misc/mvebu-iob.txt
similarity index 100%
rename from docs/marvell/misc/mvebu-iob.txt
rename to docs/plat/marvell/misc/mvebu-iob.txt
diff --git a/docs/marvell/porting.txt b/docs/plat/marvell/porting.txt
similarity index 100%
rename from docs/marvell/porting.txt
rename to docs/plat/marvell/porting.txt
diff --git a/docs/plat/rpi3.rst b/docs/plat/rpi3.rst
index a22bfc6..122b1de 100644
--- a/docs/plat/rpi3.rst
+++ b/docs/plat/rpi3.rst
@@ -1,8 +1,7 @@
Trusted Firmware-A for Raspberry Pi 3
=====================================
-.. section-numbering::
- :suffix: .
+
.. contents::
diff --git a/docs/coding-guidelines.rst b/docs/process/coding-guidelines.rst
similarity index 99%
rename from docs/coding-guidelines.rst
rename to docs/process/coding-guidelines.rst
index e8f365b..644f828 100644
--- a/docs/coding-guidelines.rst
+++ b/docs/process/coding-guidelines.rst
@@ -1,8 +1,7 @@
Trusted Firmware-A Coding Guidelines
====================================
-.. section-numbering::
- :suffix: .
+
.. contents::
diff --git a/contributing.rst b/docs/process/contributing.rst
similarity index 100%
rename from contributing.rst
rename to docs/process/contributing.rst
diff --git a/docs/frequently-asked-questions.rst b/docs/process/faq.rst
similarity index 100%
rename from docs/frequently-asked-questions.rst
rename to docs/process/faq.rst
diff --git a/docs/process/index.rst b/docs/process/index.rst
new file mode 100644
index 0000000..91f1beb
--- /dev/null
+++ b/docs/process/index.rst
@@ -0,0 +1,14 @@
+Processes & Policies
+====================
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+ :numbered:
+
+ release-information
+ security-center
+ platform-compatibility-policy
+ coding-guidelines
+ contributing
+ faq
diff --git a/docs/platform-compatibility-policy.rst b/docs/process/platform-compatibility-policy.rst
similarity index 95%
rename from docs/platform-compatibility-policy.rst
rename to docs/process/platform-compatibility-policy.rst
index 6bab447..e977e63 100644
--- a/docs/platform-compatibility-policy.rst
+++ b/docs/process/platform-compatibility-policy.rst
@@ -2,8 +2,7 @@
==================================
-.. section-numbering::
- :suffix: .
+
.. contents::
@@ -40,6 +39,6 @@
*Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.*
-.. _Porting Guide: ./porting-guide.rst
+.. _Porting Guide: ../getting_started/porting-guide.rst
.. _Release information: https://github.com/ARM-software/arm-trusted-firmware/wiki/TF-A-Release-information#removal-of-deprecated-interfaces
.. _tf-issue: https://github.com/ARM-software/tf-issues/issues
diff --git a/docs/release-information.rst b/docs/process/release-information.rst
similarity index 100%
rename from docs/release-information.rst
rename to docs/process/release-information.rst
diff --git a/docs/security-center.rst b/docs/process/security-center.rst
similarity index 100%
rename from docs/security-center.rst
rename to docs/process/security-center.rst
diff --git a/docs/security-reporting.asc b/docs/process/security-reporting.asc
similarity index 100%
rename from docs/security-reporting.asc
rename to docs/process/security-reporting.asc
diff --git a/docs/resources/TrustedFirmware-Logo_standard-white.png b/docs/resources/TrustedFirmware-Logo_standard-white.png
new file mode 100644
index 0000000..e7bff71
--- /dev/null
+++ b/docs/resources/TrustedFirmware-Logo_standard-white.png
Binary files differ
diff --git a/docs/security_advisories/index.rst b/docs/security_advisories/index.rst
new file mode 100644
index 0000000..ce2c843
--- /dev/null
+++ b/docs/security_advisories/index.rst
@@ -0,0 +1,16 @@
+Security Advisories
+===================
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+ :numbered:
+
+ security-advisory-tfv-1.rst
+ security-advisory-tfv-2.rst
+ security-advisory-tfv-3.rst
+ security-advisory-tfv-4.rst
+ security-advisory-tfv-5.rst
+ security-advisory-tfv-6.rst
+ security-advisory-tfv-7.rst
+ security-advisory-tfv-8.rst
diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h
index 452afbc..f982b57 100644
--- a/include/plat/arm/board/common/board_css_def.h
+++ b/include/plat/arm/board/common/board_css_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -54,7 +54,7 @@
* Required platform porting definitions common to all ARM CSS-based
* development platforms
*/
-
+#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
/* UART related constants */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 62623c1..69a9959 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -148,7 +148,7 @@
#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
ARM_DRAM1_SIZE - 1)
-#define ARM_DRAM2_BASE UL(0x880000000)
+#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE
#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
ARM_DRAM2_SIZE - 1)
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 2038f31..a0babb0 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -49,11 +49,31 @@
b cpu_rev_var_ls
endfunc check_errata_1043202
+/* --------------------------------------------------
+ * Disable speculative loads if Neoverse N1 supports
+ * SSBS.
+ *
+ * Shall clobber: x0.
+ * --------------------------------------------------
+ */
+func neoverse_n1_disable_speculative_loads
+ /* Check if the PE implements SSBS */
+ mrs x0, id_aa64pfr1_el1
+ tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
+ b.eq 1f
+
+ /* Disable speculative loads */
+ msr SSBS, xzr
+ isb
+
+1:
+ ret
+endfunc neoverse_n1_disable_speculative_loads
+
func neoverse_n1_reset_func
mov x19, x30
- /* Disables speculative loads */
- msr SSBS, xzr
+ bl neoverse_n1_disable_speculative_loads
/* Forces all cacheable atomic instructions to be near */
mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index 12fdfa8..7a3a51e 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -24,9 +24,9 @@
Q :=
endif
+LDFLAGS := --gc-sections -O1
ifeq ($(DEBUG),1)
- CFLAGS := -g
- LDFLAGS := -g --gc-sections -O1 -Map=$(MAPFILE)
+ LDFLAGS += -Map=$(MAPFILE)
endif
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 6856a28..2313ab0 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -48,6 +48,7 @@
/* No SCP in FVP */
#define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0)
+#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#define PLAT_ARM_DRAM2_SIZE UL(0x80000000)
/*
diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h
index 1870442..1b21c79 100644
--- a/plat/arm/board/fvp_ve/include/platform_def.h
+++ b/plat/arm/board/fvp_ve/include/platform_def.h
@@ -25,7 +25,7 @@
#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
ARM_DRAM1_SIZE - 1)
-#define ARM_DRAM2_BASE UL(0x880000000)
+#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE
#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
ARM_DRAM2_SIZE - 1)
@@ -230,6 +230,7 @@
#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
#define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
+#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#define PLAT_ARM_DRAM2_SIZE ULL(0x80000000)
/*
diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h
index adb957e..0964f56 100644
--- a/plat/arm/board/n1sdp/include/platform_def.h
+++ b/plat/arm/board/n1sdp/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,6 +24,7 @@
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
+#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
#define PLAT_ARM_DRAM2_SIZE ULL(0x780000000)
#if CSS_USE_SCMI_SDS_DRIVER
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index 0442945..f5ce4d2 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -127,12 +127,12 @@
*/
mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val);
-#ifdef PLAT_juno
+#if defined(PLAT_juno) || defined(PLAT_n1sdp)
/*
* Initialize CNTFRQ register in Non-secure CNTBase frame.
- * This is only required for Juno, because it doesn't follow ARM ARM
- * in that the value updated in CNTFRQ is not reflected in
- * CNTBASEN_CNTFRQ. Hence update the value manually.
+ * This is only required for Juno and N1SDP, because they do not
+ * follow ARM ARM in that the value updated in CNTFRQ is not
+ * reflected in CNTBASEN_CNTFRQ. Hence update the value manually.
*/
mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val);
#endif
diff --git a/readme.rst b/readme.rst
index fc03555..2737d5c 100644
--- a/readme.rst
+++ b/readme.rst
@@ -176,7 +176,7 @@
Arm FVPs without shifted affinities, and that do not support threaded CPU cores
(64-bit host machine only).
-The FVP models used are Version 11.5 Build 33, unless otherwise stated.
+The FVP models used are Version 11.6 Build 45, unless otherwise stated.
- ``FVP_Base_AEMv8A-AEMv8A``
- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
@@ -196,14 +196,14 @@
- ``FVP_Base_Cortex-A73x4``
- ``FVP_Base_Cortex-A75x4``
- ``FVP_Base_Cortex-A76x4``
-- ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
-- ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
-- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
+- ``FVP_Base_Cortex-A76AEx4``
+- ``FVP_Base_Cortex-A76AEx8``
+- ``FVP_Base_Neoverse-N1x4``
- ``FVP_Base_Deimos``
- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
- ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
- ``FVP_RD_E1Edge`` (Version 11.3 build 42)
-- ``FVP_RD_N1Edge`` (Version 11.3 build 42)
+- ``FVP_RD_N1Edge``
- ``Foundation_Platform``
The latest version of the AArch32 build of TF-A has been tested on the following
