tree 8fd89f21b24dfb9a0b6c00c0aa137547d50cfcd5
parent 7395a725ae74de70820d7b126ba1af727f39e263
author Soby Mathew <soby.mathew@arm.com> 1411384526 +0100
committer Soby Mathew <soby.mathew@arm.com> 1414604336 +0000

Optimize barrier usage during Cortex-A57 power down

This the patch replaces the DSB SY with DSB ISH
after disabling L2 prefetches during the Cortex-A57
power down sequence.

Change-Id: I048d12d830c1b974b161224eff079fb9f8ecf52d