| commit | 1b491eead580d7849a45a38f2c6a935a5d8d1160 | [log] [tgz] |
|---|---|---|
| author | Elyes Haouas <ehaouas@noos.fr> | Mon Feb 13 09:14:48 2023 +0100 |
| committer | Manish Pandey <manish.pandey2@arm.com> | Tue May 09 15:57:12 2023 +0100 |
| tree | 5085dd0af7deed3a5a52dbcd82a78aa5cd96e888 | |
| parent | 8557d491b6dbd6cbf27cc2ae6425f6cb29ca2c35 [diff] [blame] |
fix(tree): correct some typos found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
diff --git a/drivers/renesas/common/pfc_regs.h b/drivers/renesas/common/pfc_regs.h index 4187733..36084f5 100644 --- a/drivers/renesas/common/pfc_regs.h +++ b/drivers/renesas/common/pfc_regs.h
@@ -146,10 +146,10 @@ #define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U) #define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU) -/* Pin functon base address */ +/* Pin function base address */ #define PFC_BASE (0xE6060000U) -/* Pin functon registers */ +/* Pin function registers */ #define PFC_PMMR (PFC_BASE + 0x0000U) #define PFC_GPSR0 (PFC_BASE + 0x0100U) #define PFC_GPSR1 (PFC_BASE + 0x0104U)