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review.trustedfirmware.org / sandbox / arthur / trustedfirmware-a / b1a2c51a0820fce803431e6ee5bd078bb1a65b0d / plat / intel / soc / agilex
  1. 7931d33 feat(intel): platform enablement for Agilex5 SoC FPGA by Jit Loon Lim · 2 years, 3 months ago
  2. 6197dc9 feat(intel): restructure sys mgr for Agilex by Jit Loon Lim · 2 years, 3 months ago
  3. 1b491ee fix(tree): correct some typos by Elyes Haouas · 2 years, 6 months ago
  4. 5f06bff fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · 2 years, 8 months ago
  5. 02a9d70 feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 3 years, 1 month ago
  6. 42d4d3b refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 2 years, 9 months ago
  7. 4687021 feat(intel): extending to support SMMU in FCS by Sieu Mun Tang · 2 years, 10 months ago
  8. 3905f57 feat(intel): setup FPGA interface for Agilex by Jit Loon Lim · 3 years, 2 months ago
  9. e6c0389 fix(intel): fix pinmux handoff bug on Agilex by Jit Loon Lim · 3 years, 2 months ago
  10. 8e53b2f fix(intel): fix UART baud rate and clock by Sieu Mun Tang · 3 years, 1 month ago
  11. 7a756a5 build(agilex): platform changes for verifying gpt header crc by Rohit Ner · 3 years, 3 months ago
  12. 58690cd fix(intel): remove redundant NOC header declarations by Sieu Mun Tang · 3 years, 3 months ago
  13. ad47f14 feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands by Sieu Mun Tang · 3 years, 3 months ago
  14. f0f631f Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · 3 years, 3 months ago
  15. f65bdf3 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 3 years, 4 months ago
  16. 11f4f03 feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · 3 years, 3 months ago
  17. ae19fef feat(intel): enable firewall for OCRAM in BL31 by Abdul Halim, Muhammad Hadi Asyrafi · 5 years ago
  18. afa0b1a feat(intel): create source file for firewall configuration by Abdul Halim, Muhammad Hadi Asyrafi · 5 years ago
  19. bc1a573 fix(intel): refactor NOC header by Abdul Halim, Muhammad Hadi Asyrafi · 5 years ago
  20. 447e699 feat(intel): add macro to switch between different UART PORT by Boon Khai Ng · 4 years ago
  21. f571183 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · 3 years, 5 months ago
  22. c703d75 fix(intel): fix ECC Double Bit Error handling by Sieu Mun Tang · 3 years, 5 months ago
  23. 1f1c020 build(intel): define a macro for SIMICS build by Abdul Halim, Muhammad Hadi Asyrafi · 5 years ago
  24. 286b96f build(intel): initial commit for crypto driver by Sieu Mun Tang · 3 years, 5 months ago
  25. a78c6c9 Merge "fix(intel): assert if bl_mem_params is NULL pointer" into integration by Madhukar Pappireddy · 3 years, 5 months ago
  26. 35fe7f4 fix(intel): assert if bl_mem_params is NULL pointer by Siew Chin Lim · 4 years, 2 months ago
  27. 000267b fix(intel): enable HPS QSPI access by default by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 10 months ago
  28. 5cb7fc8 plat/intel: do not keep mmc_device_info in stack by Yann Gautier · 4 years, 5 months ago
  29. d96e7cd intel: mailbox: Ensure time out duration is predictive by Chee Hong Ang · 5 years ago
  30. 7f56f24 intel: clear 'PLAT_SEC_ENTRY' in early platform setup by Chee Hong Ang · 5 years ago
  31. 5a32a03 intel: platform: Include GICv2 makefile by Abdul Halim, Muhammad Hadi Asyrafi · 5 years ago
  32. e734ecd plat: intel: Add FPGAINTF configuration to when configuring pinmux by Tien Hock Loh · 5 years ago
  33. aea772d plat: intel: set DRVSEL and SMPLSEL for DWMMC by Tien Hock Loh · 5 years ago
  34. fa09d54 plat: intel: Fix clock configuration bugs by Tien Hock Loh · 5 years ago
  35. 351d358 Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration by Sandrine Bailleux · 5 years ago
  36. 98964f0 16550: Use generic console_t data structure by Andre Przywara · 6 years ago
  37. d603fd3 intel: Enable EMAC PHY in Intel FPGA platform by Tien Hock, Loh · 6 years ago
  38. 78fcbd6 Merge "intel: Change boot source selection" into integration by Sandrine Bailleux · 5 years ago
  39. e1f97d9 intel: Extend SiP service to support mailbox's RSU by Hadi Asyrafi · 6 years ago
  40. 77fc469 intel: Change boot source selection by Hadi Asyrafi · 6 years ago
  41. 2a1e086 intel: agilex: Enable uboot BL31 loading by Hadi Asyrafi · 6 years ago
  42. f2decc7 intel: Add function to check fpga readiness by Hadi Asyrafi · 6 years ago
  43. 9c8f3af intel: Add bridge control for FPGA reconfig by Hadi Asyrafi · 6 years ago
  44. 20335ca intel: System Manager refactoring by Hadi Asyrafi · 6 years ago
  45. 391eeee intel: Refactor reset manager driver by Hadi Asyrafi · 6 years ago
  46. 3dcb94d intel: Enable bridge access in Intel platform by Hadi Asyrafi · 6 years ago
  47. 222519a intel: Modify non secure access function by Hadi Asyrafi · 6 years ago
  48. bc3579b Merge "intel: Fix memory calibration" into integration by Manish Pandey · 6 years ago
  49. 7a05f06 Remove redundant declarations. by Madhukar Pappireddy · 6 years ago
  50. 3d9f726 intel: Fix memory calibration by Hadi Asyrafi · 6 years ago
  51. 1520b5d intel: Refactor common platform code [5/5] by Hadi Asyrafi · 6 years ago
  52. c76d423 intel: Refactor common platform code [4/5] by Hadi Asyrafi · 6 years ago
  53. d09adcb intel: Refactor common platform code [3/5] by Hadi Asyrafi · 6 years ago
  54. e9b5e36 intel: Refactor common platform code [2/5] by Hadi Asyrafi · 6 years ago
  55. 328718f intel: Refactor common platform code [1/5] by Hadi Asyrafi · 6 years ago
  56. b90f207 Invalidate dcache build option for bl2 entry at EL3 by Hadi Asyrafi · 6 years ago
  57. afac968 intel: agilex: Fix psci power domain off by Hadi Asyrafi · 6 years ago
  58. 3441952 Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration by Paul Beesley · 6 years ago
  59. 24d16a2 intel: agilex: HMC driver calculate DDR size by Hadi Asyrafi · 6 years ago
  60. 960a12b intel: agilex: Clear PLL lostlock bypass mode by Hadi Asyrafi · 6 years ago
  61. d1b6013 Merge "intel: agilex: Fix memory controller driver" into integration by Paul Beesley · 6 years ago
  62. b266d82 intel: agilex: Fix memory controller driver by Hadi Asyrafi · 6 years ago
  63. 4e865bd intel: agilex: Fix reliance on hard coded clock information by Hadi Asyrafi · 6 years ago
  64. 5119fa7 Merge changes from topic "intel-plat-refactor" into integration by Sandrine Bailleux · 6 years ago
  65. 3f7b149 intel: Platform common code refactor by Hadi Asyrafi · 6 years ago
  66. d882078 intel: Platform common code refactor by Hadi Asyrafi · 6 years ago
  67. 94eef29 intel: agilex: Fix BL31 memory mapping by Hadi Asyrafi · 6 years ago
  68. 3bd24e7 intel: agilex: Fix build error by Ambroise Vincent · 6 years ago
  69. 2f11d54 intel: Adds support for Agilex platform by Hadi Asyrafi · 6 years ago