- 9e51f15 chore: simplify the macro names in ENABLE_FEAT mechanism by Sona Mathew · 1 year, 5 months ago
- 8815cda feat(spmd): initialize SCR_EL3.EEL2 bit at RESET by Manish Pandey · 1 year, 6 months ago
- 970a4a8 fix(ras): restrict ENABLE_FEAT_RAS to have only two states by Manish Pandey · 1 year, 10 months ago
- 6597fcf feat(ras): use FEAT_IESB for error synchronization by Manish Pandey · 2 years, 1 month ago
- 461c0a5 refactor(cm): move EL3 registers to global context by Elizabeth Ho · 2 years, 1 month ago
- 5c52d7e refactor(cm): remove world differentiation for EL2 context restore by Boyan Karatotev · 2 years, 2 months ago
- f0c96a2 refactor(cm): clean up SCR_EL3 and CPTR_EL3 initialization by Boyan Karatotev · 2 years, 4 months ago
- ece8f7d refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only by Boyan Karatotev · 2 years, 6 months ago
- 83a4dae refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init by Boyan Karatotev · 2 years, 6 months ago
- c73686a feat(pmu): introduce pmuv3 lib/extensions folder by Boyan Karatotev · 2 years, 6 months ago
- 88727fc refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED by Andre Przywara · 2 years, 6 months ago
- 42d4d3b refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 2 years, 9 months ago
- dc2b8e8 Merge changes from topic "panic_cleanup" into integration by Bipin Ravi · 2 years, 5 months ago
- bd62ce9 refactor(aarch64): rename do_panic and el3_panic by Govindraj Raja · 2 years, 7 months ago
- d87c0e2 refactor(el3_runtime): introduce save_x30 macro by Manish Pandey · 2 years, 7 months ago
- 96a8ed1 feat(bl2): add support to separate no-loadable sections by Jiafei Pan · 3 years, 5 months ago
- 7d33ffe fix(el3-runtime): set unset pstate bits to default by Daniel Boulby · 4 years, 2 months ago
- dc78e62 feat(sme): enable SME functionality by johpow01 · 4 years, 1 month ago
- 596d20d fix(pie): invalidate data cache in the entire image range if PIE is enabled by Zelalem Aweke · 3 years, 10 months ago
- 6c09af9 feat(rme): run BL2 in root world when FEAT_RME is enabled by Zelalem Aweke · 4 years, 1 month ago
- 5de20ec feat(trf): initialize trap settings of trace filter control registers access by Manish V Badarkhe · 4 years, 1 month ago
- 2031d61 feat(sys_reg_trace): initialize trap settings of trace system registers access by Manish V Badarkhe · 4 years, 1 month ago
- 40ff907 feat(trbe): initialize trap settings of trace buffer control registers access by Manish V Badarkhe · 4 years, 1 month ago
- 0c5e7d1 feat(sve): enable SVE for the secure world by Max Shvetsov · 4 years, 5 months ago
- 12f6c06 fix(security): Set MDCR_EL3.MCCD bit by Alexei Fedorov · 4 years, 3 months ago
- 0063dd1 Add support for FEAT_MTPMU for Armv8.6 by Javier Almansa Sobrino · 4 years, 8 months ago
- d7b5f40 Increase type widths to satisfy width requirements by Jimmy Brisson · 5 years ago
- 3b8456b runtime_exceptions: Update AT speculative workaround by Manish V Badarkhe · 5 years ago
- 1a04b2e Fix compilation error when ENABLE_PIE=1 by Varun Wadekar · 5 years ago
- f8578e6 bl31: Split into two separate memory regions by Samuel Holland · 7 years ago
- da90359 PIE: make call to GDT relocation fixup generalized by Manish Pandey · 6 years ago
- 2a7adf2 Explicitly disable the SPME bit in MDCR_EL3 by Petre-Ionut Tudor · 6 years ago
- 0a12302 Add missing support for BL2_AT_EL3 in XIP memory by Lionel Debieve · 6 years ago
- b90f207 Invalidate dcache build option for bl2 entry at EL3 by Hadi Asyrafi · 6 years ago
- e290a8f AArch64: Disable Secure Cycle Counter by Alexei Fedorov · 6 years ago
- 5283962 Add ARMv8.3-PAuth registers to CPU context by Antonio Nino Diaz · 7 years ago
- ed4fc6f Disable processor Cycle Counting in Secure state by Antonio Nino Diaz · 6 years ago
- f5478de Reorganize architecture-dependent header files by Antonio Nino Diaz · 7 years ago[Renamed from include/common/aarch64/el3_common_macros.S]
- 3f99f7e Merge pull request #1731 from miyatsu/doc-fix-20181225 by Antonio Niño Díaz · 7 years ago