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review.trustedfirmware.org / sandbox / arthur / trustedfirmware-a / refs/heads/master / . / fdts / rd1ae.dts
blob: 26eaa65089979b7a580118d29b707ecb158d21ca [file] [log] [blame]
Divin Rajbb7c7e72024-04-04 14:00:36 +0100[diff] [blame]1/*
2 * Copyright (c) 2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12 model = "RD-1 AE";
13 compatible = "arm,rd1ae", "arm,neoverse";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 chosen {
19 stdout-path = &soc_serial0;
20 };
21
22 cpus {
23 #address-cells = <2>;
24 #size-cells = <0>;
25
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,neoverse-v3";
29 reg = <0x0 0x0>;
30 enable-method = "psci";
31 i-cache-size = <0x10000>;
32 i-cache-line-size = <0x40>;
33 i-cache-sets = <0x100>;
34 d-cache-size = <0x10000>;
35 d-cache-line-size = <0x40>;
36 d-cache-sets = <0x100>;
37 };
38 cpu1: cpu@10000 {
39 device_type = "cpu";
40 compatible = "arm,neoverse-v3";
41 reg = <0x0 0x10000>;
42 enable-method = "psci";
43 i-cache-size = <0x10000>;
44 i-cache-line-size = <0x40>;
45 i-cache-sets = <0x100>;
46 d-cache-size = <0x10000>;
47 d-cache-line-size = <0x40>;
48 d-cache-sets = <0x100>;
49 };
50 cpu2: cpu@20000 {
51 device_type = "cpu";
52 compatible = "arm,neoverse-v3";
53 reg = <0x0 0x20000>;
54 enable-method = "psci";
55 i-cache-size = <0x10000>;
56 i-cache-line-size = <0x40>;
57 i-cache-sets = <0x100>;
58 d-cache-size = <0x10000>;
59 d-cache-line-size = <0x40>;
60 d-cache-sets = <0x100>;
61 };
62 cpu3: cpu@30000 {
63 device_type = "cpu";
64 compatible = "arm,neoverse-v3";
65 reg = <0x0 0x30000>;
66 enable-method = "psci";
67 i-cache-size = <0x10000>;
68 i-cache-line-size = <0x40>;
69 i-cache-sets = <0x100>;
70 d-cache-size = <0x10000>;
71 d-cache-line-size = <0x40>;
72 d-cache-sets = <0x100>;
73 };
74 cpu4: cpu@40000 {
75 device_type = "cpu";
76 compatible = "arm,neoverse-v3";
77 reg = <0x0 0x40000>;
78 enable-method = "psci";
79 i-cache-size = <0x10000>;
80 i-cache-line-size = <0x40>;
81 i-cache-sets = <0x100>;
82 d-cache-size = <0x10000>;
83 d-cache-line-size = <0x40>;
84 d-cache-sets = <0x100>;
85 };
86 cpu5: cpu@50000 {
87 device_type = "cpu";
88 compatible = "arm,neoverse-v3";
89 reg = <0x0 0x50000>;
90 enable-method = "psci";
91 i-cache-size = <0x10000>;
92 i-cache-line-size = <0x40>;
93 i-cache-sets = <0x100>;
94 d-cache-size = <0x10000>;
95 d-cache-line-size = <0x40>;
96 d-cache-sets = <0x100>;
97 };
98 cpu6: cpu@60000 {
99 device_type = "cpu";
100 compatible = "arm,neoverse-v3";
101 reg = <0x0 0x60000>;
102 enable-method = "psci";
103 i-cache-size = <0x10000>;
104 i-cache-line-size = <0x40>;
105 i-cache-sets = <0x100>;
106 d-cache-size = <0x10000>;
107 d-cache-line-size = <0x40>;
108 d-cache-sets = <0x100>;
109 };
110 cpu7: cpu@70000 {
111 device_type = "cpu";
112 compatible = "arm,neoverse-v3";
113 reg = <0x0 0x70000>;
114 enable-method = "psci";
115 i-cache-size = <0x10000>;
116 i-cache-line-size = <0x40>;
117 i-cache-sets = <0x100>;
118 d-cache-size = <0x10000>;
119 d-cache-line-size = <0x40>;
120 d-cache-sets = <0x100>;
121 };
122 cpu8: cpu@80000 {
123 device_type = "cpu";
124 compatible = "arm,neoverse-v3";
125 reg = <0x0 0x80000>;
126 enable-method = "psci";
127 i-cache-size = <0x10000>;
128 i-cache-line-size = <0x40>;
129 i-cache-sets = <0x100>;
130 d-cache-size = <0x10000>;
131 d-cache-line-size = <0x40>;
132 d-cache-sets = <0x100>;
133 };
134 cpu9: cpu@90000 {
135 device_type = "cpu";
136 compatible = "arm,neoverse-v3";
137 reg = <0x0 0x90000>;
138 enable-method = "psci";
139 i-cache-size = <0x10000>;
140 i-cache-line-size = <0x40>;
141 i-cache-sets = <0x100>;
142 d-cache-size = <0x10000>;
143 d-cache-line-size = <0x40>;
144 d-cache-sets = <0x100>;
145 };
146 cpu10: cpu@a0000 {
147 device_type = "cpu";
148 compatible = "arm,neoverse-v3";
149 reg = <0x0 0xa0000>;
150 enable-method = "psci";
151 i-cache-size = <0x10000>;
152 i-cache-line-size = <0x40>;
153 i-cache-sets = <0x100>;
154 d-cache-size = <0x10000>;
155 d-cache-line-size = <0x40>;
156 d-cache-sets = <0x100>;
157 };
158 cpu11: cpu@b0000 {
159 device_type = "cpu";
160 compatible = "arm,neoverse-v3";
161 reg = <0x0 0xb0000>;
162 enable-method = "psci";
163 i-cache-size = <0x10000>;
164 i-cache-line-size = <0x40>;
165 i-cache-sets = <0x100>;
166 d-cache-size = <0x10000>;
167 d-cache-line-size = <0x40>;
168 d-cache-sets = <0x100>;
169 };
170 cpu12: cpu@c0000 {
171 device_type = "cpu";
172 compatible = "arm,neoverse-v3";
173 reg = <0x0 0xc0000>;
174 enable-method = "psci";
175 i-cache-size = <0x10000>;
176 i-cache-line-size = <0x40>;
177 i-cache-sets = <0x100>;
178 d-cache-size = <0x10000>;
179 d-cache-line-size = <0x40>;
180 d-cache-sets = <0x100>;
181 };
182 cpu13: cpu@d0000 {
183 device_type = "cpu";
184 compatible = "arm,neoverse-v3";
185 reg = <0x0 0xd0000>;
186 enable-method = "psci";
187 i-cache-size = <0x10000>;
188 i-cache-line-size = <0x40>;
189 i-cache-sets = <0x100>;
190 d-cache-size = <0x10000>;
191 d-cache-line-size = <0x40>;
192 d-cache-sets = <0x100>;
193 };
194 cpu14: cpu@e0000 {
195 device_type = "cpu";
196 compatible = "arm,neoverse-v3";
197 reg = <0x0 0xe0000>;
198 enable-method = "psci";
199 i-cache-size = <0x10000>;
200 i-cache-line-size = <0x40>;
201 i-cache-sets = <0x100>;
202 d-cache-size = <0x10000>;
203 d-cache-line-size = <0x40>;
204 d-cache-sets = <0x100>;
205 };
206 cpu15: cpu@f0000 {
207 device_type = "cpu";
208 compatible = "arm,neoverse-v3";
209 reg = <0x0 0xf0000>;
210 enable-method = "psci";
211 i-cache-size = <0x10000>;
212 i-cache-line-size = <0x40>;
213 i-cache-sets = <0x100>;
214 d-cache-size = <0x10000>;
215 d-cache-line-size = <0x40>;
216 d-cache-sets = <0x100>;
217 };
218 };
219
220 memory@80000000 {
221 device_type = "memory";
222 /*
223 * 0x7fc0 0000 - 0x7fff ffff : BL32
224 * 0x7fbf 0000 - 0x7fbf ffff : FFA_SHARED_MM_BUF
225 */
226 reg = <0x00000000 0x80000000 0 0x7fbf0000>,
227 <0x00000080 0x80000000 0 0x80000000>;
228 };
229
230 timer {
231 compatible = "arm,armv8-timer";
232 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
233 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
234 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
235 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
236 };
237
238 soc_clk24mhz: clk24mhz {
239 compatible = "fixed-clock";
240 #clock-cells = <0>;
241 clock-frequency = <24000000>;
242 clock-output-names = "refclk24mhz";
243 };
244
245 soc_refclk1mhz: refclk1mhz {
246 compatible = "fixed-clock";
247 #clock-cells = <0>;
248 clock-frequency = <1000000>;
249 clock-output-names = "refclk1mhz";
250 };
251
252 soc {
253 compatible = "simple-bus";
254 #address-cells = <2>;
255 #size-cells = <2>;
256 ranges;
257
Ziad Elhanafy6e1bf7e2024-07-15 14:07:06 +0100[diff] [blame]258 timer@2a810000 {
259 compatible = "arm,armv7-timer-mem";
260 reg = <0x0 0x2a810000 0 0x10000>;
261 #address-cells = <2>;
262 #size-cells = <2>;
263 clock-frequency = <250000000>;
264 ranges;
265
266 frame@2a830000 {
267 frame-number = <0>;
268 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
269 reg = <0x0 0x2a830000 0x0 0x10000>;
270 };
271 };
272
Divin Rajbb7c7e72024-04-04 14:00:36 +0100[diff] [blame]273 gic: interrupt-controller@30000000 {
274 compatible = "arm,gic-v3";
275 reg = <0x0 0x30000000 0 0x10000>, // GICD
David Huf72eeb22024-11-18 18:08:52 +0000[diff] [blame]276 <0x0 0x301c0000 0 0x400000>; // GICR
Divin Rajbb7c7e72024-04-04 14:00:36 +0100[diff] [blame]277 #interrupt-cells = <3>;
278 #address-cells = <2>;
279 #size-cells = <2>;
280 ranges;
281 interrupt-controller;
282 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
283
284 its1: msi-controller@30040000 {
285 compatible = "arm,gic-v3-its";
286 reg = <0x0 0x30040000 0x0 0x40000>;
287 msi-controller;
288 #msi-cells = <1>;
289 };
290 its2: msi-controller@30080000 {
291 compatible = "arm,gic-v3-its";
292 reg = <0x0 0x30080000 0x0 0x40000>;
293 msi-controller;
294 #msi-cells = <1>;
295 };
296 its3: msi-controller@300c0000 {
297 compatible = "arm,gic-v3-its";
298 reg = <0x0 0x300c0000 0x0 0x40000>;
299 msi-controller;
300 #msi-cells = <1>;
301 };
302 its4: msi-controller@30100000 {
303 compatible = "arm,gic-v3-its";
304 reg = <0x0 0x30100000 0x0 0x40000>;
305 msi-controller;
306 #msi-cells = <1>;
307 };
308 its5: msi-controller@30140000 {
309 compatible = "arm,gic-v3-its";
310 reg = <0x0 0x30140000 0x0 0x40000>;
311 msi-controller;
312 #msi-cells = <1>;
313 };
314 its6: msi-controller@30180000 {
315 compatible = "arm,gic-v3-its";
316 reg = <0x0 0x30180000 0x0 0x40000>;
317 msi-controller;
318 #msi-cells = <1>;
319 };
320 };
321
322 soc_serial0: serial@2a400000 {
323 compatible = "arm,pl011", "arm,primecell";
324 reg = <0x0 0x2a400000 0x0 0x10000>;
325 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
327 clock-names = "uartclk", "apb_pclk";
328 };
329
330 watchdog@2a440000 {
331 compatible = "arm,sbsa-gwdt";
332 reg = <0x0 0x2a440000 0 0x1000>,
333 <0x0 0x2a450000 0 0x1000>;
334 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
335 };
336
337 rtc@c170000 {
338 compatible = "arm,pl031", "arm,primecell";
339 reg = <0x0 0x0c170000 0x0 0x10000>;
340 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&soc_clk24mhz>;
342 clock-names = "apb_pclk";
343 };
344
345 virtio-net@c150000 {
346 compatible = "virtio,mmio";
347 reg = <0x0 0xc150000 0x0 0x200>;
348 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
349 };
350
351 virtio-block@c130000 {
352 compatible = "virtio,mmio";
353 reg = <0x0 0xc130000 0x0 0x200>;
354 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
355 };
356
357 virtio-rng@c140000 {
358 compatible = "virtio,mmio";
359 reg = <0x0 0xc140000 0x0 0x200>;
360 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
361 };
362
363 pci@4000000000 {
364 #address-cells = <0x03>;
365 #size-cells = <0x02>;
366 compatible = "pci-host-ecam-generic";
367 device_type = "pci";
368 bus-range = <0x00 0x11>;
369 reg = <0x40 0x00 0x00 0x04000000>;
370 ranges = <0x43000000 0x40 0x40000000 0x40 0x40000000 0x10 0x00000000
371 0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x08000000
372 0x01000000 0x00 0x00 0x00 0x77800000 0x00 0x800000>;
373 msi-map = <0x00 &its1 0x40000 0x10000>;
374 iommu-map = <0x00 &smmu 0x40000 0x10000>;
375 dma-coherent;
376 };
377
378 smmu: iommu@280000000 {
379 compatible = "arm,smmu-v3";
380 reg = <0x2 0x80000000 0x0 0x100000>;
381 dma-coherent;
382 #iommu-cells = <1>;
383 interrupts = <1 210 1>,
384 <1 211 1>,
385 <1 212 1>,
386 <1 213 1>;
387 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
388 msi-parent = <&its1 0x10000>;
389 };
390
391 sysreg: sysreg@c010000 {
392 compatible = "arm,vexpress-sysreg";
393 reg = <0x0 0xc010000 0x0 0x1000>;
394 gpio-controller;
395 #gpio-cells = <2>;
396 };
397
398 fixed_3v3: v2m-3v3@c011000 {
399 compatible = "regulator-fixed";
400 reg = <0x0 0xc011000 0x0 0x1000>;
401 regulator-name = "3V3";
402 regulator-min-microvolt = <3300000>;
403 regulator-max-microvolt = <3300000>;
404 regulator-always-on;
405 };
406
407 mmci@c050000 {
408 compatible = "arm,pl180", "arm,primecell";
409 reg = <0x0 0xc050000 0x0 0x1000>;
410 interrupts = <0 0x8B 0x4>,
411 <0 0x8C 0x4>;
412 cd-gpios = <&sysreg 0 0>;
413 wp-gpios = <&sysreg 1 0>;
414 bus-width = <8>;
415 max-frequency = <12000000>;
416 vmmc-supply = <&fixed_3v3>;
417 clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
418 clock-names = "mclk", "apb_pclk";
419 };
420
421 };
422
423 psci {
424 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
425 method = "smc";
426 cpu_suspend = <0xc4000001>;
427 cpu_off = <0x84000002>;
David Huf72eeb22024-11-18 18:08:52 +0000[diff] [blame]428 cpu_on = <0xc4000003>;
Divin Rajbb7c7e72024-04-04 14:00:36 +0100[diff] [blame]429 };
430
431};