blob: 350cd3459b46f0ebfaa62466fe6b97915b337456 [file] [log] [blame]
Yann Gautier20544d62024-11-22 15:01:10 +01001// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2/*
3 * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
4 */
5
6#include "stm32mp157c-dk2.dts"
7
8/ {
9 model = "STMicroelectronics STM32MP157C-DK2 Discovery Board (SP_MIN)";
10};
11
12&rcc {
13 st,clksrc = <
14 CLK_MPU_PLL1P
15 CLK_AXI_PLL2P
16 CLK_MCU_PLL3P
17 CLK_RTC_LSE
18 CLK_MCO1_DISABLED
19 CLK_MCO2_DISABLED
20 CLK_CKPER_HSE
21 CLK_FMC_ACLK
22 CLK_QSPI_ACLK
23 CLK_ETH_PLL4P
24 CLK_SDMMC12_PLL4P
25 CLK_DSI_DSIPLL
26 CLK_STGEN_HSE
27 CLK_USBPHY_HSE
28 CLK_SPI2S1_PLL3Q
29 CLK_SPI2S23_PLL3Q
30 CLK_SPI45_HSI
31 CLK_SPI6_HSI
32 CLK_I2C46_HSI
33 CLK_SDMMC3_PLL4P
34 CLK_USBO_USBPHY
35 CLK_ADC_CKPER
36 CLK_CEC_LSE
37 CLK_I2C12_HSI
38 CLK_I2C35_HSI
39 CLK_UART1_HSI
40 CLK_UART24_HSI
41 CLK_UART35_HSI
42 CLK_UART6_HSI
43 CLK_UART78_HSI
44 CLK_SPDIF_PLL4P
45 CLK_FDCAN_PLL4R
46 CLK_SAI1_PLL3Q
47 CLK_SAI2_PLL3Q
48 CLK_SAI3_PLL3Q
49 CLK_SAI4_PLL3Q
50 CLK_RNG1_CSI
51 CLK_RNG2_LSI
52 CLK_LPTIM1_PCLK1
53 CLK_LPTIM23_PCLK3
54 CLK_LPTIM45_LSE
55 >;
56
57 st,clkdiv = <
58 DIV(DIV_MPU, 1)
59 DIV(DIV_AXI, 0)
60 DIV(DIV_MCU, 0)
61 DIV(DIV_APB1, 1)
62 DIV(DIV_APB2, 1)
63 DIV(DIV_APB3, 1)
64 DIV(DIV_APB4, 1)
65 DIV(DIV_APB5, 2)
66 DIV(DIV_MCO1, 0)
67 DIV(DIV_MCO2, 0)
68 >;
69};